Apparatus, method, and system for monolithic formation of array word lines and pad word lines in memory circuits

Abstract

The present invention provides an apparatus, method, and system for monolithic formation of array word lines and pad word lines within a memory circuit. [Solution] The present invention provides a system for monolithic word lines in a memory circuit, wherein the structure for connecting the word lines includes a conductive element and a first dielectric. The conductive element connects the array word line in the array region at the first edge to the padded word line in the pad region at the second edge. The conductive element is located within the interconnection region between the first and second edges. The first dielectric is located on the array word line, the conductive element, and the padded word line. The first dielectric has a dielectric surface that extends from the interconnection region to the pad region. The conductive element and the second dielectric form a monolithic word line from the array word line and the padded word line through the second edge.

Description

Technical Field

[0001] The present invention relates to a memory device, and more particularly, to an apparatus, method, and system for monolithic formation of array word lines and pad word lines in a memory circuit.

Background Art

[0002] This section of the background art is merely intended to provide context, and the disclosure of any aspect within this section does not constitute an admission that the aspect being referred to is prior art.

[0003] Three-dimensional (3D) memory configurations are becoming increasingly popular. 3D memory devices such as VSDRAM (vertically stacked dynamic random-access memory) and V-NAND (Vertical-NAND) flash memory increase storage density by including vertically stacked memory cells. One characteristic of a 3D memory circuit is the arrangement of bit lines and word lines. As memory density increases, the arrangement of bit lines and word lines can cause issues such as shorts, which mean a defective electrical connection between two points.

[0004] However, conventional techniques for preventing short circuits and other device failures face several challenges, particularly with high-density and high-aspect-ratio memory circuits. Techniques such as wordline stitching, precise device profile fabrication, optimized patterning and lithography, precise deposition of insulating materials, and device profile analysis are costly, difficult to implement, and still carry the risk of short circuits and defects.

[0005] The information disclosed in this background section is solely for the purpose of improving understanding of the background art of the present invention and therefore may include information that does not constitute prior art. [Overview of the project] [Problems that the invention aims to solve]

[0006] The present invention has been made in view of the above-mentioned conventional problems, and the object of the present invention is to provide an apparatus, method, and system for monolithic formation of array word lines and pad word lines in a memory circuit. [Means for solving the problem]

[0007] To overcome these issues, systems and methods for forming array word lines and pad word lines integrated within a three-dimensional memory device are described herein. In one embodiment, the three-dimensional memory device includes a structure for connecting word lines from the word line pad area (WL pad area) to the array area. The structure includes a conductive element and a first dielectric. The conductive element connects the array word lines (array WL) in the word line array area at a first edge to the pad word lines in the word line pad area at a second edge. The conductive element is located within an interconnection area between the first and second edges. The first dielectric is located on the array word lines, the conductive element, and the pad word lines. The first dielectric has a dielectric surface that extends from the interconnection area to the word line pad area. The conductive element and the first dielectric form a monolithic word line from the array word lines and the pad word lines through the second edge.

[0008] In one embodiment, the structure further includes a second dielectric disposed on the interconnection region and a third dielectric disposed on the first dielectric within the wordline pad region. In one embodiment, the predetermined thickness is the same as the gate oxide thickness. In one embodiment, the second dielectric is different from the second dielectric, the third dielectric, or both the second and third dielectrics. [Effects of the Invention]

[0009] According to the present invention, an apparatus, method, and system for monolithic formation of array word lines and pad word lines in a memory circuit can be provided. The fabrication process for monolithic formation of word lines in a three-dimensional memory circuit involves simultaneously forming word lines in the array region and word lines in the pad region, resulting in conductive elements between the array word lines and pad word lines having a flat surface, thus avoiding short circuits or damage within the word line region. [Brief explanation of the drawing]

[0010] [Figure 1] This block diagram shows a system utilizing a 3D memory circuit according to one embodiment. [Figure 2] This figure shows a 3D memory device utilizing a monolithic word line structure according to one embodiment. [Figure 3] This figure shows three cross-sections of the capping process flow for the fabrication of the monolithic WL according to one embodiment. [Figure 4] This figure shows the first part of the capping process flow for fabricating a monolithic word line in a three-dimensional perspective view according to one embodiment. [Figure 5] This figure shows the second part of the capping process flow for fabricating a monolithic word line in a three-dimensional perspective view according to one embodiment. [Figure 6] This figure shows the first part of the capping process flow for fabricating a monolithic word line in an array view according to one embodiment. [Figure 7] This figure shows the second part of the capping process flow for fabricating a monolithic word line in an array view according to one embodiment. [Figure 8]This figure shows the first part of the capping process flow for fabricating a monolithic word line in an array view according to one embodiment. [Figure 9] This figure shows the second part of the capping process flow for fabricating a monolithic word line in an array view according to one embodiment. [Figure 10] This figure shows the process flow for forming an interconnecting area according to one embodiment. [Figure 11] This figure shows three cross-sections of the masking process flow for the production of a monolithic word line according to one embodiment. [Figure 12] This figure shows the first part of the masking process flow for fabricating a monolithic word line in an array cross-section according to one embodiment. [Figure 13] This figure shows the second part of the masking process flow for fabricating a monolithic word line in an array cross-section according to one embodiment. [Figure 14] This figure shows the first part of the masking process flow for fabricating a monolithic word line in a pad cross-section according to one embodiment. [Figure 15] This figure shows the second part of the masking process flow for fabricating a monolithic word line in a pad cross-section according to one embodiment. [Figure 16] This figure shows the first part of the masking process flow for creating a monolithic word line in an interconnecting view according to one embodiment. [Figure 17] This figure shows the second part of the masking process flow for creating a monolithic word line in an interconnected view according to one embodiment. [Figure 18] This is a flowchart showing the process for manufacturing a monolithic word line structure for a memory circuit according to one embodiment. [Figure 19]A flowchart showing a process for preparing one or more monolithic word line pathways using capping according to one embodiment. [Figure 20] A flowchart showing a process for preparing one or more monolithic word line pathways using masking according to one embodiment. **DETAILED DESCRIPTION OF THE INVENTION**

[0011] In the sections that follow, aspects of the subject matter disclosed in this specification will be described with reference to embodiments as examples shown in the drawings.

[0012] In the detailed description that follows, numerous specific details are set forth to provide a thorough understanding of the present invention. However, it should be understood by those of ordinary skill in the art that the disclosed aspects may be practiced without these specific details. In other instances, well-known methods, procedures, components, and circuits have not been described in detail so as not to obscure the subject matter disclosed herein.

[0013] Throughout this specification, references to “one embodiment” (or “an embodiment”) mean that any feature, structure, or characteristic described in relation to an embodiment may be included in at least one embodiment disclosed herein. Therefore, the phrases “in one embodiment” (or “in an embodiment”) or “according to one embodiment” (or other similar phrases with “import”) in various places throughout this specification do not necessarily refer to the same embodiment. Furthermore, specific features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In this regard, as used herein, “as an example” means “provided as an example, instance, or illustration.” Any embodiment described herein as “example” should not be construed as necessarily preferred or having advantages over other embodiments. Also, depending on the context of the description herein, a singular form may include a corresponding plural form, and a plural form may include a corresponding singular form. Similarly, hyphenated terms (e.g., two-dimensional, pre-determined, pixel-specific) may be interchangeable with their corresponding non-hyphenated versions (e.g., two-dimensional, pre-determined, pixel-specific), and uppercase terms (e.g., Counter Clock, Row Select, PIXOUT) may be interchangeable with their non-uppercase versions (e.g., counter clock, row select, pixout). Such interchangeability should not be considered inconsistent between them.

[0014] Please understand that the various figures illustrated and described herein (including component diagrams) are for illustrative purposes only and may not be drawn to scale. For example, the dimensions of some elements may be exaggerated relative to others for clarity. Furthermore, where appropriate, reference numerals may be repeated across drawings to correspond to and / or refer to similar elements. The drawings below illustrating various components, structures, interconnections, configurations, and steps of fabrication are primarily for illustrative purposes. They are not intended to accurately depict these elements. Cross-sectional representations may be used to refer to 3D blocks within a 3D structure. In some cases, relevant parts within a drawing may be clearly illustrated, while other parts are less clearly or distinctly illustrated to avoid confusion and improve contrast and clarity. These parts may be referenced in the above drawing and therefore do not need to be explained again. These parts may also have little to do with the parts(s) being explained. In addition, the shading of parts within a drawing may not have a consistent design and may be modified to maintain clarity and contrast within the drawing. For example, part A may have a light shading in Figure X but a dark shading in Figure Y. Moreover, as mentioned earlier, the components of a drawing may not be illustrated to an appropriate scale.

[0015] The terminology described herein is for the purpose of describing one embodiment only and is not intended to limit the claimed subject matter. As described herein, singular nouns (a, an, the) are intended to include plural nouns as well, unless the context clearly indicates otherwise. When used herein, "comprise and / or comprising" should be understood to identify the presence of the mentioned feature, integers, steps, operations, elements, and / or components, but not to exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0016] When an element or layer is referred to as "on" or "connected to" another element or layer, it may be directly on, directly connected to, or intervening to the other element or layer. Conversely, when an element or layer is referred to as "directly on" or "directly connected to" another element or layer, there may be no intervening elements or layers. As used herein, "and / or" may include any and all one or more associated listed items.

[0017] Terms such as "first," "second," etc., as used herein, are used as labels preceding nouns and, unless explicitly defined, do not imply any type of order (e.g., spatial, temporal, logical, etc.). The same reference number may be used across two or more drawings to refer to parts, components, blocks, circuits, units, or modules having the same or similar function. However, such descriptions are for the sake of simplicity of illustration or ease of discussion only and do not imply that the construction or architectural details of such components or units are identical across all embodiments, or that such commonly-referenced parts / modules are the only way to realize some of the exemplary embodiments disclosed herein.

[0018] As used herein, “monolithic” refers to “formed of a single element.” A single or one-body element may contain uniformly distributed material. “Monolithic formation” is the simultaneous formation of elements that produce a monolithic, single, or one-body element. This is in contrast to formations that stitch together, join, or link together two or more separate elements to aggregate them. Stitching together two or more separate elements can produce an uneven surface at the stitching site, which may skew, crooked, or warped, leading to tier-to-tier shorts, breaks, and other defects.

[0019] As used herein, “pathway” refers to a patterned channel or trench prepared to be filled with a material according to a specified function. If it is filled with metal, it becomes a conducting line used as a word line or bit line in a memory circuit, or any other conducting line that transmits signals in a circuit. “Pathway” is sometimes used to mean channel, hollow space, trench, pattern, patterned line, or line.

[0020] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as generally understood by a person skilled in the art in which the present invention pertains. Terms as defined in commonly used dictionaries should further be understood to have a meaning consistent with their meaning in the context of the relevant art, and should not be interpreted in an ideal or overly formal sense unless expressly defined herein.

[0021] Many applications, particularly in artificial intelligence (AI) and signal processing, require large storage capacity and high-throughput computations. To meet these needs, high-density memory circuits in three dimensions have been developed. A typical three-dimensional DRAM (dynamic random access memory) device stacks multiple layers of memory cells vertically. Bitlines (BLs) and wordlines (WLs) are vertically aligned to access cells in different layers. Bitlines and wordlines are conductive elements used to select memory cells arranged in a row-and-column array. A wordline pad (WL pad) is a structure that allows wordlines to be connected to other parts of the memory circuit and to external circuits. Wordlines are therefore run from the pad area to the array area. When a word line is formed so that it extends from a pad area to an array area within a single process stage, the resulting word line (resulting WL) is referred to as a monolithic word line (monolithic WL).

[0022] The following describes a system and method for providing monolithic formation of word lines from array word lines and pad word lines. In one embodiment, a three-dimensional memory device includes a structure for connecting word lines from a word line pad area (WL pad area) to an array area. The word line pad area (WL pad area) has one or more word lines, referred to as pad word lines (pad WLs) for convenience of reference. Similarly, the word line array area (WL array area) has one or more word lines, referred to as array word lines (array WLs) for convenience of reference. Typically, array word lines are shorter than pad word lines. The structure includes a conductive element and a first dielectric. The conductive element connects the array word lines in the word line array area at the first edge to the pad word lines in the word line pad area at the second edge. The conductive element is located within an interconnecting area between the first edge and the second edge. The first dielectric is arranged on the array word line, conductive element, and pad word line. The first dielectric has a dielectric surface that extends from the interconnection region to the word line pad region. The conductive element and the first dielectric form a monolithic word line from the array word line and pad word line through a second edge. The structure further includes a second dielectric arranged on the first dielectric in the interconnection region and a third dielectric arranged on the first dielectric in the word line pad region. In one embodiment, the predetermined thickness is the same as the gate oxide thickness. In one embodiment, all three dielectrics are different. The first edge is the boundary between the array region and the interconnection region. The second edge is the boundary between the interconnection region and the pad region and is referred to as the unit block edge.A unit block edge is the edge of a well-defined block of semiconductor, and a well-defined block of semiconductor is used as a unit for measuring several physical properties or qualities such as flatness, purity, and geometrical regularity. The conductive element is a metal. In one embodiment, the metal is one of tungsten (W), titanium nitride (TiN), molybdenum (Mo), aluminum (Al), copper (Cu), cobalt (Co), ruthenium (Ru), iridium (Ir), platinum (Pt), tantalum (Ta), or rhodium (Rh). The metal may also be a combination of two or more of the materials mentioned above.

[0023] The fabrication process for monolithic word line formation in three-dimensional memory circuits results in a flat surface between the conductive elements of the array word line and the pad word line, thus avoiding short circuits or breaks within the word line region. This is achieved by simultaneously forming the word line in the array region and the word line in the pad region, as in one or more monolithic word lines. This is in contrast to techniques that separate the array word line and the pad word line, or form one after the other and then stitch them together. Stitching word lines from two separate areas (regions) can lead to tier-to-tier short circuits or line breaks. These techniques of forming the two types of lines separately can result in uneven or skewed surfaces at the boundary between the connecting region and the pad region.

[0024] The technology is efficient in the manufacturing process. This is particularly advantageous for memory circuits stacked vertically with high aspect ratios. An inherently flat surface is achieved by metal deposition occurring simultaneously across the entire word line, including the array and pad areas.

[0025] Figure 1 is a block diagram illustrating a system utilizing a three-dimensional memory circuit according to one embodiment. System 100 includes a digital baseband circuit 105, an RF (radio frequency) transceiver circuit 150, and an analog baseband circuit 170. System 100 represents either a digital system or a mobile system. When system 100 is used as a digital system without a mobile circuit, the RF transceiver circuit 150 and the analog baseband circuit 170 are not used. Furthermore, when system 100 is used as a mobile device, many digital devices are reduced in size, and some devices are not used.

[0026] The digital baseband circuit 105 includes a CPU (central processing unit) 110, a memory controller 120, and an I / O controller 130. System 100 may include more or fewer components than those described above. Furthermore, components can be integrated as other components. For example, the memory controller 120 and the I / O controller 130 can be integrated into a single controller.

[0027] The CPU 110 is a programmable device that executes a collection of instructions or programs to carry out tasks. The CPU 110 is a host that controls or manages other processors or devices. In particular, the CPU 110 includes application programmable interfaces (APIs), applications, or drivers that are executed by the CPU to perform specific tasks. The CPU 110 is a general-purpose processor, a digital signal processor (DSP), a microcontroller, or a specially designed processor. The CPU 110 includes single-core or multi-core configurations. Each core has multi-way multi-threading. The CPU 110 has a simultaneous multi-threading feature, further exploiting parallelism through multiple threads across multiple cores. Furthermore, the CPU 110 has an internal cache at multiple levels. The CPU 110 communicates with other devices in the system via bus 115. Bus 115 is any suitable bus that connects the CPU 110 to other devices. For example, bus 115 is a direct media interface (DMI). Bus 115 also includes custom buses, such as a bus for interface to an analog section when the system 100 is used as a mobile device.

[0028] The memory controller 120 controls memory devices such as main memory 122, cache memory 124, and flash memory 126. Main memory 122 includes RAM, including static random access memory (SRAM) and dynamic RAM (DRAM), and / or read-only memory (ROM) or other types of memory. DRAM includes synchronous DRAM (SDRAM) and modulo DDR SDRAM (Double Data Rate SDRAM) (e.g., DDR2, DDR3, DDR4, DDR5, and DDR6). Main memory 122 stores instruction words or programs loaded from a mass storage device, which, when executed by the CPU 110, trigger the CPU 110 to perform operations for a specific task. Main memory 122 also stores data used in operations. ROM is a solid-state drive (SSD) and includes instruction words, programs, constants, or data that are maintained regardless of the presence or absence of power. The instruction words or programs correspond to the functions described below. In one embodiment, the main memory 122 includes a 3-D memory device or circuit 128 such as VSDRAM and V-NAND flash memory or any other memory device having memory cells that are stacked vertically to increase storage density.

[0029] The IO controller 130 controls the input device 132, the output device 134, and the mass storage 136. The input device 132 includes a keyboard, mouse, image sensor or camera, game console, and microphone. Other input devices such as a stylus, joystick, scanner, and light pen can also be used. The output device 134 includes a printer, monitor, or screen, headset, and multi-monitor set. When used as a computing device without mobile characteristics, the monitor is a high-resolution display. For games and other multi-display modes, a multi-monitor set provides high resolution with multiple monitors (e.g., three monitors). When used for mobile communication, the screen provides a basic interface for the user to explore and access various applications and perform tasks. The screen uses an OLED (organic light emitting diode) (super retina) display with multiple touch or haptic sensors. The high-capacity storage 136 includes CD-ROMs, hard disks, and SSDs (solid-state drives). The I / O controller 130 also has a network interface card (NIC) 145 that provides interfaces to the network and wireless medium 148.

[0030] Additional devices or bus interfaces are used for interconnections and / or expansion. In one embodiment, the bus interface includes a PCIe (Peripheral Component Interconnect Express) bus, a USB (Universal Serial Bus), and the like.

[0031] The RF transceiver circuit 150 includes a transmitter 152, an antenna array 158, a voltage-controlled oscillator (VCO) 156, and a receiver 154. The RF transceiver circuit 150 operates in a high GHz frequency band and accommodates the latest cellular equipment such as 5G wireless.

[0032] Transmitter 152 transmits digital baseband data to antenna array 158. Transmitter 152 includes a DAC (digital-to-analog), AGC (automatic gain controller), IF (intermediate frequency) circuit, mixer, RF circuit, and PA (power amplifier). Other components include filters, amplifiers, multiplexers, coaxial cable, and phase shifters. The DAC converts digital data f1 to analog data f2. The AGC automatically adjusts the signal amplitude of f2 to generate signal f3, maintaining a consistent intensity level in a dynamic and changing environment. The IF circuit performs an intermediate frequency process, such as filtering, to generate signal f4. The mixer converts the frequency of signal f4 to other frequencies. This is done by mixing signal f4 with signal Vt from VCO 156. Here, mixing refers to frequency conversion, which transforms signal f4 into signal f5 at another frequency. For the transmitter, the converted frequency is higher than the frequency of f4. This transformation is called upconversion. For 5G communication, the frequency range includes a low-band (below 1 GHz), an intermediate-band (1 GHz to 6 GHz), and a high-band (24 GHz to 53 GHz or higher). The resulting signal f5 passes through various radio frequency processes performed by RF circuits such as high-band filtering to generate signal f6. Signal f6 is enhanced and amplified by a PA to generate signal f7. Signal f7 is then supplied to antenna array 158 and transmitted to a suitable destination and medium (e.g., base station). Antenna array 158 uses beamforming to concentrate the radio waves of f7 in the desired direction. Antenna array 158 is used for both transmission and reception. In reception, antenna array 158 receives the RF signal and sends it to receiver 154.The number of antennas in antenna array 158 depends on the desired coverage. Antenna array 158 includes antennas (161, 162, 163, 164) configured to operate with 5G communication, Gigabit LTE (Gigabit Long Term Evolution) (e.g., 2.4GHz, 5GHz, and 6GHz), Wi-Fi, and Bluetooth®, respectively. The number of antennas may be greater or less than this.

[0033] The VCO156 provides low phase noise oscillation by coupling multiple in-phase oscillators together. The VCO156 sends a signal to the mixer at a specific frequency (v t , v r The VCO156 provides a high-frequency periodic signal, comprising multiple oscillator core circuits (or VCO cores).

[0034] Receiver 154 processes the received signal r7 in the opposite manner to transmitter 152. Receiver 154 includes an LNA (low noise amplifier), RF circuitry, mixer, IF circuitry, AGC, and ADC (analog-to-digital converter). Receiver 154 may contain more or fewer of the above components. The LNA amplifies the weak signal r7 while maintaining a good SNR (signal-to-noise ratio), generating signal r6 for subsequent processing. Signal r6 is then processed by the RF circuitry, such as through band-pass filtering, to provide signal r5. Signal r5 is then passed to signal v from VCO 156. rThe mixer in the transmitter 152 performs frequency conversion, downconverting signal r5 to a suitable lower frequency signal r4. Similar to the mixer in the transmitter 152, but in reverse operation, the mixer in the receiver 154 performs frequency conversion, converting the high-frequency signal r5 to the low-frequency signal r4. Signal r4 is then subjected to IF processing, such as additional filtering, by the IF circuit to generate signal r3. The AGC amplifies and enhances the signal to generate signal r2. The ADC converts the analog signal r2 into a digital signal r1, which is processed by the CPU 110.

[0035] The analog baseband circuit 170 provides analog processing for various components. The analog baseband circuit 170 handles the processing of signals and data between the digital baseband circuit and the RF transceiver circuit 150. The analog baseband circuit 170 performs a variety of tasks, including modulation / demodulation, RF transceiver circuit 150, and special circuit control for 3G, 4G / LTE, Bluetooth®, and 5G communications. The analog baseband circuit 170 also includes an audio device circuit 174, a sensor circuit 176, a SIM card (subscriber identity module card) 178, and other components. The audio device circuit 174 includes an additional block for processing audio signals, performing audio-related functions such as filtering, correlation, and speech recognition. The audio device circuit 174 includes a digital circuit that performs a fast Fourier transform (FFT) and performs signal processing in the frequency domain. The sensor circuit 176 includes a variety of sensors such as proximity, ambient light, and motion sensors (accelerometer and gyroscope, compass, barometer, fingerprint sensor for touch ID, image sensor for facial ID, LiDAR (light detection and ranging) scanner, etc.). The SIM card 178 is a small, removable chip that stores the user's phone number and carrier information and allows the device to connect to a cellular network.

[0036] The power supply and battery circuit 180 provides power and battery backup supply to the entire system. The power supply and battery circuit 180 includes a charger for charging the battery. The battery is a rechargeable battery (e.g., a lithium-ion battery). Power management is performed by application software and circuitry, providing low-power mode and performance management.

[0037] System 100 is an example illustrating the role of a 3D memory device in a laptop, desktop, or mobile environment. Often, application environments can impose additional requirements, including low power consumption, reliable signal integrity, fault tolerance, and stable operation, in extreme conditions such as heat and confined spaces. Other applications that can benefit from 3D memory devices or circuits include mobile communications (e.g., smartphones, base stations, user devices), cameras, vehicles, entertainment (e.g., games, multimedia, music, movies), technical designs (e.g., animation, graphics), medical (e.g., visualization, medical imaging), robotics, drones, automotive test equipment, audio processing, speech synthesizers, video and image analysis, vision, automated face recognition, AI (artificial intelligence) applications, and data centers.

[0038] Figure 2 shows a three-dimensional memory device 128 utilizing a monolithic wordline structure according to one embodiment. The three-dimensional memory device 128 includes structures 201 and other circuit elements (not shown). Structure 201 includes regions (or areas) (210, 220, 225).

[0039] Region 210 is a region having an array of memory cells constructed by capacitors for storage elements and transistors for switching control to select, enable, or disable storage elements during memory access operations. This array of memory cells includes one or more bitlines BL and wordlines WL that provide conductive paths to the storage elements for memory addressing. For convenience of reference, region 210 is referred to as the array region, and wordlines within the array region are referred to as array wordlines.

[0040] Region 220 is a region having pads for connecting word lines to other circuits, such as a row decoder. This is referred to as the word line pad area (WL pad area) or pad area. The word line pad area 220 contains one or more word lines that extend into the array area 210 to form one or more monolithic word lines. For convenience of reference, this region 220 is referred to as the word line pad area or simply the pad area, and word lines within the pad area are referred to as pad word lines. In one embodiment, an array word line is shorter than a pad word line. Word lines in memory circuits are single line and monolithic. The designations array word line and pad word line do not refer to two different word lines. Rather, these terms refer to the same word line in two different regions. The portion of a word line within the array area 210 is referred to as the array word line, and the portion of a word line within the word line pad area 220 is referred to as the pad word line. Similarly, when a word line runs through an interconnecting area that connects the array area and the pad area, the portion of the word line within the interconnecting area is referred to as the interconnecting word line (WL). The designations "array word line," "interconnecting word line," and "pad word line" are primarily for convenience of reference. For each word line, these three designations refer to the same single and monolithic word line that runs from within the pad area 220 through the interconnecting area 250 into the array area 230.

[0041] Region 225 is a region in which one or more array word lines and one or more pad word lines are joined or linked to form one or more monolithic word lines. A cross section of region 225 is shown in the figure, illustrating the arrangement of various elements. This cross section, in which the array region and pad region appear to be located on the same plane, shows the internal structure of the three-dimensional structure 210. Region 225 is segmented or divided into three segments or areas, namely the array region 230, the pad region 240, and the interconnected region 250. The array region 230 and the interconnected region 250 are separated by a boundary or first edge 235. The pad region 240 and the interconnected region 250 are separated by a boundary or second edge 245. The second edge 245 is also referred to as the unit block boundary as described above. Region 225 includes a structure 222 that corresponds to a word line in the memory circuit.

[0042] Structure 222 includes an array word line 232 in an array region 230, a pad word line 270 in a pad region 240, and a conductive element 260 in an interconnecting region 250. The conductive element 260 is an interconnecting word line. As mentioned above, although they are referred to by three different names, the array word line, interconnecting word line, and pad word line are single monolithic word lines (WLs) formed simultaneously by the same material. The array word line 232, interconnecting word line, and pad word line 270 are made of or contain a metal. In one embodiment, the metal is at least one of tungsten (W), titanium nitride (TiN), molybdenum (Mo), aluminum (Al), copper (Cu), cobalt (Co), ruthenium (Ru), iridium (Ir), platinum (Pt), tantalum (Ta), or rhodium (Rh). The metal is also a combination of the elements mentioned above. The conductive element 260 or interconnecting word line connects the array word line 232 in the array region 230 at the first edge 235 to the pad word line 270 in the pad region 240 at the second edge 245. The conductive element 260 or interconnecting word line is located within the interconnecting region 250 between the first edge 235 and the second edge 245.

[0043] Structure 222 further comprises a first dielectric 281, a second dielectric 282, and a third dielectric 283. The arrangement of these dielectrics is represented by an arrangement 267 in an interconnection region and an arrangement 269 in a pad region. In one embodiment, at least one of the first dielectric 281, the second dielectric 282, and the third dielectric 283 includes silicon dioxide (SiO2), silicon nitride (SiN), tantalum pentoxide (Ta2O5), titanium dioxide (TiO2), or other high-k dielectrics. In one embodiment, each includes a different dielectric. In another embodiment, at least the first dielectric 281 includes a dielectric different from both the second dielectric 282 and the third dielectric 283.

[0044] The first dielectric 281 is positioned on the array word line 232, the conductive element 260, and the pad word line 270. The first dielectric 281 has a dielectric surface 285 that extends from the interconnection region 250 to the word line pad region 240. As described above, the conductive element 260 and the first dielectric 281 form a monolithic word line. In one embodiment, the dielectric surface 285 is a plane with less than a predetermined thickness of unevenness in at least the region 265 surrounding the second edge 245. Evenness is defined by the difference between the minimum and maximum thickness of the surface. In one embodiment, the predetermined thickness is equal to one of the gate oxide thicknesses between sub-nanometers and 2 nm, or between 2 nm and 3 nm.

[0045] The second dielectric 282 is positioned on the first dielectric 281 within the interconnection region 250 and extends from the first edge 235 to the second edge 245 as shown in the array 267. In one embodiment, the second dielectric 282 extends from the conductive element 260 to the adjacent conductive element within the interconnection region 250.

[0046] The third dielectric 283 is positioned on the first dielectric 281 within a pad region 240 and extends from one pad word line 270 to an adjacent pad word line (adjacent pad WL) within the pad region 240, as shown in the array 269. In one embodiment, the third dielectric 283 extends from an array region 230 between two adjacent first dielectrics to a near second edge 245 inside the second dielectric 282.

[0047] The dielectric surface 285 is achieved by the simultaneous deposition of metal within the array word lines 232, pad word lines 270, and interconnecting word lines. The metal is allowed to fill the conductive pathways provided for the word lines within the recessed channel, and the metal thus acquires a vertically flat surface at the periphery of the channel. This is formed by the fabrication process.

[0048] There are two embodiments for the manufacturing process. One is called the capping process, and the other is called the masking process. The two processes differ in how they mask the sides of the array and the sides of the pads.

[0049] Figure 3 shows three views of the capping process flow 300 for the fabrication of a monolithic word line according to one embodiment. The process 300 has three views, namely a 3D view 310, an array view 330, and a pad view 350. The process 300 includes seven stages. Each stage is shown in one of the three views described above. To maintain clarity and efficiency when showing the drawings, each view is divided into two parts. The first part includes stages 1 to 4, and the second part includes stages 5 to 7.

[0050] Stage 1 involves partially forming array word lines (WLs) on the 3D structure. Stage 2 involves depositing a capping mask onto the top surface of the 3D structure. Stage 3 involves etching and opening the word line pad areas. Stage 4 involves stripping the silicon paths. Stage 5 involves removing the capping mask. Stage 6 involves removing the liner oxide. Stage 7 involves depositing metal into the word line paths.

[0051] The three-dimensional perspective view 310 includes a first part 311 and a second part 312. The first part 311 includes structures (321, 322, 323, 324) corresponding to the first to fourth stages, respectively. The second part 312 includes structures (325, 326, 327) corresponding to the fifth to seventh stages, respectively. Elements within the array section 330 and the pad section 350 are not visible in the three-dimensional perspective view 310.

[0052] The array section 330 includes a first part 331 and a second part 332. The first part 331 includes structures (341, 342, 343, 344) corresponding to the first to fourth stages, respectively. The second part 332 includes structures (345, 346, 347) corresponding to the fifth to seventh stages, respectively. Elements in the three-dimensional perspective view 310 and the pad section 350 are not visible in the array section 330.

[0053] The pad section 350 includes a first section 351 and a second section 352. The first section 351 includes structures (361, 362, 363, 364) corresponding to the first to fourth stages, respectively. The second section 352 includes structures (365, 366, 367) corresponding to the fifth to seventh stages, respectively. Elements in the three-dimensional perspective view 310 and the array section 330 are not visible in the pad section 350.

[0054] Figure 4 shows the first part 311 of the capping process flow for fabricating a monolithic word line in a three-dimensional perspective view according to one embodiment. The first part 311 includes structures (321, 322, 323, 324) corresponding to the first to fourth stages shown in Figure 3.

[0055] The first stage forms structure 321 by partially generating patterns of word line pathways (WL pathways) (410, 420). The patterns and pathways form region 220 as shown in Figure 2. Pathway 410 represents an array word line pathway, and path 420 represents a pad word line pathway. Cut-outs show the internal structure of the pattern. The structure includes dielectrics (432, 434) and semiconductors (e.g., silicon (Si), polysilicon, silicon germanium (SiGe)) 436. These patterns are further etched and deposited in subsequent stages.

[0056] The second stage forms structure 322 by depositing cap 430 onto the upper surface of structure 321 in the first stage. Cap 430 is a suitable material that allows selective etching together with a hard mask. In one embodiment, cap 430 comprises amorphous carbon (abbreviated as aC or aC). The objective is to mask the array sides while leaving other trenches used against the pad sides open. Cap 430 protects the underneath portion from contamination. Cap 430 is deposited by any suitable deposition technique such as PVD (physical vapor deposition), ALD (atomic layer deposition), CVD (chemical vapor deposition), or SOG (Spin-on glass).

[0057] The third stage involves etching and opening the wordline pad region 440 to form structure 323. The cap 430 acts as a hard mask for the pad-side opening. This is accomplished by planarizing the cap 430 using a planarization process such as CMP. The cap 430 is reduced in height to become a planarized cap 435.

[0058] The fourth stage involves stripping semiconductors (e.g., silicon, polysilicon, silicon germanium) along paths 452 within the pad region to form structure 324.

[0059] Figure 5 shows a second part 312 of the capping process flow for fabricating a monolithic word line in a three-dimensional perspective view according to one embodiment. The second part 312 includes structures (325, 326, 327) corresponding to the fifth to seventh stages shown in Figure 3.

[0060] The fifth stage involves removing the cap mask 430 to form structure 325. In one embodiment, the removal is carried out using oxygen plasma. This is done by generating an oxygen plasma containing reactive species such as oxygen radicals. The oxygen radicals react with a capping material (e.g., aC) to produce volatile byproducts (e.g., carbon monoxide (CO), carbon dioxide (CO2)) which are removed using a vacuum pump.

[0061] The sixth stage involves removing the linear dielectric (e.g., oxide) to form structure 326. This creates hollow spaces in the silicon pathways within the array and pad regions. These hollow spaces correspond to word lines extending from the array region (array word lines) to the pad region (pad word lines). The cleaning process cleans the dielectric to connect the array hollow spaces to the pad hollow spaces. The enlarged section 510 shows the internal structure of the array hollow spaces 520 and the pad hollow spaces 530. The enlarged section 510 has slightly different shading in some parts to improve clarity. These hollow spaces should allow for metallization to occur simultaneously in both the array and pad regions, resulting in uniform and flat surfaces at the boundaries between the array, interconnected, and pad regions, as shown in Figure 2.

[0062] The seventh stage involves depositing an oxide material (e.g., silicon, polysilicon, silicon germanium) in the array region while repairing seams or voids in the pad region with dielectric material, followed by metallization to form structure 327. Metallization is performed by depositing a metal (e.g., TiN, W, Mo) in the array hollow space and the pad hollow space, forming a uniform monolithic word line extending from the pad region to the array region. Since the metal is deposited simultaneously through the hollow spaces that are cleaned and prepared in the array region and the pad region, the word line results in a flat and even surface throughout. This eliminates short circuits or defects on the word line. The array region 230, interconnection region 250, and pad region 240 are as shown in Figure 2. Similarly, the resulting word line is the word line (232, 260, and 270) shown in Figure 2. The first and second edges (235, 245) are as shown in Figure 2.

[0063] Figure 6 shows the first part 331 of the capping process flow for fabricating a monolithic word line in an array cross section according to one embodiment. The first part 331 includes structures (341, 342, 343, 344) corresponding to the first to fourth stages, respectively.

[0064] Structures (341, 342, 343, 344) correspond to the first to fourth stages, respectively, as shown in Figure 3. These are two-dimensional cross-sections viewed within the array region. The elements within structures (341, 342, 343, 344) are the same elements within each of structures (341, 342, 343, 344) shown in Figure 4, except that they are two-dimensional cross-sections within the array region. Thus, their descriptions are not repeated except for some observations. Cap 430 in Figure 4 is cap 630 as seen in the array cross-section. Flattened cap 435 in Figure 4 is cap 635 as seen in the array cross-section.

[0065] Figure 7 shows a second part 332 of the capping process flow for fabricating a monolithic word line in an array cross section according to one embodiment. The second part 332 includes structures (345, 346, 347) corresponding to the fifth to seventh stages shown in Figure 3.

[0066] Structures (345, 346, 347) correspond to stages 5 through 7, respectively, as shown in Figure 3. These are two-dimensional cross-sections viewed in array sections. Each element within structures (345, 346, 347) is the same element within structures (325, 326, 327) shown in Figure 5, except that they are viewed as two-dimensional cross-sections within the array region. Therefore, their descriptions are not repeated here, except for a few observations. The hollow space 520 in Figure 5 is the hollow space 720 within structure 346. The array word line 232 is shown within structure 347. Since these drawings are viewed as array regions, elements within the pad regions are not visible.

[0067] Figure 8 shows the first part 351 of the capping process flow for fabricating a monolithic word line in a pad cross section according to one embodiment. The first part 351 includes structures (361, 362, 363, 364) corresponding to the first to fourth stages shown in Figure 3.

[0068] Each of the structures (361, 362, 363, 364) corresponds to the first to fourth stages, as shown in Figure 3. These are two-dimensional cross-sections viewed from the pad area. Each of the elements within structures (361, 362, 363, 364) is the same element within structures (321, 322, 323, 324) as shown in Figure 4, except that they are viewed as two-dimensional cross-sections within the pad area. Therefore, their descriptions will not be repeated here, except for a few observations. Cap 430 in Figure 4 is cap 830 as seen in the pad cross-section. Flattened cap 435 in Figure 4 is cap 835 as seen in the pad cross-section.

[0069] Figure 9 shows a second part 352 of the capping process flow for fabricating a monolithic word line in a pad cross section according to one embodiment. The second part 352 includes structures (365, 366, 367) corresponding to the fifth to seventh stages shown in Figure 3.

[0070] Each of the structures (365, 366, 367) corresponds to the 5th to 7th stages, as shown in Figure 3. They are two-dimensional cross-sections viewed from the pad area. Each of the elements within structures (365, 366, 367) is the same element within structures (325, 326, 327) as shown in Figure 5, except that they are viewed as two-dimensional cross-sections within the pad area. Therefore, their descriptions will not be repeated here, except for a few observations. The pad hollow space 530 in Figure 5 is the hollow space 930 within structure 366. The pad word line 270 is shown within structure 367. Since these drawings are viewed as pad areas, elements within the array area are not visible.

[0071] Figure 10 shows a process flow 1000 forming an interconnecting region according to one embodiment. Process flow 1000 shows the formation of an interconnecting element that connects the array word line and the pad word line in a single metallization occurring simultaneously within both the array region and the pad region to form a uniform monolithic word line. Process flow 1000 corresponds to process flow 300 in Figure 2, but is concentrated in the interconnecting region. Process flow 1000 includes structures (1010, 1020, 1030, 1040, 1050, 1060). Each structure is the result of a process stage operating on the above structure. For structure 1010, the above structure is a three-dimensional substrate. The sequence of process stages is the same as the sequence in Figure 3.

[0072] The first stage forms a structure 1010 having dielectrics (1012, 1014) and a semiconductor channel 1016. An edge 1015 is formed across the dielectrics (1012, 1014) and the semiconductor channel 1016. The third stage forms a structure 1020 with a silicon nitride (SiN) recess as indicated by arrow 1023. The recess is terminated at edge 1025. The fourth stage forms a structure 1030 by performing a silicon strip (Si strip) as indicated by arrow 1035. The sixth stage forms a structure 1040 by oxide cleaning as indicated by arrow 1045. The seventh stage forms a structure 1050 by depositing gate oxide (Gox) in layers (1052, 1054, and 1055). In one embodiment, the oxide is of the low-temperature chemical bath deposition (CBD) type for ease of cleaning. The gate oxide layer (Gox layer) 1052 in the array region surrounding the silicon pathway is thicker than layer 1054 in the pad region, providing a better reaction with silicon. The second part of the seventh stage involves depositing a metal (e.g., TiN) to form structure 1060. Structure 1060 shows the array region 230, the interconnection region 250, and the pad region 240. The first edge 235 corresponds to edge 1025 in structure 1020. The second edge 245 corresponds to edge 1015 in structure 1010. Dielectrics (281, 282, 283) are formed from dielectrics (1012, 1014). Parts of structures (1050, 1060) are shown in the enlarged section 1065. The enlarged section 1065 shows that the thickness d1 of layer 1052 is larger than the thickness d2 of layer 1054.

[0073] A second embodiment of the process for forming a monolithic word line is referred to as the masking process. This process is similar to the capping process in Figure 3, specifically in the last two stages, namely stages 6 and 7.

[0074] Figure 11 shows three cross-sections of a masking process flow 1100 for the fabrication of a monolithic word line according to one embodiment. Process 1100 has three cross-sections, namely the array cross-section 1110, the pad cross-section 1130, and the interconnection cross-section 1150. Process 1100 includes six stages. Each stage is shown in one of the three cross-sections described above. To maintain clarity and efficiency in showing the drawings, each cross-section is divided into two parts. The first part includes stages 1 to 3, and the second part includes stages 4 to 6.

[0075] The first stage involves etching the array and pad regions using oxide high aspect ratio (HAR). The second stage involves forming channel silicon nitride liner recesses. The third stage involves stripping the semiconductor (e.g., silicon). The fourth stage involves cleaning the liner oxide. The fifth stage involves depositing the gate oxide. The sixth stage involves depositing metal into the word line paths (WL paths).

[0076] The array section 1110 includes a first section 1111 and a second section 1112. The first section 1111 includes structures (1121, 1122, 1123) corresponding to the first to third stages, respectively. The second section 1112 includes structures (1124, 1125, 1126) corresponding to the fourth to sixth stages, respectively. Elements within the pad section 1130 and the interconnecting section 1150 are not visible within the array section 1110.

[0077] The pad section 1130 includes a first section 1131 and a second section 1132. The first section 1131 includes structures (1141, 1142, 1143) corresponding to the first to third stages, respectively. The second section 1132 includes structures (1144, 1145, 1146) corresponding to the fourth to sixth stages, respectively. Elements within the array section 1110 and the interconnected section 1150 are not visible within the pad section 1130.

[0078] The interconnected section 1150 includes a first section 1151 and a second section 1152. The first section 1151 includes structures (1161, 1162, 1163) corresponding to the first to third stages, respectively. The second section 1152 includes structures (1164, 1165, 1166) corresponding to the fourth to sixth stages, respectively. Elements within the array section 1110 and the pad section 1130 are not visible within the interconnected section 1150.

[0079] Figure 12 shows the first part 1111 of the masking process flow 1110 shown in Figure 11 for the fabrication of a monolithic word line in an array cross-section according to one embodiment. The first part 1111 includes structures (1121, 1122, 1123) corresponding to the first to third stages shown in Figure 11.

[0080] The first stage involves creating a hard mask 1210 on the upper surface of the three-dimensional structure to form structure 1121. The pattern includes patterns for a semiconductor (e.g., silicon 1220) and a dielectric (1232, 1234). The second stage involves opening the hard mask 1210 to become a mask 1240 and forming structure 1122. A silicon oxide nitride liner recess 1250 is formed. The third stage involves stripping the semiconductor (e.g., silicon) to form structure 1123.

[0081] Figure 13 shows a second part 1112 of the masking process flow 1110 shown in Figure 11 for the fabrication of a monolithic word line in an array cross-section according to one embodiment. The second part 1112 includes structures (1124, 1125, 1126) corresponding to the fourth to sixth stages shown in Figure 11.

[0082] The fourth stage involves cleaning the liner oxide and creating cleaned semiconductor and dielectric channels 1310 to form structure 1124. The fifth stage involves depositing gate oxide 1320 in the semiconductor and dielectric channels to form structure 1125. This stage is similar to the first part of the seventh stage in the capping process shown in Figure 3. The sixth stage involves depositing metal (e.g., Ti, W) into the hollow spaces within the array and pad regions to form word lines 1330 and form structure 1126. The enlarged cross-section 1340 shows word lines 1330. This stage is similar to the second part of the seventh stage in the capping process shown in Figure 3.

[0083] Figure 14 shows the first part 1131 of the masking process flow 1130 shown in Figure 11 for the fabrication of a monolithic word line in a pad cross section according to one embodiment. The first part 1131 includes structures (1141, 1142, 1143) corresponding to the first to third stages in Figure 11, respectively.

[0084] The first stage forms structure 1141 together with mask 1140. The virtual lines (or reference lines) (1, 2) are the same as the reference lines of structure 1121 in Figure 12. The second stage forms structure 1142. Mask 1410 in structure 1141 becomes mask 1420. The third stage forms structure 1143.

[0085] Figure 15 shows the second part 1132 of the masking process flow 1130 shown in Figure 11 for the fabrication of a monolithic word line in a pad cross section according to one embodiment. The second part 1132 includes structures (1144, 1145, 1146) corresponding to the fourth to sixth stages shown in Figure 11.

[0086] The fourth stage involves cleaning the liner oxide to form the cleaned semiconductor and dielectric channels 1510 and structure 1144. The fifth stage involves depositing the gate oxide 1520 in the semiconductor and dielectric channels to form structure 1145. The enlarged cross-section 1540 shows the gate oxide 1520. This stage is similar to the first part of the seventh stage in the capping process shown in Figure 3. The sixth stage involves depositing a metal (e.g., Ti, W) in the hollow space in the array and pad regions to form the word line 1530 and structure 1146. This stage is similar to the second part of the seventh stage in the capping process shown in Figure 3.

[0087] Figure 16 shows the first part 1151 of the masking process flow 1150 shown in Figure 11 for the fabrication of a monolithic word line in an interconnected cross section according to one embodiment. The first part 1151 includes structures (1161, 1162, 1163) corresponding to the first to third stages shown in Figure 11.

[0088] The first stage forms a structure 1161 having virtual lines (1, 2) shown in structure 1121 in Figure 12 and structure 1141 in Figure 14. Structure 1161 has a semiconductor 1610 and a dielectric (1612, 1614). The second stage forms a structure 1162 having a liner recess 1620. The third stage forms a structure 1163.

[0089] Figure 17 shows the second part 1152 of the masking process flow 1150 shown in Figure 11 for the fabrication of a monolithic word line in an interconnected cross section according to one embodiment. The second part 1152 includes structures (1164, 1165, 1166) corresponding to the fourth to sixth stages shown in Figure 11.

[0090] The fourth stage forms a structure 1164 having cleaned liner oxide 1710. The fifth stage forms a structure 1165 by depositing gate oxide 1720 onto semiconductor and dielectric channels. This stage is similar to the first part of the seventh stage in the capping process shown in Figure 3. The sixth stage forms a conductive pathway 1730 and a structure 1166 by depositing metal (e.g., Ti, W) into the hollow spaces within the array and pad regions. This stage is similar to the second part of the seventh stage in the capping process shown in Figure 3. The conductive pathway 1730 includes array word lines 232, interconnecting word lines, and pad word lines 270 as shown in Figure 2. Structure 1166 also includes first edges 235 and second edges 245 as shown in Figure 2.

[0091] Figure 18 is a flowchart of process 1800 for fabricating a monolithic word line for a memory circuit according to one embodiment. Process 1800 corresponds to the capping and masking embodiments shown in Figures 3 and 11. For simplicity, not all correspondences between the structures in Figures 3 and 11 and the process in Figure 18 are described.

[0092] Process 1800 forms array word line regions for one or more array word line paths and pad word line regions having one or more pad word line paths within a three-dimensional structure (Process 1810). Next, Process 1800 prepares one or more monolithic word lines including one or more array word line paths, one or more pad word line paths, and one or more interconnected word line paths (Process 1820). Process 1820 implements the capping process described in Figure 19 and the masking process described in Figure 20.

[0093] Next, process 1800 deposits gate oxide into one or more padded word line paths, one or more interconnected word line paths, and one or more arrayed word line paths (process 1830). Then, process 1800 deposits metal into one or more padded word line paths, one or more interconnected word line paths, and one or more arrayed word line paths to simultaneously form one or more monolithic word lines from one or more monolithic word line paths (process 1840). The metal is at least one of tungsten (W), titanium nitride (TiN), molybdenum (Mo), aluminum (Al), copper (Cu), cobalt (Co), ruthenium (Ru), iridium (Ir), platinum (Pt), tantalum (Ta), rhodium (Rh), or any combination of these materials. Process 1800 then performs a variety of cleaning-up operations and then terminates. Process 1840 yields structures 327 in Figure 5, 347 in Figure 7, and 367 in Figure 9 (for the capping embodiment), and structures 1126 in Figure 13, 1146 in Figure 15, and 1166 in Figure 17 (for the masking embodiment).

[0094] Figure 19 is a flowchart of process 1820 for preparing one or more monolithic wordline paths shown in Figure 18 using capping according to one embodiment. Process 1820 represents the first to seventh stages shown in Figure 3, shown for three cross-sections: a three-dimensional perspective view 310, an array cross-section 330, and a pad cross-section 350.

[0095] Process 1820 generates dielectric recesses in the array word line region and the pad word line region (Process 1910). Process 1910 produces structure 321 in Figure 4, structure 341 in Figure 6, and structure 361 in Figure 8. Next, Process 1820 forms caps on the top surface of the three-dimensional structures (Process 1920). Process 1920 produces structure 322 in Figure 4, structure 342 in Figure 6, and structure 362 in Figure 8. Next, Process 1820 etches the pad word line region (Process 1930). Next, Process 1820 strips the silicon in the pad word line region into one or more interconnected word line paths in the interconnected region between the array word line region and the pad word line region (Process 1940). Next, Process 1820 removes the caps (Process 1950). This is done by ashing the caps using oxygen plasma. When amorphous carbon is used to form the cap, ashing the cap involves removing the amorphous carbon using an energized gas or plasma and a low-temperature process. Process 1950 produces structure 325 in Figure 5, structure 345 in Figure 7, and structure 365 in Figure 9. Next, process 1820 cleans the oxides in the array word line region (process 1960), and then terminates.

[0096] Figure 20 is a flowchart of process 1820 for preparing one or more monolithic word lines shown in Figure 18 using masking according to one embodiment. Process 1820 shows parts of the first to sixth stages shown in Figure 11 for three cross-sections, namely the array cross-section 1110, the pad cross-section 1130, and the interconnection cross-section 1150.

[0097] Process 1820 forms a mask on the three-dimensional structure (Process 2010). Process 2010 produces structure 1121 in Figure 12, structure 1141 in Figure 14, and structure 1161 in Figure 16. Next, Process 1820 releases the mask over the array word line region on the array side and the pad word line region on the pad side (Process 2020). Next, Process 1820 etches one or more array word line paths and one or more pad word line paths (Process 2030). Next, Process 1820 etches one or more array word line paths and one or more pad word line paths with different thicknesses by adjusting the mask thickness on the pad side. Next, Process 1820 recesses the dielectric in the array region and the semiconductor in the pad region, cleans the dielectric in the interconnection region, and connects one or more array word line paths and one or more pad word line paths (Process 2050). Process 1820 then terminates.

[0098] The detailed description of the present invention includes detailed descriptions of many specific embodiments, but these detailed descriptions of embodiments should not be interpreted as limitations on any of the claims, but rather as descriptions of features specific to those embodiments. Certain features described in the detailed description of the present invention from the context of a separate embodiment may be realized in a combination of a single embodiment. Conversely, diverse features described from the context of a single embodiment may also be realized in multiple embodiments or sub-combinations of any suitable parts. Furthermore, features are described to operate in a particular combination, and indeed, to be initially claimed, but in some cases one or more features may be excluded from the claimed combination, and the claimed combination may refer to a sub-combination or a variation of a sub-combination.

[0099] Similarly, while actions are shown in a specific order in the drawings, this should not be interpreted as requiring such actions to be performed in that specific order, or that all illustrated actions must be performed to achieve the intended result. In certain situations, multitasking and parallel processing may be advantageous. Furthermore, the separation of various system components in the embodiments described above should not be interpreted as requiring such separation in all embodiments, and the described program components and systems can generally be integrated together in a single software product or packaged in multiple software products.

[0100] Specific embodiments of the subject matter have been described herein. Other embodiments may be within the scope of the claims. In some cases, the operations described in the claims may be performed in a different order and still achieve the intended results. In addition, the processes shown in the drawings do not necessarily require a specific illustrated order or sequential order to achieve the intended results. In certain embodiments, multitasking and parallel processing may be advantageous.

[0101] As will be recognized by those skilled in the art, the innovative concepts described herein can be modified and varied across a wide range of applications. Therefore, the claims should not be limited to any of the above-mentioned specific examples, but rather defined by the claims themselves. [Explanation of Symbols]

[0102] 100 Systems 105 Digital Baseband Circuit 110 CPU 115 Bus 120 memory controllers 122 Main Memory 124 cache memory 126 Flash Memory 128 Three-dimensional (3D) memory device or circuit 130 IO controller 132 Input device 134 Output device 136 Large Capacity Storage 146 Network Interface Card (NIC) 148 Wireless Medium 150 RF Transceiver Circuit 152 Transmitter 154 Receiver 156 VCO 158 Antenna Array 161, 162, 163, 164 antennas 170 Analog Baseband Circuit 172 Baseband Unit 174 Audio Equipment Circuit 176 Sensor Circuit 178 SIM cards 180 Power supply and battery circuits Structure 201, 1010, 1020, 1030, 1040, 1050, 1060 210 Array Region (3D Structure) 220 (wordline) pad area Structure corresponding to 222 word lines 225 areas 230 array area 232 Array Word Lines 235, 1015 First Edge 245, 1025 Second Edge 240 pad area 250 interconnected areas 260 Conductive elements (interconnected word lines) 265 Region surrounding the second edge 267 Array within the interconnected region 269 ​​Arrangement within the pad area 270 Pad Wordline 281, 282, 283 First to Third Dielectrics 285 Dielectric surface 300, 1000 Capping Process Flow (Process) 310 Three-dimensional perspective view 311, 331, 351, 1111, 1131, 1151 Part 1 312, 332, 352, 1112, 1132, 1152 2nd part Structure corresponding to the first stage: 321, 341, 361, 1121, 1141, 1161 Structure corresponding to the second stage: 322, 342, 362, 1122, 1142, 1162 323, 343, 363, 1123, 1143, 1163 Structure corresponding to the third stage 324, 344, 364, 1124, 1144, 1164 Structure corresponding to the 4th stage Structure corresponding to the 5th stage: 325, 345, 365, 1125, 1145, 1165 Structure corresponding to the 6th stage: 326, 346, 366, 1126, 1146, 1166 Structure corresponding to the 7th stage (327, 347, 367) 330 Array (Cross Section) 350 pads (cross-section) 410 Array Word Line Path 420 Pad Word Line Route 430, 435, 630, 830, 835 caps 432, 434, 1012, 1014, 1232, 1234, 1612, 1614 dielectric 436, 1610 Semiconductors 440 Wordline Pad Area Path within the 452 pad area 510, 1065, 1340, 1540 Enlarged cross-sections 520, 720 array hollow space 530, 930 pad hollow space 635 Flattened cap 1016 Semiconductor Channel 1052 Gate Oxide Layer 1054 Layers within the pad area 1100 Masking Process Flow 1110 Array Cross Section 1130 Pad cross-section 1150 Interconnected cross section 1210 Hard Mask 1220 Silicone 1240 masks 1310, 1510 Dielectric Channel 1320, 1520, 1720 gate oxides 1330, 1530 Wordline 1420 masks 1620 Liner recess 1710 Liner Oxide 1730 Conductive Path

Claims

1. A device for forming a monolith within a memory circuit, A conductive element is provided which array word lines in the array region of the first edge and pad word lines in the pad region of the second edge are connected and which is arranged within the interconnected region between the first edge and the second edge. The array word lines, the conductive elements, and the first dielectric having a dielectric surface arranged on the pad word lines and extending from the interconnection region to the pad region, The apparatus is characterized in that the conductive element and the first dielectric form a monolithic word line through the second edge.

2. The apparatus according to claim 1, further comprising a second dielectric disposed on the first dielectric within the interconnected region.

3. The apparatus according to claim 2, further comprising a third dielectric disposed on the first dielectric within the pad region.

4. The apparatus according to claim 1, characterized in that the dielectric surface is flat and has a thickness equal to or less than the thickness of the gate oxide.

5. The apparatus according to claim 3, characterized in that the first dielectric is different from at least one of the second dielectric and the third dielectric.

6. The apparatus according to claim 1, characterized in that the second edge is a unit block edge.

7. The apparatus according to claim 1, characterized in that the conductive element includes a metal.

8. The apparatus according to claim 7, characterized in that the metal includes at least one of tungsten (W), titanium nitride (TiN), molybdenum (Mo), aluminum (Al), copper (Cu), cobalt (Co), ruthenium (Ru), iridium (Ir), platinum (Pt), tantalum (Ta), or rhodium (Rh).

9. The apparatus according to claim 1, characterized in that the array word line is shorter than the pad word line.

10. The apparatus according to claim 1, characterized in that the array word line and the pad word line are word lines of a three-dimensional memory circuit.

11. A method for forming a monolith within a memory circuit, The steps include forming an array word line region for an array word line path and a padded word line region having a padded word line path within a three-dimensional structure, The steps include preparing a monolithic word line path (monolithic WL pathway) including the array word line path, the pad word line path, and the interconnected word line path, The steps include depositing gate oxide within the pad word line path, the interconnected word line path, and the array word line path, A method characterized by comprising the step of depositing metal from the monolithic word line path into the pad word line path, the interconnected word line path, and the array word line path.

12. The step of preparing the monolithic word line path is: A step of generating dielectric recesses in the array word line region and the pad word line region, The steps include forming a cap on the upper surface of the three-dimensional structure, The step of etching the aforementioned pad word line region, The method according to 11, comprising the step of stripping silicon in the padded word line into the interconnected word line path within the interconnected word line region between the array word line region and the padded word line region.

13. The step of preparing the monolithic word line path is: The step of removing the aforementioned cap, The method according to 12, further comprising the step of cleaning oxides in the array word line region.

14. The step of preparing the monolithic word line path is: The steps include forming a mask on the upper surface of the three-dimensional structure, The steps include: releasing the mask over the array word line region on the side of the array and the pad word line region on the side of the pad; The steps include etching the array word line path and the pad word line path, The steps include: recessing the dielectric in the array word line region and recessing the semiconductor in the pad word line region; The method according to 12, characterized by comprising the steps of cleaning the dielectric in the interconnection region and connecting the array word line path and the pad word line path.

15. The method according to 14, characterized in that the step of etching the array word line path and the pad word line path includes the step of etching the array word line path and the pad word line path having different depths by adjusting the mask thickness on the side of the pad.

16. The method according to 12, characterized in that the step of forming the cap includes the step of forming the cap using amorphous carbon.

17. The method according to 13, characterized in that the step of removing the cap includes a step of ashing the cap using oxygen plasma.

18. The method according to 11, characterized in that the step of depositing the metal includes depositing a metal which is at least one of tungsten (W), titanium nitride (TiN), molybdenum (Mo), aluminum (Al), copper (Cu), cobalt (Co), ruthenium (Ru), iridium (Ir), platinum (Pt), tantalum (Ta), or rhodium (Rh).

19. The method according to 11, characterized in that the step of depositing the metal includes the step of depositing the metal within the pad word line path, the interconnected word line path, and the array word line path.

20. A system for forming a monolith within a memory circuit, The aforementioned memory circuit is An array region having an array word line, A padded area having a padded word line, It has an interconnected structure, The aforementioned interconnection structure is A conductive element is provided which the array word line at the first edge and the pad word line at the second edge are connected and which is positioned within the interconnected region between the first edge and the second edge. The array word line, the conductive element, and the first dielectric having a dielectric surface arranged on the pad word line and extending from the interconnection region to the pad region, The conductive element and the first dielectric are characterized in that they form a monolithic word line from the array word line and the pad word line through the second edge.

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