Display device and method for manufacturing a display device

Abstract

The present invention provides a display device and a method for manufacturing the display device that can improve yield. [Solution] A display device according to one embodiment comprises: a substrate having a display area for displaying an image and a peripheral area outside the display area; a first lower electrode disposed above the substrate in the display area; a rib layer made of an inorganic material having a first surface located on the opposite side of the substrate and a pixel aperture overlapping the first lower electrode; a partition wall including a conductive first lower part disposed on the first surface and a first upper part disposed above the first lower part and protruding from the side surface of the first lower part; an organic layer in contact with the first lower electrode through the pixel aperture; an upper electrode covering the organic layer and in contact with the first lower part; a cap layer covering the upper electrode; and a first sealing layer made of an inorganic material covering the cap layer and having a second surface located on the opposite side of the substrate and having a surface roughness greater than the first surface.

Description

Technical Field

[0001] Embodiments of the present invention relate to a display device and a method for manufacturing the display device.

Background Art

[0002] In recent years, display devices applying organic light-emitting diodes (OLEDs) as display elements have been put into practical use. In this type of display device, technologies for improving the yield are required.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Patent Document 5

Patent Document 6

Patent Document 7

Summary of the Invention

Problems to be Solved by the Invention

[0004] One object of the present invention is to provide a display device and a method for manufacturing the display device capable of improving the yield.

Means for Solving the Problems

[0005] A display device according to one embodiment includes a substrate having a display area for displaying an image and a peripheral area outside the display area; a first lower electrode disposed above the substrate in the display area; a rib layer made of an inorganic material having a first surface located on the opposite side of the substrate and a pixel aperture overlapping the first lower electrode; a partition wall including a conductive first lower part disposed on the first surface and a first upper part disposed above the first lower part and protruding from the side surface of the first lower part; an organic layer in contact with the first lower electrode through the pixel aperture; an upper electrode covering the organic layer and in contact with the first lower part; a cap layer covering the upper electrode; and a first sealing layer made of an inorganic material covering the cap layer and having a second surface located on the opposite side of the substrate and having a surface roughness greater than the first surface.

[0006] A method for manufacturing a display device according to one embodiment involves forming a lower electrode in a display area for displaying an image, forming a rib layer made of an inorganic material having a pixel aperture that overlaps with the lower electrode, forming a partition wall including a conductive first lower part disposed on the rib layer and a first upper part disposed on the first lower part and protruding from the side surface of the first lower part, forming an organic layer in contact with the lower electrode through the pixel aperture, forming an upper electrode covering the organic layer and in contact with the first lower part, forming a cap layer covering the upper electrode, and forming a first sealing layer covering the cap layer over the display area and the peripheral area outside the display area, and applying a surface treatment to the upper surface of the first sealing layer and roughening the upper surface. [Brief explanation of the drawing]

[0007] [Figure 1] Figure 1 shows an example of the configuration of a display device according to this embodiment. [Figure 2] Figure 2 is a schematic plan view showing an example of a sub-pixel layout. [Figure 3] Figure 3 is a schematic cross-sectional view of the display device along the line III-III in Figure 2. [Figure 4] Figure 4 is a schematic cross-sectional view, enlarged from the area enclosed by frame IV in Figure 3. [Figure 5] Figure 5 is a schematic plan view showing some elements of a display device. [Figure 6] FIG. 6 is a schematic cross-sectional view showing the structure around the slit. [Figure 7] FIG. 7 is a schematic plan view showing some elements of the display device. [Figure 8] FIG. 8 is a schematic plan view obtained by enlarging the region surrounded by the frame VIII in FIG. 7. [Figure 9] FIG. 9 is a schematic cross-sectional view of the display device along the line IX-IX in FIG. 8. [Figure 10] FIG. 10 is a schematic cross-sectional view of the display device in the peripheral region. [Figure 11] FIG. 11 is a schematic plan view of the mother substrate according to the present embodiment. [Figure 12] FIG. 12 is a schematic plan view of the panel portion. [Figure 13A] FIG. 13A is a schematic cross-sectional view showing the manufacturing process of the display device. [Figure 13B] FIG. 13B is a schematic cross-sectional view showing the process following FIG. 13A. [Figure 13C] FIG. 13C is a schematic cross-sectional view showing the process following FIG. 13B. [Figure 13D] FIG. 13D is a schematic cross-sectional view showing the process following FIG. 13C. [Figure 13E] FIG. 13E is a schematic cross-sectional view showing the process following FIG. 13D. <图13E是表示图13D后续工序的示意性剖视图。 [Figure 13F] [Figure 13G] FIG. 13F is a schematic cross-sectional view showing the process following FIG. 13E. [Figure 13H] FIG. 13G is a schematic cross-sectional view showing the process following FIG. 1F. [Figure 13I] FIG. 13H is a schematic cross-sectional view showing the process following FIG. 13G. [Figure 13J] FIG. 13I is a schematic cross-sectional view showing the process following FIG. 13H. [Figure 14A] FIG. 14A is a schematic cross-sectional view showing the manufacturing process of the display device. [Figure 14B] Figure 14B is a schematic cross-sectional view showing the process following Figure 14A. [Figure 14C] Figure 14C is a schematic cross-sectional view showing the process following Figure 14B. [Figure 14D] Figure 14D is a schematic cross-sectional view showing the process following Figure 14C. [Figure 14E] Figure 14E is a schematic cross-sectional view showing the process following Figure 14D. [Figure 15A] Figure 15A is a schematic cross-sectional view showing the manufacturing process of a display device according to a comparative example. [Figure 15B] Figure 15B is a schematic cross-sectional view showing the process following Figure 15A. [Figure 16] Figure 16 is a schematic cross-sectional view showing the manufacturing process of a display device according to a comparative example.

Embodiments for Carrying Out the Invention

[0008] Some embodiments will be described with reference to the drawings. The disclosure is merely an example, and for those that can be easily conceived by those skilled in the art for appropriate modifications while maintaining the gist of the invention, they are naturally included in the scope of the present invention. Also, for the purpose of making the description clearer, the drawings may schematically represent the width, thickness, shape, etc. of each part compared to the actual aspect, but it is merely an example and does not limit the interpretation of the present invention. Also, in this specification and each drawing, components having the same or similar functions as those described above for the already presented drawings may be assigned the same reference numerals, and detailed descriptions that overlap may be omitted as appropriate.

[0009] In addition, in the drawings, for the purpose of facilitating understanding as necessary, the X-axis, Y-axis, and Z-axis orthogonal to each other are described. The direction along the X-axis is referred to as the X direction (first direction), the direction along the Y-axis is referred to as the Y direction (second direction), and the direction along the Z-axis is referred to as the Z direction. Also, viewing various elements parallel to the Z direction is referred to as a plan view.

[0010] Each embodiment of the display device is an organic electroluminescent display device equipped with an organic light-emitting diode (OLED) as a display element, and can be mounted on various electronic devices such as televisions, personal computers, in-vehicle equipment, tablet terminals, smartphones, mobile phone terminals, and wearable terminals.

[0011] Figure 1 shows an example configuration of a display device DSP according to this embodiment. The display device DSP includes an insulating substrate 10. The substrate 10 has a display area DA for displaying an image and a peripheral area SA outside the display area DA. The substrate 10 may be glass or a flexible resin film.

[0012] In this embodiment, the shape of the substrate 10 in plan view is circular. However, the shape of the substrate 10 in plan view is not limited to a circle, and may be other shapes such as a rectangle, square, or ellipse.

[0013] The display area DA comprises multiple pixels PX arranged in a matrix in the X and Y directions. Each pixel PX includes multiple sub-pixels SP that display different colors. In this embodiment, it is assumed that each pixel PX includes a green sub-pixel SP1, a blue sub-pixel SP2, and a red sub-pixel SP3. However, each pixel PX may include sub-pixels SP of other colors, such as white, together with sub-pixels SP1, SP2, and SP3, or in place of any one of sub-pixels SP1, SP2, and SP3.

[0014] The display device DSP further includes a terminal section T located in the peripheral region SA. A flexible circuit board, for example, that supplies voltage and signals for driving the display device DSP, is connected to the terminal section T.

[0015] The sub-pixel SP comprises a pixel circuit 1 and a display element DE driven by the pixel circuit 1. The pixel circuit 1 comprises a pixel switch 2, a drive transistor 3, and a capacitor 4. The pixel switch 2 and the drive transistor 3 are switching elements composed of, for example, thin-film transistors.

[0016] The display area DA is arranged with multiple scan lines GL that supply scan signals to the pixel circuit 1 of each sub-pixel SP, multiple signal lines SL that supply video signals to the pixel circuit 1 of each sub-pixel SP, and multiple power lines PL. In the example in Figure 1, the scan lines GL and power lines PL extend in the X direction, and the signal lines SL extend in the Y direction.

[0017] The gate electrode of pixel switch 2 is connected to the scan line GL. The source electrode of pixel switch 2 is connected to the signal line SL. The drain electrode of pixel switch 2 is connected to the gate electrode of drive transistor 3 and capacitor 4. The source electrode of drive transistor 3 is connected to the power line PL and capacitor 4. The drain electrode of drive transistor 3 is connected to display element DE.

[0018] Note that the configuration of the pixel circuit 1 is not limited to the example shown. For example, the pixel circuit 1 may include more thin-film transistors and capacitors.

[0019] Figure 2 is a schematic plan view showing an example of the layout of sub-pixels SP1, SP2, and SP3. In the example in Figure 2, sub-pixels SP2 and SP3 are aligned with sub-pixel SP1 in the X direction. Furthermore, sub-pixels SP2 and SP3 are aligned in the Y direction.

[0020] When sub-pixels SP1, SP2, and SP3 are arranged in this manner, the display area DA forms columns in which sub-pixels SP2 and SP3 are alternately arranged in the Y direction, and columns in which multiple sub-pixels SP1 are repeatedly arranged in the Y direction. These columns are arranged alternately in the X direction. Note that the layout of sub-pixels SP1, SP2, and SP3 is not limited to the example in Figure 2.

[0021] A rib layer 5 is arranged in the display area DA. The rib layer 5 has pixel apertures AP1, AP2, and AP3 in sub-pixels SP1, SP2, and SP3, respectively. In the example in Figure 2, pixel aperture AP1 is larger than pixel aperture AP2, and pixel aperture AP2 is larger than pixel aperture AP3. That is, among sub-pixels SP1, SP2, and SP3, sub-pixel SP1 has the largest aperture ratio, and sub-pixel SP3 has the smallest aperture ratio. Note that the size and shape of pixel apertures AP1, AP2, and AP3 are not limited to the example shown.

[0022] Sub-pixel SP1 comprises a lower electrode LE1 (first lower electrode), an upper electrode UE1, and an organic layer OR1, which overlap with the pixel aperture AP1. Sub-pixel SP2 comprises a lower electrode LE2 (second lower electrode), an upper electrode UE2, and an organic layer OR2, which overlap with the pixel aperture AP2. Sub-pixel SP3 comprises a lower electrode LE3, an upper electrode UE3, and an organic layer OR3, which overlap with the pixel aperture AP3.

[0023] The portion of the lower electrode LE1, upper electrode UE1, and organic layer OR1 that overlaps with the pixel aperture AP1 constitutes the display element DE1 of the sub-pixel SP1. The portion of the lower electrode LE2, upper electrode UE2, and organic layer OR2 that overlaps with the pixel aperture AP2 constitutes the display element DE2 of the sub-pixel SP2. The portion of the lower electrode LE3, upper electrode UE3, and organic layer OR3 that overlaps with the pixel aperture AP3 constitutes the display element DE3 of the sub-pixel SP3. The display elements DE1, DE2, and DE3 may further include a cap layer, which will be described later. The rib layer 5 surrounds each of these display elements DE1, DE2, and DE3.

[0024] A conductive partition wall 6 is positioned in the display area DA. The partition wall 6 is located above the rib layer 5 and overlaps with the rib layer 5 overall. In the example in Figure 2, the partition wall 6 has a planar shape similar to that of the rib layer 5. That is, the partition wall 6 has openings in the sub-pixels SP1, SP2, and SP3, respectively. From another perspective, the rib layer 5 and the partition wall 6 are grid-like in plan view and surround the display elements DE1, DE2, and DE3, respectively. The partition wall 6 also surrounds the pixel apertures AP1, AP2, and AP3. The partition wall 6 serves as wiring that supplies a common voltage to the upper electrodes UE1, UE2, and UE3.

[0025] As will be explained in more detail later, the partition wall 6 has multiple slits SL6. In the example in Figure 2, each slit SL6 extends in the Y direction. For example, the sub-pixels SP1, SP2, and SP3 that make up one pixel PX are arranged between two adjacent slits SL6 in the X direction.

[0026] Figure 3 is a schematic cross-sectional view of the display device DSP along the line III-III in Figure 2. A circuit layer 11 is arranged on the substrate 10 described above. The circuit layer 11 includes various circuits and wiring such as the pixel circuit 1, scan line GL, signal line SL, and power line PL shown in Figure 1. The circuit layer 11 is covered with an organic insulating layer 12. The organic insulating layer 12 functions as a planarizing film that flattens the irregularities caused by the circuit layer 11.

[0027] The lower electrodes LE1, LE2, and LE3 are positioned on the organic insulating layer 12 and spaced apart from each other. The rib layer 5 is positioned on the organic insulating layer 12 and the lower electrodes LE1, LE2, and LE3. The ends of the lower electrodes LE1, LE2, and LE3 are covered by the rib layer 5. Although not shown in the cross-section of Figure 3, the lower electrodes LE1, LE2, and LE3 are each connected to the pixel circuit 1 of the circuit layer 11 (the drain electrode of the drive transistor 3 shown in Figure 1) through contact holes provided in the organic insulating layer 12. The rib layer 5 has a first surface S1 located on the opposite side from the substrate 10 in the Z direction.

[0028] The partition wall 6 includes a conductive lower part 61 (first lower part) positioned on the first surface S1, and an upper part 62 (first upper part) positioned above the lower part 61. The upper part 62 has a greater width than the lower part 61. As a result, both ends of the upper part 62 protrude beyond the sides of the lower part 61. This shape of partition wall 6 is called an overhang shape.

[0029] In the example shown in Figure 3, the lower part 61 has a bottom layer 63 positioned on the first surface S1 and an axial layer 64 positioned on top of the bottom layer 63. For example, the bottom layer 63 is formed thinner than the axial layer 64. In the example shown in Figure 3, both ends of the bottom layer 63 protrude from the sides of the axial layer 64. Also, the ends of the bottom layer 63 are located between the ends of the upper part 62 and the sides of the axial layer 64 in a plan view. The upper part 62 is positioned on top of the axial layer 64.

[0030] The organic layer OR1 covers the lower electrode LE1 through the pixel aperture AP1. The upper electrode UE1 covers the organic layer OR1 and faces the lower electrode LE1. The organic layer OR2 covers the lower electrode LE2 through the pixel aperture AP2. The upper electrode UE2 covers the organic layer OR2 and faces the lower electrode LE2. The organic layer OR3 covers the lower electrode LE3 through the pixel aperture AP3. The upper electrode UE3 covers the organic layer OR3 and faces the lower electrode LE3. The upper electrodes UE1, UE2, and UE3 are in contact with the side surface of the lower part 61 of the partition wall 6.

[0031] Display element DE1 includes a cap layer CP1 covering the upper electrode UE1. Display element DE2 includes a cap layer CP2 covering the upper electrode UE2. Display element DE3 includes a cap layer CP3 covering the upper electrode UE3. The cap layers CP1, CP2, and CP3 each serve as optical adjustment layers that improve the efficiency of light extraction from the organic layers OR1, OR2, and OR3, respectively.

[0032] In the following explanation, a multilayer containing an organic layer OR1, an upper electrode UE1, and a cap layer CP1 will be referred to as multilayer film FL1, a multilayer containing an organic layer OR2, an upper electrode UE2, and a cap layer CP2 will be referred to as multilayer film FL2, and a multilayer containing an organic layer OR3, an upper electrode UE3, and a cap layer CP3 will be referred to as multilayer film FL3.

[0033] Sub-pixels SP1, SP2, and SP3 are each fitted with sealing layers SE11, SE12, and SE13 (first sealing layers) that cover the laminated films FL1, FL2, and FL3, respectively. Sealing layer SE11 (first portion) continuously covers the display element DE1 and the surrounding partition wall 6. Sealing layer SE12 (second portion) continuously covers the display element DE2 and the surrounding partition wall 6. Sealing layer SE13 continuously covers the display element DE3 and the surrounding partition wall 6. Sealing layers SE11, SE12, and SE13 each have a second surface S2 located on the opposite side of the substrate 10 in the Z direction. The second surface S2 is subjected to a surface treatment described later. In the drawing, the area of ​​the second surface S2 to which this surface treatment is applied is indicated by a dashed line.

[0034] In the example shown in Figure 3, the sealing layer SE11 on the partition wall 6 between sub-pixels SP1 and SP2 is separated from the sealing layer SE12 on the same partition wall 6. Also, the sealing layer SE11 on the partition wall 6 between sub-pixels SP1 and SP3 is separated from the sealing layer SE13 on the same partition wall 6. However, any two of the sealing layers SE11, SE12, and SE13 may be in contact above the partition wall 6.

[0035] For example, gaps are formed between the sealing layers SE11, SE12, SE13 and the upper part 62 of the partition wall 6. The laminated films FL1, FL2, FL3 may be placed in at least a portion of these gaps.

[0036] The sealing layers SE11, SE12, and SE13 are covered by the resin layer RS1 (first resin layer). Specifically, the second surface S2 is covered by the resin layer RS1. The resin layer RS1 is covered by the sealing layer SE2 (second sealing layer). The sealing layer SE2 is covered by the resin layer RS2 (second resin layer). The resin layers RS1, RS2, and sealing layer SE2 are provided continuously over at least the entire display area DA, and a portion of them extends into the peripheral area SA.

[0037] In the example shown in Figure 3, a touch panel electrode TP for detecting user touch operations is placed on top of the sealing layer SE2. The touch panel electrode TP is made of, for example, a metal material and has a shape similar to the partition wall 6 in a plan view.

[0038] A cover member, such as a polarizing plate, protective film, or cover glass, may be further placed above the resin layer RS2. Such a cover member may be bonded to the resin layer RS2 via an adhesive layer, such as OCA (Optical Clear Adhesive).

[0039] The organic insulating layer 12 is formed of an organic insulating material such as polyimide. The rib layer 5 and the sealing layers SE11, SE12, SE13, SE2 are formed of an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), or silicon oxynitride (SiON). In one example, the rib layer 5 is formed of silicon oxynitride, and the sealing layers SE11, SE12, SE13, SE2 are formed of silicon nitride. The resin layers RS1, RS2 are formed of a resin material (organic insulating material) such as epoxy resin or acrylic resin.

[0040] The lower electrodes LE1, LE2, and LE3 each have a reflective layer and a pair of conductive oxide layers covering the upper and lower surfaces of the reflective layer, respectively. The reflective layer can be formed from a metallic material with excellent light reflectivity, such as silver. Each conductive oxide layer can be formed from a transparent conductive oxide such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), or IGZO (Indium Gallium Zinc Oxide).

[0041] The upper electrodes UE1, UE2, and UE3 are formed from a metallic material such as a magnesium-silver alloy (MgAg). For example, the lower electrodes LE1, LE2, and LE3 correspond to the anode, and the upper electrodes UE1, UE2, and UE3 correspond to the cathode.

[0042] The organic layers OR1, OR2, and OR3 are composed of multiple thin films including an emissive layer. In one example, the organic layers OR1, OR2, and OR3 have a structure in which a hole injection layer, a hole transport layer, an electron blocking layer, an emissive layer, a hole blocking layer, an electron transport layer, and an electron injection layer are stacked sequentially in the Z direction. However, the organic layers OR1, OR2, and OR3 may have other structures, such as a so-called tandem structure including multiple emissive layers.

[0043] The cap layers CP1, CP2, and CP3 have a laminated structure in which multiple transparent layers are stacked, for example. These transparent layers may include layers formed from inorganic materials and layers formed from organic materials. Furthermore, these transparent layers have different refractive indices. For example, the refractive indices of these transparent layers are different from those of the upper electrodes UE1, UE2, and UE3 and the sealing layers SE11, SE12, and SE13. Note that at least one of the cap layers CP1, CP2, and CP3 may be omitted.

[0044] The bottom layer 63 and axial layer 64 of the partition wall 6 are formed of, for example, a metallic material. Examples of metallic materials for the bottom layer 63 include molybdenum (Mo), titanium (Ti), titanium nitride (TiN), molybdenum-tungsten alloy (MoW), or molybdenum-niobium alloy (MoNb). Examples of metallic materials for the axial layer 64 include aluminum (Al), aluminum-neodymium alloy (AlNd), aluminum-yttrium alloy (AlY), or aluminum-silicon alloy (AlSi). At least one of the bottom layer 63 and the axial layer 64 may have a laminated structure of multiple layers. Furthermore, the axial layer 64 may include a layer formed of an insulating material.

[0045] For example, the upper part 62 of the partition wall 6 has a laminated structure consisting of a lower layer made of a metallic material and an upper layer made of a conductive oxide. As the metallic material forming the lower layer, for example, titanium, titanium nitride, molybdenum, tungsten, molybdenum-tungsten alloy, or molybdenum-niobium alloy can be used. As the conductive oxide forming the upper layer, for example, ITO or IZO can be used. The upper part 62 may also have a single-layer structure of metallic material. Furthermore, the upper part 62 may include a layer made of an insulating material.

[0046] A common voltage is supplied to the partition wall 6. This common voltage is supplied to the upper electrodes UE1, UE2, and UE3, which are in contact with the sides of the lower part 61. The lower electrodes LE1, LE2, and LE3 are supplied with pixel voltages corresponding to the video signal on the signal line SL through the pixel circuits 1 of the sub-pixels SP1, SP2, and SP3, respectively.

[0047] The organic layers OR1, OR2, and OR3 emit light in response to the application of voltage. Specifically, when a potential difference is formed between the lower electrode LE1 and the upper electrode UE1, the light-emitting layer of organic layer OR1 emits light in the green wavelength range. When a potential difference is formed between the lower electrode LE2 and the upper electrode UE2, the light-emitting layer of organic layer OR2 emits light in the blue wavelength range. When a potential difference is formed between the lower electrode LE3 and the upper electrode UE3, the light-emitting layer of organic layer OR3 emits light in the red wavelength range.

[0048] As another example, the light-emitting layers of organic layers OR1, OR2, and OR3 may emit light of the same color (e.g., white). In this case, the display device DSP may include a color filter that converts the light emitted by the light-emitting layers into light of the color corresponding to the sub-pixels SP1, SP2, and SP3. Alternatively, the display device DSP may include a layer containing quantum dots that are excited by the light emitted by the light-emitting layers to generate light of the color corresponding to the sub-pixels SP1, SP2, and SP3.

[0049] Figure 4 is a schematic cross-sectional view, enlarged from the area enclosed by frame IV in Figure 3. The second surface S2 has finer irregularities than the first surface S1. In other words, the surface roughness of the second surface S2 is greater than that of the first surface S1. From another perspective, the number of irregularities on the second surface S2 is greater than the number of irregularities on the first surface S1.

[0050] The surface roughness described herein may be the arithmetic mean roughness (Ra), maximum height roughness (Rz, Rmax), and root mean square roughness (Rq) as defined in JIS B0601:2013. The surface roughness of the first surface S1 and the second surface S2 can be measured, for example, by analyzing the cross-section of the display device DSP using a non-contact surface roughness measuring instrument.

[0051] Furthermore, the same configuration as that of the sealing layer SE11 can be applied to the sealing layers SE12 and SE13. That is, the surface roughness of the second surface S2 of the sealing layers SE12 and SE13 is greater than the surface roughness of the first surface S1.

[0052] Figure 5 is a schematic plan view showing some elements of the display device DSP. The partition wall 6 and upper electrodes UE1, UE2, and UE3 constitute a common electrode CE that applies a common voltage to the display elements DE1, DE2, and DE3. The common electrode CE is, for example, circular and overlaps the display area DA overall.

[0053] The common electrode CE has multiple slits SL6, at least one end of which reaches the outer edge (contour in a plan view) of the common electrode CE. In the example in Figure 5, both ends of the slits SL6 reach the outer edge of the common electrode CE. As a result, the common electrode CE is divided into multiple spaced segments SG through each slit SL6.

[0054] In the example shown in Figure 5, the slit SL6 extends in the Y direction. In another example, the slit SL6 may extend parallel to the X direction. The number of slits SL6 provided in the common electrode CE is not particularly limited.

[0055] The spacing of the slits SL6 in the X direction is, for example, constant. In this case, the width of each segment SG in the X direction is also constant. In other examples, the spacing of the slits SL6 and the width of the segments SG do not have to be constant.

[0056] Each segment SG has ends Ea and Eb in the direction of extension of the slit SL6 (Y direction in this embodiment). End Ea is connected to a power supply line PW provided in the peripheral region SA. The power supply line PW is connected to a terminal section T. A common voltage is applied to each segment SG from the terminal section T via the power supply line PW. In the example in Figure 5, the ends Eb of each segment SG are separated via the slit SL6 and are not connected by a conductive member such as the power supply line PW.

[0057] Because the common electrode CE is divided into multiple segments SG by the slit SL6, large eddy currents are less likely to occur in the common electrode CE. Therefore, the decrease in communication sensitivity due to near-field communication (NFC) can be suppressed.

[0058] Figure 6 is a schematic cross-sectional view showing the structure around the slit SL6. In Figure 6, elements below the organic insulating layer 12 and elements above the resin layer RS1 are omitted.

[0059] Slit SL6 is located between the lower electrodes LE1 and LE2. The sealing layers SE11 and SE12 are spaced apart directly above slit SL6. The resin layer RS1 fills slit SL6 and is in contact with the rib layer 5.

[0060] Electronic devices equipped with a display device DSP may include optical sensors, such as illuminance sensors, to detect ambient light. Such optical sensors are positioned, for example, on the back side (the side of the substrate 10) of the display device DSP. If a slit SL6 is provided in the partition wall 6, ambient light can pass through the slit SL6 and reach the optical sensor.

[0061] Figure 7 is a schematic plan view showing some elements of the display device DSP. The dam section DS1 is located in the peripheral region SA. The dam section DS1 is located between the display region DA and the terminal section T, and surrounds the display region DA. Near the terminal section T, the dam section DS1 extends in the X direction. The dam section DS1 is composed of multiple dams formed in a convex shape.

[0062] Figure 8 is a schematic plan view showing an enlarged view of the area enclosed by frame VIII in Figure 7. In the surrounding area SA, in addition to the dam section DS1 described above, the dummy pixel area DMY and the surrounding partition wall 7 are located. The dummy pixel area DMY encloses the display area DA and is adjacent to the display area DA. The surrounding partition wall 7 is located between the display area DA and the dam section DS1 and encloses the dummy pixel area DMY and the display area DA. The dam section DS1 encloses the surrounding partition wall 7, the dummy pixel area DMY, and the display area DA.

[0063] Multiple dummy pixels DPX are arranged in the dummy pixel region DMY. Dummy pixels DPX include, for example, dummy sub-pixels DP1, DP2, and DP3. Dummy sub-pixels DP1, DP2, and DP3 have structures similar to the sub-pixels SP1, SP2, and SP3 shown in Figure 2, respectively. Specifically, dummy sub-pixel DP1 comprises a lower electrode LE1, an organic layer OR1, an upper electrode UE1, and a sealing layer SE11. Dummy sub-pixel DP2 comprises a lower electrode LE2, an organic layer OR2, an upper electrode UE2, and a sealing layer SE12. Dummy sub-pixel DP3 comprises a lower electrode LE3, an organic layer OR3, an upper electrode UE3, and a sealing layer SE13.

[0064] However, the dummy sub-pixels DP1, DP2, and DP3 are configured not to emit light. Such a configuration can be achieved, for example, by cutting a part of the pixel circuit 1 in each of the dummy sub-pixels DP1, DP2, and DP3. Alternatively, the pixel apertures AP1, AP2, and AP3 may be omitted in each of the dummy sub-pixels DP1, DP2, and DP3. As a result, the rib layer 5 is interposed between the organic layers OR1, OR2, OR3 and the lower electrodes LE1, LE2, LE3, and the voltage required to cause them to emit light is no longer applied to the organic layers OR1, OR2, OR3.

[0065] A portion of the partition wall 6 is located in the dummy pixel region DMY, enclosing each of the multiple dummy pixels DPX. More specifically, the partition wall 6 encloses each of the dummy sub-pixels DP1, DP2, and DP3. The shape and layout of the openings in the partition wall 6 for each of the dummy sub-pixels DP1, DP2, and DP3 are the same as the shape and layout of the openings in the partition wall 6 for each of the sub-pixels SP1, SP2, and SP3. The slit SL6 is also provided in the dummy pixel region DMY.

[0066] The peripheral partition wall 7 has multiple openings AP arranged in a matrix. From another viewpoint, the peripheral partition wall 7 is formed in a grid pattern in plan view. In the example shown in Figure 8, multiple openings AP aligned in the X direction on the dam section DS1 side are connected by slits SL7. The peripheral partition wall 7 is covered with, for example, a sealing layer SE13. Note that the peripheral partition wall 7 may be covered with a sealing layer SE11 or a sealing layer SE12 instead of the sealing layer SE13.

[0067] The sealing layer SE13 has an end portion E13 located between the display area DA and the dam section DS1. In the example shown in Figure 8, the end portion E13 is located between the surrounding bulkhead 7 and the dam section DS1.

[0068] Dam section DS1 comprises Dam DM1 surrounding the surrounding bulkhead 7, Dam DM2 surrounding Dam DM1, Dam DM3 surrounding Dam DM2, and Dam DM4 surrounding Dam DM3. Note that the number of dams in Dam section DS1 is not limited to four.

[0069] Figure 9 is a schematic cross-sectional view of the display device DSP along the IX-IX line in Figure 8. In Figure 9, elements below the organic insulating layer 12 and elements above the resin layer RS1 are omitted.

[0070] In the peripheral region SA, a conductive layer CL is positioned between the organic insulating layer 12 and the rib layer 5. The conductive layer CL is formed using the same material and process as, for example, the lower electrodes LE1, LE2, and LE3 described above.

[0071] In the peripheral region SA, the peripheral partition wall 7 is positioned on top of the rib layer 5. The peripheral partition wall 7 includes a lower part 71 (second lower part) positioned on the first surface S1 and an upper part 72 (second upper part) positioned on top of the lower part 71. The upper part 72 has a greater width than the lower part 71. As a result, both ends of the upper part 72 protrude beyond the sides of the lower part 71.

[0072] In the example shown in Figure 9, the lower section 71 has a bottom layer 73 positioned on top of the rib layer 5 and an axial layer 74 positioned on top of the bottom layer 73. For example, the bottom layer 73 is formed to be thinner than the axial layer 74. In the example shown in Figure 9, both ends of the bottom layer 73 protrude from the sides of the axial layer 74. Also, the ends of the bottom layer 73 are located between the ends of the upper section 72 and the sides of the axial layer 74 in a plan view. The upper section 72 is positioned on top of the axial layer 74.

[0073] The bottom layer 73 is made of the same material as the bottom layer 63 shown in Figure 3. The axial layer 74 is made of the same material as the axial layer 64 shown in Figure 3. The upper part 72 is made of the same material as the upper part 62 shown in Figure 3. The lower part 71 may or may not be conductive, similar to the lower part 61 shown in Figure 3.

[0074] In the peripheral region SA, a laminated film FL3, including an organic layer OR3, an upper electrode UE3, and a cap layer CP3, is positioned on the rib layer 5 and the upper part 72. The laminated film FL3 and multiple openings AP are covered by a sealing layer SE13. In the example shown in Figure 9, the sealing layer SE13 is in contact with the cap layer CP3 through the openings AP. The sealing layer SE13 is covered by a resin layer RS1.

[0075] In the peripheral region SA, as in the display region DA, the second surface S2 of the sealing layer SE13 is also surface-treated. That is, in the peripheral region SA, the surface roughness of the second surface S2 is greater than that of the first surface S1.

[0076] Figure 10 is a schematic cross-sectional view of the display device DSP in the peripheral region SA. The circuit layer 11 shown in Figure 3 includes inorganic insulating layers 31, 32, and 33 made of inorganic insulating material, an organic insulating layer 34 made of organic insulating material, and metal layers 41 and 42. The inorganic insulating layer 31 covers the upper surface of the substrate 10. The metal layer 41 is placed on top of the inorganic insulating layer 31. The inorganic insulating layer 32 covers the metal layer 41. The metal layer 42 is placed on top of the inorganic insulating layer 32. The inorganic insulating layer 33 covers the metal layer 42. The organic insulating layer 34 covers the inorganic insulating layer 33. The organic insulating layer 34 is covered by the organic insulating layer 12.

[0077] Dams DM1, DM2, DM3, and DM4 all protrude above the substrate 10. In the example shown in Figure 10, dam DM1 is formed from organic insulating layers 12 and 34. Dams DM2, DM3, and DM4 are similarly formed from organic insulating layers 12 and 34. In other words, in this embodiment, dams DM1, DM2, DM3, and DM4 are formed from the same material as organic insulating layers 12 and 34 and in the same layer as organic insulating layers 12 and 34.

[0078] Below dams DM1 and DM2, wiring WL is located. Wiring WL constitutes, for example, the power supply line PW shown in Figure 5. In each of dams DM1 and DM2, a portion of wiring WL is located between organic insulating layers 12 and 34.

[0079] The conductive layer CL is located on the display area DA side (left side in the figure) of the dam DM1 and covers the organic insulating layer 12. The conductive layer CL is in contact with the wiring WL at the contact portion CN1. In a plan view, the contact portion CN1 is located between the end Ec of the organic insulating layer 12 and the dam DM1. The rib layer 5 continuously covers the conductive layer CL and the dams DM1, DM2, DM3, and DM4.

[0080] The end E13 of the sealing layer SE13 is located between the surrounding bulkhead 7 and the dam DM1. That is, dams DM1, DM2, DM3, and DM4 are not covered by the sealing layer SE13. Also, the portion of the rib layer 5 located directly above dams DM1, DM2, DM3, and DM4 is exposed from the sealing layer SE13. In the example shown in Figure 10, the end E13 is located between the surrounding bulkhead 7 and the end Ec.

[0081] Above the sealing layer SE13 are the resin layer RS1, sealing layer SE2, and resin layer RS2 shown in Figure 3. Above the sealing layer SE2 are the touch panel wiring TPL connected to the touch panel electrode TP shown in Figure 3. For example, the touch panel wiring TPL is made of the same material as the touch panel electrode TP.

[0082] Dams DM1, DM2, DM3, and DM4 play a role in preventing the curing of resin layers RS1 and RS2 during the manufacturing of the DSP display device. In the example shown in Figure 10, the end Er1 of resin layer RS1 is located above dam DM2. That is, resin layer RS1 covers dam DM1 and a portion of dam DM2. However, the position of end Er1 is not limited to this example.

[0083] The sealing layer SE2 covers the end portion Er1 of the resin layer RS1 and the dams DM3 and DM4. The sealing layer SE2 is in contact with the rib layer 5 in the region outside of the end portion Er1 (to the right in the figure). In the example shown in Figure 10, the end portion Er2 of the resin layer RS2 is located above the dam DM4. That is, the resin layer RS2 covers the dam DM3 and a portion of the dam DM4. However, the position of the end portion Er2 is not limited to this example.

[0084] Figure 11 is a schematic plan view of the motherboard MB (display device motherboard) according to this embodiment. The motherboard MB is rectangular, as shown in the figure, but it may also have other shapes such as a circle.

[0085] The motherboard MB has multiple panel sections PP arranged in a matrix, and margin areas BA surrounding these panel sections PP. In the example shown in Figure 11, each panel section PP is arranged in the X and Y directions with margin areas BA in between. However, the arrangement of multiple panel sections PP on the motherboard MB is not limited to this example. In other examples, some panel sections PP may be arranged without being separated by margin areas BA.

[0086] Figure 12 is a schematic plan view of the panel section PP. The outline of the panel section PP corresponds to the cut line CL1 used to cut each panel section PP from the motherboard MB.

[0087] The panel section PP has the display area DA and the peripheral area SA described above. The peripheral area SA in the panel section PP corresponds to the area between the display area DA and the cut line CL1.

[0088] The peripheral region SA further has a cut line CL2 that forms the outer shape of the substrate 10 of the display device DSP. During the manufacturing of the display device DSP, the panel portion PP is cut out from the motherboard MB along the cut line CL1. Furthermore, the display device DSP is cut out from the panel portion PP along the cut line CL2.

[0089] The panel section PP includes a dam section DS2 in addition to the dam section DS1 described above. The dam section DS2 plays the role of blocking the resin layer RS2 before it hardens. For example, the dam section DS2 has multiple dams formed of organic insulating layers 12 and 34, similar to dams DM1, DM2, DM3, and DM4.

[0090] Dam section DS1 is located between the cut line CL2 and the display area DA, enclosing the display area DA. Dam section DS2 is located between the cut lines CL1 and CL2, enclosing the cut line CL2. In the example in Figure 12, dam sections DS1 and DS2 merge near the terminal section T, and this merged portion passes between the terminal section T and the display area DA.

[0091] The cut line CL2 is mostly located between the dam sections DS1 and DS2. However, in the example in Figure 12, the cut line CL2 is located outside the dam sections DS1 and DS2 near the terminal section T. In other words, the cut line CL2 crosses the dam section DS2 near the terminal section T.

[0092] Next, an example of a manufacturing method for a display device DSP will be described. Figures 13A to 13J are schematic cross-sectional views showing the manufacturing process of a display device DSP. In Figures 13A to 13J, elements below the organic insulating layer 12 are omitted.

[0093] In forming the panel portion PP, first a circuit layer 11 and an organic insulating layer 12 are formed on the substrate 10 of the mother board MB. Next, as shown in Figure 13A, lower electrodes LE1, LE2, and LE3 are formed on the organic insulating layer 12 in the display area DA. In addition, a conductive layer CL is formed on the organic insulating layer 12 in the peripheral area SA. Subsequently, a rib layer 5 covering the lower electrodes LE1, LE2, and LE3 and the conductive layer CL is formed over the entire mother board MB. At this point, pixel apertures AP1, AP2, and AP3 are not provided on the rib layer 5. The rib layer 5 can be formed by CVD (Chemical Vapor Deposition).

[0094] After the formation of the rib layer 5, a process is carried out to form the partition wall 6 and the peripheral partition wall 7. In this process, layers for processing the bottom layers 63 and 73, layers for processing the axial layers 64 and 74, and layers for processing the upper layers 62 and 72 are formed in order. Then, a resist patterned to the shape of the partition wall 6 and the peripheral partition wall 7 is placed, and the above layers are patterned using this resist as a mask. As a result, the partition wall 6 and the peripheral partition wall 7 are formed as shown in Figure 13B.

[0095] Next, a process is carried out to create pixel apertures AP1, AP2, and AP3. In this process, a resist is formed to cover the partition wall 6 and the peripheral partition wall 7, and the rib layer 5 is patterned using this resist as a mask. As a result, as shown in Figure 13B, pixel apertures AP1, AP2, and AP3 that expose the lower electrodes LE1, LE2, and LE3 are formed in the rib layer 5. Note that the process of forming the partition wall 6 and the peripheral partition wall 7 may be carried out after the process of forming the pixel apertures AP1, AP2, and AP3 in the rib layer 5.

[0096] Subsequently, a process for forming the display element DE1 is carried out. In forming the display element DE1, first, as shown in Figure 13C, the laminated film FL1 and the sealing layer SE11 are formed over the display area DA and the peripheral area SA. Specifically, the organic layer OR1, the upper electrode UE1 covering the organic layer OR1, the cap layer CP1 covering the upper electrode UE1, and the sealing layer SE11 covering the cap layer CP1 are formed in this order. The organic layer OR1 covers the lower electrodes LE1, LE2, LE3 through the pixel apertures AP1, AP2, AP3 in the display area DA, and covers the rib layer 5 in the display area DA and the peripheral area SA.

[0097] The laminated film FL1 is divided into multiple parts by overhanging partition walls 6 and peripheral partition walls 7. The sealing layer SE11 continuously covers each divided part of the laminated film FL1, as well as the partition walls 6 and peripheral partition walls 7.

[0098] The organic layer OR1, the upper electrode UE1, and the cap layer CP1 can be formed, for example, by vapor deposition. The sealing layer SE11 can also be formed, for example, by CVD.

[0099] Next, a surface treatment step is performed on the second surface S2 of the sealing layer SE11. In this step, as shown in Figure 13D, plasma treatment is performed on the second surface S2 using the plasma treatment apparatus 100. As a result, fine irregularities are formed on the second surface S2, as shown in Figure 13E, and the second surface S2 is roughened. Consequently, the surface roughness of the second surface S2 becomes greater than that of the first surface S1.

[0100] For the plasma processing described above, for example, plasma CVD or plasma dry etching can be applied. When plasma CVD is applied, it is possible to perform the plasma CVD within the CVD apparatus in which the sealing layer SE11 shown in Figure 13C is formed. When plasma dry etching is applied, it is possible to perform the plasma dry etching within the etching apparatus in which the patterning of the multilayer film FL1 and the sealing layer SE11, described later using Figures 13F and 13G, is performed.

[0101] The gases used in plasma CVD include, for example, argon (Ar) or nitrogen trifluoride (NF3). The gases used in plasma dry etching include, for example, argon, sulfur hexafluoride (SF6) or carbon tetrafluoride (CF4). Furthermore, the surface treatment for roughening the second surface S2 is not limited to plasma treatment.

[0102] Next, the multilayer film FL1 and the sealing layer SE11 are patterned. In this patterning process, as shown in Figure 13F, a resist R1 is placed on top of the sealing layer SE11. The resist R1 covers the pixel aperture AP1 and a portion of the surrounding partition wall 6.

[0103] Subsequently, an etching process is performed using resist R1 as a mask. As a result, as shown in Figure 13G, the portions of the multilayer film FL1 and the encapsulation layer SE11 that are exposed from resist R1 are removed. In other words, the portions of the multilayer film FL1 and the encapsulation layer SE11 that overlap with the lower electrode LE1 are left, and the other portions are removed. This forms the display element DE1 on the sub-pixel SP1. This etching process may include wet etching or dry etching performed sequentially on the encapsulation layer SE11, the cap layer CP1, the upper electrode UE1, and the organic layer OR1. After these etchings, resist R1 is removed (peeled off).

[0104] Furthermore, during wet etching of the multilayer film FL1, the portion of the multilayer film FL1 located above the partition wall 6 and below the sealing layer SE11 is also removed. This creates a gap between the sealing layer SE11 above the partition wall 6 and the partition wall 6. Since the multilayer film FL1 constituting the display element DE1 is completely surrounded by the sealing layer SE11 and the partition wall 6, it is not eroded by the wet etching described above.

[0105] Subsequently, a process for forming the display element DE2 is carried out. The display element DE2 can be formed using the same procedure as the display element DE1. That is, in forming the display element DE2, a multilayer film FL2 and a sealing layer SE12 are formed. As shown in Figure 3, the multilayer film FL2 includes an organic layer OR2 that covers the lower electrode LE2 through the pixel aperture AP2, an upper electrode UE2 that covers the organic layer OR2, and a cap layer CP2 that covers the upper electrode UE2.

[0106] The organic layer OR2, the upper electrode UE2, and the cap layer CP2 can be formed, for example, by vapor deposition. The sealing layer SE12 can be formed, for example, by CVD. The laminated film FL2 is divided into multiple parts by an overhanging partition wall 6 and a peripheral partition wall 7. The sealing layer SE12 continuously covers each divided part of the laminated film FL2, the partition wall 6, and the peripheral partition wall 7. Subsequently, a plasma treatment is performed on the second surface S2 of the sealing layer SE12. This roughens the second surface S2 of the sealing layer SE12, making the surface roughness of the second surface S2 greater than that of the first surface S1. By patterning these laminated film FL2 and sealing layer SE2, a display element DE2 is formed on the sub-pixel SP2, as shown in Figure 13H.

[0107] Subsequently, a process for forming the display element DE3 is carried out. The display element DE3 can be formed using the same procedure as for the display elements DE1 and DE2. That is, in forming the display element DE3, a multilayer film FL3 and a sealing layer SE13 are formed. As shown in Figure 3, the multilayer film FL3 includes an organic layer OR3 that covers the lower electrode LE3 through the pixel aperture AP3, an upper electrode UE3 that covers the organic layer OR3, and a cap layer CP3 that covers the upper electrode UE3.

[0108] The organic layer OR3, the upper electrode UE3, and the cap layer CP3 can be formed, for example, by vapor deposition. The sealing layer SE13 can be formed, for example, by CVD. The laminated film FL3 is divided into multiple parts by an overhanging partition wall 6 and a peripheral partition wall 7. The sealing layer SE13 continuously covers each divided part of the laminated film FL3, the partition wall 6, and the peripheral partition wall 7. Subsequently, a plasma treatment is performed on the second surface S2 of the sealing layer SE13. This roughens the second surface S2 of the sealing layer SE13, making the surface roughness of the second surface S2 greater than that of the first surface S1. By patterning these laminated film FL3 and sealing layer SE13, a display element DE3 is formed on the sub-pixel SP3, as shown in Figure 13I.

[0109] Note that, while this example assumes that the display elements DE1, DE2, and DE3 are formed in this order, they may be formed in any other order.

[0110] After the display elements DE1, DE2, and DE3 are formed, a resin layer RS1, a sealing layer SE2, a touch panel electrode TP, a touch panel wiring TPL, and a resin layer RS2 are formed as shown in Figure 13J. Resin layers RS1 and RS2 can be formed, for example, by an inkjet method. The sealing layer SE2 can be formed, for example, by CVD. Then, each panel portion PP is cut out from the mother board MB along the cut line CL1. Furthermore, the panel portion PP is cut along the cut line CL2. This completes the display device DSP.

[0111] Next, we will explain an example of a manufacturing method for the DSP display device, focusing on the structure around the dam section DS1. Figures 14A to 14E are schematic cross-sectional views showing the manufacturing process of the DSP display device.

[0112] First, as shown in Figure 14A, a circuit layer 11, an organic insulating layer 12, wiring WL, a conductive layer CL, dams DM1, DM2, DM3, DM4, and a rib layer 5 are formed on the substrate 10. Dams DM1, DM2, DM3, and DM4 are each covered by the rib layer 5. A peripheral partition wall 7 and a laminated film FL3 are formed on the rib layer 5, and a sealing layer SE13 is formed that covers the rib layer 5, the peripheral partition wall 7, and the laminated film FL3. At this point, the sealing layer SE13 covers the dams DM1, DM2, DM3, and DM4.

[0113] Next, as shown in Figure 14B, a surface treatment is performed on the second surface S2 of the sealing layer SE13. This process is carried out in the same manner as the process shown in Figure 13D. That is, plasma treatment is performed on the second surface S2 using the plasma treatment apparatus 100. As a result, fine irregularities are formed on the second surface S2, as shown in Figure 14C, and the second surface S2 is roughened. Consequently, the surface roughness of the second surface S2 becomes greater than that of the first surface S1.

[0114] Next, an etching process is performed to pattern the sealing layer SE13. As shown in Figure 14D, this etching removes the portion of the sealing layer SE13 that covers the dams DM1, DM2, DM3, and DM4. As a result, the dam portion DS1 is exposed from the sealing layer SE13. Even after this etching process, the surrounding partition wall 7 is still covered by the sealing layer SE13. This etching process is the same process as the etching process used to pattern the laminated film FL3 and the sealing layer SE13 in the display area DA to form the display element DE3.

[0115] Next, as shown in Figure 14E, a resin layer RS1 is formed. The resin layer RS1 is formed by applying a liquid resin material to the area inside the dam section DS1 and allowing it to harden. Before hardening, the resin layer RS1 is dammed by the dam section DS1. In the example shown in Figure 14E, the resin layer RS1 before hardening is dammed by the dam DM2.

[0116] Next, the sealing layer SE2, touch panel wiring TPL, and resin layer RS2 are formed. Then, the PP of each panel section is cut along the cut lines CL1 and CL2, completing the display device DSP shown in Figure 10.

[0117] Here, we will explain the case where the above-described surface treatment process is not performed on the second surface S2 of each of the sealing layers SE11, SE12, and SE13.

[0118] Figures 15A, 15B, and 16 are schematic cross-sectional views showing the manufacturing process of a DSP display device according to a comparative example. Figures 15A and 15B show the structure around the slit SL6, similar to Figure 6. In this comparative example, the sealing layers SE11, SE12, and SE13 are not subjected to the surface treatment described above. Therefore, the surface roughness of the second surface S2 is approximately equal to the surface roughness of the first surface S1.

[0119] For example, when forming the resin layer RS1 using an inkjet method, droplets D of the resin material are ejected onto each panel section PP, as shown in Figure 15A. Most of these droplets D adhere to the sealing layers SE11, SE12, and SE13.

[0120] As shown in Figure 15B, droplets D adhering to the sealing layers SE11, SE12, and SE13 spread out due to wetting. The spreading droplets D are repelled by surface tension at the edges E11 and E12 of the sealing layers SE11 and SE12. As a result, there is a possibility that droplets D may not flow into the slit SL6.

[0121] If droplet D is cured without flowing into slit SL6, a shape defect may occur in the resin layer RS1 near slit SL6. If the sealing layer SE2 is formed in this state, the sealing layer SE2 may be fragmented, potentially creating a pathway for moisture to penetrate. In addition, the touch panel electrode TP formed on top of the sealing layer SE2 may break.

[0122] Figure 16, like Figure 9, shows the structure around the opening AP of the peripheral partition wall 7 located in the peripheral region SA. As shown in Figure 16, droplets D adhering to the second surface S2 of the sealing layer SE13 are repelled by surface tension at the end Es3 of the sealing layer SE13 located above the opening AP. As a result, droplets D do not flow into the opening AP, which can lead to defects in the shape of the resin layer RS1. In such cases, the formation of a moisture intrusion path due to the separation of the sealing layer SE2, or disconnection of the touch panel wiring TPL, may occur.

[0123] In contrast, in this embodiment, the second surfaces S2 of each of the sealing layers SE11, SE12, and SE13 are surface-treated, resulting in increased surface roughness. That is, by surface-treating the second surfaces S2, the wettability of the second surfaces S2 is improved, making it easier for droplets D to spread. As a result, droplets D can easily flow into the slits SL6 and openings AP. Consequently, the resin layer RS1 is smoothed, making it possible to form a resin layer RS1 with a flat upper surface. Therefore, it is possible to suppress the fragmentation of the sealing layer SE2 and the disconnection of the touch panel electrodes TP and touch panel wiring TPL. This makes it possible to improve the yield of the display device DSP.

[0124] The surface treatment (plasma treatment) can be performed within the equipment used for the pre- or post-processing steps of the surface treatment process. Specifically, the surface treatment can be performed using a CVD apparatus for forming the sealing layers SE11, SE12, and SE13, or an etching apparatus for forming the display elements DE1, DE2, and DE3. Therefore, there is no need to prepare separate equipment for surface treatment, which makes it possible to simplify the manufacturing process and reduce capital investment.

[0125] Furthermore, in this embodiment, the end portion E13 of the sealing layer SE13 is located between the surrounding partition wall 7 and the dam DM1. That is, the dams DM1, DM2, DM3, and DM4 are not covered by the sealing layer SE13. Therefore, it is possible to improve the wettability only in the areas where the sealing layers SE11, SE12, and SE13 are formed, without changing the wettability of the area surrounding the dam portion DS1. This makes it easier to control the position of the end portion Er1 of the resin layer RS1, allowing for a reduction in the width of each of the dams DM1, DM2, DM3, and DM4, or a reduction in the number of dams. As a result, it is possible to narrow the bezel of the display device DSP.

[0126] Furthermore, because end portion E13 is located between the surrounding bulkhead 7 and the dam DM1, the sealing layer SE13 and sealing layer SE2 are not in contact in the region outside end portion Er1 of the resin layer RS1. If sealing layer SE13 and sealing layer SE2 were in contact, the uneven shape of the second surface S2 would be reflected on the upper surface of sealing layer SE2, potentially leading to the formation of unintended irregularities on the upper surface of sealing layer SE2. These irregularities on the upper surface of sealing layer SE2 could cause the region where sealing layer SE13 and sealing layer SE2 are in contact to appear cloudy, potentially hindering visual inspection.

[0127] On the other hand, in this embodiment, the sealing layer SE2 is in contact with the rib layer 5 in the region outside the end Er1 of the resin layer RS1. Therefore, the clouding described above does not occur, and it is possible to suppress the deterioration of yield. Furthermore, since the resin layer RS1 is formed thicker than the sealing layer SE2, almost no irregularities caused by the uneven shape of the second surface S2 are formed on the upper surface of the resin layer RS1.

[0128] All display devices and methods for manufacturing display devices that can be implemented by those skilled in the art by appropriately modifying the design based on the display devices and methods for manufacturing display devices described above as embodiments of the present invention also fall within the scope of the present invention insofar as they encompass the gist of the present invention.

[0129] Within the scope of the concept of the present invention, a person skilled in the art can conceive of various modifications, and such modifications are also understood to fall within the scope of the present invention. For example, modifications to the above-described embodiments in which a person skilled in the art has appropriately added, deleted, or modified components, or added, omitted, or modified processes, are also included within the scope of the present invention, as long as they retain the gist of the present invention.

[0130] Furthermore, any other effects and advantages brought about by the embodiments described above that are obvious from the description herein or that can be appropriately conceived by those skilled in the art are naturally considered to be brought about by the present invention. [Explanation of Symbols]

[0131] DSP...Display device, DE1, DE2, DE3...Display elements, LE1, LE2, LE3...Lower electrodes, OR1, OR2, OR3...Organic layers, UE1, UE2, UE3...Upper electrodes, SE11, SE12, SE13, SE2...Sealing layers, RS1, RS2...Resin layers, 5...Rib layer, 6...Partition wall, 7...Peripheral partition wall, 61, 71...Lower part, 62, 72...Upper part, 63, 73...Bottom layer, 64, 74...Axial layer, 100...Plasma processing device.

Claims

1. A substrate having a display area for displaying an image and a peripheral area outside the display area, In the display area, a first lower electrode is positioned above the substrate, A rib layer made of an inorganic material has a first surface located on the opposite side of the substrate and a pixel aperture that overlaps with the first lower electrode, A partition wall comprising a first lower portion disposed on the first surface and having conductivity, and a first upper portion disposed above the first lower portion and protruding from the side surface of the first lower portion, The organic layer in contact with the first lower electrode through the pixel aperture, The upper electrode covers the organic layer and is in contact with the first lower part, A cap layer covering the upper electrode, The first sealing layer, which is located on the opposite side of the substrate and has a second surface rougher than the first surface, covers the cap layer and is made of an inorganic material, comprises Display device.

2. The dam section is located in the surrounding area, encloses the display area, and is covered by the rib layer, The first sealing layer has an end portion located between the display area and the dam portion in a plan view. The display device according to claim 1.

3. The second surface is covered and further comprises a first resin layer made of an organic material, The first resin layer covers at least a portion of the dam section. The display device according to claim 2.

4. The peripheral region is further provided with a peripheral partition wall that is positioned on the rib layer and surrounds the display area, The first sealing layer covers the peripheral partition wall. The display device according to claim 1.

5. The aforementioned peripheral partition wall has a plurality of openings, The first sealing layer covers the plurality of openings. The display device according to claim 4.

6. The first sealing layer is in contact with the cap layer through the opening. The display device according to claim 5.

7. The dam section is located in the surrounding area, enclosing the display area and the surrounding partition wall, and is further covered by the rib layer, The first sealing layer has an end located between the peripheral partition wall and the dam section, The display device according to claim 4.

8. The peripheral partition wall includes a second lower portion positioned on the first surface and a second upper portion positioned above the second lower portion and protruding from the side surface of the second lower portion. The display device according to any one of claims 4 to 7.

9. The display area is further provided with a second lower electrode that is positioned apart from the first lower electrode in a first direction, The partition wall is positioned between the first lower electrode and the second lower electrode and has a slit extending in a second direction intersecting the first direction. The display device according to claim 1.

10. The first sealing layer has a first portion positioned directly above the first lower electrode and a second portion positioned directly above the second lower electrode. The first and second portions are spaced apart directly above the slit. The display device according to claim 9.

11. The second surface is covered and further comprises a first resin layer made of an organic material, The first resin layer is in contact with the rib layer in the slit. The display device according to claim 9 or 10.

12. A first resin layer, formed of an organic material, covers the second surface, A second sealing layer, formed of an inorganic material, covers the first resin layer, The present invention further comprises a second resin layer made of an organic material that covers the second sealing layer, The display device according to claim 1.

13. A lower electrode is formed in the display area where the image is displayed. A rib layer made of an inorganic material having a pixel aperture that overlaps with the lower electrode, and a partition wall including a conductive first lower part disposed on the rib layer and a first upper part disposed on the first lower part and protruding from the side surface of the first lower part, An organic layer in contact with the lower electrode through the pixel aperture, an upper electrode covering the organic layer and in contact with the first lower part, a cap layer covering the upper electrode, and a first sealing layer covering the cap layer are formed over the display area and the peripheral area outside the display area. The upper surface of the first sealing layer is subjected to a surface treatment, and the upper surface is roughened. A method for manufacturing a display device.

14. The aforementioned surface treatment is plasma treatment. A method for manufacturing a display device according to claim 13.

15. The aforementioned plasma treatment is plasma CVD or plasma dry etching. A method for manufacturing a display device according to claim 14.

16. The gas used in the plasma treatment includes one of argon, nitrogen trifluoride, sulfur hexafluoride, or carbon tetrafluoride. A method for manufacturing a display device according to claim 14 or 15.

17. After the surface treatment, a resist covering the pixel aperture is formed on the first sealing layer, and the organic layer, the upper electrode, the cap layer, and the portion of the first sealing layer exposed from the resist are removed by etching to form a display element. A method for manufacturing a display device according to claim 13.

18. Before forming the rib layer, a dam section surrounding the display area is formed in the surrounding area. In the step of forming the rib layer, the rib layer covering the dam portion is formed. In the step of forming the first sealing layer, the first sealing layer covering the dam portion is formed on the rib layer, After the surface treatment, the first sealing layer covering the dam portion is removed. A method for manufacturing a display device according to claim 13.

19. After removing the first sealing layer covering the dam portion, a first resin layer is formed on the first sealing layer, the end of which is dammed by the dam portion. A method for manufacturing a display device according to claim 18.

20. Simultaneously with the process of forming the partition wall, a peripheral partition wall is formed in the peripheral region, which includes a second lower portion positioned on the rib layer and a second upper portion positioned on the second lower portion and protruding from the side surface of the second lower portion, and which surrounds the display area. After removing the first sealing layer covering the dam section, the first sealing layer covers the surrounding partition wall. A method for manufacturing a display device according to claim 18.

Images