Semiconductor equipment
The semiconductor device integrates a back-side gate and RC-IGBT region to enhance IGBT performance by controlling electron discharge and diode current flow, addressing snapback and tail current issues for improved characteristics.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- KK TOSHIBA
- Filing Date
- 2024-11-14
- Publication Date
- 2026-05-26
AI Technical Summary
Existing semiconductor devices face challenges in improving characteristics such as suppressing snapback, tail current generation, and maintaining good diode characteristics in Insulated Gate Bipolar Transistors (IGBTs), particularly in Reverse Conductive IGBT (RC-IGBT) configurations.
The semiconductor device incorporates a back-side gate region and an RC-IGBT region within a single continuous semiconductor component, allowing for controlled electron discharge and diode current flow through the back gate, thereby suppressing snapback and tail current while enhancing diode characteristics.
This configuration improves the performance of IGBTs by relaxing constraints on area ratios and enabling efficient electron injection and current control, resulting in better diode characteristics and reduced snapback.
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Figure 2026086197000001_ABST
Abstract
Description
Technical Field
[0001] Embodiments of the present invention relate to semiconductor devices.
Background Art
[0002] For example, in semiconductor devices, improvement in characteristics is desired.
Prior Art Documents
Patent Documents
[0003]
Patent Document 1
Summary of the Invention
Problems to be Solved by the Invention
[0004] Embodiments of the present invention provide a semiconductor device capable of improving characteristics.
Means for Solving the Problems
[0005] According to embodiments of the present invention, the semiconductor device includes a first electrode, a second electrode, a third electrode, a fourth electrode, a semiconductor member, a first insulating member, and a second insulating member. The first electrode includes a first electrode portion and a second electrode portion. The semiconductor member includes a first semiconductor portion and a second semiconductor portion. The first semiconductor portion is located between the first electrode portion and the second electrode in a first direction from the first electrode to the second electrode. The second semiconductor portion is located between the second electrode portion and the second electrode in the first direction. The direction from the first electrode portion to the second electrode portion intersects the first direction. Each of the first and second semiconductor portions includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, and a third semiconductor region of a first conductivity type. The second electrode is electrically connected to the third semiconductor region. The second semiconductor region is located between the first semiconductor region and the third semiconductor region. At least a portion of the first insulating member is provided between the plurality of third electrodes and the semiconductor member. The first semiconductor portion includes a fourth semiconductor region of the second conductivity type and a fifth semiconductor region of the first conductivity type. The fourth electrode is located between the first electrode portion and the first semiconductor portion. The fifth semiconductor region is electrically connected to the first electrode portion. The fourth semiconductor region is located between the fifth semiconductor region and the first semiconductor region included in the first semiconductor portion. The second insulating member is located between the fourth electrode and the first semiconductor portion. The second semiconductor portion includes a sixth semiconductor region of the second conductivity type and a seventh semiconductor region of the first conductivity type. The sixth and seventh semiconductor regions are located between the second electrode portion and the first semiconductor region included in the second semiconductor portion. [Brief explanation of the drawing]
[0006] [Figure 1] Figure 1 is a schematic cross-sectional view illustrating a semiconductor device according to the first embodiment. [Figure 2] Figure 2 is a schematic diagram illustrating the operation of a semiconductor device according to the first embodiment. [Figure 3] Figure 3 is a schematic cross-sectional view illustrating a semiconductor device according to the second embodiment. [Figure 4] Figure 4 is a schematic diagram illustrating the operation of a semiconductor device according to the second embodiment. [Figure 5] Figures 5(a) to 5(c) are schematic plan views illustrating a semiconductor device according to an embodiment. [Modes for carrying out the invention]
[0007] Embodiments of the present invention will be described below with reference to the drawings. Drawings are schematic or conceptual, and the relationships between the thickness and width of each part, as well as the ratios of the sizes of different parts, are not necessarily identical to those of reality. Even when representing the same part, the dimensions and ratios may be depicted differently in different drawings. In this specification and in each figure, elements similar to those described above are denoted by the same reference numerals with respect to previously shown figures, and detailed explanations are omitted as appropriate.
[0008] (First Embodiment) Figure 1 is a schematic cross-sectional view illustrating a semiconductor device according to the first embodiment. As shown in Figure 1, the semiconductor device 110 according to this embodiment includes a first electrode 51, a second electrode 52, a plurality of third electrodes 53, a fourth electrode 54, a semiconductor member 10M, a first insulating member 41, and a second insulating member 42.
[0009] The first electrode 51 includes a first electrode portion 51a and a second electrode portion 51b. The semiconductor member 10M includes a first semiconductor portion 10a and a second semiconductor portion 10b. The first semiconductor portion 10a is located between the first electrode portion 51a and the second electrode 52 in a first direction D1 from the first electrode 51 to the second electrode 52. The second semiconductor portion 10b is located between the second electrode portion 51b and the second electrode 52 in the first direction D1.
[0010] The first direction D1 is defined as the Z-axis direction. One direction perpendicular to the Z-axis direction is defined as the X-axis direction. The direction perpendicular to both the Z-axis and X-axis directions is defined as the Y-axis direction.
[0011] For example, the first electrode 51 and the second electrode 52 are along the X-Y plane. The semiconductor member 10M is along the X-Y plane.
[0012] The direction from the first electrode portion 51a to the second electrode portion 51b intersects the first direction D1. The direction from the first semiconductor portion 10a to the second semiconductor portion 10b intersects the first direction D1.
[0013] Each of the first semiconductor portion 10a and the second semiconductor portion 10b includes a first semiconductor region 11 of the first conductivity type, a second semiconductor region 12 of the second conductivity type, and a third semiconductor region 13 of the first conductivity type.
[0014] The first conductivity type is one of n-type and p-type. The second conductivity type is the other of n-type and p-type. Hereinafter, it is assumed that the first conductivity type is n-type and the second conductivity type is p-type.
[0015] The second electrode 52 is electrically connected to the third semiconductor region 13. The second semiconductor region 12 is between the first semiconductor region 11 and the third semiconductor region 13. The first semiconductor region 11 may function as a drift layer, for example. The second semiconductor region 12 may function as a base layer, for example. The third semiconductor region 13 may function as a source layer, for example.
[0016] At least a part of the first insulating member 41 is provided between the plurality of third electrodes 53 and the semiconductor member 10M. The first insulating member 41 insulates the plurality of third electrodes 53 from the semiconductor member 10M.
[0017] The first semiconductor portion 10a includes a fourth semiconductor region 14 of the second conductivity type and a fifth semiconductor region 15 of the first conductivity type. The fourth electrode 54 is between the first electrode portion 51a and the first semiconductor portion 10a. The fifth semiconductor region 15 is electrically connected to the first electrode 51 (for example, the first electrode portion 51a). The fourth semiconductor region 14 is between the fifth semiconductor region 15 and the first semiconductor region 11 included in the first semiconductor portion 10a.
[0018] The second insulating member 42 is between the fourth electrode 54 and the first semiconductor portion 10a. A part of the second insulating member 42 may be provided between the fourth electrode 54 and the first electrode 51. The second insulating member 42 insulates the fourth electrode 54 from the semiconductor member 10M (the first semiconductor portion 10a). The second insulating member 42 insulates the fourth electrode 54 from the first electrode 51.
[0019] The second semiconductor portion 10b includes a sixth semiconductor region 16 of the second conductivity type and a seventh semiconductor region 17 of the first conductivity type. The sixth semiconductor region 16 and the seventh semiconductor region 17 are between the second electrode portion 51b and the first semiconductor region 11 included in the second semiconductor portion 10b.
[0020] In the semiconductor device 110, the current flowing between the first electrode 51 and the second electrode 52 is controlled by the potentials of the plurality of third electrodes 53. The potentials of the plurality of third electrodes 53 may be, for example, potentials based on the potential of the second electrode 52. The first electrode 51 functions as, for example, a collector electrode. The second electrode 52 functions as, for example, an emitter electrode. The plurality of third electrodes 53 function as gate electrodes (for example, main gate electrodes). The semiconductor device 110 is, for example, an IGBT (Insulated Gate Bipolar Transistor).
[0021] In the semiconductor device 110, a fourth electrode 54 is provided. By controlling the potential of the fourth electrode 54, the flow of carriers between the semiconductor member 10M and the first electrode 51 can be controlled. The fourth electrode 54 functions as, for example, a back gate.
[0022] The first electrode portion 51a and the first semiconductor portion 10a are regions where a back gate is provided. The second electrode portion 51b and the second semiconductor portion 10b are regions where a back gate is not provided. The second semiconductor portion 10b is a region where a p-type sixth semiconductor region 16 and an n-type seventh semiconductor region 17 are provided. The second electrode portion 51b and the second semiconductor portion 10b correspond to an RC-IGBT (Reverse Conductive Insulated Gate Bipolar Transistor) region.
[0023] In this embodiment, a single continuous semiconductor component 10M is provided with a back-side gate region and an RC-IGBT region. This makes it possible to provide a semiconductor device with improved characteristics.
[0024] For example, in an RC-IGBT, a first reference example is conceivable in which a large area of p-type semiconductor region is provided on the side (back side) of the first electrode 51 in order to suppress snapback. The large area of p-type semiconductor region functions as a trigger region to suppress snapback.
[0025] In this first example, in a large area of the p-type semiconductor region, there is no path for electron escape. As a result, for example, a tail current is generated. Furthermore, in the first example, when the diode mode state should be reached, no diode current flows. Therefore, the diode characteristics deteriorate.
[0026] In contrast, in this embodiment, stored electrons can be discharged through the channel of the back gate. This suppresses the tail current. Furthermore, diode current can flow through the channel of the back gate. This results in good diode characteristics. According to this embodiment, snapback is suppressed while the tail current is suppressed, resulting in good diode characteristics. According to this embodiment, the characteristics can be improved.
[0027] Furthermore, in the second reference example, a control gate electrode is provided in addition to the large area p-type semiconductor region in the first reference example. In the second reference example, because diode current does not flow due to the large area p-type semiconductor region, the function of the control gate electrode cannot be obtained.
[0028] In contrast, in this embodiment, the diode current can flow through the back gate, thus providing the benefits of the control gate electrode operation (e.g., loss suppression).
[0029] On the other hand, there is a third reference example in which the RC-IGBT portion (second electrode portion 51b) is not provided, and the back gate is provided across the entire surface. In the third reference example, in order to properly operate the back gate, there are likely to be constraints on the area ratio between the p-type semiconductor region and the n-type semiconductor region on the back side. This limits the improvement of characteristics.
[0030] In contrast, in this embodiment, both the RC-IGBT portion and the back gate portion are provided. This relaxes the constraints on the area ratio, resulting in higher performance.
[0031] In this embodiment, the direction from the sixth semiconductor region 16 to the seventh semiconductor region 17 intersects with the first direction D1.
[0032] The second semiconductor portion 10b may include a plurality of sixth semiconductor regions 16 and a plurality of seventh semiconductor regions 17. One of the plurality of sixth semiconductor regions 16 lies between one of the plurality of seventh semiconductor regions 17 and another of the plurality of seventh semiconductor regions 17. One of the plurality of seventh semiconductor regions 17 lies between one of the plurality of sixth semiconductor regions 16 and another of the plurality of sixth semiconductor regions 16.
[0033] The sixth semiconductor region 16 and the seventh semiconductor region 17 may be arranged alternately in a direction intersecting the first direction D1.
[0034] As shown in Figure 1, each of the first semiconductor portion 10a and the second semiconductor portion 10b may further include an eighth semiconductor region 18 of the first conductivity type. The fourth semiconductor region 14 lies between the first electrode portion 51a and a part of the eighth semiconductor region 18. The sixth semiconductor region 16 and the seventh semiconductor region 17 lies between the second electrode portion 51b and another part of the eighth semiconductor region 18.
[0035] The concentration of the eighth impurity of the first conductivity type in the eighth semiconductor region 18 is higher than the concentration of the first impurity of the first conductivity type in the first semiconductor region 11. The concentration of the eighth impurity is, for example, 1 × 10⁻⁶ 18 cm -3 The above is 1 x 1021 cm -3 The following is acceptable. The first impurity concentration is, for example, 1 × 10⁻⁶ 12 cm -3 The above is 1 x 10 15 cm -3 The following is fine.
[0036] As shown in Figure 1, the direction from a portion of the fourth electrode 54 to a portion of the eighth semiconductor region 18 may be along the first direction D1. A portion of the fourth semiconductor region 14 is located between a portion of the eighth semiconductor region 18 and the fifth semiconductor region 15 in a direction intersecting the first direction D1.
[0037] In the example shown in Figure 1, multiple third electrodes 53 are aligned along a second direction D2 that intersects with a first direction D1. For example, multiple third electrodes 53 extend along a third direction D3. The third direction D3 intersects with the first direction D1 and the second direction D2. The fourth electrode 54 extends along the third direction D3.
[0038] As shown in Figure 1, a plurality of fourth electrodes 54 may be provided. The direction from one of the plurality of fourth electrodes 54 to another of the plurality of fourth electrodes 54 may be along the second direction D2. The direction in which the plurality of fourth electrodes 54 are aligned may be along the direction in which the plurality of third electrodes 53 are aligned. This allows the current path controlled by the plurality of third electrodes 53 to be aligned with the current path controlled by the plurality of fourth electrodes 54. The current can be effectively controlled. In this embodiment, the direction in which the fourth electrodes 54 extend may intersect with the direction in which the plurality of third electrodes 53 extend.
[0039] In the embodiment, the pitch of the plurality of sixth semiconductor regions 16 (sixth semiconductor region pitch) is preferably, for example, 3 to 2000 times the pitch of the plurality of third electrodes 53 (third electrode pitch). This makes it possible to improve the efficiency of electron injection from the back surface during diode operation by reducing the back surface gate pitch, for example. For example, it is possible to improve the diode current efficiency of the entire chip. In one example, the sixth semiconductor region pitch is, for example, 100 μm or more and 1000 μm or less. The third electrode pitch is, for example, 0.5 μm or more and 30 μm or less.
[0040] The pitch of the multiple fourth electrodes 54 (fourth electrode pitch) is preferably 1 to 2000 times the pitch of the multiple third electrodes 53 (third electrode pitch). The fourth electrode pitch may be larger than the third electrode pitch. In one example, the fourth electrode pitch is, for example, 0.5 μm or more and 1000 μm or less.
[0041] The pitch of the multiple fourth electrodes 54 (fourth electrode pitch) is preferably 0.0005 times or more and 10 times or less the pitch of the multiple sixth semiconductor regions 16 (sixth semiconductor region pitch). The fourth electrode pitch may be less than the sixth semiconductor region pitch.
[0042] The concentration of the fourth impurity of the second conductivity type in the fourth semiconductor region 14 is preferably 0.1 times or more and 1000 times or less the concentration of the sixth impurity of the second conductivity type in the sixth semiconductor region 16. This makes it easier to effectively pass IGBT current throughout the entire chip, for example. For example, the concentration of the fourth impurity may be higher than the concentration of the sixth impurity.
[0043] The concentration of the fifth impurity of the first conductivity type in the fifth semiconductor region 15 is preferably 0.001 times or more and 10 times or less the concentration of the seventh impurity of the first conductivity type in the seventh semiconductor region 17. This makes it easier, for example, to effectively pass diode current. For example, the concentration of the fifth impurity may be lower than the concentration of the seventh impurity.
[0044] As shown in Figure 1, the thickness of the fourth semiconductor region 14 along the first direction D1 is defined as the fourth thickness t4. The thickness of the sixth semiconductor region 16 along the first direction D1 is defined as the sixth thickness t6. In one example, the fourth thickness t4 is between 10 nm and 100 μm. In another example, the sixth thickness t6 is between 1 nm and 100 μm.
[0045] The thickness of the fifth semiconductor region 15 along the first direction D1 is defined as the fifth thickness t5. The thickness of the seventh semiconductor region 17 along the first direction D1 is defined as the seventh thickness t7. In one example, the fifth thickness t5 is between 1 nm and 100 μm. In another example, the seventh thickness t7 is between 1 nm and 100 μm.
[0046] As shown in Figure 1, the direction from the third electrode 53 to the second semiconductor region 12 intersects with the first direction D1. The direction from the third electrode 53 to the third semiconductor region 13 also intersects with the first direction D1. The third electrode 53 is a trench-type gate electrode. In this embodiment, a planar gate electrode structure may be applied.
[0047] As shown in Figure 1, in this example, the semiconductor device 110 further includes a sixth electrode 56. The sixth electrode 56 is located between one of the plurality of third electrodes 53 and another of the plurality of third electrodes 53. A portion of the first insulating member 41 is in contact with a portion of the plurality of third electrodes 53 and the third semiconductor region 13. The first insulating member 41 is not in contact with the third semiconductor region 13 between the sixth electrode 56 and the third semiconductor region 13.
[0048] The semiconductor device 110 may further include a third insulating member 43. The third insulating member 43 is provided between a plurality of third electrodes 53 and a second electrode 52. The third insulating member 43 is provided between a sixth electrode 56 and a second electrode 52.
[0049] As shown in Figure 1, a control unit 70 may be provided. The control unit 70 may be included in the semiconductor device 110. The control unit 70 may be provided separately from the semiconductor device 110. The control unit 70 is electrically connected to the first electrode 51, the second electrode 52, the third electrode 53, and the fourth electrode 54. The control unit 70 is configured to control the potential of the multiple third electrodes 53 (third electrode potential VE3). The control unit 70 is configured to control the potential of the fourth electrode 54 (fourth electrode potential VE4). The third electrode potential VE3 and the fourth electrode potential VE4 may be, for example, potentials based on the potential of the second electrode 52.
[0050] Figure 2 is a schematic diagram illustrating the operation of a semiconductor device according to the first embodiment. The horizontal axis in Figure 2 represents time tm. The vertical axis in Figure 2 represents the potential of the third electrode VE3 or the potential of the fourth electrode VE4.
[0051] The control unit 70 is configured to move the multiple third electrodes 53 from the first potential V1 to the second potential V2, which is higher than the first potential V1, at the first time tm1. The control unit 70 is configured to move the multiple third electrodes 53 from the second potential V2 to the first potential V1 at the second time tm2, following the first time tm1. The control unit 70 is configured to move the multiple third electrodes 53 from the first potential V1 to the second potential V2 at the third time tm3, following the second time tm2. The control unit 70 is configured to move the multiple third electrodes 53 from the second potential V2 to the first potential V1 at the fourth time tm4, following the third time tm3. The control unit 70 is configured to move the multiple third electrodes 53 from the first potential V1 to the second potential V2 at the fifth time tm5, following the fourth time tm4. The first potential V1 and the second potential V2 are potentials based on the potential of the second electrode 52.
[0052] The control unit 70 is configured to set the fourth electrode 54 to the third potential V3 at the first time tm1. The control unit 70 is configured to move the fourth electrode 54 from the third potential V3 to the fourth potential V4, which is higher than the third potential V3, at the sixth time tm6, between the first time tm1 and the second time tm2. The control unit 70 is configured to move the fourth electrode 54 from the fourth potential V4 to the third potential V3 at the seventh time tm7, between the sixth time tm6 and the third time tm3. The control unit 70 is configured to move the fourth electrode 54 from the third potential V3 to the fourth potential V4 at the eighth time tm8, between the seventh time tm7 and the third time tm3. The control unit 70 is configured to move the fourth electrode 54 from the fourth potential V4 to the third potential V3 at the ninth time tm9, after the fourth time tm4. The third potential V3 and the fourth potential V4 are potentials based on the potential of the first electrode 51.
[0053] The seventh time point tm7 may be substantially the same as the second time point tm2. The ninth time point tm9 may be substantially the same as the fifth time point tm5.
[0054] The period between the first time point tm1 and the second time point tm2 corresponds, for example, to the IGBT mode period. The period between the eighth time point tm8 and the fourth time point tm4 corresponds to the diode mode period. The period between the third time point tm3 and the fourth time point tm4 corresponds to the DESAT control period. During the DESAT control period, carriers are extracted by controlling the surface gate.
[0055] During the period between the 6th time tm6 and the 7th time tm7, the carrier is discharged by the operation of the 4th electrode 54 (backside gate). The period between the 8th time tm8 and the 9th time tm9 corresponds to the ON period of the backside gate in diode mode.
[0056] As shown in Figure 2, the control unit 70 may include a first circuit 70a and a second circuit 70b. The first circuit 70a is configured to control the potentials of a plurality of third electrodes 53 (third electrode potential VE3). The second circuit 70b is configured to control the potential of the fourth electrode 54 (fourth electrode potential VE4). These circuits may be isolated from each other. Isolation may be achieved, for example, by a photocoupler or a DC-DC converter.
[0057] (Second Embodiment) Figure 3 is a schematic cross-sectional view illustrating a semiconductor device according to the second embodiment. As shown in Figure 3, the semiconductor device 111 according to this embodiment further includes a fifth electrode 55. The configuration of the semiconductor device 111, excluding the fifth electrode 55, may be the same as that of the semiconductor device 110.
[0058] In the semiconductor device 111, the fifth electrode 55 is located between one of the plurality of third electrodes 53 and another of the plurality of third electrodes 53. A portion of the first insulating member 41 is provided between the fifth electrode 55 and the semiconductor member 10M. The portion of the first insulating member 41 insulates the fifth electrode 55 from the semiconductor member 10M.
[0059] The fifth electrode 55 functions, for example, as a control gate. The fifth electrode 55 may be driven independently of the third electrode 53.
[0060] A control unit 70 may be provided in the semiconductor device 111. In addition to the operation described with respect to Figure 2, the control unit 70 may be configured to further control the fifth electrode potential VE5 of the fifth electrode 55. For example, the first circuit 70a is configured to control the fifth electrode potential VE5.
[0061] Figure 4 is a schematic diagram illustrating the operation of a semiconductor device according to the second embodiment. The horizontal axis in Figure 4 represents time tm. The vertical axis in Figure 4 represents the potential of the third electrode VE3, the potential of the fourth electrode VE4, or the potential of the fifth electrode VE5.
[0062] As shown in Figure 4, the control unit 70 is configured to perform the following scans in addition to the operations described with respect to Figure 2. The control unit 70 is configured to move the fifth electrode 55 from the fifth potential V5 to the sixth potential V6, which is higher than the fifth potential V5, at the first time tm1. The control unit 70 is configured to move the fifth electrode 55 from the sixth potential V6 to the fifth potential V5 at the sixth time tm6. The control unit 70 is configured to move the fifth electrode 55 from the fifth potential V5 to the sixth potential V6 at the ninth time tm9. For example, the control unit 70 is configured to keep the fifth electrode 55 at the fifth potential V5 between the sixth time tm6 and the ninth time tm9.
[0063] For example, at the sixth time tm6, the fifth electrode 55 shifts from the sixth potential V6 to the fifth potential V5, causing carriers to be discharged in the vicinity of the fifth electrode 55.
[0064] Figures 5(a) to 5(c) are schematic plan views illustrating a semiconductor device according to an embodiment. These figures illustrate the planar patterns of the first electrode portion 51a and the second electrode portion 51b. These figures also illustrate the planar patterns of the first semiconductor portion 10a and the second semiconductor portion 10b.
[0065] As shown in Figures 5(a) and 5(b), the first electrode portion 51a may be provided between a part of the second electrode portion 51b and another part of the second electrode portion 51b in a direction intersecting the first direction D1. The first semiconductor portion 10a may be provided between a part of the second semiconductor portion 10b and another part of the second semiconductor portion 10b in a direction intersecting the first direction D1. The planar patterns of the first electrode portion 51a and the first semiconductor portion 10a are arbitrary.
[0066] As shown in Figure 5(c), a plurality of first electrode portions 51a may be provided. One of the plurality of first electrode portions 51a may be provided between a part of the second electrode portion 51b and another part of the second electrode portion 51b. A plurality of first semiconductor portions 10a may be provided. One of the plurality of first semiconductor portions 10a may be provided between a part of the second semiconductor portion 10b and another part of the second semiconductor portion 10b.
[0067] In embodiments, at least one of the first electrode 51 and the second electrode 52 may contain a metal. The metal may include, for example, at least one selected from the group consisting of Al, Ti, Ni, Au, Ag, and Cu. At least one of the third electrode 53, the fourth electrode 54, the fifth electrode 55, and the sixth electrode 56 may contain polysilicon. The semiconductor member 10M may contain silicon. The semiconductor member 10M may contain a compound semiconductor. The compound semiconductor may contain at least one selected from the group consisting of SiC, GaN, GaO, and GaAs.
[0068] In the embodiment, information regarding the shape of the semiconductor region is obtained, for example, by electron microscope images. Information regarding composition and elemental concentration is obtained, for example, by EDX (Energy Dispersive X-ray Spectroscopy) or SIMS (Secondary Ion Mass Spectrometry).
[0069] The embodiments may include the following technical proposals. (Technical proposal 1) A first electrode including a first electrode portion and a second electrode portion, The second electrode and Multiple third electrodes, The fourth electrode and, A semiconductor component including a first semiconductor portion and a second semiconductor portion, First insulating member and The second insulating member, Equipped with, The first semiconductor portion is located between the first electrode portion and the second electrode in a first direction from the first electrode to the second electrode, The second semiconductor portion is located between the second electrode portion and the second electrode in the first direction. The direction from the first electrode portion to the second electrode portion intersects with the first direction. Each of the first semiconductor portion and the second semiconductor portion is: The first semiconductor region of the first conductivity type, The second semiconductor region of the second conductivity type, The third semiconductor region of the first conductivity type, Includes, The second electrode is electrically connected to the third semiconductor region. The second semiconductor region is located between the first semiconductor region and the third semiconductor region. At least a portion of the first insulating member is provided between the plurality of third electrodes and the semiconductor member, The first semiconductor portion is The fourth semiconductor region of the second conductivity type, The fifth semiconductor region of the first conductivity type, Includes, The fourth electrode is located between the first electrode portion and the first semiconductor portion. The fifth semiconductor region is electrically connected to the first electrode portion. The fourth semiconductor region is located between the fifth semiconductor region and the first semiconductor region included in the first semiconductor portion. The second insulating member is located between the fourth electrode and the first semiconductor portion. The second semiconductor portion is The sixth semiconductor region of the second conductivity type, The seventh semiconductor region of the first conductivity type, Includes, The sixth semiconductor region and the seventh semiconductor region are located between the second electrode portion and the first semiconductor region included in the second semiconductor portion, respectively, in a semiconductor device.
[0070] (Technical proposal 2) The semiconductor device according to Technical Proposal 1, wherein the direction from the sixth semiconductor region to the seventh semiconductor region intersects with the first direction.
[0071] (Technical proposal 3) The second semiconductor portion includes a plurality of the sixth semiconductor regions and a plurality of the seventh semiconductor regions. One of the plurality of sixth semiconductor regions is located between one of the plurality of seventh semiconductor regions and another of the plurality of seventh semiconductor regions. The semiconductor device according to Technical Proposal 2, wherein one of the plurality of seventh semiconductor regions is located between one of the plurality of sixth semiconductor regions and another of the plurality of sixth semiconductor regions.
[0072] (Technical proposal 4) The semiconductor device according to any one of Technical Proposals 1 to 3, wherein the sixth semiconductor region pitch of the plurality of sixth semiconductor regions is 3 times or more and 2000 times or less the third electrode pitch of the plurality of third electrodes.
[0073] (Technical proposal 5) The plurality of third electrodes are arranged along a second direction intersecting the first direction, The plurality of third electrodes extend along a third direction that intersects the first and second directions, The fourth electrode extends along the third direction, as described in any one of the technical proposals 1 to 3.
[0074] (Technical proposal 6) Multiple of the fourth electrodes are provided, The semiconductor device according to Technical Proposal 1 or 2, wherein the fourth electrode pitch of the plurality of fourth electrodes is 1 to 2000 times the third electrode pitch of the plurality of third electrodes.
[0075] (Technical proposal 7) Multiple of the fourth electrodes are provided, The semiconductor device according to Technical Proposal 3, wherein the fourth electrode pitch of the plurality of fourth electrodes is 0.0005 times or more and 10 times or less the sixth semiconductor region pitch of the plurality of sixth semiconductor regions.
[0076] (Technical proposal 8) The semiconductor device according to any one of Technical Proposals 1 to 7, wherein the concentration of the fourth impurity of the second conductivity type in the fourth semiconductor region is 0.1 times or more and 1000 times or less the concentration of the sixth impurity of the second conductivity type in the sixth semiconductor region.
[0077] (Technical proposal 9) The semiconductor device according to any one of Technical Proposals 1 to 8, wherein the concentration of the fifth impurity of the first conductivity type in the fifth semiconductor region is 0.001 times or more and 10 times or less the concentration of the seventh impurity of the first conductivity type in the seventh semiconductor region.
[0078] (Technical proposal 10) The semiconductor device according to any one of Technical Proposals 1 to 9, wherein the sixth semiconductor region and the seventh semiconductor region are arranged alternately in a direction intersecting the first direction.
[0079] (Technical proposal 11) The semiconductor device according to any one of Technical Proposals 1 to 3, wherein the direction in which the fourth electrode extends intersects with the direction in which the plurality of third electrodes extend.
[0080] (Technical proposal 12) Each of the first semiconductor portion and the second semiconductor portion further includes an eighth semiconductor region of the first conductivity type, The fourth semiconductor region is located between the first electrode portion and a part of the eighth semiconductor region. The semiconductor device according to any one of Technical Proposals 1 to 11, wherein the sixth semiconductor region and the seventh semiconductor region are located between the second electrode portion and another part of the eighth semiconductor region.
[0081] (Technical proposal 13) Further equipped with a sixth electrode, The sixth electrode is located between one of the plurality of third electrodes and another of the plurality of third electrodes. A portion of the first insulating member is in contact with a portion of the plurality of third electrodes and the third semiconductor region. The semiconductor device according to any one of Technical Proposals 1 to 12, wherein the first insulating member is located between the sixth electrode and the third semiconductor region and does not come into contact with the third semiconductor region.
[0082] (Technical proposal 14) It further includes a control unit, The control unit is configured to move the plurality of third electrodes from a first potential to a second potential higher than the first potential at a first time step. The control unit is configured to move the plurality of third electrodes from the second potential to the first potential at a second time after the first time, The control unit is configured to move the plurality of third electrodes from the first potential to the second potential at a third time after the second time, The control unit is configured to move the plurality of third electrodes from the second potential to the first potential at a fourth time after the third time, The control unit is configured to move the plurality of third electrodes from the first potential to the second potential at a fifth time after the fourth time, The control unit is configured to set the fourth electrode to the third potential at the first time interval. The control unit is configured to move the fourth electrode from the third potential to a fourth potential higher than the third potential at a sixth time between the first time and the second time. The control unit is configured to move the fourth electrode from the fourth potential to the third potential at the seventh time between the sixth time and the third time, The control unit is configured to move the fourth electrode from the third potential to the fourth potential at the eighth time between the seventh time and the third time, The semiconductor device according to any one of the technical proposals 1 to 13, wherein the control unit is configured to move the fourth electrode from the fourth potential to the third potential at a ninth time after the fourth time.
[0083] (Technical proposal 15) Further equipped with a fifth electrode, The fifth electrode is located between one of the plurality of third electrodes and another of the plurality of third electrodes. A part of the first insulating member is provided between the fifth electrode and the semiconductor member, as described in any one of Technical Proposals 1 to 12, in the semiconductor device described in Technical Proposal 1 to 12.
[0084] (Technical proposal 16) It further includes a control unit, The control unit is configured to move the plurality of third electrodes from a first potential to a second potential higher than the first potential at a first time step. The control unit is configured to move the plurality of third electrodes from the second potential to the first potential at a second time after the first time, The control unit is configured to move the plurality of third electrodes from the first potential to the second potential at a third time after the second time, The control unit is configured to move the plurality of third electrodes from the second potential to the first potential at a fourth time after the third time, The control unit is configured to move the plurality of third electrodes from the first potential to the second potential at a fifth time after the fourth time, The control unit is configured to set the fourth electrode to the third potential at the first time interval. The control unit is configured to move the fourth electrode from the third potential to a fourth potential higher than the third potential at a sixth time between the first time and the second time. The control unit is configured to move the fourth electrode from the fourth potential to the third potential at the seventh time between the sixth time and the third time, The control unit is configured to move the fourth electrode from the third potential to the fourth potential at the eighth time between the seventh time and the third time, The control unit is configured to move the fourth electrode from the fourth potential to the third potential at the ninth time after the fourth time, The control unit is configured to move the fifth electrode from the fifth potential to a sixth potential that is higher than the fifth potential at the first time step. The control unit is configured to move the fifth electrode from the sixth potential to the fifth potential at the sixth time step, The semiconductor device according to Technical Proposal 15, wherein the control unit is configured to move the fifth electrode from the fifth potential to the sixth potential at the ninth time.
[0085] (Technical proposal 17) The semiconductor device according to Technical Proposal 16, wherein the control unit is configured to keep the fifth electrode at the fifth potential between the sixth time and the ninth time.
[0086] (Technical proposal 18) The semiconductor device according to any one of Technical Proposals 1 to 17, wherein the first electrode portion is provided between a part of the second electrode portion and another part of the second electrode portion in a direction intersecting the first direction.
[0087] (Technical proposal 19) The semiconductor device according to any one of Technical Proposals 1 to 18, wherein the first semiconductor portion is provided between a part of the second semiconductor portion and another part of the second semiconductor portion in a direction intersecting the first direction.
[0088] (Technical proposal 20) Multiple first electrode portions are provided, A semiconductor device according to any one of the technical proposals 1 to 17, wherein one of the plurality of first electrode portions is located between a portion of the second electrode portion and another portion of the second electrode portion.
[0089] According to the embodiment, a semiconductor device capable of improving characteristics is provided.
[0090] Embodiments of the present invention have been described above with reference to examples. However, the present invention is not limited to these examples. For example, the specific configuration of each element included in a semiconductor device, such as electrodes, semiconductor members, semiconductor regions, and insulating members, is included within the scope of the present invention as long as those skilled in the art can appropriately select from the known range to implement the present invention and obtain similar effects.
[0091] Combinations of two or more elements from each example, to the extent technically feasible, are also included within the scope of the present invention, insofar as they encompass the gist of the invention.
[0092] All semiconductor devices that a person skilled in the art can implement by appropriately modifying the design based on the semiconductor device described above as an embodiment of the present invention also fall within the scope of the present invention, insofar as they encompass the gist of the present invention.
[0093] Within the scope of the concept of this invention, a person skilled in the art would be able to conceive of various modifications and alterations, and it is understood that such modifications and alterations also fall within the scope of this invention.
[0094] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]
[0095] 10M: Semiconductor material, 10a, 10b: First and second semiconductor portions, 11-18: First to eighth semiconductor regions, 41-43: First to third insulating materials, 51-56: First to sixth electrodes, 51a, 51b: First and second electrode portions, 70: Control unit, 70a, 70b: First and second circuits, 110, 111: Semiconductor device, D1-D3: First to third directions, V1-V6: First to sixth potentials, t4-t7: Fourth to seventh thicknesses, tm: Time, tm1-tm9: First to ninth time points
Claims
1. A first electrode including a first electrode portion and a second electrode portion, The second electrode and Multiple third electrodes, The fourth electrode and A semiconductor member including a first semiconductor portion and a second semiconductor portion, First insulating member and The second insulating member, Equipped with, The first semiconductor portion is located between the first electrode portion and the second electrode in a first direction from the first electrode to the second electrode, The second semiconductor portion is located between the second electrode portion and the second electrode in the first direction. The direction from the first electrode portion to the second electrode portion intersects with the first direction. Each of the first semiconductor portion and the second semiconductor portion is: The first semiconductor region of the first conductivity type, The second semiconductor region of the second conductivity type, The third semiconductor region of the first conductivity type, Includes, The second electrode is electrically connected to the third semiconductor region. The second semiconductor region is located between the first semiconductor region and the third semiconductor region. At least a portion of the first insulating member is provided between the plurality of third electrodes and the semiconductor member, The first semiconductor portion is The fourth semiconductor region of the second conductivity type, The fifth semiconductor region of the first conductivity type, Includes, The fourth electrode is located between the first electrode portion and the first semiconductor portion. The fifth semiconductor region is electrically connected to the first electrode portion. The fourth semiconductor region is located between the fifth semiconductor region and the first semiconductor region included in the first semiconductor portion. The second insulating member is located between the fourth electrode and the first semiconductor portion. The second semiconductor portion is The sixth semiconductor region of the second conductivity type, The seventh semiconductor region of the first conductivity type, Includes, The sixth semiconductor region and the seventh semiconductor region are semiconductor devices located between the second electrode portion and the first semiconductor region included in the second semiconductor portion.
2. The semiconductor device according to claim 1, wherein the direction from the sixth semiconductor region to the seventh semiconductor region intersects with the first direction.
3. The second semiconductor portion includes a plurality of the sixth semiconductor regions and a plurality of the seventh semiconductor regions. One of the plurality of sixth semiconductor regions is located between one of the plurality of seventh semiconductor regions and another of the plurality of seventh semiconductor regions. The semiconductor device according to claim 2, wherein one of the plurality of seventh semiconductor regions is located between one of the plurality of sixth semiconductor regions and another of the plurality of sixth semiconductor regions.
4. The semiconductor device according to any one of claims 1 to 3, wherein the sixth semiconductor region pitch of the plurality of sixth semiconductor regions is 3 times or more and 2000 times or less the third electrode pitch of the plurality of third electrodes.
5. The plurality of third electrodes are arranged along a second direction intersecting the first direction, The plurality of third electrodes extend along a third direction that intersects the first and second directions, The semiconductor device according to any one of claims 1 to 3, wherein the fourth electrode extends along the third direction.
6. Multiple fourth electrodes are provided, The semiconductor device according to claim 1 or 2, wherein the fourth electrode pitch of the plurality of fourth electrodes is 1 to 2000 times the third electrode pitch of the plurality of third electrodes.
7. Multiple fourth electrodes are provided, The semiconductor device according to claim 3, wherein the fourth electrode pitch of the plurality of fourth electrodes is 0.0005 times or more and 10 times or less the sixth semiconductor region pitch of the plurality of sixth semiconductor regions.
8. The semiconductor device according to any one of claims 1 to 3, wherein the concentration of the fourth impurity of the second conductivity type in the fourth semiconductor region is 0.1 times or more and 1000 times or less the concentration of the sixth impurity of the second conductivity type in the sixth semiconductor region.
9. The semiconductor device according to any one of claims 1 to 3, wherein the concentration of the fifth impurity of the first conductivity type in the fifth semiconductor region is 0.001 times or more and 10 times or less the concentration of the seventh impurity of the first conductivity type in the seventh semiconductor region.
10. The semiconductor device according to any one of claims 1 to 3, wherein the sixth semiconductor region and the seventh semiconductor region are arranged alternately in a direction intersecting the first direction.
11. The semiconductor device according to any one of claims 1 to 3, wherein the direction in which the fourth electrode extends intersects with the direction in which the plurality of third electrodes extend.
12. Each of the first semiconductor portion and the second semiconductor portion further includes an eighth semiconductor region of the first conductivity type, The fourth semiconductor region is located between the first electrode portion and a part of the eighth semiconductor region. The semiconductor device according to any one of claims 1 to 3, wherein the sixth semiconductor region and the seventh semiconductor region are located between the second electrode portion and another part of the eighth semiconductor region.
13. Further equipped with a sixth electrode, The sixth electrode is located between one of the plurality of third electrodes and another of the plurality of third electrodes. A portion of the first insulating member is in contact with a portion of the plurality of third electrodes and the third semiconductor region. The semiconductor device according to any one of claims 1 to 3, wherein the first insulating member is located between the sixth electrode and the third semiconductor region and does not come into contact with the third semiconductor region.
14. It further includes a control unit, The control unit is configured to move the plurality of third electrodes from a first potential to a second potential higher than the first potential at a first time step. The control unit is configured to move the plurality of third electrodes from the second potential to the first potential at a second time after the first time, The control unit is configured to move the plurality of third electrodes from the first potential to the second potential at a third time after the second time, The control unit is configured to move the plurality of third electrodes from the second potential to the first potential at a fourth time after the third time, The control unit is configured to move the plurality of third electrodes from the first potential to the second potential at a fifth time after the fourth time, The control unit is configured to set the fourth electrode to the third potential at the first time interval. The control unit is configured to move the fourth electrode from the third potential to a fourth potential higher than the third potential at a sixth time between the first time and the second time. The control unit is configured to move the fourth electrode from the fourth potential to the third potential at the seventh time between the sixth time and the third time, The control unit is configured to move the fourth electrode from the third potential to the fourth potential at the eighth time between the seventh time and the third time, The semiconductor device according to any one of claims 1 to 3, wherein the control unit is configured to move the fourth electrode from the fourth potential to the third potential at a ninth time after the fourth time.
15. Further equipped with a fifth electrode, The fifth electrode is located between one of the plurality of third electrodes and another of the plurality of third electrodes. A part of the first insulating member is provided between the fifth electrode and the semiconductor member, as described in any one of claims 1 to 3.
16. It further includes a control unit, The control unit is configured to move the plurality of third electrodes from a first potential to a second potential higher than the first potential at a first time step. The control unit is configured to move the plurality of third electrodes from the second potential to the first potential at a second time after the first time, The control unit is configured to move the plurality of third electrodes from the first potential to the second potential at a third time after the second time, The control unit is configured to move the plurality of third electrodes from the second potential to the first potential at a fourth time after the third time, The control unit is configured to move the plurality of third electrodes from the first potential to the second potential at a fifth time after the fourth time, The control unit is configured to set the fourth electrode to the third potential at the first time interval. The control unit is configured to move the fourth electrode from the third potential to a fourth potential higher than the third potential at a sixth time between the first time and the second time. The control unit is configured to move the fourth electrode from the fourth potential to the third potential at the seventh time between the sixth time and the third time, The control unit is configured to move the fourth electrode from the third potential to the fourth potential at the eighth time between the seventh time and the third time, The control unit is configured to move the fourth electrode from the fourth potential to the third potential at the ninth time after the fourth time, The control unit is configured to move the fifth electrode from the fifth potential to a sixth potential that is higher than the fifth potential at the first time step. The control unit is configured to move the fifth electrode from the sixth potential to the fifth potential at the sixth time step, The semiconductor device according to claim 15, wherein the control unit is configured to move the fifth electrode from the fifth potential to the sixth potential at the ninth time.
17. The semiconductor device according to claim 16, wherein the control unit is configured to keep the fifth electrode at the fifth potential between the sixth time and the ninth time.
18. The semiconductor device according to any one of claims 1 to 3, wherein the first electrode portion is provided between a part of the second electrode portion and another part of the second electrode portion in a direction intersecting the first direction.
19. The semiconductor device according to any one of claims 1 to 3, wherein the first semiconductor portion is provided between a part of the second semiconductor portion and another part of the second semiconductor portion in a direction intersecting the first direction.
20. Multiple first electrode portions are provided, The semiconductor device according to any one of claims 1 to 3, wherein one of the plurality of first electrode portions is located between a part of the second electrode portion and another part of the second electrode portion.