Indication device

Abstract

To provide a display device that can improve the fixing force of light-emitting elements. [Solution] An embodiment of the present specification includes a substrate containing a plurality of subpixels, a first assembly wiring 121 and a second assembly wiring 122 arranged on the substrate among the plurality of subpixels and spaced apart from each other, a first upper planarization layer disposed on the first and second assembly wirings and having an opening 118a that overlaps with the first and second assembly wirings, a light-emitting element disposed in the opening and including a first electrode 134, a first semiconductor layer 131, a light-emitting layer 132, a second semiconductor layer 133, and a second electrode 135, a contact electrode CE that electrically connects the first and second assembly wirings to the first electrode, and an organic insulating layer OL disposed on the first upper planarization layer and covering a portion of the side and top surfaces of the light-emitting element. Accordingly, the fixing force of the light-emitting element can be improved.

Description

Technical Field

[0001] This specification relates to a display device, and more particularly to a display device using LEDs (Light Emitting Diodes).

Background Art

[0002] Display devices used in computer monitors, TVs, mobile phones, etc. include organic light emitting display devices (OLEDs) that emit light by themselves, and liquid crystal display devices (LCDs) that require a separate light source.

[0003] The application range of display devices is diverse, not only for computer monitors and TVs, but also for personal mobile devices. Research is underway on display devices that have a large display area while having a reduced volume and weight.

[0004] In recent years, display devices including LEDs have attracted attention as next-generation display devices. Since LEDs are made of inorganic substances rather than organic substances, they have excellent reliability and a longer lifespan compared to liquid crystal display devices and organic light emitting display devices. In addition, LEDs not only have a fast lighting speed, but also have excellent luminous efficiency, strong impact resistance, excellent stability, and can display high-brightness images.

Summary of the Invention

Problems to be Solved by the Invention

[0005] The problem to be solved by this specification is to provide a display device capable of improving the fixing force of a light emitting element.

[0006] Another problem to be solved by this specification is to provide a display device with improved manufacturing process efficiency.

[0007] The problems described herein are not limited to those mentioned above, and other problems not mentioned can be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0008] A display device according to one embodiment of this specification includes a substrate containing a plurality of subpixels, a first assembly wiring and a second assembly wiring arranged on the substrate with respect to the plurality of subpixels and spaced apart from each other, a first upper planarization layer disposed on the first and second assembly wirings and having an opening that overlaps with the first and second assembly wirings, a light-emitting element disposed in the opening and including a first electrode, a first semiconductor layer, a light-emitting layer, a second semiconductor layer, and a second electrode, a contact electrode that electrically connects the first and second assembly wirings to the first electrode, and an organic insulating layer disposed on the first upper planarization layer and covering a portion of the side and top surfaces of the light-emitting element. Accordingly, the fixing force of the light-emitting element can be improved.

[0009] Specific details of other embodiments are included in the detailed description and drawings.

[0010] This specification describes how to minimize the fluidity of the light-emitting element after self-assembly and improve the fixing force of the light-emitting element.

[0011] This specification can improve the efficiency of the bonding process for light-emitting elements.

[0012] The effects described herein are not limited to those exemplified above, and a wider variety of effects are included within this specification. [Brief explanation of the drawing]

[0013] [Figure 1] This is a schematic diagram of a display device according to one embodiment of this specification. [Figure 2] This is an enlarged plan view of a display device according to one embodiment of this specification. [Figure 3] This is a magnified plan view of region X in Figure 2. [Figure 4a] These are cross-sectional views along lines A-A' in Figure 2 and B-B' in Figure 3. [Figure 4b] This is a cross-sectional view along line C-C' in Figure 3. [Figure 4c] This is a cross-sectional view along line D-D' in Figure 3. [Figure 5a] This is a process diagram illustrating the formation process of a display device according to one embodiment of this specification. [Figure 5b] This is a process diagram illustrating the formation process of a display device according to one embodiment of this specification. [Figure 5c] This is a process diagram illustrating the formation process of a display device according to one embodiment of this specification. [Figure 5d] This is a process diagram illustrating the formation process of a display device according to one embodiment of this specification. [Figure 5e] This is a process diagram illustrating the formation process of a display device according to one embodiment of this specification. [Figure 5f] This is a process diagram illustrating the formation process of a display device according to one embodiment of this specification. [Figure 6] This is an enlarged plan view of a display device according to another embodiment of this specification. [Figure 7] This is an enlarged plan view of a display device according to yet another embodiment of this specification. [Figure 8] This is an enlarged plan view of a display device according to yet another embodiment of this specification. [Figure 9a] This is an enlarged plan view of a display device according to yet another embodiment of this specification. [Figure 9b] This is a cross-sectional view along line E-E' in Figure 9a. [Modes for carrying out the invention]

[0014] The advantages and features of this specification, and the methods for achieving them, will become clear by referring to the embodiments described in detail below together with the accompanying drawings. However, this specification is not limited to the embodiments disclosed below, but can be embodied in various different forms. Merely, these embodiments are provided so that the disclosure of this specification is complete and to fully inform those with ordinary knowledge in the technical field to which this specification pertains of the scope of the invention.

[0015] The shapes, dimensions (e.g., length, width, height, thickness, radius, diameter, area), ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of this specification are exemplary, so this specification is not limited to the matters illustrated. The dimensions including the size and thickness of each component shown in the drawings are shown for convenience of explanation, and the present invention is not limited to the size and thickness of the components shown. The relative sizes, positions, and thicknesses of the components illustrated in the drawings are part of the present disclosure. Throughout the specification, the same reference numerals refer to the same components. Also, when explaining this specification, if it is determined that a specific explanation of related known technologies may obscure the gist of this specification, the detailed explanation thereof will be omitted. When terms such as "including", "having", "being made" as mentioned in this specification are used, other parts can be added as long as "only" is not used. When a component is expressed in the singular, it includes the case of including a plurality unless otherwise explicitly stated.

[0016] When interpreting a component, it is interpreted as including an error range even without separate explicit description.

[0017] When it is an explanation of the positional relationship, for example, when the positional relationship between two parts is described such as "on ~", "above ~", "below ~", "next to ~", etc., as long as "immediately" or "directly" is not used, one or more other parts may be located between the two parts.

[0018] When an element or layer is referred to as "on" another element or layer, this includes cases where another layer or other element is interposed immediately above or between the other element.

[0019] Furthermore, while terms such as "first," "second," etc., are used to describe a variety of components, these components are not limited by these terms. These terms are simply used to distinguish one component from another. Therefore, the first component referred to below may also be the second component within the technical concept of this specification.

[0020] Throughout the specification, the same reference numeral refers to the same component.

[0021] The area and thickness of each component shown in the drawings are provided for illustrative purposes only, and this specification is not necessarily limited to the area and thickness of the components shown.

[0022] The features of each of the various embodiments described herein can be combined or linked together, either partially or entirely, allowing for a variety of technically diverse interoperability and drive, and each embodiment may be implemented independently of the others or together in relation to one another.

[0023] In the following sections, various embodiments of this specification will be described in detail with reference to the attached drawings.

[0024] Figure 1 is a schematic plan view of a display device according to one embodiment of this specification.

[0025] In Figure 1, for the sake of explanation, only the display panel PN, gate drive unit GD, data drive unit DD, and timing controller TC are shown among the various components of the display device 100.

[0026] Referring to Figure 1, the display device 100 includes a display panel PN containing a plurality of subpixels SP, a gate drive unit GD and a data drive unit DD that supply various signals to the display panel PN, and a timing controller TC that controls the gate drive unit GD and the data drive unit DD.

[0027] The display panel PN is a configuration for displaying images to the user and includes multiple sub-pixels SP. Multiple scan lines SL and multiple data lines DL intersect each other in the display panel PN, and each of the multiple sub-pixels SP is connected to the scan lines SL and data lines DL. In addition, each of the multiple sub-pixels SP may be connected to high-potential power lines VDD, low-potential power lines, reference lines RL, etc.

[0028] Multiple subpixels SP are the smallest units that make up the screen, and each of the multiple subpixels SP includes a light-emitting element and a pixel circuit for driving it. Multiple light-emitting elements can be defined differently depending on the type of display panel PN. For example, if the display panel PN is an inorganic light-emitting display panel, the light-emitting elements may be LEDs (Light-emitting Diodes) or micro-LEDs (Micro Light-emitting Diodes).

[0029] The gate drive unit GD supplies multiple scan signals SCAN to multiple scan wirings SL using multiple gate control signals GCS provided by the timing controller TC. In Figure 1, one gate drive unit GD is shown spaced apart on one side of the display panel PN, but the number and arrangement of gate drive units GD are not limited to this.

[0030] The data drive unit DD converts the video data RGB input from the timing controller TC into a data voltage Vdata using a reference gamma voltage, based on multiple data control signals DCS provided by the timing controller TC. The data drive unit DD can then supply the converted data voltage Vdata to multiple data lines DL.

[0031] The timing controller TC aligns the externally input video data RGB and supplies it to the data drive unit DD. The timing controller TC can generate a gate control signal GCS and a data control signal DCS using externally input synchronization signals, such as a dot clock signal, a data enable signal, and horizontal / vertical synchronization signals. The timing controller TC can then control the gate drive unit GD and the data drive unit DD by supplying the generated gate control signal GCS and data control signal DCS to them, respectively.

[0032] In the following, Figures 2 to 4 will be referenced together for a more detailed explanation of the display panel PN of the display device 100.

[0033] Figure 2 is an enlarged plan view of a display device according to one embodiment of this specification. Figure 3 is an enlarged plan view of region X in Figure 2. Figure 4a is a cross-sectional view along A-A' in Figure 2 and B-B' in Figure 3. Figure 4b is a cross-sectional view along C-C' in Figure 3. Figure 4c is a cross-sectional view along D-D' in Figure 3. Referring to Figure 2, each of the multiple sub-pixels SP includes a first transistor T1, a second transistor T2, a third transistor T3, a storage capacitor Cst, and one or more light-emitting elements LEDs. In Figure 2, for the sake of simplicity, the hatching of the assembly wiring 120 and the light-emitting elements LEDs is omitted, the contact electrodes CE are not shown, and the organic insulating layer OL is not shown. In Figure 3, the pixel electrodes PE are not shown.

[0034] Referring to Figure 2, the display device 100 includes a plurality of subpixels SP, which include a first subpixel SP1 arranged in a first column so as to be repeated in the row direction, a second subpixel SP2 arranged in a second column, and a third subpixel SP3 arranged in a third column.

[0035] Each of the first subpixel SP1, second subpixel SP2, and third subpixel SP3 includes a light-emitting element (LED) and a pixel circuit, and can independently emit light. For example, the first subpixel SP1 may be a red subpixel, the second subpixel SP2 a green subpixel, and the third subpixel SP3 a blue subpixel, but is not limited to this. The pixel circuit may also include a first transistor T1, a second transistor T2, a third transistor T3, and a storage capacitor Cst.

[0036] The display panel PN includes a substrate 110, a buffer layer 111, a gate insulating layer 112, an interlayer insulating layer 113, a first passivation layer 114, a lower planarization layer 115, a second passivation layer 116, a third passivation layer 117, a first upper planarization layer 118, an organic insulating layer OL, and a second upper planarization layer 119.

[0037] The substrate 110 is a structure for supporting the various components included in the display panel PN, and may be made of an insulating material. For example, the substrate 110 may be made of glass or resin. The substrate 110 may also contain polymers or plastics, and may be made of a flexible material.

[0038] High-potential power supply wiring VDD, multiple data wiring DL, reference wiring RL, assembly wiring 120, light-shielding layer LS, and first capacitor electrode SC1 are arranged on the substrate 110.

[0039] The high-potential power supply wiring VDD is wiring that transmits a high-potential power supply voltage to each of multiple sub-pixels SP. Multiple high-potential power supply wirings VDD can transmit the high-potential power supply voltage to the second transistor T2 of each of the multiple sub-pixels SP. The high-potential power supply wiring VDD can extend along the column direction between multiple sub-pixels SP. For example, the high-potential power supply wiring VDD can be arranged along the column direction between the first sub-pixel SP1 and the third sub-pixel SP3. The high-potential power supply wiring VDD can then transmit the high-potential power supply voltage to each of the multiple sub-pixels SP arranged in the row direction through the auxiliary high-potential power supply wiring VDDA, which will be described later. In this case, the high-potential power supply wiring VDD can be referred to as the first power supply wiring. The column direction can be referred to as the first direction, and the row direction as the second direction.

[0040] Multiple data paths DL are paths that transmit a data voltage Vdata to each of multiple subpixels SP. Multiple data paths DL can be connected to the first transistor T1 of each of the multiple subpixels SP. Multiple data paths DL can extend along the column direction between the multiple subpixels SP. For example, a data path DL extending along the column direction between the first subpixel SP1 and the high-potential power supply path VDD can transmit the data voltage Vdata to the first subpixel SP1, a data path DL placed between the first subpixel SP1 and the second subpixel SP2 can transmit the data voltage Vdata to the second subpixel SP2, and a data path DL placed between the third subpixel SP3 and the high-potential power supply path VDD can transmit the data voltage Vdata to the third subpixel SP3.

[0041] The reference wiring RL is a wiring that transmits a reference voltage to each of the multiple sub-pixels SP. The reference wiring RL can be connected to the third transistor T3 of each of the multiple sub-pixels SP. The reference wiring RL can extend along the column direction between the multiple sub-pixels SP. For example, the reference wiring RL can extend along the column direction between the second sub-pixel SP2 and the third sub-pixel SP3. The third drain electrode DE3 of the third transistor T3 of the first sub-pixel SP1, second sub-pixel SP2, and third sub-pixel SP3 adjacent to the reference wiring RL can extend along the row direction and be electrically connected to the reference wiring RL. In this case, the reference wiring RL can be referred to as the third power supply wiring.

[0042] A light-shielding layer LS is placed on the substrate 110 for each of the multiple subpixels SP. The light-shielding layer LS can block light incident on the transistor below the substrate 110, thereby minimizing leakage current. For example, the light-shielding layer LS can block light incident on the second active layer ACT2 of the second transistor T2, which is a driving transistor.

[0043] A first capacitor electrode SC1 is placed on the substrate 110 for each of the multiple subpixels SP. The first capacitor electrode SC1 can form a storage capacitor Cst together with other capacitor electrodes. The first capacitor electrode SC1 can be formed integrally with the light-shielding layer LS.

[0044] A buffer layer 111 is placed on the high-potential power supply wiring VDD, multiple data wiring DL, reference wiring RL, light-shielding layer LS, and first capacitor electrode SC1. The buffer layer 111 can reduce the penetration of moisture or impurities through the substrate 110. The buffer layer 111 may, but is not limited to, a single or multi-layer structure of silicon oxide (SiOx) or silicon nitride (SiNx). However, the buffer layer 111 may, but is not limited to, be omitted depending on the type of substrate 110 or the type of transistor.

[0045] First, a first transistor T1 is placed on the buffer layer 111 for each of the multiple subpixels SP. The first transistor T1 is a transistor that transmits the data voltage Vdata to the second gate electrode GE2 of the second transistor T2. The first transistor T1 can be turned on by a scan signal from the scan wiring SL, and the data voltage Vdata from the data wiring DL can be transmitted from the turned-on first transistor T1 to the second gate electrode GE2 of the second transistor T2. Therefore, the first transistor T1 can be called a switching transistor.

[0046] The first transistor T1 includes a first active layer ACT1, a first gate electrode GE1, a first source electrode SE1, and a first drain electrode DE1.

[0047] A first active layer ACT1 is placed on the buffer layer 111. The first active layer ACT1 may, but is not limited to, a semiconductor material such as an oxide semiconductor, amorphous silicon, or polysilicon.

[0048] A gate insulating layer 112 is disposed on the first active layer ACT1. The gate insulating layer 112 is an insulating layer for insulating the first active layer ACT1 from the first gate electrode GE1, and may, but is not limited to, a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx).

[0049] A first gate electrode GE1 is positioned on the gate insulating layer 112. The first gate electrode GE1 can be electrically connected to the scan wiring SL. The first gate electrode GE1 may be composed of a conductive material, such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

[0050] An interlayer insulating layer 113 is placed on the first gate electrode GE1. Contact holes are formed in the interlayer insulating layer 113 for the first source electrode SE1 and the first drain electrode DE1 to connect to the first active layer ACT1, respectively. The interlayer insulating layer 113 is an insulating layer for protecting the structure below the interlayer insulating layer 113 and may, but is not limited to, a single or multiple layer of silicon oxide (SiOx) or silicon nitride (SiNx).

[0051] A first source electrode SE1 and a first drain electrode DE1 are arranged on the interlayer insulating layer 113, electrically connected to the first active layer ACT1. The first drain electrode DE1 may be connected to the data wiring DL and the first active layer ACT1, and the first source electrode SE1 may be connected to the first active layer ACT1 and the second gate electrode GE2 of the second transistor T2. The first source electrode SE1 and the first drain electrode DE1 may be composed of a conductive material, such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or alloys thereof, but are not limited thereto.

[0052] A second transistor T2 is placed on the buffer layer 111 in each of the multiple subpixels SP. The second transistor T2 is a transistor that supplies drive current to the light-emitting element LED. The second transistor T2 can control the drive current that flows to the light-emitting element LED when it is turned on. Therefore, the second transistor T2 that controls the drive current can be called a drive transistor.

[0053] The second transistor T2 includes a second active layer ACT2, a second gate electrode GE2, a second source electrode SE2, and a second drain electrode DE2.

[0054] A second active layer ACT2 is placed on the buffer layer 111. The second active layer ACT2 may, but is not limited to, a semiconductor material such as an oxide semiconductor, amorphous silicon, or polysilicon.

[0055] A gate insulating layer 112 is placed on the second active layer ACT2, and a second gate electrode GE2 is placed on the gate insulating layer 112. The second gate electrode GE2 can be electrically connected to the first source electrode SE1 of the first transistor T1. The second gate electrode GE2 may be composed of a conductive material, such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

[0056] An interlayer insulating layer 113 is disposed on the second gate electrode GE2, and a second source electrode SE2 and a second drain electrode DE2 are disposed on the interlayer insulating layer 113, which are electrically connected to the second active layer ACT2. The second drain electrode DE2 may be electrically connected to the second active layer ACT2 and the high-potential power supply wiring VDD, and the second source electrode SE2 may be electrically connected to the second active layer ACT2 and the light-emitting element LED. The second source electrode SE2 and the second drain electrode DE2 may be composed of a conductive material, such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but are not limited thereto.

[0057] A third transistor T3 is placed on the buffer layer 111 in each of the multiple subpixels SP. The third transistor T3 is a transistor for compensating the threshold voltage of the second transistor T2. The third transistor T3 is connected between the second source electrode SE2 of the second transistor T2 and the reference wiring RL. The third transistor T3 can be turned on and transmit a reference voltage to the second source electrode SE2 of the second transistor T2, thereby sensing the threshold voltage of the second transistor T2. Therefore, the third transistor T3, which senses the characteristics of the second transistor T2, can be called a sensing transistor.

[0058] The third transistor T3 includes a third active layer ACT3, a third gate electrode GE3, a third source electrode SE3, and a third drain electrode DE3.

[0059] A third active layer ACT3 is placed on the buffer layer 111. The third active layer ACT3 may, but is not limited to, a semiconductor material such as an oxide semiconductor, amorphous silicon, or polysilicon.

[0060] A gate insulating layer 112 is placed on the third active layer ACT3, and a third gate electrode GE3 is placed on the gate insulating layer 112. The third gate electrode GE3 can be electrically connected to the scan wiring SL. The third gate electrode GE3 may be composed of a conductive material, such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

[0061] An interlayer insulating layer 113 is disposed on the third gate electrode GE3, and a third source electrode SE3 and a third drain electrode DE3 are disposed on the interlayer insulating layer 113, which are electrically connected to the third active layer ACT3. The third drain electrode DE3 may be electrically connected to the third active layer ACT3 and the reference wiring RL, and the third source electrode SE3 may be electrically connected to the third active layer ACT3 and the second source electrode SE2 of the second transistor T2. The third source electrode SE3 and the third drain electrode DE3 may be composed of a conductive material, such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but are not limited thereto.

[0062] The first transistor T1 and the third transistor T3 shown in Figure 2 are both transistors that are connected to and controlled by the scan wiring SL, but the pixel circuit is not limited to this and may include transistors connected to the light-emitting wiring EL.

[0063] A second capacitor electrode SC2 is placed on the gate insulating layer 112. The second capacitor electrode SC2 is one of the electrodes forming the storage capacitor Cst and may be placed superimposed on the first capacitor electrode SC1. The second capacitor electrode SC2 may be formed integrally with the second gate electrode GE2 of the second transistor T2 and may be electrically connected to the second gate electrode GE2. The first capacitor electrode SC1 and the second capacitor electrode SC2 may be placed separated from each other by the buffer layer 111 and the gate insulating layer 112.

[0064] Then, multiple scan wirings SL, auxiliary high-potential power supply wiring VDDA, and a third capacitor electrode SC3 are arranged on the interlayer insulating layer 113.

[0065] First, the scan wiring SL is a wiring that transmits a scan signal SCAN to each of the multiple subpixels SP. The scan wiring SL may extend in the row direction across the multiple subpixels SP. The scan wiring SL may be electrically connected to the first gate electrode GE1 of the first transistor T1 and the third gate electrode GE3 of the third transistor T3 of each of the multiple subpixels SP.

[0066] An auxiliary high-potential power supply wiring VDDA is placed on the interlayer insulating layer 113. The auxiliary high-potential power supply wiring VDDA may extend in the row direction and be arranged across multiple sub-pixels SP. The auxiliary high-potential power supply wiring VDDA may be electrically connected to the high-potential power supply wiring VDD extending in the column direction and to the second drain electrode DE2 of the second transistor T2 of each of the multiple sub-pixels SP arranged along the row direction.

[0067] A third capacitor electrode SC3 is placed on the interlayer insulating layer 113. The third capacitor electrode SC3 is an electrode that forms a storage capacitor Cst and can be placed superimposed on the first capacitor electrode SC1 and the second capacitor electrode SC2. The third capacitor electrode SC3 is formed integrally with the second source electrode SE2 of the second transistor T2 and can be electrically connected to the second source electrode SE2. The second source electrode SE2 can also be electrically connected to the first capacitor electrode SC1 through contact holes formed in the interlayer insulating layer 113 and the buffer layer 111. Thus, the first capacitor electrode SC1 and the third capacitor electrode SC3 can be electrically connected to the second source electrode SE2 of the second transistor T2.

[0068] The storage capacitor Cst can store the potential difference between the second gate electrode GE2 and the second source electrode SE2 of the second transistor T2 while the light-emitting element LED is emitting light, thereby supplying a constant current to the light-emitting element LED. The storage capacitor Cst is formed on the substrate 110 and includes a first capacitor electrode SC1 connected to the second source electrode SE2, a second capacitor electrode SC2 formed on the buffer layer 111 and gate insulating layer 112 and connected to the second gate electrode GE2, and a third capacitor electrode SC3 formed on the interlayer insulating layer 113 and connected to the second source electrode SE2, and can store the voltage between the second gate electrode GE2 and the second source electrode SE2 of the second transistor T2.

[0069] A first passivation layer 114 is placed on the first transistor T1, the second transistor T2, the third transistor T3, and the storage capacitor Cst. The first passivation layer 114 is an insulating layer for protecting the underlying structure and may, but is not limited to, a single or multiple layer of silicon oxide (SiOx) or silicon nitride (SiNx).

[0070] A lower planarization layer 115 is placed on the first passivation layer 114. The lower planarization layer 115 can planarize the upper part of the substrate 110 on which multiple transistors T1, T2, T3 and storage capacitor Cst are arranged. The lower planarization layer 115 may consist of a single layer or multiple layers, and may, for example, be made of a photoresist or an acrylic-based organic material, but is not limited thereto.

[0071] A second passivation layer 116 is placed on the lower planarization layer 115. The second passivation layer 116 is an insulating layer for protecting the lower structure of the second passivation layer 116 and may consist of a single or multiple layer of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0072] A connecting electrode 150 and multiple assembly wirings 120 are placed on the second passivation layer 116.

[0073] The connecting electrode 150 is an electrode that electrically connects the second transistor T2 and the pixel electrode PE. The connecting electrode 150 can be electrically connected to the second source electrode SE2, which is the third capacitor electrode SC3, through contact holes formed in the second passivation layer 116, the lower planarization layer 115, and the first passivation layer 114.

[0074] The connecting electrode 150 may have a multilayer structure consisting of a first connecting layer 150a and a second connecting layer 150b. The first connecting layer 150a is placed on the second passivation layer 116, and the second connecting layer 150b is placed over the first connecting layer 150a. The second connecting layer 150b may be placed so as to completely surround the top and side surfaces of the first connecting layer 150a.

[0075] The second connecting layer 150b is made of a material that is more corrosion-resistant than the first connecting layer 150a, thereby minimizing short-circuit failures caused by migration between the first connecting layer 150a and adjacent wiring during the manufacturing of the display device 100. For example, the first connecting layer 150a may be made of conductive materials such as copper (Cu) and chromium (Cr), and the second connecting layer 150b may be made of molybdenum (Mo), molybdenum titanium (MoTi), etc., but is not limited to these.

[0076] Multiple assembly wirings 120 are placed on the second passivation layer 116.

[0077] Multiple assembly wiring 120 include multiple first assembly wiring 121 and multiple second assembly wiring 122.

[0078] Multiple first assembly wirings 121 and multiple second assembly wirings 122 may extend in the column direction in the first subpixel SP1, second subpixel SP2, and third subpixel SP3, respectively, and be arranged spaced apart from one another at a certain interval.

[0079] Multiple assembly wirings 120 are arranged in a region that overlaps with the low-potential power supply wiring and can be electrically connected to the low-potential power supply wiring. The low-potential power supply wiring is wiring that transmits a low-potential power supply voltage to the light-emitting element LED. The low-potential power supply wiring may extend in the column direction at each of the multiple sub-pixels SP. For example, low-potential power supply wiring may be provided at each of the first sub-pixel SP1, second sub-pixel SP2, and third sub-pixel SP3.

[0080] Each of the multiple assembled wirings 120 includes conductive layers 121a, 122a placed on the second passivation layer 116, and cladding layers 121b, 122b placed on the conductive layers 121a, 122a and covering the entire top and sides of the conductive layers 121a, 122a.

[0081] The first assembled wiring 121 includes a first conductive layer 121a and a first cladding layer 121b, and the second assembled wiring 122 includes a second conductive layer 122a and a second cladding layer 122b.

[0082] The first conductive layer 121a and the second conductive layer 122a do not need to be superimposed on the light-emitting element LED. That is, the ends of the first conductive layer 121a and the second conductive layer 122a may be positioned outside the ends of the light-emitting element LED.

[0083] The first cladding layer 121b of the first assembly wiring 121 may be arranged to cover the top and side surfaces of the first conductive layer 121a, and the second cladding layer 122b of the second assembly wiring 122 may be arranged to cover the top and side surfaces of the second conductive layer 122a. In this case, the first cladding layer 121b and the second cladding layer 122b may extend from the ends of the first conductive layer 121a and the second conductive layer 122a toward the central part of the light-emitting element LED and overlap with the light-emitting element LED. For example, the first cladding layer 121b and the second cladding layer 122b may each be arranged to overlap a region corresponding to less than half of the area of ​​the bottom surface of the light-emitting element LED.

[0084] The first conductive layer 121a and the second conductive layer 122a may be made of the same material by the same process as the first connecting layer 150a of the connecting electrode 150. For example, the first conductive layer 121a and the second conductive layer 122a may be made of conductive materials such as copper (Cu) and chromium (Cr). The first cladding layer 121b and the second cladding layer 122b may be made of the same material by the same process as the second connecting layer 150b of the connecting electrode 150. For example, the first cladding layer 121b and the second cladding layer 122b may be made of a material that is more corrosion-resistant than the first conductive layer 121a and the second conductive layer 122a, such as molybdenum (Mo) or titanium molybdenum (MoTi), but are not limited to this.

[0085] A third passivation layer 117 is placed on the connecting electrode 150 and the assembly wiring 120. The third passivation layer 117 is an insulating layer for protecting the structure below the third passivation layer 117 and may consist of a single or multiple layer of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0086] The third passivation layer 117 may have some areas open in regions adjacent to the multiple light-emitting LEDs. For example, the third passivation layer 117 may expose a portion of the upper surface of the first assembly wiring 121 and the second assembly wiring 122 in a region adjacent to one side of the multiple light-emitting LEDs.

[0087] A first upper flattening layer 118 is placed on the third passivation layer 117. The first upper flattening layer 118 can flatten the top of the third passivation layer 117. The first upper flattening layer 118 can cover a portion of the first cladding layer 121b of the first assembled wiring 121 and a portion of the first cladding layer 122b of the second assembled wiring 122.

[0088] The first upper flattening layer 118 may consist of a single layer or multiple layers, and may, for example, be made of an acrylic-based organic material, but is not limited thereto.

[0089] On the other hand, the first upper planarization layer 118 includes a plurality of apertures 118a arranged at positions corresponding to each of the plurality of subpixels SP. The plurality of apertures 118a are portions into which a plurality of light-emitting elements LEDs are inserted, and may also be referred to as pockets.

[0090] One opening 118a may be positioned to overlap with portions of the first assembly wiring 121 and the second assembly wiring 122, which are arranged adjacent to each other in a single subpixel SP. That is, portions of the first cladding layer 121b of the first assembly wiring 121 and portions of the first cladding layer 122b of the second assembly wiring 122 may be positioned inside the opening 118a where the first upper planarization layer 118 is not positioned.

[0091] Multiple openings 118a can open up a portion of the third passivation layer 117. For example, as shown in Figures 4a to 4c, the third passivation layer 117 can expose a portion of the upper surface of the first assembly wiring 121 and the second assembly wiring 122 in the area excluding the area where the organic insulating layer OL is placed, through multiple openings 118a.

[0092] Multiple light-emitting LEDs are arranged on the third passivation layer 117 through multiple openings 118a. One or more light-emitting LEDs are arranged in a single subpixel SP. As shown in Figure 2, two light-emitting LEDs may be arranged in a single subpixel SP. A light-emitting LED is an element that emits light in response to an electric current. Light-emitting LEDs can include those that emit red light, green light, blue light, etc., and a variety of hues of light, including white, can be realized by combining these. Furthermore, a variety of hues of light can also be realized by using light-emitting LEDs that emit light of a specific hue and a light conversion member that converts light from the light-emitting LEDs into light of other hues.

[0093] The light-emitting element LED can emit light by receiving a drive current from the second transistor T2. The light-emitting element LED can include red, green, and blue light-emitting elements. For example, the light-emitting element LED placed in the first subpixel SP1 may be a red light-emitting element, the light-emitting element LED placed in the second subpixel SP2 may be a green light-emitting element, and the light-emitting element LED placed in the third subpixel SP3 may be a blue light-emitting element, but is not limited to this.

[0094] In this case, multiple light-emitting LEDs arranged in a single subpixel SP can be connected in parallel. That is, one electrode of each of the multiple light-emitting LEDs can be connected to the source electrode SE2 of the same second transistor T2, and the other electrodes can be connected to the same assembly wiring 120.

[0095] The light-emitting element LED may include a first light-emitting element 130 and a second light-emitting element 140. The light-emitting element LEDs, each located in a plurality of subpixels SP, may be arranged in a column direction. For example, as shown in Figures 2 and 3, the second light-emitting element 140 may be located above the first light-emitting element 130.

[0096] The first light-emitting element 130 can emit light of the same color as the second light-emitting element 140. In this case, since the first light-emitting element 130 and the second light-emitting element 140 are the same type of light-emitting element LED, the size of the first light-emitting element 130 may be the same as the size of the second light-emitting element 140. Here, the size of the light-emitting element LED may refer to, but is not limited to, the area of ​​the bottom surface of the light-emitting element LED, the width in cross-section, the volume, the height, etc.

[0097] In Figures 2 and 4, for the sake of explanation, it is shown that each of the multiple subpixels SP has two light-emitting LEDs, but the number of light-emitting LEDs placed in each of the multiple subpixels SP is not limited to this.

[0098] Referring to Figures 3 to 4c, the light-emitting element 130 includes a first semiconductor layer 131, a light-emitting layer 132, a second semiconductor layer 133, a first electrode 134, a second electrode 135, and a sealing layer 136.

[0099] A first semiconductor layer 131 is placed on a third passivation layer 117, and a second semiconductor layer 133 is placed on the first semiconductor layer 131. The first semiconductor layer 131 and the second semiconductor layer 133 may be layers formed by doping specific materials with n-type and p-type impurities. For example, the first semiconductor layer 131 and the second semiconductor layer 133 may be layers doped with p-type or n-type impurities in materials such as gallium nitride (GaN), indium aluminum phosphide (InAlP), gallium arsenide (GaAs), etc. The p-type impurity may be magnesium (Mg), zinc (Zn), beryllium (Be), etc., and the n-type impurity may be silicon (Si), germanium (Ge), tin (Sn), etc., but is not limited to these.

[0100] A portion of the first semiconductor layer 131 may be positioned to protrude outside the second semiconductor layer 133. The upper surface of the first semiconductor layer 131 may consist of a portion that overlaps with the lower surface of the second semiconductor layer 133 and a portion positioned outside the lower surface of the second semiconductor layer 133. However, the size and shape of the first semiconductor layer 131 and the second semiconductor layer 133 can be varied and are not limited thereto.

[0101] A light-emitting layer 132 is disposed between a first semiconductor layer 131 and a second semiconductor layer 133. The light-emitting layer 132 can emit light by receiving holes and electrons from the first semiconductor layer 131 and the second semiconductor layer 133. The light-emitting layer 132 can be a single layer or a multi-quantum well (MQW) structure, and may be made of, for example, indium gallium nitride (InGaN) or gallium nitride (GaN), but is not limited thereto.

[0102] A first electrode 134 is positioned to surround the bottom and sides of the first semiconductor layer 131. The first electrode 134 is an electrode for electrically connecting the first light-emitting element 130 and the assembly wiring 120. The first electrode 134 may be made of a conductive material, such as a transparent conductive material like ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide), or an opaque conductive material like titanium (Ti), gold (Au), silver (Ag), copper (Cu), or alloys thereof, but is not limited thereto.

[0103] A second electrode 135 is placed on the upper surface of the second semiconductor layer 133. The second electrode 135 is an electrode that electrically connects the pixel electrode PE (described later) and the second semiconductor layer 133. The second electrode 135 may be made of a conductive material, such as a transparent conductive material like ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide), but is not limited thereto.

[0104] A sealing layer 136 is provided that surrounds at least a portion of the first semiconductor layer 131, the light-emitting layer 132, the second semiconductor layer 133, the first electrode 134, and the second electrode 135. The sealing layer 136 is made of an insulating material and can protect the first semiconductor layer 131, the light-emitting layer 132, and the second semiconductor layer 133. The sealing layer 136 may be provided to cover the light-emitting layer 132, a portion of the side surface of the first semiconductor layer 131 adjacent to the light-emitting layer 132, and a portion of the side surface of the second semiconductor layer 133 adjacent to the light-emitting layer 132. The first electrode 134 and the second electrode 135 may be exposed from the sealing layer 136, and the contact electrode CE and pixel electrode PE that are formed thereafter can be electrically connected to the first electrode 134 and the second electrode 135.

[0105] Referring to Figure 4a, the second light-emitting element 140 is positioned on the third passivation layer 117. The second light-emitting element 140 is positioned above the first light-emitting element 130 and is arranged together with the first light-emitting element 130 and the pixel circuit to form a single sub-pixel SP.

[0106] The second light-emitting element 140 includes a first semiconductor layer 141, an emissive layer 142, a second semiconductor layer 143, a first electrode 144, a second electrode 145, and a sealing layer 146. The first semiconductor layer 141, emissive layer 142, second semiconductor layer 143, second electrode 145, and sealing layer 146 of the second light-emitting element 140 may be substantially identical to the first semiconductor layer 131, emissive layer 132, second semiconductor layer 133, second electrode 135, and sealing layer 136 of the first light-emitting element 130. Therefore, redundant explanations are omitted.

[0107] The second light-emitting element 140 can be electrically connected to the first light-emitting element 130 and the pixel electrode PE extending from the pixel circuit through contact holes formed in the organic insulating layer OL and the second upper planarization layer 119. Thus, in a single sub-pixel SP, the first light-emitting element 130 and the second light-emitting element 140 can be electrically connected to the second transistor T2.

[0108] The contact electrode CE is positioned inside the opening 118a. The contact electrode CE is an electrode that electrically connects the first assembly wiring 121 and the second assembly wiring 122, which are positioned inside the opening 118a, to the first electrodes 134 and 144 of the light-emitting LED.

[0109] The contact electrode CE can contact the side surface of the light-emitting element LED in areas other than the region where the first portion OL1 of the organic insulating layer OL is located. For example, the contact electrode CE is located inside the opening 118a and can contact at least a portion of the first electrodes 134 and 144. In this case, the contact electrode CE can contact the first cladding layer 121b of the first assembly wiring 121 and the second cladding layer 121b of the second assembly wiring 121 in the region where the third passivation layer 117 is open, thereby electrically connecting the first assembly wiring 121 and the second assembly wiring 122 with the first electrodes 134 and 144.

[0110] On the other hand, the contact electrode CE may consist of a conductive material, such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0111] An organic insulating layer OL is placed on the first upper flattening layer 118. The organic insulating layer OL is also placed inside the opening 118a and may be in contact with a portion of the multiple light-emitting elements (LEDs). For example, the organic insulating layer OL may cover a portion of the sides and a portion of the top surface of the multiple light-emitting elements (LEDs). In this case, the multiple light-emitting elements (LEDs) can be stably fixed inside the opening 118a by the organic insulating layer OL.

[0112] The organic insulating layer OL may, but is not limited to, acrylic-based organic materials.

[0113] The organic insulating layer OL comprises a first portion OL1, a second portion OL2, and a third portion OL3.

[0114] The first portion OL1 is the portion of the multiple light-emitting LEDs that is in contact with the side surface of the light-emitting LED, among the top, bottom, and side surfaces. Therefore, the first portion OL1 may be the portion located in the opening 118a within the organic insulating layer OL. On the other hand, the first portion OL1 may be located in the portion of the side surface of the light-emitting LED, excluding the portion in contact with the contact electrode CE.

[0115] The first portion OL1 can overlap with either the first assembly wiring 121 or the second assembly wiring 122 within the opening 118a. In this case, the first portion OL1 can be placed on the third passivation layer 117 within the opening 118a and positioned to overlap with the first assembly wiring 121 and the second assembly wiring 122. Referring to Figure 3, the area of ​​the region in which the first portion OL1 overlaps with the first assembly wiring 121 and the area of ​​the region in which the first portion OL1 overlaps with the second assembly wiring 122 may be the same.

[0116] A first portion OL1 of the organic insulating layer OL may extend outward from the opening 118a and be positioned on the first upper planarizing layer 118.

[0117] The second portion OL2 of the organic insulating layer OL is positioned on the upper surface of the multiple light-emitting LEDs, among the upper, lower, and side surfaces of the light-emitting LEDs, and covers a portion of the upper surface of the light-emitting LEDs. Therefore, the side surface of the second portion OL2 may be positioned along a portion of the periphery of the second electrodes 135 and 145.

[0118] The second part OL2 is positioned on the top surface of the multiple light-emitting LEDs, and can be used to fix the light-emitting LEDs in place without them becoming detached. The third part OL3 is the part positioned at the bottom of the multiple light-emitting LEDs, among the top, bottom, and side surfaces.

[0119] The third portion OL3 of the organic insulating layer OL may be placed in the space between the third passivation layer 117 and the light-emitting element LED. Thereafter, the third portion OL3 may be in contact with the underside of the light-emitting element LED. Alternatively, the third portion OL3 may be placed so as to overlap with the third passivation layer 117, which is positioned on the first assembly wiring 121 and the second assembly wiring 122 below a plurality of light-emitting element LEDs. In this case, the third portion OL3 may function as an adhesive layer so that the light-emitting element LED is fixed to the third passivation layer 117.

[0120] The second upper planarization layer 119 is placed on the organic insulating layer OL and on the organic insulating layer opening OLa where the organic insulating layer is not formed. The second upper planarization layer 119 can planarize the upper part of the substrate 110 on the organic insulating layer OL.

[0121] The second upper flattening layer 119 may be composed of a single layer or multiple layers. For example, the second upper flattening layer 119 may be made of an acrylic-based organic material, but is not limited thereto.

[0122] The second upper planarization layer 119 can fill the opening 118a and planarize the upper part of the substrate 110 on which multiple light-emitting elements (LEDs) are arranged. For example, the second upper planarization layer 119 can fill the opening 118a in areas excluding the region where the organic insulating layer OL is arranged. Therefore, the second upper planarization layer 119 can be positioned inside the opening 118a on the contact electrode CE. The planar shape of the second upper planarization layer 119 positioned in the opening 118a may be rectangular, as shown in Figure 3.

[0123] On the other hand, the second upper flattening layer 119 can contact a portion of the side surface and a portion of the top surface of the multiple light-emitting LEDs at the opening 118a. Referring to Figures 4a to 4c, the second upper flattening layer 119 includes contact holes that expose a portion of the top surface of the light-emitting LEDs. Pixel electrodes PE can be placed in the contact holes of the second upper flattening layer 119 and electrically connected to the second electrodes 135 and 145 of the multiple light-emitting LEDs.

[0124] Pixel electrodes PE are placed on the second upper planarization layer 119.

[0125] The pixel electrode PE is an electrode for electrically connecting multiple light-emitting elements (LEDs) to a connecting electrode 150. The pixel electrode PE is electrically connected to the pixel circuit and extends to the first light-emitting element 130 and the second light-emitting element 140. That is, the pixel electrode PE can extend to the first light-emitting element 130 and also be connected to the second light-emitting element 140, and can be electrically connected to the connecting electrode 150 and the second transistor T2 through contact holes formed in the second upper planarization layer 119.

[0126] On the other hand, referring to Figure 4b, the pixel electrode PE can be placed on multiple light-emitting elements (LEDs) in areas where the organic insulating layer OL is not present. In this case, the pixel electrode PE can contact the second electrodes 135 and 145 in areas of the upper surface of the multiple light-emitting elements (LEDs) excluding the area where the second portion OL2 is placed, without forming a separate contact hole in the second portion OL2 of the organic insulating layer OL.

[0127] The pixel electrode PE may be composed of a conductive material, such as a transparent conductive material like ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide), but is not limited thereto.

[0128] The manufacturing method of the display device 100 will be described below with reference to Figures 5a to 5f.

[0129] Figures 5a to 5f are process diagrams illustrating the formation process of a display device according to one embodiment of this specification.

[0130] Referring to Figure 5a, the light-emitting LED can be self-assembled inside the opening 118a using the first and second assembly wiring 121. The first upper planarization layer 118 provides a pocket which is a space into which the light-emitting LED can be fixed, and the light-emitting LED can be fixed on a third passivation layer 117 located inside the opening 118a.

[0131] Next, referring to Figure 5b, an organic insulating layer OL is formed on the front surface of the substrate 110. Specifically, the organic insulating layer OL can be formed on the first upper planarization layer 118 and the light-emitting element LED. The organic insulating layer OL can be formed so as to be in contact with the front surface of the light-emitting element LED inside the opening 118a. Furthermore, while being formed on the front surface of the substrate 110, the organic insulating layer OL can penetrate between the third passivation layer 117 and the light-emitting element LED, becoming a third portion OL3 of the organic insulating layer OL that acts as an adhesive between the third passivation layer 117 and the light-emitting element LED.

[0132] Next, referring to Figure 5c, the organic insulating layer OL is patterned to remove a portion of the organic insulating layer OL located inside the opening 118a. Through the patterning process, a portion of the organic insulating layer OL covering the side surface of the first upper planarization layer 118, the side surface of the light-emitting element LED, and the upper portion of the light-emitting element LED can be removed at the opening 118a. For example, as shown in Figure 3, a rectangular region in the organic insulating layer OL can be removed on a plane through the ashing process. Thus, a portion of the first portion OL1 of the organic insulating layer OL covering the side surface of the light-emitting element LED and a portion of the second portion OL2 covering the upper surface of the light-emitting element LED can be left. In this way, the organic insulating layer OL can fix the light-emitting element LED during subsequent processes and prevent the light-emitting element LED from detaching.

[0133] At this time, a portion of the third passivation layer 117 located below the organic insulating layer OL may be removed together. For example, the third passivation layer 117 may be removed at the opening 118a, excluding the first portion OL1 and the third portion of the organic insulating layer OL. As a result, a portion of the upper surface of the first assembly wiring 121 and a portion of the upper surface of the second assembly wiring 122 may be exposed.

[0134] Next, referring to Figure 5d, a conductive layer CL is formed on the front surface of the substrate 110. Specifically, the conductive layer CL may be formed to cover the first upper planarization layer 118 and the light-emitting element LED. In particular, the conductive layer CL may be formed in contact with the upper surface of the first assembly wiring 121 and the upper surface of the second assembly wiring 121, which are exposed by the third passivation layer 117 inside the opening 118a.

[0135] Next, referring to Figure 5e, a portion of the organic insulating layer OL and the conductive layer CL located on the first upper planarization layer 118 are removed through an etching process. For example, only the conductive layer CL located on the upper surface of the first assembly wiring 121 and the upper surface of the second assembly wiring 121, exposed by the contact hole of the third passivation layer 117 inside the opening 118a, may remain. Thus, a contact electrode CE in contact with the side surface of the first semiconductor layer 131 can be formed.

[0136] Next, referring to Figure 5e, a second upper planarization layer 119 is formed on the front surface of the substrate 110. The second upper planarization layer 119 can fill the area where the first upper planarization layer 118 has been removed. For example, it can be positioned inside the opening 118a, excluding the organic insulating layer OL, and can cover the contact electrode CE and the light-emitting element LED. Thus, inside the opening 118a, the second upper planarization layer 119 can cover the light-emitting element LED together with the organic insulating layer OL.

[0137] Next, referring to Figure 5f, a pixel electrode PE is formed on the second upper planarization layer 119. Specifically, a contact hole is formed in a part of the second upper planarization layer 119 on the light-emitting element LED, so that the pixel electrode PE can be connected to the light-emitting element LED.

[0138] In the manufacturing of a display device using a method in which light-emitting elements are self-assembled inside an opening, multiple light-emitting elements were fixed to the substrate with a bonding layer placed beneath each element. For example, after the self-assembly of multiple light-emitting elements had progressed, an organic layer was coated onto the entire surface of the substrate so that an organic layer could penetrate beneath the light-emitting elements. Subsequently, the organic layer was removed from the remaining area excluding the organic layer located beneath the multiple light-emitting elements, and the multiple light-emitting elements were fixed to the substrate with a bonding layer placed on the organic layer located beneath each element. In such a case, since the bonding layer is placed only on the underside of the light-emitting elements, the fixing force of the light-emitting elements on the substrate was weakened. Therefore, when contact electrodes, a second upper planarization layer, pixel electrodes, etc. are formed on the light-emitting elements after self-assembly inside the opening, the light-emitting elements may not be fixed and may flow, potentially causing the light-emitting elements to detach within the opening or causing contact failures during the process of forming contact electrodes, etc., on the light-emitting elements as they move. Furthermore, since a high-thickness organic layer removal process is carried out to remove all areas of the organic layer placed on the front surface of the substrate excluding the organic layer located beneath the multiple light-emitting elements, the efficiency of the process was reduced.

[0139] In one embodiment of the display device 100 according to this specification, after self-assembling the light-emitting element LED inside the opening 118a on the substrate 110, an organic insulating layer OL for fixing the light-emitting element LED can be formed so as to be in contact with at least the top surface and side surface of the light-emitting element LED. That is, the organic insulating layer OL can fix the light-emitting element LED inside the opening 118a with its top, side, and bottom surfaces. This can improve the fixing force between the light-emitting element LED and the substrate 110, and prevent the light-emitting element LED from becoming detached. Furthermore, it is possible to prevent errors caused by the flow of the light-emitting element LED during the subsequent process of forming contact electrodes CE etc. on the self-assembled light-emitting element LED.

[0140] Furthermore, in the display device 100 according to one embodiment of this specification, the first upper flattening layer 118 and the organic insulating layer OL are also arranged outside the opening 118a. Therefore, the efficiency of the organic layer removal process can be improved by not having to perform the process of removing the first upper flattening layer 118 and the organic insulating layer OL outside the opening 118a.

[0141] Furthermore, in the display device 100 according to one embodiment of this specification, the first upper planarization layer 118 and the organic insulating layer OL extend through the opening 118a to cover the pixel circuit of the sub-pixel SP. Therefore, the organic insulating layer OL can insulate the pixel circuit from other components and prevent the risk of short circuits without the addition of a separate passivation layer.

[0142] Figure 6 is an enlarged plan view of a display device according to another embodiment of this specification. The display device 600 in Figure 6 is substantially identical to the display device 100 in Figures 1 to 5f, except that the contact electrode CE, the organic insulating layer OL, and the second upper planarization layer are different, so redundant explanations are omitted.

[0143] An organic insulating layer OL is placed on the first upper flattening layer 118. The organic insulating layer OL includes a first portion OL1, a second portion OL2, and a third portion.

[0144] The first portion OL1 may be in contact with a portion of the side surface of the light-emitting element LED at the opening 118a. The first portion OL1 may overlap with either the first assembly wiring 121 or the second assembly wiring 122 within the opening 118a. The area of ​​the region on the first light-emitting element 130 where the first portion OL1 overlaps with the first assembly wiring 121 may differ from the area of ​​the region where it overlaps with the second assembly wiring 122. For example, the first portion OL1 may overlap with the entire side surface of the first light-emitting element 130 positioned on the first assembly wiring 121. On the other hand, the first portion OL1 may overlap with a portion of the side surface of the first light-emitting element 130 positioned on the second assembly wiring 122. As shown in Figure 6, the first portion OL1 may be positioned to overlap with half of the side surface of the first light-emitting element 130 positioned on the second assembly wiring 122, but is not limited to this. Also, the first portion OL1 may overlap with a portion of the side surface of the second light-emitting element 140 positioned on the first assembly wiring 121. As shown in Figure 6, the first portion OL1 may, but is not limited to, be positioned to overlap half of the side surface of the second light-emitting element 140, which is positioned on the first assembly wiring 121. Alternatively, the first portion OL1 may completely overlap the side surface of the second light-emitting element 140, which is positioned on the second assembly wiring 122.

[0145] The second portion OL2 is arranged on multiple light-emitting LEDs within the opening 118a. The area of ​​the region on the first light-emitting element 130 in which the second portion OL2 overlaps with the first assembly wiring 121 may differ from the area in which it overlaps with the second assembly wiring 122. For example, the second portion OL2 may completely overlap the upper surface of the first light-emitting element 130 arranged on the first assembly wiring 121. On the other hand, the second portion OL2 may overlap a portion of the upper surface of the first light-emitting element 130 arranged on the second assembly wiring 122. As shown in Figure 6, the second portion OL2 may be arranged to overlap half of the upper surface of the first light-emitting element 130 arranged on the second assembly wiring 122, but is not limited to this. Also, the second portion OL2 may overlap a portion of the upper surface of the second light-emitting element 140 arranged on the first assembly wiring 121. As shown in Figure 6, the second portion OL2 may, but is not limited to, be positioned to overlap half of the upper surface of the second light-emitting element 140, which is positioned on the first assembly wiring 121. Alternatively, the second portion OL2 may completely overlap the upper surface of the second light-emitting element 140, which is positioned on the second assembly wiring 122.

[0146] Although not shown in Figure 6, the third portion is positioned in the space between the third passivation layer 117 and the light-emitting element LED, and may be in contact with the lower surface of the light-emitting element LED.

[0147] The contact electrode CE is positioned inside the opening 118a. The contact electrode CE is positioned in the region excluding the region where the first portion OL1 of the organic insulating layer OL is located. Therefore, the area in contact between the side surface of the light-emitting element LED and the contact electrode CE may be smaller than the area in contact between the side surface of the light-emitting element LED and the first portion OL1.

[0148] Although not shown in Figure 6, the second upper planarization layer is placed on the organic insulating layer OL and in the openings OLa of the organic insulating layer where the organic insulating layer is not formed.

[0149] The second upper planarization layer can fill the opening 118a in the region excluding the region where the organic insulating layer OL is located. Therefore, the second upper planarization layer can be positioned inside the opening 118a on the contact electrode CE.

[0150] The second upper flattening layer may be in contact with a portion of the side surface and a portion of the top surface of the multiple light-emitting LEDs at the opening 118a.

[0151] The second upper planarization layer includes contact holes that expose a portion of the upper surface of the light-emitting LED. Pixel electrodes PE are placed in the contact holes of the second upper planarization layer 119 and can be electrically connected to the second electrodes 135, 145 of the multiple light-emitting LEDs.

[0152] In another embodiment of the display device 600 described herein, after the light-emitting element LED is self-assembled on the substrate 110 inside the opening 118a, the organic insulating layer OL that fixes the light-emitting element LED can be formed so as to be in contact with at least the top surface and the side surface of the light-emitting element LED. This can improve the fixing force between the light-emitting element LED and the substrate 110, and prevent the light-emitting element LED from becoming detached.

[0153] Furthermore, in the display device 600 according to other embodiments of this specification, the efficiency of the organic layer removal process can be improved by not performing the step of removing the first upper flattening layer 118 and the organic insulating layer OL outside the opening 118a.

[0154] Furthermore, in the display device 600 according to other embodiments of this specification, the first upper planarization layer 118 and the organic insulating layer OL can insulate the pixel circuit from other components and prevent the risk of short circuits without the addition of a separate passivation layer.

[0155] Furthermore, in the display device 600 according to other embodiments of this specification, the organic insulating layer OL can cover more than half of the upper surface area of ​​the light-emitting element LED and more than half of the side surface area of ​​the light-emitting element LED. This can improve the fixing force between the light-emitting element LED and the substrate 110, and prevent the light-emitting element LED from detaching.

[0156] Figure 7 is an enlarged plan view of a display device according to another embodiment of this specification. The display device 700 in Figure 7 is substantially identical to the display device 100 in Figures 1 to 5f, except that the contact electrode CE, the organic insulating layer OL, and the second upper planarization layer are different, so a redundant explanation will be omitted.

[0157] An organic insulating layer OL is placed on the first upper flattening layer 118. The organic insulating layer OL includes a first portion OL1, a second portion OL2, and a third portion.

[0158] The first portion OL1 may be in contact with a portion of the side surface of the light-emitting element LED at the opening 118a. The first portion OL1 in contact with the first light-emitting element 130 may overlap with one of the first assembly wiring 121 and the second assembly wiring 122, and the first portion OL1 in contact with the second light-emitting element 140 may overlap with the other of the first assembly wiring 121 and the second assembly wiring 122. For example, as shown in Figure 7, the first portion OL1 may be positioned only in the region of the side surface of the first light-emitting element 130 that overlaps with the first assembly wiring 121. On the other hand, the first portion OL1 may be positioned only in the region of the side surface of the second light-emitting element 140 that overlaps with the second assembly wiring 122. On the other hand, although Figure 7 shows that the first portion OL1 is positioned only in the region corresponding to 1 / 4 of the side surface of the first light-emitting element 130 and the region corresponding to 1 / 4 of the side surface of the second light-emitting element 140, the position of the first portion OL1 is not limited to this.

[0159] The second portion OL2 is arranged on multiple light-emitting LEDs within the opening 118a. The second portion OL2 in contact with the first light-emitting element 130 overlaps with one of the first assembly wiring 121 and the second assembly wiring 122, while the second light-emitting element 140 and the second portion OL2 may overlap with the other of the first assembly wiring 121 and the second assembly wiring 122. For example, as shown in Figure 7, the second portion OL2 may be arranged only in the region of the side surface of the first light-emitting element 130 that overlaps with the first assembly wiring 121. On the other hand, the second portion OL2 may be arranged only in the region of the side surface of the second light-emitting element 140 that overlaps with the second assembly wiring 122. On the other hand, in Figure 7, the second portion OL2 is shown to be arranged only in a region corresponding to 1 / 4 of the side surface of the first light-emitting element 130, and the second portion OL2 is shown to be arranged only in a region corresponding to 1 / 4 of the side surface of the second light-emitting element 140, but the position of the second portion OL2 is not limited to this.

[0160] Although not shown in Figure 7, the third portion is positioned in the space between the third passivation layer 117 and the light-emitting element LED, and may be in contact with the lower surface of the light-emitting element LED.

[0161] The contact electrode CE is positioned inside the opening 118a. The contact electrode CE is positioned in the region excluding the region where the first portion OL1 of the organic insulating layer OL is positioned. Therefore, the contact electrode CE may be positioned so as to overlap more than half of the side surface of the light-emitting element LED. Thus, the area in contact between the side surface of the light-emitting element LED and the contact electrode CE may be larger than the area in contact between the side surface of the light-emitting element LED and the first portion OL1.

[0162] Although not shown in Figure 7, a second upper planarization layer is placed on the organic insulating layer OL and in the openings OLa of the organic insulating layer where the organic insulating layer is not formed.

[0163] The second upper planarization layer can fill the opening 118a in the region excluding the region where the organic insulating layer OL is located. Therefore, the second upper planarization layer can be positioned inside the opening 118a on the contact electrode CE.

[0164] The second upper flattening layer may be in contact with a portion of the side surface and a portion of the top surface of the multiple light-emitting LEDs at the opening 118a.

[0165] The second upper planarization layer includes contact holes that expose a portion of the upper surface of the light-emitting LED. Pixel electrodes PE are placed in the contact holes of the second upper planarization layer 119 and can be electrically connected to the second electrodes 135, 145 of the multiple light-emitting LEDs.

[0166] In other embodiments of the display device 700 described herein, after self-assembling the light-emitting element LEDs inside the opening 118a on the substrate 110, the organic insulating layer OL that fixes the light-emitting element LEDs can be formed so as to be in contact with at least the top surface and the side surface of the light-emitting element LEDs. This can improve the fixing force between the light-emitting element LEDs and the substrate 110 and prevent the light-emitting element LEDs from becoming detached.

[0167] Furthermore, in the display device 700 according to another embodiment of this specification, the efficiency of the organic layer removal process can be improved by not performing the step of removing the first upper flattening layer 118 and the organic insulating layer OL outside the opening 118a.

[0168] Furthermore, in another embodiment of the display device 700 described herein, the first upper planarization layer 118 and the organic insulating layer OL can insulate the pixel circuit from other components and prevent the risk of short circuits without the addition of a separate passivation layer.

[0169] Furthermore, in another embodiment of the display device 700 described herein, the area in contact between the side surface of the light-emitting element LED and the contact electrode CE may be larger than the area in contact between the side surface of the light-emitting element LED and the first portion OL1. Therefore, the contact area between the light-emitting element LED and the contact electrode CE can be increased, thereby improving the contact resistance.

[0170] Figure 8 is an enlarged plan view of a display device according to another embodiment of this specification. The display device 800 in Figure 8 is substantially identical to the display device 100 in Figures 1 to 5f, except that the contact electrode CE, the organic insulating layer OL, and the second upper planarization layer are different, so a redundant explanation will be omitted.

[0171] An organic insulating layer OL is placed on the first upper flattening layer 118. The organic insulating layer OL includes a first portion OL1, a second portion OL2, and a third portion.

[0172] The first portion OL1 may be in contact with a portion of the side surface of the light-emitting element LED at the opening 118a. The area of ​​the region in which the first portion OL1 overlaps with the first assembly wiring 121 may be different from the area in which the first portion OL1 overlaps with the second assembly wiring 122. The first portion OL1 may completely overlap with one of the first assembly wiring 121 and the second assembly wiring 122, and partially overlap with the other. For example, as shown in Figure 8, the first portion OL1 may completely overlap with the first assembly wiring 121 and partially overlap with the second assembly wiring 122. Thus, the first portion OL1 may overlap with more than half of the side surface of the light-emitting element LED.

[0173] The second portion OL2 is positioned on multiple light-emitting LEDs within the opening 118a. The area of ​​the region in which the second portion OL2 overlaps with the first assembly wiring 121 and the area in which the second portion OL2 overlaps with the second assembly wiring 122 may differ. For example, as shown in Figure 8, the second portion OL2 may completely overlap with the first assembly wiring 121 and partially overlap with the second assembly wiring 122. Thus, the second portion OL2 may overlap with more than half of the upper surface of the light-emitting LEDs.

[0174] Although not shown in Figure 8, the third portion is positioned in the space between the third passivation layer 117 and the light-emitting element LED, and may be in contact with the lower surface of the light-emitting element LED.

[0175] The contact electrode CE is positioned inside the opening 118a.

[0176] The contact electrode CE is positioned in the region of the organic insulating layer OL excluding the region where the first portion OL1 is located. Therefore, the area in contact between the side surface of the light-emitting element LED and the contact electrode CE may be smaller than the area in contact between the side surface of the light-emitting element LED and the first portion OL1.

[0177] Although not shown in Figure 8, a second upper planarization layer is placed on the organic insulating layer OL and in the openings OLa of the organic insulating layer where the organic insulating layer is not formed.

[0178] The second upper planarization layer can fill the opening 118a with the organic insulating layer opening OLa. Thus, the second upper planarization layer can be positioned inside the opening 118a on the contact electrode CE.

[0179] The second upper flattening layer may be in contact with a portion of the side surface and a portion of the top surface of the multiple light-emitting LEDs at the opening 118a.

[0180] The second upper planarization layer includes contact holes that expose a portion of the upper surface of the light-emitting LED. Pixel electrodes PE are placed in the contact holes of the second upper planarization layer 119 and can be electrically connected to the second electrodes 135, 145 of the multiple light-emitting LEDs.

[0181] In another embodiment of the display device 800 described herein, after the light-emitting element LED is self-assembled on the substrate 110 inside the opening 118a, the organic insulating layer OL that fixes the light-emitting element LED can be formed so as to be in contact with at least the top surface and the side surface of the light-emitting element LED. This can improve the fixing force between the light-emitting element LED and the substrate 110 and prevent the light-emitting element LED from becoming detached.

[0182] Furthermore, in the display device 800 according to another embodiment of this specification, the efficiency of the organic layer removal process can be improved by not performing the step of removing the first upper flattening layer 118 and the organic insulating layer OL outside the opening 118a.

[0183] Furthermore, in another embodiment of the display device 800 described herein, the first upper planarization layer 118 and the organic insulating layer OL can insulate the pixel circuit from other components and prevent the risk of short circuits without the addition of a separate passivation layer.

[0184] Furthermore, in another embodiment of the display device 800 described herein, the organic insulating layer OL can cover more than half of the upper surface area of ​​the light-emitting element LED and more than half of the side surface area of ​​the light-emitting element LED. This can improve the fixing force between the light-emitting element LED and the substrate 110, and prevent the light-emitting element LED from detaching.

[0185] Figure 9a is an enlarged plan view of a display device according to another embodiment of this specification. Figure 9b is a cross-sectional view along line E-E' in Figure 9a. The display device 900 in Figures 9a and 9b is substantially identical to the display device 100 in Figures 1 to 5f, except that the second portion OL2 of the organic insulating layer OL, the second upper planarization layer 919, and the pixel electrode PE are different, so redundant explanations are omitted.

[0186] An organic insulating layer OL is disposed on the first upper flattening layer 118. The organic insulating layer OL can cover a portion of the sides of multiple light-emitting elements (LEDs). The organic insulating layer OL includes a first portion OL1 and a third portion OL3.

[0187] The first part OL1 is positioned to be in contact with the sides of multiple light-emitting LEDs and covers a portion of the sides of the light-emitting LEDs.

[0188] The third portion OL3 is positioned in the space between the third passivation layer 117 and the light-emitting element LED, and may be in contact with the lower surface of the light-emitting element LED.

[0189] On the other hand, the organic insulating layer OL does not need to be placed on the upper surface of multiple light-emitting LEDs. Therefore, as shown in Figure 9a, the organic insulating layer OL can expose the second electrodes 135 and 145 that are placed on the upper surface of multiple light-emitting LEDs.

[0190] The contact electrode CE is positioned in the region excluding the area where the first portion OL1 of the organic insulating layer OL is located, and can electrically connect the first electrodes 134 and 144 of the light-emitting element LED to the first assembly wiring 121 and the second assembly wiring 122.

[0191] Referring to Figure 9b, the second upper planarization layer 919 is placed in the organic insulating layer OL and in the openings OLa of the organic insulating layer where the organic insulating layer is not formed.

[0192] The second upper planarization layer 919 can fill the opening 118a in the region excluding the region where the organic insulating layer OL is located. Therefore, the second upper planarization layer 919 can be positioned on the contact electrode CE inside the opening 118a.

[0193] The second upper planarization layer 919 includes contact holes that expose the upper surface of the light-emitting LEDs. Pixel electrodes PE are placed in the contact holes of the second upper planarization layer 919 and can be electrically connected to the second electrodes 135, 145 of the multiple light-emitting LEDs.

[0194] Multiple pixel electrodes PE for electrically connecting the light-emitting elements LEDs and connecting electrodes 150 are arranged on the second upper planarization layer 919.

[0195] In another embodiment of the display device 900 described herein, after the light-emitting element LED is self-assembled on the substrate 110 inside the opening 118a, the organic insulating layer OL that fixes the light-emitting element LED can be formed so as to be in contact with the side surface of the light-emitting element LED. This improves the fixing force between the light-emitting element LED and the substrate 110, and prevents the light-emitting element LED from becoming detached.

[0196] Furthermore, in the display device 900 according to another embodiment of this specification, the efficiency of the organic layer removal process can be improved by not performing the step of removing the first upper flattening layer 118 and the organic insulating layer OL outside the opening 118a.

[0197] Furthermore, in another embodiment of the display device 900 described herein, the first upper planarization layer 118 and the organic insulating layer OL can insulate the pixel circuit from other components and prevent the risk of short circuits without the addition of a separate passivation layer.

[0198] Furthermore, in another embodiment of the display device 900 described herein, the organic insulating layer OL is arranged in the region excluding the upper surface of the light-emitting element LED. Therefore, the front surfaces of the second electrodes 135 and 145, which are arranged on the upper surface of the light-emitting element LED, can contact the pixel electrode PE. Thus, the contact resistance between the light-emitting element LED and the pixel electrode PE can be improved.

[0199] The embodiments disclosed herein are for illustrative purposes only and not to limit the technical concept herein. The more areas where the organic insulating layer OL is left, the stronger the fixing force of the light-emitting element LED can be, and the more areas where the organic insulating layer OL is open, the more stable the contact with the pixel electrode PE can be. Depending on the size and design of the light-emitting element LED, it is possible to form it in various ways to ensure appropriate fixing force and contact area.

[0200] The various embodiments of this specification may be described as follows.

[0201] A display device according to one embodiment of this specification includes a substrate including a plurality of subpixels, a first assembly wiring and a second assembly wiring arranged on the substrate with respect to the plurality of subpixels and spaced apart from each other, a first upper planarization layer disposed on the first and second assembly wiring and having an opening that overlaps with the first and second assembly wiring, a light-emitting element disposed in the opening and including a first electrode, a first semiconductor layer, a light-emitting layer, a second semiconductor layer, and a second electrode, a contact electrode that electrically connects the first and second assembly wiring and the first electrode, and an organic insulating layer disposed on the first upper planarization layer and covering a portion of the side surface and a portion of the top surface of the light-emitting element.

[0202] According to other features of this specification, the organic insulating layer may include a first portion that contacts the side surface of the light-emitting element with respect to the portion that contacts the contact electrode.

[0203] According to other features of this specification, the invention further includes a second upper planarizing layer disposed on the light-emitting element and the organic insulating layer, the second upper planarizing layer may be disposed to fill the openings.

[0204] According to other features of this specification, the second upper planarizing layer may be positioned to fill the opening in the area excluding the area in which the organic insulating layer is located.

[0205] According to other features of this specification, the light-emitting element includes a first light-emitting element and a second light-emitting element, each of which is arranged in a plurality of subpixels, wherein a first portion in contact with the first light-emitting element superimposed on one of the first and second assembly wirings, and a first portion in contact with the second light-emitting element may superimpose on the other of the first and second assembly wirings.

[0206] According to other features of this specification, the light-emitting element includes a first light-emitting element and a second light-emitting element, each of which is arranged in a plurality of subpixels, and a first portion in contact with the first light-emitting element and a first portion in contact with the second light-emitting element may be superimposed on either a first assembly wiring or a second assembly wiring, respectively.

[0207] According to other features of this specification, the planar shape of the second upper flattening layer positioned in the opening may be rectangular.

[0208] According to other features of this specification, the area of ​​the region in which the first part overlaps with the first assembly wiring and the area of ​​the region in which the first part overlaps with the second assembly wiring may be the same.

[0209] According to other features of this specification, the area of ​​the region in which the first part overlaps with the first assembly wiring and the area of ​​the region in which the first part overlaps with the second assembly wiring may be different.

[0210] According to other features of this specification, the first part may completely overlap with one of the first and second assembly wirings, and partially overlap with the other.

[0211] According to other features of this specification, the area in contact between the side of the light-emitting element and the contact electrode may be larger than the area in contact between the side of the light-emitting element and the first portion.

[0212] According to other features of this specification, the area in contact between the side of the light-emitting element and the contact electrode may be smaller than the area in contact between the side of the light-emitting element and the first portion.

[0213] According to other features of this specification, the organic insulating layer may further include a second portion that covers a portion of the upper surface of the light-emitting element.

[0214] Another feature of this specification further includes a transistor disposed on a substrate and a pixel electrode electrically connecting the transistor to a second electrode, wherein the pixel electrode may be in contact with the second electrode in the upper surface of the light-emitting element, excluding the region on which the second portion is disposed.

[0215] According to other features of this specification, the side surface of the second part may be positioned along a portion of the area around the second electrode.

[0216] According to other features of this specification, the organic insulating layer may further include a third portion located beneath the light-emitting element.

[0217] Although embodiments of this specification have been described in more detail above with reference to the attached drawings, this specification is not necessarily limited to these embodiments and can be modified and implemented in various ways without deviating from the technical concept of this specification. Accordingly, the embodiments disclosed herein are for illustrative purposes only, not to limit the technical concept of this specification, and the scope of the technical concept of this specification is not limited by such embodiments. Therefore, the embodiments described above should be understood in all respects as illustrative and non-limiting. The scope of protection of this specification should be interpreted based on all the technical concepts discussed, and all technical concepts within an equivalent scope should be interpreted as being included in the scope of rights of this specification.

Claims

1. A substrate containing multiple subpixels; First and second assembly wirings arranged on the substrate at a distance from each other, with respect to a plurality of subpixels; A first upper flattening layer disposed on the first assembly wiring and the second assembly wiring; An opening located in the first upper flattening layer and overlapping with the first and second assembly wiring; A light-emitting element, which includes a top surface and side surfaces, and is disposed in the opening, and includes a first electrode and a second electrode disposed on the first electrode; Contact electrodes electrically connecting the first assembly wiring, the second assembly wiring, and the first electrode; and A display device comprising an organic insulating layer disposed in a portion of the opening and covering a portion of the side surface of the light-emitting element.

2. A portion of the side surface of the light-emitting element is in contact with the first portion of the organic insulating layer. The display device according to claim 1, wherein another portion of the side surface of the light-emitting element is in contact with the contact electrode.

3. The light-emitting element and the second upper planarizing layer disposed on the organic insulating layer further include The display device according to claim 2, wherein the second upper flattening layer is disposed in a part of the opening.

4. The aforementioned opening includes an organic insulating layer opening, The display device according to claim 3, wherein the second upper flattening layer is disposed at the opening of the organic insulating layer.

5. The light-emitting element includes a first light-emitting element and a second light-emitting element, each of which is arranged in a plurality of subpixels. The first portion in contact with the first light-emitting element overlaps with one of the first assembly wiring and the second assembly wiring. The display device according to claim 3, wherein the first portion in contact with the second light-emitting element is superimposed on the other one of the first assembly wiring and the second assembly wiring.

6. The light-emitting element includes a first light-emitting element and a second light-emitting element, each of which is arranged in a plurality of subpixels. The display device according to claim 3, wherein the first portion in contact with the first light-emitting element and the first portion in contact with the second light-emitting element each superimpose on either the first assembly wiring or the second assembly wiring.

7. The display device according to claim 4, wherein the planar shape of the second upper flattening layer disposed at the opening of the organic insulating layer is rectangular.

8. The display device according to claim 6, wherein the area of ​​the region in which the first part overlaps with the first assembly wiring is the same as the area of ​​the region in which the first part overlaps with the second assembly wiring.

9. The display device according to claim 6, wherein the area of ​​the region in which the first part overlaps with the first assembly wiring and the area of ​​the region in which the first part overlaps with the second assembly wiring are different.

10. The display device according to claim 6, wherein the first part completely overlaps with one of the first assembly wiring and the second assembly wiring, and partially overlaps with the other.

11. The display device according to claim 2, wherein the area in which the side surface of the light-emitting element and the contact electrode are in contact with each other is the same as the area in which the side surface of the light-emitting element and the first portion are in contact with each other, or is larger than the area in which the side surface of the light-emitting element and the first portion are in contact with each other.

12. The display device according to claim 2, wherein the area in which the side surface of the light-emitting element and the contact electrode are in contact with each other is smaller than the area in which the side surface of the light-emitting element and the first portion are in contact with each other.

13. The display device according to claim 1, wherein the organic insulating layer further includes a second portion that covers a part of the upper surface of the light-emitting element.

14. Transistors arranged on the aforementioned substrate; and The device further includes a pixel electrode that electrically connects the transistor and the second electrode, The display device according to claim 13, wherein the pixel electrode is in contact with the second electrode in the region of the upper surface of the light-emitting element, excluding the region in which the second portion is arranged.

15. The display device according to claim 13, wherein the side surface of the second portion is arranged along a portion of the periphery of the second electrode.

16. The display device according to claim 1, wherein the organic insulating layer further comprises a third portion disposed below the light-emitting element.

17. The first assembled wiring includes a first conductive layer and a first cladding layer covering the top and side surfaces of the first conductive layer. The second assembled wiring comprises a second conductive layer and a second cladding layer covering the top and sides of the second conductive layer. The first conductive layer and the second conductive layer are not superimposed on the light-emitting element. The display device according to claim 1, wherein the first cladding layer and the second cladding layer are superimposed on the light-emitting element.

18. The light-emitting element and the second upper planarizing layer disposed on the organic insulating layer further include The display device according to claim 1, wherein the second upper flattening layer is disposed on the contact electrode within the opening.

19. The display device according to claim 2, wherein the first portion extends outward from the opening and is disposed on the first upper flattening layer.

20. A display device, substrate; Multiple assembly wirings arranged on the substrate at a distance from each other; A first upper flattening layer arranged on the plurality of assembly wirings; An opening located in the first upper flattening layer; Organic insulating layer; A light-emitting element arranged in the opening, including its side surface; and Contact electrode to be placed in the opening Equipped with, The contact electrode is arranged to be in contact with the plurality of assembly wirings and the light-emitting element. The organic insulating layer overlaps with the plurality of assembled wirings at the opening and is in contact with the side surface of the light-emitting element, in a display device.

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