Semiconductor equipment

Abstract

One of the objectives is to provide a semiconductor device with a novel structure. [Solution] A first wire, a second wire, a third wire, a fourth wire, and a first gate A first transistor having electrodes, a first source electrode, and a first drain electrode, A second transient having two gate electrodes, a second source electrode, and a second drain electrode. A transistor has a first transistor provided on a substrate containing a semiconductor material, and a second transistor A semiconductor device is composed of an oxide semiconductor layer.

Description

[Technical Field]

[0001] The disclosed invention relates to a semiconductor device utilizing a semiconductor element and a method for manufacturing the same. ru. [Background technology]

[0002] Memory devices using semiconductor elements are volatile, meaning that the stored data is lost when the power supply is cut off. They can be broadly classified into two types: physical data and non-volatile data, which retains its contents even when the power supply is cut off. .

[0003] A typical example of a volatile memory device is DRAM (Dynamic Random Access Memory). DRAM has a memory (cess memory). DRAM selects transistors that make up the memory elements. By accumulating electric charge in the capacitor, it stores information.

[0004] Based on the principle described above, in DRAM, when information is read, the charge in the capacitor is lost. Therefore, a write operation is required each time data is read. Also, the memory element The transistors that make up the circuit have leakage current, and charge flows out even when they are not selected. Alternatively, because data is constantly flowing in, the data retention period is short. Therefore, it is written again at predetermined intervals. A refresh operation is required, making it difficult to significantly reduce power consumption. Furthermore, since the memory contents are lost when the power supply is cut off, magnetism is necessary for long-term memory retention. A different type of memory device utilizing materials or optical materials will be needed.

[0005] Another example of volatile memory is SRAM (Static Random Access Memory). SRAM has memory. SRAM uses circuits such as flip-flops to store information. For retention, a refresh operation is not required, which is advantageous over DRAM in this regard. However, since circuits such as flip - flops are used, there is a problem that the unit price per storage capacity becomes high. Also, in terms of the fact that the stored content is lost when the power supply is cut off, there is no difference from DRAM.

[0006] A representative example of a non - volatile memory device is a flash memory. The flash memory has a floating gate between the gate electrode and the channel formation region of a transistor, and stores data by holding charges in the floating gate. Therefore, the data retention period is extremely long (semi - permanent), and it has the advantage that the refresh operation required for volatile memory devices is not necessary (for example, see Patent Document 1). However, since the gate insulating layer constituting the memory element deteriorates due to the tunnel current generated during writing, there is a problem that the memory element stops functioning after a predetermined number of writes. In order to mitigate the influence of this problem, for example, a technique of equalizing the number of writes of each memory element is adopted. However, in order to realize this, complex peripheral circuits are required. Thus, even if such a technique is adopted, the fundamental problem of lifespan is not solved. That is, flash memory is not suitable for applications where the information rewrite frequency is high.

[0007]

[0008] In addition, in order to hold charges in the floating gate or to remove those charges, a high voltage is required. Furthermore, a relatively long time is required for holding or removing charges, and there is also a problem that it is not easy to speed up writing and erasing.

Prior Art Documents

Patent Document

[0009]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0010] In view of the above problems, in one aspect of the disclosed invention, a semiconductor device with a new structure is provided that can retain stored content even when no power is supplied and has no limit on the number of write operations. This is one of the objectives.

Means for Solving the Problems

[0011] One aspect of the present invention relates to a semiconductor device having a stacked structure of a transistor formed using an oxide semiconductor and a transistor formed using other materials. For example, the following configuration can be adopted.

[0012] One aspect of the present invention has a first wiring, a second wiring, a third wiring, a fourth wiring, and a fifth wiring. A plurality of memory elements are connected in parallel between the first wiring and the second wiring. One of the plurality of memory elements includes a first transistor having a first gate electrode, a first source electrode, and a first drain electrode, a second transistor having a second gate electrode, a second source electrode, and a second drain electrode, and a third transistor having a third gate electrode, a third source electrode, and a third drain electrode. The first transistor is provided on a substrate including a semiconductor material, the second transistor is configured to include an oxide semiconductor layer, and the first gate electrode is connected to one of the second source electrode or the second drain electrode. ​ , electrically connected, the first wiring and the first source electrode are electrically connected, the first The drain electrode and the third source electrode are electrically connected, and the second wiring and the third drain The in electrode is electrically connected to the third wire and the second source electrode or second drain electrode. The other electrode is electrically connected to the fourth wire and the second electrode. It is a semiconductor device that is connected and electrically connected to the fifth wiring and the third gate electrode.

[0013] Furthermore, one aspect of the present invention includes a first wiring, a second wiring, a third wiring, and a fourth wiring. It has a fifth wiring, and between the first wiring and the second wiring, multiple memory elements are arranged in parallel. Connected, one of the multiple memory elements has a first gate electrode, a first source electrode, and a first A first transistor having a drain electrode, a second gate electrode, a second source electrode, and The device comprises a second transistor having a second drain electrode and a capacitive element, and a first transistor having a second drain electrode. The transistor is mounted on a substrate containing semiconductor material, and the second transistor is on an oxide semiconductor layer. It is configured to include a first gate electrode and a second source electrode or a second drain electrode. One electrode of the capacitive element is electrically connected to the first wiring and the first source electrode. This means that the second wiring and the first drain electrode are electrically connected, The third wiring is electrically connected to the other of the second source electrode or the second drain electrode. The fourth wire and the second gate electrode are electrically connected, and the fifth wire and the capacitive element The other electrode is a semiconductor device that is electrically connected to it.

[0014] In the above, the first transistor is a channel forming device provided on a substrate containing a semiconductor material. A region, an impurity region provided so as to sandwich the channel formation region, and on the channel formation region A first gate insulating layer, a first gate electrode on the first gate insulating layer, an impurity region and an electrical It has a first source electrode and a first drain electrode that are connected to each other.

[0015] Furthermore, in the above, the second transistor is a second gate electrode on a substrate containing semiconductor material. The electrode, the second gate insulating layer on the second gate electrode, and the oxide semiconductor on the second gate insulating layer. A body layer and a second source electrode and a second drain electrode electrically connected to the oxide semiconductor layer. It has, and

[0016] Furthermore, in the above, the third transistor is a channel provided on a substrate containing semiconductor material. An impurity region is provided so as to sandwich the channel formation region and the channel formation region A third gate insulating layer on the region, a third gate electrode on the third gate insulating layer, and an impurity region. It has a third source electrode and a third drain electrode that are electrically connected to it.

[0017] Furthermore, in the above, the substrate containing the semiconductor material may be a single-crystal semiconductor substrate or an SOI substrate. It is preferable to use a plate. In particular, silicon is preferred as the semiconductor material.

[0018] Furthermore, in the above, the oxide semiconductor layer is an In-Ga-Zn-O based oxide semiconductor material. It is preferable that it contains. In particular, the oxide semiconductor layer is made of In2Ga2ZnO7 crystals. It is preferable that it contains. Furthermore, the hydrogen concentration of the oxide semiconductor layer is 5 × 10 19 / cm 3 The following is preferable. Also, the off-current of the second transistor is 1 × 10⁻⁶. -13 It is preferable to set it to A or less.

[0019] Furthermore, in the above, the second transistor is provided in a region that overlaps with the first transistor. It can be configured in this way.

[0020] In this specification, the terms "above" and "below" refer to the relative positions of the constituent elements, such as "directly above" or This does not necessarily mean "directly below". For example, "the first gate on the gate insulating layer The expression "gate electrode" implies that there are other components between the gate insulating layer and the gate electrode. It will not be excluded. Also, the terms "upper" and "lower" are merely expressions used for the sake of explanation, and not particularly Unless otherwise specified, this also includes the inverted versions.

[0021] Furthermore, in this specification, the terms "electrode" and "wiring" do not limit the functionality of these components. It is not fixed. For example, "electrode" can be used as part of "wiring". The reverse is also true. Furthermore, the terms "electrode" and "wiring" can refer to multiple "electrodes" and "wiring". This also includes cases where the "lines" are formed as a single unit.

[0022] Furthermore, the "source" and "drain" functions are used when employing transistors with different polarities. However, this can change when the direction of current changes during circuit operation. In this specification, the terms "source" and "drain" may be used interchangeably. It is assumed that this is possible.

[0023] In this specification, etc., "electrically connected" means "having some kind of electrical effect." This includes cases where the connection is made via ". Here, "something that has some electrical effect" The term "connection" is not particularly limited as long as it enables the exchange of electrical signals between connected objects.

[0024] For example, "something that has some kind of electrical effect" includes not only electrodes and wiring, but also traps. Switching elements such as inverters, resistive elements, inductors, capacitors, and various other components. This includes elements that possess certain capabilities.

[0025] Furthermore, generally speaking, an "SOI substrate" is a substrate in which a silicon semiconductor layer is provided on an insulating surface. However, in this specification, etc., a semiconductor layer made of a material other than silicon is provided on the insulating surface. It is used as a concept that also includes the substrate with the specified configuration. In other words, the semiconductor that the "SOI substrate" possesses The layer is not limited to a silicon semiconductor layer. Also, the substrate in "SOI substrate" is silicon This applies not only to semiconductor substrates such as wafers, but also to glass substrates, quartz substrates, sapphire substrates, and metal substrates. This also includes non-semiconductor substrates such as conductive substrates and insulating substrates. Those having the above characteristics are also broadly included in the term "SOI substrate". Furthermore, in this specification, etc., "semiconductor The term "substrate" refers not only to a substrate made solely of semiconductor materials, but to all substrates containing semiconductor materials. This shall indicate the following. In other words, in this specification, "SOI substrate" is also broadly referred to as "semiconductor substrate". It is included in. [Effects of the Invention]

[0026] In one aspect of the present invention, the lower part has a transistor made of a material other than an oxide semiconductor, and the upper A semiconductor device having a transistor made of an oxide semiconductor is provided.

[0027] Transistors using oxide semiconductors have extremely low off-currents, so we decided to use them. It is possible to retain memory content for an extremely long period of time. In other words, refresh function This eliminates the need for manual operation, or makes it possible to significantly reduce the frequency of refresh operations. Therefore, power consumption can be significantly reduced. Also, even if there is no power supply... It is possible to retain memory content over a long period of time.

[0028] Furthermore, it does not require high voltage for writing information, and there are no issues with component degradation. Because information is written depending on whether the inverter is on or off, high-speed operation is also possible. It can be easily implemented. Furthermore, it has the advantage of not requiring any action to erase the information. .

[0029] Furthermore, transistors using materials other than oxide semiconductors are capable of sufficiently high-speed operation, By using this method, it is possible to read the contents of memory at high speed.

[0030] Thus, transistors using materials other than oxide semiconductors and transistors using oxide semiconductors By integrating a transistor, a semiconductor device with unprecedented features can be realized. It is possible. [Brief explanation of the drawing]

[0031] [Figure 1] A circuit diagram used to explain a semiconductor device. [Figure 2] Cross-sectional and plan views illustrating a semiconductor device. [Figure 3] A cross-sectional diagram illustrating the manufacturing process of semiconductor devices. [Figure 4] A cross-sectional diagram illustrating the manufacturing process of semiconductor devices. [Figure 5] A cross-sectional diagram illustrating the manufacturing process of semiconductor devices. [Figure 6]A cross-sectional diagram illustrating a semiconductor device. [Figure 7] A cross-sectional diagram illustrating a semiconductor device. [Figure 8] A cross-sectional diagram illustrating a semiconductor device. [Figure 9] A cross-sectional diagram illustrating a semiconductor device. [Figure 10] A circuit diagram illustrating a memory element. [Figure 11] A timing chart diagram to explain the operation of memory elements. [Figure 12] A circuit diagram used to explain a semiconductor device. [Figure 13] A circuit diagram illustrating a memory element. [Figure 14] A circuit diagram used to explain a semiconductor device. [Figure 15] A circuit diagram illustrating a memory element. [Figure 16] A diagram showing the relationship between node A and the fifth wiring potential. [Figure 17] A circuit diagram used to explain a semiconductor device. [Figure 18] A circuit diagram illustrating a memory element. [Figure 19] A circuit diagram used to explain a semiconductor device. [Figure 20] A circuit diagram illustrating a memory element. [Figure 21] A circuit diagram illustrating a memory element. [Figure 22] A circuit diagram to explain the readout circuit. [Figure 23] A diagram used to explain electronic devices. [Figure 24] Cross-sectional view of an inverse staggered transistor using an oxide semiconductor. [Figure 25] The energy band diagram (schematic diagram) in the A-A' section of Figure 24. [Figure 26] (A) shows the state where a positive potential (+VG) is applied to gate (G1), and (B) shows the state where a negative potential (-VG) is applied to gate (G1). [Figure 27]This diagram shows the relationship between the vacuum level, the work function (φM) of metals, and the electron affinity (χ) of oxide semiconductors. [Modes for carrying out the invention]

[0032] An example of an embodiment of the present invention will be described below with reference to the drawings. However, the present invention is as follows The description is not limited to the present invention, and without departing from the spirit and scope of the present invention, its form and Those skilled in the art will readily understand that the details can be modified in various ways. Therefore, the present invention is as follows: The description of the embodiment shown is not to be limited to the content described therein.

[0033] Note that the position, size, and scope of each component shown in the drawings, etc., are for ease of understanding. The position, size, and extent of the boundary may not be shown. Therefore, it is not always possible to see this in drawings, etc. It is not limited to the indicated location, size, or range.

[0034] Furthermore, the ordinal numbers such as "1st," "2nd," and "3rd" used in this specification, etc., are intended to avoid confusion of constituent elements. This is added to avoid any misunderstandings and does not mean that the number is limited.

[0035] (Embodiment 1) In this embodiment, the configuration and manufacturing method of a semiconductor device according to one aspect of the disclosed invention are described below. This will be explained with reference to Figures 1 to 9.

[0036] <Circuit configuration of semiconductor device> Figure 1 shows an example of the circuit configuration of a semiconductor device. This semiconductor device is made of materials other than oxide semiconductors. It consists of a transistor 160 made of material and a transistor 162 made of oxide semiconductor. It will be accomplished.

[0037] Here, the gate electrode of transistor 160 and the source electrode or dot of transistor 162 It is electrically connected to one of the rain electrodes. Also, the first line The source wire (also called the source line) and the source electrode of transistor 160 are electrically connected, and the second The wiring (2nd Line: also called the bit line) and the drain electrode of transistor 160 and They are electrically connected. And the third wire (3rd Line: also known as the 1st signal line) The other of the source electrode or drain electrode of transistor 162 is electrically connected. And the fourth wire (4th Line: also called the second signal line) and transistor 162 The gate electrode is electrically connected.

[0038] Transistor 160, which uses materials other than oxide semiconductors, is capable of sufficiently high-speed operation, By using this, it is possible to perform tasks such as reading stored contents at high speed. Furthermore, The oxide semiconductor transistor 162 has the characteristic of having an extremely low off-current. Therefore, by turning off transistor 162, transistor 160 It is possible to maintain the potential of the gate electrode for an extremely long period of time.

[0039] By taking advantage of the characteristic that the potential of the gate electrode can be maintained, information can be written as follows: It can be held and read.

[0040] First, we will explain how to write and retain information. First, the potential of the fourth wire is... The potential at which transistor 162 turns on is set to the ON state, and transistor 162 is turned ON. As a result, the potential of the third wire is applied to the gate electrode of transistor 160 (write (Including). Then, the potential of the fourth wire is set as the potential at which transistor 162 is in the off state. By turning off transistor 162, the gate electrode of transistor 160 The electric potential is maintained (held).

[0041] Since the off-current of transistor 162 is extremely small, the gate electrode of transistor 160 The potential is maintained for a long time. For example, the potential of the gate electrode of transistor 160 is If the potential is such that transistor 160 is turned on, then transistor 160 will remain in the turned-on state for a long time. This will be maintained over time. Also, the potential of the gate electrode of transistor 160 If the potential is such that transistor 160 is in the off state, then transistor 160 will remain in the off state for a long time. It is retained over time.

[0042] Next, we will explain how to read the information. As mentioned above, the ON state of transistor 160 Alternatively, when the OFF state is maintained, a predetermined potential (low potential) is applied to the first wiring. When this happens, the potential of the second wiring differs depending on whether transistor 160 is on or off. It takes a value such that, for example, when transistor 160 is ON, the potential of the first wiring is Conversely, the potential of the second wiring decreases. On the other hand, transistor 160 is in the OFF state. In this case, the potential of the second wire does not change.

[0043] In this way, while the information is retained, the potential of the second wiring is compared with a predetermined potential. By doing so, information can be extracted.

[0044] Next, we will explain how to rewrite information. Rewriting information involves writing the information as described above and This is done in the same way as holding. In other words, the potential of the fourth wire is set when transistor 162 is ON. To achieve this potential, transistor 162 is turned ON. This results in the potential of the third wiring. (A potential related to new information) is applied to the gate electrode of transistor 160. Then, The potential of the fourth wire is set to the potential at which transistor 162 is in the OFF state, By turning off 62, the new information is retained.

[0045] Thus, the semiconductor device relating to the disclosed invention directly generates information through subsequent writing. It is possible to rewrite the information. Therefore, it is necessary in flash memory and other applications. This eliminates the need for an erase operation, thus suppressing the decrease in operating speed caused by the erase operation. In other words, high-speed operation of semiconductor devices will be achieved.

[0046] Note that the above explanation refers to an n-type transistor (n-channel transistor) that uses electrons as the majority carrier. This concerns the case where a st(s) is used, but instead of an n-type transistor, a large number of holes are used. It goes without saying that a p-type transistor can be used as the carrier.

[0047] <Planar and cross-sectional configurations of semiconductor devices> Figure 2 shows an example of the configuration of the semiconductor device described above. Figure 2(A) shows a cross-section of the semiconductor device. Figure 2(B) shows the planes of the semiconductor device. Here, Figure 2(A) is the same as Figure 2(B). This corresponds to the cross-section along lines A1-A2 and B1-B2. Figures 2(A) and 2(B) The semiconductor device shown in ) has a transistor 160 at the bottom that uses a material other than an oxide semiconductor. It has a transistor 162 made of oxide semiconductor on its upper part. Transistor 160 and transistor 162 are both described as n-type transistors. However, a p-type transistor may also be used. In particular, transistor 160 should be a p-type transistor. This is easy.

[0048] The transistor 160 is located in a channel formation region 11 provided on a substrate 100 containing semiconductor material. 6 and the impurity region 114 and high concentration impurity region provided so as to sandwich the channel formation region 116. The pure material region 120 (these are also simply called the impurity region) and the channel-forming region 11 A gate insulating layer 108a provided on 6, and a gate provided on the gate insulating layer 108a Electrode 110a and source electrode or drain electrode 1 which are electrically connected to the impurity region 114 It has 30a, a source electrode or a drain electrode 130b.

[0049] Here, a sidewall insulating layer 118 is provided on the side surface of the gate electrode 110a. Furthermore, in the region of the substrate 100 that does not overlap with the sidewall insulating layer 118 when viewed in cross-section, It has a high-concentration impurity region 120, and a metal compound region 124 is located on the high-concentration impurity region 120. It exists. Also, on the substrate 100, there is an element isolation insulating layer 10 surrounding the transistor 160. 6 is provided, and the interlayer insulating layer 126 and interlayer insulating layer are provided so as to cover the transistor 160. A marginal layer 128 is provided. Source electrode or drain electrode 130a, source electrode or The drain electrode 130b is located at an opening formed in the interlayer insulating layer 126 and the interlayer insulating layer 128. It is electrically connected to the metal compound region 124 through the source electrode or The drain electrode 130a, source electrode or drain electrode 130b are located in the metal compound region 12 It is electrically connected to the high-concentration impurity region 120 and the impurity region 114 via 4. Furthermore, the gate electrode 110a is connected to the source electrode or drain electrode 130a or the source electrode Alternatively, electrode 130c, which is provided similarly to the drain electrode 130b, is electrically connected.

[0050] The transistor 162 has a gate electrode 136d provided on the interlayer insulating layer 128, and a gate A gate insulating layer 138 provided on electrode 136d, and a gate insulating layer 138 provided on An oxide semiconductor layer 140, and provided on the oxide semiconductor layer 140, and The electrically connected source electrode or drain electrode 142a, source electrode or drain It has an in electrode 142b.

[0051] Here, the gate electrode 136d is embedded in the insulating layer 132 formed on the interlayer insulating layer 128. It is provided to be inserted. Also, similar to the gate electrode 136d, the source electrode or drain Electrode 136a is in contact with in electrode 130a and is in contact with source electrode or drain electrode 130b. Electrode 136b is in contact with electrode 130c, and electrode 136c is formed accordingly.

[0052] Furthermore, a protective layer is placed on top of the transistor 162 so as to be in contact with a portion of the oxide semiconductor layer 140. An insulating layer 144 is provided, and an interlayer insulating layer 146 is provided on the protective insulating layer 144. Here, the protective insulating layer 144 and the interlayer insulating layer 146 have a source electrode or drain. An opening is provided that reaches the source electrode 142a, or the drain electrode 142b. Furthermore, through the opening, electrodes 150d and 150e are connected to the source electrode or drain electrode. It is formed in contact with electrode 142a, source electrode or drain electrode 142b. Similar to the electrodes 150d and 150e, electrodes 150a, 150b, and 150c are formed which are in contact with the electrodes 136a, 136b, and 136c through openings provided in the gate insulating layer 138, the protective insulating layer 144, and the interlayer insulating layer 146. Here, it is desirable that the oxide semiconductor layer 140 is sufficiently purified by removing impurities such as hydrogen. Specifically, the hydrogen concentration in the oxide semiconductor layer 140 is 5×10 / cm

[0053] or less, desirably 5×10 / cm 19 or less, more desirably 5×10 3 / cm 18 or less. Also, in the oxide semiconductor layer 140 where the hydrogen concentration is sufficiently reduced and highly purified, the carrier concentration is 5×10 3 / cm 17 or less, desirably 5×10 3 / cm or less. Thus, by using an oxide semiconductor in which the hydrogen concentration is sufficiently reduced and highly purified and is i - type or substantially i - type, a transistor 162 with extremely excellent off - current characteristics can be obtained. For example, when the drain voltage Vd is +1V or +10V and the gate voltage Vg ranges from - 5V to - 20V, the off - current is 1×10 14 3 12 A or less. Thus, by applying the oxide semiconductor layer 140 in which the hydrogen concentration is sufficiently reduced and highly purified and reducing the off - current of the transistor 162, a semiconductor device with a new configuration can be realized. Note that the hydrogen concentration in the above - mentioned oxide semiconductor layer 140 is measured by secondary ion mass spectrometry (SIMS: Secondary Ion Mass Spec 3 -1 3 <000:0477>

[0054] trometry). This was measured using troscopy.

[0054] Furthermore, an insulating layer 152 is provided on the interlayer insulating layer 146, and embedded in the insulating layer 152. Electrodes 154a, 154b, 154c, and 154d are provided so as to be inserted. Here, electrode 154a is in contact with electrode 150a, and electrode 154b is in contact with electrode 150 It is in contact with b, and electrode 154c is in contact with electrode 150c and electrode 150d, and electrode 1 Electrode 54d is in contact with electrode 150e.

[0055] In other words, in the semiconductor device shown in Figure 2, the gate electrode 110a of transistor 160 and The source electrode or drain electrode 142a of transistor 162 is connected to electrode 130c, electrode Electrodes 136c, 150c, 154c and 150d are electrically connected. Yes, they are.

[0056] <Method for fabricating semiconductor devices> Next, we will describe an example of a method for manufacturing the above semiconductor device. Below, we will first explain the lower part The method for fabricating the transistor 160 will be explained with reference to Figure 3, and then the upper transistor The method for manufacturing Ta162 will be explained with reference to Figures 4 and 5.

[0057] <Method for fabricating the lower transistor> First, prepare a substrate 100 containing semiconductor material (see Figure 3(A)). The plate 100 can be a single-crystal semiconductor substrate such as silicon or silicon carbide, or a polycrystalline semiconductor substrate. Compound semiconductor substrates such as silicon germanium, SOI substrates, etc. can be applied. Here, we will use a single-crystal silicon substrate as the substrate 100 containing semiconductor material. An example will be shown. Generally speaking, an "SOI substrate" is a substrate with silicon semiconductor on an insulating surface. This refers to a substrate having a conductive layer, but in this specification, it refers to a substrate having a silicon on the insulating surface. This concept is used to include substrates with a semiconductor layer made of materials other than those mentioned above. The semiconductor layer of the "SOI substrate" is not limited to a silicon semiconductor layer. The substrate has a configuration in which a semiconductor layer is provided on an insulating substrate such as a glass substrate, with an insulating layer in between. It shall include the following.

[0058] A protective layer 102 is formed on the substrate 100, which serves as a mask for forming an element isolation insulating layer. (See Figure 3(A)). The protective layer 102 can be, for example, silicon oxide or silicon nitride. An insulating layer made of silicon nitride or similar material can be used. In order to control the threshold voltage of the transistor, an impurity is imparted to impart n-type conductivity. Monochemical elements or impurity elements that impart p-type conductivity may be added to the substrate 100. In the case of ricon, impurities that impart n-type conductivity include, for example, phosphorus and arsenic. This can be achieved. Furthermore, examples of impurities that impart p-type conductivity include boron and aluminum. Materials such as nium and gallium can be used.

[0059] Next, etching is performed using the protective layer 102 as a mask, and the protective layer 102 is covered A portion of the substrate 100 in the area that is not covered (exposed area) is removed. This separates it. A semiconductor region 104 is formed (see Figure 3(B)). This etching process involves dry etching. Etching is preferred, but wet etching may also be used. The etching solution and other materials can be appropriately selected depending on the material to be etched.

[0060] Next, an insulating layer is formed to cover the semiconductor region 104, and the region superimposed on the semiconductor region 104 By selectively removing the insulating layer, an element isolation insulating layer 106 is formed (see Figure 3(B)). The insulating layer is formed using silicon oxide, silicon nitride, silicon nitride oxide, etc. Methods for removing the insulating layer include polishing treatments such as CMP and etching treatments. Either of these may be used. Note that after the formation of the semiconductor region 104, or after device isolation and insulation After the formation of layer 106, the protective layer 102 is removed.

[0061] Next, an insulating layer is formed on the semiconductor region 104, and a layer containing a conductive material is formed on the insulating layer. ru.

[0062] The insulating layer will later become the gate insulating layer, and can be obtained using methods such as CVD or sputtering. Silicon oxide, silicon nitride, silicon nitride, hafnium oxide, aluminum oxide A single-layer or multi-layer structure of a film containing aluminum, tantalum oxide, etc. is preferable. By oxidizing and nitriding the surface of the semiconductor region 104 through lazma treatment or thermal oxidation treatment, The above insulating layer may be formed. High-density plasma treatment can be performed using, for example, He, Ar, Kr, X This process is carried out using a mixture of gases such as noble gases (e), oxygen, nitrogen oxides, ammonia, nitrogen, and hydrogen. This is possible. Furthermore, the thickness of the insulating layer is not particularly limited, but for example, 1 nm to 100 nm. It can be less than or equal to m.

[0063] The layer containing conductive material is made of metallic materials such as aluminum, copper, titanium, tantalum, and tungsten. It can be formed using semiconductor materials such as polycrystalline silicon containing conductive materials. A layer containing a conductive material may be formed using [a specific method]. The formation method is not particularly limited and may include vapor deposition, C [another specific method]. Various film deposition methods such as the VD method, sputtering method, and spin coating method can be used. In this embodiment, an example of forming a layer containing a conductive material using a metal material is described below. This shall be shown.

[0064] Subsequently, the insulating layer and the layer containing the conductive material are selectively etched to form the gate insulating layer 108 a. Form the gate electrode 110a (see Figure 3(C)).

[0065] Next, an insulating layer 112 is formed to cover the gate electrode 110a (see Figure 3(C)). Then, By adding phosphorus (P) or arsenic (As) to the semiconductor region 104, impurity regions with shallow junction depths are created. Region 114 is formed (see Figure 3(C)). Note that here an n-type transistor is formed. Although phosphorus and arsenic are added for this purpose, when forming a p-type transistor, boron (B) or Adding impurity elements such as aluminum (Al) is sufficient. As a result, a channel formation region 116 is formed below the gate insulating layer 108a of the semiconductor region 104. This is formed (see Figure 3(C)). Here, the concentration of the added impurities can be set as appropriate. It is possible, but when semiconductor devices are miniaturized to a high degree, it is desirable to increase the concentration. Furthermore, in this process, the impurity region 114 is formed after the insulating layer 112 is formed. Although this method is used, it is also acceptable to form the insulating layer 112 after forming the impurity region 114. stomach.

[0066] Next, the sidewall insulating layer 118 is formed (see Figure 3(D)). Layer 118 is formed to cover the insulating layer 112, and then an insulating layer is formed to provide high anisotropy to the insulating layer. By applying an etching process, it can be formed in a self-aligned manner. The insulating layer 112 is partially etched, and the upper surface of the gate electrode 110a and the impurity region are removed. It would be good to expose the top surface of 114.

[0067] Next, cover the gate electrode 110a, impurity region 114, sidewall insulating layer 118, etc. Then, an insulating layer is formed. And in the region in contact with the impurity region 114, phosphorus (P) and arsenic (As), etc., are added to form a high-concentration impurity region 120 (see Figure 3(E)). Next, the above insulating layer is removed, and the gate electrode 110a, sidewall insulating layer 118, high concentration A metal layer 122 is formed to cover the pure material region 120, etc. (see Figure 3(E)). 122 uses various film deposition methods such as vacuum deposition, sputtering, and spin coating. It can be formed. The metal layer 122 reacts with the semiconductor material constituting the semiconductor region 104. Therefore, it is desirable to form it using a metal material that results in a low-resistance metal compound. Examples of related materials include titanium, tantalum, tungsten, nickel, cobalt, and platinum. These include:

[0068] Next, heat treatment is performed to react the metal layer 122 with the semiconductor material. This results in high A metal compound region 124 is formed adjacent to the concentration impurity region 120 (see Figure 3(F)). Furthermore, if polycrystalline silicon or the like is used as the gate electrode 110a, A metal compound region will also be formed in the area of ​​0a that is in contact with the metal layer 122.

[0069] As for the above heat treatment, for example, heat treatment by irradiation with a flash lamp can be used. Of course, other heat treatment methods may be used, but the chemical reaction involved in the formation of metal compounds is important. To improve controllability, it is desirable to use a method that enables very short heat treatment times. It appears that the above-mentioned metallic compound region is formed by the reaction between a metallic material and a semiconductor material. This is a region in which conductivity is sufficiently enhanced. This allows for a significant reduction in electrical resistance and improvement of the device characteristics. After forming region 124, the metal layer 122 is removed.

[0070] Next, an interlayer insulating layer 126 and an interlayer insulating layer are formed to cover each of the components formed by the above process. Forms 128 (see Figure 3(G)). Interlayer insulating layers 126 and 128 are formed of oxides Silicon nitride, silicon nitride, hafnium oxide, aluminum oxide, tahnix oxide It can be formed using inorganic insulating materials such as tin. Also, polyimide, acrylic, etc. It is also possible to form it using organic insulating material. Note that here, the interlayer insulating layer 126 The structure consists of a two-layer configuration with an interlayer insulating layer 128, but the configuration of the interlayer insulating layer is not limited to this. After the formation of the interlayer insulating layer 128, its surface is flattened by CMP or etching. It is desirable to do so.

[0071] Subsequently, an opening is formed in the interlayer insulating layer that extends to the metal compound region 124, and the opening Then, the source electrode or drain electrode 130a and the source electrode or drain electrode 130b are connected. Form (see Figure 3(H)). Source electrode or drain electrode 130a or source electrode or The drain electrode 130b is, for example, subjected to PVD or CVD methods in the region including the opening. After forming the conductive layer, a portion of the conductive layer is removed using methods such as etching or CMP. It can be formed by removal.

[0072] Furthermore, a portion of the above conductive layer can be removed to form the source electrode or drain electrode 130a or source electrode. Alternatively, when forming the drain electrode 130b, the surface is processed to be flat. This is desirable. For example, after forming a thin titanium film or titanium nitride film in the region including the opening, When forming a tungsten film to fill an opening, subsequent CMP (Chemical Polishing) can cause problems. It removes essential elements such as tungsten, titanium, and titanium nitride, while also improving the flatness of the surface. This can be done. In this way, the source electrode or drain electrode 130a, source electrode Alternatively, by planarizing the surface including the drain electrode 130b, a good result can be obtained in a later process. This makes it possible to form suitable electrodes, wiring, insulating layers, semiconductor layers, and so on.

[0073] In this case, the source electrode or drain electrode 130 that comes into contact with the metal compound region 124 Although only a and the source electrode or drain electrode 130b are shown, in this process, The electrode in contact with electrode 110a (for example, electrode 130c in Figure 2) is also included. It can be formed. Source electrode or drain electrode 130a, source electrode or drain There are no particular limitations on the material that can be used as the in electrode 130b; various conductive materials are acceptable. These can be used, for example, molybdenum, titanium, chromium, tantalum, and tungsten. Conductive materials such as aluminum, copper, neodymium, and scandium can be used.

[0074] As a result, a transistor 160 is formed using a substrate 100 containing semiconductor material. After the above process, electrodes, wiring, insulating layers, etc. may be formed. Furthermore, by adopting a multilayer wiring structure consisting of a laminated structure of interlayer insulating layers and conductive layers, high We can provide a semiconductor device with integrated components.

[0075] <Method for fabricating the upper transistor> Next, using Figures 4 and 5, the process of fabricating the transistor 162 on the interlayer insulating layer 128 is described. The process will be explained. Figures 4 and 5 show various electrodes on the interlayer insulating layer 128 and the trap. This shows the manufacturing process for transistor 162, and is therefore located at the bottom of transistor 162. Details regarding transistor 160 and other components have been omitted.

[0076] First, the interlayer insulating layer 128, the source electrode or drain electrode 130a, the source electrode or drain An insulating layer 132 is formed on the rain electrode 130b and electrode 130c (see Figure 4(A)). The marginal layer 132 can be formed using methods such as PVD or CVD. Silicon nitride, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide It can be formed using inorganic insulating materials such as ru.

[0077] Next, the source electrode or drain electrode 130a, source electrode or An opening is formed that extends to the drain electrode 130b and electrode 130c. An opening is also formed in the region where the gate electrode 136d is formed. A conductive layer 134 is formed to embed it (see Figure 4(B)). The above opening is made using a mask. It can be formed by methods such as etching. The mask is a photomask. It can be formed by methods such as exposure. Etching can be done using wet etching. Either etching or dry etching can be used, but from the perspective of microfabrication, dry etching is preferable. It is preferable to use a ching. The conductive layer 134 is formed by methods such as PVD or CVD. This can be done using a film method. Materials that can be used to form the conductive layer 134 include Molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium Examples include conductive materials such as scandium, as well as alloys and compounds of these materials (e.g., nitrides). It is possible.

[0078] More specifically, for example, a thin titanium film is formed in the region including the opening by the PVD method, and CV After forming a thin titanium nitride film using method D, a tungsten film was formed to embed it in the opening. A method can be applied to achieve this. Here, the titanium film formed by the PVD method is The oxide film on the surface is reduced, and the lower electrode (here, the source electrode or drain electrode 130a, sole Function to reduce contact resistance with the drain electrode or electrode 130b, electrode 130c, etc. It has. Furthermore, the titanium nitride film formed thereafter suppresses the diffusion of conductive materials. It has the function of [unclear]. In addition, after forming a barrier film with titanium or titanium nitride, plating is performed. A copper film may be formed according to the law.

[0079] After forming the conductive layer 134, the conductive layer 13 is formed using methods such as etching and CMP. Remove a portion of 4 to expose the insulating layer 132, and then remove electrodes 136a, 136b, and 13 6c, forming the gate electrode 136d (see Figure 4(C)). Note that one of the conductive layers 134 Remove the portion to form electrodes 136a, 136b, 136c, and gate electrode 136d. When doing so, it is desirable to process the surface so that it becomes flat. In this way, insulating layer 132 The surfaces of electrodes 136a, 136b, 136c, and gate electrode 136d are planarized. This allows for the formation of good electrodes, wiring, insulating layers, semiconductor layers, etc., in subsequent processes. This becomes possible.

[0080] Next, insulating layer 132, electrode 136a, electrode 136b, electrode 136c, gate electrode 136d A gate insulating layer 138 is formed to cover it (see Figure 4(D)). Gate insulating layer 138 This can be formed using methods such as CVD or sputtering. Also, the gate insulating layer 138 is silicon oxide, silicon nitride, silicon oxide nitride, silicon oxide nitride, aluminum oxide, oxide It is preferable to form the gate insulation to include hafnium, tantalum oxide, etc. Layer 138 may be a single-layer structure or a multi-layer structure. For example, as a raw material gas By plasma CVD using silane (SiH4), oxygen, and nitrogen, silicon oxide nitride is produced. A gate insulating layer 138 can be formed. The thickness of the gate insulating layer 138 is not particularly limited. However, it is not possible to set it to, for example, 10 nm to 500 nm. For example, a first gate insulating layer with a film thickness of 50 nm or more and 200 nm or less, and the first gate insulating It is preferable to laminate a second gate insulating layer with a thickness of 5 nm to 300 nm on the layer.

[0081] Furthermore, by removing impurities, the oxide semiconductor can be made i-type or substantially i-type (high Purified oxide semiconductors are extremely sensitive to interface states and interface charges, therefore When using oxide semiconductors like the one shown in the image for the oxide semiconductor layer, the interface with the gate insulating layer is important. Therefore, the gate insulating layer 138 in contact with the highly purified oxide semiconductor layer is made of high-grade material. This will require a change in quality.

[0082] For example, high-density plasma CVD using μ-wave (2.45 GHz) is a method that produces dense materials with high dielectric strength. It is suitable in that it can form a high-quality gate insulating layer 138. The close contact between the conductor layer and the high-quality gate insulating layer reduces the interface state and improves the interface properties. Because it can be made into something desirable.

[0083] Of course, if it can form a good insulating layer as a gate insulating layer, then high-purity material Even when using an oxide semiconductor layer, other methods such as sputtering and plasma CVD are used. The method can be applied. Furthermore, the film quality and interface properties can be modified by heat treatment after formation. An insulating layer may be applied. In any case, the film quality of the gate insulating layer 138 is good. Furthermore, it reduces the interface state density with the oxide semiconductor layer, enabling the formation of a good interface. You just need to form it.

[0084] Furthermore, 85℃, 2×10 6 V / cm, 12-hour gate bias thermal stress test (B In the T test, if impurities are added to the oxide semiconductor, the impurities and the oxide semiconductor... The bond with the main component is broken by a strong electric field (B: bias) and high temperature (T: temperature), and is generated. The uncoupled hands induce a drift in the threshold voltage (Vth).

[0085] In contrast, impurities in oxide semiconductors, especially hydrogen and water, are eliminated as much as possible, and as described above, By improving the interface characteristics with the insulating layer, stable transients are achieved even under BT testing. It is possible to obtain the result.

[0086] Next, an oxide semiconductor layer is formed on the gate insulating layer 138, and etching is performed using a mask. The oxide semiconductor layer is processed by methods such as those described above to form island-shaped oxide semiconductor layers 140. (See Figure 4(E)).

[0087] Examples of oxide semiconductor layers include In-Ga-Zn-O, In-Sn-Zn-O, and In-A l-Zn-O series, Sn-Ga-Zn-O series, Al-Ga-Zn-O series, Sn-Al-Zn -O series, In-Zn-O series, Sn-Zn-O series, Al-Zn-O series, In-O series, Sn- It is preferable to use an O-based or Zn-O-based oxide semiconductor layer, particularly an amorphous oxide semiconductor layer. In this embodiment, an In-Ga-Zn-O based oxide semiconductor film is deposited as the oxide semiconductor layer. An amorphous oxide semiconductor layer will be formed using a target by sputtering. Furthermore, by adding silicon to the amorphous oxide semiconductor layer, its crystallization is suppressed. Therefore, for example, a target containing 2% to 10% by weight of SiO2 can be used. A oxide semiconductor layer may be formed.

[0088] For example, an oxide semiconductor layer can be fabricated using the sputtering method. A metal oxide target with zinc as the main component can be used. In addition, In, Ga, and a target for oxide semiconductor film deposition containing Zn (composition ratio: In2O3:Ga2O 3:ZnO=1:1:1[mol%], In:Ga:Zn=1:1:0.5[atom% ]) and other similar materials can also be used. In addition, oxide semiconductor films containing In, Ga, and Zn can be deposited. For targeting, In:Ga:Zn = 1:1:1 [atom%], or In:Ga A target with a composition ratio of Zn=1:1:2 [atom%] may also be used. The packing density of the target for deposition of synthetic semiconductor films is 90% to 100%, preferably 95% or more. (For example, 99.9%). Use an oxide semiconductor film deposition target with a high packing density. This results in the formation of a dense oxide semiconductor layer.

[0089] The formation atmosphere for oxide semiconductor layers can be a noble gas atmosphere (typically argon), an oxygen atmosphere, or... Alternatively, a mixed atmosphere of a noble gas (typically argon) and oxygen is preferable. In particular, impurities such as hydrogen, water, hydroxyl groups, and hydrides are present at a concentration of around ppm (desired). It is preferable to use a high-purity gas that has been reduced to a concentration of approximately ppb.

[0090] During the formation of the oxide semiconductor layer, the substrate is held in a processing chamber under reduced pressure, and the substrate temperature is controlled. The temperature should be between 100°C and 600°C, preferably between 200°C and 400°C. Heat the substrate. By forming an oxide semiconductor layer while doing so, the impurity concentration contained in the oxide semiconductor layer is reduced. It can be reduced. Also, damage caused by sputtering is reduced. And the processing chamber Sputtered gas, from which hydrogen and water have been removed while removing residual moisture from the inside, is introduced, and metal oxides To form an oxide semiconductor layer targeting [the target], in order to remove residual moisture in the processing chamber, It is preferable to use an adsorption-type vacuum pump. For example, a cryopump or an ion pump. A titanium sublimation pump can be used. In addition, as an exhaust means, A cold trap may be added to the pump. Exhaust using a cryopump. The deposition chamber is, for example, a compound containing hydrogen atoms such as water (H2O) (preferably Because compounds containing carbon atoms are exhausted, oxide semiconductors formed in the deposition chamber are affected. The concentration of impurities in the layer can be reduced.

[0091] Forming conditions include, for example, a distance of 100 mm between the substrate and the target, and a pressure of 0.6 Pa, DC power of 0.5 kW, atmosphere is oxygen (oxygen flow rate ratio 100%). These conditions can be applied. Furthermore, when using a pulsed DC power supply, film deposition can be performed. The amount of powdery material (also called particles or dust) that is sometimes generated can be reduced, and the film thickness distribution can be made uniform. Therefore, it is preferable. The thickness of the oxide semiconductor layer is 2 nm or more and 200 nm or less, preferably 5 nm. The thickness should be between 30 nm and 30 nm. Note that the appropriate thickness will vary depending on the oxide semiconductor material used. Therefore, the thickness should be selected appropriately depending on the material being used.

[0092] Furthermore, before forming the oxide semiconductor layer by sputtering, argon gas is introduced and plastic Reverse sputtering is performed to generate sputter, and dust adhering to the surface of the gate insulating layer 138 is removed. It is preferable to remove it. Here, reverse sputtering is defined as in normal sputtering, sputtering Instead of colliding ions with the target, by colliding ions with the treatment surface... This refers to a method of modifying the surface. One method involves colliding ions with the treated surface. A high-frequency voltage is applied to the processing surface in an argon atmosphere to generate plasma near the substrate. There are methods such as [doing something]. Furthermore, instead of an argon atmosphere, an atmosphere of nitrogen, helium, oxygen, etc. can be used. You may use it.

[0093] The above oxide semiconductor layer can be etched using either dry etching or wet etching. You may also use this. Of course, you can also use both in combination. To create the desired shape... To enable etching, etching conditions (etching gas, etching solution, etc.) should be adjusted according to the material. Set the etching time, temperature, etc. as appropriate.

[0094] Etching gases used in dry etching include, for example, chlorine-containing gases (chlorine-based gases, For example, chlorine (Cl2), boron chloride (BCl3), silicon chloride (SiCl4), carbon tetrachloride ( Examples include CCl4, etc. Also, fluorine-containing gases (fluorinated gases, such as carbon tetrafluoride) are used. Fluorine (CF4), sulfur fluoride (SF6), nitrogen fluoride (NF3), trifluoromethane (CHF) 3) etc.), hydrogen bromide (HBr), oxygen (O2), and these gases with helium (He) or Gases to which noble gases such as argone (Ar) have been added may also be used.

[0095] As for dry etching methods, parallel plate type RIE (Reactive Ion Etching) Methods such as the ing method and ICP (Inductively Coupled Plasma: induction) A coupled plasma etching method can be used. It can etch into the desired shape. Etching conditions (amount of power applied to the coil-type electrode, amount of power applied to the electrode on the substrate side) The power consumption, electrode temperature on the substrate, etc., should be set as appropriate.

[0096] The etching solution used for wet etching is a solution of phosphoric acid, acetic acid, and nitric acid, Ammonia Hydrogenated Water (31% hydrogen peroxide by weight: 28% ammonia by weight: water = 5:2:2) These can be used. In addition, etching solutions such as ITO07N (manufactured by Kanto Chemical Co., Ltd.) can be used. It's okay to be there.

[0097] Next, it is desirable to perform a first heat treatment on the oxide semiconductor layer. This first heat treatment This allows for the dehydration or dehydrogenation of the oxide semiconductor layer. The temperature of the first heat treatment is The temperature should be between 300°C and 750°C, preferably above 400°C and below the substrate's strain point. For example, The substrate is introduced into an electric furnace using a resistance heating element, and the oxide semiconductor layer 140 is exposed to a nitrogen atmosphere. A heat treatment is performed at 450°C under atmospheric pressure for 1 hour. During this time, the oxide semiconductor layer 140 is exposed to the atmosphere. This prevents re-introduction of water or hydrogen without physical contact.

[0098] Furthermore, heat treatment equipment is not limited to electric furnaces; it also includes heat conduction from a heated medium such as gas, or It may also be a device that heats the object to be processed by thermal radiation. For example, GRTA(Gas Rapid Thermal Anneal) equipment, LRTA (Lamp Rapid RTA (Rapid Thermal Anneal) for Thermal Anneal devices, etc. A device can be used. The LRTA device uses halogen lamps and metal halide lamps. Lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, high-pressure water A device that heats an object to be processed by radiating light (electromagnetic waves) from a lamp such as a silver lamp. Yes, there is. A GRTA device is a device that performs heat treatment using high-temperature gas. As for the gas, Inert gases such as argon or nitrogen, which do not react with the material being treated during heat treatment. A gas is used.

[0099] For example, as a first heat treatment, a substrate is placed in an inert gas heated to a high temperature of 650°C to 700°C. After adding the inert gas and heating for several minutes, the substrate is removed from the inert gas in a GRTA treatment. It is also possible to use GRTA treatment, which allows for high-temperature heat treatment in a short time. Because it is a heat treatment, it can be applied even under temperature conditions that exceed the strain point of the substrate.

[0100] Furthermore, the first heat treatment mainly uses nitrogen or noble gases (helium, neon, argon, etc.) It is desirable to carry out the procedure in an atmosphere that does not contain water, hydrogen, etc. For example The purity of nitrogen, or noble gases such as helium, neon, and argon, introduced into the heat treatment apparatus, 6N (99.9999%) or higher, preferably 7N (99.99999%) or higher (i.e.) The impurity concentration shall be 1 ppm or less, preferably 0.1 ppm or less.

[0101] Depending on the conditions of the first heat treatment, or the material of the oxide semiconductor layer, the oxide semiconductor layer may crystallize. Furthermore, it may be microcrystalline or polycrystalline. For example, the crystallinity rate may be 90% or more, or 80%. In some cases, a microcrystalline oxide semiconductor layer of % or more may be formed. Also, depending on the conditions of the first heat treatment, Depending on the material of the oxide semiconductor layer, it may become an amorphous oxide semiconductor layer that does not contain crystalline components. There are also combinations.

[0102] Furthermore, microcrystals (with a particle size of 1 nm or less) can be placed on amorphous oxide semiconductors (for example, on the surface of an oxide semiconductor layer). The oxide semiconductor layer will have a mixture of elements smaller than 20 nm (typically between 2 nm and 4 nm). In some cases, it may be the case.

[0103] Furthermore, by arranging microcrystals within an amorphous material, the electrical properties of the oxide semiconductor layer can be altered. It is also possible to use an In-Ga-Zn-O-based oxide semiconductor film deposition target. When forming an oxide semiconductor layer using In2Ga2ZnO7, which has electrical anisotropy, By forming microcrystalline regions with oriented crystal grains, the electrical properties of the oxide semiconductor layer are changed. It is possible.

[0104] More specifically, for example, by orienting the c-axis of In2Ga2ZnO7 to be perpendicular to the surface of the oxide semiconductor layer, the conductivity in the direction parallel to the surface of the oxide semiconductor layer can be improved, and the insulation in the direction perpendicular to the surface of the oxide semiconductor layer can be improved. Further, such a microcrystalline portion has a function of suppressing the intrusion of impurities such as water and hydrogen into the oxide semiconductor layer.

[0105]

[0106] Note that the oxide semiconductor layer having the above-mentioned microcrystalline portion can be formed by surface heating of the oxide semiconductor layer by GRTA treatment. Further, by using a sputtering target in which the content of Zn is smaller than the content of In or Ga, it is possible to form more suitably.

[0107] The first heat treatment for the oxide semiconductor layer 140 can also be performed on the oxide semiconductor layer before being processed into the island-shaped oxide semiconductor layer 140. In that case, after the first heat treatment, the substrate is taken out from the heating device, and a photolithography process is performed.

[0108] Note that since the above heat treatment has the effect of dehydrating and dehydrogenating the oxide semiconductor layer 140, it can also be called a dehydration treatment, a dehydrogenation treatment, or the like. Such a dehydration treatment, dehydrogenation treatment can be performed at a timing such as after forming a source electrode or a drain electrode on the oxide semiconductor layer 140 after forming the oxide semiconductor layer, and then forming a protective insulating layer on the source electrode or the drain electrode. Further, such a dehydration treatment, dehydrogenation treatment may be performed not once but a plurality of times.

[0109] Next, the source electrode or drain electrode 142a is brought into contact with the oxide semiconductor layer 140. A source electrode or drain electrode 142b is formed (see Figure 4(F)). The drain electrode 142a, the source electrode or drain electrode 142b are oxide semiconductor layer 1 After forming a conductive layer to cover 40, selectively etch the conductive layer by It can be formed.

[0109] The conductive layer is produced using PVD methods such as sputtering, or CVD methods such as plasma CVD. It can be formed by [doing something]. Also, the conductive layer material can be aluminum, chromium, copper, Elements selected from tantalum, titanium, molybdenum, and tungsten, or the elements mentioned above, are used as components. Alloys such as manganese, magnesium, zirconium, and beryllium can be used. Materials selected from one or more of the following may be used: aluminum, thorium, or aluminum. In addition to nium, titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and Scandinavian Materials consisting of one or more elements selected from um may be used. The conductive layer is It may be a single-layer structure or a laminated structure of two or more layers. For example, a structure containing silicon. Aluminum film single layer structure, aluminum film with titanium film laminated on top of aluminum film, titanium Examples include a three-layer structure in which a film, an aluminum film, and a titanium film are stacked.

[0110] Here, the exposure used during mask formation for etching includes ultraviolet light, KrF laser light, and ArF Using laser light is preferable.

[0111] The channel length (L) of the transistor is the length between the lower end of the source electrode or drain electrode 142a and the lower end of the source electrode or drain electrode 142a. This is determined by the distance between the source electrode or the lower end of the drain electrode 142b. When performing exposure with a channel length (L) of less than 25 nm, the wavelength is extremely wavy, ranging from a few nanometers to several tens of nanometers. Using short-length extreme ultraviolet light, dew on mask formation Light is used. Exposure with ultra-ultraviolet light has high resolution and a large depth of field. Therefore, later formed It is also possible to set the channel length (L) of the transistor to between 10 nm and 1000 nm. Therefore, the operating speed of the circuit can be increased. Furthermore, because the off-current value is extremely small, the power consumption is low. This prevents the force from becoming too large.

[0112] Furthermore, when etching the conductive layer, care is taken to ensure that the oxide semiconductor layer 140 is not removed. Adjust the materials and etching conditions as appropriate. In this process, a portion of the oxide semiconductor layer 140 is etched, and grooves (recesses) are formed. ) can also form an oxide semiconductor layer having ).

[0113] Furthermore, between the oxide semiconductor layer 140 and the source electrode or drain electrode 142a, and the oxide semiconductor An oxide conductive layer is formed between the conductive layer 140 and the source electrode or drain electrode 142b. It may also be an oxide conductive layer and a source electrode or drain electrode 142a or source electrode or The metal layer for forming the drain electrode 142b is formed continuously (continuous deposition). It is possible. The oxide conductive layer can function as either a source region or a drain region. By providing a conductive oxide layer, the resistance of the source region or drain region can be reduced. This enables high-speed operation of transistors.

[0114] In addition, in order to reduce the number of masks used and the number of processes, exposure is performed such that the transmitted light has multiple intensities. A resist mask may be formed using a multi-tone mask, which is a mask, and the etching process may be performed using this resist mask. The resist mask formed using the multi-tone mask has a shape (step shape) with multiple thicknesses, and the shape can be further deformed by ashing. Therefore, it can be used in multiple etching processes for processing different patterns. That is, with a single multi-tone mask, resist masks corresponding to at least two or more different patterns can be formed. Thus, the number of exposure masks can be reduced, and the corresponding photolithography process can also be reduced, so that the process can be simplified.

[0115] Note that after the above process, it is preferable to perform plasma treatment using a gas such as N2O, N2, or Ar. By this plasma treatment, water or the like adhering to the surface of the exposed oxide semiconductor layer is removed. Also, plasma treatment may be performed using a mixed gas of oxygen and argon.

[0116] Next, without exposing to the atmosphere, a protective insulating layer 144 that contacts a part of the oxide semiconductor layer 140 is formed (see FIG. 4(G)).

[0117] The protective insulating layer 144 can be formed by appropriately using a method such as sputtering that does not mix impurities such as water and hydrogen into the protective insulating layer 144. Also, its thickness should be at least 1 nm or more. Materials that can be used for the protective insulating layer 144 include silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, etc. Also, its structure may be a single-layer structure. ​​​​​​​​​​​​A laminated structure is also acceptable. The substrate temperature when forming the protective insulating layer 144 should be above room temperature and up to 300°C. The following is preferable, and the atmosphere should be a noble gas atmosphere (typically argon) or an oxygen atmosphere. Alternatively, a mixed atmosphere of a noble gas (typically argon) and oxygen is preferred.

[0118] If hydrogen is present in the protective insulating layer 144, the hydrogen may penetrate into the oxide semiconductor layer, and the hydrogen may... This can lead to oxygen abstraction in the oxide semiconductor layer, and the back channel side of the oxide semiconductor layer This can lead to a decrease in resistance and the formation of parasitic channels. Therefore, protective insulating layer 1 It is important to avoid using hydrogen in the formation process of 44, as it contains as little hydrogen as possible. That is the case.

[0119] Furthermore, it is preferable to form the protective insulating layer 144 while removing residual moisture in the processing chamber. The ion semiconductor layer 140 and the protective insulating layer 144 are free from hydrogen, hydroxyl groups, or moisture. This is for the purpose of doing so.

[0120] To remove residual moisture from the processing chamber, it is preferable to use an adsorption-type vacuum pump. For example, cryopumps, ion pumps, and titanium sublimation pumps can be used. It is preferable. Furthermore, as an exhaust method, a turbo pump with a cold trap is used. It is also acceptable. The deposition chamber, which has been evacuated using a cryopump, contains, for example, hydrogen atoms and water (H2 Because compounds containing hydrogen atoms, such as O), are removed, the protective insulation formed in the deposition chamber is The concentration of impurities in layer 144 can be reduced.

[0121] The sputtering gas used when forming the protective insulating layer 144 may be hydrogen, water, hydroxyl groups or Impurities such as hydrides are removed to a concentration of approximately ppm (preferably, approximately ppb). It is preferable to use a highly purified gas.

[0122] Next, a second heat treatment (preferably 20) is performed under an inert gas atmosphere or an oxygen gas atmosphere. It is desirable to perform the procedure at temperatures between 0°C and 400°C (for example, between 250°C and 350°C). Next, a second heat treatment is performed at 250°C for 1 hour under a nitrogen atmosphere. After the second heat treatment, This can reduce variations in the electrical characteristics of the converter.

[0123] Furthermore, even if heat treatment is performed in air at temperatures between 100°C and 200°C for 1 hour to 30 hours Good. This heat treatment may be performed by heating while maintaining a constant heating temperature, or from room temperature to 100°C or higher. The process involves repeatedly raising the temperature to a heating temperature of 200°C or lower, and then lowering it from the heating temperature back to room temperature. This may be done. Alternatively, this heat treatment may be performed under reduced pressure before the formation of the protective insulating layer. Performing heat treatment under reduced pressure can shorten the heating time. Note that this heat treatment is as described above. This can be performed in place of the second heat treatment, or before or after the second heat treatment.

[0124] Next, an interlayer insulating layer 146 is formed on the protective insulating layer 144 (see Figure 5(A)). The marginal layer 146 can be formed using methods such as PVD or CVD. Silicon nitride, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide It can be formed using inorganic insulating materials such as ru. After the formation of the interlayer insulating layer 146, It is desirable to planarize the surface using methods such as CMP or etching.

[0125] Next, the interlayer insulating layer 146, the protective insulating layer 144, and the gate insulating layer 138 are treated with electrode 1 36a, electrode 136b, electrode 136c, source electrode or drain electrode 142a, source An opening is formed that reaches the electrode or drain electrode 142b, and the electrode is embedded in the opening. A conductive layer 148 is formed (see Figure 5(B)). The above opening is made by etching using a mask, etc. It can be formed by the following method. The mask can be formed by methods such as exposure using a photomask. Therefore, it is possible to form it. Etching methods include wet etching and dry etching. Either etching method can be used, but from the perspective of microfabrication, dry etching is recommended. The following is preferable. The conductive layer 148 is formed using a film deposition method such as PVD or CVD. This is possible. Materials that can be used to form the conductive layer 148 include molybdenum, cyanoacrylate, and cyanoacrylate. Tan, chromium, tantalum, tungsten, aluminum, copper, neodymium, scandium Examples include conductive materials, their alloys, and compounds (such as nitrides).

[0126] Specifically, for example, a thin titanium film is formed in the region including the opening by the PVD method, and then the CVD method is applied. After forming a thin titanium nitride film, a tungsten film is formed to fill the opening. The following method can be applied. Here, the titanium film formed by the PVD method is at the interface The oxide film is reduced, and the lower electrode (here, electrode 136a, electrode 136b, electrode 136c, so Contact with the source electrode or drain electrode 142a, source electrode or drain electrode 142b) It has the function of reducing contact resistance. Furthermore, the titanium nitride film that is formed afterward is a conductive material. It has a barrier function that suppresses the diffusion of the material. In addition, a barrier film made of titanium or titanium nitride. After forming the material, a copper film may be formed by a plating method.

[0127] After forming the conductive layer 148, the conductive layer 148 is processed using methods such as etching and CMP. By removing a portion and exposing the interlayer insulating layer 146, electrodes 150a, 150b, and 15 0c, electrode 150d, and electrode 150e are formed (see Figure 5(C)). Note that the above conductive layer 1 Remove a portion of 48 to obtain electrode 150a, electrode 150b, electrode 150c, electrode 150d, electrode When forming 150e, it is desirable to process the surface so that it becomes flat. The interlayer insulating layer 146, electrode 150a, electrode 150b, electrode 150c, electrode 150d, By planarizing the surface of electrode 150e, good electrodes, wiring, and insulation can be achieved in subsequent processes. This makes it possible to form layers, semiconductor layers, and so on.

[0128] Furthermore, an insulating layer 152 is formed, and electrodes 150a, 150b, and 1 An opening is formed that extends to electrode 50c, electrode 150d, and electrode 150e, and the material is embedded in the opening. After forming a conductive layer, a portion of the conductive layer is removed using methods such as etching or CMP. , exposing the insulating layer 152, electrode 154a, electrode 154b, electrode 154c, electrode 154 Form d (see Figure 5(D)). This step is the same as when forming electrode 150a, etc. Since there is some information available, I will omit the details.

[0129] When transistor 162 is fabricated using the method described above, the hydrogen concentration of the oxide semiconductor layer 140 The degree is 5x10 19 / cm 3 The following applies, and the off-current of transistor 162 is 1 × 10⁻⁶. -13 The result is less than A. Such an oxide semiconductor with a sufficiently reduced hydrogen concentration and high purity. By applying the conductive layer 140, a transistor 162 with excellent characteristics can be obtained. Furthermore, it has a transistor 160 made of a material other than an oxide semiconductor at the bottom, and an oxide semiconductor at the top. It is possible to fabricate a semiconductor device with excellent characteristics that has a transistor 162 made of semiconductor material. Cut.

[0130] Furthermore, as a semiconductor material that can be compared to oxide semiconductors, silicon carbide (for example, 4H) is a suitable example. There is -SiC). Oxide semiconductors and 4H-SiC have several things in common. The riah density is one example. Using the Fermi-Dirac distribution at room temperature, oxide semiconductors The number of minority carriers in the body is 10 -7 / cm 3 It is estimated to be of a certain degree, but this is for 4H-SiC. 6.7 x 10 -11 / cm 3 Similarly, this is an extremely low value. Intrinsic carriers of silicon Density (1.4×10 10 / cm 3 Compared to other degrees, the degree is extraordinary. I understand that very well.

[0131] Furthermore, the energy band gap of oxide semiconductors is 3.0~3.5eV, and 4H-S Since the energy bandgap of iC is 3.26 eV, it is a wide-bandgap semiconductor. In this respect, oxide semiconductors and silicon carbide have something in common.

[0132] On the other hand, there is a very significant difference between oxide semiconductors and silicon carbide. This is the process temperature. In semiconductor processes using silicon carbide, it is generally 1500°C to 20°C. Because it requires activation heat treatment at 00°C, stacking with semiconductor elements using other semiconductor materials is not possible. Manufacturing is difficult. At such high temperatures, semiconductor substrates and semiconductor elements will be destroyed. This is for the purpose of [something]. On the other hand, oxide semiconductors have a maximum temperature of 300-500°C (below the glass transition temperature). However, it can be manufactured by heat treatment (around 700°C), and can be integrated using other semiconductor materials. After forming the circuit, it becomes possible to form semiconductor elements using oxide semiconductors.

[0133] Furthermore, unlike with silicon carbide, it is possible to use substrates with low heat resistance, such as glass substrates. It has the advantage of not requiring high-temperature heat treatment. It has the advantage of being able to keep energy costs sufficiently low.

[0134] Furthermore, in oxide semiconductors, the Institute for Solid State Physics (IPSJ) has established DOS (density of state) and other properties. Many studies have been conducted, but these studies do not aim to significantly reduce the use of DOS itself. Not included. In one aspect of the disclosed invention, water or hydrogen, which can cause DOS, is contained in an oxide semiconductor. By further removing impurities, a highly purified oxide semiconductor is produced. This is how DOS itself is created. It is based on the idea of ​​significantly reducing it. And through this, extremely superior industrial This makes it possible to manufacture the product.

[0135] Furthermore, it supplies oxygen to the unbonded metals that occur due to oxygen deficiency, and the oxygen vacancies By reducing DOS, an even higher purity (type i) oxide semiconductor can be achieved. This is also possible. For example, by forming an oxygen-rich oxide film in close proximity to the channel-forming region. By supplying oxygen from the oxide film, it is possible to reduce DOS caused by oxygen vacancies.

[0136] Defects in oxide semiconductors include shallow energy levels of 0.1-0.2 eV below the conduction band due to excess hydrogen, and acid These are thought to be caused by deep energy levels due to a lack of prime elements. Therefore, the technological concept of thoroughly removing hydrogen and supplying sufficient oxygen is correct. cormorant.

[0137] Furthermore, although oxide semiconductors are generally considered to be n-type, in one aspect of the disclosed invention, impurities, In particular, the removal of water and hydrogen is used to achieve the i-type transformation. In this respect, silicon and other materials This is not simply a matter of adding impurities to create an i-type compound, but rather involves a completely new technological concept.

[0138] In this embodiment, the transistor 162 is shown as having a bottom gate structure. However, the present invention is not limited to this. For example, the structure of transistor 162 may be It can also be a top-gate type structure. Furthermore, the structure of transistor 162 can be channel A dual gate electrode having two gate electrode layers arranged above and below the formation region with a gate insulating layer in between. It can also be designed as a Lugate-type structure.

[0139] <Conductivity mechanism of transistors using oxide semiconductors> Here, the conductivity mechanism of an oxide semiconductor transistor is shown using Figures 24 to 27. I will explain this. However, the following explanation is merely one consideration, and the validity of the invention may not be denied based on it. It should be noted that this is not something that can be done.

[0140] Figure 24 shows a dual-gate transistor (thin-film transistor) using an oxide semiconductor. This is a cross-sectional view. An oxide semiconductor is connected to the gate electrode layer (GE1) via a gate insulating layer (GI1). A conductive layer (OS) is provided, and a source electrode (S) and a drain electrode (D) are provided on it. It is also composed of an oxide semiconductor layer (OS), a source electrode (S), and a drain electrode (D A gate insulating layer (GI2) is provided to cover the gate, and the gate is placed on the oxide semiconductor layer (OS). A gate electrode (GE2) is provided via an insulating layer (GI2).

[0141] Figure 25 shows a schematic energy band diagram in the A-A' section of Figure 24. 5(A) makes the potential difference between the source and drain zero (equal potential, V D This shows the case where (=0V) Figure 25(B) shows the case where the potential of the drain is increased relative to the source (V D >0) indicates They are doing it.

[0142] Figure 26 shows a schematic energy band diagram of the cross-section B-B' in Figure 24. Figure 26(A) shows a positive potential (+V) at the gate (G1). G ) is a given state, This shows the ON state where carriers (electrons) flow between the drain and the outlet. Also, see Figure 26. (B) is a negative potential (-V) at the gate (G1). G ) is the given state, and the off state ( This indicates a situation where several carriers are not transmitting data.

[0143] Figure 27 shows the vacuum level and the work function of the metal (φ M ), Relationship of electron affinity (χ) of oxide semiconductors This indicates.

[0144] Conventional oxide semiconductors are n-type, and their Fermi level (E f ) is at the center of the band gap The intrinsic Fermi level (E) is located there. i It is located away from the conduction band and closer to it. In solid semiconductors, some hydrogen is known to act as a donor, and is one of the factors that contribute to n-type semiconductor formation. It is.

[0145] In contrast, the oxide semiconductor according to one aspect of the disclosed invention uses hydrogen, which is a factor in n-type formation, as an acid By removing elements from oxide semiconductors, the oxide semiconductor contains as few elements other than the main components (impurity elements) as possible. By increasing the purity in such a way, it becomes true (type i), or something that is as close to true as possible. In other words, instead of adding impurity elements to make it i-type, impurities such as hydrogen and water are removed as much as possible. The characteristic feature is that by removing certain components, a highly purified type i (intrinsic semiconductor) or something close to it is produced. This is the result. f ) is the true Fermi level (E i ) to the same extent as It is possible.

[0146] Band gap (E) of oxide semiconductors g If the voltage is 3.15 eV, then the electron affinity (χ) is It is said to be 4.3 eV. Work done by titanium (Ti) that makes up the source electrode and drain electrode. The function is approximately equal to the electron affinity (χ) of the oxide semiconductor. In this case, it is a metal-oxide semiconductor. At the interface, no Schottky-type barrier is formed for electrons.

[0147] That is, the work function of the metal (φ M If the electron affinity (χ) of the oxide semiconductor is equal to that of the two, When a person makes contact, an energy band diagram (schematic diagram) like the one shown in Figure 25(A) is displayed.

[0148] In Figure 25(B), the black circles (●) represent electrons. When a positive potential is applied to the drain, The particles are injected into the oxide semiconductor through the barrier (h) and flow towards the drain. The height of (h) changes depending on the gate voltage and drain voltage, but a positive drain voltage When applied, the height of the barrier in Figure 25(A) without voltage application, i.e., the bandgap, is used. Top (E g It becomes half of that, or lower.

[0149] At this time, as shown in Figure 26(A), electrons are separated from the gate insulating layer and the highly purified oxide semiconductor. It moves near the interface with the body (the lowest, most energetically stable part of the oxide semiconductor).

[0150] Furthermore, as shown in Figure 26(B), when a negative potential is applied to the gate electrode (G1), a decimal Since the number of holes, which act as carriers, is virtually zero, the current will be extremely close to zero.

[0151] In this way, high purity is achieved by minimizing the presence of elements other than the main components of oxide semiconductors (impurity elements). By degree conversion, it becomes intrinsic (type i) or substantially intrinsic, thus the gate insulating layer The interfacial properties with the semiconductor become apparent. Therefore, the gate insulating layer has a good interface with the oxide semiconductor. The ability to form such a thing is required. Specifically, for example, power supply frequencies in the VHF band to microwave band. Insulating layers fabricated by CVD using high-density plasma generated in large quantities, and sputtering It is preferable to use an insulating layer manufactured by law.

[0152] To improve the purity of the oxide semiconductor while ensuring a good interface between the oxide semiconductor and the gate insulating layer. By doing so, for example, the channel width W of the transistor is 1 × 10 4 μm, channel length L In the case of 3 μm, at room temperature, 1 × 10⁻⁶ -13 Off-current less than A, 0.1V / dec. The subthreshold swing value (S value) (gate insulation layer thickness: 100nm) was achieved. It is possible.

[0153] In this way, the oxide semiconductor is processed to minimize the presence of elements other than its main component (impurity elements). Purification can improve the operation of thin-film transistors.

[0154] <Variation> Figures 6 to 9 show modified configurations of the semiconductor device. In the following, the modified configurations are described as follows: This section describes a configuration of transistor 162 that differs from the one described above. The configuration of the Ta160 is the same as described above.

[0155] Figure 6 shows a gate electrode 136d located beneath an oxide semiconductor layer 140, with a source electrode or a gate electrode. The rain electrode 142a, or the source electrode or drain electrode 142b, is located in the oxide semiconductor layer 14 The transistor 162 has a configuration in which it is in contact with the oxide semiconductor layer 140 on the lower surface of 0. An example of a semiconductor device is shown. Note that the planar structure can be modified as appropriate to correspond to the cross-section. Here, we will only show the cross-section.

[0156] A major difference between the configuration shown in Figure 6 and the configuration shown in Figure 2 is the source electrode or the drain electrode. Connection between 142a, the source electrode or drain electrode 142b, and the oxide semiconductor layer 140. There is a position there. In other words, in the configuration shown in Figure 2, on the upper surface of the oxide semiconductor layer 140 , source electrode or drain electrode 142a, or source electrode or drain electrode 142b In contrast to contact, in the configuration shown in Figure 6, on the lower surface of the oxide semiconductor layer 140, Contact with the source electrode or drain electrode 142a, or the source electrode or drain electrode 142b And, due to this difference in contact, the arrangement of other electrodes, insulating layers, etc. may differ. The details of each component are the same as in Figure 2.

[0157] Specifically, the semiconductor device shown in Figure 6 has a gate electrode 13 provided on the interlayer insulating layer 128. 6d, gate insulating layer 138 provided on gate electrode 136d, and gate insulating layer 138 A source electrode or drain electrode 142a is provided above, source electrode or drain electrode Electrode 142b, source electrode or drain electrode 142a, source electrode or drain electrode It has an oxide semiconductor layer 140 in contact with the upper surface of 142b.

[0158] Here, the gate electrode 136d is embedded in the insulating layer 132 formed on the interlayer insulating layer 128. It is provided to be inserted. Also, similar to the gate electrode 136d, the source electrode or drain Electrode 136a is in contact with in electrode 130a and is in contact with source electrode or drain electrode 130b. Electrode 136b is in contact with electrode 130c, and electrode 136c is formed accordingly.

[0159] Furthermore, a protective layer is placed on top of the transistor 162 so as to be in contact with a portion of the oxide semiconductor layer 140. An insulating layer 144 is provided, and an interlayer insulating layer 146 is provided on the protective insulating layer 144. Here, the protective insulating layer 144 and the interlayer insulating layer 146 have a source electrode or drain. An opening is provided that reaches the source electrode 142a, or the drain electrode 142b. Furthermore, through the opening, electrodes 150d and 150e are connected to the source electrode or drain electrode. It is formed in contact with electrode 142a, source electrode or drain electrode 142b. Similar to pole 150d and electrode 150e, the gate insulating layer 138, protective insulating layer 144, and interlayer insulating layer Through the opening provided in layer 146, electrodes 136a, 136b, and 136c are in contact. Electrodes 150a, 150b, and 150c are formed.

[0160] Furthermore, an insulating layer 152 is provided on the interlayer insulating layer 146, and embedded in the insulating layer 152. Electrodes 154a, 154b, 154c, and 154d are provided so as to be inserted. Here, electrode 154a is in contact with electrode 150a, and electrode 154b is in contact with electrode 150 It is in contact with b, and electrode 154c is in contact with electrode 150c and electrode 150d, and electrode 1 Electrode 54d is in contact with electrode 150e.

[0161] Figure 7 shows an example of a semiconductor device configuration having a gate electrode 136d on an oxide semiconductor layer 140. Here, Figure 7(A) shows the source electrode or drain electrode 142a, and the source electrode Alternatively, the drain electrode 142b is located on the lower surface of the oxide semiconductor layer 140. This is an example of a configuration in contact with layer 140, and Figure 7(B) shows the source electrode or drain electrode 142 a, or the source electrode or drain electrode 142b, on the upper surface of the oxide semiconductor layer 140 This is an example of a configuration in which the oxide semiconductor layer 140 is in contact with the other layer.

[0162] The main difference between the configurations shown in Figures 2 and 6 and the configuration shown in Figure 7 is that the oxide semiconductor layer 140 is placed on top of the oxide semiconductor layer 140. The point is that it has a gate electrode 136d. Also, the configuration shown in Figure 7(A) and Figure 7(B) The main difference in configuration is the source electrode or drain electrode 142a, or the source electrode or drain The rain electrode 142b is located on either the lower or upper surface of the oxide semiconductor layer 140. The point is whether or not they make contact. And due to these differences, other electrodes, insulation The arrangement of layers and other elements differs. The details of each component are the same as in Figure 2, etc.

[0163] Specifically, the semiconductor device shown in Figure 7(A) has a source power source provided on the interlayer insulating layer 128. A electrode or drain electrode 142a, a source electrode or drain electrode 142b, and a source electrode Alternatively, contacting the upper surface of the drain electrode 142a, source electrode, or drain electrode 142b An oxide semiconductor layer 140 and a gate insulating layer 138 provided on the oxide semiconductor layer 140 , the gate electrode 136d in the region overlapping with the oxide semiconductor layer 140 on the gate insulating layer 138 and , has.

[0164] Furthermore, in Figure 7(B), the oxide semiconductor layer 140 provided on the interlayer insulating layer 128 and the oxide Source electrode or drain electrode 1 provided so as to be in contact with the upper surface of the material semiconductor layer 140 42a, source electrode or drain electrode 142b, oxide semiconductor layer 140, source electrode Alternatively, provided on the drain electrode 142a and the source electrode or drain electrode 142b The gate insulating layer 138 is superimposed on the oxide semiconductor layer 140 on the gate insulating layer 138. It has a gate electrode 136d in the region.

[0165] Note that in the configuration shown in Figure 7, some components may be omitted compared to the configuration shown in Figure 2, etc. There are (for example, electrode 150a and electrode 154a). In this case, the manufacturing process is simplified and This can also be obtained as a secondary effect. Of course, it is not essential in the configuration shown in Figure 2, etc. It goes without saying that some components can be omitted.

[0166] Figure 8 shows the case where the device size is relatively large, with a gate below the oxide semiconductor layer 140. This is an example of a configuration having electrode 136d. In this case, the requirements for surface flatness and coverage are Since the pressure is relatively gentle, wiring and electrodes are formed so as to be embedded in the insulating layer. It is not necessary. For example, by performing patterning after the formation of the conductive layer, the gate electrode 136 It is possible to form d, etc. Although not shown in the diagram here, transistor 160 It is possible to manufacture the same in the same way.

[0167] The main difference between the configuration shown in Figure 8(A) and the configuration shown in Figure 8(B) is the source electrode or drain. The in electrode 142a, or the source electrode or drain electrode 142b, is located in the oxide semiconductor layer 140 The point is whether contact occurs on the lower surface or the upper surface. Due to these differences, the arrangement of other electrodes, insulating layers, etc., is different. The details of the constituent elements are the same as in Figure 2, etc.

[0168] Specifically, in Figure 8(A), the gate electrode 136d is provided on the interlayer insulating layer 128, A gate insulating layer 138 provided on the gate electrode 136d, and provided on the gate insulating layer 138 Source electrode or drain electrode 142a, source electrode or drain electrode 142 b, and source electrode or drain electrode 142a, source electrode or drain electrode 142b It has an oxide semiconductor layer 140 in contact with the upper surface of

[0169] Furthermore, in Figure 8(B), the gate electrode 136d provided on the interlayer insulating layer 128 and the gate A gate insulating layer 138 provided on electrode 136d, and a gate electrode on gate insulating layer 138. An oxide semiconductor layer 140 is provided in the region overlapping with 136d, and the oxide semiconductor layer 140 Source electrode or drain electrode 142a provided so as to be in contact with the upper surface, source electrode Alternatively, it has a drain electrode 142b.

[0170] Furthermore, in the configuration shown in Figure 8, some components are omitted compared to the configuration shown in Figure 2, etc. This can sometimes happen. In this case as well, the benefit of simplifying the manufacturing process can be obtained.

[0171] Figure 9 shows the case where the device size is relatively large, with a gate on the oxide semiconductor layer 140. This is an example of a configuration having electrode 136d. In this case as well, surface flatness and coverage The requirements are relatively lenient, so wiring and electrodes can be embedded in the insulating layer. It is not necessary to do so. For example, by performing patterning after the formation of the conductive layer, the gate electrode 1 It is possible to form 36d, etc. Although not shown in the diagram here, transistor 1 The same method can be used to manufacture the 60 as well.

[0172] The main difference between the configuration shown in Figure 9(A) and the configuration shown in Figure 9(B) is the source electrode or drain. The in electrode 142a, or the source electrode or drain electrode 142b, is located in the oxide semiconductor layer 140 The point is whether contact occurs on the lower surface or the upper surface. Due to these differences, the arrangement of other electrodes, insulating layers, etc., is different. The details of the constituent elements are the same as in Figure 2, etc.

[0173] Specifically, in Figure 9(A), the source electrode or drain is provided on the interlayer insulating layer 128. A source electrode 142a, a source electrode or drain electrode 142b, and a source electrode or drain Oxide semiconductor in contact with the upper surface of electrode 142a, source electrode, or drain electrode 142b Layer 140, source electrode or drain electrode 142a, source electrode or drain electrode 1 42b, a gate insulating layer 138 provided on the oxide semiconductor layer 140, and gate insulating layer 13 8 has a gate electrode 136d provided in a region that overlaps with the oxide semiconductor layer 140 on the above. ru.

[0174] Furthermore, in Figure 9(B), the oxide semiconductor layer 140 provided on the interlayer insulating layer 128 and the oxide Source electrode or drain electrode 1 provided so as to be in contact with the upper surface of the material semiconductor layer 140 42a, source electrode or drain electrode 142b, and source electrode or drain electrode 14 2a, source electrode or drain electrode 142b, a gate provided on the oxide semiconductor layer 140 A gate insulating layer 138 and an oxide semiconductor layer 140 on the gate insulating layer 138 are provided in the region where they overlap. It has a gate electrode 136d that is kicked.

[0175] Furthermore, in the configuration shown in Figure 9, some components are omitted compared to the configuration shown in Figure 2, etc. This can sometimes happen. In this case as well, the benefit of simplifying the manufacturing process can be obtained.

[0176] As described above, one aspect of the disclosed invention realizes a semiconductor device with a new configuration. In this embodiment, transistors 160 and 162 are stacked to form the transistor. Although an example has been given, the configuration of the semiconductor device is not limited to this. In this configuration, the channel length directions of transistors 160 and 162 are perpendicular to each other. I have explained an example, but the positional relationship between transistor 160 and transistor 162 is not the same. It is not limited. Furthermore, by superimposing transistor 160 and transistor 162 It is permissible to set one up.

[0177] Furthermore, in this embodiment, for the sake of ease of understanding, the semiconductor device is the smallest memory unit (1 bit). As explained above, the configuration of semiconductor devices is not limited to this. Multiple semiconductor devices can be used. By connecting them appropriately, it is also possible to configure more advanced semiconductor devices. For example, the above semiconductor device By using multiple units, it is possible to configure NAND and NOR type semiconductor devices. The configuration is not limited to Figure 1 and can be changed as appropriate.

[0178] The semiconductor device according to this embodiment is extremely efficient due to the low off-current characteristics of the transistor 162. It is possible to retain information for a long period of time. In other words, it is required for DRAM, etc. Refresh operations are unnecessary, and power consumption can be reduced. Furthermore, it is virtually non-volatile. It can be used as a semiconductor device that generates electricity.

[0179] Furthermore, information is written through the switching operation of transistor 162, It does not require high voltage and there are no issues with component degradation. Furthermore, the on / off switching of the transistor... Therefore, because information is written to and erased, high-speed operation can be easily achieved. Also, It is unnecessary to perform an operation to erase information required in flash memory, etc. There are also advantages.

[0180] Furthermore, transistors using materials other than oxide semiconductors are capable of sufficiently high-speed operation, By using this method, it is possible to read the contents of memory at high speed.

[0181] The configurations and methods shown in this embodiment may be combined with the configurations and methods shown in other embodiments as appropriate. They can be used together.

[0182] (Embodiment 2) In this embodiment, as a semiconductor device according to one aspect of the present invention, the circuit configuration of the memory element and Let me explain how it works.

[0183] Figure 10 shows an example of a circuit diagram of a memory element (hereinafter also referred to as a memory cell) in a semiconductor device. The memory cell 200 shown in Figure 10 has a first wiring SL (source line) and a second wiring BL. (Bit line), third wiring S1 (first signal line), fourth wiring S2 (second signal line), The fifth wire WL (word wire), transistor 201 (first transistor), and Transistor 202 (the second transistor) and transistor 203 (the third transistor) It consists of, . Transistors 201 and 203 are made of oxide semiconductors It is formed using external materials, and transistor 202 is formed using an oxide semiconductor. It is.

[0184] Here, the gate electrode of transistor 201 and the source electrode or dot of transistor 202 It is electrically connected to one of the rain electrodes. Also, the first wiring and transistor 2 The source electrode of 01 is electrically connected to the drain electrode of transistor 201, and the transistor The source electrode of the converter 203 is electrically connected. And the second wiring and The drain electrode of transistor 203 is electrically connected to the third wiring and the transistor. The other of the source or drain electrode of 202 is electrically connected to the fourth wiring, The gate electrode of transistor 202 is electrically connected to the fifth wire and the transistor It is electrically connected to the gate electrode of the 203.

[0185] Next, I will explain the operation of the circuit in detail.

[0186] When writing to memory cell 200, set the first wire to 0V, the fifth wire to 0V, and the second wire Set the first wire to 0V and the fourth wire to 2V. When writing data "1", set the third wire to When writing 2V and data "0", the third wire should be set to 0V. At this time, the transistor Transistor 203 will be in the off state, and transistor 202 will be in the on state. Note that when writing is complete... Therefore, before the potential of the third wire changes, the fourth wire is set to 0V, and transistor 20 Turn off setting 2.

[0187] As a result, after writing data "1", the gate electrode of transistor 201 is connected to the gate electrode. The potential of node A (hereinafter referred to as Node A) is approximately 2V, and after writing data "0", the potential of node A becomes approximately 0V. The voltage becomes V. Node A accumulates charge corresponding to the potential of the third wire, but the transistor... Since the off-current of transistor 202 is extremely small, or practically zero, transistor 201 The potential of the gate electrode is maintained for a long time. The timing chart of the write operation An example is shown in Figure 11.

[0188] Next, when reading the memory cells, set the first wire to 0V, the fifth wire to 2V, and the fourth wire to 0V. Set the first wire to 0V, the third wire to 0V, and the read circuit connected to the second wire to the operating state. Let it be in this state. At this time, transistor 203 is in the ON state and transistor 202 is in the OFF state. Yes.

[0189] If the data is "0", meaning node A is at approximately 0V, then transistor 201 is in the off state. Therefore, the resistance between the second wire and the first wire is high. On the other hand, data "1", Since node A is at approximately 2V, transistor 201 is ON, therefore the second The resistance between the wiring and the first wiring will be low. The read circuit will detect the difference in the resistance state of the memory cell. Therefore, the data "0" and "1" can be read. Note that the second wiring during writing is Although it is set to 0V, it is acceptable for it to be in a floating state or charged to a potential above 0V. Readout The third wire was set to 0V at that time, but it was in a floating state or charged to a potential of 0V or higher. That's fine.

[0190] Note that the definitions of data "1" and data "0" are for convenience only, and they could be reversed. Furthermore, the operating voltage mentioned above is just an example. The operating voltage is when the data is "0" and transistor 2 When 01 is in the off state, transistor 201 turns on when the data is "1". Furthermore, transistor 202 is ON during writing and OFF at other times. In addition, it is necessary to select such a configuration so that transistor 203 is turned on when reading. Instead of 2V, you may use the power supply potential VDD of the surrounding logic circuits.

[0191] Figure 12 shows a block of a semiconductor device according to one embodiment of the present invention having an m × n bit memory capacity. The circuit diagram is shown.

[0192] A semiconductor device according to one aspect of the present invention comprises m fifth and fourth wirings and n second wirings Wiring and a third wiring, and multiple memory cells 200(1,1) to 200(m,n) arranged in m vertical rows. Memory cell arrays arranged in a matrix of (rows) x n columns (m, n are natural numbers) 210, the second wiring and third wiring drive circuit 211, and the fourth wiring and fifth wiring drive It is composed of peripheral circuits such as circuit 213 and read circuit 212. A refresh circuit or the like may be provided as part of the circuit.

[0193] Let's consider memory cell 200(i, j) as a representative of each memory cell. Here, 200(i, j) (where i is an integer between 1 and m, and j is an integer between 1 and n) is the second wiring BL(j), third wiring S1(j), fifth wiring WL(i), and fourth wiring S2(i), And are connected to the first wiring respectively. The first wiring is given the first wiring potential Vs. It is also the second wiring BL(1)~BL(n) and the third wiring S1(1)~S1 (n) is the second wiring and the third wiring drive circuit 211 and read circuit 212, and the fifth wiring Lines WL(1) to WL(m) and the fourth wiring S2(1) to S2(m) are the fourth wiring and the fifth They are each connected to the wiring drive circuit 213.

[0194] The operation of the semiconductor device shown in Figure 12 will be explained. In this configuration, line by line writing and Perform a read operation.

[0195] When writing to memory cells 200(i,1) to 200(i,n) in the i-th row, the first Wiring potential Vs is 0V, fifth wiring WL(i) is 0V, second wiring BL(1)~BL(n) Let the voltage be 0V and the voltage of the fourth wire S2(i) be 2V. At this time, transistor 202 is in the ON state. This is the result. The third wiring S1(1)~S1(n) is 2V for the column where data "1" is written, data The column where "0" is written will be set to 0V. Note that when writing is complete, the third wiring S1 (1) Before the potential of (1) S1(n) changes, set the fourth wiring S2(i) to 0V, Turn off the ZISTA 202. Also, the unselected fifth wire is 0V, and the unselected fourth wire... Assume the voltage is 0V.

[0196] As a result, the gate electrode of transistor 201 of the memory cell that wrote data "1" The potential of the connected node (hereinafter referred to as Node A) is approximately 2V, and the data "0" was written. The potential at node A of the memory cell is approximately 0V. Also, the potential at node A of the unselected memory cell is... That remains unchanged.

[0197] When reading memory cells 200(i,1) to 200(i,n) in the i-th row, The wiring potential Vs is 0V, the fifth wiring WL(i) is 2V, the fourth wiring S2(i) is 0V, Set the wiring S1(1) to S1(n) of circuit 3 to 0V and connect it to the second wiring BL(1) to BL(n). The read circuit is set to the operating state. In the read circuit, for example, the resistive state of the memory cell is... Based on the difference in state, the data "0" and "1" can be read. Note that the fifth unselected state The wires are set to 0V, and the fourth wire, which is not selected, is also set to 0V. Note that the second wire during writing is set to 0V. However, it is acceptable if it is in a floating state or charged to a potential of 0V or higher. The third reading The wiring was set to 0V, but it is acceptable if it is in a floating state or charged to a potential above 0V. stomach.

[0198] Note that the definitions of data "1" and data "0" are for convenience only, and they could be reversed. Furthermore, the operating voltage mentioned above is just an example. The operating voltage is when the data is "0" and transistor 2 When 01 is in the off state, transistor 201 turns on when the data is "1". Furthermore, transistor 202 is ON during writing and OFF at other times. In addition, it is necessary to select such a configuration so that transistor 203 is turned on when reading. Instead of 2V, you may use the power supply potential VDD of the surrounding logic circuits.

[0199] Next, another example of the circuit configuration and operation of a memory element according to one aspect of the present invention will be described.

[0200] Figure 13 shows an example of a memory cell circuit in a semiconductor device. The memory cell 22 shown in Figure 13 0 is the first wiring SL, the second wiring BL, the third wiring S1, the fourth wiring S2, and the fifth Wiring WL, transistor 201 (first transistor), and transistor 202 (second It is composed of transistor 203 (the third transistor) and Transistors 201 and 203 are formed using materials other than oxide semiconductors. The transistor 202 is formed using an oxide semiconductor.

[0201] The circuit of memory cell 220 shown in Figure 13 can be compared with the circuit of memory cell 200 shown in Figure 10. Therefore, the direction of the third wiring and the fourth wiring are different. In other words, the memory cell 220 in Figure 13 The circuit arranges the third wire in the fifth wiring direction (row direction) and the fourth wire in the second wiring direction. The configuration is arranged in a column direction.

[0202] Here, the gate electrode of transistor 201 and the source electrode or dot of transistor 202 It is electrically connected to one of the rain electrodes. Also, the first wiring and transistor 2 The source electrode of 01 is electrically connected to the drain electrode of transistor 201, and the transistor The source electrode of the converter 203 is electrically connected. And the second wiring and The drain electrode of transistor 203 is electrically connected to the third wiring and the transistor. The other of the source or drain electrode of 202 is electrically connected to the fourth wiring, The gate electrode of transistor 202 is electrically connected to the fifth wire and the transistor It is electrically connected to the gate electrode of the 203.

[0203] The operation of the memory cell 220 circuit shown in Figure 13 is the same as the operation of the memory cell 200 circuit shown in Figure 10. Since its operation is similar to that of [another system], a detailed explanation will be omitted.

[0204] Figure 14 shows a block of a semiconductor device according to one embodiment of the present invention having an m × n bit memory capacity. The circuit diagram is shown.

[0205] A semiconductor device according to one aspect of the present invention comprises m third and fifth wirings and n second wirings Wiring and a fourth wiring, and multiple memory cells 220(1,1) to 220(m,n) arranged in m vertical rows. Memory cell arrays arranged in a matrix of (rows) x n columns (m, n are natural numbers) 230, the second wiring and fourth wiring drive circuit 231, and the third wiring and fifth wiring drive It is composed of peripheral circuits such as circuit 233 and read circuit 232. A refresh circuit or the like may be provided as part of the circuit.

[0206] The semiconductor device shown in Figure 14 differs from the semiconductor device shown in Figure 12 in that it has a third wiring and a fourth wiring. The wiring directions are different. In other words, the semiconductor device in Figure 14 has the third wiring in the fifth wiring direction ( The wiring is arranged in the row direction, and the fourth wiring is arranged in the second wiring direction (column direction).

[0207] Let's consider memory cell 220(i,j) as a representative of each memory cell. Here, 220(i, j) (where i is an integer between 1 and m, and j is an integer between 1 and n) is the second wiring BL(j), fourth wiring S2(j), fifth wiring WL(i), and third wiring S1(i), And are connected to the first wiring respectively. The first wiring is given the first wiring potential Vs. It is also the second wiring BL(1)~BL(n) and the fourth wiring S2(1)~S2 (n) is the second wiring and the fourth wiring drive circuit 231 and read circuit 232, and the fifth wiring Lines WL(1) to WL(m) and the third wiring S1(1) to S1(m) are the third wiring and the fifth They are each connected to the wiring drive circuit 233.

[0208] The operation of the semiconductor device shown in Figure 14 will be explained. In this configuration, writing is done column by column, and reading is done column by column. Headings should be added to each line.

[0209] When writing to memory cells 220(1,j) to 220(m,j) in column j, the first Wiring potential Vs is 0V, the fifth wiring WL(1)~WL(m) is 0V, and the second wiring BL(j) Let the voltage be 0V and the fourth wire S2(j) be 2V. The third wires S1(1) to S1(m) are... The line to which data "1" is written will be 2V, and the line to which data "0" is written will be 0V. When terminating, before the potential of the third wiring S1(1)~S1(m) changes, the fourth Set wiring S2(j) to 0V and turn off transistor 202. Also, the unselected Wiring 2 is set to 0V, and the unselected fourth wire is also set to 0V.

[0210] As a result, the gate electrode of transistor 201 of the memory cell that wrote data "1" The potential of the connected node (hereinafter referred to as Node A) is approximately 2V, and the data "0" was written. The potential at node A of the memory cell is approximately 0V. Also, the potential at node A of the unselected memory cell is... That remains unchanged.

[0211] To read memory cells 220(i,1) to 220(i,n) in the i-th row, Set the first wire to 0V, the fifth wire WL(i) to 2V, and the fourth wires S2(1) to S2(n) to 0V. The third wiring S1(i) is set to 0V and connected to the second wiring BL(1)~BL(n) The read circuit is set to the operating state. In the read circuit, for example, differences in the resistance state of the memory cells are detected. From this, the data "0" and "1" can be read. Note that the unselected fifth wire is 0V. The unselected third wire is set to 0V. Note that the second wire was set to 0V during writing, It is acceptable if it is in a charging state or charged to a potential of 0V or higher. The third wiring during reading is Although it is set to 0V, it is acceptable for it to be in a floating state or charged to a potential of 0V or higher.

[0212] Note that the definitions of data "1" and data "0" are for convenience only, and they could be reversed. Furthermore, the operating voltage mentioned above is just an example. The operating voltage is when the data is "0" and transistor 2 When 01 is in the off state, transistor 201 turns on when the data is "1". Furthermore, transistor 202 is ON during writing and OFF at other times. In addition, it is necessary to select such a configuration so that transistor 203 is turned on when reading. Instead of 2V, you may use the power supply potential VDD of the surrounding logic circuits.

[0213] Transistors using oxide semiconductors have extremely low off-currents, so we decided to use them. It is possible to retain memory content for an extremely long period of time. In other words, refresh function This eliminates the need for manual operation, or makes it possible to significantly reduce the frequency of refresh operations. Therefore, power consumption can be significantly reduced. Also, even if there is no power supply... It is possible to retain memory content over a long period of time.

[0214] Furthermore, it does not require high voltage for writing information, and there are no issues with component degradation. Because information is written depending on whether the inverter is on or off, high-speed operation is also possible. It can be easily achieved. Also, to erase the information required in flash memory, etc. Another advantage is that it eliminates the need for eye movements.

[0215] Furthermore, transistors using materials other than oxide semiconductors are capable of sufficiently high-speed operation, By using this method, it is possible to read the contents of memory at high speed.

[0216] (Embodiment 3) This embodiment describes an example of a memory element circuit configuration and operation that differs from that of Embodiment 2. explain.

[0217] Figure 15 shows an example of a circuit diagram of a memory cell in a semiconductor device. The memory cell shown in Figure 15. 240 consists of the first wiring SL, the second wiring BL, the third wiring S1, the fourth wiring S2, and the fifth Wiring WL, transistor 201 (first transistor), and transistor 202 (second It consists of two transistors and a capacitive element 204. Transistor 201 is It is formed using materials other than oxide semiconductors, and transistor 202 is an oxide semiconductor. It is formed using [this method].

[0218] Here, the gate electrode of transistor 201 and the source electrode or dot of transistor 202 One electrode of the rain electrode and one electrode of the capacitive element 204 are electrically connected. The first wire and the source electrode of transistor 201 are electrically connected, and the second wire The drain electrode of transistor 201 is electrically connected to the third wiring, and the transistor The source electrode or drain electrode of the zista 202 is electrically connected to the other, and the fourth electrode The wire and the gate electrode of transistor 202 are electrically connected, and the fifth wire and the capacitance element The other electrode of sub-electrode 204 is electrically connected to it.

[0219] Next, I will explain the operation of the circuit in detail.

[0220] When writing to memory cell 240, set the first wire to 0V, the fifth wire to 0V, and the second wire Set the first wire to 0V and the fourth wire to 2V. When writing data "1", set the third wire to When writing 2V and data "0", the third wire should be set to 0V. At this time, the transistor The TA202 will be in the ON state. Note that when writing is complete, the potential of the third wiring will change. Before doing so, set the fourth wire to 0V and turn off transistor 202.

[0221] As a result, after writing data "1", the gate electrode of transistor 201 is connected to the gate electrode. The potential of node A (hereinafter referred to as node A) is approximately 2V, and after writing data "0", the potential of node A is It will be approximately 0V.

[0222] When reading memory cell 240, set the first wire to 0V, the fifth wire to 2V, and the fourth wire to 0V. Set the first wire to 0V, the third wire to 0V, and the read circuit connected to the second wire to the operating state. This is the state in which transistor 202 is in the off state.

[0223] The state of transistor 201 when the fifth wire is set to 2V will be explained. The potential of node A, which determines the state of terminal 201, is determined by the capacitance C1 between the fifth wiring and node A, and the transistor It depends on the gate-source and drain-drain capacitance C2 of the converter 201.

[0224] Figure 16 shows the relationship between the potential of the fifth wiring and the potential of node A. Here, as an example, Assume that when Rangista 201 is off, C1 / C2 >> 1, and when it is on, C1 / C2 = 1. Also, the threshold voltage of transistor 201 is set to 2.5V. The fifth value in the graph shown in Figure 16 Under the condition that the wiring potential is 2V, when the data is "0", node A will be approximately 2V, but ZISTA201 is in the off state. Meanwhile, in the state of data "1", node A is approximately 3.25V. As a result, transistor 201 turns ON. The memory cell is ON when transistor 201 is ON. In the ON state, it is in a low-resistance state, and in the OFF state, it is in a high-resistance state. Therefore, the read circuit is for the memory cell The data "0" and "1" can be read from the difference in resistance. If not, that is, when the potential of the fifth wiring is 0V, then for data "0", node A is approximately 0 In data "1", node A is approximately 2V, and in both cases, transistor 201 is in the OFF state. To become.

[0225] Note that the third wire was set to 0V during reading, but it may be used in a floating state or at a potential of 0V or higher. It's okay if it's charged. Data "1" and data "0" are definitions for convenience, and the reverse is not true. That's fine.

[0226] The operating voltages mentioned above are just examples. The potential of the third wire during writing is the transient after writing. When transistor 202 is in the OFF state, and the potential of the fifth wiring is 0V, transistor 201 Within the range where the device is in the OFF state, you can select the potentials for data "0" and "1" respectively. (During reading) The fifth wiring potential is such that when the data is "0", transistor 201 is in the off state, and You should select the transistor 201 so that it turns ON when the value is set to "1". The threshold voltage of transistor 201 is one example. By changing the state of transistor 201 as described above... Any threshold is acceptable as long as it is within the acceptable range.

[0227] A semiconductor device according to one aspect of the present invention shown in Figure 17 comprises m fifth and fourth wirings, n second and third wires, and multiple memory cells 240(1,1)~(m,n) Memory cells arranged in a matrix of m rows x n columns (where m and n are natural numbers) Array 250, second wiring and third wiring drive circuit 211, fourth wiring and fifth wiring It is composed of peripheral circuits such as the line drive circuit 213 and the read circuit 212. Peripheral circuits such as a refresh circuit may be provided.

[0228] Let's consider memory cell 240(i,j) as a representative of each memory cell. Here, 240(i, j) (where i is an integer between 1 and m, and j is an integer between 1 and n) is the second wiring BL(j), third wiring S1(j), fifth wiring WL(i), and fourth wiring S2(i), And are connected to the first wiring respectively. The first wiring is given the first wiring potential Vs. It is also the second wiring BL(1)~BL(n) and the third wiring S1(1)~S1 (n) is the second wiring and the third wiring drive circuit 211 and read circuit 212, and the fifth wiring Lines WL(1) to WL(m) and the fourth wiring S2(1) to S2(m) are the fourth wiring and the fifth They are each connected to the wiring drive circuit 213.

[0229] The operation of the semiconductor device shown in Figure 17 will be explained. In this configuration, line by line writing and Perform a read operation.

[0230] When writing to memory cells 240(i,1) to 240(i,n) in the i-th row, Set the wiring potential Vs to 0V, the fifth wiring WL(i) to 0V, and the second wiring BL(1)~BL(n Let ) be 0V and the fourth wire S2(i) be 2V. At this time, transistor 202 is ON This is the state. The third wiring S1(1)~S1(n) is 2V for the column where data "1" is written, The column to which "0" is written will be set to 0V. Note that when writing is complete, the third wiring S Before the potential of 1(1) to S1(n) changes, set the fourth wiring S2(i) to 0V, Turn off inverter 202. Also, the unselected fifth wire is 0V, and the unselected fourth wire The line is assumed to be 0V.

[0231] As a result, the gate voltage of transistor 201 of the memory cell that wrote data "1" The potential of the node connected to the pole (hereinafter referred to as Node A) is approximately 2V, after writing data "0". The potential of node A becomes approximately 0V. Also, the potential of node A of the non-selected memory cell remains unchanged. stomach.

[0232] When reading from memory cells 240(i,1) to 240(i,n) in the i-th row, The wiring potential Vs is 0V, the fifth wiring WL(i) is 2V, the fourth wiring S2(i) is 0V, Set the wiring S1(1) to S1(n) of circuit 3 to 0V and connect it to the second wiring BL(1) to BL(n). The read circuit is set to the operating state. At this time, transistor 202 is in the off state. Furthermore, the unselected fifth wire is set to 0V, and the unselected fourth wire is also set to 0V.

[0233] Let's explain the state of transistor 201 during readout. As already explained, If the ZISTA201 is OFF and C1 / C2 >> 1, and ON and C1 / C2 = 1, The relationship between the potential of the fifth wiring and the potential of node A is shown in Figure 16. Also, the transistor The threshold voltage for 201 is set to 2.5V. For unselected memory cells, the potential of the fifth wiring is 0V. Therefore, node A of the memory cell with data "0" is approximately 0V, and node A of the memory cell with data "1" is approximately 0V. Node A of the memory cell becomes approximately 2V, and in both cases, transistor 201 is in the off state. In the i-th row of memory cells, the fifth wiring potential becomes 2V, and therefore the data "0" is present. Node A of the memory cell is at approximately 2V, and transistor 201 is in the off state, but data Node A of the memory cell containing "1" reaches approximately 3.25V, and transistor 201 turns ON. This is the state in which the memory cell is in a low-resistance state when transistor 201 is ON, and high-resistance when it is OFF. It enters a neutral state. As a result, only the memory cells in the i-th row that have data "0" remain active. This results in a low resistance state. The read circuit, due to the difference in load resistance connected to the second wiring, It can read "0" and "1".

[0234] Note that the third wire was set to 0V during reading, but it may be used in a floating state or at a potential of 0V or higher. It's okay if it's charged. Data "1" and data "0" are definitions for convenience, and the reverse is not true. That's fine.

[0235] The operating voltages mentioned above are just examples. The potential of the third wire during writing is the transient after writing. When transistor 202 is in the OFF state, and the potential of the fifth wiring is 0V, transistor 201 Within the range where the device is in the OFF state, you can select the potentials for data "0" and "1" respectively. (During reading) The fifth wiring potential is such that when the data is "0", transistor 201 is in the off state, and You should select the transistor 201 so that it turns ON when the value is set to "1". The threshold voltage of transistor 201 is one example. By changing the state of transistor 201 as described above... Any threshold is acceptable as long as it is within the acceptable range.

[0236] Transistors using oxide semiconductors have extremely low off-currents, so we decided to use them. It is possible to retain memory content for an extremely long period of time. In other words, refresh function This eliminates the need for manual operation, or makes it possible to significantly reduce the frequency of refresh operations. Therefore, power consumption can be significantly reduced. Also, even if there is no power supply... It is possible to retain memory content over a long period of time.

[0237] Furthermore, it does not require high voltage for writing information, and there are no issues with component degradation. Because information is written depending on whether the inverter is on or off, high-speed operation is also possible. It can be easily achieved. Also, to erase the information required in flash memory, etc. Another advantage is that it eliminates the need for eye movements.

[0238] Furthermore, transistors using materials other than oxide semiconductors are capable of sufficiently high-speed operation, By using this method, it is possible to read the contents of memory at high speed.

[0239] Next, another example of the circuit configuration and operation of a memory element according to one aspect of the present invention will be described.

[0240] Figure 18 shows an example of a memory cell circuit in a semiconductor device. The memory cell 26 shown in Figure 18... 0 is the first wiring SL, the second wiring BL, the third wiring S1, the fourth wiring S2, and Wiring WL 5, transistor 201, transistor 202, capacitive element 204, and It is composed of these. Transistor 201 is constructed using materials other than oxide semiconductors. Furthermore, transistor 202 is formed using an oxide semiconductor.

[0241] The circuit of memory cell 260 shown in Figure 18 is different from the circuit of memory cell 240 shown in Figure 15. The direction of the third and fourth wirings is different. That is, in the memory cell 260 in Figure 18, the third The wiring is arranged in the fifth wiring direction (row direction), and the fourth wiring is arranged in the second wiring direction (column direction). It is configured to be placed in a specific location.

[0242] Here, the gate electrode of transistor 201 and the source electrode or dot of transistor 202 One electrode of the rain electrode and one electrode of the capacitive element 204 are electrically connected. The first wire and the source electrode of transistor 201 are electrically connected, and the second wire The drain electrode of transistor 201 is electrically connected to the third wiring, and the transistor The source electrode or drain electrode of the zista 202 is electrically connected to the other, and the fourth electrode The wire and the gate electrode of transistor 202 are electrically connected, and the fifth wire and the capacitance element The other electrode of sub-electrode 204 is electrically connected to it.

[0243] The operation of the memory cell 260 circuit shown in Figure 18 is the same as the operation of the memory cell 240 circuit shown in Figure 15. Since its operation is similar to that of [another system], a detailed explanation will be omitted.

[0244] Figure 19 shows a block of a semiconductor device according to one embodiment of the present invention having an m × n bit memory capacity. The circuit diagram is shown.

[0245] A semiconductor device according to one aspect of the present invention comprises m third and fifth wirings and n second wirings Wiring and a fourth wiring, and multiple memory cells 260(1,1) to 260(m,n) arranged in m vertical rows. Memory cell arrays arranged in a matrix of (rows) x n columns (m, n are natural numbers) 270, and the second wiring and fourth wiring drive circuits 231, and the third wiring and fifth wiring drive It is composed of peripheral circuits such as circuit 233 and read circuit 232. A refresh circuit or the like may be provided as part of the circuit.

[0246] The semiconductor device shown in Figure 19 differs from the semiconductor device shown in Figure 17 in that it has a third wiring and a fourth wiring. The wiring directions are different. In other words, the semiconductor device in Figure 19 has the third wiring in the fifth wiring direction ( The wiring is arranged in the row direction, and the fourth wiring is arranged in the second wiring direction (column direction).

[0247] Let's consider memory cell 260(i,j) as a representative of each memory cell. Here, 260(i, j) (where i is an integer between 1 and m, and j is an integer between 1 and n) is the second wiring BL(j), fourth wiring S2(j), fifth wiring WL(i), and third wiring S1(i), And are connected to the first wiring respectively. The first wiring is given the first wiring potential Vs. It is also the second wiring BL(1)~BL(n) and the fourth wiring S2(1)~S2 (n) is the second wiring and the fourth wiring drive circuit 231 and read circuit 232, and the fifth wiring Lines WL(1) to WL(m) and the third wiring S1(1) to S1(m) are the third wiring and the fifth They are each connected to the wiring drive circuit 233.

[0248] The operation of the semiconductor device shown in Figure 19 is the same as the operation of the semiconductor device shown in Figure 17, Detailed explanations will be omitted.

[0249] Transistors using oxide semiconductors have extremely low off-currents, so we decided to use them. It is possible to retain memory content for an extremely long period of time. In other words, refresh function This eliminates the need for manual operation, or makes it possible to significantly reduce the frequency of refresh operations. Therefore, power consumption can be significantly reduced. Also, even if there is no power supply... It is possible to retain memory content over a long period of time.

[0250] Furthermore, it does not require high voltage for writing information, and there are no issues with component degradation. Because information is written depending on whether the inverter is on or off, high-speed operation is also possible. It can be easily achieved. Also, to erase the information required in flash memory, etc. Another advantage is that it eliminates the need for eye movements.

[0251] Furthermore, transistors using materials other than oxide semiconductors are capable of sufficiently high-speed operation, By using this method, it is possible to read the contents of memory at high speed.

[0252] (Embodiment 4) In this embodiment, an example of a memory element circuit configuration and operation different from those in embodiments 2 and 3 is provided. I will explain about that.

[0253] Figure 20 shows an example of a circuit diagram for a memory cell in a semiconductor device. The memo shown in Figure 20(A) is also included. Recell 280a and memory cell 280b shown in Figure 20(B) are the same as shown in Figure 10. Compared to the Morisel 200 and the memory cell 220 shown in Figure 13, the first transistor and the third This configuration involves reversing the relationship between the series connections of the transistors.

[0254] Here, the memory cell 280a shown in Figure 20(A) is connected to the gate electrode of transistor 201. The source electrode or drain electrode of transistor 202 is electrically connected to Furthermore, the first wiring and the source electrode of transistor 203 are electrically connected. The drain electrode of transistor 203 and the source electrode of transistor 201 are electrically connected. They are connected. And the second wire and the drain electrode of transistor 201 are electrically connected. It is connected to the third wire and the source or drain electrode of transistor 202. This means that the fourth wire and the gate electrode of transistor 202 are electrically connected. The fifth wire and the gate electrode of transistor 203 are electrically connected. It is.

[0255] Furthermore, the memory cell 280b shown in Figure 20(B) is connected to the memory cell circuit shown in Figure 20(A). In comparison, the direction of the third and fourth wiring is different. In other words, as shown in Figure 20(B) In the Morissel circuit, the fourth wire is positioned in the second wiring direction (column direction), and the third wire is positioned in the fifth direction. The configuration is designed to be arranged in the wiring direction (row direction).

[0256] The memory cell 280a shown in Figure 20(A) and the memory cell 280b shown in Figure 20(B) The operation of the path is as follows: memory cell 200 shown in Figure 10 and memory cell 220 shown in Figure 13. Since the operation is similar to that of the previous circuit, a detailed explanation will be omitted.

[0257] (Embodiment 5) In this embodiment, an example of a memory element circuit configuration and operation different from those in Embodiments 2 to 4 is provided. I will explain about that.

[0258] Figure 21 shows an example of a circuit diagram of a memory cell in a semiconductor device. The memory cell shown in Figure 21. The circuit of 290 is compared to the circuit of memory cell 200 in Figure 10, with node A and the first wiring and The configuration includes a capacitive element in between.

[0259] The memory cell 290 shown in Figure 21 has a first wiring SL, a second wiring BL, and a third wiring S1. , the fourth wiring S2, the fifth wiring WL, transistor 201, transistor 202 and It consists of transistor 203 and capacitive element 205. Transistor 201 And transistor 203 is formed using a material other than an oxide semiconductor, Sta202 is formed using an oxide semiconductor.

[0260] Here, the gate electrode of transistor 201 and the source electrode or dot of transistor 202 One electrode of the rain electrode and one electrode of the capacitive element 205 are electrically connected. The first wiring, the source electrode of transistor 201, and the other electrode of capacitive element 205 are They are electrically connected, with the drain electrode of transistor 201 and the saw electrode of transistor 203. The electrode is electrically connected. Then, the second wiring and the dovetail of transistor 203 The in electrode is electrically connected to the third wire and the source electrode of transistor 202. The other end of the drain electrode is electrically connected to the fourth wire and the gate of transistor 202. The electrode is electrically connected to the fifth wire and the gate electrode of transistor 203. They are electrically connected.

[0261] The operation of the memory cell circuit shown in Figure 21 is the same as the operation of the memory cell circuit shown in Figure 10. Therefore, a detailed explanation will be omitted. By having such a capacitive element 205, the holding characteristics are Improve it.

[0262] (Embodiment 6) An example of a readout circuit in a semiconductor device according to one aspect of the present invention will be explained with reference to Figure 22. do.

[0263] The readout circuit shown in Figure 22 includes a transistor 206 and a differential amplifier.

[0264] During reading, terminal A is connected to the second wiring to which the memory cell to be read is connected. Furthermore, a bias voltage Vbias is applied to the gate electrode of transistor 206, and a predetermined To pass an electric current through.

[0265] Memory cells have different resistances depending on whether they store "1" or "0" data. Specifically, select When transistor 201 of the memory cell is ON, it enters a low-resistance state, and the selected memory When the Morissel transistor 201 is in the off state, it enters a high-resistance state.

[0266] When the memory cell is in a high-resistance state, the potential of terminal A becomes higher than the reference potential Vref, and the differential The output of the lamp outputs the data "1". On the other hand, when the memory cell is in a low-resistance state, the terminal When the potential of child A becomes lower than the reference potential Vref, the differential amplifier outputs the data "0". To be empowered.

[0267] In this way, the read circuit can read data from the memory cell. The readout circuit in this embodiment is just one example. Other known circuits may be used. For example, pre A charging circuit may be included. A second reference wire may be connected instead of the reference potential Vref. A configuration like this is also acceptable. A latching sense amplifier can be used instead of a differential amplifier.

[0268] (Embodiment 7) In this embodiment, an example of an electronic device equipped with the semiconductor device obtained in the previous embodiment is described below. This will be explained using Figure 23. The semiconductor device obtained in the previous embodiment does not have a power supply. Even in such cases, it is possible to retain information. Furthermore, no degradation occurs due to writing and erasing. Furthermore, its operation is also high-speed. For this reason, a new configuration of electric device can be created using this semiconductor device. It is possible to provide sub-devices. Furthermore, the semiconductor device according to the above embodiment is integrated These components are then mounted on circuit boards and installed inside various electronic devices.

[0269] Figure 23(A) shows a notebook-type personal computer including a semiconductor device according to the above embodiment. It is a data system consisting of the main unit 301, the casing 302, the display unit 303, the keyboard 304, etc. This has been done. A semiconductor device according to one aspect of the present invention is used in a notebook-type personal computer. By applying this technology, it becomes possible to retain information even when there is no power supply. Also, There is no degradation associated with writing and erasing. Furthermore, the operation is also fast. For this reason, It is preferable to apply a semiconductor device according to one embodiment of the invention to a notebook-type personal computer. That is the case.

[0270] Figure 23(B) shows a personal digital assistant (PDA) including a semiconductor device according to the previous embodiment. The main unit 311 includes a display unit 313, an external interface 315, and operation buttons 314, etc. A stylus 312 is provided as an accessory for operation. By applying the semiconductor device mentioned above to a PDA, information can be retained even when there is no power supply. It is possible to do so. Furthermore, no degradation occurs due to writing and erasing. Moreover, its operation is It is high-speed. For this reason, it is preferable to apply a semiconductor device according to one aspect of the present invention to a PDA. That is the case.

[0271] Figure 23(C) shows an example of an electronic paper including a semiconductor device according to the above embodiment, This shows the e-book 320. The e-book 320 is housed in two enclosures, enclosure 321 and enclosure 323. It is constructed such that the housing 321 and housing 323 are integrated by the shaft portion 337. The shaft portion 337 can be used as an axis for opening and closing operations. With this configuration, ebooks 320 can be used like a paper book. Semiconductor device according to one aspect of the present invention By applying this to electronic paper, it is possible to retain information even when there is no power supply. It is capable of handling data. Furthermore, there is no degradation associated with writing or erasing data. Moreover, its operation is high-speed. Therefore, it is preferable to apply a semiconductor device according to one aspect of the present invention to electronic paper. ru.

[0272] The display unit 325 is incorporated into the housing 321, and the display unit 327 is incorporated into the housing 323. The display units 325 and 327 may be configured to display a continuation screen, or differently. It is also possible to configure the system to display a different screen. By configuring the system to display different screens, for example, Text is displayed on the right-hand display unit (display unit 325 in Figure 23(C)), and on the left-hand display unit (Figure 23 (C) allows an image to be displayed on the display unit 327).

[0273] Furthermore, Figure 23(C) shows an example in which the housing 321 is equipped with an operating section, etc. The body 321 is equipped with a power supply 331, operation keys 333, speaker 335, etc. Pages can be turned using -333. Note that the keyboard and port are located on the same surface as the display unit. The configuration may also include input devices, etc. Connection terminals (earphone jack, USB terminal, or AC adapter and USB cable, etc.) The configuration may also include terminals that can be connected to various cables, a recording medium insertion section, and so on. Furthermore, eBook 320 may be configured to also function as an electronic dictionary.

[0274] Furthermore, the e-book 320 may be configured to transmit and receive information wirelessly. It is also possible to configure the system to allow users to purchase and download desired book data from a sub-book server. It is possible.

[0275] Furthermore, electronic paper can be applied to any field that displays information. For example, in addition to ebooks, there are posters, advertisements on trains and other vehicles, and credit cards. This can be applied to displays on various types of cards, such as TCG cards.

[0276] Figure 23(D) shows a mobile phone including a semiconductor device according to the previous embodiment. The telephone consists of two housings, housing 340 and housing 341. Housing 341 is front Display panel 342, speaker 343, microphone 344, pointing device 3 It is equipped with 46, a camera lens 347, an external connection terminal 348, etc. Also, the housing 340 This includes a solar cell 349 for charging the mobile phone, an external memory slot 350, etc. It is equipped with. Furthermore, the antenna is built into the housing 341. Semiconductor according to one aspect of the present invention By applying the device to a mobile phone, information can be retained even when there is no power supply. This is possible. Furthermore, there is no degradation associated with writing and erasing. Moreover, the operation is also high-speed. Therefore, it is preferable to apply a semiconductor device according to one aspect of the present invention to a mobile phone. be.

[0277] The display panel 342 has a touch panel function, and the image displayed in Figure 23(D) is Multiple operation keys 345 are shown with dotted lines. Note that the mobile phone has a solar cell 34 A boost circuit is implemented to increase the voltage output from 9 to the voltage required for each circuit. Furthermore, in addition to the above configuration, the configuration will incorporate a contactless IC chip, a small recording device, etc. It's also possible.

[0278] The display panel 342 changes its orientation as appropriate depending on the usage mode. Since the camera lens 347 is located on the same plane as 42, video calls are possible. Speaker 343 and microphone 344 are not limited to voice calls, but also video calls, recording, and playback. Raw materials can be used. Furthermore, the housing 340 and housing 341 slide together, as shown in Figure 23(D). It can be transformed from an unfolded state to an overlapping state, and can be made smaller for portability. It is Noh.

[0279] External connection terminal 348 can be connected to various cables such as AC adapters and USB cables. It also enables charging and data communication. In addition, the external memory slot 350 can be used for recording media. By inserting this, it can handle the storage and movement of larger amounts of data. In addition to the above functions, It may also be equipped with infrared communication capabilities, television reception capabilities, etc.

[0280] Figure 23(E) shows a digital camera including a semiconductor device according to the previous embodiment. The digital camera consists of the main unit 361, the display unit (A) 367, the eyepiece 363, and the operation switch 364. It consists of a display unit (B) 365, a battery 366, and the like. One aspect of the present invention By applying the semiconductor device to a digital camera, information can be transmitted even when there is no power supply. It is possible to retain it. Furthermore, no degradation occurs due to writing or erasing. Its operation is also fast. For this reason, a semiconductor device according to one aspect of the present invention is suitable for a digital camera. It is preferable to use it.

[0281] Figure 23(F) shows a television apparatus including a semiconductor device according to the previous embodiment. In the vision device 370, the display unit 373 is incorporated into the housing 371. This makes it possible to display video. Note that here, the enclosure is connected by stand 375. This shows the configuration that supported 371.

[0282] The television device 370 can be operated using the control switches on the housing 371 or a separate remote control. This can be done using the control unit 380. The operation keys 379 on the remote control unit 380 This allows you to control the channel and volume, and manipulate the image displayed on the display unit 373. It is possible to output from the remote control unit 380 to the remote control unit 380. A configuration may also be provided that includes a display unit 377 for displaying the information. Semiconductor according to one aspect of the present invention By applying this device to a television system, information can be retained even when there is no power supply. It is possible to do so. Furthermore, no degradation occurs due to writing and erasing. Moreover, its operation is It is high-speed. For this reason, a semiconductor device according to one aspect of the present invention is applied to a television apparatus. This is preferable.

[0283] Furthermore, it is preferable that the television equipment 370 be configured to include a receiver, modem, etc. The receiver can receive regular television broadcasts. It can also receive broadcasts via a modem. By connecting to a wired or wireless communication network, one-way communication (from sender to receiver) is possible. (Sender) or two-way information communication (between sender and receiver, or between receivers, etc.) This is possible.

[0284] The configurations and methods shown in this embodiment may be combined with the configurations and methods shown in other embodiments as appropriate. Can be used together [Explanation of Symbols]

[0285] 100 circuit boards 102 Protective layer 104 Semiconductor field 106 element isolation insulating layer 108a Gate Insulation Layer 110a Shuttle bus 112 Insulating layer 114 Impurity region 116 Channel formation region 118 Sidewall insulation layer 120 High concentration impurity region 122 Metal layer 124 Metal compound area 126 Interlayer insulating layer 128 Interlayer insulating layer 130a Source electrode or drain electrode 130b Source electrode or drain electrode 130c electrode 130d electrode 132 Insulating layer 134 Conductive layer 136a electrode 136b Electrode 136c electrode 136d Gate 138 Gate Insulation Layer 140 Oxide semiconductor layer 142a Source electrode or drain electrode 142b Source electrode or drain electrode 144 Protective insulating layer 146 Interlayer insulating layer 148 Conductive layer 150a electrode 150b electrode 150c electrode 150d electrode 150e electrode 152 Insulating layer 154a electrode 154b electrode 154c electrode 154d electrode 154e electrode 160 transistors 162 transistors 200 memory cells 201 Transistors 202 transistors 203 Transistors 204 Capacitive element 205 Capacitive element 206 transistors 210 memory cell array 211 Second wiring and third wiring drive circuit 212 Readout Circuit 213 Fourth and fifth wiring drive circuits 220 memory cells 230 memory cell array 231 Second wiring and fourth wiring drive circuit 232 Readout Circuit 233 Third Wiring and Fifth Wiring Drive Circuit 240 memory cells 250 memory cell array 260 memory cells 270 memory cell array 280a memory cell 280b memory cell 290 memory cells 301 Main Unit 302 enclosures 303 Display section 304 Keyboard 311 Main Unit 312 Stylus 313 Display section 314 Operation buttons 315 External Interface 320 eBooks 321 cabinet 323 enclosures 325 Display section 327 Display section 331 Power supply 333 Operation Keys 335 speakers 337 Shaft 340 cabinets 341 cabinets 342 Display Panel 343 speakers 344 Microphone 345 Operation Keys 346 Pointing devices 347 Camera Lenses 348 External connection terminals 349 solar cells 350 external memory slots 361 Main Unit 363 Eyepiece 364 Operation Switches 365 Display section (B) 366 Battery 367 Display section (A) 370 Television equipment 371 cabinets 373 Display section 375 Stand 377 Display section 379 Operation Keys 380 Remote Control Unit

Claims

[Claim 1] The first wiring and, The second wiring and The third wiring and The fourth wiring and It has a fifth wiring, Multiple memory elements are connected in parallel between the first wiring and the second wiring. One of the aforementioned plurality of memory elements is A first transistor having a first gate electrode, a first source electrode, and a first drain electrode, A second transistor having a second gate electrode, a second source electrode, and a second drain electrode, A third transistor having a third gate electrode, a third source electrode, and a third drain electrode, It has, The first transistor is provided on a substrate containing a semiconductor material, The second transistor is composed of an oxide semiconductor layer, The first gate electrode and either the second source electrode or the second drain electrode are electrically connected. The first wiring and the first source electrode are electrically connected. The first drain electrode and the third source electrode are electrically connected. The second wiring and the third drain electrode are electrically connected. The third wiring and the other of the second source electrode or the second drain electrode are electrically connected. The fourth wiring and the second gate electrode are electrically connected. A semiconductor device in which the fifth wiring and the third gate electrode are electrically connected.

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