Method for manufacturing semiconductor devices

Abstract

This invention provides a method for modifying insulating films. [Solution] The method comprises a first step of preparing an insulating film containing hydrogen, and a second step of removing hydrogen as water molecules from the insulating film by microwave treatment, thereby reducing the hydrogen content in the insulating film. The microwave treatment is performed using oxygen gas and argon gas in a temperature range of 200°C to 300°C, and the ratio of the flow rate of oxygen gas to the sum of the flow rates of oxygen gas and argon gas is preferably greater than 0% and 50% or less.

Description

[Technical Field]

[0001] One aspect of the present invention relates to a transistor, a semiconductor device, and electronic equipment. Another aspect of the present invention relates to a method for manufacturing a semiconductor device. Another aspect of the present invention relates to a semiconductor wafer and a module.

[0002] In this specification, the term "semiconductor device" refers to any device that can function by utilizing semiconductor properties. Semiconductor elements such as transistors, as well as semiconductor circuits, computing devices, and memory devices, are all forms of semiconductor devices. Display devices (such as liquid crystal displays and light-emitting displays), projection devices, lighting devices, electro-optical devices, energy storage devices, memory devices, semiconductor circuits, imaging devices, and electronic devices may also be considered to have semiconductor devices.

[0003] Furthermore, one aspect of the present invention is not limited to the above-mentioned technical field. One aspect of the invention disclosed herein relates to a product, a method, or a method of manufacture. Another aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter. [Background technology]

[0004] In recent years, semiconductor device development has progressed, with LSIs, CPUs, and memory being the main components used. A CPU is an assembly of semiconductor elements that have semiconductor integrated circuits (at least transistors and memory) formed on chips by processing semiconductor wafers, and electrodes that serve as connection terminals are formed on them.

[0005] Semiconductor circuits (IC chips) such as LSIs, CPUs, and memory are mounted on circuit boards, such as printed circuit boards, and used as components in various electronic devices.

[0006] Furthermore, the technology of constructing transistors using semiconductor thin films formed on substrates with insulating surfaces is attracting attention. These transistors are widely applied in electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices). While silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, oxide semiconductors are attracting attention as other materials.

[0007] Furthermore, transistors using oxide semiconductors are known to have extremely low leakage current in the non-conductive state. For example, Patent Document 1 discloses a low-power CPU that utilizes the low leakage current characteristic of transistors using oxide semiconductors. Also, for example, Patent Document 2 discloses a memory device that can retain its contents for a long period of time by utilizing the low leakage current characteristic of transistors using oxide semiconductors.

[0008] Furthermore, in recent years, with the miniaturization and weight reduction of electronic devices, there has been an increasing demand for even higher density integrated circuits. There is also a need to improve the productivity of semiconductor devices, including integrated circuits. [Prior art documents] [Patent Documents]

[0009] [Patent Document 1] Japanese Patent Publication No. 2012-257187 [Patent Document 2] Japanese Patent Publication No. 2011-151383 [Overview of the Initiative] [Problems that the invention aims to solve]

[0010] One aspect of the present invention aims to provide a method for modifying an insulating film. Another aspect of the present invention aims to provide a method for reducing the hydrogen concentration in an insulating film. Another aspect of the present invention aims to provide a semiconductor device with less variation in transistor characteristics and a method for manufacturing the same. Another aspect of the present invention aims to provide a semiconductor device with good electrical characteristics and a method for manufacturing the same. Another aspect of the present invention aims to provide a semiconductor device with good reliability and a method for manufacturing the same. Another aspect of the present invention aims to provide a semiconductor device with high on-current and a method for manufacturing the same. Another aspect of the present invention aims to provide a semiconductor device with high field-effect mobility and a method for manufacturing the same. Another aspect of the present invention aims to provide a semiconductor device with good frequency characteristics and a method for manufacturing the same. Another aspect of the present invention aims to provide a semiconductor device that can be miniaturized or highly integrated and a method for manufacturing the same. Another aspect of the present invention aims to provide a semiconductor device with low power consumption and a method for manufacturing the same.

[0011] Furthermore, the description of these problems does not preclude the existence of other problems. Moreover, one aspect of the present invention does not need to solve all of these problems. Other problems will naturally become apparent from the description in the specification, drawings, and claims, and it is possible to extract other problems from the description in the specification, drawings, and claims. [Means for solving the problem]

[0012] One aspect of the present invention is a method for modifying an insulating film, comprising a first step of preparing an insulating film containing hydrogen, and a second step of removing hydrogen as water molecules from the insulating film by microwave treatment, thereby reducing the hydrogen concentration in the insulating film.

[0013] Furthermore, one aspect of the present invention is a method for modifying an insulating film, comprising: a first step of preparing an insulating film having OH groups bonded to silicon (Si); and a second step of removing the OH groups as water molecules by microwave treatment of the insulating film, thereby reducing the hydrogen concentration in the insulating film.

[0014] Furthermore, one aspect of the present invention is a method for modifying an insulating film, comprising: a first step of preparing an insulating film having a group of atoms containing hydrogen bonded to silicon (Si); and a second step of reducing the hydrogen concentration in the insulating film by subjecting the insulating film to microwave treatment to remove the hydrogen contained in the group of atoms as water molecules. In this configuration, the group of atoms containing hydrogen is preferably one or more of the following: an OH group, a group of atoms containing carbon and hydrogen, a group of atoms containing oxygen, carbon and hydrogen, and a group of atoms containing nitrogen and hydrogen.

[0015] In the above configuration, microwave processing is performed using oxygen gas and argon gas in a temperature range of 200°C to 300°C, and it is preferable that the ratio of the oxygen gas flow rate to the sum of the oxygen gas flow rates and argon gas flow rates is greater than 0% and 50% or less.

[0016] Furthermore, in the above configuration, the insulating film is preferably a silicon oxide film deposited by the ALD method at a deposition temperature of 200°C to 300°C. Moreover, it is more preferable that the insulating film is deposited by the PEALD method.

[0017] Another aspect of the present invention is a method for manufacturing a semiconductor device, comprising: a first step of forming an oxide semiconductor film; a second step of forming a conductive film on the oxide semiconductor film; a third step of forming an oxide semiconductor layer and a conductive layer by processing the oxide semiconductor film and the conductive film into island shapes; a fourth step of forming a first insulating film on the conductive layer; a fifth step of forming a first conductor and a second conductor from the conductive layer and forming an opening in the first insulating film that reaches the oxide semiconductor layer by processing the first insulating film and the conductive layer; a sixth step of forming a silicon oxide film as a second insulating film by ALD so as to cover the opening; and a seventh step of performing microwave processing in a temperature range of 200°C to 300°C.

[0018] Another aspect of the present invention is a method for manufacturing a semiconductor device, comprising: a first step of forming an oxide semiconductor film; a second step of forming a conductive film on the oxide semiconductor film; a third step of forming an oxide semiconductor layer and a conductive layer by processing the oxide semiconductor film and the conductive film into island shapes; a fourth step of forming a first insulating film on the conductive layer; a fifth step of forming a first conductor and a second conductor from the conductive layer by processing the first insulating film and the conductive layer, and forming an opening in the first insulating film that reaches the oxide semiconductor layer; a sixth step of forming an aluminum oxide film as a third insulating film by ALD so as to cover the opening; a seventh step of forming a silicon oxide film as a second insulating film on the third insulating film by ALD at a film formation temperature of 200°C to 300°C; and an eighth step of performing microwave processing in a temperature range of 200°C to 300°C. In this configuration, it is preferable that the second insulating film has a region in which its film thickness is greater than that of the third insulating film.

[0019] In the above configuration, microwave processing is performed using oxygen gas and argon gas, and it is preferable that the ratio of the oxygen gas flow rate to the sum of the oxygen gas flow rates and argon gas flow rates is greater than 0% and 50% or less.

[0020] Furthermore, in the above configuration, the second insulating film is preferably formed by the PEALD method.

[0021] Furthermore, in the above configuration, it is preferable that the oxide semiconductor film is formed by a sputtering method using a target having one or more selected from In, Ga, or Zn.

[0022] Furthermore, in the above configuration, it is preferable that the first conductor and the second conductor each contain tantalum and nitrogen.

[0023] Furthermore, in the above configuration, it is preferable that the interface between the side surface of the first conductor and the second insulator, and the vicinity of the interface, as well as the interface between the side surface of the second conductor and the second insulator, and the vicinity of the interface, contain a metal oxide, the metal oxide contains tantalum and nitrogen, and the metal oxide has a region with a film thickness of 1.0 nm or more and 4.0 nm or less.

[0024] Another aspect of the present invention is a method for manufacturing a semiconductor device, comprising: a first step of forming an oxide semiconductor layer; a second step of forming a first conductor and a second conductor on the oxide semiconductor layer; a third step of depositing an insulating film on the oxide semiconductor layer; and a fourth step of performing microwave processing in a temperature range of 200°C to 300°C. [Effects of the Invention]

[0025] One aspect of the present invention provides a method for modifying an insulating film. Another aspect of the present invention provides a method for reducing the hydrogen concentration in an insulating film. Another aspect of the present invention provides a semiconductor device with less variation in transistor characteristics and a method for manufacturing the same. Another aspect of the present invention provides a semiconductor device with good electrical characteristics and a method for manufacturing the same. Another aspect of the present invention provides a semiconductor device with good reliability and a method for manufacturing the same. Another aspect of the present invention provides a semiconductor device with high on-current and a method for manufacturing the same. Another aspect of the present invention provides a semiconductor device with high field-effect mobility and a method for manufacturing the same. Another aspect of the present invention provides a semiconductor device with good frequency characteristics and a method for manufacturing the same. Another aspect of the present invention provides a semiconductor device that can be miniaturized or highly integrated and a method for manufacturing the same. Another aspect of the present invention provides a semiconductor device with low power consumption and a method for manufacturing the same.

[0026] Furthermore, the description of these effects does not preclude the existence of other effects. Moreover, one embodiment of the present invention does not need to possess all of these effects. Other effects will naturally become apparent from the description in the specification, drawings, and claims, and it is possible to extract other effects from the description in the specification, drawings, and claims. [Brief explanation of the drawing]

[0027] [Figure 1] Figure 1 is a flowchart showing an example of the procedure for a method of modifying an insulating film according to one aspect of the present invention. [Figure 2] Figure 2 is a top view illustrating a microwave processing apparatus according to one aspect of the present invention. [Figure 3] Figure 3 is a cross-sectional view illustrating a microwave apparatus according to one aspect of the present invention. [Figure 4] Figure 4 is a cross-sectional view illustrating a microwave processing apparatus according to one aspect of the present invention. [Figure 5] Figure 5 is a cross-sectional view illustrating a microwave processing apparatus according to one aspect of the present invention. [Figure 6] Figure 6A is a top view of a semiconductor device according to one embodiment of the present invention. Figures 6B to 6D are cross-sectional views of a semiconductor device according to one embodiment of the present invention. [Figure 7] Figures 7A and 7B are cross-sectional views of a semiconductor device according to one embodiment of the present invention. [Figure 8] Figure 8A illustrates the classification of IGZO crystal structures. Figure 8B illustrates the XRD spectrum of a CAAC-IGZO film. Figure 8C illustrates the micro-electron diffraction pattern of a CAAC-IGZO film. [Figure 9] Figure 9A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 9B to 9D are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 10] Figure 10A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 10B to 10D are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 11] Figure 11A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 11B to 11D are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 12] Figure 12A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 12B to 12D are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 13] Figure 13A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 13B to 13D are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 14] Figure 14A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 14B to 14D are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 15]Figure 15A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 15B to 15D are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 16] Figure 16A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 16B to 16D are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 17] Figure 17A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 17B to 17D are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 18] Figure 18A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 18B to 18D are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 19] Figure 19A is a top view of a semiconductor device according to one embodiment of the present invention. Figures 19B to 19D are cross-sectional views of a semiconductor device according to one embodiment of the present invention. [Figure 20] Figure 20A is a top view of a semiconductor device according to one embodiment of the present invention. Figures 20B to 20D are cross-sectional views of a semiconductor device according to one embodiment of the present invention. [Figure 21] Figure 21A is a top view of a semiconductor device according to one embodiment of the present invention. Figures 21B to 21D are cross-sectional views of a semiconductor device according to one embodiment of the present invention. [Figure 22] Figure 22A is a plan view of a semiconductor device according to one embodiment of the present invention. Figures 22B and 22C are cross-sectional views of a semiconductor device according to one embodiment of the present invention. [Figure 23] Figure 23 is a cross-sectional view showing the configuration of a storage device according to one aspect of the present invention. [Figure 24] Figure 24 is a cross-sectional view showing the configuration of a storage device according to one aspect of the present invention. [Figure 25] Figure 25 is a cross-sectional view of a semiconductor device according to one aspect of the present invention. [Figure 26] Figures 26A and 26B are cross-sectional views of a semiconductor device according to one aspect of the present invention. [Figure 27]Figure 27 is a cross-sectional view of a semiconductor device according to one aspect of the present invention. [Figure 28] Figure 28A is a block diagram showing an example of the configuration of a storage device according to one aspect of the present invention. Figure 28B is a perspective view showing an example of the configuration of a storage device according to one aspect of the present invention. [Figure 29] Figures 29A to 29H are circuit diagrams showing an example of the configuration of a storage device according to one aspect of the present invention. [Figure 30] Figures 30A and 30B are schematic diagrams of a semiconductor device according to one embodiment of the present invention. [Figure 31] Figures 31A and 31B illustrate an example of an electronic component. [Figure 32] Figures 32A to 32E are schematic diagrams of a storage device according to one embodiment of the present invention. [Figure 33] Figures 33A to 33H show an electronic device according to one embodiment of the present invention. [Figure 34] Figure 34A is a schematic diagram of the sample used in the example. Figure 34B shows the TDS analysis results used in the example. [Figure 35] Figure 35 is a schematic diagram of a sample according to the example. [Figure 36] Figures 36A to 36C are cross-sectional STEM images of the sample according to the example. [Figure 37] Figure 37 is a diagram illustrating the oxide film thickness of tantalum nitride according to the example. [Modes for carrying out the invention]

[0028] The embodiments will be described below with reference to the drawings. However, it will be readily apparent to those skilled in the art that the embodiments can be implemented in many different ways, and their form and details can be modified in various ways without departing from the spirit and scope. Therefore, the present invention is not to be construed as being limited to the following embodiments.

[0029] Furthermore, in drawings, size, layer thickness, or area may be exaggerated for clarity. Therefore, they are not necessarily limited to that scale. Also, drawings are schematic representations of ideal examples and are not limited to the shapes or values ​​shown. For example, in actual manufacturing processes, layers or resist masks may be unintentionally reduced due to processes such as etching, but this may not be reflected in the drawings for ease of understanding. Additionally, in drawings, the same reference numerals may be used across different drawings for identical parts or parts with similar functions, and repeated explanations may be omitted. Furthermore, when referring to similar functions, the hatch patterns may be the same, and no specific reference numeral may be assigned.

[0030] Furthermore, in particular, in top views (also called "plan views") or perspective views, descriptions of some components may be omitted to facilitate understanding of the invention. Also, descriptions of some hidden lines may be omitted.

[0031] Furthermore, the ordinal numbers used in this specification, such as "first," "second," etc., are for convenience only and do not indicate the order of processes or stacking. Therefore, for example, "first" can be replaced with "second" or "third," etc., as appropriate in the explanation. Also, the ordinal numbers described in this specification may not be the same as the ordinal numbers used to specify an aspect of the present invention.

[0032] Furthermore, in this specification, terms indicating placement, such as "above" and "below," are used for convenience to explain the positional relationships between components with reference to the drawings. The positional relationships between components change as appropriate depending on the direction in which each component is depicted. Therefore, the terms used are not limited to those described in the specification and can be appropriately rephrased depending on the situation.

[0033] For example, if it is explicitly stated in this specification that X and Y are connected, then the disclosure in this specification includes cases where X and Y are electrically connected, where X and Y are functionally connected, and where X and Y are directly connected. Therefore, it is not limited to predetermined connection relationships, such as those shown in the figures or text, but also includes connection relationships other than those shown in the figures or text. Here, X and Y are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

[0034] Furthermore, in this specification, a transistor is defined as an element having at least three terminals, including a gate, a drain, and a source. It also has a region where a channel is formed between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode) (hereinafter also referred to as the channel-forming region), and current can flow between the source and the drain through the channel-forming region. In this specification, the channel-forming region refers to the region through which current primarily flows.

[0035] Furthermore, the functions of the source or drain may be reversed when transistors of different polarities are used, or when the direction of current changes during circuit operation. For this reason, the terms source and drain may be used interchangeably in this specification.

[0036] The channel length refers to the distance between the source (source region or source electrode) and the drain (drain region or drain electrode) in the region where the semiconductor (or the part of the semiconductor through which current flows when the transistor is ON) and the gate electrode overlap, or in the channel formation region, as seen in a top view of a transistor. It should be noted that the channel length is not necessarily the same in all regions of a single transistor. That is, the channel length of a single transistor may not be a single fixed value. Therefore, in this specification, the channel length is defined as any one value, maximum value, minimum value, or average value in the channel formation region.

[0037] Channel width refers to the length of the channel formation region perpendicular to the channel length direction, for example, in a top view of a transistor, where the semiconductor (or the part of the semiconductor through which current flows when the transistor is ON) and the gate electrode overlap, or within the channel formation region. Note that the channel width is not necessarily the same across all regions in a single transistor. That is, the channel width of a single transistor may not be a single fixed value. Therefore, in this specification, the channel width is defined as any one value, maximum value, minimum value, or average value within the channel formation region.

[0038] In this specification, depending on the transistor structure, the channel width in the region where the channel is actually formed (hereinafter also referred to as the "effective channel width") may differ from the channel width shown in the top view of the transistor (hereinafter also referred to as the "apparent channel width"). For example, when the gate electrode covers the side surface of the semiconductor, the effective channel width may become larger than the apparent channel width, and this effect may not be negligible. For example, in a miniature transistor where the gate electrode covers the side surface of the semiconductor, the proportion of the channel formation region formed on the side surface of the semiconductor may be large. In that case, the effective channel width will be larger than the apparent channel width.

[0039] In such cases, it can be difficult to estimate the effective channel width through actual measurements. For example, estimating the effective channel width from design values ​​requires the assumption that the semiconductor shape is known. Therefore, if the semiconductor shape is not precisely known, it is difficult to accurately measure the effective channel width.

[0040] In this specification, when simply referred to as "channel width," it may refer to the apparent channel width. Alternatively, when simply referred to as "channel width," it may refer to the effective channel width. Note that channel length, channel width, effective channel width, apparent channel width, etc., can be determined by analyzing cross-sectional TEM images, etc.

[0041] Impurities in semiconductors refer to elements other than the main components that make up the semiconductor. For example, elements with a concentration of less than 0.1 atomic percent can be considered impurities. The presence of impurities can cause, for example, an increase in the defect level density of the semiconductor or a decrease in crystallinity. In the case of oxide semiconductors, impurities that alter the properties of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of oxide semiconductors, such as hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Water can also function as an impurity. Furthermore, for example, the inclusion of impurities can cause oxygen vacancies (V) in oxide semiconductors. O (Also known as an oxygen vacancy) may form.

[0042] In this specification, silicon oxide nitride refers to a material whose composition contains more oxygen than nitrogen. Similarly, silicon oxide nitride refers to a material whose composition contains more nitrogen than oxygen. Similarly, aluminum oxide nitride refers to a material whose composition contains more oxygen than nitrogen. Similarly, aluminum oxide nitride refers to a material whose composition contains more nitrogen than oxygen. Similarly, hafnium oxide nitride refers to a material whose composition contains more oxygen than nitrogen. Similarly, hafnium oxide nitride refers to a material whose composition contains more nitrogen than oxygen.

[0043] Furthermore, in this specification, the term "insulator" may be replaced with "insulating film" or "insulating layer." Similarly, the term "conductor" may be replaced with "conductive film" or "conductive layer." Finally, the term "semiconductor" may be replaced with "semiconductor film" or "semiconductor layer."

[0044] Furthermore, in this specification, "parallel" means a state in which two lines are positioned at an angle of -10 degrees or more and 10 degrees or less. Therefore, the case of -5 degrees or more and 5 degrees or less is also included. Also, "approximately parallel" means a state in which two lines are positioned at an angle of -30 degrees or more and 30 degrees or less. Also, "perpendicular" means a state in which two lines are positioned at an angle of 80 degrees or more and 100 degrees or less. Therefore, the case of 85 degrees or more and 95 degrees or less is also included. Also, "approximately perpendicular" means a state in which two lines are positioned at an angle of 60 degrees or more and 120 degrees or less.

[0045] In this specification, "metal oxide" refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also called oxide semiconductors or simply OS), etc. For example, when a metal oxide is used in the semiconductor layer of a transistor, that metal oxide may be referred to as an oxide semiconductor. In other words, when an OS transistor is described, it can be rephrased as a transistor having a metal oxide or oxide semiconductor.

[0046] Furthermore, in this specification, normally off means that when no potential is applied to the gate, or when the gate is given a ground potential, the drain current flowing through the transistor per 1 μm of channel width is 1 × 10⁻¹⁶ at room temperature. -20 A or less, 1 × 10 at 85℃ -18 A or less, or 1 × 10 at 125°C -16 This means being less than or equal to A.

[0047] Furthermore, if upper and lower numerical limits are specified in this specification, configurations in which these limits can be freely combined are also disclosed.

[0048] (Embodiment 1) In this embodiment, a method for modifying an insulating film according to one aspect of the present invention will be described with reference to Figures 1 to 5.

[0049] Figure 1 is a flowchart showing an example of a procedure for modifying an insulating film. The method for modifying an insulating film includes step S01 and step S02, as shown in Figure 1.

[0050] Step S01 is the process of preparing the insulating film 11. The insulating film 11 may be provided on the substrate.

[0051] Step S02 is a step of performing microwave treatment on the insulating film 11. This step can modify the insulating film 11. Modifications to the insulating film 11 include reducing the impurity concentration in the insulating film 11, reducing the defect level density in the insulating film 11, and densifying the insulating film 11.

[0052] Now, let's discuss microwave processing.

[0053] For microwave processing, it is preferable to use a microwave processing apparatus that has a power supply for generating a high-density plasma using microwaves. Here, the frequency of the microwave processing apparatus should be 300 MHz or more and 300 GHz or less, preferably 2.4 GHz or more and 2.5 GHz or less, for example, 2.45 GHz. By using a high-density plasma, a high density of oxygen radicals can be generated. The power of the power supply that applies microwaves to the microwave processing apparatus should be 1000 W or more and 10000 W or less, preferably 2000 W or more and 5000 W or less. The microwave processing apparatus may also have a power supply that applies RF to the substrate side.

[0054] Furthermore, the microwave processing time should be between 3 minutes and 24 hours, preferably between 5 minutes and 2 hours, and more preferably between 10 minutes and 1 hour. Microwave processing exceeding 24 hours is undesirable as it leads to a decrease in productivity.

[0055] Furthermore, microwave processing is preferably carried out under reduced pressure, and the pressure in the deposition chamber should be between 10 Pa and 1000 Pa, preferably between 300 Pa and 700 Pa.

[0056] Furthermore, microwave processing is preferably carried out in an oxygen-containing atmosphere. For example, an oxygen-containing atmosphere may be provided using oxygen gas and argon gas, helium gas, or krypton gas. When using oxygen gas and argon gas as the oxygen-containing atmosphere, the ratio of the oxygen gas flow rate to the sum of the oxygen gas and argon gas flow rates is expressed as the oxygen flow rate ratio (O2 / (O2+Ar)). The oxygen flow rate ratio (O2 / (O2+Ar)) should be greater than 0% and 100% or less, preferably greater than 0% and 50% or less, more preferably between 10% and 40%, and even more preferably between 10% and 30%. Similarly, when using an oxygen-containing atmosphere consisting of oxygen gas and helium gas or krypton gas, the oxygen flow rate ratio (O2 / (O2+He) or O2 / (O2+Kr)) should be greater than 0% and 100% or less, preferably greater than 0% and 50% or less, more preferably 10% to 40%, and even more preferably 10% to 30%.

[0057] The above is an explanation of microwave processing.

[0058] Next, we will explain the modification of the insulating film 11.

[0059] Examples of insulating films applicable to the insulating film 11 include oxide insulating films. Examples of such oxide insulating films include oxide insulating films containing one or more selected from silicon, aluminum, hafnium, zirconium, etc. Specifically, examples include silicon oxide films, aluminum oxide films, hafnium oxide films, zirconium oxide films, oxide films containing aluminum and hafnium, oxide films containing hafnium and zirconium, and oxide films containing silicon and hafnium.

[0060] When the insulating film 11 is a silicon oxide film, the insulating film 11 can be modified by performing microwave treatment in an oxygen-containing atmosphere. Specifically, by performing this microwave treatment, the number of OH groups bonded to silicon (Si) in the insulating film 11 can be reduced. More specifically, at least hydrogen from the OH groups bonded to silicon (Si) can be removed as water molecules. In other words, by performing this microwave treatment, hydrogen in the insulating film 11 can be removed as water molecules. Therefore, the hydrogen concentration in the insulating film 11 can be reduced. When the insulating film 11 is a silicon oxide film, the insulating film 11 becomes an insulating film having at least oxygen and silicon. The oxygen-containing atmosphere is preferably, for example, a mixed atmosphere of oxygen gas and argon gas.

[0061] Hydrogen in silicon oxide films exists as adsorbed water, OH groups bonded to silicon (Si), and other forms. The amount of adsorbed water and OH groups bonded to silicon (Si) in a silicon oxide film can be evaluated using methods such as TDS (Thermal Desorption Spectroscopy) analysis. For example, in the desorption gas profile with a mass-to-charge ratio of m / z = 18 obtained from TDS analysis of a silicon oxide film, peaks indicating desorption up to approximately 200°C, 400°C, and 750°C may be detected. The peaks indicating desorption up to approximately 200°C and 400°C are thought to be related to adsorbed water. The peak indicating desorption up to approximately 750°C is thought to be related to OH groups bonded to silicon (Si). Hereafter, for convenience, in the desorption gas profile with a mass-to-charge ratio of m / z = 18 obtained by TDS analysis of silicon oxide films, the peak that desorbs up to about 200°C may be referred to as the α peak, the peak that desorbs up to about 400°C as the β peak, and the peak that desorbs up to about 750°C as the γ peak.

[0062] The γ peak is a peak that desorbs at temperatures above 400°C, but by microwave treatment of a silicon oxide film in an oxygen-containing atmosphere, the γ peak can be reduced even at treatment temperatures below 400°C. In other words, the OH groups bonded to silicon (Si) can be reduced. This reduces the hydrogen concentration in the silicon oxide film. While higher microwave treatment temperatures can reduce the γ peak more efficiently, the effect of reducing the γ peak can also be obtained at relatively low microwave treatment temperatures. For example, the temperature range for the microwave treatment may be 150°C to 400°C, or 200°C to 300°C, for example, around 250°C.

[0063] Furthermore, silicon oxide films treated with microwaves in an oxygen-containing atmosphere may become denser compared to films that have not undergone such microwave treatment. Specifically, silicon oxide films treated with microwaves may have a slower etching rate compared to films that have not undergone such treatment. The increased density of the silicon oxide film can suppress the diffusion of impurities through the film.

[0064] Furthermore, when a silicon oxide film is deposited by atomic layer deposition (ALD) using an organic precursor (referred to as an organic precursor), hydrogen from the organic precursor is mixed into the silicon oxide film, resulting in a tendency for the hydrogen concentration in the film to be high. The hydrogen in the silicon oxide film exists as hydrogen-containing atomic groups bonded to adsorbed water and silicon (Si). Examples of hydrogen-containing atomic groups include OH groups (hydroxyl groups), alkyl groups containing carbon and hydrogen, alkoxy groups containing oxygen, carbon and hydrogen, and amino groups containing nitrogen and hydrogen. Therefore, by applying microwave treatment to the silicon oxide film, the hydrogen contained in these atomic groups can be removed as water molecules, thereby more effectively modifying the silicon oxide film. In addition, the hydrogen concentration in the silicon oxide film can be reduced.

[0065] Furthermore, when a silicon oxide film is formed by the ALD method using an oxidizing agent containing hydrogen, the hydrogen contained in the oxidizing agent is mixed into the silicon oxide film, so the hydrogen concentration in the film tends to be high. Examples of hydrogen-containing oxidizing agents include water (H2O). Therefore, by performing microwave treatment on the silicon oxide film, the film can be modified more effectively. In addition, the hydrogen concentration in the silicon oxide film can be reduced.

[0066] Furthermore, when the silicon oxide film is deposited at a deposition temperature of, for example, 200°C to 300°C, the hydrogen concentration in the silicon oxide film tends to be high. Therefore, by applying microwave treatment to the silicon oxide film, the film can be modified more effectively. In addition, the hydrogen concentration in the silicon oxide film can be reduced.

[0067] The above is an explanation of the modification of the insulating film 11, using a silicon oxide film as an example. Note that if the insulating film 11 is an oxide insulating film containing at least silicon, the insulating film 11 can be modified by microwave treatment. Similar effects can be expected with oxide insulating films other than silicon oxide films by microwave treatment. In other words, if the insulating film 11 is an oxide insulating film containing one or more metals selected from silicon, aluminum, hafnium, zirconium, etc., it is presumed that the number of hydrogen-containing atomic groups (OH groups, alkyl groups containing carbon and hydrogen, alkoxy groups containing oxygen, carbon and hydrogen, amino groups containing nitrogen and hydrogen, etc.) bonded to the metal (aluminum, hafnium, or zirconium) present in the oxide insulating film can be reduced. Therefore, it is presumed that the hydrogen concentration in the oxide insulating film can be reduced.

[0068] Furthermore, the insulating film applicable to insulating film 11 may be an oxidizing film such as a silicon oxidizing film. By performing microwave treatment on the oxidizing film, the OH groups bonded to silicon (Si) present in the oxidizing film can be reduced. Therefore, the hydrogen concentration in the silicon oxidizing film can be reduced.

[0069] Furthermore, the insulating film 11 may have a laminated structure of two or more layers. In that case, it is not limited to a laminated structure made of the same material, but may be a laminated structure made of different materials. Also, if the insulating film 11 has a laminated structure of two or more layers, it is sufficient that at least one layer of the laminated structure is the insulating film described above.

[0070] Furthermore, microwave treatment may be performed on a structure in which a metal oxide film functioning as a semiconductor is provided near the insulating film 11. The metal oxide film contains metal and oxygen, with hydrogen as an impurity. Therefore, it is expected that the metal oxide film will be modified by performing microwave treatment on the insulating film 11 and the metal oxide film. For example, it is expected that the hydrogen concentration in the metal oxide will be reduced. Examples of the metal oxide film include oxide films containing indium or zinc.

[0071] The above is an explanation of the modification of the insulating film 11.

[0072] <Microwave Processing Equipment> The following describes a microwave processing apparatus that can be used in the above-mentioned method for modifying the insulating film and the semiconductor device fabrication method described later.

[0073] First, we will explain the configuration of a manufacturing equipment that minimizes the inclusion of impurities during the manufacturing of semiconductor devices and other equipment, using Figures 2 to 5.

[0074] Figure 2 schematically shows a top view of a single-wafer multi-chamber manufacturing apparatus 2700. The manufacturing apparatus 2700 includes an atmospheric substrate supply chamber 2701 equipped with a cassette port 2761 for housing substrates and an alignment port 2762 for aligning substrates; an atmospheric substrate transport chamber 2702 for transporting substrates from the atmospheric substrate supply chamber 2701; a load lock chamber 2703a for loading substrates and switching the pressure inside the chamber from atmospheric pressure to reduced pressure or from reduced pressure to atmospheric pressure; an unload lock chamber 2703b for unloading substrates and switching the pressure inside the chamber from reduced pressure to atmospheric pressure or from atmospheric pressure to reduced pressure; a transport chamber 2704 for transporting substrates in a vacuum; and chambers 2706a, 2706b, 2706c, and 2706d.

[0075] Furthermore, the atmospheric substrate transport chamber 2702 is connected to the load lock chamber 2703a and the unload lock chamber 2703b, the load lock chamber 2703a and the unload lock chamber 2703b are connected to the transport chamber 2704, and the transport chamber 2704 is connected to chambers 2706a, 2706b, 2706c, and 2706d.

[0076] Furthermore, gate valves GV are provided at the connection points of each chamber, and each chamber can be independently maintained in a vacuum state, except for the atmospheric substrate supply chamber 2701 and the atmospheric substrate transport chamber 2702. In addition, a transport robot 2763a is provided in the atmospheric substrate transport chamber 2702, and a transport robot 2763b is provided in the transport chamber 2704. Transport robots 2763a and 2763b can transport substrates within the manufacturing apparatus 2700.

[0077] The back pressure (total pressure) in the transport chamber 2704 and each chamber is, for example, 1 × 10⁻⁶ -4 Pa or less, preferably 3 × 10 -5 Pa or less, more preferably 1 × 10⁻⁶ -5 The pressure shall be less than or equal to Pa. Furthermore, the partial pressure of gas molecules (atoms) with a mass-to-charge ratio (m / z) of 18 in the transport chamber 2704 and each chamber shall be, for example, 3 × 10⁻⁶. -5Below Pa, preferably 1×10 -5 Below Pa, more preferably 3×10 -6 Below Pa. Also, the partial pressure of gas molecules (atoms) with m / z of 28 in the transfer chamber 2704 and each chamber is, for example, 3×10 -5 Below Pa, preferably 1×10 -5 Below Pa, more preferably 3×10 -6 Below Pa. Also, the partial pressure of gas molecules (atoms) with m / z of 44 in the transfer chamber 2704 and each chamber is, for example, 3×10 -5 Below Pa, preferably 1×10 -5 Below Pa, more preferably 3×10 -6 Below Pa.

[0078] Note that the total pressure and partial pressure in the transfer chamber 2704 and each chamber can be measured using an ionization vacuum gauge, a mass spectrometer, etc.

[0079] Also, it is desirable that the transfer chamber 2704 and each chamber have a structure with little external leakage or internal leakage. For example, the leak rate of the transfer chamber 2704 is 1×10 0 Below Pa / min, preferably 5×10 -1 Below Pa / min. Also, the leak rate of each chamber is 1×10 -1 Below Pa / min, preferably 5×10 -2 Below Pa / min.

[0080] Note that the leak rate can be derived from the total pressure and partial pressure measured using an ionization vacuum gauge, a mass spectrometer, etc. For example, it may be derived from the total pressure 10 minutes after starting vacuum pumping with a vacuum pump such as a turbomolecular pump and the total pressure 10 minutes after closing the valve. Note that the total pressure 10 minutes after starting the above vacuum pumping is preferably the average value when the total pressure is measured multiple times.

[0081] The leak rate depends on both external and internal leaks. External leaks occur when gas enters from outside the vacuum system due to tiny holes, faulty seals, etc. Internal leaks are caused by leaks from valves or other partitions within the vacuum system, or by the release of gas from internal components. To keep the leak rate below the aforementioned values, countermeasures must be taken from both external and internal leaks.

[0082] For example, the opening and closing parts of the conveying chamber 2704 and each chamber may be sealed with metal gaskets. Preferably, the metal gaskets are made of metal coated with iron fluoride, aluminum oxide, or chromium oxide. Metal gaskets offer better adhesion than O-rings, reducing external leakage. Furthermore, using a passivated metal coated with iron fluoride, aluminum oxide, or chromium oxide suppresses the release of impurity-containing gases from the metal gasket, thereby reducing internal leakage.

[0083] Furthermore, aluminum, chromium, titanium, zirconium, nickel, or vanadium, which emit less impurity-containing gas, are used as components of the manufacturing apparatus 2700. Alternatively, the aforementioned metals that emit less impurity-containing gas may be used as a coating on an alloy containing iron, chromium, and nickel. Alloys containing iron, chromium, and nickel are rigid, heat-resistant, and suitable for processing. Here, reducing the surface area by reducing surface irregularities of the components through polishing or other means can reduce the emission of gas.

[0084] Alternatively, the components of the aforementioned manufacturing apparatus 2700 may be coated with iron fluoride, aluminum oxide, chromium oxide, or the like.

[0085] The components of the manufacturing apparatus 2700 are preferably made of metal as much as possible. For example, when installing viewing windows made of quartz or the like, it is advisable to thinly coat the surface with iron fluoride, aluminum oxide, chromium oxide, etc., to suppress the release of gases.

[0086] The adsorbed substances present in the transport chamber 2704 and each chamber do not affect the pressure in the transport chamber 2704 and each chamber because they are adsorbed onto the inner walls, but they cause gas release when the transport chamber 2704 and each chamber are evacuated. Therefore, although there is no correlation between the leak rate and the exhaust rate, it is important to use a pump with high exhaust capacity to desorb as much of the adsorbed substances present in the transport chamber 2704 and each chamber as possible and evacuate them in advance. In addition, the transport chamber 2704 and each chamber may be baked to promote the desorption of adsorbed substances. Baking can increase the desorption rate of adsorbed substances by about 10 times. Baking should be performed at a temperature between 100°C and 450°C. At this time, if the adsorbed substances are removed while introducing an inert gas into the transport chamber 2704 and each chamber, the desorption rate of water and other substances that are difficult to desorb by exhaust alone can be further increased. In addition, the desorption rate of adsorbed substances can be further increased by heating the introduced inert gas to approximately the same temperature as the baking temperature. It is preferable to use a noble gas as the inert gas here.

[0087] Alternatively, it is preferable to increase the pressure in the transport chamber 2704 and each chamber by introducing an inert gas such as a heated noble gas or oxygen, and then exhaust the transport chamber 2704 and each chamber again after a certain period of time. By introducing a heated gas, adsorbed substances can be removed from the transport chamber 2704 and each chamber, thereby reducing the amount of impurities present in the transport chamber 2704 and each chamber. This process is most effective when repeated 2 to 30 times, preferably 5 to 15 times. Specifically, the pressure in the transport chamber 2704 and each chamber can be increased to 0.1 Pa to 10 kPa, preferably 1 Pa to 1 kPa, and more preferably 5 Pa to 100 Pa by introducing an inert gas or oxygen with a temperature of 40°C to 400°C, preferably 50°C to 200°C, and the pressure can be maintained for 1 minute to 300 minutes, preferably 5 minutes to 120 minutes. Subsequently, the transport chamber 2704 and each chamber are evacuated for a period of 5 minutes to 300 minutes, preferably 10 minutes to 120 minutes.

[0088] Next, chambers 2706b and 2706c will be explained using the schematic cross-sectional diagrams shown in Figure 3.

[0089] Chambers 2706b and 2706c are chambers capable of performing microwave processing on an object to be processed. The only difference between chambers 2706b and 2706c is the atmosphere used during microwave processing. Other configurations are common to both chambers, and will therefore be described together below.

[0090] Chambers 2706b and 2706c each have a slot antenna plate 2808, a dielectric plate 2809, a substrate holder 2812, and an exhaust port 2819. Outside of chambers 2706b and 2706c, a gas supply source 2801, a valve 2802, a high-frequency generator 2803, a waveguide 2804, a mode converter 2805, a gas pipe 2806, a waveguide 2807, a matching box 2815, a high-frequency power supply 2816, a vacuum pump 2817, and a valve 2818.

[0091] The high-frequency generator 2803 is connected to the mode converter 2805 via a waveguide 2804. The mode converter 2805 is connected to the slot antenna plate 2808 via a waveguide 2807. The slot antenna plate 2808 is positioned in contact with the dielectric plate 2809. The gas supply source 2801 is connected to the mode converter 2805 via a valve 2802. Gas is then supplied to chambers 2706b and 2706c through a gas pipe 2806 that passes through the mode converter 2805, waveguide 2807, and dielectric plate 2809. The vacuum pump 2817 has the function of exhausting gas and other substances from chambers 2706b and 2706c via a valve 2818 and an exhaust port 2819. The high-frequency power supply 2816 is connected to the substrate holder 2812 via a matching box 2815.

[0092] The substrate holder 2812 has the function of holding the substrate 2811. For example, it has the function of electrostatically or mechanically chucking the substrate 2811. It also functions as an electrode to which power is supplied from the high-frequency power supply 2816. It also has an internal heating mechanism 2813 and has the function of heating the substrate 2811.

[0093] As the vacuum pump 2817, for example, a dry pump, mechanical booster pump, ion pump, titanium sublimation pump, cryopump, or turbomolecular pump can be used. In addition to the vacuum pump 2817, a cryotrap may also be used. Using a cryopump and cryotrap is particularly preferable because it allows for efficient water removal.

[0094] Furthermore, the heating mechanism 2813 may be, for example, a heating mechanism that uses a resistance heating element. Alternatively, it may be a heating mechanism that heats by heat conduction or thermal radiation from a heated medium such as a gas. For example, RTA (Rapid Thermal Annealing) such as GRTA (Gas Rapid Thermal Annealing) or LRTA (Lamp Rapid Thermal Annealing) can be used. GRTA performs heat treatment using a high-temperature gas. An inert gas is used as the gas.

[0095] Furthermore, the gas supply source 2801 may be connected to the purifier via a mass flow controller. It is preferable to use a gas with a dew point of -80°C or lower, preferably -100°C or lower. For example, oxygen gas, nitrogen gas, and noble gases (such as argon gas) may be used.

[0096] For example, silicon oxide (quartz), aluminum oxide (alumina), or yttrium oxide (yttria) may be used as the dielectric plate 2809. Furthermore, another protective layer may be formed on the surface of the dielectric plate 2809. The protective layer may be made of magnesium oxide, titanium oxide, chromium oxide, zirconium oxide, hafnium oxide, tantalum oxide, silicon oxide, aluminum oxide, or yttrium oxide. Since the dielectric plate 2809 will be exposed to particularly high-density regions of the high-density plasma 2810 described later, providing a protective layer can mitigate damage. As a result, an increase in particles during processing can be suppressed.

[0097] The high-frequency generator 2803 has the function of generating microwaves in frequencies such as 0.3 GHz to 3.0 GHz, 0.7 GHz to 1.1 GHz, or 2.2 GHz to 2.8 GHz. The microwaves generated by the high-frequency generator 2803 are transmitted to the mode converter 2805 via the waveguide 2804. In the mode converter 2805, the microwaves transmitted as TE mode are converted to TEM mode. The microwaves are then transmitted to the slot antenna plate 2808 via the waveguide 2807. The slot antenna plate 2808 is provided with multiple slot holes, and the microwaves pass through these slot holes and the dielectric plate 2809. This generates an electric field below the dielectric plate 2809, thereby generating a high-density plasma 2810. The high-density plasma 2810 contains ions and radicals depending on the type of gas supplied from the gas supply source 2801. For example, oxygen radicals are present.

[0098] At this time, the substrate 2811 can be modified by ions and radicals generated in the high-density plasma 2810, which can alter the film on the substrate 2811. It is preferable to apply a bias to the substrate 2811 using a high-frequency power supply 2816. For example, a radio frequency (RF) power supply with frequencies such as 13.56 MHz or 27.12 MHz can be used as the high-frequency power supply 2816. By applying a bias to the substrate, ions in the high-density plasma 2810 can be efficiently delivered to the back of openings formed in the film on the substrate 2811.

[0099] For example, oxygen radical treatment using high-density plasma 2810 can be performed by introducing oxygen from gas supply source 2801 in chamber 2706b or chamber 2706c.

[0100] Next, chambers 2706a and 2706d will be explained using the schematic cross-sectional diagrams shown in Figure 4.

[0101] Chambers 2706a and 2706d are chambers capable of irradiating the workpiece with electromagnetic waves, for example. The only difference between chambers 2706a and 2706d is the type of electromagnetic wave they emit. Since many other components are common to both, they will be described together below.

[0102] Chambers 2706a and 2706d each have one or more lamps 2820, a substrate holder 2825, a gas inlet 2823, and an exhaust port 2830. Outside of chambers 2706a and 2706d, a gas supply source 2821, a valve 2822, a vacuum pump 2828, and a valve 2829 are provided.

[0103] The gas supply source 2821 is connected to the gas inlet 2823 via valve 2822. The vacuum pump 2828 is connected to the exhaust port 2830 via valve 2829. The lamp 2820 is positioned opposite the substrate holder 2825. The substrate holder 2825 has the function of holding the substrate 2824. The substrate holder 2825 also has an internal heating mechanism 2826 that has the function of heating the substrate 2824.

[0104] For lamp 2820, for example, a light source having the function of emitting electromagnetic waves such as visible light or ultraviolet light may be used. For example, a light source having the function of emitting electromagnetic waves with peaks in wavelengths of 10 nm to 2500 nm, 500 nm to 2000 nm, or 40 nm to 340 nm may be used.

[0105] For example, lamp 2820 can be a light source such as a halogen lamp, metal halide lamp, xenon arc lamp, carbon arc lamp, high-pressure sodium lamp, or high-pressure mercury lamp.

[0106] For example, electromagnetic waves emitted from the lamp 2820 can be partially or entirely absorbed by the substrate 2824, thereby modifying the film on the substrate 2824. For example, defects can be created or reduced, or impurities can be removed. Furthermore, if the substrate 2824 is heated during the process, the creation or reduction of defects or the removal of impurities can be performed more efficiently.

[0107] Alternatively, for example, the substrate holder 2825 may be heated by electromagnetic waves emitted from the lamp 2820, thereby heating the substrate 2824. In this case, the substrate holder 2825 does not need to have a heating mechanism 2826 inside.

[0108] For vacuum pump 2828, refer to the description for vacuum pump 2817. For heating mechanism 2826, refer to the description for heating mechanism 2813. For gas supply source 2821, refer to the description for gas supply source 2801.

[0109] The microwave processing apparatus that can be used in this embodiment is not limited to the one described above. The microwave processing apparatus 2900 shown in Figure 5 can be used. The microwave processing apparatus 2900 has a quartz tube 2901, an exhaust port 2819, a gas supply source 2801, a valve 2802, a high-frequency generator 2803, a waveguide 2804, a gas pipe 2806, a vacuum pump 2817, and a valve 2818. The microwave processing apparatus 2900 also has a substrate holder 2902 inside the quartz tube 2901 that holds a plurality of substrates 2811 (2811_1 to 2811_n, where n is an integer of 2 or more). The microwave processing apparatus 2900 may also have a heating means 2903 on the outside of the quartz tube 2901.

[0110] Microwaves generated by the high-frequency generator 2803 are irradiated onto a substrate placed inside the quartz tube 2901 via the waveguide 2804. The vacuum pump 2817 is connected to the exhaust port 2819 via the valve 2818, and can adjust the pressure inside the quartz tube 2901. The gas supply source 2801 is connected to the gas pipe 2806 via the valve 2802, and can introduce a desired gas into the quartz tube 2901. The heating means 2903 can heat the substrate 2811 inside the quartz tube 2901 to a desired temperature. Alternatively, the heating means 2903 may heat the gas supplied from the gas supply source 2801. The microwave processing device 2900 can perform heating and microwave processing on the substrate 2811 simultaneously. Alternatively, the substrate 2811 can be heated first, followed by microwave processing, or the substrate 2811 can be microwaved first, followed by heating.

[0111] Substrates 2811_1 to 2811_n may all be processing substrates forming semiconductor devices or memory devices, or some of the substrates may be dummy substrates. For example, substrates 2811_1 and 2811_n may be dummy substrates, and substrates 2811_2 to 2811_n-1 may be processing substrates. Alternatively, substrates 2811_1, 2811_2, 2811_n-1, and 2811_n may be dummy substrates, and substrates 2811_3 to 2811_n-2 may be processing substrates. Using dummy substrates is preferable because it allows multiple processing substrates to be processed uniformly during microwave processing or heat processing, reducing variations between processing substrates. For example, it is preferable to place dummy substrates on the processing substrates closest to the high-frequency generator 2803 and waveguide 2804, as this suppresses direct exposure of the processing substrates to microwaves.

[0112] By using the above manufacturing equipment, it becomes possible to modify the film while suppressing the inclusion of impurities in the processed material.

[0113] According to one aspect of the present invention, a method for modifying an insulating film can be provided. Furthermore, according to one aspect of the present invention, a method for reducing the hydrogen concentration in an insulating film can be provided.

[0114] The configurations and methods described in this embodiment can be implemented by appropriately combining at least a part thereof with other embodiments and examples described herein.

[0115] (Embodiment 2) In this embodiment, an example of a semiconductor device having a transistor 200 according to one aspect of the present invention, and a method for manufacturing the same, will be described using Figures 6A to 22C.

[0116] <Example of semiconductor device configuration> The configuration of a semiconductor device having transistor 200 will be explained using Figures 6A to 6D. Figures 6A to 6D are top views and cross-sectional views of a semiconductor device having transistor 200. Figure 6A is a top view of the semiconductor device. Figures 6B to 6D are cross-sectional views of the semiconductor device. Here, Figure 6B is a cross-sectional view of the area indicated by the dashed line A1-A2 in Figure 6A, and is also a cross-sectional view of transistor 200 in the channel length direction. Figure 6C is a cross-sectional view of the area indicated by the dashed line A3-A4 in Figure 6A, and is also a cross-sectional view of transistor 200 in the channel width direction. Figure 6D is a cross-sectional view of the area indicated by the dashed line A5-A6 in Figure 6A. Note that in the top view of Figure 6A, some elements have been omitted for clarity.

[0117] A semiconductor device according to one aspect of the present invention includes an insulator 212 on a substrate (not shown), an insulator 214 on the insulator 212, a transistor 200 on the insulator 214, an insulator 280 on the transistor 200, an insulator 282 on the insulator 280, an insulator 283 on the insulator 282, an insulator 274 on the insulator 283, and an insulator 285 on the insulator 283 and the insulator 274. The insulators 212, 214, 280, 282, 283, 285, and 274 function as interlayer films. The device also includes conductors 240a and 240b that are electrically connected to the transistor 200 and function as plugs. An insulator 241a is provided in contact with the side surface of the conductor 240a, and an insulator 241b is provided in contact with the side surface of the conductor 240b. Furthermore, a conductor 246a is provided on the insulator 285 and on the conductor 240a, electrically connected to the conductor 240a and functioning as wiring, and a conductor 246b is provided on the insulator 285 and on the conductor 240b, electrically connected to the conductor 240b and functioning as wiring. In addition, the insulator 283 is in contact with a part of the upper surface of the insulator 214, the side surface of the insulator 216, the side surface of the insulator 222, the side surface of the insulator 275, the side surface of the insulator 280, and the side surface and upper surface of the insulator 282.

[0118] In the following, conductors 240a and 240b may be collectively referred to as conductor 240. Similarly, insulators 241a and 241b may be collectively referred to as insulator 241. Furthermore, conductors 246a and 246b may be collectively referred to as conductor 246.

[0119] Insulator 241a is provided in contact with the inner wall of the opening of insulator 280, insulator 282, insulator 283, and insulator 285, and conductor 240a is provided in contact with the side surface of insulator 241a. Insulator 241b is provided in contact with the inner wall of the opening of insulator 280, insulator 282, insulator 283, and insulator 285, and conductor 240b is provided in contact with the side surface of insulator 241b. Note that insulator 241a and insulator 241b each have a structure in which a first insulator is provided in contact with the inner wall of the opening, and a second insulator is provided further inside. In addition, conductor 240a (conductor 240b) has a structure in which a first conductor is provided in contact with the side surface of insulator 241a (insulator 241b), and a second conductor is provided further inside. Here, the height of the upper surface of the conductor 240a (conductor 240b) and the height of the upper surface of the insulator 285 in the region overlapping with the conductor 246a (conductor 246b) can be made to be approximately the same.

[0120] While transistor 200 shows a configuration in which the first insulator and the second insulator of insulator 241a (insulator 241b) are stacked, the present invention is not limited thereto. For example, the insulator 241a (insulator 241b) may be provided as a single layer or as a stacked structure of three or more layers. Also, while transistor 200 shows a configuration in which the first conductor and the second conductor of conductor 240a (conductor 240b) are stacked, the present invention is not limited thereto. For example, the conductor 240a (conductor 240b) may be provided as a single layer or as a stacked structure of three or more layers. When a structure has a stacked structure, ordinal numbers may be assigned to distinguish them according to the order of formation.

[0121] [Transistor 200] As shown in Figures 6A to 6D, the transistor 200 comprises an insulator 216 on an insulator 214, a conductor 205 (conductor 205a and conductor 205b) arranged to be embedded in the insulator 214 and / or insulator 216, an insulator 222 on the insulator 216 and on the conductor 205, an insulator 224 on the insulator 222, an oxide 230a on the insulator 224, an oxide 230b on the oxide 230a, a conductor 242a on the oxide 230b, an insulator 271a on the conductor 242a, and an oxide 230 The device includes a conductor 242b on b, an insulator 271b on the conductor 242b, an insulator 252 on the oxide 230b, an insulator 250 on the insulator 252, an insulator 254 on the insulator 250, a conductor 260 (conductors 260a and 260b) located on the insulator 254 and overlapping with a portion of the oxide 230b, and an insulator 275 arranged on the insulator 222, the insulator 224, the oxide 230a, the oxide 230b, the conductor 242a, the conductor 242b, the insulator 271a, and the insulator 271b. Here, as shown in Figures 6B and 6C, insulator 252 is in contact with the top surface of insulator 222, the side surface of insulator 224, the side surface of oxide 230a, the side surface and top surface of oxide 230b, the side surface of conductor 242a, the side surface of conductor 242b, the side surface of insulator 271a, the side surface of insulator 271b, the side surface of insulator 275, the side surface of insulator 280, and the bottom surface of insulator 250. The top surface of conductor 260 is positioned so as to be roughly the same height as the top of insulator 254, the top of insulator 250, the top of insulator 252, and the top surface of insulator 280. Insulator 282 is in contact with at least a portion of the top surfaces of conductor 260, insulator 252, insulator 250, insulator 254, and insulator 280.

[0122] In the following, oxides 230a and 230b may be collectively referred to as oxide 230. Similarly, conductors 242a and 242b may be collectively referred to as conductor 242. Furthermore, insulators 271a and 271b may be collectively referred to as insulator 271.

[0123] Insulators 280 and 275 are provided with openings that reach oxide 230b. Insulators 252, 250, 254, and 260 are arranged within these openings. In addition, in the channel length direction of transistor 200, conductors 260, 252, 250, and 254 are provided between insulators 271a and conductor 242a, and between insulators 271b and conductor 242b. Insulator 254 has a region in contact with the side surface of conductor 260 and a region in contact with the bottom surface of conductor 260.

[0124] Preferably, the oxide 230 has an oxide 230a disposed on the insulator 224 and an oxide 230b disposed on top of the oxide 230a. By having oxide 230a below oxide 230b, the diffusion of impurities from structures formed below oxide 230a to oxide 230b can be suppressed.

[0125] Although the transistor 200 shows a configuration in which the oxide 230 consists of two layers, oxide 230a and oxide 230b, the present invention is not limited to this. For example, the configuration may consist of a single layer of oxide 230b or a stacked structure of three or more layers, or each of oxide 230a and oxide 230b may have a stacked structure.

[0126] Conductor 260 functions as the first gate (also called the top gate) electrode, and conductor 205 functions as the second gate (also called the back gate) electrode. Insulators 252, 250, and 254 function as the first gate insulators, and insulators 222 and 224 function as the second gate insulators. Note that gate insulators are sometimes called gate insulating layers or gate insulating films. Conductor 242a functions as either the source or the drain, and conductor 242b functions as either the source or the drain. At least a portion of the region of oxide 230 that overlaps with conductor 260 functions as a channel-forming region.

[0127] Here, an enlarged view of the vicinity of the channel formation region in Figure 6B is shown in Figure 7A. As shown in Figure 7A, the oxide 230b has a region 230bc that functions as the channel formation region of the transistor 200, and regions 230ba and 230bb that are provided so as to sandwich region 230bc and function as the source region or drain region. At least a portion of region 230bc is superimposed on the conductor 260. In other words, region 230bc is provided in the region between the conductors 242a and 242b. Region 230ba is provided superimposed on the conductor 242a, and region 230bb is provided superimposed on the conductor 242b.

[0128] Region 230bc, which functions as a channel-forming region, is a high-resistance region with a lower carrier concentration due to fewer oxygen vacancies or lower impurity concentrations compared to regions 230ba and 230bb. Therefore, region 230bc can be said to be type i (intrinsic) or substantially type i.

[0129] Furthermore, regions 230ba and 230bb, which function as source or drain regions, are regions with high oxygen deficiencies or high concentrations of impurities such as hydrogen, nitrogen, and metallic elements, resulting in increased carrier concentration and low resistance. In other words, regions 230ba and 230bb are n-type regions with higher carrier concentration and lower resistance compared to region 230bc.

[0130] Here, the carrier concentration in region 230bc, which functions as a channel-forming region, is 1 × 10⁻⁶. 18 cm -3 The following is preferable: 1 × 10 17 cm -3 It is more preferable that it be less than 1 × 10 16 cm -3 It is even more preferable that it be less than 1 × 10 13 cm -3 It is even more preferable that it be less than 1 × 10 12 cm -3It is even more preferable that it be less than . There are no particular limitations on the lower limit of the carrier concentration in the region 230bc that functions as a channel-forming region, but for example, 1 × 10 -9 cm -3 It can be done this way.

[0131] Furthermore, a region may be formed between region 230bc and region 230ba (region 230bb) where the carrier concentration is equal to or lower than that of region 230ba (region 230bb) and equal to or higher than that of region 230bc. In other words, this region functions as a junction region between region 230bc and region 230ba (region 230bb). The hydrogen concentration in this junction region may be equal to or lower than that of region 230ba (region 230bb) and equal to or higher than that of region 230bc. Also, the oxygen deficiency in this junction region may be equal to or less than that of region 230ba (region 230bb) and equal to or greater than that of region 230bc.

[0132] Although Figure 7A shows an example in which regions 230ba, 230bb, and 230bc are formed in oxide 230b, the present invention is not limited to this. For example, each of the above regions may be formed not only in oxide 230b but also in oxide 230a.

[0133] Furthermore, in oxide 230, it can be difficult to clearly detect the boundaries between each region. The concentrations of metal elements, as well as impurity elements such as hydrogen and nitrogen, detected within each region may not be limited to stepwise changes between regions, but may also change continuously within each region. In other words, the closer a region is to the channel-forming region, the lower the concentrations of metal elements, as well as impurity elements such as hydrogen and nitrogen should be.

[0134] In transistor 200, it is preferable to use a metal oxide (hereinafter also referred to as an oxide semiconductor) that functions as a semiconductor for the oxide 230 (oxide 230a and oxide 230b) which includes the channel formation region.

[0135] Furthermore, it is preferable to use a metal oxide with a band gap of 2 eV or more, and more preferably one with a band gap of 2.5 eV or more, as it functions as a semiconductor. By using a metal oxide with a large band gap in this way, the off-current of the transistor can be reduced.

[0136] As oxide 230, for example, a metal oxide such as In-M-Zn oxide having indium, element M, and zinc (element M is one or more selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium) may be used. Alternatively, In-Ga oxide, In-Zn oxide, or indium oxide may be used as oxide 230.

[0137] Here, it is preferable that the atomic ratio of In to element M in the metal oxide used for oxide 230b is greater than the atomic ratio of In to element M in the metal oxide used for oxide 230a.

[0138] In this way, by placing oxide 230a below oxide 230b, the diffusion of impurities and oxygen from structures formed below oxide 230a to oxide 230b can be suppressed.

[0139] It is preferable that oxide 230b is crystalline. In particular, it is preferable to use CAAC-OS (c-axis aligned crystalline oxide semiconductor) as oxide 230b.

[0140] CAAC-OS is a metal oxide with a highly crystalline, dense structure and low levels of impurities and defects (e.g., oxygen vacancies). In particular, by heat-treating the metal oxide after its formation at a temperature that does not cause polycrystallization (e.g., between 400°C and 600°C), the CAAC-OS can be made to have an even more crystalline and dense structure. By increasing the density of CAAC-OS in this way, the diffusion of impurities or oxygen within the CAAC-OS can be further reduced.

[0141] On the other hand, because it is difficult to identify clear grain boundaries in CAAC-OS, the decrease in electron mobility caused by grain boundaries is less likely to occur. Therefore, metal oxides containing CAAC-OS have stable physical properties. Consequently, metal oxides containing CAAC-OS are highly heat resistant and reliable.

[0142] In transistors using oxide semiconductors, the electrical properties tend to fluctuate and reliability may be poor if impurities and oxygen vacancies are present in the region where the channel is formed in the oxide semiconductor. Furthermore, hydrogen near the oxygen vacancy can fill the oxygen vacancy, creating a defect (hereinafter referred to as V). O Sometimes called H, it forms a channel and generates electrons that become carriers. For this reason, if the region where the channel is formed in the oxide semiconductor contains oxygen vacancies, the transistor is likely to exhibit normally-on characteristics (a characteristic in which the channel exists and current flows through the transistor even without applying voltage to the gate electrode). Therefore, in the region where the channel is formed in the oxide semiconductor, impurities, oxygen vacancies, and V are likely to be present. O It is preferable that H is reduced as much as possible. In other words, it is preferable that the region in the oxide semiconductor where the channel is formed has a reduced carrier concentration and is type i (intrinsed) or substantially type i.

[0143] In contrast, by placing an insulator containing oxygen that is released by heating (hereinafter sometimes referred to as excess oxygen) near the oxide semiconductor and performing heat treatment, oxygen is supplied from the insulator to the oxide semiconductor, eliminating oxygen deficiencies and V OH can be reduced. However, if an excessive amount of oxygen is supplied to the source or drain region, it may cause a decrease in the on-current of transistor 200 or a decrease in the field-effect mobility. Furthermore, variations in the amount of oxygen supplied to the source or drain region within the substrate surface will result in variations in the characteristics of the semiconductor device containing the transistor.

[0144] Therefore, in an oxide semiconductor, the region 230bc, which functions as a channel-forming region, preferably has a reduced carrier concentration and is i-type or substantially i-type, while the regions 230ba and 230bb, which function as a source region or drain region, preferably have a high carrier concentration and are n-type. In other words, oxygen vacancies in region 230bc of the oxide semiconductor, and V O It is preferable to reduce H so that an excessive amount of oxygen is not supplied to regions 230ba and 230bb.

[0145] Therefore, in this embodiment, with the conductor 242a and conductor 242b placed on the oxide 230b, microwave treatment is performed in an oxygen-containing atmosphere to eliminate oxygen deficiencies in region 230bc, and V O The aim is to reduce H. Here, microwave processing refers to processing using a device that has a power supply that generates high-density plasma using microwaves, for example. Furthermore, in this specification, microwaves refer to electromagnetic waves having a frequency of 300 MHz or more and 300 GHz or less.

[0146] By performing microwave treatment in an oxygen-containing atmosphere, the oxygen gas can be converted into plasma using microwaves or high-frequency waves such as RF, and this oxygen plasma can be applied. At this time, microwaves or high-frequency waves such as RF can also be irradiated into region 230bc. Due to the action of plasma, microwaves, etc., the V of region 230bc O H is oxygen-deficient (V O It can be separated into (V) and hydrogen (H), remove the hydrogen from region 230bc, and fill the oxygen deficiency with oxygen. In other words, in region 230bc, "V O H → H + VO The following reaction occurs, which reduces the hydrogen concentration in region 230bc. Therefore, the oxygen deficiency in region 230bc, and V O This can reduce H and lower the carrier concentration.

[0147] Furthermore, when performing microwave processing in an oxygen-containing atmosphere, the effects of microwaves, high frequencies such as RF, and oxygen plasma are shielded by conductors 242a and 242b and do not reach regions 230ba and 230bb. In addition, the effects of oxygen plasma can be reduced by insulators 271, 275, and 280, which are provided covering oxide 230b and conductor 242. As a result, during microwave processing, V O This reduces H and prevents excessive oxygen supply, thus preventing a decrease in carrier concentration.

[0148] Furthermore, the oxygen injected into region 230bc can take various forms, including oxygen atoms, oxygen molecules, and oxygen radicals (also called O radicals, which are atoms or molecules with unpaired electrons, or ions). Note that the oxygen injected into region 230bc may be one or more of the above forms, and oxygen radicals are particularly preferred.

[0149] Here, it is preferable to perform microwave treatment in an oxygen-containing atmosphere after the deposition of the insulating film that will become the insulator 252, and / or after the deposition of the insulating film that will become the insulator 250. By performing microwave treatment in an oxygen-containing atmosphere via the insulator 252 and / or the insulator 250 in this way, oxygen can be efficiently injected into region 230bc. Furthermore, by arranging the insulator 252 in contact with the side surface of the conductor 242 and the surface of region 230bc, the injection of more oxygen than necessary into region 230bc can be suppressed, thereby suppressing oxidation of the side surface of the conductor 242. In addition, oxidation of the side surface of the conductor 242 can be suppressed when the insulating film that will become the insulator 250 is deposited.

[0150] In this way, oxygen vacancies are selectively created in the oxide semiconductor region 230bc, and V O By reducing H, region 230bc can be made i-type or substantially i-type. Furthermore, the supply of excess oxygen to regions 230ba and 230bb, which function as source or drain regions, can be suppressed, and the n-type can be maintained. This suppresses variations in the electrical properties of transistor 200 and prevents variations in the electrical properties of transistor 200 within the substrate plane.

[0151] By adopting the above configuration, it is possible to provide a semiconductor device with minimal variation in transistor characteristics. Furthermore, it is possible to provide a semiconductor device with good reliability and excellent electrical characteristics.

[0152] Furthermore, as shown in Figure 6C, in a cross-sectional view of the transistor 200 in the channel width direction, there may be a curved surface between the side surface and the top surface of the oxide 230b. In other words, the ends of the side surface and the ends of the top surface may be curved (hereinafter also referred to as rounded).

[0153] The radius of curvature of the curved surface is preferably greater than 0 nm and less than the film thickness of the oxide 230b in the region overlapping with the conductor 242, or less than half the length of the region without the curved surface. Specifically, the radius of curvature of the curved surface is greater than 0 nm and 20 nm or less, preferably 1 nm to 15 nm, and more preferably 2 nm to 10 nm. By adopting such a shape, the coverage of the oxide 230b by the insulator 252, insulator 250, insulator 254, and conductor 260 can be improved.

[0154] It is preferable that oxide 230 has a layered structure of multiple oxide layers with different chemical compositions. Specifically, it is preferable that the atomic ratio of element M to the main metal element in the metal oxide used in oxide 230a is greater than the atomic ratio of element M to the main metal element in the metal oxide used in oxide 230b. Furthermore, it is preferable that the atomic ratio of element M to In in the metal oxide used in oxide 230a is greater than the atomic ratio of element M to In in the metal oxide used in oxide 230b. Furthermore, it is preferable that the atomic ratio of In to element M in the metal oxide used in oxide 230b is greater than the atomic ratio of In to element M in the metal oxide used in oxide 230a.

[0155] Furthermore, it is preferable that the oxide 230b is a crystalline oxide such as CAAC-OS. Crystalline oxides such as CAAC-OS have few impurities and defects (such as oxygen deficiencies), and possess a dense structure with high crystallinity. Therefore, the extraction of oxygen from the oxide 230b by the source electrode or drain electrode can be suppressed. As a result, even when heat treatment is performed, the extraction of oxygen from the oxide 230b is reduced, and the transistor 200 is stable against high temperatures (so-called thermal budget) in the manufacturing process.

[0156] Here, at the junction of oxide 230a and oxide 230b, the lower end of the conduction band changes smoothly. In other words, the lower end of the conduction band at the junction of oxide 230a and oxide 230b can be said to change continuously or be a continuous junction. To achieve this, it is desirable to lower the defect level density of the mixed layer formed at the interface between oxide 230a and oxide 230b.

[0157] Specifically, by having oxides 230a and 230b share a common element other than oxygen as a main component, a mixed layer with a low defect level density can be formed. For example, if oxide 230b is In-M-Zn oxide, oxide 230a may be In-M-Zn oxide, M-Zn oxide, an oxide of element M, In-Zn oxide, indium oxide, etc.

[0158] Specifically, for oxide 230a, a metal oxide with a composition of In:M:Zn = 1:3:4 [atomic ratio] or close to it may be used, or a metal oxide with a composition of In:M:Zn = 1:1:0.5 [atomic ratio] or close to it may be used. Similarly, for oxide 230b, a metal oxide with a composition of In:M:Zn = 1:1:1 [atomic ratio] or close to it may be used, or a metal oxide with a composition of In:M:Zn = 4:2:3 [atomic ratio] or close to it may be used. Note that "close to it" includes a range of ±30% of the desired atomic ratio. Furthermore, it is preferable to use gallium as element M.

[0159] Furthermore, when depositing metal oxide films by sputtering, the above atomic ratio is not limited to the atomic ratio of the deposited metal oxide film, but may also be the atomic ratio of the sputtering target used for depositing the metal oxide film.

[0160] By configuring oxides 230a and 230b as described above, the defect level density at the interface between oxide 230a and oxide 230b can be reduced. As a result, the influence of interface scattering on carrier conduction is reduced, and transistor 200 can obtain a large on-current and high frequency characteristics.

[0161] Furthermore, as shown in Figure 6C and other figures, by providing an insulator 252 made of aluminum oxide or the like in contact with the top and side surfaces of the oxide 230, the indium contained in the oxide 230 may be unevenly distributed at and near the interface between the oxide 230 and the insulator 252. As a result, the atomic ratio near the surface of the oxide 230 becomes similar to that of indium oxide, or similar to that of In-Zn oxide. By increasing the atomic ratio of indium near the surface of the oxide 230, particularly oxide 230b, the field-effect mobility of the transistor 200 can be improved.

[0162] It is preferable that at least one of insulators 212, 214, 271, 275, 282, 283, and 285 functions as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen from the substrate side or from above the transistor 200 into the transistor 200. Therefore, it is preferable that at least one of insulators 212, 214, 271, 275, 282, 283, and 285 is an insulating material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms (i.e., the above impurities do not easily permeate it). Alternatively, it is preferable to use an insulating material that has the function of suppressing the diffusion of oxygen (e.g., at least one such as oxygen atoms or oxygen molecules) (i.e., the above oxygen does not easily permeate it).

[0163] In this specification, a barrier insulating film refers to an insulating film that has barrier properties. In this specification, barrier properties refer to the function of suppressing the diffusion of the corresponding substance (also called low permeability), or the function of capturing and fixing the corresponding substance (also called gettering).

[0164] For insulators 212, 214, 271, 275, 282, 283, and 285, it is preferable to use insulators that have the function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen. For example, aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, or silicon nitride oxide can be used. For example, for insulators 212, 275, and 283, it is preferable to use silicon nitride, which has higher hydrogen barrier properties. Also, for example, for insulators 214, 271, 282, and 285, it is preferable to use aluminum oxide, magnesium oxide, etc., which have high hydrogen capture and hydrogen fixation functions. This makes it possible to suppress the diffusion of impurities such as water and hydrogen from the substrate side to the transistor 200 side via insulators 212 and 214. Alternatively, it is possible to suppress the diffusion of impurities such as water and hydrogen from the interlayer insulating film located outside the insulator 285 towards the transistor 200. Alternatively, it is possible to suppress the diffusion of oxygen contained in the insulator 224, etc., towards the substrate side via the insulators 212 and 214. Alternatively, it is possible to suppress the diffusion of oxygen contained in the insulator 280, etc., upward from the transistor 200 via the insulator 282, etc. Thus, it is preferable to have a structure in which the transistor 200 is surrounded by insulators 212, 214, 271, 275, 282, 283, and 285, which have the function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen.

[0165] Here, it is preferable to use oxides having an amorphous structure as insulators 212, 214, 271, 275, 282, 283, and 285. For example, AlO x (x is any number greater than 0), MgO yIt is preferable to use a metal oxide such as (y is any number greater than 0). In such an amorphous metal oxide, oxygen atoms have dangling bonds, and these dangling bonds may have the property of capturing or fixing hydrogen. By using such an amorphous metal oxide as a component of the transistor 200, or by providing it around the transistor 200, hydrogen contained in the transistor 200, or hydrogen present around the transistor 200, can be captured or fixed. It is particularly preferable to capture or fix hydrogen contained in the channel formation region of the transistor 200. By using an amorphous metal oxide as a component of the transistor 200, or by providing it around the transistor 200, it is possible to manufacture a transistor 200 and a semiconductor device that have good characteristics and are highly reliable.

[0166] Furthermore, while insulators 212, 214, 271, 275, 282, 283, and 285 are preferably amorphous, they may also have regions of polycrystalline structure. In addition, insulators 212, 214, 271, 275, 282, 283, and 285 may have a multilayer structure in which an amorphous layer and a polycrystalline layer are stacked. For example, a stacked structure in which a polycrystalline layer is formed on top of an amorphous layer is also possible.

[0167] The insulators 212, 214, 271, 275, 282, 283, and 285 may be deposited using, for example, a sputtering method. Since the sputtering method does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration of insulators 212, 214, 271, 275, 282, 283, and 285 can be reduced. The deposition method is not limited to sputtering, and chemical vapor deposition (CVD), molecular beam epitaxy (MBE), pulsed laser deposition (PLD), atomic layer deposition (ALD), etc., may be used as appropriate.

[0168] Furthermore, it may be preferable to lower the resistivity of insulators 212, 275, and 283. For example, the resistivity of insulators 212, 275, and 283 may be approximately 1 × 10⁻⁶. 13 By setting the resistivity to Ωcm, insulators 212, 275, and 283 may be able to mitigate the charge-up of conductors 205, 242, 260, or 246 in processes using plasma or the like during semiconductor device manufacturing. The resistivity of insulators 212, 275, and 283 is preferably 1 × 10⁻⁶. 10 Ωcm or more, 1 × 10 15 The density should be less than or equal to Ωcm.

[0169] Furthermore, it is preferable that insulators 216, 274, 280, and 285 have a lower dielectric constant than insulator 214. By using a material with a low dielectric constant as the interlayer film, parasitic capacitance between wirings can be reduced. For example, silicon oxide, silicon oxynitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, and porous silicon oxide may be used as insulators 216, 274, 280, and 285 as appropriate.

[0170] The conductor 205 is arranged to overlap with the oxide 230 and the conductor 260. Here, it is preferable that the conductor 205 is embedded in an opening formed in the insulator 216. In some cases, a portion of the conductor 205 may be embedded in the insulator 214.

[0171] The conductor 205 comprises a conductor 205a and a conductor 205b. The conductor 205a is provided in contact with the bottom surface and side wall of the opening. The conductor 205b is provided so as to be embedded in a recess formed in the conductor 205a. Here, the height of the upper surface of the conductor 205b is approximately equal to the height of the upper surface of the conductor 205a and the height of the upper surface of the insulator 216.

[0172] Here, it is preferable to use a conductive material for the conductor 205a that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms. Alternatively, it is preferable to use a conductive material that has the function of suppressing the diffusion of oxygen (for example, at least one such as oxygen atoms or oxygen molecules).

[0173] By using a conductive material that has the function of reducing hydrogen diffusion for the conductor 205a, it is possible to prevent impurities such as hydrogen contained in the conductor 205b from diffusing into the oxide 230 via the insulator 224, etc. Furthermore, by using a conductive material that has the function of suppressing oxygen diffusion for the conductor 205a, it is possible to suppress the oxidation of the conductor 205b and the decrease in conductivity. As a conductive material that has the function of suppressing oxygen diffusion, it is preferable to use, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, etc. Therefore, the conductive material can be used as a single layer or in a laminate for the conductor 205a. For example, titanium nitride can be used for the conductor 205a.

[0174] Furthermore, it is preferable to use a conductive material whose main component is tungsten, copper, or aluminum for the conductor 205b. For example, tungsten may be used for the conductor 205b.

[0175] Conductor 205 may function as a second gate electrode. In this case, the threshold voltage (Vth) of transistor 200 can be controlled by changing the potential applied to conductor 205 independently of the potential applied to conductor 260, without linking it to the potential applied to conductor 260. In particular, by applying a negative potential to conductor 205, it is possible to increase the Vth of transistor 200 and reduce the off-current. Therefore, applying a negative potential to conductor 205 reduces the drain current when the potential applied to conductor 260 is 0V compared to not applying a negative potential.

[0176] Furthermore, the electrical resistivity of the conductor 205 is designed considering the potential applied to the conductor 205, and the film thickness of the conductor 205 is set to match this electrical resistivity. The film thickness of the insulator 216 is approximately the same as that of the conductor 205. Here, it is preferable to make the film thicknesses of the conductor 205 and the insulator 216 as thin as possible within the limits permitted by the design of the conductor 205. By making the film thickness of the insulator 216 thin, the absolute amount of impurities such as hydrogen contained in the insulator 216 can be reduced, thereby reducing the diffusion of these impurities into the oxide 230.

[0177] Furthermore, as shown in Figure 6A, the conductor 205 should be larger than the size of the region that does not overlap with the conductors 242a and 242b of the oxide 230. In particular, as shown in Figure 6C, it is preferable that the conductor 205 extends to the region outside the edges of the oxide 230a and oxide 230b in the channel width direction. That is, it is preferable that the conductor 205 and the conductor 260 are superimposed on the outside of the side surface of the oxide 230 in the channel width direction, with an insulator in between. With this configuration, the channel formation region of the oxide 230 can be electrically surrounded by the electric field of the conductor 260 which functions as the first gate electrode and the electric field of the conductor 205 which functions as the second gate electrode. In this specification, a transistor structure in which the channel formation region is electrically surrounded by the electric fields of the first gate and the second gate is called a surrounded channel (S-channel) structure.

[0178] In this specification, an S-channel transistor refers to a transistor structure in which the channel formation region is electrically surrounded by the electric fields of one and the other of a pair of gate electrodes. Furthermore, the S-channel structure disclosed in this specification is different from the Fin-type structure and the Planar-type structure. By adopting an S-channel structure, it is possible to create a transistor that has improved resistance to short-channel effects, or in other words, a transistor in which short-channel effects are less likely to occur.

[0179] Furthermore, as shown in Figure 6C, the conductor 205 is extended to function as wiring. However, the configuration is not limited to this, and a conductor that functions as wiring may be provided beneath the conductor 205. Also, it is not necessary to provide one conductor 205 for each transistor. For example, the conductor 205 may be shared by multiple transistors.

[0180] In the transistor 200, the conductor 205 is shown as a stacked structure of conductor 205a and conductor 205b, but the present invention is not limited to this. For example, the conductor 205 may be provided as a single layer or as a stacked structure of three or more layers.

[0181] Insulators 222 and 224 function as gate insulators.

[0182] Preferably, the insulator 222 has the function of suppressing the diffusion of hydrogen (for example, at least one such as a hydrogen atom or a hydrogen molecule). Furthermore, preferably, the insulator 222 has the function of suppressing the diffusion of oxygen (for example, at least one such as an oxygen atom or an oxygen molecule). For example, it is preferable that the insulator 222 has the function of suppressing the diffusion of one or both hydrogen and oxygen more effectively than the insulator 224.

[0183] The insulator 222 may be an insulator containing an oxide of either or both of the insulating materials aluminum and hafnium. Preferably, the insulator is an oxide containing aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate). When the insulator 222 is formed using such a material, the insulator 222 functions as a layer that suppresses the release of oxygen from the oxide 230 to the substrate side and / or the diffusion of impurities such as hydrogen from the periphery of the transistor 200 to the oxide 230. Therefore, by providing the insulator 222, it is possible to suppress the diffusion of impurities such as hydrogen into the inside of the transistor 200 and suppress the generation of oxygen vacancies in the oxide 230. In addition, it is possible to suppress the reaction of the conductor 205 with the oxygen contained in the insulator 224 or the oxide 230.

[0184] Alternatively, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to the above-mentioned insulator. Alternatively, these insulators may be subjected to nitriding treatment. Furthermore, insulator 222 may be used by laminating silicon oxide, silicon oxide nitride, or silicon nitride onto these insulators.

[0185] Furthermore, the insulator 222 may be a single-layer or multi-layer insulator containing so-called high-k materials, such as aluminum oxide, hafnium oxide, tantalum oxide, or zirconium oxide. As transistors become smaller and more integrated, thinning of the gate insulator can lead to problems such as leakage current. By using a high-k material as the insulator that functions as the gate insulator, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness. In addition, materials with high dielectric constants, such as lead zirconate titanate (PZT), strontium titanate (SrTiO3), and (Ba,Sr)TiO3 (BST), may also be used as the insulator 222.

[0186] The insulator 224 in contact with the oxide 230 can be, for example, silicon oxide, silicon oxide nitride, or the like, as appropriate.

[0187] Furthermore, during the manufacturing process of the transistor 200, it is preferable to perform a heat treatment with the surface of the oxide 230 exposed. This heat treatment may be performed, for example, at a temperature of 100°C to 600°C, more preferably 350°C to 550°C. The heat treatment should be performed in an atmosphere of nitrogen gas or an inert gas, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, it is preferable to perform the heat treatment in an oxygen atmosphere. This allows oxygen to be supplied to the oxide 230, thereby reducing oxygen deficiency. The heat treatment may also be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere of nitrogen gas or an inert gas, and then in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to replenish the desorbed oxygen. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas, and then continuously in an atmosphere of nitrogen gas or an inert gas.

[0188] Furthermore, by performing an oxygenation treatment on oxide 230, oxygen deficiencies in oxide 230 are repaired by the supplied oxygen, or in other words, "V O This can accelerate the reaction "+O → null". Furthermore, the supplied oxygen reacts with the hydrogen remaining in oxide 230, removing the hydrogen as H2O (dehydration). As a result, the hydrogen remaining in oxide 230 recombines with the oxygen vacancy and V O This can suppress the formation of H.

[0189] Furthermore, the insulators 222 and 224 may have a laminated structure of two or more layers. In this case, the laminated structure is not limited to being made of the same material, but may be made of different materials. Also, the insulator 224 may be formed in an island shape by being superimposed with the oxide 230a. In this case, the insulator 275 will be in contact with the side surface of the insulator 224 and the upper surface of the insulator 222.

[0190] Conductors 242a and 242b are provided in contact with the upper surface of oxide 230b. Conductors 242a and 242b function as the source electrode or drain electrode of transistor 200, respectively.

[0191] As the conductor 242, it is preferable to use, for example, a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, or a nitride containing titanium and aluminum. In one embodiment of the present invention, a nitride containing tantalum is particularly preferred. Alternatively, for example, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel may be used. These materials are preferred because they are conductive materials that are resistant to oxidation or maintain conductivity even when absorbing oxygen.

[0192] Furthermore, hydrogen contained in oxide 230b, etc., may diffuse into conductor 242a or conductor 242b. In particular, by using tantalum-containing nitrides for conductor 242a and conductor 242b, hydrogen contained in oxide 230b, etc., is more likely to diffuse into conductor 242a or conductor 242b, and the diffused hydrogen may combine with nitrogen present in conductor 242a or conductor 242b. In other words, hydrogen contained in oxide 230b, etc., may be absorbed by conductor 242a or conductor 242b.

[0193] Furthermore, it is preferable that no curved surface is formed between the side surface of the conductor 242 and the top surface of the conductor 242. By using a conductor 242 without such a curved surface, the cross-sectional area of ​​the conductor 242 in the channel width direction can be increased, as shown in Figure 6D. This increases the conductivity of the conductor 242 and increases the on-current of the transistor 200.

[0194] The insulator 271a is provided in contact with the upper surface of the conductor 242a, and the insulator 271b is provided in contact with the upper surface of the conductor 242b. Preferably, the insulator 271 functions as a barrier insulating film against oxygen. Therefore, it is preferable that the insulator 271 has a function to suppress the diffusion of oxygen. For example, it is preferable that the insulator 271 has a function to suppress the diffusion of oxygen more than the insulator 280. As the insulator 271, for example, a silicon-containing nitride such as silicon nitride may be used. Furthermore, it is preferable that the insulator 271 has a function to capture impurities such as hydrogen. In that case, as the insulator 271, an amorphous metal oxide, such as aluminum oxide or magnesium oxide, may be used. In particular, it is preferable to use amorphous aluminum oxide or amorphous aluminum oxide as the insulator 271 because it may be possible to capture or fix hydrogen more effectively. This makes it possible to manufacture a transistor 200 and semiconductor device with good characteristics and high reliability.

[0195] The insulator 275 is provided so as to cover the insulator 224, oxide 230a, oxide 230b, conductor 242, and insulator 271. Preferably, the insulator 275 has the function of capturing and fixing hydrogen. In that case, it is preferable that the insulator 275 includes silicon nitride or an insulator of a metal oxide having an amorphous structure (e.g., aluminum oxide, magnesium oxide, etc.). Alternatively, for example, a laminated film of aluminum oxide and silicon nitride on the aluminum oxide may be used as the insulator 275.

[0196] By providing the insulators 271 and 275 described above, the conductor 242 can be surrounded by an insulator that has barrier properties against oxygen. In other words, the oxygen contained in the insulators 224 and 280 can be prevented from diffusing into the conductor 242. This prevents the conductor 242 from being directly oxidized by the oxygen contained in the insulators 224 and 280, which would increase its resistivity and reduce the on-current.

[0197] The insulator 252 functions as part of the gate insulator. Preferably, the insulator 252 is a barrier insulating film against oxygen. The insulator 252 can be any insulator that can be used for the insulator 282 described above. The insulator 252 may be an insulator containing an oxide of either or both aluminum and hafnium. Examples of such insulators include aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), and an oxide containing hafnium and silicon (hafnium silicate). In this embodiment, aluminum oxide is used as the insulator 252. In this case, the insulator 252 is an insulator containing at least oxygen and aluminum.

[0198] As shown in Figure 6C, the insulator 252 is provided in contact with the top and side surfaces of oxide 230b, the side surface of oxide 230a, the side surface of insulator 224, and the top surface of insulator 222. In other words, the regions of oxide 230a, oxide 230b, and insulator 224 that overlap with the conductor 260 are covered by the insulator 252 in the cross-section in the channel width direction. This allows the insulator 252, which has an oxygen barrier property, to block the desorption of oxygen from oxide 230a and oxide 230b during heat treatment, etc. Thus, the formation of oxygen vacancies in oxide 230a and oxide 230b can be reduced. As a result, oxygen vacancies and V formed in region 230bc are reduced. O H can be reduced. Therefore, the electrical characteristics of transistor 200 can be improved, and its reliability can be enhanced.

[0199] Conversely, even if an excess amount of oxygen is present in the insulator 280, insulator 250, etc., it is possible to suppress the excessive supply of such oxygen to oxides 230a and 230b. Therefore, it is possible to suppress the excessive oxidation of regions 230ba and 230bb via region 230bc, which would otherwise cause a decrease in the on-current of transistor 200 or a decrease in field-effect mobility.

[0200] Furthermore, as shown in Figure 6B, the insulator 252 is provided in contact with the respective sides of the conductor 242, insulator 271, insulator 275, and insulator 280. Therefore, oxidation of the side surface of the conductor 242 and the formation of an oxide film on that side surface can be reduced. This makes it possible to suppress a decrease in the on-current of the transistor 200 or a decrease in the field-effect mobility.

[0201] Furthermore, the insulator 252, along with the insulator 254, the insulator 250, and the conductor 260, must be provided in an opening formed in the insulator 280 or the like. In order to miniaturize the transistor 200, it is preferable that the film thickness of the insulator 252 be thin. The film thickness of the insulator 252 is 0.1 nm or more and 5.0 nm or less, preferably 0.5 nm or more and 3.0 nm or less, and more preferably 1.0 nm or more and 3.0 nm or less. In this case, it is sufficient that the insulator 252 has a region with the above-mentioned film thickness in at least a part of it. Also, it is preferable that the film thickness of the insulator 252 is thinner than the film thickness of the insulator 250. In this case, it is sufficient that the insulator 252 has a region with a film thickness thinner than the insulator 250 in at least a part of it.

[0202] To deposit the insulator 252 with a thin film thickness as described above, it is preferable to use the ALD method. ALD methods include thermal ALD, which uses only thermal energy for the reaction between the precursor and reactant, and plasma-enhanced ALD (PEALD), which uses plasma-excited reactants. The PEALD method is preferable in some cases because the use of plasma allows for film deposition at lower temperatures.

[0203] The ALD method utilizes the self-regulating properties of atoms to deposit atoms layer by layer, resulting in several advantages: ultra-thin film deposition is possible, deposition on structures with high aspect ratios is possible, film deposition with fewer defects such as pinholes is possible, film deposition with excellent coverage is possible, and film deposition is possible at low temperatures. Therefore, the insulator 252 can be deposited with good coverage on the sides of openings formed in the insulator 280, etc., with the thin film thickness described above.

[0204] Note that precursors used in the ALD method may contain carbon and other impurities. Therefore, films formed by the ALD method may contain more carbon and other impurities compared to films formed by other film deposition methods. The quantity of impurities can be quantified using secondary ion mass spectrometry (SIMS) or X-ray photoelectron spectroscopy (XPS).

[0205] The insulator 250 functions as part of the gate insulator. It is preferable that the insulator 250 is placed in contact with at least a portion of the insulator 252. The insulator 250 can be silicon oxide, silicon oxynitride, silicon nitride, silicon nitride, fluorine-added silicon oxide, carbon-added silicon oxide, carbon and nitrogen-added silicon oxide, or porous silicon oxide. Silicon oxide and silicon oxynitride are particularly preferred because they are stable with respect to heat. In this case, the insulator 250 will be an insulator having at least oxygen and silicon.

[0206] Similar to the insulator 224, it is preferable that the concentration of impurities such as water and hydrogen in the insulator 250 is reduced.

[0207] Furthermore, the film thickness of the insulator 250 is preferably 0.5 nm to 20 nm, and more preferably 1.0 nm to 15.0 nm. In this case, the insulator 250 only needs to have a region with the above-mentioned film thickness in at least a part of it. In order to deposit the insulator 250 with a thin film thickness and good coating properties, it is preferable to deposit the insulator 250 using, for example, the ALD method.

[0208] Furthermore, in order to obtain a high-quality film, the insulating film that becomes the insulator 250 is preferably deposited at a high temperature (for example, a temperature of 400°C or higher), but it is more preferable to deposit it at a temperature that can suppress oxidation of the sides of the conductor 242. Such a temperature is, for example, lower than 400°C, preferably 300°C or lower, more preferably 250°C or lower, and 100°C or higher. By depositing the insulating film at such a temperature, oxidation of the sides of the conductor 242 during the deposition of the insulating film can be suppressed.

[0209] It is preferable to perform microwave treatment in an oxygen-containing atmosphere after forming the insulating film that will become the insulator 250. By performing this microwave treatment, the film quality of the insulator 250 can be improved. One way to improve the film quality of the insulator 250 is to reduce the hydrogen concentration in the insulator 250. In other words, by performing this microwave treatment, the hydrogen concentration in the insulator 250 can be reduced. This reduces the hydrogen concentration in the oxide 230 adjacent to the insulator 250, thereby improving the reliability of the transistor 200.

[0210] Furthermore, in addition to improving the film quality of the insulator 250 through the microwave treatment described above, densification of the insulator 250 is also expected. By making the insulator 250 denser and reducing the defect level density within the insulator 250, the reliability of the transistor 200 can be improved.

[0211] As described in the previous embodiment, when silicon oxide is used as the insulator 250, the film quality of the silicon oxide can be improved by performing microwave treatment in an oxygen-containing atmosphere. Specifically, the γ peak can be reduced by performing this microwave treatment. Therefore, the amount of hydrogen in the silicon oxide can be reduced, and the diffusion of hydrogen into the oxide 230 can be suppressed. Note that the higher the temperature during the microwave treatment, the more efficiently the γ peak can be reduced, but this may promote oxidation of the sides of the conductor 242. The effect of reducing the γ peak can be obtained even if the temperature range during microwave treatment is 150°C to 400°C, or 200°C to 300°C, for example, around 250°C. Therefore, it is preferable to perform microwave treatment in such a temperature range.

[0212] Therefore, it is preferable to deposit the insulating film that will become the insulator 250 at a relatively low temperature, and then perform microwave treatment in an oxygen-containing atmosphere. This makes it possible to form an insulator 250 with good film quality while suppressing oxidation of the sides of the conductor 242. Furthermore, it is possible to form an insulator 250 with a reduced hydrogen concentration while suppressing oxidation of the sides of the conductor 242. Thus, the reliability of the transistor 200 can be improved.

[0213] Figure 6B and others show a configuration in which the insulator 250 is a single layer, but the present invention is not limited to this, and a laminated structure of two or more layers is also possible. For example, as shown in Figure 7B, the insulator 250 may be a laminated structure of two layers, consisting of an insulator 250a and an insulator 250b on top of the insulator 250a.

[0214] As shown in Figure 7B, when the insulator 250 has a two-layer laminated structure, it is preferable that the lower insulator 250a is formed using an insulator that is permeable to oxygen, and the upper insulator 250b is formed using an insulator that has the function of suppressing the diffusion of oxygen. With this configuration, it is possible to suppress the diffusion of oxygen contained in the insulator 250a to the conductor 260. In other words, it is possible to suppress the decrease in the amount of oxygen supplied to the oxide 230. In addition, it is possible to suppress the oxidation of the conductor 260 by the oxygen contained in the insulator 250a. For example, the insulator 250a may be made using a material that can be used for the insulator 250 as described above, and the insulator 250b may be an insulator containing an oxide of aluminum and / or hafnium. As such an insulator, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), an oxide containing hafnium and silicon (hafnium silicate), etc., can be used. In this embodiment, hafnium oxide is used as the insulator 250b. In this case, the insulator 250b is an insulator having at least oxygen and hafnium. The film thickness of the insulator 250b is 0.5 nm or more and 5.0 nm or less, preferably 1.0 nm or more and 5.0 nm or less, more preferably 1.0 nm or more and 3.0 nm or less. In this case, it is sufficient that the insulator 250b has at least a portion of the above-mentioned film thickness region.

[0215] Furthermore, when silicon oxide, silicon oxynitride, or the like is used for insulator 250a, insulator 250b may be an insulating material that is a high-k material with a high dielectric constant. By making the gate insulator a laminated structure of insulator 250a and insulator 250b, a laminated structure that is stable against heat and has a high dielectric constant can be made. Therefore, it is possible to reduce the gate potential applied during transistor operation while maintaining the physical film thickness of the gate insulator. In addition, it is possible to thin the equivalent oxide film thickness (EOT) of the insulator that functions as a gate insulator. Thus, the dielectric breakdown voltage of insulator 250 can be increased.

[0216] The insulator 254 functions as part of the gate insulator. Preferably, a barrier insulating film against hydrogen is used as the insulator 254. This prevents impurities such as hydrogen contained in the conductor 260 from diffusing into the insulator 250 and oxide 230b. The insulator 254 can be any insulator that can be used for the insulator 283 described above. For example, silicon nitride deposited by the PEALD method can be used as the insulator 254. In this case, the insulator 254 will be an insulator containing at least nitrogen and silicon.

[0217] Furthermore, the insulator 254 may also have barrier properties against oxygen. This can suppress the diffusion of oxygen contained in the insulator 250 into the conductor 260.

[0218] Furthermore, the insulator 254, along with the insulator 252, the insulator 250, and the conductor 260, must be provided in an opening formed in the insulator 280 or the like. In order to miniaturize the transistor 200, it is preferable that the film thickness of the insulator 254 be thin. The film thickness of the insulator 254 is 0.1 nm or more and 5.0 nm or less, preferably 0.5 nm or more and 3.0 nm or less, and more preferably 1.0 nm or more and 3.0 nm or less. In this case, it is sufficient that the insulator 254 has a region with the above-mentioned film thickness in at least a part of it. Also, it is preferable that the film thickness of the insulator 254 is thinner than the film thickness of the insulator 250. In this case, it is sufficient that the insulator 254 has a region with a thinner film thickness than the insulator 250 in at least a part of it.

[0219] The conductor 260 functions as the first gate electrode of the transistor 200. Preferably, the conductor 260 has a conductor 260a and a conductor 260b disposed on top of the conductor 260a. For example, it is preferable that the conductor 260a is arranged to enclose the bottom and sides of the conductor 260b. Also, as shown in Figures 6B and 6C, the top surface of the conductor 260 roughly coincides with the top of the insulator 252, the top of the insulator 250, and the top of the insulator 254. In Figures 6B and 6C, the conductor 260 is shown as a two-layer structure of conductor 260a and conductor 260b, but it may also be a single-layer structure or a stacked structure of three or more layers.

[0220] It is preferable to use a conductive material for the conductor 260a that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, and copper atoms. Alternatively, it is preferable to use a conductive material that has the function of suppressing the diffusion of oxygen (for example, at least one such as oxygen atoms or oxygen molecules).

[0221] Furthermore, because the conductor 260a has the function of suppressing oxygen diffusion, it is possible to suppress the oxidation of the conductor 260b by the oxygen contained in the insulator 250, which would otherwise reduce its conductivity. As a conductive material that has the function of suppressing oxygen diffusion, it is preferable to use, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, etc.

[0222] Furthermore, since the conductor 260 also functions as wiring, it is preferable to use a conductor with high conductivity. For example, the conductor 260b can be a conductive material mainly composed of tungsten, copper, or aluminum. The conductor 260b may also be in a laminated structure, for example, a laminated structure of titanium or titanium nitride and the above conductive material.

[0223] Furthermore, in transistor 200, the conductor 260 is formed self-aligningly to fill the openings formed in the insulator 280 and the like. By forming the conductor 260 in this way, the conductor 260 can be reliably positioned in the region between the conductors 242a and 242b without the need for alignment.

[0224] Furthermore, as shown in Figure 6C, in the channel width direction of transistor 200, with reference to the bottom surface of insulator 222, the height of the bottom surface of conductor 260 in the region where conductor 260 and oxide 230b do not overlap is preferably lower than the height of the bottom surface of oxide 230b. By configuring conductor 260, which functions as a gate electrode, to cover the side and top surfaces of the channel formation region of oxide 230b via insulator 250 or the like, the electric field of conductor 260 can be more easily applied to the entire channel formation region of oxide 230b. Therefore, the on-current of transistor 200 can be increased and the frequency characteristics can be improved. With reference to the bottom surface of insulator 222, the difference between the height of the bottom surface of conductor 260 in the region where oxide 230a and oxide 230b and conductor 260 do not overlap and the height of the bottom surface of oxide 230b is 0 nm or more and 100 nm or less, preferably 3 nm or more and 50 nm or less, more preferably 5 nm or more and 20 nm or less.

[0225] The insulator 280 is provided on the insulator 275, and openings are formed in the regions where the insulators 252, 250, 254, and conductor 260 are provided. The upper surface of the insulator 280 may also be flattened.

[0226] The insulator 280, which functions as an interlayer film, preferably has a low dielectric constant. By using a material with a low dielectric constant as the interlayer film, parasitic capacitance occurring between the wiring can be reduced. The insulator 280 is preferably made of the same material as the insulator 216, for example. Silicon oxide and silicon oxynitride are particularly preferred because they are thermally stable. Materials such as silicon oxide, silicon oxynitride, and silicon oxide with vacancies are particularly preferred because they can easily form regions containing oxygen that is desorbed by heating.

[0227] It is preferable that the impurity concentrations such as water and hydrogen in the insulator 280 are reduced. For example, as the insulator 280, oxides containing silicon such as silicon oxide and silicon oxynitride may be appropriately used.

[0228] The insulator 282 preferably functions as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen from above into the insulator 280, and preferably has a function of capturing impurities such as hydrogen. Further, the insulator 282 preferably functions as a barrier insulating film that suppresses the permeation of oxygen. As the insulator 282, an insulator having an amorphous structure, for example, an insulator such as aluminum oxide may be used. In this case, the insulator 282 is an insulator having at least oxygen and aluminum. By providing the insulator 282 having a function of capturing impurities such as hydrogen in contact with the insulator 280 within the region sandwiched between the insulator 212 and the insulator 283, impurities such as hydrogen contained in the insulator 280 and the like can be captured, and the amount of hydrogen in the region can be made constant. In particular, using aluminum oxide having an amorphous structure as the insulator 282 is preferable because hydrogen can be captured or fixed more effectively in some cases. Thereby, a transistor 200 and a semiconductor device having good characteristics and high reliability can be manufactured.

[0229] The insulator 283 functions as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen from above into the insulator 280. The insulator 283 is disposed on the insulator 282. As the insulator 283, it is preferable to use nitrides containing silicon such as silicon nitride and silicon oxynitride. For example, silicon nitride formed by a sputtering method may be used as the insulator 283. By forming the insulator 283 by a sputtering method, silicon nitride having a high density can be formed. Further, as the insulator 283, silicon nitride formed by a PEALD method or a CVD method may be laminated on silicon nitride formed by a sputtering method.

[0230] The conductor 240 is preferably made of a conductive material mainly composed of tungsten, copper, or aluminum. Also, each of the conductors 240a and 240b may have a laminated structure.

[0231] When the conductor 240 has a laminated structure, for the first conductor disposed in the vicinity of the insulators 285, 283, 282, 280, 275, and 271, it is preferable to use a conductive material having a function of suppressing the permeation of impurities such as water and hydrogen. For example, it is preferable to use tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, etc. Also, the conductive material having a function of suppressing the permeation of impurities such as water and hydrogen may be used in a single layer or in a laminated form. Further, it is possible to suppress impurities such as water and hydrogen contained in the upper layer than the insulator 283 from mixing into the oxide 230 through the conductor 240.

[0232] As the insulator 241, a barrier insulating film that can be used for the insulator 275 or the like may be used. For example, as the insulator 241, an insulator such as silicon nitride, aluminum oxide, or silicon oxynitride may be used. Since the insulator 241a (insulator 241b) is provided in contact with the insulators 283, 282, and 271, it is possible to suppress impurities such as water and hydrogen contained in the insulator 280 or the like from mixing into the oxide 230 through the conductor 240a (conductor 240b). In particular, silicon nitride is suitable because of its high blocking property against hydrogen. Also, it is possible to prevent oxygen contained in the insulator 280 from being absorbed by the conductor 240.

[0233] When each of the insulators 241a and 241b has a laminated structure as shown in FIG. 6B, the first insulator in contact with the inner wall of the opening of the insulator 280 or the like and the second insulator inside thereof are preferably used in combination with a barrier insulating film against oxygen and a barrier insulating film against hydrogen.

[0234] For example, aluminum oxide deposited by the ALD method can be used as the first insulator, and silicon nitride deposited by the PEALD method can be used as the second insulator. This configuration suppresses oxidation of the conductor 240 and further reduces the incorporation of hydrogen into the conductor 240.

[0235] Furthermore, a conductor 246a that functions as wiring and is in contact with the upper surface of the conductor 240a, and a conductor 246b that functions as wiring and is in contact with the upper surface of the conductor 240b may be arranged. It is preferable that the conductor 246 is made of a conductive material mainly composed of tungsten, copper, or aluminum. In addition, each of the conductors 246a and 246b may have a laminated structure, for example, a laminate of titanium or titanium nitride and the conductive material. The conductor may be formed so as to be embedded in an opening provided in the insulator.

[0236] <Component materials for semiconductor devices> The following describes the constituent materials that can be used in semiconductor devices.

[0237] <<Substrate>> As the substrate for forming transistor 200, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate may be used. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (such as yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon and germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Furthermore, there are semiconductor substrates having insulating regions within the aforementioned semiconductor substrates, such as SOI (Silicon On Insulator) substrates. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Alternatively, there are substrates having metal nitrides or metal oxides. Furthermore, there are substrates on which a conductor or semiconductor is provided on an insulating substrate, substrates on which a conductor or insulator is provided on a semiconductor substrate, and substrates on which a semiconductor or insulator is provided on a conductive substrate. Alternatively, substrates with elements mounted on them may be used. Examples of elements mounted on the substrate include capacitive elements, resistive elements, switch elements, light-emitting elements, and memory elements.

[0238] <<Insulator>> Insulators include insulating oxides, nitrides, oxidized nitrides, nitride oxides, metal oxides, metal oxidized nitrides, and metal nitride oxides.

[0239] For example, as transistors become smaller and more integrated, thinning of the gate insulator can lead to problems such as leakage current. By using a high-k material for the insulator that functions as the gate insulator, it is possible to lower the voltage during transistor operation while maintaining the physical film thickness. On the other hand, by using a material with a low dielectric constant for the insulator that functions as the interlayer film, parasitic capacitance between wiring can be reduced. Therefore, it is best to select the material according to the function of the insulator.

[0240] Furthermore, examples of insulators with high dielectric constants include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxidized nitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxidized nitrides containing silicon and hafnium, or nitrides containing silicon and hafnium.

[0241] Insulators with low dielectric constants include silicon oxide, silicon oxide nitride, silicon oxide nitride, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, silicon oxide with vacancies, or resins.

[0242] Furthermore, the electrical properties of transistors using metal oxides can be stabilized by surrounding them with an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen. As an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen, for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum can be used in a single layer or in a multilayer structure. Specifically, as an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and metal nitrides such as aluminum nitride, silicon oxide nitride, and silicon nitride can be used.

[0243] Furthermore, the insulator that functions as a gate insulator is preferably an insulator that has a region containing oxygen that is desorbed by heating. For example, by having a silicon oxide or silicon oxynitride having a region containing oxygen that is desorbed by heating in contact with the oxide 230, the oxygen deficiency of the oxide 230 can be compensated for.

[0244] <<Conductive material>> As the conductor, it is preferable to use a metallic element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above metallic elements, or an alloy combining the above metallic elements. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. Furthermore, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or maintain conductivity even when absorbing oxygen. Alternatively, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements like phosphorus, or silicides such as nickel silicide may be used.

[0245] Furthermore, multiple conductive layers formed from the above materials may be used in a laminated structure. For example, a laminated structure may be formed by combining the aforementioned metal element material with an oxygen-containing conductive material. Alternatively, a laminated structure may be formed by combining the aforementioned metal element material with a nitrogen-containing conductive material. Alternatively, a laminated structure may be formed by combining the aforementioned metal element material with an oxygen-containing conductive material and a nitrogen-containing conductive material.

[0246] Furthermore, when using an oxide in the channel formation region of a transistor, it is preferable to use a laminated structure for the conductor functioning as the gate electrode, which combines a material containing the aforementioned metal element with a conductive material containing oxygen. In this case, it is preferable to place the conductive material containing oxygen on the channel formation region side. By placing the conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material is more easily supplied to the channel formation region.

[0247] In particular, it is preferable to use a conductive material containing metal elements and oxygen contained in the metal oxide in which the channel is formed as the conductor that functions as the gate electrode. Alternatively, conductive materials containing the aforementioned metal elements and nitrogen may be used. For example, conductive materials containing nitrogen such as titanium nitride and tantalum nitride may be used. In addition, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and silicon-doped indium tin oxide may be used. In addition, indium gallium zinc oxide containing nitrogen may be used. By using such materials, it may be possible to capture hydrogen contained in the metal oxide in which the channel is formed. Alternatively, it may be possible to capture hydrogen that is mixed in from an external insulator or the like.

[0248] <<Metal Oxides>> It is preferable to use a metal oxide (oxide semiconductor) that functions as a semiconductor as oxide 230. Below, metal oxides applicable to oxide 230 according to the present invention will be described.

[0249] The metal oxide preferably contains at least indium or zinc. In particular, it preferably contains indium and zinc. In addition to these, it is preferable that aluminum, gallium, yttrium, tin, etc. are contained. Further, one or more selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, etc. may be contained.

[0250] Here, consider the case where the metal oxide is an In-M-Zn oxide having indium, element M, and zinc. Note that element M is aluminum, gallium, yttrium, or tin. Applicable elements for other element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, etc. However, there may be cases where a plurality of the aforementioned elements are combined as element M.

[0251] In addition, in this specification, etc., a metal oxide having nitrogen may also be collectively referred to as a metal oxide. Further, a metal oxide having nitrogen may be referred to as a metal oxynitride.

[0252] <Classification of crystal structure> First, the classification of the crystal structure in the oxide semiconductor will be described using FIG. 8A. FIG. 8A is a diagram for explaining the classification of the crystal structure of an oxide semiconductor, typically IGZO (a metal oxide containing In, Ga, and Zn).

[0253] As shown in Figure 8A, oxide semiconductors are broadly classified into "Amorphous," "Crystalline," and "Crystal." "Amorphous" includes completely amorphous materials. "Crystalline" includes CAAC (c-axis-aligned crystalline), nc (nanocrystalline), and CAC (cloud-aligned composite) (excluding single crystal and polycrystal). Note that single crystal, polycrystal, and completely amorphous materials are excluded from the "Crystalline" classification. "Crystal" includes single crystal and polycrystal materials.

[0254] The structure within the thick frame shown in Figure 8A represents an intermediate state between "Amorphous" and "Crystal," and belongs to a new boundary region (New crystalline phase). In other words, this structure can be described as being completely different from the energetically unstable "Amorphous" and "Crystal" states.

[0255] The crystal structure of a film or substrate can be evaluated using X-ray diffraction (XRD) spectroscopy. Figure 8B shows the XRD spectrum obtained by GIXD (Grazing-Incidence XRD) measurement of a CAAC-IGZO film classified as "Crystalline." The GIXD method is also known as the thin-film method or Seemann-Bohlin method. Hereafter, the XRD spectrum obtained by the GIXD measurement shown in Figure 8B will simply be referred to as the XRD spectrum. The composition of the CAAC-IGZO film shown in Figure 8B is approximately In:Ga:Zn = 4:2:3 [atomic ratio]. The thickness of the CAAC-IGZO film shown in Figure 8B is 500 nm.

[0256] In Figure 8B, the horizontal axis represents 2θ [deg.] and the vertical axis represents intensity [au]. As shown in Figure 8B, the XRD spectrum of the CAAC-IGZO film shows a peak indicating clear crystallinity. Specifically, the XRD spectrum of the CAAC-IGZO film shows a peak indicating c-axis orientation near 2θ = 31°. As shown in Figure 8B, the peak near 2θ = 31° is asymmetrical with respect to the angle at which the peak intensity was detected.

[0257] Furthermore, the crystal structure of a film or substrate can be evaluated by the diffraction pattern (also called the nano-beam electron diffraction pattern) observed by nano-beam electron diffraction (NBED). The diffraction pattern of a CAAC-IGZO film is shown in Figure 8C. Figure 8C shows the diffraction pattern observed by NBED with the electron beam incident parallel to the substrate. The composition of the CAAC-IGZO film shown in Figure 8C is approximately In:Ga:Zn=4:2:3 [atomic ratio]. In nano-beam electron diffraction, electron diffraction is performed with a probe diameter of 1 nm.

[0258] As shown in Figure 8C, the diffraction pattern of the CAAC-IGZO film shows multiple spots indicating c-axis orientation.

[0259] <<Oxide semiconductor structure>> Note that when focusing on the crystal structure, oxide semiconductors may be classified differently from those shown in Figure 8A. For example, oxide semiconductors can be divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include the aforementioned CAAC-OS and nc-OS. Non-single-crystal oxide semiconductors also include polycrystalline oxide semiconductors, pseudo-amorphous oxide semiconductors (a-like OS), and amorphous oxide semiconductors.

[0260] Here, we will explain the details of the CAAC-OS, nc-OS, and a-like OS mentioned above.

[0261] [CAAC-OS] CAAC-OS is an oxide semiconductor having multiple crystalline regions, the c-axis of which is oriented in a specific direction. This specific direction is the thickness direction of the CAAC-OS film, the normal direction to the surface on which the CAAC-OS film is formed, or the normal direction to the surface of the CAAC-OS film. A crystalline region is a region with periodic atomic arrangement. If we consider the atomic arrangement as a lattice arrangement, then a crystalline region is also a region with a aligned lattice arrangement. Furthermore, CAAC-OS has regions where multiple crystalline regions are connected in the ab-plane direction, and these regions may exhibit distortion. Distortion refers to a point in the connected region where the orientation of the lattice arrangement changes between a region with a aligned lattice arrangement and another region with a aligned lattice arrangement. In short, CAAC-OS is an oxide semiconductor that is c-axis oriented and does not exhibit clear orientation in the ab-plane direction.

[0262] Each of the multiple crystalline regions described above is composed of one or more minute crystals (crystals with a maximum diameter of less than 10 nm). When a crystalline region is composed of a single minute crystal, the maximum diameter of that crystalline region is less than 10 nm. When a crystalline region is composed of many minute crystals, the size of that crystalline region may be around several tens of nanometers.

[0263] Furthermore, in In-M-Zn oxides (where element M is one or more elements selected from aluminum, gallium, yttrium, tin, titanium, etc.), CAAC-OS tends to have a layered crystalline structure (also called a layered structure) consisting of layers containing indium (In) and oxygen (hereinafter referred to as the In layer) and layers containing element M, zinc (Zn), and oxygen (hereinafter referred to as the (M,Zn) layer). Note that indium and element M are mutually substitutable. Therefore, the (M,Zn) layer may contain indium. Also, the In layer may contain element M. Also, the In layer may contain Zn. This layered structure can be observed, for example, as a lattice image in high-resolution TEM images.

[0264] When structural analysis of a CAAC-OS film is performed using an XRD instrument, for example, out-of-plane XRD measurements using θ / 2θ scanning show a peak indicating c-axis orientation at 2θ = 31° or nearby. Note that the position of the c-axis orientation peak (value of 2θ) may vary depending on the type and composition of the metal elements constituting the CAAC-OS.

[0265] Furthermore, for example, multiple bright spots are observed in the electron diffraction pattern of a CAAC-OS film. These spots are observed at point-symmetric positions with respect to the incident electron beam spot (also called the direct spot) that passed through the sample.

[0266] When the crystal region is observed from the specific direction described above, the lattice arrangement within that crystal region is based on a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be non-regular hexagonal. Furthermore, the strain may have lattice arrangements such as pentagons or heptagons. Moreover, in CAAC-OS, clear grain boundaries cannot be observed even near the strain. In other words, it can be seen that the formation of grain boundaries is suppressed by the strain in the lattice arrangement. This is thought to be because CAAC-OS can tolerate strain due to the fact that the arrangement of oxygen atoms is not dense in the ab-plane direction, and the bond distance between atoms changes due to the substitution of metal atoms.

[0267] A crystal structure in which clear grain boundaries are observed is called a polycrystal. Grain boundaries act as recombination centers, trapping carriers and potentially causing a decrease in transistor on-current and field-effect mobility. Therefore, CAAC-OS, in which clear grain boundaries are not observed, is one of the crystalline oxides with a suitable crystal structure for the semiconductor layer of a transistor. In addition, a structure containing Zn is preferred for the composition of CAAC-OS. For example, In-Zn oxide and In-Ga-Zn oxide are preferred because they suppress the generation of grain boundaries more than In oxide.

[0268] CAAC-OS is an oxide semiconductor with high crystallinity and no clearly defined grain boundaries. Therefore, CAAC-OS is less susceptible to the decrease in electron mobility caused by grain boundaries. Furthermore, since the crystallinity of oxide semiconductors can decrease due to the inclusion of impurities and the generation of defects, CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Consequently, oxide semiconductors containing CAAC-OS have stable physical properties. Therefore, oxide semiconductors containing CAAC-OS are heat-resistant and highly reliable. In addition, CAAC-OS is stable even at high temperatures (so-called thermal budget) during the manufacturing process. Therefore, using CAAC-OS in OS transistors allows for greater flexibility in the manufacturing process.

[0269] [nc-OS] nc-OS exhibits periodicity in atomic arrangement in minute regions (e.g., regions between 1 nm and 10 nm, particularly between 1 nm and 3 nm). In other words, nc-OS contains minute crystals. These minute crystals are also called nanocrystals because their size is, for example, between 1 nm and 10 nm, particularly between 1 nm and 3 nm. Furthermore, nc-OS shows no regularity in crystal orientation between different nanocrystals. Therefore, no orientation is observed throughout the film. Consequently, depending on the analytical method, nc-OS may be indistinguishable from a-like OS or amorphous oxide semiconductors. For example, when structural analysis of an nc-OS film is performed using an XRD instrument, no peaks indicating crystallinity are detected in out-of-plane XRD measurements using θ / 2θ scanning. Also, when electron diffraction (also called limited-field electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter larger than that of the nanocrystals (e.g., 50 nm or larger), a diffraction pattern resembling a halo pattern is observed. On the other hand, when electron diffraction (also called nanobeam electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter close to or smaller than the size of the nanocrystal (for example, 1 nm to 30 nm), an electron diffraction pattern may be obtained in which multiple spots are observed within a ring-shaped region centered on a direct spot.

[0270] [a-like OS] a-like OS is an oxide semiconductor having a structure between nc-OS and amorphous oxide semiconductors. a-like OS has porous or low-density regions. That is, a-like OS has lower crystallinity compared to nc-OS and CAAC-OS. Also, a-like OS has a higher hydrogen concentration in the film compared to nc-OS and CAAC-OS.

[0271] <<Oxide Semiconductor Composition>> Next, we will explain the details of CAC-OS mentioned above. Note that CAC-OS refers to the material composition.

[0272] [CAC-OS] CAC-OS is a material composition in which, for example, the elements constituting the metal oxide are unevenly distributed in sizes of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or close to that size. In the following, a state in which one or more metal elements are unevenly distributed in a metal oxide, and the regions containing these metal elements are mixed in sizes of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or close to that size, is also referred to as a mosaic or patchy state.

[0273] Furthermore, CAC-OS is a composite metal oxide having a mosaic-like structure formed by the separation of the material into a first region and a second region, with the first region distributed within the film (hereinafter also referred to as a cloud-like structure). In other words, CAC-OS is a composite metal oxide having a structure in which the first region and the second region are mixed.

[0274] Here, the atomic ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in In-Ga-Zn oxide are denoted as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS of In-Ga-Zn oxide, the first region is the region where [In] is greater than the [In] in the composition of the CAC-OS film. The second region is the region where [Ga] is greater than the [Ga] in the composition of the CAC-OS film. Alternatively, for example, the first region is the region where [In] is greater than the [In] in the second region, and [Ga] is smaller than the [Ga] in the second region. The second region is the region where [Ga] is greater than the [Ga] in the first region, and [In] is smaller than the [In] in the first region.

[0275] Specifically, the first region described above is a region whose main components are indium oxide, indium zinc oxide, etc. The second region described above is a region whose main components are gallium oxide, gallium zinc oxide, etc. In other words, the first region can be rephrased as a region whose main component is In. Similarly, the second region can be rephrased as a region whose main component is Ga.

[0276] Furthermore, a clear boundary may not be observed between the first region and the second region described above.

[0277] For example, in the case of CAC-OS in In-Ga-Zn oxide, EDX mapping obtained using energy dispersive X-ray spectroscopy (EDX) confirms that it has a structure in which regions mainly composed of In (first region) and regions mainly composed of Ga (second region) are unevenly distributed and mixed.

[0278] When CAC-OS is used in a transistor, the conductivity due to the first region and the insulation due to the second region work complementaryly to give CAC-OS a switching function (on / off function). In other words, CAC-OS has conductive function in part of the material, insulating function in part of the material, and semiconductor function as a whole. By separating the conductive function and the insulating function, both functions can be maximized. Therefore, by using CAC-OS in a transistor, a high on-current (I) can be achieved. on This enables high field-effect mobility (μ) and good switching operation.

[0279] Oxide semiconductors can take on diverse structures, each possessing different properties. One embodiment of the present invention may include two or more of the following: amorphous oxide semiconductors, polycrystalline oxide semiconductors, a-like OS, CAC-OS, nc-OS, and CAAC-OS.

[0280] <Transistors containing oxide semiconductors> Next, we will explain the case where the above oxide semiconductor is used in a transistor.

[0281] By using the above-mentioned oxide semiconductor in transistors, it is possible to realize transistors with high field-effect mobility. Furthermore, it is possible to realize highly reliable transistors.

[0282] It is preferable to use an oxide semiconductor with a low carrier concentration in the channel formation region of a transistor. For example, the carrier concentration in the channel formation region of an oxide semiconductor is 1 × 10⁻⁶. 17 cm -3 The following is preferably 1 × 10 15 cm -3 More preferably 1 × 10 13 cm -3 More preferably 1 × 10 11 cm -3 More preferably 1 × 10 10 cm -3It is less than 1 × 10 -9 cm -3 This concludes the explanation. Furthermore, when lowering the carrier concentration of an oxide semiconductor film, the impurity concentration in the oxide semiconductor film should be lowered to reduce the defect level density. In this specification, a low impurity concentration and low defect level density are referred to as high-purity intrinsic or substantially high-purity intrinsic. Note that oxide semiconductors with low carrier concentrations are sometimes referred to as high-purity intrinsic or substantially high-purity intrinsic oxide semiconductors.

[0283] Furthermore, oxide semiconductor films that are highly pure or substantially highly pure have a low defect level density, which may result in a low trap level density.

[0284] Furthermore, charges trapped in the trap levels of oxide semiconductors can take a long time to disappear, sometimes behaving like fixed charges. Therefore, transistors in which channel formation regions are formed in oxide semiconductors with a high trap level density may exhibit unstable electrical properties.

[0285] Therefore, reducing the impurity concentration in the oxide semiconductor is effective in stabilizing the electrical characteristics of the transistor. Furthermore, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in adjacent films. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0286] <Impurities> Here, we will explain the effects of various impurities in oxide semiconductors.

[0287] In oxide semiconductors, the presence of silicon, one of the Group 14 elements, or carbon, leads to the formation of defect levels in the oxide semiconductor. Therefore, the concentration of silicon or carbon in the channel formation region of the oxide semiconductor and the concentration of silicon or carbon near the interface with the channel formation region (concentration obtained by secondary ion mass spectrometry (SIMS)) are compared by 2 × 10⁻⁶.18 atoms / cm 3 The following is preferably 2 × 10 17 atoms / cm 3 The following applies:

[0288] Furthermore, if an oxide semiconductor contains alkali metals or alkaline earth metals, it may form defect levels and generate carriers. Therefore, transistors using oxide semiconductors containing alkali metals or alkaline earth metals tend to exhibit normally-on characteristics. For this reason, the concentration of alkali metals or alkaline earth metals in the channel formation region of the oxide semiconductor obtained by SIMS should be set to 1 × 10⁻⁶. 18 atoms / cm 3 The following is preferably 2 × 10 16 atoms / cm 3 Do the following:

[0289] Furthermore, in oxide semiconductors, the presence of nitrogen generates electrons, which act as carriers, increasing the carrier concentration and making it easier for the semiconductor to become n-type. As a result, transistors using oxide semiconductors containing nitrogen tend to exhibit normally-on characteristics. Alternatively, the presence of nitrogen in oxide semiconductors can lead to the formation of trap levels. As a result, the electrical properties of the transistor may become unstable. For this reason, the nitrogen concentration in the channel formation region of oxide semiconductors obtained by SIMS should be set to 5 × 10⁻⁶. 19 atoms / cm 3 Less than 5 × 10 18 atoms / cm 3 More preferably 1 × 10 18 atoms / cm 3 More preferably 5 × 10 17 atoms / cm 3 Do the following:

[0290] In addition, hydrogen contained in an oxide semiconductor may react with oxygen bonded to a metal atom to form water, thereby forming oxygen vacancies. When hydrogen enters these oxygen vacancies, electrons, which are carriers, may be generated. Also, a part of hydrogen may bond with oxygen bonded to a metal atom to generate electrons, which are carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen tends to have normally-on characteristics. For this reason, it is preferable that hydrogen in the channel formation region of the oxide semiconductor be reduced as much as possible. Specifically, in the channel formation region of the oxide semiconductor, the hydrogen concentration obtained by SIMS is less than 1×10 20 atoms / cm 3 , preferably less than 5×10 19 atoms / cm 3 , more preferably less than 1×10 19 atoms / cm 3 , still more preferably less than 5×10 18 atoms / cm 3 , still more preferably less than 1×10 18 atoms / cm 3 .

[0291] By using an oxide semiconductor with sufficiently reduced impurities in the channel formation region of a transistor, stable electrical characteristics can be imparted.

[0292] <<Other semiconductor materials>> The semiconductor materials that can be used for the oxide 230 are not limited to the metal oxides described above. As the oxide 230, a semiconductor material having a bandgap (a semiconductor material that is not a zero-gap semiconductor) may be used. For example, it is preferable to use a single-element semiconductor such as silicon, a compound semiconductor such as gallium arsenide, or a layer material that functions as a semiconductor (also referred to as an atomic layer material, a two-dimensional material, etc.) as the semiconductor material. In particular, it is suitable to use a layer material that functions as a semiconductor as the semiconductor material.

[0293] Herein, in this specification, "layered material" refers to a general term for a group of materials having a layered crystalline structure. A layered crystalline structure is a structure in which layers formed by covalent or ionic bonds are stacked via weaker bonds than covalent or ionic bonds, such as van der Waals forces. Layered materials have high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, it is possible to provide a transistor with a large on-current.

[0294] Layered materials include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogens. Chalcogens are a general term for elements belonging to Group 16, and include oxygen, sulfur, selenium, tellurium, polonium, and livermorium. Examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides.

[0295] As oxide 230, it is preferable to use, for example, a transition metal chalcogenide that functions as a semiconductor. Specific examples of transition metal chalcogenides applicable as oxide 230 include molybdenum sulfide (typically MoS2), molybdenum selenide (typically MoSe2), molybdenum tellurium (typically MoTe2), tungsten sulfide (typically WS2), tungsten selenide (typically WSe2), tungsten tellurium (typically WTe2), hafnium sulfide (typically HfS2), hafnium selenide (typically HfSe2), zirconium sulfide (typically ZrS2), and zirconium selenide (typically ZrSe2).

[0296] <Method for fabricating semiconductor devices> Next, a method for manufacturing a semiconductor device, which is one embodiment of the present invention as shown in Figures 6A to 6D, will be explained using Figures 9A to 18D.

[0297] In each figure, A shows a top view. In each figure, B is a cross-sectional view corresponding to the area indicated by the dashed line A1-A2 in A, and is also a cross-sectional view of transistor 200 in the channel length direction. In each figure, C is a cross-sectional view corresponding to the area indicated by the dashed line A3-A4 in A, and is also a cross-sectional view of transistor 200 in the channel width direction. In each figure, D is a cross-sectional view of the area indicated by the dashed line A5-A6 in A. Note that in the top view A of each figure, some elements have been omitted for clarity.

[0298] In the following, insulating materials for forming insulators, conductive materials for forming conductors, or semiconductor materials for forming semiconductors can be deposited using methods such as sputtering, CVD, MBE, PLD, and ALD as appropriate.

[0299] Sputtering methods include RF sputtering, which uses a high-frequency power supply; DC sputtering, which uses a direct current power supply; and pulsed DC sputtering, which changes the voltage applied to the electrodes in pulses. RF sputtering is mainly used for depositing insulating films, while DC sputtering is mainly used for depositing conductive metal films. Pulsed DC sputtering is mainly used when depositing compounds such as oxides, nitrides, and carbides using reactive sputtering.

[0300] Furthermore, CVD methods can be classified into plasma CVD (PECVD), which utilizes plasma; thermal CVD (TCVD), which utilizes heat; and photo CVD (Photo CVD), which utilizes light. They can also be further divided into metal CVD (MCVD) and metal-organic CVD (MOCVD) depending on the source gas used.

[0301] Plasma CVD allows for the production of high-quality films at relatively low temperatures. Thermal CVD, on the other hand, does not use plasma, thus minimizing plasma damage to the workpiece. For example, wiring, electrodes, and elements (transistors, capacitive elements, etc.) contained in semiconductor devices can be charged up by receiving charge from the plasma. In this case, the accumulated charge can destroy the wiring, electrodes, and elements contained in the semiconductor device. In contrast, thermal CVD, which does not use plasma, does not cause such plasma damage, thus increasing the yield of semiconductor devices. Furthermore, because thermal CVD does not cause plasma damage during film formation, films with fewer defects can be obtained.

[0302] Furthermore, ALD methods that can be used include thermal ALD, which carries out the reaction of the precursor and reactant using only thermal energy, and PEALD, which uses plasma-excited reactants.

[0303] CVD and ALD methods differ from sputtering, where particles emitted from a target or other source are deposited. Therefore, they are less affected by the shape of the workpiece and provide good step-level coating. In particular, the ALD method is suitable for coating the surface of openings with high aspect ratios due to its excellent step-level coating and uniform thickness. However, because the ALD method has a relatively slow deposition rate, it is sometimes preferable to use it in combination with other deposition methods that have a faster deposition rate, such as the CVD method.

[0304] Furthermore, the CVD method allows for the deposition of films with arbitrary compositions by changing the flow rate ratio of the source gases. For example, in the CVD method, films with continuously changing compositions can be deposited by changing the flow rate ratio of the source gases while the film is being deposited. When depositing films while changing the flow rate ratio of the source gases, the time required for film deposition can be shortened compared to depositing films using multiple deposition chambers, because the time required for transport and pressure adjustment is eliminated. Therefore, it may be possible to increase the productivity of semiconductor devices.

[0305] Furthermore, the ALD method allows for the deposition of films of any composition by simultaneously introducing multiple different types of precursors, or by controlling the number of cycles for each precursor.

[0306] First, a substrate (not shown) is prepared, and an insulator 212 is deposited on the substrate (see Figures 9A to 9D). The deposition of the insulator 212 is preferably carried out using a sputtering method. By using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration in the insulator 212 can be reduced. However, the deposition of the insulator 212 is not limited to the sputtering method; CVD, MBE, PLD, ALD, etc., may be used as appropriate.

[0307] In this embodiment, silicon nitride is deposited as the insulator 212 using a silicon target in a nitrogen gas atmosphere by pulsed DC sputtering. By using pulsed DC sputtering, the generation of particles due to arcing on the target surface can be suppressed, making the film thickness distribution more uniform. Furthermore, by using a pulsed voltage, the rise and fall of the discharge can be made steeper than with a high-frequency voltage. This allows for more efficient power supply to the electrode, improving the sputtering rate and film quality.

[0308] By using an insulator that is impermeable to impurities such as water and hydrogen, such as silicon nitride, the diffusion of impurities such as water and hydrogen contained in the layer below the insulator 212 can be suppressed. Furthermore, by using an insulator that is impermeable to copper, such as silicon nitride, as the insulator 212, even if a diffusive metal such as copper is used in the conductor layer below the insulator 212 (not shown), the diffusion of that metal upward through the insulator 212 can be suppressed.

[0309] Next, an insulator 214 is deposited on the insulator 212 (see Figures 9A to 9D). The deposition of the insulator 214 is preferably carried out using a sputtering method. By using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration in the insulator 214 can be reduced. However, the deposition of the insulator 214 is not limited to the sputtering method; CVD, MBE, PLD, ALD, etc., may be used as appropriate.

[0310] In this embodiment, aluminum oxide is deposited as the insulator 214 using a pulsed DC sputtering method with an aluminum target in an atmosphere containing oxygen gas. By using the pulsed DC sputtering method, the film thickness distribution can be made more uniform, and the sputtering rate and film quality can be improved. Here, RF (Radio Frequency) power may be applied to the substrate. The amount of oxygen injected into the layer below the insulator 214 can be controlled by the magnitude of the RF power applied to the substrate. The RF power is 0 W / cm². 2 The above is 1.86 W / cm². 2 The following applies: In other words, the amount of oxygen injected can be varied to suit the characteristics of the transistor by changing the RF power used during the formation of the insulator 214. Therefore, an amount of oxygen suitable for improving the reliability of the transistor can be injected. Furthermore, the RF frequency is preferably 10 MHz or higher. Typically, it is 13.56 MHz. The higher the RF frequency, the less damage can be inflicted on the substrate.

[0311] It is preferable to use an amorphous metal oxide, such as aluminum oxide, as the insulator 214, which has a high ability to capture and fix hydrogen. This allows for the capture or fixation of hydrogen contained in the insulator 216, etc., preventing the hydrogen from diffusing into the oxide 230. In particular, it is preferable to use amorphous aluminum oxide, or aluminum oxide with an amorphous structure, as the insulator 214, as this may allow for more effective capture or fixation of hydrogen. This makes it possible to fabricate a transistor 200 and semiconductor device with good properties and high reliability.

[0312] Next, an insulator 216 is deposited on the insulator 214. The deposition of the insulator 216 is preferably carried out using a sputtering method. By using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration in the insulator 216 can be reduced. However, the deposition of the insulator 216 is not limited to the sputtering method; CVD, MBE, PLD, ALD, etc., may be used as appropriate.

[0313] In this embodiment, silicon oxide is deposited as the insulator 216 using a silicon target in an atmosphere containing oxygen gas by pulsed DC sputtering. By using the pulsed DC sputtering method, the film thickness distribution can be made more uniform, and the sputtering rate and film quality can be improved.

[0314] It is preferable to continuously deposit insulators 212, 214, and 216 without exposure to the atmosphere. For example, a multi-chamber type deposition apparatus can be used. This allows for the deposition of insulators 212, 214, and 216 with reduced hydrogen content in the films, and further reduces the incorporation of hydrogen into the films between each deposition process.

[0315] Next, an opening is formed in the insulator 216 that reaches the insulator 214. The opening includes, for example, grooves and slits. In some cases, the term "opening" refers to the region in which the opening is formed. The opening may be formed using wet etching, but dry etching is preferable for microfabrication. Furthermore, it is preferable to select an insulator 214 that functions as an etching stopper film when etching the insulator 216 to form grooves. For example, if silicon oxide or silicon oxynitride is used for the insulator 216 in which grooves are formed, then silicon nitride, aluminum oxide, or hafnium oxide may be used for the insulator 214.

[0316] As a dry etching apparatus, a capacitively coupled plasma (CCP) etching apparatus having parallel plate electrodes can be used. The capacitively coupled plasma etching apparatus having parallel plate electrodes may be configured to apply a high-frequency voltage to one electrode of the parallel plate electrodes. Alternatively, it may be configured to apply multiple different high-frequency voltages to one electrode of the parallel plate electrodes. Alternatively, it may be configured to apply a high-frequency voltage of the same frequency to each of the parallel plate electrodes. Alternatively, it may be configured to apply high-frequency voltages of different frequencies to each of the parallel plate electrodes. Alternatively, a dry etching apparatus having a high-density plasma source can be used. A dry etching apparatus having a high-density plasma source may be, for example, an inductively coupled plasma (ICP) etching apparatus.

[0317] After the opening is formed, a conductive film that will become the conductor 205a is deposited. It is desirable that the conductive film contains a conductor that has the function of suppressing oxygen permeation. For example, tantalum nitride, tungsten nitride, titanium nitride, etc. can be used. Alternatively, a laminated film can be formed of a conductor that has the function of suppressing oxygen permeation and a tantalum, tungsten, titanium, molybdenum, aluminum, copper, or molybdenum-tungsten alloy. The conductive film can be deposited using sputtering, CVD, MBE, PLD, ALD, etc.

[0318] In this embodiment, a titanium nitride film is formed as the conductive film that will become the conductor 205a. By using such a metal nitride as the layer beneath the conductor 205b, oxidation of the conductor 205b by the insulator 216 and the like can be suppressed. Furthermore, even if a highly diffusive metal such as copper is used as the conductor 205b, it is possible to prevent the metal from diffusing out of the conductor 205a.

[0319] Next, a conductive film to form the conductor 205b is deposited. This conductive film can be made of materials such as tantalum, tungsten, titanium, molybdenum, aluminum, copper, or a molybdenum-tungsten alloy. The conductive film can be deposited using methods such as plating, sputtering, CVD, MBE, PLD, or ALD. In this embodiment, a tungsten film is deposited as the conductive film.

[0320] Next, by performing CMP treatment, a portion of the conductive film that will become conductor 205a and a portion of the conductive film that will become conductor 205b are removed, exposing the insulator 216 (see Figures 9A to 9D). As a result, conductor 205a and conductor 205b remain only in the opening. Note that a portion of the insulator 216 may be removed by this CMP treatment.

[0321] Next, an insulator 222 is deposited on the insulator 216 and the conductor 205 (see Figures 9A to 9D). The insulator 222 may be made from an insulator containing an oxide of either or both aluminum and hafnium. An insulator containing an oxide of either or both aluminum and hafnium has barrier properties against oxygen, hydrogen, and water. Because the insulator 222 has barrier properties against hydrogen and water, the diffusion of hydrogen and water contained in the structures surrounding the transistor 200 into the transistor 200 through the insulator 222 is suppressed, thereby suppressing the formation of oxygen vacancies in the oxide 230.

[0322] The insulator 222 can be deposited using methods such as sputtering, CVD, MBE, PLD, and ALD. In this embodiment, hafnium oxide is deposited as the insulator 222 using the ALD method.

[0323] Next, it is preferable to perform a heat treatment. The heat treatment should be performed at a temperature of 250°C to 650°C, preferably 300°C to 500°C, and more preferably 320°C to 450°C. The heat treatment should be performed in an atmosphere of nitrogen gas or an inert gas, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, when performing the heat treatment in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas should be about 20%. The heat treatment may also be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere of nitrogen gas or an inert gas, and then further in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to replenish the desorbed oxygen.

[0324] Furthermore, it is preferable that the gas used in the above heat treatment is highly purified. For example, the amount of water contained in the gas used in the above heat treatment should be 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, it is possible to prevent as much as possible from moisture or other substances being incorporated into the insulator 222 and the like.

[0325] In this embodiment, as a heat treatment, after the insulator 222 is formed, a nitrogen gas to oxygen gas flow rate ratio of 4 slm:1 slm is used, and the treatment is performed at a temperature of 400°C for 1 hour. This heat treatment can remove impurities such as water and hydrogen contained in the insulator 222. Furthermore, when an oxide containing hafnium is used as the insulator 222, a portion of the insulator 222 may crystallize as a result of this heat treatment. The heat treatment can also be performed at a later time, such as after the insulator 224 is formed.

[0326] Next, an insulating film 224A is deposited on the insulator 222 (see Figures 9A to 9D). The insulating film 224A can be deposited using sputtering, CVD, MBE, PLD, ALD, etc. In this embodiment, a silicon oxide film is deposited as the insulating film 224A using the sputtering method. By using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration in the insulating film 224A can be reduced. Since the insulating film 224A will come into contact with the oxide 230a in a later step, it is preferable that the hydrogen concentration is reduced in this way.

[0327] Next, oxide films 230A and 230B are sequentially deposited on the insulating film 224A (see Figures 9A to 9D). It is preferable to deposit oxide films 230A and 230B continuously without exposing them to the atmosphere. By depositing the films without exposure to the atmosphere, it is possible to prevent impurities or moisture from the atmosphere from adhering to oxide films 230A and 230B, and to keep the area near the interface between oxide films 230A and 230B clean.

[0328] The oxide films 230A and 230B can be deposited using sputtering, CVD, MBE, PLD, ALD, and the like. The ALD method is preferred for depositing oxide films 230A and 230B because it allows for the formation of films with uniform thickness even in grooves or openings with large aspect ratios. The PEALD method is also preferred because it allows for the formation of oxide films 230A and 230B at lower temperatures compared to the thermal ALD method. In this embodiment, the oxide films 230A and 230B are deposited using sputtering.

[0329] For example, when depositing oxide films 230A and 230B by sputtering, oxygen or a mixture of oxygen and a noble gas is used as the sputtering gas. By increasing the proportion of oxygen in the sputtering gas, the excess oxygen in the deposited oxide film can be increased. Furthermore, when depositing the above oxide films by sputtering, the above-mentioned In-M-Zn oxide target can be used.

[0330] In particular, during the formation of the oxide film 230A, some of the oxygen contained in the sputtering gas may be supplied to the insulator 224. Therefore, the proportion of oxygen contained in the sputtering gas should be 70% or more, preferably 80% or more, and more preferably 100%.

[0331] Furthermore, when the oxide film 230B is formed by sputtering, if the proportion of oxygen in the sputtering gas is set to be more than 30% but 100% or less, preferably 70% or more but 100%, an oxygen-rich oxide semiconductor is formed. Transistors using an oxygen-rich oxide semiconductor in the channel formation region can achieve relatively high reliability. However, the present invention is not limited to this. When the oxide film 230B is formed by sputtering, if the proportion of oxygen in the sputtering gas is set to be 1% or more but 30% or less, preferably 5% or more but 20%, an oxygen-deficient oxide semiconductor is formed. Transistors using an oxygen-deficient oxide semiconductor in the channel formation region can achieve relatively high field-effect mobility. In addition, the crystallinity of the oxide film can be improved by performing film formation while heating the substrate.

[0332] In this embodiment, oxide film 230A is formed by sputtering using an oxide target with an In:Ga:Zn ratio of 1:3:4. Oxide film 230B is formed by sputtering using an oxide target with an In:Ga:Zn ratio of 4:2:4.1, an In:Ga:Zn ratio of 1:1:1, or an In:Ga:Zn ratio of 1:1:2. Each oxide film can be formed according to the desired properties of oxide 230a and oxide 230b by appropriately selecting the deposition conditions and atomic ratios.

[0333] Furthermore, it is preferable to deposit the insulating film 224A, oxide film 230A, and oxide film 230B by sputtering without exposure to the atmosphere. For example, a multi-chamber type deposition apparatus can be used. This reduces the incorporation of hydrogen into the films between each deposition process for the insulating film 224A, oxide film 230A, and oxide film 230B.

[0334] Next, it is preferable to perform a heat treatment. The heat treatment should be performed within a temperature range in which the oxide films 230A and 230B do not undergo polycrystallization, and should be performed between 250°C and 650°C, preferably between 400°C and 600°C. The heat treatment should be performed in an atmosphere of nitrogen gas or an inert gas, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, when performing the heat treatment in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas should be about 20%. The heat treatment may also be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere of nitrogen gas or an inert gas, and then in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to replenish the desorbed oxygen.

[0335] Furthermore, it is preferable that the gas used in the above heat treatment is highly purified. For example, the amount of water contained in the gas used in the above heat treatment should be 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, it is possible to prevent as much as possible from the incorporation of water and other substances into the oxide film 230A, oxide film 230B, etc.

[0336] In this embodiment, the heat treatment involves a nitrogen gas to oxygen gas flow rate ratio of 4 slm:1 slm, performed at a temperature of 400°C for 1 hour. This heat treatment containing oxygen gas can reduce impurities such as carbon, water, and hydrogen in the oxide film 230A and oxide film 230B. By reducing impurities in the film in this way, the crystallinity of oxide film 230B can be improved, resulting in a denser, more compact structure. This increases the crystalline region in oxide film 230A and oxide film 230B, and reduces in-plane variation of the crystalline region in oxide film 230A and oxide film 230B. Therefore, in-plane variation of the electrical characteristics of transistor 200 can be reduced.

[0337] Next, a conductive film 242A is deposited on the oxide film 230B (see Figures 9A to 9D). The conductive film 242A can be deposited using sputtering, CVD, MBE, PLD, ALD, etc. For example, a tantalum nitride film can be deposited as the conductive film 242A using sputtering. Before depositing the conductive film 242A, a heat treatment may be performed. This heat treatment may be performed under reduced pressure, and the conductive film 242A may be deposited continuously without exposure to the atmosphere. By performing such a treatment, moisture and hydrogen adsorbed on the surface of the oxide film 230B can be removed, and the moisture and hydrogen concentrations in the oxide film 230A and oxide film 230B can be further reduced. The temperature of the heat treatment is preferably between 100°C and 400°C. In this embodiment, the temperature of the heat treatment is set to 200°C.

[0338] Next, an insulating film 271A is deposited on the conductive film 242A (see Figures 9A to 9D). The insulating film 271A can be deposited using sputtering, CVD, MBE, PLD, ALD, or the like. It is preferable to use an insulating film 271A that has the function of suppressing oxygen permeation. For example, an aluminum oxide film or a silicon nitride film can be deposited as the insulating film 271A by sputtering.

[0339] Furthermore, it is preferable to deposit the conductive film 242A and the insulating film 271A by sputtering without exposure to the atmosphere. For example, a multi-chamber type deposition apparatus may be used. This reduces the amount of hydrogen in the films when depositing the conductive film 242A and the insulating film 271A, and also reduces the amount of hydrogen introduced into the films between each deposition process. In addition, if a hard mask is provided on the insulating film 271A, the hard mask film may also be deposited continuously without exposure to the atmosphere.

[0340] Next, the insulating film 224A, oxide film 230A, oxide film 230B, conductive film 242A, and insulating film 271A are processed into island-like structures using lithography to form the insulator 224, oxide 230a, oxide 230b, conductive layer 242B, and insulating layer 271B (see Figures 10A to 10D). Here, the insulator 224, oxide 230a, oxide 230b, conductive layer 242B, and insulating layer 271B are formed so that at least a portion of them overlaps with the conductor 205. The above processing can be performed using either dry etching or wet etching. Dry etching is suitable for microfabrication. Furthermore, the processing of the insulating film 224A, oxide film 230A, oxide film 230B, conductive film 242A, and insulating film 271A may be carried out under different conditions.

[0341] In lithography, the resist is first exposed through a mask. Next, the exposed area is removed or left intact using a developer to form a resist mask. Then, the conductor, semiconductor, or insulator can be processed into a desired shape by etching through the resist mask. For example, the resist mask can be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, or EUV (Extreme Ultraviolet) light. Alternatively, immersion technology can be used, in which a liquid (e.g., water) is filled between the substrate and the projection lens for exposure. In addition, an electron beam or ion beam may be used instead of the aforementioned light. When using an electron beam or ion beam, a mask is not required. The resist mask can be removed by dry etching such as ashing, wet etching, wet etching after dry etching, or dry etching after wet etching.

[0342] Furthermore, a hard mask made of an insulator or conductor may be used beneath the resist mask. When using a hard mask, an insulating film or conductive film that serves as the hard mask material is formed on the conductive film 242A, a resist mask is formed on top of it, and a hard mask of the desired shape can be formed by etching the hard mask material. Etching of the conductive film 242A, etc., may be performed after removing the resist mask, or it may be performed while the resist mask remains. In the latter case, the resist mask may disappear during etching. The hard mask may also be removed by etching after etching of the conductive film 242A, etc. On the other hand, if the hard mask material does not affect subsequent processes or can be used in subsequent processes, it is not always necessary to remove the hard mask. In this embodiment, an insulating layer 271B is used as the hard mask.

[0343] Here, since the insulating layer 271B functions as a mask for the conductive layer 242B, the conductive layer 242B does not have a curved surface between its side and top surfaces, as shown in Figures 10B to 10D. As a result, the conductor 242 shown in Figures 6B and 6D has a angular end where the side and top surfaces meet. Because the end where the side and top surfaces of the conductor 242 meet is angular, the cross-sectional area of ​​the conductor 242 is larger compared to when that end has a curved surface. As a result, the resistance of the conductor 242 is reduced, and the on-current of the transistor 200 can be increased.

[0344] Furthermore, as shown in Figures 10B to 10D, the cross-sections of the insulator 224, oxide 230a, oxide 230b, conductive layer 242B, and insulating layer 271B may be tapered. In this specification, a tapered shape refers to a shape in which at least a part of the side surface of the structure is inclined with respect to the substrate surface. For example, it is preferable that the angle between the inclined side surface and the substrate surface (hereinafter sometimes referred to as the taper angle) is less than 90°. For example, the insulator 224, oxide 230a, oxide 230b, conductive layer 242B, and insulating layer 271B may have a taper angle of 60° or more and less than 90°. By making the cross-section tapered in this way, the coverage of the insulator 275 and other materials can be improved in subsequent processes, and defects such as porosity can be reduced.

[0345] However, the above is not limited to the above, and the sides of the insulator 224, oxide 230a, oxide 230b, conductive layer 242B, and insulating layer 271B may be configured to be approximately perpendicular to the upper surface of the insulator 222. Such a configuration makes it possible to reduce the area and increase the density when providing multiple transistors 200.

[0346] Furthermore, by-products generated during the etching process may form in layers on the sides of the insulator 224, oxide 230a, oxide 230b, conductive layer 242B, and insulating layer 271B. In this case, the layered by-products will be formed between the insulator 224, oxide 230a, oxide 230b, conductive layer 242B, and insulating layer 271B and the insulator 275. Therefore, it is preferable to remove the layered by-products formed in contact with the upper surface of the insulator 222.

[0347] Next, an insulator 275 is formed by covering the insulator 224, oxide 230a, oxide 230b, conductive layer 242B, and insulating layer 271B (see Figures 11A to 11D). Here, it is preferable that the insulator 275 is in close contact with the upper surface of the insulator 222 and the side surface of the insulator 224. The insulator 275 can be formed using sputtering, CVD, MBE, PLD, ALD, etc. It is preferable that the insulator 275 is an insulating film that has the function of suppressing oxygen permeation. For example, as the insulator 275, aluminum oxide can be formed using the sputtering method, and silicon nitride can be formed on top of it using the PEALD method. By making the insulator 275 such a layered structure, the function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen may be improved.

[0348] In this way, oxide 230a, oxide 230b, and conductive layer 242B can be covered with insulator 275 and insulating layer 271B, which have the function of suppressing oxygen diffusion. This reduces the direct diffusion of oxygen from insulator 280, etc., to insulator 224, oxide 230a, oxide 230b, and conductive layer 242B in subsequent processes.

[0349] Next, an insulating film, which will become an insulator 280, is deposited on the insulator 275. The insulating film can be deposited using sputtering, CVD, MBE, PLD, ALD, or the like. For example, a silicon oxide film can be deposited as the insulating film using sputtering. By depositing the insulating film using sputtering in an oxygen-containing atmosphere, an insulator 280 containing excess oxygen can be formed. Furthermore, by using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration in the insulator 280 can be reduced. Note that a heat treatment may be performed before depositing the insulating film. The heat treatment may be performed under reduced pressure, and the insulating film may be deposited continuously without exposure to the atmosphere. By performing such a treatment, moisture and hydrogen adsorbed on the surface of the insulator 275 can be removed, and the moisture and hydrogen concentrations in the oxide 230a, oxide 230b, and insulator 224 can be further reduced. The heat treatment conditions described above can be used for this heat treatment.

[0350] Next, the insulating film that will become the insulator 280 is subjected to CMP treatment to form an insulator 280 with a flat top surface (see Figures 11A to 11D). Alternatively, silicon nitride may be deposited on the insulator 280 by, for example, a sputtering method, and the silicon nitride may be subjected to CMP treatment until it reaches the insulator 280.

[0351] Next, a portion of the insulator 280, a portion of the insulator 275, a portion of the insulating layer 271B, and a portion of the conductive layer 242B are processed to form an opening that reaches the oxide 230b. It is preferable that the opening be formed so as to overlap with the conductor 205. The formation of the opening creates the insulator 271a, the insulator 271b, the conductor 242a, and the conductor 242b (see Figures 12A to 12D).

[0352] Here, as shown in Figures 12B and 12C, the sides of the insulators 280, 275, 271, and conductor 242 may be tapered. Also, the taper angle of the insulator 280 may be larger than the taper angle of the conductor 242. Furthermore, although not shown in Figures 12A to 12C, the upper part of the oxide 230b may be removed when forming the above-mentioned opening.

[0353] Furthermore, the processing of a portion of the insulator 280, a portion of the insulator 275, a portion of the insulating layer 271B, and a portion of the conductive layer 242B can be carried out using either a dry etching method or a wet etching method. Dry etching is suitable for microfabrication. Moreover, these processing methods may be carried out under different conditions. For example, a portion of the insulator 280 may be processed by dry etching, a portion of the insulator 275 and a portion of the insulating layer 271B may be processed by wet etching, and a portion of the conductive layer 242B may be processed by dry etching.

[0354] Here, impurities may adhere to the sides of oxide 230a, the top and sides of oxide 230b, the sides of conductor 242, the sides of insulator 280, etc., and these impurities may diffuse into the interior. A step to remove such impurities may be performed. In addition, a damaged area may be formed on the surface of oxide 230b during the dry etching. Such a damaged area may be removed. Examples of such impurities include components contained in insulator 280, insulator 275, insulating layer 271B, and conductive layer 242B, components contained in materials used in the apparatus used to form the opening, and components contained in the gas or liquid used for etching. Examples of such impurities include hafnium, aluminum, silicon, tantalum, fluorine, and chlorine.

[0355] In particular, impurities such as aluminum and silicon inhibit the CAAC-OS conversion of oxide 230b. Therefore, it is preferable that impurity elements that inhibit CAAC-OS conversion, such as aluminum and silicon, are reduced or removed. For example, the concentration of aluminum atoms in oxide 230b and its vicinity should be 5.0 atomic% or less, preferably 2.0 atomic% or less, more preferably 1.5 atomic% or less, even more preferably 1.0 atomic% or less, and even more preferably less than 0.3 atomic%.

[0356] Furthermore, the region of metal oxides where CAAC-OS formation is inhibited by impurities such as aluminum and silicon, resulting in a-like OS, is sometimes called the non-CAAC region. In the non-CAAC region, the density of the crystal structure is reduced, therefore V O A large amount of H is formed, making it easier for the transistor to become normally-on. Therefore, it is preferable that the non-CAAC region of oxide 230b is reduced or removed.

[0357] In contrast, it is preferable that the oxide 230b has a layered CAAC structure. In particular, it is preferable that the CAAC structure extends to the lower end of the drain of the oxide 230b. Here, in the transistor 200, the conductor 242a or conductor 242b, and its vicinity, function as a drain. That is, it is preferable that the oxide 230b near the lower end of the conductor 242a (conductor 242b) has a CAAC structure. In this way, even at the drain end, which significantly affects the drain breakdown voltage, the damaged region of the oxide 230b is removed and a CAAC structure is present, which further suppresses fluctuations in the electrical characteristics of the transistor 200. Furthermore, the reliability of the transistor 200 can be improved.

[0358] In order to remove impurities and other contaminants adhering to the oxide 230b surface during the etching process described above, a cleaning treatment is performed. Cleaning methods include wet cleaning using a cleaning solution (which can also be called wet etching), plasma treatment using plasma, and heat treatment. These cleaning methods may be combined as appropriate. Note that this cleaning treatment may deepen the grooves.

[0359] Wet cleaning may be performed using aqueous solutions of ammonia water, oxalic acid, phosphoric acid, hydrofluoric acid, etc., diluted with carbonated water or distilled water, distilled water, carbonated water, etc. Alternatively, ultrasonic cleaning may be performed using these aqueous solutions, distilled water, or carbonated water. Alternatively, these cleaning methods may be combined as appropriate.

[0360] In this specification, an aqueous solution obtained by diluting hydrofluoric acid with pure water is sometimes referred to as diluted hydrofluoric acid, and an aqueous solution obtained by diluting ammonia water with pure water is sometimes referred to as diluted ammonia water. The concentration and temperature of the aqueous solution may be adjusted as appropriate depending on the impurities to be removed and the configuration of the semiconductor device to be cleaned. The ammonia concentration of the diluted ammonia water should be 0.01% to 5%, preferably 0.1% to 0.5%. The hydrogen fluoride concentration of the diluted hydrofluoric acid should be 0.01 ppm to 100 ppm, preferably 0.1 ppm to 10 ppm.

[0361] For ultrasonic cleaning, a frequency of 200 kHz or higher is preferred, and a frequency of 900 kHz or higher is even more preferred. Using this frequency can reduce damage to oxides such as 230b.

[0362] Furthermore, the above cleaning process may be performed multiple times, and the cleaning solution may be changed each time. For example, the first cleaning process may be performed using diluted hydrofluoric acid or diluted ammonia water, and the second cleaning process may be performed using pure water or carbonated water.

[0363] In this embodiment, the cleaning process described above involves wet cleaning using diluted ammonia water. This cleaning process removes impurities that have adhered to the surface or diffused into the interior of oxides 230a and 230b. Furthermore, it can improve the crystallinity of oxide 230b.

[0364] Heat treatment may be performed after the etching or cleaning described above. The heat treatment should be performed at a temperature of 100°C to 450°C, preferably 350°C to 400°C. The heat treatment should be performed in an atmosphere of nitrogen gas or an inert gas, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, it is preferable to perform the heat treatment in an oxygen atmosphere. This allows oxygen to be supplied to oxides 230a and 230b, thereby reducing oxygen deficiency. Furthermore, such heat treatment can improve the crystallinity of oxide 230b. The heat treatment may also be performed under reduced pressure. Alternatively, after heat treatment in an oxygen atmosphere, continuous heat treatment in a nitrogen atmosphere may be performed without exposure to the atmosphere.

[0365] Next, the insulating film 252A is deposited (see Figures 13A to 13D). The insulating film 252A can be deposited using sputtering, CVD, MBE, PLD, ALD, etc. It is preferable to deposit the insulating film 252A using the ALD method. As mentioned above, it is preferable to deposit the insulating film 252A with a thin film thickness, and it is necessary to minimize variations in film thickness. In contrast, the ALD method is a film deposition method that alternately introduces a precursor and a reactant (e.g., an oxidizing agent), and the film thickness can be adjusted by the number of times this cycle is repeated, thus enabling precise film thickness adjustment. Also, as shown in Figures 13B and 13C, the insulating film 252A needs to be deposited with good coverage on the bottom and side surfaces of openings formed in the insulator 280, etc. In particular, it is preferable to deposit it with good coverage on the top and side surfaces of the oxide 230 and the side surfaces of the conductor 242. Since atomic layers can be deposited one by one on the bottom and sides of the opening, the insulating film 252A can be formed on the opening with good coverage.

[0366] Furthermore, when the insulating film 252A is deposited by the ALD method, ozone (O3), oxygen (O2), water (H2O), etc., can be used as oxidizing agents. By using hydrogen-free oxidizing agents such as ozone (O3) and oxygen (O2), the amount of hydrogen diffusing into the oxide 230b can be reduced.

[0367] In this embodiment, an aluminum oxide film is formed as the insulating film 252A by thermal ALD method.

[0368] Next, an insulating film 250A is deposited (see Figures 13A to 13D). A heat treatment may be performed before depositing the insulating film 250A, and this heat treatment may be carried out under reduced pressure, allowing for continuous deposition of the insulating film 250A without exposure to the atmosphere. Furthermore, it is preferable to carry out this heat treatment in an atmosphere containing oxygen. By performing such a treatment, moisture and hydrogen adsorbed on the surface of the insulating film 252A can be removed, and the moisture and hydrogen concentrations in oxide 230a and oxide 230b can be further reduced. The temperature of the heat treatment is preferably between 100°C and 400°C.

[0369] The insulating film 250A can be deposited using methods such as sputtering, CVD, PECVD, MBE, PLD, and ALD. Furthermore, it is preferable to deposit the insulating film 250A using a deposition method that utilizes a gas with reduced or removed hydrogen atoms. This allows for a reduction in the hydrogen concentration of the insulating film 250A. Since the insulating film 250A will later become an insulator 250 facing the oxide 230b via a thin insulating film 252, such a reduction in hydrogen concentration is preferable.

[0370] Furthermore, it is preferable to deposit the insulating film 250A using a film deposition method that provides good coverage. For example, it is preferable to deposit it using the ALD method. This allows the insulating film 250A to be deposited with good coverage over openings formed in the insulator 280, etc., via the insulating film 252A.

[0371] As described above, the film quality of the insulator 250 can be improved by performing microwave treatment in an oxygen-containing atmosphere after depositing the insulating film 250A. Therefore, the deposition temperature of the insulating film 250A may be low. The deposition temperature can be, for example, lower than 400°C, such as 300°C or below, or 250°C or below, and above 100°C. By depositing the insulating film 250A at such a temperature, oxidation of the conductor 242 near the insulating film 250A (especially the side surfaces of the conductor 242) can be suppressed.

[0372] In this embodiment, an organic precursor is used as the insulating film 250A, and a silicon oxide film is deposited by the PEALD method. By depositing the film using the PEALD method, the insulating film 250A can be deposited with a thin film thickness and good coating properties. In this embodiment, an organic precursor is used as the precursor, but an inorganic precursor may also be used.

[0373] Next, it is preferable to perform microwave processing in an oxygen-containing atmosphere (see Figures 13A to 13D). In Figures 13B to 13D, the dotted lines represent microwaves, high-frequency oxygen plasma such as RF, oxygen radicals, etc. In this microwave processing, for example, by applying RF to the substrate side, oxygen ions generated by the high-density plasma can be efficiently guided into the oxide 230b. Furthermore, the processing temperature for this microwave processing should be 150°C to 400°C, preferably 200°C to 300°C, and more preferably around 250°C.

[0374] Furthermore, it is preferable to perform the above microwave treatment in an oxygen-containing atmosphere. By performing the microwave treatment in an oxygen-containing atmosphere, the carrier concentration in region 230bc can be reduced. In addition, by preventing an excessive amount of oxygen from being introduced into the chamber during the microwave treatment, it is possible to prevent an excessive reduction in carrier concentration in regions 230ba and 230bb.

[0375] In addition, for the conditions other than the processing temperature in the above microwave processing, the conditions of the microwave processing described in the previous embodiment may be used. Also, the processing temperature may be 750°C or lower, or 500°C or lower, for example, about 400°C. Further, after performing the microwave processing, heat treatment may be continuously performed without exposing to the outside air. For example, heat treatment may be performed at 100°C or higher and 750°C or lower, preferably 300°C or higher and 500°C or lower.

[0376] As shown in FIGS. 13B to 13D, by performing microwave processing in an oxygen-containing atmosphere, oxygen gas can be plasmaized using microwaves or high-frequency waves such as RF, and the oxygen plasma can be made to act on the region between the conductors 242a and 242b of the oxide 230b. At this time, microwaves or high-frequency waves such as RF can also be irradiated to the region 230bc. That is, microwaves, high-frequency oxygen plasma, etc. can be made to act on the region 230bc shown in FIG. 7A. By the action of plasma, microwaves, etc., the V O H in the region 230bc is separated, and hydrogen (H) can be removed from the region 230bc. That is, in the region 230bc, the reaction of "V O H→H+V O " occurs, and the V O H contained in the region 230bc can be reduced. Therefore, the oxygen deficiency and V O H in the region 230bc can be reduced, and the carrier concentration can be decreased. Further, by supplying oxygen radicals generated by the oxygen plasma or oxygen contained in the insulator 250 to the oxygen deficiency formed in the region 230bc, the oxygen deficiency in the region 230bc can be further reduced, and the carrier concentration can be decreased.

[0377] Meanwhile, conductors 242a and 242b are provided on regions 230ba and 230bb shown in Figure 7A. Here, it is preferable that the conductor 242 functions as a shielding film against the effects of microwaves, high frequencies such as RF, and oxygen plasma when microwave processing is performed in an oxygen-containing atmosphere. For this reason, it is preferable that the conductor 242 has the function of shielding electromagnetic waves between 300 MHz and 300 GHz, for example, between 2.4 GHz and 2.5 GHz.

[0378] As shown in Figures 13B to 13D, conductors 242a and 242b shield against the effects of microwaves or high-frequency oxygen plasma such as RF, so these effects do not extend to regions 230ba and 230bb. As a result, microwave processing does not affect regions 230ba and 230bb. O This reduces H and prevents excessive oxygen supply, thus preventing a decrease in carrier concentration.

[0379] Furthermore, an insulator 252 having barrier properties against oxygen is provided in contact with the sides of the conductors 242a and 242b. This makes it possible to suppress the formation of an oxide film on the sides of the conductors 242a and 242b by microwave processing.

[0380] Furthermore, by depositing the insulating film 250A at a temperature that can suppress oxidation of the conductor 242, and then performing microwave treatment in an oxygen-containing atmosphere, it is possible to form an insulator 250 with reduced hydrogen concentration while suppressing oxidation of the sides of the conductor 242. Therefore, the reliability of the transistor 200 can be improved.

[0381] As described above, oxygen vacancies are selectively created in the oxide semiconductor region 230bc, and V OBy removing H, region 230bc can be made i-type or substantially i-type. Furthermore, the supply of excess oxygen to regions 230ba and 230bb, which function as source or drain regions, can be suppressed, thereby maintaining the n-type configuration. This suppresses variations in the electrical properties of transistor 200 and prevents variations in the electrical properties of transistor 200 within the substrate plane.

[0382] In microwave processing, electromagnetic interaction between microwaves and molecules in oxide 230b can directly transfer thermal energy to oxide 230b. This thermal energy can cause oxide 230b to heat up. This type of heat treatment is sometimes called microwave annealing. Performing microwave processing in an oxygen-containing atmosphere can sometimes achieve effects equivalent to oxygen annealing. Furthermore, if oxide 230b contains hydrogen, this thermal energy may be transferred to the hydrogen in oxide 230b, causing activated hydrogen to be released from oxide 230b.

[0383] In this embodiment, after forming the insulating film 250A, microwave treatment is performed at a processing temperature of 250°C, with an oxygen flow rate ratio (O2 / (O2+Ar)) of 25%, and a processing time of 10 minutes.

[0384] Note that the above microwave treatment may be performed after the deposition of the insulating film 252A. When performing the microwave treatment after the deposition of the insulating film 252A, it is preferable to use the microwave treatment conditions described above.

[0385] Furthermore, when the insulator 250 is made into a two-layer laminated structure as shown in Figure 7B, the insulating film that will become the insulator 250b should be deposited after the insulating film 250A has been deposited. The insulating film can be deposited using sputtering, CVD, MBE, PLD, ALD, or the like. It is preferable that the insulating film be formed using an insulator that has the function of suppressing oxygen diffusion. With this configuration, it is possible to suppress the diffusion of oxygen contained in the insulator 250a to the conductor 260. In other words, it is possible to suppress the decrease in the amount of oxygen supplied to the oxide 230. In addition, it is possible to suppress the oxidation of the conductor 260 by the oxygen contained in the insulator 250a. The insulating film can be made using the same material as the insulator 222. For example, a hafnium oxide film may be deposited as the insulating film by thermal ALD.

[0386] Furthermore, when an insulating film that forms the insulator 250b is provided as described above, microwave treatment may be performed after the insulating film is formed. This microwave treatment may use the same microwave treatment conditions as those used after the formation of the insulating film 252A, or after the formation of the insulating film 250A. Alternatively, microwave treatment may be performed after the formation of the insulating film without performing the microwave treatment that is performed after the formation of the insulating film 252A and / or the insulating film 250A.

[0387] Furthermore, after the deposition of insulating film 252A, insulating film 250A, and insulating film that will become insulator 250b, a heat treatment may be performed while maintaining a reduced pressure state after each microwave treatment. By performing such a treatment, hydrogen can be efficiently removed from insulating film 252A, insulating film 250A, insulating film that will become insulator 250b, oxide 230b, and oxide 230a. In addition, some of the hydrogen may be gettered by the conductor 242. Alternatively, the step of performing a heat treatment while maintaining a reduced pressure state after microwave treatment may be repeated multiple times. By repeating the heat treatment, hydrogen can be removed even more efficiently from insulating film 252A, insulating film 250A, insulating film that will become insulator 250b, oxide 230b, and oxide 230a. The heat treatment temperature is preferably 300°C to 500°C. Furthermore, the above microwave treatment, i.e., microwave annealing, may also serve as the heat treatment. If oxide 230b and the like are sufficiently heated by microwave annealing, the heat treatment may not be necessary.

[0388] Furthermore, by performing microwave treatment to modify the film quality of the insulating film 252A, insulating film 250A, and insulating film 250b, the diffusion of hydrogen, water, impurities, etc. can be suppressed. Therefore, in subsequent processes such as deposition of a conductive film that becomes the conductor 260, or post-treatment such as heat treatment, the diffusion of hydrogen, water, impurities, etc., to oxides 230b, oxides 230a, etc., via the insulating film 252 can be suppressed.

[0389] Next, the insulating film 254A is deposited (see Figures 14A to 14D). The insulating film 254A can be deposited using sputtering, CVD, MBE, PLD, ALD, etc. It is preferable to deposit the insulating film 254A using the ALD method, similar to the insulating film 252A. By depositing the film using the ALD method, the insulating film 254A can be deposited with a thin film thickness and good coverage. In this embodiment, a silicon nitride film is deposited as the insulating film 254A using the PEALD method.

[0390] Next, microwave treatment may be performed in an oxygen-containing atmosphere. For microwave treatment performed after deposition of insulating film 254A, the microwave treatment conditions described above should be used.

[0391] Next, a conductive film to become conductor 260a and a conductive film to become conductor 260b are deposited in sequence. The conductive films to become conductor 260a and conductor 260b can be deposited using sputtering, CVD, MBE, PLD, ALD, etc. In this embodiment, a titanium nitride film is deposited as the conductive film to become conductor 260a using the ALD method, and a tungsten film is deposited as the conductive film to become conductor 260b using the CVD method.

[0392] Next, by CMP treatment, insulating films 252A, 250A, 254A, the conductive film that will become conductor 260a, and the conductive film that will become conductor 260b are polished until the insulator 280 is exposed, thereby forming insulators 252, 250, 254, and conductor 260 (conductor 260a and conductor 260b) (see Figures 15A to 15D). As a result, insulator 252 is positioned to cover the opening that reaches oxide 230b. Conductor 260 is also positioned to fill the opening via insulators 252 and 250.

[0393] Next, a heat treatment may be performed under the same conditions as the heat treatment described above. In this embodiment, the treatment is performed in a nitrogen atmosphere at a temperature of 400°C for 1 hour. This heat treatment can reduce the moisture concentration and hydrogen concentration in the insulator 250 and insulator 280. After the heat treatment, the insulator 282 may be deposited continuously without exposure to the atmosphere.

[0394] Next, insulators 282 are formed on insulators 252, 250, 254, 260, and 280 (see Figures 15A to 15D). The insulator 282 can be deposited using sputtering, CVD, MBE, PLD, ALD, etc. It is preferable to deposit the insulator 282 using sputtering. By using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration in the insulator 282 can be reduced.

[0395] In this embodiment, aluminum oxide is deposited as the insulator 282 using a pulsed DC sputtering method with an aluminum target in an atmosphere containing oxygen gas. By using the pulsed DC sputtering method, the film thickness distribution can be made more uniform, and the sputtering rate and film quality can be improved.

[0396] Furthermore, by using the sputtering method to deposit the insulator 282 in an oxygen-containing atmosphere, oxygen can be added to the insulator 280 during film formation. This allows the insulator 280 to contain excess oxygen. In this case, it is preferable to deposit the insulator 282 while heating the substrate.

[0397] Next, an etching mask is formed on the insulator 282 by lithography, and a portion of the insulator 282, a portion of the insulator 280, a portion of the insulator 275, a portion of the insulator 222, and a portion of the insulator 216 are processed until the upper surface of the insulator 214 is exposed (see Figures 16A to 16D). This processing may be done using wet etching, but dry etching is preferable for fine processing.

[0398] Next, a heat treatment may be performed. The heat treatment should be performed at a temperature of 250°C to 650°C, preferably 350°C to 600°C. Furthermore, it is preferable that this heat treatment temperature is lower than the heat treatment temperature performed after the formation of the oxide film 230B. The heat treatment should be performed in an atmosphere of nitrogen gas or an inert gas. By performing this heat treatment, some of the oxygen added to the insulator 280 diffuses into the oxide 230 via the insulator 250, etc.

[0399] Furthermore, by performing the above heat treatment, oxygen contained in insulator 280 and hydrogen combined with that oxygen can be released to the outside from the side surface of insulator 280 formed by the processing of insulators 282, 280, 275, 222, and 216. The hydrogen combined with oxygen is released as water. Therefore, the amount of unwanted oxygen and hydrogen contained in insulator 280 can be reduced.

[0400] Furthermore, an insulator 252 is provided in contact with the upper and side surfaces of the oxide 230 in the region where the oxide 230 overlaps with the conductor 260. Since the insulator 252 has an oxygen barrier property, it can reduce the diffusion of excess oxygen into the oxide 230. This allows oxygen to be supplied in such a way that excess oxygen is not supplied to region 230bc and its vicinity. This suppresses oxidation of the side surfaces of the conductor 242 by excess oxygen, while preventing oxygen deficiencies and V2 formation in region 230bc. O H can be reduced. Therefore, the electrical characteristics of transistor 200 can be improved, and its reliability can be enhanced.

[0401] On the other hand, when transistors 200 are densely integrated, the volume of insulator 280 per transistor 200 may become excessively small. In this case, the amount of oxygen diffused into the oxide 230 during the heat treatment described above becomes significantly smaller. When the oxide 230 is heated while in contact with an oxide insulator that does not contain sufficient oxygen (for example, insulator 250), there is a risk that the oxygen constituting the oxide 230 will be desorbed. However, in the transistor 200 shown in this embodiment, an insulator 252 is provided in contact with the upper and side surfaces of the oxide 230 in the region that overlaps with the conductor 260 of the oxide 230. Since the insulator 252 has barrier properties against oxygen, the desorption of oxygen from the oxide 230 can be reduced even during the heat treatment described above. As a result, oxygen deficiencies and V are formed in region 230bc. O H can be reduced. Therefore, the electrical characteristics of transistor 200 can be improved, and its reliability can be enhanced.

[0402] As described above, in the semiconductor device according to this embodiment, a transistor with good electrical characteristics and good reliability can be formed whether the amount of oxygen supplied from the insulator 280 is high or low. Therefore, a semiconductor device can be provided that suppresses variations in the electrical characteristics of the transistor 200 within the substrate surface.

[0403] Next, an insulator 283 is formed on the insulator 282 (see Figures 17A to 17D). The insulator 283 can be deposited using sputtering, CVD, MBE, PLD, ALD, etc. It is preferable to deposit the insulator 283 using sputtering. By using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration in the insulator 283 can be reduced. The insulator 283 may also be multilayered. For example, silicon nitride may be deposited using sputtering, and then silicon nitride may be deposited on the silicon nitride using the ALD method. By encasing the transistor 200 with the highly barrier insulators 283 and 214, moisture and hydrogen can be prevented from entering from the outside.

[0404] Next, an insulator 274 is formed on the insulator 283. The insulator 274 can be deposited using sputtering, CVD, MBE, PLD, ALD, or the like. In this embodiment, silicon oxide is deposited as the insulator 274 by the CVD method.

[0405] Next, the upper surface of the insulator 274 is flattened by CMP treatment, which involves polishing the insulator 274 until the insulator 283 is exposed (see Figures 17A to 17D). This CMP treatment may remove a portion of the upper surface of the insulator 283.

[0406] Next, an insulator 285 is formed on the insulator 274 and the insulator 283 (see Figures 18A to 18D). The insulator 285 can be deposited using sputtering, CVD, MBE, PLD, ALD, etc. It is preferable to deposit the insulator 285 using sputtering. By using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration in the insulator 285 can be reduced.

[0407] In this embodiment, silicon oxide is deposited as the insulator 285 by sputtering.

[0408] Next, openings reaching the conductor 242 are formed in insulators 271, 275, 280, 282, 283, and 285 (see Figures 18A and 18B). These openings can be formed using lithography. In Figure 18A, the shape of the opening is circular in a top view, but it is not limited to this. For example, the opening may be approximately circular, such as an ellipse, polygonal, such as a quadrilateral, or a polygonal shape with rounded corners in a top view.

[0409] Next, insulating films to form insulators 241a and 241b are deposited, and the insulating films are anisotropically etched to form insulator 241 (see Figure 18B). The insulating films can be deposited using sputtering, CVD, MBE, PLD, ALD, etc. It is preferable to use an insulating film that has the function of suppressing oxygen permeation. For example, it is preferable to deposit an aluminum oxide film using the ALD method, and then deposit a silicon nitride film on top of it using the PEALD method. Silicon nitride is preferred because it has high blocking properties for hydrogen.

[0410] Furthermore, for the anisotropic etching of the insulating films that will become insulators 241a and 241b, a dry etching method, for example, may be used. By providing insulators 241 on the side walls of the opening, the permeation of oxygen from the outside can be suppressed, and oxidation of the conductor 240 that will be formed next can be prevented. In addition, impurities such as water and hydrogen contained in the insulator 280 can be prevented from diffusing into the conductor 240.

[0411] Next, conductive films that will become conductor 240a and conductor 240b are formed. It is desirable that the conductive films have a laminated structure that includes a conductor that has the function of suppressing the permeation of impurities such as water and hydrogen. For example, it can be a laminate of tantalum nitride, titanium nitride, etc., and tungsten, molybdenum, copper, etc. The conductive films can be formed using sputtering, CVD, MBE, PLD, ALD, etc.

[0412] Next, by performing a CMP (Chemical Polishing) treatment, a portion of the conductive film that will become conductors 240a and 240b is removed, exposing the upper surface of the insulator 285. As a result, the conductive film remains only in the openings, making it possible to form conductors 240a and 240b with flat upper surfaces (see Figures 18A to 18D). Note that this CMP treatment may remove a portion of the upper surface of the insulator 285.

[0413] Next, a conductive film to form the conductor 246 is deposited. This conductive film can be deposited using methods such as sputtering, CVD, MBE, PLD, or ALD.

[0414] Next, a conductive film to become the conductor 246 is processed by lithography to form a conductor 246a that contacts the upper surface of the conductor 240a, and a conductor 246b that contacts the upper surface of the conductor 240b. At this time, a portion of the insulator 285 in the region where the conductors 246a and 246b do not overlap with the insulator 285 may be removed.

[0415] Based on the above, a semiconductor device having the transistor 200 shown in Figures 6A to 6D can be fabricated. As shown in Figures 9A to 18D, the transistor 200 can be fabricated using the semiconductor device fabrication method shown in this embodiment.

[0416] <Modified examples of semiconductor devices> In the following section, an example of a semiconductor device according to one aspect of the present invention will be described using Figures 19A to 21D.

[0417] In each figure, A shows a top view of the semiconductor device. B in each figure is a cross-sectional view corresponding to the area indicated by the dashed line A1-A2 in figure A. C in each figure is a cross-sectional view corresponding to the area indicated by the dashed line A3-A4 in figure A. D in each figure is a cross-sectional view corresponding to the area indicated by the dashed line A5-A6 in figure A. In the top view of figure A, some elements have been omitted for clarity.

[0418] In the semiconductor devices shown in Figures A through D, the same reference numerals are used to denote structures that have the same function as those shown in <Examples of Semiconductor Device Configurations>. Furthermore, in this section as well, the materials used for the semiconductor devices are those described in detail in <Examples of Semiconductor Device Configurations>.

[0419] <Example 1 of a semiconductor device> The semiconductor devices shown in Figures 19A to 19D are modified versions of the semiconductor devices shown in Figures 6A to 6D. The semiconductor devices shown in Figures 19A to 19D differ from those shown in Figures 6A to 6D in that they do not have an insulator 282. Therefore, in the semiconductor devices shown in Figures 19A to 19D, the insulator 283 is in contact with the upper surface of the conductor 260, the upper surface of the insulator 280, the uppermost part of the insulator 254, the uppermost part of the insulator 250, and the uppermost part of the insulator 252.

[0420] For example, if sufficient oxygen can be supplied to the oxide 230 by microwave processing as shown in Figures 13A to 13D, the region 230bc can be substantially made i-type without providing an insulator 282 and adding oxygen to the insulator 280. In such cases, as shown in Figures 19A to 19D, by using a configuration without an insulator 282, the manufacturing process of the semiconductor device can be simplified and productivity can be improved.

[0421] <Modified example of a semiconductor device 2> The semiconductor devices shown in Figures 20A to 20D are modified examples of the semiconductor devices shown in Figures 6A to 6D. The semiconductor devices shown in Figures 20A to 20D differ from those shown in Figures 6A to 6D in that oxide 243a and oxide 243b are provided. Oxide 243a is provided between oxide 230b and conductor 242a, and oxide 243b is provided between oxide 230b and conductor 242b. Here, it is preferable that oxide 243a is in contact with the upper surface of oxide 230b and the lower surface of conductor 242a. It is also preferable that oxide 243b is in contact with the upper surface of oxide 230b and the lower surface of conductor 242b.

[0422] It is preferable that oxides 243a and 243b have the function of suppressing oxygen permeation. Placing oxide 243a (oxide 243b), which has the function of suppressing oxygen permeation, between the conductor 242a (conductor 242b), which functions as a source electrode or drain electrode, and oxide 230b is preferable because it reduces the electrical resistance between the conductor 242a (conductor 242b) and oxide 230b. With such a configuration, it may be possible to improve the electrical characteristics, field effect mobility, and reliability of the transistor 200.

[0423] Furthermore, metal oxides containing element M may be used as oxides 243a and 243b. In particular, element M may be aluminum, gallium, yttrium, or tin. It is also preferable that oxides 243a and 243b have a higher concentration of element M than oxides 230b. Gallium oxide may also be used as oxides 243a and 243b. Furthermore, metal oxides such as In-M-Zn oxide may be used as oxides 243a and 243b. Specifically, it is preferable that the atomic ratio of element M to In in the metal oxide used for oxides 243a and 243b is greater than the atomic ratio of element M to In in the metal oxide used for oxide 230b. The film thickness of oxides 243a and 243b is preferably 0.5 nm to 5 nm, more preferably 1 nm to 3 nm, and even more preferably 1 nm to 2 nm. It is also preferable that oxides 243a and 243b are crystalline. When oxides 243a and 243b are crystalline, the release of oxygen from oxide 230 can be effectively suppressed. For example, if oxides 243a and 243b have a crystalline structure such as a hexagonal crystal, the release of oxygen from oxide 230 can be suppressed.

[0424] <Modified example of semiconductor device 3> The semiconductor device shown in Figures 21A to 21D is a modified version of the semiconductor device shown in Figures 6A to 6D. The semiconductor device shown in Figures 21A to 21D differs from the semiconductor device shown in Figures 6A to 6D in that the insulator 283 is in contact with a part of the upper surface of the insulator 212. Therefore, the transistor 200 is placed within the region sealed by the insulator 283 and the insulator 212. This configuration makes it possible to suppress the ingress of hydrogen contained outside the sealed region into the sealed region. Furthermore, although the transistor 200 shown in Figures 21A to 21D shows a configuration in which the insulator 212 and the insulator 283 are provided as single layers, the present invention is not limited to this. For example, the insulator 212 and the insulator 283 may each be provided as a stacked structure of two or more layers.

[0425] <Examples of semiconductor device applications> In the following section, an example of a semiconductor device according to one aspect of the present invention will be described using Figure 22.

[0426] Figure 22A shows a top view of the semiconductor device 500. The x-axis in Figure 22A is taken parallel to the channel length direction of the transistor 200, and the y-axis is taken perpendicular to the x-axis. Figure 22B is a cross-sectional view corresponding to the area indicated by the dashed line A1-A2 in Figure 22A, and is also a cross-sectional view of the transistor 200 in the channel length direction. Figure 22C is a cross-sectional view corresponding to the area indicated by the dashed line A3-A4 in Figure 22A, and is also a cross-sectional view of the aperture region 400 and its vicinity. Note that some elements have been omitted from the top view of Figure 22A for clarity.

[0427] In the semiconductor devices shown in Figures 22A to 22C, structures having the same function as those constituting the semiconductor device shown in <Example of Semiconductor Device Configuration> are denoted by the same reference numerals. Furthermore, in this section as well, the materials used for the semiconductor device components are those described in detail in <Example of Semiconductor Device Configuration>.

[0428] The semiconductor device 500 shown in Figures 22A to 22C is a modified example of the semiconductor device shown in Figures 6A to 6D. The semiconductor device 500 shown in Figures 22A to 22C differs from the semiconductor device shown in Figures 6A to 6D in that an opening region 400 is formed in the insulator 282 and the insulator 280. It also differs from the semiconductor device shown in Figures 6A to 6D in that a sealing portion 265 is formed to surround the plurality of transistors 200.

[0429] The semiconductor device 500 has a plurality of transistors 200 and a plurality of aperture regions 400 arranged in a matrix. A plurality of conductors 260, which function as gate electrodes for the transistors 200, are provided extending in the y-axis direction. The aperture regions 400 are formed in areas that do not overlap with the oxide 230 and the conductors 260. Furthermore, a sealing portion 265 is formed to surround the plurality of transistors 200, the plurality of conductors 260, and the plurality of aperture regions 400. Note that the number, arrangement, and size of the transistors 200, conductors 260, and aperture regions 400 are not limited to the structure shown in Figure 22A, but can be appropriately set according to the design of the semiconductor device 500.

[0430] As shown in Figures 22B and 22C, the sealing portion 265 is provided so as to surround the multiple transistors 200, insulators 216, 222, 275, 280, and 282. In other words, insulator 283 is provided so as to cover insulators 216, 222, 275, 280, and 282. In the sealing portion 265, insulator 283 is in contact with the upper surface of insulator 214. Also in the sealing portion 265, insulator 274 is provided between insulator 283 and insulator 285. The upper surface of insulator 274 is approximately the same height as the uppermost surface of insulator 283. Furthermore, the same type of insulator as insulator 280 can be used for insulator 274.

[0431] This structure allows multiple transistors 200 to be enclosed by insulators 283, 214, and 212. Here, it is preferable that one or more of insulators 283, 214, and 212 function as a barrier insulating film against hydrogen. This prevents hydrogen contained outside the sealing portion 265 from entering the sealing portion 265.

[0432] As shown in Figure 22C, the insulator 282 has an opening in the opening region 400. In addition, the insulator 280 may have a groove that overlaps the opening of the insulator 282 in the opening region 400. The depth of the groove in the insulator 280 should not be too deep, except to expose the upper surface of the insulator 275, for example, it should be about 1 / 4 to 1 / 2 of the maximum film thickness of the insulator 280.

[0433] Furthermore, as shown in Figure 22C, the insulator 283 is in contact with the side surface of the insulator 282, the side surface of the insulator 280, and the upper surface of the insulator 280 inside the opening region 400. In addition, a portion of the insulator 274 may be formed within the opening region 400 to fill in the recess formed in the insulator 283. In this case, the height of the upper surface of the insulator 274 formed within the opening region 400 and the uppermost surface of the insulator 283 may be approximately the same.

[0434] With such an opening region 400 formed and the insulator 280 exposed through the opening in the insulator 282, heat treatment can be performed to supply oxygen to the oxide 230 while diffusing some of the oxygen contained in the insulator 280 outward from the opening region 400. This ensures that sufficient oxygen is supplied from the insulator 280 containing oxygen that is released by heating to the region in the oxide semiconductor layer that functions as a channel-forming region and its vicinity, while preventing the supply of an excessive amount of oxygen.

[0435] At this time, the hydrogen contained in the insulator 280 can combine with oxygen and be released to the outside through the opening region 400. The hydrogen combined with oxygen is released as water. Therefore, the amount of hydrogen contained in the insulator 280 can be reduced, and the mixing of hydrogen contained in the insulator 280 into the oxide 230 can be reduced.

[0436] Furthermore, although the shape of the aperture region 400 in a top view in Figure 22A is approximately rectangular, the present invention is not limited to this. For example, the shape of the aperture region 400 in a top view may be rectangular, elliptical, circular, rhombus, or a combination thereof. Also, the area and spacing of the aperture region 400 can be appropriately set according to the design of the semiconductor device including the transistors 200. For example, in areas where the density of transistors 200 is low, the area of ​​the aperture region 400 can be increased or the spacing of the aperture region 400 can be decreased. Also, for example, in areas where the density of transistors 200 is high, the area of ​​the aperture region 400 can be decreased or the spacing of the aperture region 400 can be increased.

[0437] According to one aspect of the present invention, a semiconductor device with less variation in transistor characteristics and a method for manufacturing the same can be provided. Furthermore, according to one aspect of the present invention, a semiconductor device having good electrical characteristics and a method for manufacturing the same can be provided. Furthermore, according to one aspect of the present invention, a semiconductor device with good reliability and a method for manufacturing the same can be provided. Furthermore, according to one aspect of the present invention, a semiconductor device with high on-current and a method for manufacturing the same can be provided. Furthermore, according to one aspect of the present invention, a semiconductor device with high field-effect mobility and a method for manufacturing the same can be provided. Furthermore, according to one aspect of the present invention, a semiconductor device that can be miniaturized or highly integrated and a method for manufacturing the same can be provided. Furthermore, according to one aspect of the present invention, a semiconductor device with low power consumption and a method for manufacturing the same can be provided.

[0438] The configurations and methods described in this embodiment can be implemented by appropriately combining at least a part thereof with other embodiments and examples described herein.

[0439] (Embodiment 3) In this embodiment, one form of a semiconductor device will be described using Figures 23 to 27.

[0440] [Storage device 1] Figure 23 shows an example of a semiconductor device (memory device) according to one aspect of the present invention. In the semiconductor device according to one aspect of the present invention, transistor 200 is provided above transistor 300, and capacitive element 100 is provided above transistor 300 and transistor 200. Note that the transistor 200 can be the same transistor 200 described in the previous embodiment.

[0441] Transistor 200 is a transistor in which a channel is formed in a semiconductor layer having an oxide semiconductor. Because transistor 200 has a small off-current, it can be used in a memory device to retain stored data for a long period of time. In other words, because refresh operations are not required, or are performed very infrequently, the power consumption of the memory device can be significantly reduced.

[0442] In the semiconductor device shown in Figure 23, wire 1001 is electrically connected to the source of transistor 300, and wire 1002 is electrically connected to the drain of transistor 300. Wire 1003 is electrically connected to one of the source and drain of transistor 200, wire 1004 is electrically connected to the first gate of transistor 200, and wire 1006 is electrically connected to the second gate of transistor 200. The gate of transistor 300 and the other of the source and drain of transistor 200 are electrically connected to one of the electrodes of capacitive element 100, and wire 1005 is electrically connected to the other electrode of capacitive element 100.

[0443] Furthermore, the memory devices shown in Figure 23 can be arranged in a matrix to form a memory cell array.

[0444] <Transistor 300> The transistor 300 is provided on a substrate 311 and has a conductor 316 that functions as a gate, an insulator 315 that functions as a gate insulator, a semiconductor region 313 that is part of the substrate 311, and low-resistance regions 314a and 314b that function as a source region or drain region. The transistor 300 may be either a p-channel type or an n-channel type.

[0445] In Figure 23, the transistor 300 has a convex shape in the semiconductor region 313 (part of the substrate 311) where the channel is formed. Furthermore, the sides and top surface of the semiconductor region 313 are covered by a conductor 316 via an insulator 315. The conductor 316 may be made of a material that adjusts the work function. Such a transistor 300 is also called a FIN-type transistor because it utilizes the convex portion of the semiconductor substrate. It may also have an insulator in contact with the top of the convex portion, functioning as a mask for forming the convex portion. While this example shows the formation of the convex portion by processing a part of the semiconductor substrate, a semiconductor film with a convex shape may also be formed by processing an SOI substrate.

[0446] Note that the transistor 300 shown in Figure 23 is just one example, and the structure is not limited to this; any appropriate transistor can be used depending on the circuit configuration or driving method.

[0447] <Capacitive element 100> The capacitive element 100 is provided above the transistor 200. The capacitive element 100 has a conductor 110 that functions as a first electrode, a conductor 120 that functions as a second electrode, and an insulator 130 that functions as a dielectric. Here, it is preferable to use an insulator 130 that can be used as the insulator 283 shown in the above embodiment.

[0448] Furthermore, for example, the conductor 112 provided on the conductor 240 and the conductor 110 can be formed simultaneously. The conductor 112 functions as a plug or wiring that electrically connects to the capacitive element 100, the transistor 200, or the transistor 300.

[0449] In Figure 23, the conductors 112 and 110 are shown as single-layer structures, but the configuration is not limited to this, and a laminated structure of two or more layers is also possible. For example, a conductor with high adhesion to both the barrier conductor and the highly conductive conductor may be formed between the barrier conductor and the highly conductive conductor.

[0450] Furthermore, the insulator 130 may be made of, for example, silicon oxide, silicon oxide nitride, silicon nitride, silicon oxide, aluminum oxide, aluminum oxide nitride, aluminum nitride, hafnium oxide, hafnium oxide nitride, hafnium oxide nitride, hafnium nitride, etc., and can be provided in a laminated or single layer.

[0451] For example, it is preferable to use a laminated structure of a material with high dielectric strength, such as silicon oxidnitride, and a high dielectric constant (high-k) material for the insulator 130. With this configuration, the capacitive element 100 can secure sufficient capacitance by having a high dielectric constant (high-k) insulator, and the dielectric strength is improved by having an insulator with high dielectric strength, thereby suppressing electrostatic discharge breakdown of the capacitive element 100.

[0452] Examples of high-dielectric constant (high-k) materials (materials with a high relative permittivity) that serve as insulators include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxidized nitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxidized nitrides containing silicon and hafnium, or nitrides containing silicon and hafnium.

[0453] On the other hand, materials with high dielectric strength (materials with low dielectric constant) include silicon oxide, silicon oxide nitride, silicon oxide nitride, silicon nitride, fluorine-added silicon oxide, carbon-added silicon oxide, carbon and nitrogen-added silicon oxide, and porous silicon oxide or resins.

[0454] <Wiring layer> A wiring layer containing interlayer films, wiring, and plugs may be provided between each structure. Furthermore, multiple wiring layers may be provided depending on the design. Here, a conductor functioning as a plug or wiring may be grouped together and assigned the same reference numeral. Also, in this specification, the wiring and the plug that electrically connects to the wiring may be an integrated unit. That is, a part of the conductor may function as wiring, and a part of the conductor may function as a plug.

[0455] For example, on the transistor 300, insulators 320, 322, 324, and 326 are sequentially stacked as interlayer films. Insulators 320, 322, 324, and 326 also have embedded conductive elements such as conductors 328 and 330 that are electrically connected to the capacitive element 100 or the transistor 200. Conductors 328 and 330 function as plugs or wiring.

[0456] Furthermore, the insulator functioning as an interlayer film may also function as a planarizing film that covers the uneven shape beneath it. For example, the upper surface of the insulator 322 may be planarized by a planarizing treatment such as chemical mechanical polishing (CMP) to improve its flatness.

[0457] A wiring layer may be provided on the insulator 326 and the conductor 330. For example, in Figure 23, insulators 350, 352, and 354 are stacked in order. Conductors 356 are formed on insulators 350, 352, and 354. The conductor 356 functions as a plug or wiring.

[0458] Similarly, insulators 210, 212, 214, and 216 have conductors 218 and conductors (conductors 205) that constitute the transistor 200 embedded in them. Conductors 218 function as plugs or wires that electrically connect to the capacitive element 100 or the transistor 300. Furthermore, insulators 150 are provided on conductors 120 and insulator 130.

[0459] Here, similar to the insulator 241 shown in the above embodiment, an insulator 217 is provided in contact with the side surface of the conductor 218, which functions as a plug. The insulator 217 is provided in contact with the inner wall of the opening formed in the insulators 210, 212, 214, and 216. In other words, the insulator 217 is provided between the conductor 218 and the insulators 210, 212, 214, and 216. Note that since the conductor 205 can be formed in parallel with the conductor 218, the insulator 217 may also be formed in contact with the side surface of the conductor 205.

[0460] As the insulator 217, for example, an insulator such as silicon nitride, aluminum oxide, or silicon nitride oxide may be used. Since the insulator 217 is provided in contact with insulators 210, 212, 214, and 222, it is possible to suppress the mixing of impurities such as water or hydrogen from insulators 210 or 216 into the oxide 230 through the conductor 218. Silicon nitride is particularly suitable because of its high blocking properties for hydrogen. In addition, it is possible to prevent oxygen contained in insulators 210 or 216 from being absorbed by the conductor 218.

[0461] The insulator 217 can be formed in the same manner as the insulator 241. For example, silicon nitride can be deposited using the PEALD method, and an opening reaching the conductor 356 can be formed using anisotropic etching.

[0462] Insulators that can be used as interlayer films include insulating oxides, nitrides, oxidized nitrides, nitride oxides, metal oxides, metal oxidized nitrides, and metal nitride oxides.

[0463] For example, by using a material with a low dielectric constant for the insulator that functions as an interlayer film, parasitic capacitance between wiring can be reduced. Therefore, it is best to select the material according to the function of the insulator.

[0464] For example, it is preferable that insulators 150, 210, 352, and 354 have an insulator with a low dielectric constant. For example, it is preferable that the insulator has fluorine-added silicon oxide, carbon-added silicon oxide, carbon and nitrogen-added silicon oxide, porous silicon oxide, or a resin. Alternatively, it is preferable that the insulator has a laminated structure of silicon oxide, silicon oxynitride, silicon nitride, silicon nitride, fluorine-added silicon oxide, carbon-added silicon oxide, carbon and nitrogen-added silicon oxide, or porous silicon oxide, and a resin. Since silicon oxide and silicon oxynitride are thermally stable, combining them with a resin can create a thermally stable laminated structure with a low dielectric constant. Examples of resins include polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, or acrylic.

[0465] Furthermore, the electrical characteristics of a transistor using an oxide semiconductor can be stabilized by surrounding it with an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen. Therefore, insulators 214, 212, and 350 should be insulators that have the function of suppressing the permeation of impurities such as hydrogen and oxygen.

[0466] As an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen, for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum may be used in a single layer or in a multilayer structure. Specifically, as an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide, silicon nitride or silicon nitride, etc., can be used.

[0467] Conductors that can be used for wiring and plugs may include materials containing one or more metallic elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, etc. Alternatively, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements like phosphorus, or silicides such as nickel silicide may be used.

[0468] For example, conductive materials such as metal materials, alloy materials, metal nitride materials, or metal oxide materials formed from the above materials can be used as conductors 328, 330, 356, 218, and 112, either in a single layer or in a laminated form. It is preferable to use high-melting-point materials such as tungsten or molybdenum that provide both heat resistance and conductivity, with tungsten being preferable. Alternatively, it is preferable to form them from low-resistance conductive materials such as aluminum or copper. Using low-resistance conductive materials can reduce wiring resistance.

[0469] <Wiring or plugs in layers containing oxide semiconductors> Furthermore, when an oxide semiconductor is used in the transistor 200, an insulator having an excess oxygen region may be provided near the oxide semiconductor. In that case, it is preferable to provide a barrier insulator between the insulator having the excess oxygen region and the conductor provided on the insulator having the excess oxygen region.

[0470] For example, in Figure 23, an insulator 241 may be provided between the insulators 224 and 280, which have excess oxygen, and the conductor 240. By providing the insulator 241 in contact with the insulators 222, 282, and 283, the insulator 224 and the transistor 200 can be sealed by the barrier insulator.

[0471] In other words, by providing the insulator 241, it is possible to suppress the absorption of excess oxygen present in the insulators 224 and 280 into the conductor 240. Furthermore, by having the insulator 241, it is possible to suppress the diffusion of hydrogen, which is an impurity, into the transistor 200 via the conductor 240.

[0472] Furthermore, as the insulator 241, an insulating material having the function of suppressing the diffusion of impurities such as water or hydrogen, and oxygen, is preferable. For example, silicon nitride, silicon oxide nitride, aluminum oxide, or hafnium oxide are preferred. Silicon nitride is particularly preferred because of its high blocking properties for hydrogen. In addition, other materials such as metal oxides such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, or tantalum oxide can also be used.

[0473] Furthermore, as shown in the above embodiment, the transistor 200 may be configured to be sealed with insulators 212, 214, 282, and 283. This configuration reduces the amount of hydrogen contained in insulators 274, 150, etc., that mixes into insulator 280, etc.

[0474] Here, the conductor 240 penetrates insulators 283 and 282, and the conductor 218 penetrates insulators 214 and 212. However, as described above, insulator 241 is provided in contact with conductor 240, and insulator 217 is provided in contact with conductor 218. This reduces the amount of hydrogen that enters the inside of insulators 212, 214, 282, and 283 via conductors 240 and 218. In this way, the transistor 200 is sealed with insulators 212, 214, 282, 283, 241, and 217, reducing the amount of impurities such as hydrogen contained in insulator 274, etc., that enter from the outside.

[0475] <Dicing line> The following describes dicing lines (sometimes called scribe lines, division lines, or cutting lines) that are provided when extracting multiple semiconductor devices as chips by dividing a large-area substrate into individual semiconductor elements. One method of division is to first form grooves (dicing lines) in the substrate to divide the semiconductor elements, and then cut along the dicing lines to divide (divide) the substrate into multiple semiconductor devices.

[0476] Here, for example, as shown in Figure 23, it is preferable to design the region where insulator 283 and insulator 214 are in contact to overlap with the dicing line. In other words, openings are provided in insulators 282, 280, 275, 224, 222, and 216 near the region that will become the dicing line provided on the outer edge of the memory cell having multiple transistors 200.

[0477] In other words, in the openings provided in insulators 282, 280, 275, 224, 222, and 216, insulator 214 and insulator 283 are in contact.

[0478] Furthermore, for example, openings may be provided in insulators 282, 280, 275, 224, 222, 216, and 214. With this configuration, insulator 212 and insulator 283 come into contact at the openings provided in insulators 282, 280, 275, 224, 222, 216, and 214. In this case, insulators 212 and 283 may be formed using the same material and method. By forming insulators 212 and 283 using the same material and method, adhesion can be improved. For example, silicon nitride is preferable.

[0479] This structure allows the transistor 200 to be enclosed by insulators 212, 214, 282, and 283. Since at least one of insulators 212, 214, 282, and 283 has the function of suppressing the diffusion of oxygen, hydrogen, and water, even if the substrate is divided into multiple chips for each circuit region on which the semiconductor element shown in this embodiment is formed, it is possible to prevent impurities such as hydrogen or water from entering from the side of the divided substrate and diffusing into the transistor 200.

[0480] Furthermore, this structure prevents excess oxygen from insulators 280 and 224 from diffusing to the outside. Therefore, excess oxygen from insulators 280 and 224 is efficiently supplied to the oxide in which the channel in transistor 200 is formed. This oxygen reduces oxygen deficiencies in the oxide in which the channel in transistor 200 is formed. As a result, the oxide in which the channel in transistor 200 is formed can be made into an oxide semiconductor with a low defect level density and stable properties. In other words, fluctuations in the electrical properties of transistor 200 can be suppressed and reliability can be improved.

[0481] In the memory device shown in Figure 23, the capacitive element 100 is of the planar type, but the memory device shown in this embodiment is not limited to this. For example, as shown in Figure 24, the capacitive element 100 may be of the cylindrical type. In the memory device shown in Figure 24, the configuration below the insulator 150 is the same as that of the semiconductor device shown in Figure 23.

[0482] The capacitive element 100 shown in Figure 24 includes an insulator 150 on an insulator 130, an insulator 142 on an insulator 150, a conductor 115 disposed in an opening formed in the insulators 150 and 142, an insulator 145 on the conductor 115 and 142, a conductor 125 on the insulator 145, and an insulator 152 on the conductor 125 and 145. Here, at least a portion of the conductor 115, the insulator 145, and the conductor 125 are disposed in the opening formed in the insulators 150 and 142.

[0483] The conductor 115 functions as the lower electrode of the capacitive element 100, the conductor 125 functions as the upper electrode of the capacitive element 100, and the insulator 145 functions as the dielectric of the capacitive element 100. In the openings of the insulators 150 and 142, the upper and lower electrodes of the capacitive element 100 are configured to face each other with the dielectric in between, not only on the bottom surface but also on the sides, allowing for a large capacitance per unit area. Therefore, the deeper the opening, the larger the capacitance of the capacitive element 100 can be. By increasing the capacitance per unit area of ​​the capacitive element 100 in this way, miniaturization or high integration of semiconductor devices can be promoted.

[0484] The insulator 152 may be any insulator that can be used for the insulator 280. Furthermore, the insulator 142 preferably functions as an etching stopper when forming the opening in the insulator 150, and may be any insulator that can be used for the insulator 214.

[0485] The shape of the openings formed in the insulators 150 and 142 when viewed from above may be a rectangle, a polygon other than a rectangle, a polygon with curved corners, or a circle including an ellipse. In this case, it is preferable that the area overlapping between the opening and the transistor 200 is large when viewed from above. By adopting such a configuration, the occupied area of ​​the semiconductor device having the capacitive element 100 and the transistor 200 can be reduced.

[0486] The conductor 115 is positioned in contact with the openings formed in the insulators 142 and 150. Preferably, the upper surface of the conductor 115 substantially coincides with the upper surface of the insulator 142. The lower surface of the conductor 115 is in contact with the conductor 110 through the opening in the insulator 130. The conductor 115 is preferably formed using an ALD method or a CVD method; for example, any conductor suitable for the conductor 205 may be used.

[0487] The insulator 145 is arranged to cover the conductor 115 and the insulator 142. For example, it is preferable to deposit the insulator 145 using the ALD method or the CVD method. The insulator 145 can be made of, for example, silicon oxide, silicon oxide nitride, silicon nitride, silicon, zirconium oxide, aluminum oxide, aluminum oxide nitride, aluminum oxide nitride, aluminum nitride, hafnium oxide, hafnium oxide nitride, hafnium nitride, hafnium oxide, hafnium nitride, etc., and can be provided in a laminated or single layer. For example, as the insulator 145, an insulating film laminated in the order of zirconium oxide, aluminum oxide, and zirconium oxide can be used.

[0488] Furthermore, it is preferable to use a material with high dielectric strength, such as silicon oxidative nitride, or a high dielectric constant (high-k) material for the insulator 145. Alternatively, a laminated structure of a material with high dielectric strength and a high dielectric constant (high-k) material may be used.

[0489] Examples of high-dielectric constant (high-k) materials (materials with a high relative permittivity) used as insulators include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxidized nitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxidized nitrides containing silicon and hafnium, and nitrides containing silicon and hafnium. By using such high-k materials, the capacitance of the capacitive element 100 can be sufficiently secured even if the insulator 145 is made thicker. By making the insulator 145 thicker, the leakage current generated between the conductor 115 and the conductor 125 can be suppressed.

[0490] On the other hand, materials with high dielectric strength include silicon oxide, silicon oxide nitride, silicon oxide nitride, silicon nitride, fluorine-added silicon oxide, carbon-added silicon oxide, carbon and nitrogen-added silicon oxide, porous silicon oxide, and resins. For example, silicon nitride (SiN) deposited using the PEALD method. x ), silicon oxide (SiO2) deposited using the PEALD method x ), silicon nitride (SiN) deposited using the PEALD method x An insulating film can be used that is laminated in the order of zirconium oxide, silicon oxide deposited by the ALD method, and zirconium oxide. Alternatively, an insulating film can be used that is laminated in the order of zirconium oxide, silicon oxide deposited by the ALD method, and zirconium oxide. By using such an insulator with high dielectric strength, the dielectric strength is improved and electrostatic discharge breakdown of the capacitive element 100 can be suppressed.

[0491] The conductor 125 is positioned to fill the openings formed in the insulators 142 and 150. The conductor 125 is also electrically connected to the wiring 1005 via the conductors 140 and 153. The conductor 125 is preferably formed using the ALD method or CVD method, and for example, any conductor that can be used for the conductor 205 may be used.

[0492] Furthermore, the conductor 153 is provided on the insulator 154 and covered by the insulator 156. The conductor 153 may be any conductor that can be used for the conductor 112, and the insulator 156 may be any insulator that can be used for the insulator 152. Here, the conductor 153 is in contact with the upper surface of the conductor 140 and functions as a terminal of the capacitive element 100, the transistor 200, or the transistor 300.

[0493] [Storage device 2] An example of a semiconductor device (memory device) according to one aspect of the present invention is shown in Figure 25.

[0494] <Example of memory device configuration> Figure 25 is a cross-sectional view of a semiconductor device having a memory device 290. The memory device 290 shown in Figure 25 has a capacitive device 292 in addition to the transistors 200 shown in Figures 6A to 6D. Figure 25 corresponds to a cross-sectional view of the transistor 200 in the channel length direction.

[0495] The capacitive device 292 comprises a conductor 242b, an insulator 271b provided on the conductor 242b, an insulator 275 provided in contact with the upper surface of the insulator 271b, the side surface of the insulator 271b, and the side surface of the conductor 242b, and a conductor 294 on the insulator 275. In other words, the capacitive device 292 constitutes a MIM (Metal-Insulator-Metal) capacitor. One of the pair of electrodes of the capacitive device 292, i.e., the conductor 242b, can also serve as the source electrode of the transistor. Furthermore, the dielectric layer of the capacitive device 292 can also serve as the protective layer provided on the transistor, i.e., the insulator 271 and the insulator 275. Therefore, since part of the transistor manufacturing process can be shared in the manufacturing process of the capacitive device 292, a highly productive semiconductor device can be produced. Furthermore, since one of the pair of electrodes of the capacitive device 292, namely the conductor 242b, also serves as the source electrode of the transistor, it is possible to reduce the area required for the placement of the transistor and the capacitive device.

[0496] For example, the conductor 294 can be any material that can be used for the conductor 242.

[0497] <Examples of memory devices> In the following, using Figures 26A, 26B, and 27, an example of a semiconductor device having a transistor 200 and a capacitive device 292 according to one aspect of the present invention, different from that shown in the previous <Example of Memory Device Configuration>, will be described. In the semiconductor device shown in Figures 26A, 26B, and 27, structures having the same function as those constituting the semiconductor device shown in the previous embodiment and <Example of Memory Device Configuration> (see Figure 25) will be denoted by the same reference numerals. In this section, the materials used for the transistor 200 and the capacitive device 292 are those described in detail in the previous embodiment and <Example of Memory Device Configuration>. Also, in Figures 26A, 26B, and 27, the memory device shown in Figure 25 is used as the memory device, but the invention is not limited to this.

[0498] <<Differential Example of Memory Device 1>> In the following, an example of a semiconductor device 600 having transistors 200a, 200b, capacitive device 292a, and capacitive device 292b according to one aspect of the present invention will be described with reference to Figure 26A.

[0499] Figure 26A is a cross-sectional view in the channel length direction of a semiconductor device 600 having transistors 200a, 200b, capacitive devices 292a, and 292b. Here, the capacitive device 292a has a conductor 242a, an insulator 271a on the conductor 242a, an insulator 275 in contact with the upper surface of the insulator 271a, the side surface of the insulator 271a, and the side surface of the conductor 242a, and a conductor 294a on the insulator 275. The capacitive device 292b has a conductor 242b, an insulator 271b on the conductor 242b, an insulator 275 in contact with the upper surface of the insulator 271b, the side surface of the insulator 271b, and the side surface of the conductor 242b, and a conductor 294b on the insulator 275.

[0500] As shown in Figure 26A, the semiconductor device 600 has a symmetrical configuration with respect to the dashed line A3-A4 as the axis of symmetry. One of the source or drain electrodes of transistor 200a and the other of the source or drain electrode of transistor 200b are combined by the conductor 242c. An insulator 271c is provided on the conductor 242c. In addition, the conductor 246, which functions as wiring, and the conductor 240, which functions as a plug, are combined to connect transistors 200a and 200b. In this way, by using the above configuration for the connections between the two transistors, two capacitive devices, wiring and plugs, it is possible to provide a semiconductor device that can be miniaturized or highly integrated.

[0501] The configurations and effects of transistors 200a, 200b, capacitive device 292a, and 292b can be seen in the example semiconductor device configuration shown in Figure 26A.

[0502] <<Modified Memory Device 2>> In the above, transistors 200a, 200b, capacitive device 292a, and 292b were given as examples of semiconductor device configurations, but the semiconductor device shown in this embodiment is not limited to these. For example, as shown in Figure 26B, a semiconductor device 600 and a semiconductor device having a similar configuration to semiconductor device 600 may be connected via a capacitive section. In this specification, a semiconductor device having transistors 200a, 200b, capacitive device 292a, and 292b is referred to as a cell. The configurations of transistors 200a, 200b, capacitive device 292a, and 292b can be considered in the above-mentioned descriptions relating to transistors 200a, 200b, capacitive device 292a, and 292b.

[0503] Figure 26B is a cross-sectional view showing a semiconductor device 600 having transistors 200a and 200b, a capacitive device 292a, and a capacitive device 292b, and a cell having a similar configuration to the semiconductor device 600, connected via a capacitive section.

[0504] As shown in Figure 26B, the conductor 294b, which functions as one electrode of the capacitive device 292b of semiconductor device 600, also serves as one electrode of the capacitive device of semiconductor device 601, which has a similar configuration to semiconductor device 600. Although not shown, the conductor 294a, which functions as one electrode of the capacitive device 292a of semiconductor device 600, also serves as one electrode of the capacitive device of the semiconductor device adjacent to the left side of semiconductor device 600, i.e., in the A1 direction in Figure 26B. The same configuration applies to the cells on the right side of semiconductor device 601, i.e., in the A2 direction in Figure 26B. In other words, a cell array (also called a memory device layer) can be formed. By using such a cell array configuration, the spacing between adjacent cells can be reduced, thereby reducing the projected area of ​​the cell array and enabling high integration. Furthermore, by arranging the cell array configuration shown in Figure 26B in a matrix, a matrix-shaped cell array can be formed.

[0505] As described above, by forming transistors 200a, 200b, capacitive devices 292a, and 292b with the configuration shown in this embodiment, the cell area can be reduced, and the semiconductor device having a cell array can be miniaturized or highly integrated.

[0506] Furthermore, the cell array may be configured not only in a planar manner but also in a stacked manner. Figure 27 shows a cross-sectional view of a configuration in which n layers of cell array 610 are stacked. As shown in Figure 27, by stacking multiple cell arrays (cell array 610_1 to cell array 610_n), cells can be accumulated and arranged without increasing the occupied area of ​​the cell array. In other words, a 3D cell array can be constructed.

[0507] The configurations and methods described in this embodiment can be implemented by appropriately combining at least a part thereof with other embodiments and examples described herein.

[0508] (Embodiment 4) In this embodiment, a transistor using an oxide as a semiconductor (hereinafter sometimes referred to as an OS transistor) and a memory device to which a capacitive element is applied (hereinafter sometimes referred to as an OS memory device) according to one aspect of the present invention will be described with reference to Figures 28A, 28B and 29A to 29H. The OS memory device is a memory device having at least a capacitive element and an OS transistor that controls the charging and discharging of the capacitive element. Because the off-current of the OS transistor is extremely small, the OS memory device has excellent retention characteristics and can function as a non-volatile memory.

[0509] <Example of a storage device configuration> Figure 28A shows an example of the configuration of an OS memory device. The storage device 1400 has peripheral circuits 1411 and a memory cell array 1470. The peripheral circuits 1411 have row circuits 1420, column circuits 1430, output circuits 1440, and control logic circuits 1460.

[0510] The column circuit 1430 includes, for example, a column decoder, a precharge circuit, a sense amplifier, a write circuit, etc. The precharge circuit has the function of precharging the wiring. The sense amplifier has the function of amplifying the data signal read from the memory cell. The above wiring is connected to the memory cells of the memory cell array 1470, and will be described in more detail later. The amplified data signal is output to the outside of the storage device 1400 as the data signal RDATA via the output circuit 1440. The row circuit 1420 includes, for example, a row decoder, a word line driver circuit, etc., and can select the row to access.

[0511] The memory device 1400 is supplied with a low power supply voltage (VSS), a high power supply voltage (VDD) for the peripheral circuit 1411, and a high power supply voltage (VIL) for the memory cell array 1470 from an external source. The memory device 1400 also receives control signals (CE, WE, RE), an address signal ADDR, and a data signal WDATA from an external source. The address signal ADDR is input to the row decoder and column decoder, and the data signal WDATA is input to the write circuit.

[0512] The control logic circuit 1460 processes externally input control signals (CE, WE, RE) to generate control signals for the row decoder and column decoder. Control signal CE is the chip enable signal, control signal WE is the write enable signal, and control signal RE is the read enable signal. The signals processed by the control logic circuit 1460 are not limited to these; other control signals may be input as needed.

[0513] The memory cell array 1470 has multiple memory cells MC arranged in a matrix and multiple wirings. The number of wirings connecting the memory cell array 1470 to the row circuit 1420 is determined by the configuration of the memory cells MC and the number of memory cells MC in each row. Similarly, the number of wirings connecting the memory cell array 1470 to the column circuit 1430 is determined by the configuration of the memory cells MC and the number of memory cells MC in each row.

[0514] Although Figure 28A shows an example in which the peripheral circuit 1411 and the memory cell array 1470 are formed on the same plane, this embodiment is not limited to this. For example, as shown in Figure 28B, the memory cell array 1470 may be provided so as to overlap a part of the peripheral circuit 1411. For example, a sense amplifier may be provided so as to overlap the memory cell array 1470.

[0515] Figures 29A to 29H illustrate an example of a memory cell configuration that can be applied to the above-described memory cell MC.

[0516] [DOSRAM] Figures 29A to 29C show examples of the circuit configuration of a DRAM memory cell. In this specification, a DRAM using a 1OS transistor, 1 capacitance element type memory cell is sometimes referred to as DOSRAM (Dynamic Oxide Semiconductor Random Access Memory). The memory cell 1471 shown in Figure 29A has a transistor M1 and a capacitance element CA. The transistor M1 has a gate (sometimes called a top gate) and a back gate.

[0517] The first terminal of transistor M1 is connected to the first terminal of capacitive element CA, the second terminal of transistor M1 is connected to wiring BIL, the gate of transistor M1 is connected to wiring WOL, and the back gate of transistor M1 is connected to wiring BGL. The second terminal of capacitive element CA is connected to wiring LL.

[0518] Wiring BIL functions as a bit line, and wiring WOL functions as a word line. Wiring LL functions as wiring for applying a predetermined potential to the second terminal of the capacitive element CA. During data writing and reading, wiring LL may be at ground potential or low-level potential. Wiring BGL functions as wiring for applying a potential to the back gate of transistor M1. By applying an arbitrary potential to wiring BGL, the threshold voltage of transistor M1 can be increased or decreased.

[0519] Here, the memory cell 1471 shown in Figure 29A corresponds to the memory device shown in Figure 25. In other words, transistor M1 corresponds to transistor 200, and capacitive element CA corresponds to capacitive device 292.

[0520] Furthermore, the memory cell MC is not limited to memory cell 1471, and the circuit configuration can be changed. For example, the memory cell MC may be configured such that the back gate of transistor M1 is connected to wiring WOL instead of wiring BGL, as shown in memory cell 1472 in Figure 29B. Alternatively, the memory cell MC may be a memory cell composed of a single-gate transistor, i.e., a transistor M1 without a back gate, as shown in memory cell 1473 in Figure 29C.

[0521] When the semiconductor device shown in the above embodiment is used as a memory cell 1471, etc., transistor 200 can be used as transistor M1 and capacitive element 100 can be used as capacitive element CA. By using an OS transistor as transistor M1, the leakage current of transistor M1 can be made very small. In other words, the written data can be held by transistor M1 for a long time, so the frequency of memory cell refresh can be reduced. Alternatively, the refresh operation of the memory cell can be made unnecessary. In addition, because the leakage current is very small, multi-level data or analog data can be held in memory cells 1471, 1472, and 1473.

[0522] Furthermore, in DOSRAM, by configuring the sense amplifier to overlap the memory cell array 1470 as described above, the bit lines can be shortened. This reduces the bit line capacitance and thus the memory cell retention capacity can be reduced.

[0523] [NOSRAM] Figures 29D to 29G show an example of a circuit configuration for a gain cell type memory cell with two transistors and one capacitance element. The memory cell 1474 shown in Figure 29D has a transistor M2, a transistor M3, and a capacitance element CB. The transistor M2 has a top gate (sometimes simply called a gate) and a back gate. In this specification, a memory device having a gain cell type memory cell using an OS transistor for transistor M2 may be called NOSRAM (Nonvolatile Oxide Semiconductor RAM).

[0524] The first terminal of transistor M2 is connected to the first terminal of capacitive element CB, the second terminal of transistor M2 is connected to wiring WBL, the gate of transistor M2 is connected to wiring WOL, and the back gate of transistor M2 is connected to wiring BGL. The second terminal of capacitive element CB is connected to wiring CAL. The first terminal of transistor M3 is connected to wiring RBL, the second terminal of transistor M3 is connected to wiring SL, and the gate of transistor M3 is connected to the first terminal of capacitive element CB.

[0525] Wiring WBL functions as a write bit line, wiring RBL functions as a read bit line, and wiring WOL functions as a word line. Wiring CAL functions as wiring for applying a predetermined potential to the second terminal of the capacitive element CB. When writing and reading data, it is preferable to apply a high-level potential to wiring CAL. Also, when holding data, it is preferable to apply a low-level potential to wiring CAL. Wiring BGL functions as wiring for applying a potential to the back gate of transistor M2. By applying an arbitrary potential to wiring BGL, the threshold voltage of transistor M2 can be increased or decreased.

[0526] Here, the memory cell 1474 shown in Figure 29D corresponds to the memory device shown in Figures 23 and 24. In other words, transistor M2 corresponds to transistor 200, capacitive element CB corresponds to capacitive element 100, transistor M3 corresponds to transistor 300, wiring WBL corresponds to wiring 1003, wiring WOL corresponds to wiring 1004, wiring BGL corresponds to wiring 1006, wiring CAL corresponds to wiring 1005, wiring RBL corresponds to wiring 1002, and wiring SL corresponds to wiring 1001.

[0527] Furthermore, the memory cell MC is not limited to memory cell 1474, and the circuit configuration can be changed as appropriate. For example, the memory cell MC may be configured such that the back gate of transistor M2 is connected to wiring WOL instead of wiring BGL, as shown in memory cell 1475 in Figure 29E. Alternatively, the memory cell MC may be a memory cell composed of a single-gate transistor, i.e., a transistor M2 without a back gate, as shown in memory cell 1476 in Figure 29F. Furthermore, the memory cell MC may be configured such that wiring WBL and wiring RBL are combined into a single wiring BIL, as shown in memory cell 1477 in Figure 29G.

[0528] When the semiconductor device shown in the above embodiment is used as a memory cell 1474, etc., transistor 200 can be used as transistor M2, transistor 300 as transistor M3, and capacitive element 100 as capacitive element CB. By using an OS transistor as transistor M2, the leakage current of transistor M2 can be made very small. As a result, the written data can be held by transistor M2 for a long time, so the frequency of memory cell refresh can be reduced. Alternatively, the refresh operation of the memory cell can be made unnecessary. Also, because the leakage current is very small, multi-level data or analog data can be held in memory cell 1474. The same applies to memory cells 1475 to 1477.

[0529] Transistor M3 may also be a transistor having silicon in its channel formation region (hereinafter sometimes referred to as a Si transistor). The conductivity type of the Si transistor may be n-channel or p-channel. Si transistors may have higher field-effect mobility than OS transistors. Therefore, a Si transistor may be used as transistor M3, which functions as a readout transistor. Furthermore, by using a Si transistor for transistor M3, transistor M2 can be stacked on top of transistor M3, thereby reducing the occupied area of ​​the memory cell and enabling higher integration of the memory device.

[0530] Furthermore, transistor M3 may be an OS transistor. When OS transistors are used for transistors M2 and M3, the memory cell array 1470 can be configured using only n-type transistors.

[0531] Figure 29H also shows an example of a gain cell type memory cell with 3 transistors and 1 capacitance element. The memory cell 1478 shown in Figure 29H has transistors M4 to M6 and a capacitance element CC. The capacitance element CC is provided as appropriate. The memory cell 1478 is electrically connected to wiring BIL, wiring RWL, wiring WWL, wiring BGL, and wiring GNDL. Wiring GNDL is a wiring that provides a low level potential. Note that the memory cell 1478 may be electrically connected to wiring RBL and wiring WBL instead of wiring BIL.

[0532] Transistor M4 is an OS transistor with a back gate, and the back gate is electrically connected to wiring BGL. Alternatively, the back gate and gate of transistor M4 may be electrically connected to each other. Alternatively, transistor M4 may not have a back gate.

[0533] Note that transistors M5 and M6 may be n-channel Si transistors or p-channel Si transistors, respectively. Alternatively, transistors M4 through M6 may be OS transistors. In this case, the memory cell array 1470 can be configured using only n-type transistors.

[0534] When the semiconductor device shown in the above embodiment is used as a memory cell 1478, transistor 200 can be used as transistor M4, transistor 300 can be used as transistors M5 and M6, and capacitive element 100 can be used as capacitive element CC. By using an OS transistor as transistor M4, the leakage current of transistor M4 can be made very small.

[0535] The configuration of the peripheral circuit 1411, memory cell array 1470, etc., as shown in this embodiment is not limited to the above. The arrangement or function of these circuits, and the wiring, circuit elements, etc. connected to them, may be changed, deleted, or added as necessary.

[0536] The configurations and methods described in this embodiment can be used in appropriate combination with other configurations and methods shown in this embodiment, or with other embodiments.

[0537] (Embodiment 5) In this embodiment, Figures 30A and 30B show an example of a chip 1200 on which the semiconductor device of the present invention is mounted. Multiple circuits (systems) are mounted on the chip 1200. This technology of integrating multiple circuits (systems) onto a single chip is sometimes called a System on Chip (SoC).

[0538] As shown in Figure 30A, the chip 1200 includes a CPU 1211, a GPU 1212, one or more analog arithmetic units 1213, one or more memory controllers 1214, one or more interfaces 1215, one or more network circuits 1216, and the like.

[0539] The chip 1200 is provided with bumps (not shown) and connects to the first surface of the package substrate 1201, as shown in Figure 30B. In addition, multiple bumps 1202 are provided on the back surface of the first surface of the package substrate 1201 and connect to the motherboard 1203.

[0540] The motherboard 1203 may be equipped with storage devices such as DRAM 1221 and flash memory 1222. For example, the DOSRAM shown in the previous embodiment can be used for the DRAM 1221. Also, for example, the NOSRAM shown in the previous embodiment can be used for the flash memory 1222.

[0541] The CPU 1211 preferably has multiple CPU cores. Similarly, the GPU 1212 preferably has multiple GPU cores. The CPU 1211 and GPU 1212 may each have memory for temporarily storing data. Alternatively, a memory common to the CPU 1211 and GPU 1212 may be provided on the chip 1200. The memory can be the aforementioned NOSRAM or DOSRAM. The GPU 1212 is suitable for parallel computation of a large amount of data and can be used for image processing or multiply-accumulate operations. By providing the GPU 1212 with an image processing circuit or multiply-accumulate operation circuit using the oxide semiconductor of the present invention, it becomes possible to perform image processing and multiply-accumulate operations with low power consumption.

[0542] Furthermore, because the CPU 1211 and GPU 1212 are located on the same chip, the wiring between the CPU 1211 and GPU 1212 can be shortened, enabling high-speed data transfer from the CPU 1211 to the GPU 1212, data transfer between the memories of the CPU 1211 and GPU 1212, and transfer of calculation results from the GPU 1212 to the CPU 1211 after calculations have been performed on the GPU 1212.

[0543] The analog arithmetic unit 1213 includes one or both an A / D (analog-to-digital) conversion circuit and a D / A (digital-to-analog) conversion circuit. Alternatively, the analog arithmetic unit 1213 may also be provided with the above-mentioned sum-of-accumulate circuit.

[0544] The memory controller 1214 has a circuit that functions as a controller for the DRAM 1221 and a circuit that functions as an interface for the flash memory 1222.

[0545] Interface 1215 has interface circuits for connecting to external devices such as display devices, speakers, microphones, cameras, and controllers. Controllers include mice, keyboards, and game controllers. Such interfaces can include USB (Universal Serial Bus) and HDMI (High-Definition Multimedia Interface).

[0546] The network circuit 1216 includes a network circuit such as a LAN (Local Area Network). It may also include a circuit for network security.

[0547] The above-mentioned circuits (systems) can be formed on chip 1200 using the same manufacturing process. Therefore, even if the number of circuits required for chip 1200 increases, there is no need to increase the number of manufacturing processes, and chip 1200 can be manufactured at a low cost.

[0548] A package substrate 1201 on which a chip 1200 having a GPU 1212 is provided, a motherboard 1203 on which DRAM 1221 and flash memory 1222 are provided, can be called a GPU module 1204.

[0549] The GPU module 1204 has a chip 1200 that uses SoC technology, which allows for a smaller size. Furthermore, its excellent image processing capabilities make it suitable for use in portable electronic devices such as smartphones, tablet devices, laptop PCs, and portable game consoles. Additionally, the multiply-accumulate circuit using the GPU 1212 enables the execution of techniques such as deep neural networks (DNN), convolutional neural networks (CNN), recurrent neural networks (RNN), autoencoders, deep Boltzmann machines (DBM), and deep belief networks (DBN), allowing the chip 1200 to be used as an AI chip, or the GPU module 1204 as an AI system module.

[0550] The configurations and methods described in this embodiment can be implemented by appropriately combining at least a part thereof with other embodiments and examples described herein.

[0551] (Embodiment 6) This embodiment shows an example of an electronic component and electronic device incorporating the storage device and other components described in the above embodiment.

[0552] <Electronic Components> First, an example of an electronic component incorporating the memory device 720 will be explained using Figures 31A and 31B.

[0553] Figure 31A shows a perspective view of an electronic component 700 and a circuit board (mounted board 704) on which the electronic component 700 is mounted. The electronic component 700 shown in Figure 31A has a memory device 720 inside a mold 711. Figure 31A omits some parts to show the inside of the electronic component 700. The electronic component 700 has a land 712 on the outside of the mold 711. The land 712 is electrically connected to an electrode pad 713, and the electrode pad 713 is electrically connected to the memory device 720 by a wire 714. The electronic component 700 is mounted, for example, on a printed circuit board 702. Multiple such electronic components are combined and electrically connected on the printed circuit board 702 to complete the mounted board 704.

[0554] The storage device 720 includes a drive circuit layer 721 and a storage circuit layer 722.

[0555] Figure 31B shows a perspective view of the electronic component 730. The electronic component 730 is an example of a SiP (System in package) or MCM (Multi-Chip Module). The electronic component 730 has an interposer 731 on a package substrate 732 (printed circuit board), and a semiconductor device 735 and multiple storage devices 720 are provided on the interposer 731.

[0556] Electronic component 730 shows an example where the memory device 720 is used as high-bandwidth memory (HBM). Furthermore, the semiconductor device 735 can be an integrated circuit (semiconductor device) such as a CPU, GPU, or FPGA.

[0557] The package substrate 732 can be a ceramic substrate, a plastic substrate, a glass epoxy substrate, or the like. The interposer 731 can be a silicon interposer, a resin interposer, or the like.

[0558] The interposer 731 has multiple wirings and functions to electrically connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 731 also functions to electrically connect integrated circuits provided on the interposer 731 to electrodes provided on the package substrate 732. For these reasons, the interposer is sometimes called a "redistribution substrate" or "intermediate substrate". In addition, through electrodes may be provided on the interposer 731, and these through electrodes may be used to electrically connect the integrated circuits and the package substrate 732. Furthermore, in silicon interposers, TSVs (Through Silicon Vias) can be used as through electrodes.

[0559] It is preferable to use a silicon interposer as the interposer 731. Since silicon interposers do not require active elements, they can be manufactured at a lower cost than integrated circuits. On the other hand, since the wiring of a silicon interposer can be formed using a semiconductor process, it is easy to form fine wiring, which is difficult with resin interposers.

[0560] In HBMs, many connections are necessary to achieve a wide memory bandwidth. Therefore, the interposer on which the HBM is mounted requires fine and high-density wiring. For this reason, it is preferable to use a silicon interposer for mounting the HBM.

[0561] Furthermore, in SiP or MCM using silicon interposers, reliability degradation due to differences in expansion coefficients between the integrated circuit and the interposer is less likely to occur. In addition, because silicon interposers have high surface flatness, connection failures between the integrated circuit and the silicon interposer are less likely to occur. In particular, in 2.5D packages (2.5-dimensional packaging) where multiple integrated circuits are arranged side by side on the interposer, it is preferable to use a silicon interposer.

[0562] Alternatively, a heat sink (heat dissipation plate) may be provided on top of the electronic component 730. If a heat sink is provided, it is preferable to align the heights of the integrated circuits provided on the interposer 731. For example, in the electronic component 730 shown in this embodiment, it is preferable to align the heights of the memory device 720 and the semiconductor device 735.

[0563] To mount the electronic component 730 onto another substrate, electrodes 733 may be provided at the bottom of the package substrate 732. Figure 31B shows an example where the electrodes 733 are formed with solder balls. By providing solder balls in a matrix at the bottom of the package substrate 732, BGA (Ball Grid Array) mounting can be achieved. Alternatively, the electrodes 733 may be formed with conductive pins. By providing conductive pins in a matrix at the bottom of the package substrate 732, PGA (Pin Grid Array) mounting can be achieved.

[0564] The electronic component 730 can be mounted on other boards using various mounting methods, not limited to BGA and PGA. For example, mounting methods such as SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), or QFN (Quad Flat Non-leaded package) can be used.

[0565] The configurations and methods described in this embodiment can be used in appropriate combination with other configurations and methods shown in this embodiment, or with other embodiments.

[0566] (Embodiment 7) This embodiment describes application examples of a memory device using the semiconductor device shown in the previous embodiment. The semiconductor device shown in the previous embodiment can be applied to memory devices of various electronic devices (e.g., information terminals, computers, smartphones, e-book readers, digital cameras (including video cameras), recording and playback de...

Claims

1. The first oxide semiconductor film is deposited by sputtering, A second oxide semiconductor film is deposited on the first oxide semiconductor film by sputtering. A conductive film is formed on the second oxide semiconductor film. A first insulating film is formed on the conductive film. The first oxide semiconductor film, the second oxide semiconductor film, the conductive film, and the first insulating film are processed into island shapes. A second insulating film is formed on the first insulating film. A third insulating film is formed on the second insulating film. An opening reaching the second oxide semiconductor film is formed in the third insulating film. A fourth insulating film is formed to cover the aforementioned opening. A fifth insulating film is formed on the fourth insulating film. A method for manufacturing a semiconductor device, wherein a microwave treatment is performed after the formation of the fifth insulating film, As the fourth insulating film, aluminum oxide deposited by the ALD method is used. As the fifth insulating film, silicon oxide film formed by the PEALD method is used. The first oxide semiconductor film and the second oxide semiconductor film each contain In, Ga, and Zn. The atomic ratio of Ga contained in the first oxide semiconductor film is greater than the atomic ratio of Ga contained in the second oxide semiconductor film. A method for manufacturing a semiconductor device in which the atomic ratio of Zn contained in the first oxide semiconductor film is greater than the atomic ratio of Ga contained in the first oxide semiconductor film.

2. In claim 1, The microwave processing is carried out using argon gas and oxygen gas. Method for manufacturing semiconductor devices.

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