Semiconductor device and method for manufacturing a semiconductor device

Abstract

We provide a semiconductor device that precisely controls doping concentrations. [Solution] Oxygen chemical concentration is 1 × 10 16 atoms / cm 3 A semiconductor device comprising a semiconductor substrate as described above, comprising a buffer region 20 of a first conductivity type having a doping concentration higher than that of a drift region 18, including bulk donors and augmented donors, wherein the concentration of thermal donors over the entire first range 200 from the lower end of the buffer region to the deepest peaks 201-5 is 10% or less of the concentration of augmented donors at the same depth position.

Description

Technical Field

[0001] The present invention relates to a semiconductor device.

Background Art

[0002] Techniques for forming semiconductor devices such as transistors on a semiconductor substrate are known (see, for example, Patent Documents 1 and 2). Patent Document 1: US Patent Application Publication No. 2020 / 0194550 Patent Document 2: US Patent Application Publication No. 2016 / 0329401 Problems to be Solved

[0003] In a semiconductor device, it is preferable to accurately control the doping concentration in a semiconductor substrate. General Disclosure

[0004] In order to solve the above problems, in a first aspect of the present invention, there is provided a semiconductor device including a semiconductor substrate having an upper surface and a lower surface, including a bulk donor and a thermal donor, and having an oxygen chemical concentration of 1×10 16 atoms / cm 3 or more. The semiconductor device may include a drift region of a first conductivity type provided on the semiconductor substrate and including the bulk donor and the thermal donor. Any of the above semiconductor devices may include a buffer region of a first conductivity type provided between the drift region and the lower surface of the semiconductor substrate, including the bulk donor and an increasing donor, and having a higher doping concentration than the drift region. In any of the above semiconductor devices, the buffer region may have one or more doping concentration peaks in the depth direction of the semiconductor substrate. In any of the above semiconductor devices, the one or more doping concentration peaks may include a deepest peak arranged farthest from the lower surface of the semiconductor substrate. In any of the above semiconductor devices, the increasing donor may include the thermal donor. In any of the above semiconductor devices, over the entire first range from the lower end of the buffer region to the deepest peak, the concentration of the thermal donor may be 10% or less of the concentration of the increasing donor at the same depth position.

[0005] In any of the semiconductor devices described above, the increasing donor may include a CiOi-H donor.

[0006] In any of the semiconductor devices described above, the concentration of the thermal donor may be 1% or more of the concentration of the increasing donor at the same depth position over the entire first range.

[0007] In any of the semiconductor devices described above, the oxygen chemical concentration of the semiconductor substrate is 1×10 17 atoms / cm 3 or more and 5×10 17 atoms / cm 3 or less.

[0008] In any of the semiconductor devices described above, the concentration of the thermal donor in the drift region may be 0.0001 times or less of the oxygen chemical concentration.

[0009] In any of the semiconductor devices described above, the doping concentration of the drift region may be 1.5 times or less of the concentration of the bulk donor.

[0010] In any of the semiconductor devices described above, at the apex position of the deepest peak, the concentration of the thermal donor may be 0.1 times or less of the doping concentration.

[0011] In any of the semiconductor devices described above, the buffer region may include a maximum peak having the highest doping concentration among the doping concentration peaks other than the deepest peak. In any of the semiconductor devices described above, at the apex position of the maximum peak, the concentration of the thermal donor may be 0.01 times or less of the doping concentration.

[0012] [[ID=3�]]In any of the semiconductor devices described above, the buffer region may include the shallowest peak closest to the lower surface of the semiconductor substrate. In any of the semiconductor devices described above, at the apex position of the shallowest peak, the concentration of the thermal donor may be 0.001 times or less of the doping concentration.

[0013] In any of the above semiconductor devices, the concentration distribution of the thermal donor may have a decreasing portion in the region of the semiconductor substrate on the upper surface side of the buffer region, where it decreases toward the upper surface of the semiconductor substrate.

[0014] In any of the semiconductor devices described above, the reduction portion may have a region in which the logarithmic gradient of the concentration of the thermal donor toward the upper surface side of the semiconductor substrate is 0.5 times or more and 10 times or less than the logarithmic gradient of the oxygen chemical concentration.

[0015] In a second embodiment of the present invention, the device has an upper and lower surface, contains a bulk donor, and has an oxygen chemical concentration of 1 × 10⁻⁶ 16 atoms / cm 3 The present invention provides a manufacturing method for manufacturing a semiconductor device using a semiconductor substrate as described above. The semiconductor device may include a drift region of a first conductivity type provided on the semiconductor substrate, which includes the bulk donor and the thermal donor. The semiconductor device may include a buffer region of a first conductivity type provided between the drift region and the lower surface of the semiconductor substrate, which includes the bulk donor and the increasing donor, and has a higher doping concentration than the drift region. In any of the above semiconductor devices, the buffer region may have one or more doping concentration peaks in the depth direction of the semiconductor substrate. In any of the above semiconductor devices, the one or more doping concentration peaks may include the deepest peak located furthest from the lower surface of the semiconductor substrate. In any of the above semiconductor devices, the increasing donor may include the thermal donor. The manufacturing method may involve annealing the semiconductor substrate such that the concentration of the thermal donor over the entire first range from the lower end of the buffer region to the deepest peak is 10% or less of the concentration of the increasing donor at the same depth position.

[0016] In any of the above manufacturing methods, in each step of annealing the semiconductor substrate, the time during which the semiconductor substrate passes through a temperature range of 400°C or higher and 500°C or lower may be 20 minutes or less per pass.

[0017] In any of the above manufacturing methods, in each step of annealing the semiconductor substrate, the time during which the semiconductor substrate passes through a temperature range of 425°C or higher and 475°C or lower may be 10 minutes or less per pass.

[0018] In any of the above manufacturing methods, the cumulative time during which the semiconductor substrate passes through a temperature range of 400°C or higher and 500°C or lower in each step of annealing the semiconductor substrate may be 120 minutes or less.

[0019] In any of the above manufacturing methods, the cumulative time during which the semiconductor substrate passes through a temperature range of 425°C or higher and 475°C or lower in each step of annealing the semiconductor substrate may be 60 minutes or less.

[0020] In any of the above manufacturing methods, a metal electrode may be formed on the upper surface of the semiconductor substrate. In any of the above manufacturing methods, the steps after forming the metal electrode may be carried out at a temperature of less than 400°C.

[0021] The above summary of the invention does not enumerate all the necessary features of the present invention. Furthermore, subcombinations of these features may also constitute an invention. [Brief explanation of the drawing]

[0022] [Figure 1] This is a top view showing an example of a semiconductor device 100 according to one embodiment of the present invention. [Figure 2] This is a magnified view of region D in Figure 1. [Figure 3] Figure 2 shows an example of an ee cross-section. [Figure 4] This figure shows a reference example of the doping concentration distribution 210 at the ff line in Figure 3. [Figure 5] This figure shows the distribution of doping concentrations 210 in the example. [Figure 6]This figure shows an example of the oxygen chemical concentration distribution and thermal donor concentration distribution in the region above the buffer region 20 (the region from depth position Zb to depth position Zu). [Figure 7] This is a chart illustrating an example of a manufacturing method for a semiconductor device 100. [Figure 8] This figure shows examples of the time change in the temperature of the semiconductor substrate 10 during each annealing stage. [Figure 9] This chart shows a more specific example of a method for manufacturing a semiconductor device 100. [Figure 10] This is a chart showing the subsequent steps following the process in Figure 9. [Modes for carrying out the invention]

[0023] The present invention will be described below through embodiments of the invention, but these embodiments are not intended to limit the invention as defined in the claims. Furthermore, not all combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0024] In this specification, one side of a semiconductor substrate parallel to its depth direction is referred to as "top," and the other side as "bottom." Of the two main surfaces of a substrate, layer, or other component, one surface is referred to as the top surface, and the other surface as the bottom surface. The directions of "top" and "bottom" are not limited to the direction of gravity or the direction in which the semiconductor device is mounted.

[0025] In this specification, technical matters may be described using the Cartesian coordinate axes, the X, Y, and Z axes. The Cartesian coordinate axes merely specify the relative positions of components and do not limit any particular direction. For example, the Z axis does not limit the direction to height relative to the ground. Note that the +Z axis direction and the -Z axis direction are opposite directions. When the sign is not specified and only the Z axis direction is written, it means the direction parallel to the +Z and -Z axes.

[0026] In this specification, orthogonal axes parallel to the upper and lower surfaces of the semiconductor substrate are defined as the X-axis and the Y-axis. Also, an axis perpendicular to the upper and lower surfaces of the semiconductor substrate is defined as the Z-axis. In this specification, the direction of the Z-axis may sometimes be referred to as the depth direction. Further, in this specification, a direction parallel to the upper and lower surfaces of the semiconductor substrate, including the X-axis and the Y-axis, may sometimes be referred to as the horizontal direction.

[0027] The region from the center of the semiconductor substrate in the depth direction to the upper surface of the semiconductor substrate may sometimes be referred to as the upper surface side. Similarly, the region from the center of the semiconductor substrate in the depth direction to the lower surface of the semiconductor substrate may sometimes be referred to as the lower surface side.

[0028] When referred to as "identical" or "equal" in this specification, it may include cases having errors due to manufacturing variations or the like. Such errors are, for example, within 10%.

[0029] In this specification, the conductivity type of a doped region doped with impurities is described as P-type or N-type. In this specification, an impurity may sometimes mean either an N-type donor or a P-type acceptor, and may be referred to as a dopant. In this specification, doping means introducing a donor or an acceptor into a semiconductor substrate to obtain a semiconductor having an N-type conductivity type or a P-type conductivity type.

[0030] In this specification, the doping concentration means the concentration of donors or acceptors in the thermal equilibrium state. In this specification, the net doping concentration means the net concentration obtained by adding the donor concentration as the concentration of positive ions and the acceptor concentration as the concentration of negative ions, including the polarity of the charges. As an example, when the donor concentration is N D and the acceptor concentration is N A , the net doping concentration at any position is N D -N A . In this specification, the net doping concentration may sometimes be simply referred to as the doping concentration.

[0031] Donors have the function of supplying electrons to a semiconductor. Acceptors have the function of receiving electrons from a semiconductor. Donors and acceptors are not limited to impurities themselves. For example, a VOH defect in a semiconductor, where a vacancy (V), oxygen (O), and hydrogen (H) are bonded, functions as an electron-supplying donor. A hydrogen donor may be a donor in which at least a vacancy (V) and hydrogen (H) are bonded. Alternatively, interstitial Si-H, where interstitial silicon (Si-i) and hydrogen are bonded in a silicon semiconductor, and CiOi-H, where interstitial carbon (Ci) and interstitial oxygen (Oi) and hydrogen are bonded, also function as electron-supplying donors. In this specification, VOH defects, CiOi-H, or interstitial Si-H may be referred to as hydrogen donors.

[0032] In this specification, the semiconductor substrate has N-type bulk donors distributed throughout. Bulk donors are donors from dopants that are substantially uniformly contained within the ingot during the manufacturing of the semiconductor substrate ingot. In this example, the bulk donor is an element other than hydrogen. The bulk donor dopants are, for example, phosphorus, antimony, arsenic, selenium, or sulfur, but are not limited to these. In this example, the bulk donor is phosphorus. Bulk donors are also contained in the P-type region. The semiconductor substrate may be a wafer cut from a semiconductor ingot, or it may be a chip made by cutting a wafer into individual pieces. The semiconductor ingot may be manufactured by one of the following methods: the Czochralski method (CZ method), the magnetic field-applied Czochralski method (MCZ method), or the float-zone method (FZ method). In this example, the ingot is manufactured by the MCZ method. The oxygen concentration in the substrate manufactured by the MCZ method is 1 × 10⁻⁶ 17 ~7×10 17 / cm 3 The oxygen concentration in a substrate manufactured by the FZ method is 1 × 10⁻⁶. 15 ~5×10 16 / cm 3The oxygen concentration tends to generate hydrogen donors more easily. The bulk donor concentration may be the chemical concentration of bulk donors distributed throughout the semiconductor substrate, and may be a value between 90% and 100% of that chemical concentration. Alternatively, a non-doped substrate that does not contain dopants such as phosphorus may be used as the semiconductor substrate. In that case, the bulk donor concentration (D0) of the non-doped substrate may be, for example, 1 × 10⁻⁶. 10 / cm 3 The above 5 x 10 12 / cm 3 The following applies: The bulk donor concentration (D0) of the non-doped substrate is preferably 1 × 10⁻⁶. 11 / cm 3 That concludes the explanation. The bulk donor concentration (D0) of the non-doped substrate is preferably 5 × 10⁻⁶. 12 / cm 3 The following applies. Note that the concentrations in this invention may be values ​​at room temperature. For example, the values ​​at room temperature may be those at 300 K (Kelvin) (approximately 26.9°C).

[0033] In this specification, when P+ type or N+ type is mentioned, it means a higher doping concentration than P type or N type, and when P- type or N- type is mentioned, it means a lower doping concentration than P type or N type. Furthermore, when P++ type or N++ type is mentioned in this specification, it means a higher doping concentration than P+ type or N+ type. Unless otherwise specified, the units used in this specification are SI units. Although units of length may be expressed in cm, calculations may be performed after converting to meters (m).

[0034] In this specification, chemical concentration refers to the atomic density of impurities measured independently of the electrical activation state. Chemical concentration can be measured, for example, by secondary ion mass spectrometry (SIMS). The net doping concentration described above can be measured by voltage-capacitance (CV) spectroscopy. Alternatively, the carrier concentration measured by broadened resistance (SR) spectroscopy may be used as the net doping concentration. The carrier concentration measured by CV or SR spectroscopy may be the value at thermal equilibrium. Furthermore, in the N-type region, since the donor concentration is sufficiently larger than the acceptor concentration, the carrier concentration in that region may be used as the donor concentration. Similarly, in the P-type region, the carrier concentration in that region may be used as the acceptor concentration. In this specification, the doping concentration in the N-type region may be referred to as the donor concentration, and the doping concentration in the P-type region may be referred to as the acceptor concentration.

[0035] If the concentration distribution of the donor, acceptor, or net doping has a peak, the peak value may be used as the concentration of the donor, acceptor, or net doping in that region. If the concentrations of the donor, acceptor, or net doping are nearly uniform, the average value of the concentrations of the donor, acceptor, or net doping in that region may be used as the concentration of the donor, acceptor, or net doping. In this specification, concentrations per unit volume are expressed as atoms / cm³. 3 , or / cm 3 This unit is used for donor or acceptor concentrations in semiconductor substrates, or for chemical concentrations. The atom notation may be omitted.

[0036] The carrier concentration measured by the SR method may be lower than the donor or acceptor concentration. When measuring spreading resistance, the carrier mobility of the semiconductor substrate may be lower than the value for the crystalline state in the range where current flows. The decrease in carrier mobility occurs because carriers are scattered due to disorder in the crystal structure caused by lattice defects, etc.

[0037] The donor or acceptor concentrations calculated from carrier concentrations measured by the CV method or SR method may be lower than the chemical concentrations of the elements that act as donors or acceptors. For example, in silicon semiconductors, the donor concentrations of phosphorus or arsenic, or the acceptor concentration of boron, are approximately 99% of their respective chemical concentrations. On the other hand, the donor concentration of hydrogen, which also acts as a donor in silicon semiconductors, is approximately 0.1% to 10% of the hydrogen chemical concentration.

[0038] Figure 1 is a top view showing an example of a semiconductor device 100 according to one embodiment of the present invention. In Figure 1, the positions of each component projected onto the upper surface of the semiconductor substrate 10 are shown. In Figure 1, only some components of the semiconductor device 100 are shown, and other components are omitted.

[0039] The semiconductor device 100 comprises a semiconductor substrate 10. The semiconductor substrate 10 is a substrate formed of a semiconductor material. As an example, the semiconductor substrate 10 is a silicon substrate. The semiconductor substrate 10 has edges 162 when viewed from above. In this specification, when simply referred to as "top view," it means viewing from the top side of the semiconductor substrate 10. In this example, the semiconductor substrate 10 has two pairs of edges 162 that face each other when viewed from above. In Figure 1, the X and Y axes are parallel to either edge 162. The Z axis is perpendicular to the top surface of the semiconductor substrate 10.

[0040] The semiconductor substrate 10 is provided with an active area 160. The active area 160 is a region in which the main current flows in the depth direction between the upper and lower surfaces of the semiconductor substrate 10 when the semiconductor device 100 is operating. An emitter electrode is provided above the active area 160, but it is omitted in Figure 1. The active area 160 may refer to the region that overlaps with the emitter electrode when viewed from above. Also, the region sandwiched between the active areas 160 when viewed from above may be included in the active area 160.

[0041] The active section 160 is provided with at least one of a transistor section 70 including a transistor element such as an IGBT (Insulated Gate Bipolar Transistor), and a diode section 80 including a diode element such as a freewheeling diode (FWD). In the example shown in Figure 1, the transistor section 70 and the diode section 80 are arranged alternately along a predetermined arrangement direction (in this example, the X-axis direction) on the upper surface of the semiconductor substrate 10. The semiconductor device 100 in this example is a reverse-conducting IGBT (RC-IGBT).

[0042] In Figure 1, the region where the transistor section 70 is located is denoted by the symbol "I," and the region where the diode section 80 is located is denoted by the symbol "F." In this specification, the direction perpendicular to the arrangement direction in a top view may be referred to as the extension direction (Y-axis direction in Figure 1). The transistor section 70 and the diode section 80 may each have their longitudinal length in the extension direction. That is, the length of the transistor section 70 in the Y-axis direction is greater than its width in the X-axis direction. Similarly, the length of the diode section 80 in the Y-axis direction is greater than its width in the X-axis direction. The extension direction of the transistor section 70 and the diode section 80 may be the same as the longitudinal direction of each trench section described later.

[0043] The diode section 80 has an N+ type cathode region in the area in contact with the lower surface of the semiconductor substrate 10. In this specification, the region in which the cathode region is provided is referred to as the diode section 80. In other words, the diode section 80 is the region that overlaps with the cathode region when viewed from above. A P+ type collector region may be provided on the lower surface of the semiconductor substrate 10 in areas other than the cathode region. In this specification, an extension region 81, which is an extension of the diode section 80 in the Y-axis direction to the gate wiring described later, may also be included in the diode section 80. A collector region is provided on the lower surface of the extension region 81.

[0044] The transistor section 70 has a P+ type collector region in the area in contact with the lower surface of the semiconductor substrate 10. Furthermore, the transistor section 70 has a gate structure periodically arranged on the upper surface side of the semiconductor substrate 10, which includes an N type emitter region, a P type base region, a gate conductive portion, and a gate insulating film.

[0045] The semiconductor device 100 may have one or more pads on the semiconductor substrate 10. In this example, the semiconductor device 100 has a gate pad 164. The semiconductor device 100 may also have pads such as an anode pad, a cathode pad, and a current sensing pad. Each pad is located near the edge 162. The vicinity of the edge 162 refers to the area between the edge 162 and the emitter electrode in a top view. When the semiconductor device 100 is mounted, each pad may be connected to an external circuit via wiring such as wires.

[0046] A gate potential is applied to the gate pad 164. The gate pad 164 is electrically connected to the conductive portion of the gate trench of the active portion 160. The semiconductor device 100 is provided with gate wiring that connects the gate pad 164 to the gate trench. In Figure 1, the gate wiring is shown with diagonal hatching.

[0047] The gate wiring in this example has an outer gate wiring 130 and an active gate wiring 131. The outer gate wiring 130 is positioned between the active portion 160 and the edge 162 of the semiconductor substrate 10 in a top view. In this example, the outer gate wiring 130 surrounds the active portion 160 in a top view. The area surrounded by the outer gate wiring 130 in a top view may be considered the active portion 160. Furthermore, a well region is formed below the gate wiring. The well region is a P-type region with a higher density than the base region, which will be described later, and is formed from the top surface of the semiconductor substrate 10 to a position deeper than the base region. The area surrounded by the well region in a top view may be considered the active portion 160.

[0048] The outer perimeter gate wiring 130 is connected to the gate pad 164. The outer perimeter gate wiring 130 is located above the semiconductor substrate 10. The outer perimeter gate wiring 130 may be a metal wiring containing aluminum or the like.

[0049] The active gate wiring 131 is provided in the active section 160. By providing the active gate wiring 131 in the active section 160, variations in the wiring length from the gate pad 164 can be reduced for each region of the semiconductor substrate 10.

[0050] The outer periphery gate wiring 130 and the active side gate wiring 131 are connected to the gate trench portion of the active portion 160. The outer periphery gate wiring 130 and the active side gate wiring 131 are positioned above the semiconductor substrate 10. The outer periphery gate wiring 130 and the active side gate wiring 131 may be wirings formed from a semiconductor such as polysilicon doped with impurities.

[0051] The active gate wiring 131 may be connected to the outer gate wiring 130. In this example, the active gate wiring 131 extends in the X-axis direction from one outer gate wiring 130 to the other outer gate wiring 130 that sandwiches the active section 160, crossing the active section 160 approximately in the center in the Y-axis direction. When the active section 160 is divided by the active gate wiring 131, the transistor section 70 and the diode section 80 may be arranged alternately in the X-axis direction in each divided region.

[0052] The semiconductor device 100 may include a temperature sensing unit (not shown) which is a PN junction diode made of polysilicon or the like, and a current detection unit (not shown) which simulates the operation of a transistor unit provided in the active unit 160.

[0053] In this example, the semiconductor device 100 includes an edge termination structure 90 between the active portion 160 and the edge 162 when viewed from above. In this example, the edge termination structure 90 is positioned between the outer peripheral gate wiring 130 and the edge 162. The edge termination structure 90 mitigates electric field concentration on the upper surface side of the semiconductor substrate 10. The edge termination structure 90 may include at least one of a guard ring, a field plate, and a resurf, which are provided in an annular shape surrounding the active portion 160.

[0054] Figure 2 is an enlarged view of region D in Figure 1. Region D is the region including the transistor section 70, the diode section 80, and the active-side gate wiring 131. The semiconductor device 100 in this example includes a gate trench section 40, a dummy trench section 30, a well section 11, an emitter section 12, a base section 14, and a contact section 15, which are provided inside the upper surface of the semiconductor substrate 10. The gate trench section 40 and the dummy trench section 30 are examples of trench sections. The semiconductor device 100 in this example also includes an emitter electrode 52 and an active-side gate wiring 131, which are provided above the upper surface of the semiconductor substrate 10. The emitter electrode 52 and the active-side gate wiring 131 are provided separately from each other.

[0055] An interlayer insulating film is provided between the emitter electrode 52 and the active gate wiring 131 and the upper surface of the semiconductor substrate 10, but this is omitted in Figure 2. In this example, contact holes 54 are provided in the interlayer insulating film, penetrating the film. In Figure 2, each contact hole 54 is hatched with diagonal lines.

[0056] The emitter electrode 52 is provided above the gate trench 40, dummy trench 30, well region 11, emitter region 12, base region 14, and contact region 15. The emitter electrode 52 contacts the emitter region 12, contact region 15, and base region 14 on the upper surface of the semiconductor substrate 10 through a contact hole 54. The emitter electrode 52 is also connected to a dummy conductive part in the dummy trench 30 through a contact hole provided in the interlayer insulating film. The emitter electrode 52 may be connected to a dummy conductive part of the dummy trench 30 at its tip in the Y-axis direction. The dummy conductive part of the dummy trench 30 does not need to be connected to the emitter electrode 52 and the gate conductive part, and may be controlled to a potential different from the potential of the emitter electrode 52 and the gate conductive part.

[0057] The active gate wiring 131 connects to the gate trench portion 40 through a contact hole provided in the interlayer insulating film. The active gate wiring 131 may be connected to the gate conductive portion of the gate trench portion 40 at the tip portion 41 of the gate trench portion 40 in the Y-axis direction. The active gate wiring 131 is not connected to the dummy conductive portion in the dummy trench portion 30.

[0058] The emitter electrode 52 is formed from a material containing metal. Figure 2 shows the area in which the emitter electrode 52 is provided. For example, at least a portion of the emitter electrode 52 is formed from aluminum or an aluminum-silicon alloy, such as AlSi or AlSiCu. The emitter electrode 52 may have a barrier metal formed from titanium or a titanium compound in the layer below the region formed from aluminum or the like. Furthermore, it may have a plug formed by embedding tungsten or the like in the contact hole so as to be in contact with the barrier metal and the aluminum or the like.

[0059] The well region 11 is provided overlapping with the active gate wiring 131. The well region 11 also extends to a predetermined width in an area that does not overlap with the active gate wiring 131. In this example, the well region 11 is provided away from the Y-axis end of the contact hole 54 towards the active gate wiring 131. The well region 11 is a second conductivity type region with a higher doping concentration than the base region 14. In this example, the base region 14 is P-type, and the well region 11 is P+-type.

[0060] Each of the transistor section 70 and the diode section 80 has multiple trench sections arranged in the direction of arrangement. In this example, the transistor section 70 has one or more gate trench sections 40 and one or more dummy trench sections 30 alternately provided along the direction of arrangement. In this example, the diode section 80 has multiple dummy trench sections 30 provided along the direction of arrangement. In this example, the diode section 80 does not have gate trench sections 40.

[0061] The gate trench portion 40 in this example may have two linear portions 39 (the trench portion which is linear along the extension direction) that extend along the extension direction perpendicular to the alignment direction, and a tip portion 41 that connects the two linear portions 39. In Figure 2, the extension direction is the Y-axis direction.

[0062] Preferably, at least a portion of the tip portion 41 is provided in a curved shape when viewed from above. By connecting the ends of the two straight portions 39 in the Y-axis direction with the tip portion 41, electric field concentration at the ends of the straight portions 39 can be mitigated.

[0063] In the transistor section 70, the dummy trench section 30 is provided between each of the straight sections 39 of the gate trench section 40. There may be one dummy trench section 30 between each of the straight sections 39, or there may be multiple dummy trench sections 30. The dummy trench section 30 may have a straight shape extending in the extension direction, and like the gate trench section 40, it may have a straight section 29 and a tip section 31. The semiconductor device 100 shown in Figure 2 includes both a dummy trench section 30 with a straight shape without a tip section 31 and a dummy trench section 30 with a tip section 31.

[0064] The diffusion depth of the well region 11 may be deeper than the depth of the gate trench portion 40 and the dummy trench portion 30. The Y-axis ends of the gate trench portion 40 and the dummy trench portion 30 are located in the well region 11 when viewed from above. In other words, at the Y-axis end of each trench portion, the bottom in the depth direction of each trench portion is covered by the well region 11. This makes it possible to mitigate electric field concentration at the bottom of each trench portion.

[0065] In the arrangement direction, mesa portions are provided between each trench portion. A mesa portion refers to a region within the semiconductor substrate 10 that is sandwiched between trench portions. For example, the upper end of a mesa portion is the upper surface of the semiconductor substrate 10. The depth position of the lower end of a mesa portion is the same as the depth position of the lower end of a trench portion. In this example, the mesa portion is provided on the upper surface of the semiconductor substrate 10, extending along the trench in the extension direction (Y-axis direction). In this example, a mesa portion 60 is provided in the transistor portion 70, and a mesa portion 61 is provided in the diode portion 80. In this specification, when simply referred to as a mesa portion, it refers to mesa portion 60 and mesa portion 61, respectively.

[0066] Each mesa portion is provided with a base region 14. Of the base regions 14 exposed on the upper surface of the semiconductor substrate 10 in the mesa portion, the region closest to the active gate wiring 131 is defined as base region 14-e. Figure 2 shows the base region 14-e located at one end of each mesa portion in the extending direction, but a base region 14-e is also located at the other end of each mesa portion. In each mesa portion, at least one of a first conductivity type emitter region 12 and a second conductivity type contact region 15 may be provided in the region sandwiched between the base regions 14-e in a top view. In this example, the emitter region 12 is N+ type and the contact region 15 is P+ type. The emitter region 12 and the contact region 15 may be provided in the depth direction between the base region 14 and the upper surface of the semiconductor substrate 10.

[0067] The mesa portion 60 of the transistor portion 70 has an emitter region 12 exposed on the upper surface of the semiconductor substrate 10. The emitter region 12 is provided in contact with the gate trench portion 40. The mesa portion 60 in contact with the gate trench portion 40 may be provided with a contact region 15 exposed on the upper surface of the semiconductor substrate 10.

[0068] Each of the contact region 15 and emitter region 12 in the mesa portion 60 extends from one trench portion to the other in the X-axis direction. As an example, the contact region 15 and emitter region 12 of the mesa portion 60 are arranged alternately along the extension direction (Y-axis direction) of the trench portion.

[0069] In other examples, the contact region 15 and emitter region 12 of the mesa portion 60 may be arranged in a stripe pattern along the extension direction (Y-axis direction) of the trench portion. For example, the emitter region 12 may be provided in the region in contact with the trench portion, and the contact region 15 may be provided in the region sandwiched between the emitter regions 12.

[0070] The mesa portion 61 of the diode portion 80 does not have an emitter region 12. A base region 14 and a contact region 15 may be provided on the upper surface of the mesa portion 61. In the region on the upper surface of the mesa portion 61 sandwiched between the base regions 14-e, a contact region 15 may be provided in contact with each base region 14-e. In the region on the upper surface of the mesa portion 61 sandwiched between the contact regions 15, a base region 14 may be provided. The base region 14 may be arranged in the entire region sandwiched between the contact regions 15.

[0071] A contact hole 54 is provided above each mesa portion. The contact holes 54 are located in the region sandwiched between the base region 14-e. In this example, the contact holes 54 are provided above the contact region 15, the base region 14, and the emitter region 12. The contact holes 54 are not provided in the region corresponding to the base region 14-e and the well region 11. The contact holes 54 may be located in the center of the mesa portion 60 in the alignment direction (X-axis direction).

[0072] In the diode section 80, an N+ type cathode region 82 is provided in the region adjacent to the lower surface of the semiconductor substrate 10. In the region on the lower surface of the semiconductor substrate 10 where the cathode region 82 is not provided, a P+ type collector region 22 may be provided. The cathode region 82 and the collector region 22 are provided between the lower surface 23 of the semiconductor substrate 10 and the buffer region 20. In Figure 2, the boundary between the cathode region 82 and the collector region 22 is shown by a dotted line.

[0073] The cathode region 82 is positioned away from the well region 11 in the Y-axis direction. This ensures a distance between the cathode region 82 and the P-type region (well region 11), which has a relatively high doping concentration and is formed to a deep position, thereby improving pressure resistance. In this example, the Y-axis end of the cathode region 82 is positioned further from the well region 11 than the Y-axis end of the contact hole 54. In other examples, the Y-axis end of the cathode region 82 may be positioned between the well region 11 and the contact hole 54.

[0074] Figure 3 shows an example of the ee cross-section in Figure 2. The ee cross-section is the XZ plane passing through the emitter region 12 and the cathode region 82. In this example, the semiconductor device 100 has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24 in this cross-section.

[0075] The interlayer insulating film 38 is provided on the upper surface of the semiconductor substrate 10. The interlayer insulating film 38 is a film that includes at least one layer of insulating film such as silicate glass with impurities such as boron or phosphorus added, a thermal oxide film, and other insulating films. The interlayer insulating film 38 is provided with contact holes 54 as described in Figure 2.

[0076] The emitter electrode 52 is located above the interlayer insulating film 38. The emitter electrode 52 is in contact with the upper surface 21 of the semiconductor substrate 10 through a contact hole 54 in the interlayer insulating film 38. The collector electrode 24 is located on the lower surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are made of a metallic material such as aluminum. In this specification, the direction connecting the emitter electrode 52 and the collector electrode 24 (Z-axis direction) is referred to as the depth direction.

[0077] The semiconductor substrate 10 has an N-type or N-type drift region 18. The drift region 18 is provided in both the transistor section 70 and the diode section 80.

[0078] The mesa portion 60 of the transistor portion 70 is provided with an N+ type emitter region 12 and a P type base region 14, arranged sequentially from the upper surface 21 of the semiconductor substrate 10. A drift region 18 is provided below the base region 14. An N+ type storage region 16 may also be provided in the mesa portion 60. The storage region 16 is located between the base region 14 and the drift region 18.

[0079] The emitter region 12 is exposed on the upper surface 21 of the semiconductor substrate 10 and is provided in contact with the gate trench portion 40. The emitter region 12 may be in contact with the trench portions on both sides of the mesa portion 60. The doping concentration of the emitter region 12 is higher than that of the drift region 18.

[0080] The base region 14 is located below the emitter region 12. In this example, the base region 14 is located in contact with the emitter region 12. The base region 14 may be in contact with the trenches on both sides of the mesa region 60.

[0081] The accumulation region 16 is located below the base region 14. The accumulation region 16 is an N+ type region with a higher doping concentration than the drift region 18. In other words, the donor concentration in the accumulation region 16 is higher than that in the drift region 18. By providing a high-concentration accumulation region 16 between the drift region 18 and the base region 14, the carrier injection promotion effect (IE effect) can be enhanced and the on-voltage can be reduced. The accumulation region 16 may be provided so as to cover the entire lower surface of the base region 14 in each mesa portion 60.

[0082] A P-shaped base region 14 is provided in the mesa portion 61 of the diode portion 80, in contact with the upper surface 21 of the semiconductor substrate 10. A drift region 18 is provided below the base region 14. A storage region 16 may also be provided below the base region 14 in the mesa portion 61.

[0083] In both the transistor section 70 and the diode section 80, an N+ type buffer section 20 may be provided below the drift section 18. The doping concentration in the buffer section 20 is higher than the doping concentration in the drift section 18. The buffer section 20 may have a concentration peak with a higher doping concentration than the drift section 18. The doping concentration of the concentration peak refers to the doping concentration at the peak of the concentration peak. Furthermore, the doping concentration of the drift section 18 may be the average value of the doping concentration in a region where the doping concentration distribution is nearly flat.

[0084] The buffer region 20 may have two or more concentration peaks in the depth direction (Z-axis direction) of the semiconductor substrate 10. The concentration peaks of the buffer region 20 may be located at the same depth as, for example, the chemical concentration peaks of hydrogen (proton) or phosphorus. The buffer region 20 may function as a field stop layer that prevents the depletion layer extending from the lower end of the base region 14 from reaching the P+ type collector region 22 and the N+ type cathode region 82.

[0085] In the transistor section 70, a P+ type collector region 22 is provided below the buffer region 20. The acceptor concentration of the collector region 22 is higher than that of the base region 14. The collector region 22 may contain the same acceptors as the base region 14, or it may contain different acceptors. The acceptors of the collector region 22 are, for example, boron.

[0086] In the diode section 80, an N+ type cathode region 82 is provided below the buffer region 20. The donor concentration of the cathode region 82 is higher than that of the drift region 18. The donor of the cathode region 82 is, for example, hydrogen or phosphorus. Note that the elements that serve as donors and acceptors for each region are not limited to the examples described above. The collector region 22 and the cathode region 82 are exposed to the lower surface 23 of the semiconductor substrate 10 and are connected to the collector electrode 24. The collector electrode 24 may be in contact with the entire lower surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are formed of a metallic material such as aluminum.

[0087] One or more gate trenches 40 and one or more dummy trenches 30 are provided on the upper surface 21 of the semiconductor substrate 10. Each trench extends from the upper surface 21 of the semiconductor substrate 10, through the base region 14, and down to below the base region 14. In regions where at least one of the emitter region 12, contact region 15, and storage region 16 is provided, each trench also penetrates these doping regions. The statement that a trench penetrates a doping region is not limited to manufacturing in the order of forming the doping region before forming the trench. Manufacturing in which doping regions are formed between the trenches after the trenches have been formed is also included in the statement that a trench penetrates a doping region.

[0088] As described above, the transistor section 70 is provided with a gate trench section 40 and a dummy trench section 30. The diode section 80 is provided with a dummy trench section 30, but not with a gate trench section 40. In this example, the boundary between the diode section 80 and the transistor section 70 in the X-axis direction is the boundary between the cathode region 82 and the collector region 22.

[0089] The gate trench portion 40 has a gate trench provided on the upper surface 21 of the semiconductor substrate 10, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is provided covering the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is provided inside the gate trench, on the inside of the gate insulating film 42. In other words, the gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon.

[0090] The gate conductive portion 44 may be longer than the base region 14 in the depth direction. The gate trench portion 40 in this cross-section is covered by an interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. The gate conductive portion 44 is electrically connected to the gate wiring. When a predetermined gate voltage is applied to the gate conductive portion 44, a channel formed by an electron inversion layer is formed on the surface layer of the interface of the base region 14 that is in contact with the gate trench portion 40.

[0091] The dummy trench portion 30 may have the same structure as the gate trench portion 40 in its cross-section. The dummy trench portion 30 includes a dummy trench, a dummy insulating film 32, and a dummy conductive portion 34 provided on the upper surface 21 of the semiconductor substrate 10. The dummy conductive portion 34 is electrically connected to the emitter electrode 52. The dummy insulating film 32 is provided covering the inner wall of the dummy trench. The dummy conductive portion 34 is provided inside the dummy trench and is located inside the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy conductive portion 34 may be formed from the same material as the gate conductive portion 44. For example, the dummy conductive portion 34 may be formed from a conductive material such as polysilicon. The dummy conductive portion 34 may have the same length as the gate conductive portion 44 in the depth direction.

[0092] In this example, the gate trench portion 40 and the dummy trench portion 30 are covered by an interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. The bottom portions of the dummy trench portion 30 and the gate trench portion 40 may be curved (curved in cross-section) with a downward convex shape.

[0093] Figure 4 shows a reference example of the doping concentration distribution 210 at the ff line in Figure 3. In concentration distribution graphs such as Figure 4, the carrier concentration measured by the SR method, etc., is used as the doping concentration. The ff line is a line parallel to the Z axis that passes through the buffer region 20. The horizontal axis in Figure 4 shows the depth position (position in the Z axis direction) within the semiconductor substrate 10. In concentration distribution graphs such as Figure 4, the lower end position of the buffer region 20 is taken as the reference position (0) in the Z axis direction, and the distance from the reference position is taken as the position in the Z axis direction. At the lower end position of the buffer region 20, there is a dip in the doping concentration distribution due to the PN junction between the collector region 22 and the buffer region 20, but this dip is omitted in Figure 4, etc.

[0094] The semiconductor substrate 10 contains oxygen throughout. Figure 4 shows the distribution 210 when a semiconductor device 100 is formed on two semiconductor substrates 10 with different oxygen chemical concentrations. In Figure 4, the dashed line distribution indicates that the oxygen chemical concentration in the semiconductor substrate 10 is relatively high (e.g., 4 × 10⁻⁶). 17 atoms / cm 3 This is an example where the distribution of the solid line indicates that the oxygen chemical concentration in the semiconductor substrate 10 is relatively low (e.g., 1 × 10⁻⁶). 17 atoms / cm 3 This is an example. The oxygen chemical concentration of the semiconductor substrate 10 may be compared using the average or maximum value of the oxygen chemical concentration of the entire substrate. In each example, the dose and acceleration energy of the dopant locally injected into the buffer region 20 are the same. The dopant injected into the buffer region 20 is, for example, a proton, but is not limited to this.

[0095] In all examples, the buffer region 20 has one or more doping concentration peaks 201. In the example in Figure 4, the buffer region 20 has five doping concentration peaks 201-1 to 201-5. In this specification, among the doping concentration peaks 201 of the buffer region 20, the doping concentration peak 201 furthest from the bottom surface 23 of the semiconductor substrate 10 (doping concentration peak 201-5 in Figure 4) is sometimes referred to as the deepest peak, and the doping concentration peak 201 closest to the bottom surface 23 (doping concentration peak 201-1 in Figure 4) is sometimes referred to as the shallowest peak. Furthermore, the depth position of the peak of doping concentration peak 201-1 is denoted as Z1, and the depth position of the peak of doping concentration peak 201-5 is denoted as Z5. The buffer region 20 has inter-peak regions 301 between adjacent doping concentration peaks 201. Multiple inter-peak regions 301 may be provided. In this specification, among the inter-peak regions 301 of the buffer region 20, the inter-peak region 301 furthest from the lower surface 23 of the semiconductor substrate 10 (inter-peak region 301-4 in Figure 4) is sometimes referred to as the deepest inter-peak region, and the inter-peak region 301 closest to the lower surface 23 (inter-peak region 301-1 in Figure 4) is sometimes referred to as the shallowest inter-peak region.

[0096] A drift region 18 is provided above the buffer region 20. Let Zb be the depth position of the boundary between the buffer region 20 and the drift region 18. Depth position Zb is the position where, in the direction from the buffer region 20 toward the drift region 18, the doping concentration first matches the doping concentration (Dd1 or Dd2) of the drift region 18. No local dopants are injected into the drift region 18. The doping concentration in the drift region 18 may be approximately constant. Thermal donors are formed throughout the semiconductor substrate 10 due to the effect of heat applied to the semiconductor substrate 10. The distribution of thermal donors is approximately uniform throughout the semiconductor substrate 10. Therefore, the doping concentration in the drift region 18 is slightly higher than the bulk donor concentration BD. Oxygen contained in the semiconductor substrate 10 forms unstable oxygen complexes during the heating or cooling process of the semiconductor substrate 10. These oxygen complexes act as dopants within the semiconductor substrate 10. In this specification, oxygen complexes are referred to as thermal donors.

[0097] The concentration of thermal donors formed at each location on the semiconductor substrate 10 varies depending on the oxygen concentration in the semiconductor substrate 10 and the heating and cooling conditions of the semiconductor substrate 10. As shown in Figure 4, in two examples with different oxygen chemical concentrations in the semiconductor substrate 10, the concentration of thermal donors formed differs, and the doping concentration varies throughout the semiconductor substrate 10.

[0098] Let Dd1 be the doping concentration in the drift region 18 in the solid line distribution 210 where the oxygen chemical concentration of the semiconductor substrate 10 is relatively low, and let Dd2 be the doping concentration in the drift region 18 in the dashed line distribution 210 where the oxygen chemical concentration of the semiconductor substrate 10 is relatively high. The doping concentration in each drift region 18 may be the average value over the entire drift region 18, or it may be the minimum value.

[0099] Let Nth1 be the concentration of thermal donors in the solid line distribution 210 where the oxygen chemical concentration of the semiconductor substrate 10 is relatively low, and let Nth2 be the concentration of thermal donors in the dashed line distribution 210 where the oxygen chemical concentration of the semiconductor substrate 10 is relatively high. The difference between the doping concentration (Dd1 or Dd2) in the drift region 18 and the bulk donor concentration BD (Dd1-BD, or Dd2-BD) corresponds to the concentration of thermal donors formed on each semiconductor substrate 10 (Nth1 or Nth2). In each example described herein, the difference between the doping concentration in the drift region 18 and the bulk donor concentration BD is taken as the concentration of thermal donors. The concentration of thermal donors may be the same throughout the semiconductor substrate 10.

[0100] The bulk donor concentration BD may be the minimum chemical concentration of the bulk donor in the semiconductor substrate 10, the chemical concentration of the bulk donor at the center of the depth direction of the semiconductor substrate 10, or the average value of the chemical concentration of the bulk donor in the drift region 18. The bulk donor is a dopant other than oxygen that is distributed throughout the semiconductor substrate 10. The bulk donor may be, for example, phosphorus, arsenic, or antimony, but is not limited to these. When both P-type bulk acceptors and N-type bulk donors are distributed throughout the semiconductor substrate 10, the bulk donor concentration BD is the net concentration determined by the difference between the bulk donor concentration and the bulk acceptor concentration. The concentrations of the bulk donor and bulk acceptor may be values ​​measured by SIMS or the like.

[0101] The buffer region 20 includes bulk donors as well as augmented donors. Augmented donors are donors other than bulk donors. Augmented donors include implanted donors formed by locally implanting ions into the buffer region 20 and the thermal donors described above. When hydrogen ions are locally implanted into the buffer region 20, the implanted donors are hydrogen donors. When phosphorus or the like is locally implanted into the buffer region 20, the implanted donors are phosphorus donors.

[0102] The concentration of thermal donors fluctuates according to the oxygen concentration of the semiconductor substrate 10. Therefore, if the concentration ratio of thermal donors included in the increased donors is high, the concentration of increased donors fluctuates according to the oxygen concentration of the semiconductor substrate 10. Consequently, as shown in the dashed and solid distribution 210 in Figure 4, the doping concentration in the buffer region 20 fluctuates according to the oxygen concentration of the semiconductor substrate 10.

[0103] In the buffer region 20, the range from the bottom of the buffer region 20 to the deepest peak (doping concentration peaks 201-5 in this example) is defined as the first range 200. In the solid line distribution 210, the minimum doping concentration in the first range 200 is defined as Nmin1, and the concentration of the increased donor at that depth is defined as ID1. In this example, the minimum doping concentration Nmin1 in the first range 200 is the doping concentration Nmin1 in the deepest inter-peak region (inter-peak region 301-4 in this example). The concentration of the increased donor ID1 is the difference between the doping concentration Nmin1 and the bulk donor concentration BD (Nmin1-BD). Also, in the dashed line distribution 210, the minimum doping concentration in the first range 200 is defined as Nmin2, and the concentration of the increased donor at that depth is defined as ID2. In the solid line distribution 210, the depth position where the doping concentration is Nmin1 is approximately the same as the depth position where the doping concentration is Nmin2 in the dashed line distribution 210. The concentration ID2 of the increasing donor is the difference between the doping concentration Nmin2 and the bulk donor concentration BD (Nmin2-BD). Note that in some cases, a portion of the interpeak region 301 may have a doping concentration lower than the bulk donor concentration BD. In such cases, the doping concentration in the interpeak region 301 with the minimum doping concentration among the interpeak regions 301 where the doping concentration is higher than the bulk donor concentration BD may be taken as Nmin1.

[0104] The increasing donor concentrations ID1 and ID2 may represent the minimum increasing donor concentrations within the first range 200. Since the thermal donor concentrations Nth1 and Nth2 are approximately constant at each depth position in the buffer region 20, the ratio of thermal donor concentrations Nth1 and Nth2 to increasing donor concentrations ID1 and ID2 represents the maximum thermal donor / increasing donor ratio within the first range 200. The average thermal donor concentration in the drift region 18 may be used as the thermal donor concentration in the buffer region 20, the maximum thermal donor concentration in the drift region 18 may be used as the thermal donor concentration in the buffer region 20, and the thermal donor concentration at depth position Zb may be used as the thermal donor concentration in the buffer region 20.

[0105] In the solid line distribution 210, the concentration ID1 of the increasing donor is 7 × 10 13 / cm 3 Therefore, the concentration Nth1 of the thermal donor is 2 × 10⁻⁶. 13 / cm 3 Of the increased donors, the proportion of thermal donors (Nth1 / ID1) is 29%. In the dashed distribution 210, the concentration of increased donors (ID2) is 1 × 10⁻⁶. 14 / cm 3 Therefore, the concentration Nth2 of the thermal donor is 5 × 10 13 / cm 3 The proportion of thermal donors among the increased donors, Nth2 / ID2, is 50%. When thermal donors account for a large proportion of increased donors, the concentration of increased donors varies greatly depending on the oxygen concentration of the semiconductor substrate 10. This causes fluctuations in characteristics such as the breakdown voltage of the semiconductor device 100. When the breakdown voltage of the example of distribution 210 (solid line) was normalized to 1, the breakdown voltage of the example of distribution 210 (dashed line) was 1.15.

[0106] Figure 5 shows the distribution of doping concentration 210 according to the example. In the example in Figure 5, the concentration of thermal donors formed on the semiconductor substrate 10 is lower than in the example in Figure 4. Therefore, the doping concentration and the concentration of increased donors at each depth position are also different from the example in Figure 4. The other structures are the same as in the example in Figure 4. In Figure 5 as well, the oxygen chemical concentration on the semiconductor substrate 10 is relatively high (e.g., 4 × 10⁻⁶). 17 atoms / cm 3 The distribution of example 210 is shown by a dashed line, and the oxygen chemical concentration in the semiconductor substrate 10 is relatively low (e.g., 1 × 10⁻⁶). 17 atoms / cm 3 The distribution of example 210 is shown by a solid line. In the example in Figure 5, the oxygen chemical concentration contained in the semiconductor substrate 10 is the same as in the example in Figure 4, but the concentration of thermal donors is controlled to a low level by controlling the thermal history of the semiconductor substrate 10.

[0107] As described above, the semiconductor substrate 10 contains bulk donors and thermal donors. Bulk donors and thermal donors may be distributed throughout the semiconductor substrate 10. The drift region 18 contains bulk donors and thermal donors. Other donors do not need to be distributed in the drift region 18.

[0108] The buffer region 20 includes bulk donors and augmented donors. As described above, augmented donors include injection donors and thermal donors. Injection donors may be hydrogen donors, phosphorus donors, or other donors. Hydrogen donors may include CiOi-H donors. Hydrogen donors may also include VOH defects or interstitial Si-H.

[0109] In this example, in both the solid and dashed distributions 210, the thermal donor concentration Nth is less than or equal to 10% of the increasing donor concentration ID at the same depth. In the example in Figure 5, in the solid distribution 210, the minimum doping concentration in the first range 200 is defined as Nmin1, and the increasing donor concentration at that depth is defined as ID1. The increasing donor concentration ID1 is the difference between the doping concentration Nmin1 and the bulk donor concentration BD (Nmin1-BD). In the dashed distribution 210, the minimum doping concentration in the first range 200 is defined as Nmin2, and the increasing donor concentration at that depth is defined as ID2.

[0110] For example, in the distribution shown by the solid line 210, the concentration ID1 of the increasing donor is 5 × 10 13 / cm 3 Therefore, the concentration Nth1 of the thermal donor is 3 × 10⁻⁶. 12 / cm 3 The proportion of thermal donors among the increased donors, Nth1 / ID1, is 6%. In the dashed distribution 210, the concentration ID2 of increased donors is 5 × 10⁻⁶. 13 / cm 3 Therefore, the concentration Nth2 of the thermal donor is 5 × 10 12 / cm 3The proportion of thermal donors among the increased donors, Nth2 / ID2, is 10%. In other words, in all examples, across the entire first range 200, the concentration of thermal donors Nth is 10% or less of the concentration of increased donors ID at the same depth location.

[0111] In this example, by reducing the proportion of thermal donors, the variation in the concentration of increased donors due to the oxygen concentration of the semiconductor substrate 10 can be suppressed. Therefore, fluctuations in characteristics such as the breakdown voltage of the semiconductor device 100 can be suppressed. In the example in Figure 5, if the breakdown voltage of the solid line distribution 210 is set to 1, the breakdown voltage of the dashed line distribution 210 was 1.02.

[0112] Throughout the entire first range 200, the thermal donor concentration Nth may be 10% or less, 8% or less, 6% or less, or 5% or less of the increasing donor concentration ID at the same depth position. By lowering the proportion of thermal donors, variations in the doping concentration in the buffer region 20 can be suppressed, thereby suppressing variations in the characteristics of the semiconductor device 100. Throughout the entire first range 200, the thermal donor concentration Nth may be 0.1% or more, 0.5% or more, 1% or more, 2% or more, 3% or more, or 5% or more of the increasing donor concentration ID at the same depth position.

[0113] The oxygen chemical concentration of the semiconductor substrate 10 is 1 × 10⁻⁶ 16 atoms / cm 3 This concludes the explanation. In this example, even when the oxygen chemical concentration of the semiconductor substrate 10 is high, fluctuations in the characteristics of the semiconductor device 100, such as its breakdown voltage, can be suppressed by suppressing the generation of thermal donors. Therefore, it is not necessary to prepare a substrate with a low oxygen chemical concentration, thus reducing the manufacturing cost of the semiconductor device 100. Furthermore, by using a semiconductor substrate 10 with a high oxygen chemical concentration, hydrogen donors can be easily formed, making it easier to increase the doping concentration of the buffer region 20. The oxygen chemical concentration of the semiconductor substrate 10 is 3 × 10⁻¹⁰. 16 atoms / cm 3 The above is sufficient, 5 × 10 16 atoms / cm 3The above is sufficient, 1 × 10 17 atoms / cm 3 The oxygen chemical concentration of the semiconductor substrate 10 is 1 × 10⁻⁶. 18 atoms / cm 3 The following may be true: 5 × 10 17 atoms / cm 3 The following is also acceptable.

[0114] The concentration of the thermal donor in drift region 18 (Nth1 or Nth2) is 0.0001 times (1 × 10) the oxygen chemical concentration in drift region 18. -4 It may be less than or equal to (times). The oxygen chemical concentration in the drift region 18 may be the average value in the drift region 18, the minimum value, or the value at the center in the depth direction of the drift region 18. This reduces the proportion of thermal donors in the increased donors of the buffer region 20, thereby suppressing characteristic fluctuations of the semiconductor device 100. The concentration of thermal donors (Nth1 or Nth2) in the drift region 18 may be 0.00005 times (5 × 10) the oxygen chemical concentration in the drift region 18. -5 It may be less than or equal to 0.00001 times (1 x 10⁻¹⁰). -5 It may be less than or equal to (times). The concentration of the thermal donor (Nth1 or Nth2) in the drift region 18 is 1 × 10⁻⁶ of the oxygen chemical concentration in the drift region 18. -8 It can be more than double, 5 x 10 -8 It can be more than double, 1 x 10 -7 It can be more than double.

[0115] The doping concentration (Dd1 or Dd2) in the drift region 18 may be 1.5 times or less the bulk donor concentration BD. This reduces the proportion of thermal donors in the increased donors of the buffer region 20, thereby suppressing characteristic fluctuations of the semiconductor device 100. The doping concentration (Dd1 or Dd2) in the drift region 18 may be 1.3 times or less the bulk donor concentration BD, or 1.1 times or less. The doping concentration (Dd1 or Dd2) in the drift region 18 is greater than the bulk donor concentration BD.

[0116] The concentration of thermal donors (Nth1 or Nth2) in the drift region 18 may be 0.5 times or less the concentration of bulk donors BD. This reduces the proportion of thermal donors in the increased donors of the buffer region 20, thereby suppressing characteristic fluctuations of the semiconductor device 100. The concentration of thermal donors (Nth1 or Nth2) in the drift region 18 may be 0.3 times or less the concentration of bulk donors BD, and may also be 0.1 times or less. The concentration of thermal donors (Nth1 or Nth2) in the drift region 18 is greater than 0.

[0117] At depth position Z5 of the apex of the deepest peak (doping concentration peaks 201-5 in this example), the thermal donor concentration Nth may be 0.1 times or less of the doping concentration Np5. In the solid and dashed distribution 210, the values ​​of the doping concentration Np5 are almost identical. This reduces the proportion of thermal donors in the increasing donors of the deepest peak of the buffer region 20, thereby suppressing characteristic fluctuations of the semiconductor device 100. For example, when the semiconductor substrate 10 is turned off, the variation in voltage waveform oscillations when the space charge region (or depletion layer) extending from the upper surface 21 reaches the buffer region 20 can be suppressed. At depth position Z5, the thermal donor concentration Nth may be 0.05 times or less of the doping concentration Np5, or 0.01 times or less.

[0118] The buffer region 20 includes the maximum peak (in this example, doping concentration peak 201-1) among the doping concentration peaks 201 other than the deepest peak. The maximum peak may be any peak other than doping concentration peak 201-1. For example, doping concentration peak 201-2 may be the maximum peak. At depth position Z1 of the peak of the maximum peak, the concentration of the thermal donor may be 0.01 times or less of the doping concentration Np1. This reduces the proportion of thermal donors in the increasing donors of the maximum peak in the buffer region 20, thereby suppressing characteristic fluctuations of the semiconductor device 100. At depth position Z1, the concentration of the thermal donor may be 0.005 times or less of the doping concentration Np1, or 0.001 times or less.

[0119] The buffer region 20 includes the shallowest peak closest to the bottom surface 23 of the semiconductor substrate 10 (in this example, the doping concentration peak 201-1). At depth position Z1 of the apex of the shallowest peak, the concentration of thermal donors may be 0.001 times or less of the doping concentration Np1. This reduces the proportion of thermal donors in the increasing donors of the shallowest peak in the buffer region 20, thereby suppressing characteristic fluctuations of the semiconductor device 100. At depth position Z1, the concentration of thermal donors may be 0.0005 times or less of the doping concentration Np1, or 0.0001 times or less.

[0120] Figure 6 shows an example of the oxygen chemical concentration distribution and thermal donor concentration distribution in the region above the buffer region 20 (the region from depth position Zb to depth position Zu). The oxygen chemical concentration may be a value measured by SIMS or the like. In this example, depth position Zb is the boundary position between the buffer region 20 and the drift region 18, and depth position Zu is the upper end position of the drift region 18.

[0121] In this example, the thermal donor concentration is not constant in the depth direction. The thermal donor concentration at each depth position in the drift region 18 can be calculated from the difference between the doping concentration and the bulk donor concentration BD. Note that the thermal donor concentration in the buffer region 20, as explained in Figure 5, etc., may be calculated using the average value of the thermal donor in the drift region 18 as shown in Figure 6, or it may be calculated using the thermal donor value at depth position Zb.

[0122] The oxygen chemical concentration distribution in this example has a decreasing region 220 in the area from depth position Zb to depth position Zu, where the oxygen chemical concentration decreases toward the upper surface 21 of the semiconductor substrate 10. In the decreasing region 220, the oxygen chemical concentration decreases in proportion to the decreasing distance from the upper surface 21. The decreasing region 220 does not have a region in which the oxygen chemical concentration increases in proportion to the decreasing distance from the upper surface 21.

[0123] Oxygen inside the semiconductor substrate 10 may be released to the outside of the semiconductor substrate 10 during the manufacturing process of the semiconductor device 100. Therefore, the oxygen concentration decreases significantly near the surface of the semiconductor substrate 10, and also gradually decreases toward the substrate surface even at positions away from the surface. In this example of the semiconductor device 100, the region where the oxygen concentration decreases toward the lower surface 23 is ground during the manufacturing process. The reduction portion 220 may be provided across the entire region from depth position Zb to depth position Zu.

[0124] The concentration of thermal donors at each depth position varies according to the oxygen chemical concentration at each depth position. In this example, the thermal donor concentration distribution has a reduction region 230 in the area from depth position Zb to depth position Zu where the thermal donor concentration decreases toward the upper surface 21 of the semiconductor substrate 10. In the reduction region 230, the thermal donor concentration decreases as the distance from the upper surface 21 decreases. The reduction region 230 does not have a region where the thermal donor concentration increases as the distance from the upper surface 21 decreases. The reduction region 230 may be provided in part or throughout the area from depth position Zb to depth position Zu. In the reduction region 230, the thermal donor concentration at depth position Zu may be reduced to half or less of the thermal donor concentration at depth position Zb, to one-quarter or less, to one-tenth or less, or to zero.

[0125] In this example, the reduction section 230 has a region 240 in which the logarithmic gradient αth of the thermal donor concentration toward the upper surface 21 side of the semiconductor substrate 10 is 0.5 times or more and 10 times or less of the logarithmic gradient αox of the oxygen chemical concentration. This reduces the proportion of thermal donors in the doping concentration of the drift region 18 and buffer region 20, thereby suppressing characteristic fluctuations of the semiconductor device 100. Let the depth position of the lower end of region 240 be Xa, and the depth position of the upper end be Xb. Let the position of the center in the depth direction of the semiconductor substrate 10 be Zc. Depth position Xa may be located in the range from depth position Zc to Zb. Depth position Xa may coincide with depth position Zb. Depth position Xb may be located in the range from depth position Zc to Zb, or in the range from depth position Zc to Zu. Depth position Xb may be located on the lower surface 23 side of the region in which the oxygen chemical concentration changes sharply. The depth position Xb may be 10 μm or more away from the upper surface 21 of the semiconductor substrate 10, 20 μm or more, or even 30 μm or more. The region 240 may have a length of 10 μm or more in the depth direction, or even 20 μm or more.

[0126] Let Noxa be the oxygen chemical concentration at depth Xa and Ntha be the thermal donor concentration. Let Noxb be the oxygen chemical concentration at depth Xb and Nthb be the thermal donor concentration. The logarithmic gradient αth of the thermal donor concentration and αox of the oxygen chemical concentration in region 240 are defined by the following equations. αth = |log 10 (Ntha)-log 10 (Nthb)| / |Xa-Xb| αox = |log 10 (Noxa)-log 10 (Noxb)| / |Xa-Xb|

[0127] In region 240, the logarithmic gradient αth of the thermal donor concentration may be 0.8 times or more the logarithmic gradient αox of the oxygen chemical concentration, and may also be 1 time or more. In region 240, the logarithmic gradient αth of the thermal donor concentration may be 7 times or less the logarithmic gradient αox of the oxygen chemical concentration, and may also be 4 times or less.

[0128] Figure 7 is a chart illustrating an example of a method for manufacturing a semiconductor device 100. The manufacturing method includes one or more steps for annealing the semiconductor substrate 10. The manufacturing method includes the steps from cutting a semiconductor wafer from a semiconductor ingot to the completion of the semiconductor device 100. The example manufacturing method in Figure 7 has a first annealing step S701 and a second annealing step S702, but the annealing step in the manufacturing method may be one or three or more. In each annealing step, the semiconductor substrate 10 is heated to a temperature of room temperature (25°C) or higher. In at least one annealing step, the semiconductor substrate 10 may be heated to a temperature of 400°C or higher.

[0129] As described above, the concentration of thermal donors formed on the semiconductor substrate 10 can be controlled by the thermal history of the semiconductor substrate 10. In the manufacturing method of this example, the semiconductor substrate 10 is annealed over the entire first range 200 shown in Figure 5 so that the concentration Nth of thermal donors is 10% or less of the concentration ID of increasing donors at the same depth position.

[0130] Figure 8 shows an example of the time change in the temperature of the semiconductor substrate 10 during each annealing stage. In Figure 8, the horizontal axis represents time, and the vertical axis represents the temperature (°C) of the semiconductor substrate 10. In each annealing stage, the semiconductor substrate 10 is heated from room temperature (RT=25°C) to a predetermined temperature. In the example in Figure 8, the semiconductor substrate 10 is heated to 500°C or higher in both the first annealing stage S701 and the second annealing stage S702.

[0131] In a semiconductor substrate 10 such as silicon, thermal donors are likely to form when the temperature of the semiconductor substrate 10 is near 450°C. Therefore, the formation of thermal donors can be suppressed by controlling the time that the semiconductor substrate 10 passes through a predetermined first temperature range in each annealing stage. In the example in Figure 8, the lower limit temperature of the first temperature range is 400°C and the upper limit temperature is 500°C. In each process of annealing the semiconductor substrate 10, the time that the semiconductor substrate 10 passes through the first temperature range, where the temperature is between 400°C and 500°C, may be 20 minutes or less per pass. In the example in Figure 8, the time that the semiconductor substrate 10 passes through the first temperature range during the heating process of the first annealing stage S701 is T11, the time that it passes through the first temperature range during the cooling process is T21, the time that the semiconductor substrate 10 passes through the first temperature range during the heating process of the second annealing stage S702 is T31, and the time that it passes through the first temperature range during the cooling process is T41. Each of T11, T21, T31, and T41 may be 20 minutes or less. This suppresses the formation of thermal donors on the semiconductor substrate 10 when passing through the first temperature zone. Each of T11, T21, T31, and T41 may be 10 minutes or less, or 5 minutes or less. In addition, the average time of T11, T21, T31, and T41 may be 10 minutes or less, or 5 minutes or less.

[0132] In each step of annealing the semiconductor substrate 10, the total time over all steps from the start to the end of the semiconductor device manufacturing process, during which the semiconductor substrate 10 passes through the first temperature range (400°C or higher, 500°C or lower), may be 120 minutes or less. In the example shown in Figure 8, the sum of T11, T21, T31, and T41 is 120 minutes or less. This suppresses the total amount of heat donors formed on the semiconductor substrate 10. The total time spent passing through the first temperature range may be 60 minutes or less, or 40 minutes or less.

[0133] The temperature range between 425°C and 475°C is defined as the second temperature range. In the second temperature range, thermal donors are more easily formed on the semiconductor substrate 10. In each step of annealing the semiconductor substrate 10, the time spent in the second temperature range (425°C and 475°C) may be 10 minutes or less per pass. In the example in Figure 8, the time spent in the second temperature range during the heating process of the first annealing step S701 is T12, the time spent in the cooling process is T22, the time spent in the second temperature range during the heating process of the second annealing step S702 is T32, and the time spent in the cooling process is T42. Each of T12, T22, T32, and T42 may be 10 minutes or less. This suppresses the formation of thermal donors on the semiconductor substrate 10 when passing through the second temperature range. Each of T12, T22, T32, and T42 may be 5 minutes or less, or 3 minutes or less. Also, the average time of T12, T22, T32, and T42 may be 5 minutes or less, or 3 minutes or less.

[0134] In each step of annealing the semiconductor substrate 10, the cumulative time over all steps from the start to the end of the semiconductor device manufacturing process 100, during which the semiconductor substrate 10 passes through the second temperature zone (425°C or higher, 475°C or lower), may be 60 minutes or less. In the example in Figure 8, the sum of T12, T22, T32, and T42 is 60 minutes or less. This suppresses the total amount of heat donors formed on the semiconductor substrate 10. The cumulative time for passing through the second temperature zone may be 30 minutes or less, or 20 minutes or less.

[0135] Figure 9 is a chart showing a more specific example of a method for manufacturing a semiconductor device 100. In the example in Figure 9, some steps of the manufacturing method are omitted. In this example, an interlayer insulating film 38 is formed on the upper surface 21 of the semiconductor substrate 10 (S901). There may be multiple steps prior to S901 in which the semiconductor substrate 10 is heated to a temperature higher than room temperature (25°C). In S901, the semiconductor substrate 10 may be heated to a temperature of 400°C or higher and 900°C or lower. The time for the temperature of the semiconductor substrate 10 to pass through the first temperature zone and the second temperature zone, as explained in Figures 7 and 8, includes the time in all steps in which the temperature of the semiconductor substrate 10 passes through the first temperature zone and the second temperature zone.

[0136] After forming the interlayer insulating film 38, contact holes 54 are formed in the interlayer insulating film 38. After forming the contact holes 54, a barrier metal may be formed inside the contact holes 54 (S902). In S902, the semiconductor substrate 10 may be heated to a temperature of 400°C or higher and 700°C or lower. The barrier metal may have a film of at least one of titanium and titanium nitride.

[0137] After forming the barrier metal, a metal electrode (emitter electrode 52 in this example) is formed on the upper surface 21 of the semiconductor substrate 10 by sputtering (S903). After forming the emitter electrode 52, the semiconductor substrate 10 is placed in an annealing furnace or the like and annealed (S904). Unless otherwise specified, when heating the semiconductor substrate 10, the entire semiconductor substrate 10 is heated by the annealing furnace or the like. In S904, the semiconductor substrate 10 may be heated to a temperature of less than 400°C.

[0138] After forming the emitter electrode 52, a protective film is formed on the emitter electrode 52 (S905). The protective film is made of, for example, polyimide. After forming the protective film, the semiconductor substrate 10 is heated to the curing temperature of the protective film (S906). In S906, the semiconductor substrate 10 may be heated to a temperature of less than 400°C.

[0139] After forming the protective film, the semiconductor substrate 10 is thinned according to the voltage withstand capability required of the semiconductor device 100 (S907). In S907, the thickness of the semiconductor substrate 10 is adjusted by grinding the lower surface 23 of the semiconductor substrate 10.

[0140] After thinning the semiconductor substrate 10, a collector region 22 is formed on the lower surface 23 of the semiconductor substrate 10 (S908), and a cathode region 82 is formed (S909). S908 and S909 may be performed in any order. In S908 and S909, dopant ions are implanted into the respective regions.

[0141] After implanting dopant ions into the collector region 22 and the cathode region 82, the semiconductor substrate 10 is annealed to activate the dopants (S910). In S910, the semiconductor substrate 10 may be locally heated by laser annealing or the like.

[0142] Figure 10 is a chart showing the process following the steps in Figure 9. After forming the collector region 22 and the cathode region 82, the buffer region 20 is formed (S911). In S911, dopant ions such as protons are injected into the buffer region 20.

[0143] After implanting dopant ions into the buffer region 20, the semiconductor substrate 10 is annealed to activate the dopant (S912). In S912, the semiconductor substrate 10 may be heated to a temperature of less than 400°C.

[0144] After forming the buffer region 20, the semiconductor substrate 10 may be irradiated with charged particles such as helium to form lifetime killers (S913). Lifetime killers are recombination centers such as lattice defects, and by combining with carriers on the semiconductor substrate 10, they shorten the lifetime of the carriers. For example, the upper surface 21 side of the diode portion 80 may be irradiated with charged particles such as helium. After irradiating with charged particles such as helium, the semiconductor substrate 10 is annealed (S914). In S914, the semiconductor substrate 10 may be heated to a temperature of less than 400°C.

[0145] After forming the lifetime killer, the collector electrode 24 is formed by sputtering (S915). After forming the collector electrode 24, the semiconductor substrate 10 is annealed (S916). In S916, the semiconductor substrate 10 may be heated to a temperature of less than 300°C. After forming the collector electrode 24, the semiconductor wafer may be diced to form individual semiconductor chips.

[0146] In the manufacturing method of this example, the steps after forming the emitter electrode 52 (steps from S905 onwards) are performed at a temperature of less than 400°C. This suppresses the formation of thermal donors on the semiconductor substrate 10. The steps after forming the emitter electrode 52 may be performed at a temperature of 390°C or lower, or at a temperature of 380°C or lower. In the manufacturing method of this example, in S901 and S902, the semiconductor substrate 10 is heated to a temperature of 400°C or higher. The temperature of the semiconductor substrate 10 in S901 and S902 may satisfy the conditions described in Figures 7 and 8.

[0147] The annealing conditions in the manufacturing method may be determined based on the oxygen chemical concentration of the semiconductor substrate 10 used. For each oxygen chemical concentration of the semiconductor substrate 10, the change in thermal donor concentration when at least one of the annealing time, heating rate, cooling rate, and annealing temperature is changed may be measured in advance. Based on these measurement results, the concentration of thermal donor formed on the semiconductor substrate 10 can be controlled by adjusting at least one of the annealing time, heating rate, cooling rate, and annealing temperature in each annealing stage.

[0148] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications or improvements can be made to the above embodiments. It will be clear from the claims that such modified or improved forms may also be included in the technical scope of the present invention.

[0149] It should be noted that the execution order of operations, procedures, steps, and stages in the apparatus, systems, programs, and methods shown in the claims, specifications, and drawings is not explicitly stated as "before," "prior to," etc., and that these can be implemented in any order unless the output of a previous process is used in a later process. Even if the operation flow in the claims, specifications, and drawings is described using phrases such as "first," "next," etc. for convenience, it does not mean that it is essential to perform the operations in that order. [Explanation of Symbols]

[0150] 10...Semiconductor substrate, 11...Well region, 12...Emitter region, 14...Base region, 15...Contact region, 16...Storage region, 18...Drift region, 20...Buffer region, 21...Top surface, 22...Collector region, 23...Bottom surface, 24...Collector electrode, 29...Straight section, 30...Dummy trench section, 31...Tip section, 32...Dummy insulating film, 34...Dummy conductive section, 38...Interlayer insulating film, 39...Straight section, 40...Gate trench section, 41...Tip section, 42...Gate insulating film, 44 ...Gate conductive part, 52...Emitter electrode, 54...Contact hole, 60, 61...Mesa part, 70...Transistor part, 80...Diode part, 81...Extended region, 82...Cathode region, 90...Edge termination structure part, 100...Semiconductor device, 130...Outer gate wiring, 131...Active side gate wiring, 160...Active part, 162...Edge, 164...Gate pad, 200...First range, 201...Doping concentration peak, 210...Distribution, 220...Decrease region, 230...Decrease region, 240...Region

Claims

[Claim 1] It has an upper and lower surface, contains bulk donors and thermal donors, and has an oxygen chemical concentration of 1 × 10⁻⁶ １６ atoms / cm ３ A semiconductor device comprising a semiconductor substrate as described above, A drift region of a first conductivity type is provided on the semiconductor substrate, including the bulk donor and the thermal donor, A buffer region of a first conductivity type is provided between the drift region and the lower surface of the semiconductor substrate, and includes the bulk donor and the increased donor, and has a higher doping concentration than the drift region. Equipped with, The buffer region has one or more doping concentration peaks in the depth direction of the semiconductor substrate. The one or more doping concentration peaks include the deepest peak located furthest from the lower surface of the semiconductor substrate, The aforementioned increased donors include the aforementioned thermal donors. The concentration of the thermal donor is 10% or less of the concentration of the increasing donor at the same depth position across the entire first range from the lower end of the buffer region to the deepest peak. Semiconductor equipment.

Images