Manufacturing method for semiconductor devices

Abstract

This invention provides a method for manufacturing a semiconductor device that forms fine wiring layers with high precision. [Solution] A semiconductor packaging method using a bridge die, wherein a surface RDL 22 is first formed on a glass substrate 20. The wiring width / inter-wiring space (L / S) of the surface RDL 22 is narrower than that of the back surface RDL 25. After forming the surface RDL 22, a post 23 is placed on the surface RDL 22, and for example, a bridge die 40 is placed on the surface RDL 22. Then, the post 23 and the bridge die 40 are sealed, and a back surface RDL 25, which is electrically connected to the post 23, is formed on top of them. In this method, unlike conventional methods, the surface RDL 22 is first formed on the glass substrate 20. This makes it possible to form a fine surface RDL 22 with high precision. With this method, for example, a surface RDL with a wiring width / inter-wiring space (L / S) of 2 μm / 2 μm or less can be formed with high precision.

Description

Technical Field

[0001] The present disclosure relates to a method for manufacturing a semiconductor device.

Background Art

[0002] In recent years, with the rapid high-functionality of electronic devices represented by AI / HPC, etc., the size increase and high-density integration of semiconductor packages have been rapidly progressing. The package structure is not limited to the high-density surface mounting, and the complexity and diversification of the package structure and mounting process have been progressing, such as inorganic (silicon) or organic interposer (Bridge die / RDL) technology, 2.xD mounting using it, and 3D mounting (HBM / Chiplet) technology using TSV. For example, Resonac Co., Ltd. is mainly based on the 'Packaging Solution Center' and is developing technologies for next-generation semiconductor packaging processes from the perspective of customers (semiconductor manufacturers) by combining mounting processes and materials.

[0003] As such a technology in the semiconductor package field, Patent Document 1 discloses a method for manufacturing a semiconductor device in which a semiconductor die is mounted face-up on a carrier and sealed, a wiring layer is formed on the sealing layer, and another semiconductor die is mounted on the wiring layer. Patent Document 2 discloses a method for manufacturing another semiconductor device.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0005] In the semiconductor device manufacturing method described in Patent Document 1, after forming a lower wiring layer, a semiconductor die (built-in chip) is placed on the lower wiring layer and a metal pillar is provided. Then, an upper wiring layer is formed on a sealing material layer that seals the semiconductor die and the metal pillar. The upper wiring layer is desired to be miniaturized because it connects the semiconductor die, such as an active die mounted on the surface, to the built-in chip, etc. However, in the manufacturing method described in Patent Document 1, the layers are stacked from the bottom up, and distortion may occur on the surface of the stacked material when forming the upper wiring layer, making it difficult to form a fine upper wiring layer with high precision.

[0006] This disclosure aims to provide a method for manufacturing a semiconductor device that can form fine wiring layers in the semiconductor device with high precision. [Means for solving the problem]

[0007] [1] In one aspect, this disclosure relates to a method for manufacturing a semiconductor device. This method for manufacturing a semiconductor device comprises the steps of: forming a first wiring layer on a first support; providing a conductive columnar member having a first end and a second end on the opposite side on the first wiring layer, wherein the first end is connected to the first wiring layer; providing a semiconductor member including a semiconductor substrate having a first surface and a second surface on the opposite side and a terminal electrode provided on the first surface side of the semiconductor substrate, wherein the terminal electrode is connected to the first wiring layer; forming a first sealing layer on the first wiring layer to seal the columnar member and the semiconductor member; and forming a second wiring layer on the first sealing layer which is electrically connected to at least the columnar member, wherein the second end is connected to the second wiring layer. In this method for manufacturing a semiconductor device, the wiring width of the first wiring layer is narrower than the wiring width of the second wiring layer.

[0008] In this semiconductor device manufacturing method, a first wiring layer having a wiring width narrower than that of the second wiring layer is first formed on a first support. In other words, the second wiring layer is formed after the first wiring layer, which is a fine wiring layer, is formed on the first support. According to this manufacturing method, the first wiring layer, which is a fine wiring layer, can be formed on the first support with high precision.

[0009] [2] In the semiconductor device manufacturing method described in [1] above, the spacing between wirings in the first wiring layer may be narrower than the spacing between wirings in the second wiring layer. In this case, the spacing between wirings in the first wiring layer, which is formed before the second wiring layer, can also be made fine.

[0010] [3] In the semiconductor device manufacturing method described in [1] or [2] above, it is preferable that at least one of the wiring width and the spacing between wirings of the first wiring layer is 5 μm or less. In this case, the first wiring layer can be made into fine wiring.

[0011] [4] Any of the semiconductor device manufacturing methods described in [1] to [3] above further comprises the steps of providing a second support on a second wiring layer and separating the first support from the first wiring layer, wherein it is preferable to separate the first support from the first wiring layer after providing the second support. In this case, various manufacturing steps can be carried out with the fine first wiring layer supported by either support, making it possible to manufacture a semiconductor device using a fine first redistribution layer. Furthermore, even if the fine first wiring layer is formed at an early stage, warping can be prevented.

[0012] [5] The semiconductor device manufacturing method described in [4] above may further include a step of providing connection bumps on the side of the second wiring layer opposite to the first sealing material layer, and the step of providing connection bumps may be performed before providing the second support on the second wiring layer, or after separating the second support from the second wiring layer. If connection bumps are formed before providing the second support on the second wiring layer, active dies such as logic dies can be attached in the final step, so that if there is a defect in the wiring board, it is not necessary to attach expensive active dies, and manufacturing costs can be reduced. Also, if connection bumps are formed after separating the second support from the second wiring layer, many steps can be performed on the wiring board without connection bumps, making it easier to perform various steps such as forming the second wiring layer, and improving manufacturing efficiency.

[0013] [6] Any of the semiconductor device manufacturing methods described in [1] to [5] above may further include a step of grinding the first sealing layer after forming the first sealing layer but before forming the second wiring layer so that the second end of the columnar member is exposed. In this case, the second wiring layer connected to the columnar member can be formed more reliably.

[0014] [7] In any of the semiconductor device manufacturing methods described in [1] to [6] above, the semiconductor component may have internal electrodes extending in the thickness direction of the semiconductor substrate. The first end of the internal electrode may be connected to a first wiring layer, and the second end of the internal electrode may be connected to a second wiring layer. In this case, through-electrodes such as TSVs (Through Silicon Vias) can be provided in the semiconductor substrate, improving the design flexibility of the wiring. Furthermore, miniaturization of the wiring can be promoted.

[0015] [8] The method for manufacturing a semiconductor device according to any of the above [1] to [7] is preferably further comprising the step of attaching at least one semiconductor chip to the side of the first wiring layer opposite to the first encapsulant layer, after the first support has been separated. In this case, even if the fine first wiring layer is formed at an early stage, a method for mounting a semiconductor chip on the first wiring layer can be realized.

[0016] [9] In the semiconductor device manufacturing method described in [8] above, in the step of attaching semiconductor chips, it is preferable to attach a first semiconductor chip and a second semiconductor chip as at least one semiconductor chip to the first wiring layer, and the first semiconductor chip and the second semiconductor chip may be electrically connected by a part of the first wiring layer and a semiconductor member. In this case, the semiconductor member can be used as a so-called bridge die.

[0017]

[10] In the semiconductor device manufacturing method described in [9] above, the first semiconductor chip may include a logic chip, and the second semiconductor chip may include a memory chip. In this case, the logic chip can be easily connected to the memory chip via a bridge die.

[0018]

[11] Any of the semiconductor device manufacturing methods described in [8] to

[10] above may further include a step of forming a second sealing layer that encapsulates at least one semiconductor chip. In this case, the semiconductor chip is reliably protected by the sealing layer.

[0019]

[12] In any of the semiconductor device manufacturing methods described in [8] to

[11] above, at least one of the connections between the first wiring layer and the terminal electrodes of the semiconductor component, and between the first wiring layer and the semiconductor chip, may be made by hybrid bonding. In this case, it is not necessary to consider solder diffusion, etc., and the design of the semiconductor device can be simplified accordingly. Furthermore, because the connection is made by hybrid bonding, fine connections can be reliably made.

[0020]

[13] In any of the semiconductor device manufacturing methods described in [1] to

[12] above, at least one of the first connection point between the first end of the columnar member and the first wiring layer, and the second connection point between the second end of the columnar member and the second wiring layer, may be connected without soldering. In this case, it is not necessary to consider solder diffusion, etc., and the design of the semiconductor device can be simplified accordingly.

[0021]

[14] In the manufacturing method of any of the semiconductor devices [1] to

[13] above, the columnar member may be provided in a substrate having a first surface and a second surface on the opposite side. In the step of providing the columnar member, a connection member including the columnar member, the substrate, and another terminal electrode provided on the first surface side of the substrate may be connected to the first wiring layer so that the first surface faces the first support. In this case, the step of providing the columnar member can be simplified. Also, the attachment of the semiconductor member and the connection member can be carried out in parallel, improving the manufacturing efficiency.

[0022]

[15] In the manufacturing method of the semiconductor device of

[14] above, in the step of forming the first encapsulant layer, the connection member may be encapsulated together with the semiconductor member. In this case, even when using a connection member, a semiconductor device can be manufactured in the same manner as when directly forming the columnar member.

[0023]

[16] The manufacturing method of the semiconductor device of

[14] or

[15] above may further include a step of grinding a part of the semiconductor substrate and a part of the substrate together with the first encapsulant layer so that the second end of the columnar member is exposed after forming the first encapsulant layer and before forming the second wiring layer. In this case, even when using a connection member, a semiconductor device can be manufactured in the same manner as when directly forming the columnar member.

Effect of the Invention

[0024] According to the present disclosure, a fine wiring layer in a semiconductor device can be formed with high precision.

Brief Description of the Drawings

[0025] [Figure 1] FIG. 1 is a cross-sectional view showing an example of a semiconductor device manufactured by the manufacturing method of the semiconductor device according to the first embodiment. [Figure 2] FIGS. 2(a) to (d) are cross-sectional views showing the manufacturing method of the semiconductor device shown in FIG. 1. [Figure 3] FIGS. 3(a) to (c) are cross-sectional views showing the manufacturing method of the semiconductor device shown in FIG. 1, and show the steps performed after the step shown in FIG. 2(d). [Figure 4] Figures 4(a) to 4(c) are cross-sectional views illustrating the manufacturing method of the semiconductor device shown in Figure 1, and show the steps performed after the step shown in Figure 3(c). [Figure 5] Figures 5(a) to 5(c) are cross-sectional views illustrating the manufacturing method of the semiconductor device shown in Figure 1, and show the steps performed after the step shown in Figure 4(c). [Figure 6] Figure 6 is a cross-sectional view showing an example of the cross-sectional configuration of a semiconductor device according to the second embodiment. [Figure 7] Figures 7(a) to 7(c) are cross-sectional views showing the manufacturing method of the semiconductor device shown in Figure 6. [Figure 8] Figures 8(a) to 8(c) are cross-sectional views illustrating the manufacturing method of the semiconductor device shown in Figure 6, and show the steps performed after the step shown in Figure 7(c). [Figure 9] Figures 9(a) to 9(c) are cross-sectional views illustrating the manufacturing method of the semiconductor device shown in Figure 6, and show the steps performed after the step shown in Figure 8(c). [Figure 10] Figures 10(a) to 10(c) are cross-sectional views illustrating the manufacturing method of the semiconductor device shown in Figure 6, and show the steps performed after the step shown in Figure 9(c). [Figure 11] Figures 11(a) to 11(c) are cross-sectional views showing a first modified example of the semiconductor device manufacturing method shown in Figure 6. [Figure 12] Figures 12(a) to 12(c) are cross-sectional views showing a first modified example of the semiconductor device manufacturing method shown in Figure 6, and represent the steps performed after the step shown in Figure 11(c). [Figure 13] Figures 13(a) to (d) are cross-sectional views showing a method for manufacturing a semiconductor device according to a second modified example. [Modes for carrying out the invention]

[0026] Embodiments of the present invention will be described in detail below with reference to the drawings. In the following description, the same or corresponding parts will be denoted by the same reference numerals, and redundant explanations will be omitted. Furthermore, unless otherwise specified, positional relationships such as up, down, left, and right will be based on the positional relationships shown in the drawings. Moreover, the dimensional ratios in the drawings are not limited to those shown.

[0027] In this specification, the term "layer" includes not only structures that are formed on the entire surface when observed in a plan view, but also structures that are formed on only a part of the surface. In this specification, the term "process" includes not only independent processes, but also processes that are not clearly distinguishable from other processes, as long as the intended function of the process is achieved. In this specification, "(meth)acrylic" means acrylic or the corresponding methacrylic. Furthermore, the content of each component in a composition means the total amount of multiple substances present in the composition if there are multiple substances corresponding to each component, unless otherwise specified.

[0028] In this specification, numerical ranges indicated using "~" represent a range that includes the numbers before and after "~" as the minimum and maximum values, respectively. In numerical ranges described in stages in this specification, the upper or lower limit of one stage of the numerical range may be replaced with the upper or lower limit of another stage of the numerical range. In numerical ranges described in this specification, the upper or lower limit of that numerical range may be replaced with the values ​​shown in the examples.

[0029] [First Embodiment] Figure 1 shows an example of a semiconductor device manufactured by the manufacturing method according to the first embodiment. As shown in Figure 1, the semiconductor device 1 comprises semiconductor dies 2 and 3 mounted on the surface side, embedded semiconductor dies 4 and 5, a fine wiring layer 6, a wiring layer 7, encapsulating material layers 8 and 9, a plurality of connection electrodes 10, a plurality of connection bumps 11, and underfills 12 and 13. The semiconductor device 1 is mounted on a substrate M. The substrate M is, for example, a motherboard. The structure S in which the semiconductor device 1 is further mounted on the substrate M is sometimes also referred to as a semiconductor device. In the semiconductor device 1, the wiring layer 7, the encapsulating material layer 8 that encapsulates the semiconductor dies 4 and 5 and the plurality of connection electrodes 10, the fine wiring layer 6 that is electrically connected to the semiconductor dies 4 and 5 and the plurality of connection electrodes 10, and the encapsulating material layer 9 that encapsulates the semiconductor dies 2 and 3 are sequentially stacked on the substrate M.

[0030] The semiconductor dies 2 and 3 are semiconductor chips such as LSI chips (logic chips), CMOS sensors, and memory chips, and are so-called active dies. Each of the semiconductor dies 2 and 3 has terminal electrodes 2a and 3a, and fine wiring layers 2b and 3b provided on the terminal electrode side 2a and 3a. In the semiconductor device 1, the semiconductor dies 2 and 3 are mounted so that the terminal electrodes 2a and 3a face the semiconductor dies 4 and 5 and the fine wiring layer 6. The terminal electrodes 2a and 3a are electrically connected to the wiring portion 6a of the fine wiring layer 6. Underfill material is introduced into the connection area of ​​the terminal electrodes 2a and 3a and hardened to form underfill 13. The semiconductor dies 2 and 3 are sealed by the sealing material that constitutes the sealing layer 9, and each surface is exposed to the outside.

[0031] The semiconductor dies 4 and 5 are, for example, bridge dies or silicon capacitors, and are so-called passive dies. The semiconductor dies 4 and 5 may also be active dies. The semiconductor dies 4 and 5 are ultra-thin semiconductor dies, for example, having a thickness of 100 μm or less, and may have a thickness of 50 μm or less. Each of the semiconductor dies 4 and 5 has terminal electrodes 4a and 5a, and fine wiring layers 4b and 5b provided on the terminal electrode 4a and 5a side. The terminal electrodes 4a and 5a and their pitches of the semiconductor dies 4 and 5 have also been miniaturized, with the diameters of the terminal electrodes 4a and 5a being, for example, 10 μm to 50 μm, and the heights of the terminal electrodes 4a and 5a being, for example, 20 μm to 50 μm. In addition, the terminal pitch (separation distance) between terminal electrodes 4a and between terminal electrodes 5a is, for example, 5 μm to 20 μm. However, the size and pitch of the terminal electrodes 4a and 5a are not limited to those described above, and may be further miniaturized.

[0032] In semiconductor device 1, semiconductor dies 4 and 5 are positioned such that their terminal electrodes 4a and 5a face the semiconductor dies 2 and 3. For example, semiconductor die 4 is a bridge die and connects semiconductor die 2 and semiconductor die 3 to each other via the wiring portion 6a of the fine wiring layer 6. For example, semiconductor die 5 is a silicon capacitor and is connected to semiconductor die 3 via the wiring portion 6a of the fine wiring layer 6. Semiconductor die 5 is not connected to semiconductor die 2. If semiconductor dies 4 and 5 further have through electrodes 4c and 5c, semiconductor dies 4 and 5 connect the wiring portion 6a of the fine wiring layer 6 and the wiring portion 7a of the wiring layer 7 via the through electrodes 4c and 5c. As a result, semiconductor dies 2 and 3 are connected to the wiring portion 7a of the wiring layer 7 and the connecting bump 11.

[0033] The fine wiring layer 6 is a rewiring layer (surface RDL) and has a wiring portion 6a and an insulating portion 6b covering the wiring portion 6a. The wiring layer 7 is a rewiring layer (backside RDL) and has a wiring portion 7a and an insulating portion 7b covering the wiring portion 7a. The wiring width of the fine wiring layer 6 is narrower than the wiring width of the wiring layer 7, and the wiring spacing of the fine wiring layer 6 is narrower than the wiring spacing of the wiring layer 7. Here, the wiring spacing refers to the separation distance at the closest point between adjacent wirings (for example, between the outer surfaces of each wiring). The wiring width and wiring spacing (L / S) of the fine wiring layer 6 may be, for example, 10 μm / 10 μm or less, 5 μm / 5 μm or less, 2 μm / 2 μm or less, or 1 μm / 1 μm or less. The wiring width and wiring spacing of the fine wiring layer 6 may be the same or different. The wiring width and wiring spacing (L / S) of the wiring layer 7 may be, for example, 20 μm / 20 μm or 15 μm / 15 μm. The wiring portion 7a of the wiring layer 7 is connected to the connection bump 11. The connection bump 11 is, for example, a solder bump. Underfill material is introduced into the connection area by the connection bump 11 and hardened to form underfill 12.

[0034] The sealing layers 8 and 9 are layers that seal the semiconductor die with a sealing material, and are sealed with a sealing material containing, for example, epoxy resin. Sealing layer 8 seals the semiconductor dies 4 and 5 and the multiple connecting electrodes 10. Sealing layer 9 seals the semiconductor dies 2 and 3.

[0035] Multiple connecting electrodes 10 are conductive columnar members that connect the fine wiring layer 6 (wiring section 6a) and the wiring layer 7 (wiring section 7a), and are commonly referred to as posts or pillars. The connecting electrodes 10 are made of, for example, copper. The connecting electrodes 10 are provided adjacent to the semiconductor dies 4 and 5. The height of the connecting electrodes 10 is approximately the same as the thickness of the semiconductor dies 4 and 5. The diameter of the connecting electrodes 10 is, for example, 10 μm to 50 μm. The connecting electrodes 10 are sealed together with the semiconductor dies 4 and 5 by a sealing material and are located within the sealing material layer 8. The semiconductor dies 4 and 5 are positioned between the connecting electrodes 10.

[0036] Next, an example of a method for manufacturing the semiconductor device 1 will be described with reference to Figures 2 to 5. Figures 2 to 5 are cross-sectional views sequentially showing the method for manufacturing the semiconductor device 1 described above.

[0037] In this semiconductor device manufacturing method, as shown in Figure 2(a), a temporary fixing layer 21 is first formed on a carrier substrate 20 (first support). The carrier substrate 20 is, for example, a glass substrate. The carrier substrate 20 may also be a Si substrate. The thickness of the carrier substrate 20 may be, for example, 1000 μm to 1200 μm, and is preferably 700 μm to 800 μm. As for the flatness of the carrier substrate 20, the arithmetic mean roughness Ra of the carrier substrate 20 is, for example, 5 nm to 200 nm, and the flatness TTV (Total Thickness Variation) of the carrier substrate 20 is, for example, 0.5 μm to 10 μm. The coefficient of linear expansion CTE of the carrier substrate 20 is, for example, 4 to 20 ppm / K. The temporary fixing layer 21 is, for example, a curable adhesive layer, and is configured to be peeled off together with the carrier substrate 20 by light or heat in a process described later.

[0038] Next, as shown in Figure 2(b), a fine wiring layer 22 (first wiring layer) is formed on the carrier substrate 20 via a temporary fixing layer 21. The fine wiring layer 22 is, for example, a rewiring layer (surface RDL). The fine wiring layer 22 is provided with a wiring portion 22a and an insulating portion 22b that covers the wiring portion 22a. The wiring portion 22a may be formed including, for example, copper pillars. A known method can be used to manufacture the fine wiring layer 22 including the wiring portion 22a. In this manufacturing method, since the fine wiring layer 22 is formed on the carrier substrate 20, the wiring portion 22a can be formed using mask exposure. Therefore, the wiring width and the spacing between wirings (L / S) of the wiring portion 22a of the fine wiring layer 22 can be miniaturized with high precision. For example, the wiring width and inter-wiring space (L / S) of the wiring portion 22a of the fine wiring layer 22 may be 10 μm / 10 μm or less, 5 μm / 5 μm or less, 2 μm / 2 μm or less, or 1 μm / 1 μm or less. The wiring width and inter-wiring space of such a fine wiring layer 22 are narrower than the wiring width and inter-wiring space of the wiring layer 25 (backside RDL) formed in a process described later. The wiring width and inter-wiring space of the fine wiring layer 22 may be the same or different.

[0039] Next, as shown in Figure 2(c), a plurality of posts 23 are formed on the fine wiring layer 22. Each post 23 is a conductive columnar member, formed from, for example, copper. Each post 23 has a first end 23a and a second end 23b on the opposite side, and is formed so that the first end 23a of each post 23 is located on the fine wiring layer 22 side. The posts 23 correspond to the connecting electrodes 10 shown in Figure 1. Since semiconductor dies 30 and 40 will also be installed on the fine wiring layer 22 in a process described later, no posts 23 are installed in that region. The posts 23 can be fabricated, for example, by a semi-additive method. The height of the posts 23 may be, for example, 50 μm to 200 μm, or 75 μm to 180 μm. The diameter of the posts 23 may be, for example, 10 μm to 50 μm. The first end 23a of the posts 23 is electrically connected to the wiring portion 22a of the fine wiring layer 22.

[0040] Next, semiconductor dies 30 and 40 (semiconductor components) are prepared (see Figure 2(d)). The semiconductor die 30 has a semiconductor substrate 31, a plurality of terminal electrodes 32, a fine wiring layer 33, and internal electrodes 34. The semiconductor die 30 corresponds to the semiconductor die 5 shown in Figure 1. The semiconductor substrate 31 is formed from, for example, silicon, and has a first surface 31a and a second surface 31b on the opposite side. The plurality of terminal electrodes 32 are provided on the first surface 31a side of the semiconductor substrate 31. The plurality of terminal electrodes 32 are, for example, copper pillars provided on the first surface 31a side of the semiconductor substrate 31 and are connected to wiring (not shown) in the semiconductor substrate 31. The diameter of each terminal electrode 32 is, for example, 1 μm to 10 μm, the terminal pitch (separation distance) between the terminal electrodes 32 is, for example, 2 μm to 20 μm, and the height of the terminal electrodes 32 is, for example, 2 μm to 50 μm. However, the size of the terminal electrodes 32 is not limited to these.

[0041] The fine wiring layer 33 is a redistribution layer located between the semiconductor substrate 31 and the terminal electrode 32. The fine wiring layer 33 has a wiring portion and an insulating portion that covers the wiring portion. The wiring portion of the fine wiring layer 33 electrically connects the wiring or internal electrode 34 in the semiconductor substrate 31 to the terminal electrode 32. The semiconductor die 30 does not necessarily have to have the fine wiring layer 33.

[0042] The internal electrode 34 is an electrode for connecting the wiring layers provided on both sides of the semiconductor die 30, and is formed to extend in the thickness direction of the semiconductor substrate 31. The internal electrode 34 corresponds to the through electrode 5c shown in Figure 1. The internal electrode 34 has a first end 34a and a second end 34b on the opposite side. The first end 34a is connected to the corresponding terminal electrode 32 via the fine wiring layer 33. On the other hand, the second end 34b of the internal electrode 34 is not exposed to the outside and is located inside the semiconductor substrate 31 at the stage when the semiconductor die 30 is attached to the fine wiring layer 22 (stage (d) in Figure 2). By grinding the second surface 31b of the semiconductor substrate 31 in a process described later, the second end 34b of the internal electrode 34 is exposed to the outside, and the internal electrode 34 functions as a through electrode. The semiconductor die 30 does not necessarily have to have an internal electrode 34 that acts as a through electrode.

[0043] The semiconductor die 40 has the same configuration as the semiconductor die 30, and includes a semiconductor substrate 41, a plurality of terminal electrodes 42, a fine wiring layer 43, and internal electrodes 44. The semiconductor die 40 corresponds to the semiconductor die 4 shown in Figure 1. The semiconductor substrate 41 is formed from, for example, silicon, and has a first surface 41a and a second surface 41b on the opposite side. The plurality of terminal electrodes 42 are provided on the first surface 41a side of the semiconductor substrate 41. The plurality of terminal electrodes 42 are connected to wiring (not shown) within the semiconductor substrate 41. The size and height of the terminal electrodes 42 are the same as those of the terminal electrodes 32.

[0044] The fine wiring layer 43 is a wiring layer located between the semiconductor substrate 41 and the terminal electrode 42. The fine wiring layer 43 has a wiring portion and an insulating portion that covers the wiring portion. The wiring portion of the fine wiring layer 43 electrically connects the wiring or internal electrode 44 in the semiconductor substrate 41 to the terminal electrode 42. The internal electrode 44 is an electrode that connects the wiring layers provided on both sides of the semiconductor die 40, and has a first end 44a and a second end 44b on the opposite side. The first end 44a is connected to the corresponding terminal electrode 42 via the fine wiring layer 43. At this stage, the second end 44b is not exposed to the outside. By grinding the second surface 41b of the semiconductor substrate 41, the second end 44b of the internal electrode 44 is exposed to the outside, and the internal electrode 44 functions as a through electrode. The semiconductor die 40 does not necessarily have to have the fine wiring layer 43 and the internal electrode 44.

[0045] Each of the semiconductor dies 30 and 40 described above can be manufactured by framing a wafer or panel-shaped semiconductor substrate containing a large number of semiconductor dies 30 and 40 having the layer configuration described above.

[0046] Next, once the semiconductor dies 30 and 40 are ready, they are attached to the fine wiring layer 22 as shown in Figure 2(d), with the lower surfaces on which the terminal electrodes 32 and 42 are located facing the fine wiring layer 22. In this step, the semiconductor dies 30 and 40 are positioned in a face-down state, with the terminal electrodes 32 and 42 facing downwards. The terminal electrodes 32 and 42 of the semiconductor dies 30 and 40 are electrically connected to the wiring portion 22a of the fine wiring layer 22. The connection of the terminal electrodes 32 and 42 to the fine wiring layer 22 may be made via solder. Alternatively, underfill may be injected into the gap between the semiconductor dies 30 and 40 and the fine wiring layer 22 and allowed to harden.

[0047] Next, as shown in Figure 3(a), the multiple posts 23 and semiconductor dies 30 and 40 are sealed with a sealing material to form a sealing material layer 24 (first sealing material layer) on the fine wiring layer 22. The sealing material layer 24 is formed by including a thermosetting resin such as epoxy resin, and is cured by heat or the like after sealing. The sealing material that forms the sealing material layer 24 is a material containing a thermosetting resin composition, for example, epoxy resin and a curing agent. The sealing material that forms the sealing material layer 24 may further contain an inorganic filler, for example, silica filler. The average particle size of the inorganic filler contained in the sealing material may be, for example, 50 μm or less, 25 μm or less, 10 μm or less, or 0.01 μm or less. The sealing material that forms the sealing material layer 24 preferably contains large particle size inorganic fillers in order to suppress warping during or after the manufacture of the semiconductor device 1. If underfill is not injected into the gap between the semiconductor dies 30, 40 and the fine wiring layer 22, a sealing material may be injected in this process.

[0048] Next, once the encapsulating layer 24 is formed, it is ground using CMP or the like to thin it down to the ground encapsulating layer 24a, as shown in Figure 3(b). The elastic modulus (Young's modulus) of the encapsulating layers 24 and 24a may be, for example, 3.0 GPa or higher. The coefficient of linear expansion of the encapsulating layers 24 and 24a may be 5 ppm / K to 150 ppm / K. This grinding exposes the second ends 34b and 44b, which are the tips of the internal electrodes 34 and 44, to the outside of the encapsulating layer 24a, resulting in the ground semiconductor dies 30a and 40a. This grinding also exposes the second ends 23b of the multiple posts 23 to the outside of the encapsulating layer 24a. The second ends 23b of the multiple posts 23 may be slightly ground.

[0049] Next, once the sealing material layer 24a is formed, a wiring layer 25 (second wiring layer) is formed on top of the sealing material layer 24a, as shown in Figure 3(c). The wiring layer 25 is, for example, a rewiring layer (backside RDL). The wiring layer 25 is provided with a wiring portion 25a and an insulating portion 25b that covers the wiring portion 25a. The wiring portion 25a connects an external device to the semiconductor dies 50, 55, which will be described later, and is connected, for example, to the second end 23b of each post 23 and to the second ends 34b, 44b of the internal electrodes 34, 44 of the semiconductor dies 30a, 40a. The wiring portion 25a may be formed including, for example, copper pillars. A known method can be used to manufacture the wiring layer 25 including the wiring portion 25a. A connecting bump 26 may be formed on the terminal on the opposite side (upper side in the figure) of the wiring portion 25a. The connecting bump 26 may be, for example, a solder bump.

[0050] Next, once the wiring layer 25 is formed, a carrier substrate 27 (second support) is placed on top of the wiring layer 25, as shown in Figure 4(a). This results in the structure, including the fine wiring layer 22, the sealing material layer 24a, and the wiring layer 25, being sandwiched between the carrier substrate 20 and the carrier substrate 27. The carrier substrate 27 can be the same as the carrier substrate 20, but a different one may also be used. When providing the carrier substrate 27, a temporary fixing layer 28 may be provided on the wiring layer 25 side. The temporary fixing layer 28 can be the same as the temporary fixing layer 21. If a connecting bump 26 is formed, it is preferable that the temporary fixing layer 28 has a thickness that protects the connecting bump 26.

[0051] Next, once the carrier substrate 27 is provided, the carrier substrate 20 is separated from the fine wiring layer 22, as shown in Figure 4(b). In this separation, the temporary fixing layer 21 is irradiated with laser light or subjected to heat treatment to reduce its adhesion, thereby separating the carrier substrate 20 from the fine wiring layer 22 by peeling.

[0052] Next, once the carrier substrate 20 is separated, semiconductor dies 50 and 55 (first semiconductor chip and second semiconductor chip) are attached to the side 22c (bottom surface shown) of the fine wiring layer 22 opposite to the sealing material layer 24a, as shown in Figure 4(c). At this time, the terminal electrodes of the semiconductor dies 50 and 55 are connected to the tips of the wiring portions 22a of the fine wiring layer 22. This connection may be made via solder. The semiconductor dies 50 and 55 are semiconductor chips such as LSI chips (logic chips), CMOS sensors, and memory chips, and are so-called active dies. The semiconductor dies 50 and 55 correspond to the semiconductor dies 3 and 2 shown in Figure 1. Here, it is sufficient to attach one or more semiconductor chips, but it is preferable to attach two or more semiconductor chips. In this process, the semiconductor die 50 and semiconductor die 55 are electrically connected to each other by the built-in semiconductor die 40a. The built-in semiconductor die 30a is connected to the semiconductor die 50. Each post 23 is similarly connected to the semiconductor dies 50 and 55 via the fine wiring layer 22. The connection of the terminal electrodes of the semiconductor dies 50 and 55 to the fine wiring layer 22 may be via solder. Alternatively, underfill may be injected into the gap between the semiconductor dies 50 and 55 and the fine wiring layer 22 and then cured.

[0053] Next, when the semiconductor dies 50 and 55 are mounted, as shown in Figure 5(a), the semiconductor dies 50 and 55 are sealed with a encapsulant on the fine wiring layer 22, forming an encapsulant layer 29 (second encapsulant layer) on the fine wiring layer 22. The encapsulant layer 29, like the encapsulant layers 24 and 24a, contains a thermosetting resin such as epoxy resin, and is cured after sealing. If underfill has not been injected into the gap between the semiconductor dies 50 and 55 and the fine wiring layer 22, the encapsulant may be injected in this step.

[0054] Next, once the semiconductor dies 50 and 55 are sealed with the sealing material to form the sealing layer 29, the sealing layer 29 may be ground until the surfaces 50a and 55a of the semiconductor dies 50 and 55 are exposed from the surface of the sealing layer, as shown in Figure 5(b). This thins the sealing layer 29 to the sealing layer 29a shown in Figure 5(b).

[0055] Next, when the sealing material layer 29a is ground down, as shown in Figure 5(c), the temporary fixing layer 28 is irradiated with laser light or subjected to heat treatment to reduce its adhesion and separate the carrier substrate 27 from the wiring layer 25 by peeling. This exposes the connecting bumps 26 to the outside. In the above description, an example was shown in which the connecting bumps 26 are manufactured in the process shown in Figure 3(c), but the explanation is not limited to this, and the connecting bumps 26 may be provided on the wiring layer 25 after the temporary fixing layer 28 has been separated.

[0056] Based on the above, the semiconductor device 1 shown in Figure 5(c) and Figure 1 is fabricated. This semiconductor device 1 is mounted on a substrate M. At this time, an underfill material is applied between the semiconductor device 1 and the substrate M. Subsequently, the underfill material is cured by heat curing or the like to fabricate the semiconductor device (structure S) shown in Figure 1.

[0057] As described above, in the semiconductor device manufacturing method according to the first embodiment, a fine wiring layer 22 (front RDL) having a wiring width narrower than the wiring width of the wiring layer 25 is first formed on the carrier substrate 20. In other words, the wiring layer 25 (back RDL) is formed after the fine wiring layer 22 is formed on the carrier substrate 20. According to this manufacturing method, the fine wiring layer 22 can be formed on the carrier substrate 20 with high precision.

[0058] In the semiconductor device manufacturing method according to this embodiment, the carrier substrate 20 is separated from the fine wiring layer 22 after the carrier substrate 27 is provided. This allows various manufacturing processes to be carried out while the fine wiring layer 22 and the encapsulating material layers 24, 24a are supported by either support. Therefore, semiconductor devices using the fine wiring layer 22 and thin encapsulating material layers 24, 24a can be reliably manufactured. Furthermore, even if the fine wiring layer 22 and encapsulating material layers 24, 24a are thin, warping and cracking can be prevented.

[0059] In the semiconductor device manufacturing method according to this embodiment, connection bumps 26 are provided on the side of the wiring layer 25 opposite to the sealing material layer 24. The step of providing the connection bumps 26 can be performed before the carrier substrate 27 is placed on the wiring layer 25, or after the carrier substrate 27 is separated from the wiring layer 25. If the connection bumps 26 are formed before the carrier substrate 27 is placed on the wiring layer 25, active dies such as logic dies can be attached in the final step. Therefore, if there is a defect in the wiring substrate, it is not necessary to attach expensive active dies, and manufacturing costs can be reduced. On the other hand, if the connection bumps 26 are formed after the carrier substrate 27 is separated from the wiring layer 25, many steps can be performed on the wiring substrate without the connection bumps 26. Therefore, various steps such as the formation of the wiring layer 25 can be performed more easily, and manufacturing efficiency can be improved.

[0060] In the semiconductor device manufacturing method according to this embodiment, the sealing material layer 24 is ground after it has been formed but before the wiring layer 25 has been formed, so that the second end 23b of the post 23 is exposed. This makes it possible to form the wiring layer 25 connected to the post 23 more reliably.

[0061] In the semiconductor device manufacturing method according to this embodiment, the semiconductor dies 30 and 40 may have internal electrodes 34 and 44 extending in the thickness direction of the semiconductor substrates 31 and 41. The first ends 34a and 44a of the internal electrodes 34 and 44 are connected to the fine wiring layer 22, and the second ends 34b and 44b of the internal electrodes 34 and 44 are connected to the wiring layer 25. This allows through-electrodes such as TSVs (Through Silicon Vias) to be provided in the semiconductor substrates 31 and 41, improving the design flexibility of the wiring. It also promotes the miniaturization of the wiring.

[0062] In the semiconductor device manufacturing method according to this embodiment, after separating the carrier substrate 20, semiconductor dies 50 and 55 are attached to the side of the fine wiring layer 22 opposite to the sealing material layer 24. This makes it possible to mount semiconductor dies 50 and 55 on the fine wiring layer 22 even when the fine wiring layer 22 is formed at an early stage.

[0063] In the semiconductor device manufacturing method according to this embodiment, a sealing material layer 29 is formed to seal the semiconductor dies 50 and 55. This ensures that the semiconductor dies 50 and 55 are reliably protected by the sealing material layer 29.

[0064] In the semiconductor device manufacturing method according to this embodiment, the first connection point between the first end 23a of the post 23 and the fine wiring layer 22 (wiring portion 22a), and the second connection point between the second end 23b of the post 23 and the wiring layer 25 (wiring portion 25a) are connected without soldering. This eliminates the need to consider solder diffusion, etc., and thus simplifies the design of the semiconductor device.

[0065] [Second Embodiment] Next, a semiconductor device and its manufacturing method according to the second embodiment will be described with reference to Figures 6 to 10. Points that overlap with the semiconductor device and its manufacturing method according to the first embodiment may be omitted from the explanation.

[0066] Figure 6 shows an example of a semiconductor device manufactured by the manufacturing method according to the second embodiment. As shown in Figure 6, the semiconductor device 1A comprises semiconductor dies 2, 3, semiconductor dies 4, 5, a fine wiring layer 6, a wiring layer 7, encapsulating material layers 8, 9, connecting bumps 11, and underfills 12, 13. Such a semiconductor device 1A is mounted on a substrate M. This semiconductor device 1A differs from the semiconductor device 1 according to the first embodiment in that it is further provided with a connecting member 60 including a plurality of connecting electrodes 10.

[0067] The connecting member 60 includes a plurality of connecting electrodes 10, a substrate 61 in which the connecting electrodes 10 are provided, a terminal electrode 62 provided on the first surface side (upper side in the figure) of the substrate 61, and a fine wiring layer 63 disposed between the substrate 61 and the terminal electrode 62.

[0068] The substrate 61 is formed from silicon or the like, similar to the semiconductor substrates of the semiconductor dies 4 and 5. The substrate 61 may also be formed from other materials (e.g., resin). The connecting electrode 10 is a through electrode that penetrates the substrate 61, and its function is the same as in the first embodiment. In the semiconductor device 1A according to the second embodiment, the connecting member 60 has a configuration similar to that of the semiconductor dies 4 and 5.

[0069] Next, an example of a method for manufacturing the semiconductor device 1A will be described with reference to Figures 7 to 10. Figures 7 to 10 are cross-sectional views showing the method for manufacturing the semiconductor device 1A described above, in order.

[0070] In the method for manufacturing a semiconductor device according to the second embodiment, as in the first embodiment, a temporary fixing layer 21 is first formed on the carrier substrate 20 (first support), as shown in Figure 7(a).

[0071] Next, as shown in Figure 7(b), a fine wiring layer 22 (first wiring layer) is formed on the carrier substrate 20 via a temporary fixing layer 21. The fine wiring layer 22 is, for example, a rewiring layer (surface RDL). The fine wiring layer 22 is provided with a wiring portion 22a and an insulating portion 22b that covers the wiring portion 22a. In this manufacturing method, as in the first embodiment, the fine wiring layer 22 is formed on the carrier substrate 20, so the wiring portion 22a can be formed using mask exposure, and the wiring width and inter-wiring space (L / S) of the wiring portion 22a can be miniaturized. For example, the wiring width and inter-wiring space (L / S) of the wiring portion 22a of the fine wiring layer 22 may be 10 μm / 10 μm or less, 5 μm / 5 μm or less, 2 μm / 2 μm or less, or 1 μm / 1 μm or less. The wiring width and inter-wiring space of such fine wiring layer 22 are, as in the first embodiment, narrower than the wiring width and inter-wiring space of the wiring layer 25 formed in a process described later.

[0072] Next, a connecting member 60 is prepared in which a plurality of posts 23 are provided inside a substrate 61 (see Figure 7(c)). The connecting member 60 includes a plurality of posts 23, a substrate 61 having a first surface 61a and a second surface 61b opposite to it, and terminal electrodes 62 provided on the first surface 61a side of the substrate 61. In the connecting member 60, the first end 23a of the post 23 is connected to the terminal electrode 62, but the second end 23b of the post 23 is located inside the substrate 61. The connecting member 60 may further have a fine wiring layer 63 between the substrate 61 and the terminal electrode 62. The fine wiring layer 63 connects the posts 23 and the terminal electrode 62.

[0073] Next, once the preparation of the connecting member 60 is complete, the connecting member 60 is attached to the fine wiring layer 22, as shown in Figure 7(c), so that the lower surface on which the terminal electrodes 62 are provided faces the carrier substrate 20. This connects each post 23 to the wiring portion 22a of the fine wiring layer 22. The connection of the terminal electrodes 62 to the fine wiring layer 22 may be made via solder. Alternatively, underfill may be injected into the gap between the connecting member 60 and the fine wiring layer 22 and allowed to harden. Simultaneously with the installation of the connecting member 60, or before or after the installation of the connecting member 60, the semiconductor dies 30 and 40 are attached to the fine wiring layer 22. The method of attaching the semiconductor dies 30 and 40 is the same as in the first embodiment. This results in the state shown in Figure 7(c). In this step, the connecting member 60 and the semiconductor dies 30 and 40 are arranged in a face-down state, with the terminal electrodes facing downwards.

[0074] Next, as shown in Figure 8(a), the connecting member 60 including multiple posts 23 and the semiconductor dies 30 and 40 are sealed with a sealing material to form a sealing material layer 24 on the fine wiring layer 22. The sealing material layer 24 is hardened by heat or other means after the sealing is completed.

[0075] Next, once the sealing layer 24 is formed, it is ground using CMP or the like to thin it down to the ground sealing layer 24a, as shown in Figure 8(b). This grinding exposes the second ends 34b and 44b, which are the tips of the internal electrodes 34 and 44, to the outside of the sealing layer 24a, forming the semiconductor dies 30a and 40a. This grinding also exposes the second ends 23b of the multiple posts 23 provided within the connecting member 60 to the outside of the sealing layer 24a.

[0076] Next, once the sealing material layer 24a is formed, a wiring layer 25 is formed on top of the sealing material layer 24a, as shown in Figure 8(c). The wiring layer 25 is, for example, a rewiring layer (backside RDL). The wiring section 25a connects an external device to the semiconductor dies 50 and 55, which will be described later. For example, it connects the second end 23b of each post 23 to the second ends 34b and 44b of the internal electrodes 34 and 44 of the semiconductor dies 30a and 40a. A connecting bump 26 may also be formed on the terminal on the opposite side (upper side in the figure) of the wiring section 25a. The connecting bump 26 may be, for example, a solder bump.

[0077] Next, once the wiring layer 25 is formed, a carrier substrate 27 is placed on top of the wiring layer 25, as shown in Figure 9(a). When placing the carrier substrate 27, a temporary fixing layer 28 may be provided on the wiring layer 25 side. After that, as shown in Figure 9(b), the carrier substrate 20 is separated from the fine wiring layer 22.

[0078] Next, once the carrier substrate 20 is separated, the semiconductor dies 50 and 55 are attached to the side 22c (the lower side shown) of the fine wiring layer 22 opposite to the sealing material layer 24a, as shown in Figure 9(c). At this time, the terminal electrodes of the semiconductor dies 50 and 55 are connected to the ends of the wiring portions 22a of the fine wiring layer 22. In this process, the semiconductor die 50 and semiconductor die 55 are electrically connected to each other by the built-in semiconductor die 40a. The built-in semiconductor die 30a is connected to the semiconductor die 50. Each post 23 is similarly connected to the semiconductor dies 50 and 55 via the fine wiring layer 22.

[0079] Next, when the semiconductor dies 50 and 55 are mounted, as shown in Figure 10(a), the semiconductor dies 50 and 55 are sealed with a sealing material on the fine wiring layer 22 to form a sealing material layer 29 on the fine wiring layer 22. The sealing material layer 29, like the sealing material layers 24 and 24a, is composed of a thermosetting resin such as epoxy resin, and is cured after sealing is performed.

[0080] Next, when the semiconductor dies 50 and 55 are sealed with the sealing material to form the sealing material layer 29, the sealing material layer 29 may be ground until the surfaces 50a and 55a of the semiconductor dies 50 and 55 are exposed from the surface of the sealing material layer 29, as shown in Figure 10(b). This thins the sealing material layer 29 to the sealing material layer 29a shown in Figure 10(b).

[0081] Next, when the sealing material layer 29a is ground down, as shown in Figure 10(c), the temporary fixing layer 28 is subjected to laser irradiation or heat treatment to reduce its adhesion and separate the carrier substrate 27 from the wiring layer 25 by peeling. As a result, the connecting bumps 26 are exposed to the outside.

[0082] Based on the above, the semiconductor device 1A shown in Figure 10(c) and Figure 6 is fabricated. This semiconductor device 1A is mounted on a substrate M. At this time, an underfill material is applied between the semiconductor device 1A and the substrate M. Subsequently, the underfill material is cured by heat curing or the like to fabricate the semiconductor device (structure S) shown in Figure 6.

[0083] [Example 1] Next, a first modified example of the manufacturing method according to the second embodiment will be described with reference to Figures 11 and 12. Figures 11(a) to 11(c) and 12(a) to 12(c) are diagrams illustrating the process following the process shown in Figure 8(a).

[0084] In the first modified method for manufacturing a semiconductor device, the steps shown in Figures 7(a) to 8(a) are performed to seal the connecting member 60 including a plurality of posts 23 and the semiconductor dies 30 and 40 with a sealing material, thereby forming a sealing material layer 24 on the fine wiring layer 22. Subsequently, as shown in Figure 11(a), the carrier substrate 20 is separated from the fine wiring layer 22 by peeling.

[0085] Next, as shown in Figure 11(b), semiconductor dies 50 and 55 are attached to the surface 22c of the fine wiring layer 22 opposite to the encapsulating material layer 24a. At this time, the terminal electrodes of the semiconductor dies 50 and 55 are connected to the tips of the wiring portions 22a of the fine wiring layer 22. In this process, the semiconductor die 50 and semiconductor die 55 are electrically connected to each other by the built-in semiconductor die 40. The built-in semiconductor die 30 is connected to the semiconductor die 50. Each post 23 is similarly connected to the semiconductor dies 50 and 55 via the fine wiring layer 22. When attaching the semiconductor dies 50 and 55, because the semiconductor dies 50 and 55 are relatively thick, the encapsulating material layer 24 is thick before grinding, and the semiconductor dies 30 and 40, which include a substrate such as silicon, and the connecting member 60 are included, they can be attached without causing warping, cracking, etc.

[0086] Next, when the semiconductor dies 50 and 55 are mounted, as shown in Figure 11(c), the semiconductor dies 50 and 55 are sealed with a sealing material on the fine wiring layer 22 to form a sealing material layer 29 on the fine wiring layer 22. The sealing material layer 29, like the sealing material layer 24, is composed of a thermosetting resin such as epoxy resin, and is cured after sealing is performed.

[0087] Next, once the semiconductor dies 50 and 55 are sealed with the sealing material to form the sealing layer 29, the sealing layer 29 may be ground until the surfaces 50a and 55a of the semiconductor dies 50 and 55 are exposed from the surface of the sealing layer 29, as shown in Figure 12(a). This thins the sealing layer 29 to the sealing layer 29a shown in Figure 12(a).

[0088] Next, when the sealing layer 29a is ground, the sealing layer 24 on the opposite side is ground using CMP or the like, and as shown in Figure 12(b), the sealing layer 24a is thinned after grinding. This grinding exposes the second ends 34b and 44b, which are the tips of the internal electrodes 34 and 44, to the outside of the sealing layer 24a, becoming semiconductor dies 30a and 40a. This grinding also exposes the second ends 23b of the multiple posts 23 provided in the connecting member 60 to the outside of the sealing layer 24a.

[0089] Next, once the sealing material layer 24a is formed, a wiring layer 25 is formed on top of the sealing material layer 24a, as shown in Figure 12(c). The wiring portion 25a of the wiring layer 25 connects the external device to the semiconductor dies 50 and 55, and is connected, for example, to the second end 23b of each post 23 and to the second ends 34b and 44b of the internal electrodes 34 and 44 of the semiconductor dies 30a and 40a. In addition, a connection bump 26 may be formed on the terminal on the opposite side (upper side in the figure) of the wiring portion 25a. The connection bump 26 may be, for example, a solder bump.

[0090] Based on the above, the semiconductor device 1A shown in Figure 12(c) and Figure 6 is fabricated. This semiconductor device 1A is then mounted on the substrate M.

[0091] [Second variation] Next, with reference to Figure 13, a second modified example of the manufacturing method according to the second embodiment will be described. As shown in Figure 13(a), in this manufacturing method, similar to the above, a temporary fixing layer 21 is first formed on the carrier substrate 20, and a fine wiring layer 22 is formed on the carrier substrate 20 via the temporary fixing layer 21.

[0092] Next, once the semiconductor dies 30, 40 and the connecting member 60 are ready, the semiconductor dies 30, 40 and the connecting member 60 are joined to the fine wiring layer 22 by so-called hybrid bonding. In this hybrid bonding, the terminal electrodes 32, 42 of the semiconductor dies 30, 40 and the terminal electrode 62 of the connecting member 60 are joined to the wiring portion 22a of the fine wiring layer 22 without the use of solder bumps or Cu bumps. In addition, the insulating portions of the fine wiring layers 33, 43 of the semiconductor dies 30, 40 and the insulating portion of the fine wiring layer 63 of the connecting member 60 are joined to the insulating portion 22b of the fine wiring layer 22. Known methods can be used for such hybrid bonding.

[0093] Next, once the semiconductor dies 30, 40 and the connecting member 60 are attached to the fine wiring layer 22 by hybrid bonding, as shown in Figure 13(c), they are sealed with a sealing material in the same manner as described above, and the sealing material layer is ground to form a sealing material layer 24a. After that, a wiring layer 25 is formed on top of the sealing material layer 24a.

[0094] Next, as shown in Figure 13(d), a carrier substrate 27 is attached to the wiring layer 25, and the carrier substrate 20 is separated from the fine wiring layer 22. Then, in the same manner as above, semiconductor dies 50 and 55 are attached to the fine wiring layer 22 and sealed with a sealing material to form a sealing layer 29a. Through this process, the semiconductor device 1A shown in Figure 13(c) and Figure 6 is manufactured. When attaching the semiconductor dies 50 and 55 to the fine wiring layer 22, the wiring portion 22a and insulating portion 22b of the fine wiring layer 22 and the semiconductor dies 50 and 55 may be joined by hybrid bonding in the same manner as above. When joining by hybrid bonding, underfill injection, etc., is not required.

[0095] As described above, in the manufacturing method of the semiconductor device according to the second embodiment and its modified form, a fine wiring layer 22 having a wiring width narrower than the wiring width of the wiring layer 25 is first formed on the carrier substrate 20, similar to the first embodiment. In other words, the wiring layer 25 is formed after the fine wiring layer 22 is formed on the carrier substrate 20. Therefore, according to this manufacturing method, the fine wiring layer 22 can be formed on the carrier substrate 20 with high precision. It should be noted that in the manufacturing method according to the second embodiment and its modified form, the same effects and advantages as in the first embodiment will be apparent to those skilled in the art in the same steps as in the first embodiment, so a detailed explanation is omitted.

[0096] In the semiconductor device manufacturing method according to this embodiment and its modified form, the post 23 is provided within a substrate 61 having a first surface 61a and a second surface 61b on the opposite side. The post 23 is then provided on the fine wiring layer 22 by connecting a connecting member 60, which includes the post 23, the substrate 61, and a terminal electrode 62 provided on the first surface 61a side of the substrate 61, to the fine wiring layer 22 such that the first surface 61a faces the carrier substrate 20. As a result, according to the manufacturing method of the second embodiment and its modified form, the process of providing the post 23 can be simplified. Furthermore, the attachment of the semiconductor dies 30, 40 and the connecting member 60 can be carried out in parallel, thereby improving manufacturing efficiency.

[0097] In the semiconductor device manufacturing method according to this embodiment and its modified form, the connecting member 60 is sealed together with the semiconductor dies 30 and 40 when forming the sealing material layer 24. Therefore, even when using the connecting member 60, the semiconductor device can be manufactured in the same way as when the post 23 is directly formed.

[0098] In the semiconductor device manufacturing method according to the second modified example, at least one of the connections between the fine wiring layer 22 and the terminal electrodes 32 and 42 of the semiconductor dies 30 and 40, and between the fine wiring layer 22 and the semiconductor dies 50 and 55, may be made by hybrid bonding. In this case, it becomes unnecessary to consider solder diffusion, etc., and the design of the semiconductor device can be simplified accordingly. Furthermore, because the connection is made by hybrid bonding, fine connections can be reliably made.

[0099] Although embodiments of the present disclosure have been described above, the present invention is not limited to the embodiments described above, and modifications may be made as appropriate without departing from the spirit of the invention. [Explanation of Symbols]

[0100] 1,1A...Semiconductor device, 20...Carrier substrate (first support), 22...Fine wiring layer (first wiring layer), 23...Post (columnar member), 23a...First end, 23b...Second end, 24,24a...Sealing material layer, 25...Wiring layer (second wiring layer), 26...Connecting bump, 27...Carrier substrate (second support), 30,30a,40,40a...Semiconductor die (semiconductor component), 31,41...Semiconductor substrate, 31a,41a...First surface, 31b,41b...Second surface, 32,42...Terminal electrodes, 34,44...Internal electrodes (through electrodes), 60...Connecting member, 61...Substrate, 61a...First surface, 62...Terminal electrodes.

Claims

1. A step of forming a first wiring layer on a first support, A step of providing a conductive columnar member having a first end and a second end on the opposite side on the first wiring layer, wherein the first end is connected to the first wiring layer, A step of providing a semiconductor member, which includes a semiconductor substrate having a first surface and a second surface on the opposite side, and terminal electrodes provided on the first surface side of the semiconductor substrate, on a first wiring layer, wherein the terminal electrodes are connected to the first wiring layer. A step of forming a first sealing material layer on the first wiring layer to seal the columnar member and the semiconductor member, The process includes a step of forming a second wiring layer on the first sealing material layer, which is electrically connected to at least the columnar member, wherein the second end is connected to the second wiring layer, The wiring width of the first wiring layer is narrower than the wiring width of the second wiring layer. A method for manufacturing a semiconductor device.

2. The spacing between wirings in the first wiring layer is narrower than the spacing between wirings in the second wiring layer. A method for manufacturing a semiconductor device according to claim 1.

3. At least one of the wiring width and the spacing between wiring in the first wiring layer is 5 μm or less. A method for manufacturing a semiconductor device according to claim 1 or 2.

4. The steps include providing a second support on the second wiring layer, The step of separating the first support from the first wiring layer further comprises After providing the second support, the first support is separated from the first wiring layer. A method for manufacturing a semiconductor device according to claim 1 or 2.

5. The process further includes providing a connecting bump on the side of the second wiring layer opposite to the first sealing material layer, The step of providing the connecting bump is performed before providing the second support on the second wiring layer, or after separating the second support from the second wiring layer. The method for manufacturing a semiconductor device according to claim 4.

6. The method further comprises a step of grinding the first sealing layer after forming the first sealing layer but before forming the second wiring layer, so that the second end of the columnar member is exposed. A method for manufacturing a semiconductor device according to claim 1 or 2.

7. The semiconductor member has internal electrodes that extend in the thickness direction of the semiconductor substrate, The first end of the internal electrode is connected to the first wiring layer, The second end of the internal electrode is connected to the second wiring layer. A method for manufacturing a semiconductor device according to claim 1 or 2.

8. The process further comprises the step of attaching at least one semiconductor chip to the surface of the first wiring layer opposite to the first sealing layer, after the first support has been separated. A method for manufacturing a semiconductor device according to claim 1 or 2.

9. In the step of attaching the semiconductor chip, the first semiconductor chip and the second semiconductor chip are attached to the first wiring layer as the at least one semiconductor chip. The first semiconductor chip and the second semiconductor chip are electrically connected by a part of the first wiring layer and the semiconductor member. The method for manufacturing a semiconductor device according to claim 8.

10. The first semiconductor chip includes a logic chip, The second semiconductor chip includes a memory chip. The method for manufacturing a semiconductor device according to claim 9.

11. The method for manufacturing a semiconductor device according to claim 8, further comprising the step of forming a second sealing layer that encapsulates the at least one semiconductor chip.

12. At least one of the following is joined by hybrid bonding: between the first wiring layer and the terminal electrode of the semiconductor member, and between the first wiring layer and the semiconductor chip. The method for manufacturing a semiconductor device according to claim 8.

13. At least one of the first connection point between the first end of the columnar member and the first wiring layer, and the second connection point between the second end of the columnar member and the second wiring layer, is connected without soldering. A method for manufacturing a semiconductor device according to claim 1 or 2.

14. The columnar member is provided within a substrate having a first surface and a second surface on the opposite side. In the step of providing the columnar member, a connecting member including the columnar member, the substrate, and another terminal electrode provided on the first surface side of the substrate is connected to the first wiring layer such that the first surface faces the first support. A method for manufacturing a semiconductor device according to claim 1 or 2.

15. In the step of forming the first sealing layer, the connecting member is sealed together with the semiconductor member. The method for manufacturing a semiconductor device according to claim 14.

16. The process further includes a step of grinding a portion of the semiconductor substrate and a portion of the substrate together with the first sealing material layer so that the second end of the columnar member is exposed, after the first sealing material layer has been formed but before the second wiring layer has been formed. The method for manufacturing a semiconductor device according to claim 14.

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