Semiconductor memory element

Abstract

We provide a 3D semiconductor memory element with increased integration density. [Solution] The semiconductor memory element 100 has a memory cell region and a pad region WPR arranged along a first horizontal direction, and comprises a first word line stack WSA consisting of a plurality of first word lines WLA that extend in the first horizontal direction (X direction) and are separated from each other in the second horizontal direction (Y direction) and vertical direction (Z direction) which are perpendicular to the first horizontal direction, and the pad region includes a plurality of first word line pad portions WLPA, and a second word line stack WSB that extends in the first horizontal direction and is separated from each other in the second horizontal direction and vertical direction, and consists of a plurality of second word lines WLB that include a plurality of second word line pad portions WLPB in the pad region, and superimposes each other in the vertical direction on the first word line stack.

Description

Technical Field

[0001] The present invention relates to a semiconductor memory device, and more particularly, to a three-dimensional semiconductor memory device including a plurality of memory cells arranged three-dimensionally.

Background Art

[0002] As miniaturization, multifunctionalization, and high performance of electronic products are required, a large-capacity semiconductor memory device is required, and an increased integration degree is required to provide a large-capacity semiconductor memory device. Since the integration degree of a conventional semiconductor memory device including a plurality of memory cells arranged two-dimensionally is mainly determined by the area occupied by a unit memory cell, although the integration degree of a two-dimensional semiconductor memory device has been increasing, it is still limited. Therefore, a three-dimensional semiconductor memory device has been proposed in which memory cells are stacked vertically on a substrate so as to include a plurality of memory cells arranged three-dimensionally to increase the memory capacity.

Summary of the Invention

Problems to be Solved by the Invention

[0003] The present invention has been made in view of the above-described prior art, and an object of the present invention is to provide a three-dimensional semiconductor memory device with an increased integration degree.

Means for Solving the Problems

[0004] A semiconductor memory element according to one aspect of the present invention, made to achieve the above objective, has a memory cell region and a pad region arranged along a first horizontal direction, a first word line stack consisting of a plurality of first word lines extending in the first horizontal direction and spaced apart from each other in a second horizontal direction and a vertical direction perpendicular to the first horizontal direction, and the pad region including a plurality of first word line pad portions, a second word line stack extending in the first horizontal direction and spaced apart from each other in the second horizontal direction and the vertical direction, and the pad region including a plurality of second word line pad portions, superimposed on the first word line stack in the vertical direction, and a plurality of first word lines extending in the vertical direction and having one end connected to the plurality of first word line pad portions. The device comprises: a first word line contact; a plurality of second word line contacts having one end extending vertically and connected to the plurality of second word line pad portions; a plurality of word line routing vias extending vertically and separated in the pad region from each of the plurality of first word lines and the plurality of second word lines; a plurality of word line routing lines connecting one end of the plurality of word line routing vias to the other end of the plurality of second word line contacts; a plurality of first routing pads connected to the other end of the plurality of first word line contacts; and a plurality of second routing pads connected to the other end of the plurality of word line routing vias, wherein the plurality of first routing pads and the plurality of second routing pads are located at the same vertical level.

[0005] To achieve the above objective, another aspect of the present invention provides a semiconductor memory element having a memory cell region and a pad region arranged along a first horizontal direction, comprising a memory cell structure and a peripheral circuit structure stacked vertically with the memory cell structure and electrically connected, wherein the peripheral circuit structure includes a peripheral circuit board and a plurality of peripheral circuit transistors located on the active surface of the peripheral circuit board, and the memory cell structure comprises a first word line stack consisting of a plurality of first word lines extending in the first horizontal direction and spaced apart from each other in a second horizontal direction and a vertical direction perpendicular to the first horizontal direction, and the pad region including a plurality of first word line pad portions, and a plurality of second word lines extending in the first horizontal direction and spaced apart from each other in the second horizontal direction and the vertical direction, and the pad region including a plurality of second word line pad portions, The system includes: a second word line stack superimposed on each other in the vertical direction; a plurality of first word line contacts having one end extending in the vertical direction and connected to the plurality of first word line pad portions; a plurality of second word line contacts having one end extending in the vertical direction and connected to the plurality of second word line pad portions; a plurality of word line routing vias extending in the vertical direction, separated from each of the plurality of first word lines and the plurality of second word lines in the pad region; a plurality of word line routing lines connecting one end of the plurality of word line routing vias to the other end of the plurality of second word line contacts; a plurality of first routing pads connected to the other end of the plurality of first word line contacts; and a plurality of second routing pads connected to the other end of the plurality of word line routing vias.

[0006] To achieve the above objective, a semiconductor memory element according to yet another aspect of the present invention comprises a memory cell structure and a peripheral circuit structure stacked vertically on the memory cell structure and electrically connected, having a memory cell region and a pad region arranged along a first horizontal direction, the peripheral circuit structure includes a peripheral circuit board and a plurality of peripheral circuit transistors located on the active surface of the peripheral circuit board, the memory cell structure comprises a first word line stack consisting of a plurality of first word lines extending in the first horizontal direction and spaced apart from each other in a second horizontal direction and a vertical direction perpendicular to the first horizontal direction, each including a plurality of first word line pad portions in the pad region, a second word line stack overlapping each other vertically on the first word line stack, each consisting of a plurality of second word lines extending in the first horizontal direction and spaced apart from each other in the second horizontal direction and the vertical direction, each including a plurality of second word line pad portions in the pad region, a plurality of first bit lines extending vertically between the plurality of first word lines, and a plurality of second bit lines extending vertically between the plurality of second word lines The bit line includes: a plurality of first word line contacts connected to the lower surface of the plurality of first word line pad portions and extending vertically; a plurality of second word line contacts connected to the upper surface of the plurality of second word line pad portions and extending vertically; a plurality of word line routing vias extending vertically in the pad region along the spaces between the second horizontally spaced first word lines among the plurality of first word lines, and between the second horizontally spaced second word lines among the plurality of second word lines; a plurality of word line routing lines connecting the upper ends of the plurality of second word line contacts to the upper ends of the plurality of word line routing vias; a plurality of first routing pads connected to the lower ends of the plurality of first word line contacts; and a plurality of second routing pads connected to the lower ends of the plurality of word line routing vias and electrically connected to the plurality of second word line contacts, wherein the plurality of first word line contacts have a tapered shape, with their horizontal width increasing as they move away from the plurality of first word line pad portions.The plurality of second word line contacts have a tapered shape, with their horizontal width increasing as they move away from the plurality of second word line pads, and the plurality of word line routing vias have a tapered shape, with their horizontal width decreasing as they extend from the plurality of word line routing lines toward the plurality of second routing pads. [Effects of the Invention]

[0007] According to the semiconductor memory element of the present invention, the area in which multiple word line pads are arranged in a planar manner is reduced, thereby increasing the integration density. [Brief explanation of the drawing]

[0008] [Figure 1] This is an equivalent circuit diagram showing an example of a memory cell array of a semiconductor memory element according to one embodiment of the present invention. [Figure 2] This is a block diagram illustrating an example of a semiconductor memory element according to one embodiment of the present invention. [Figure 3A] This is a plan view of a semiconductor memory element, the first example according to one embodiment of the present invention, as seen from above and below. [Figure 3B] This is a plan view of a semiconductor memory element, the first example according to one embodiment of the present invention, as seen from below and above. [Figure 3C] These are cross-sectional views of the first example of a semiconductor memory element, cut along the line I-I' in Figures 3A and 3B. [Figure 3D] These are cross-sectional views of the first example of a semiconductor memory element, cut along the line II-II' in Figures 3A and 3B. [Figure 3E] These are cross-sectional views of the first example of a semiconductor memory element, cut along the line III-III' in Figures 3A and 3B. [Figure 4A] This is a perspective view showing an example of a memory cell included in a semiconductor memory element according to one embodiment of the present invention. [Figure 4B] This is a perspective view showing another example of a memory cell included in a semiconductor memory device according to one embodiment of the present invention. [Figure 4C]This is a perspective view showing yet another example of a memory cell contained in a semiconductor memory element according to one embodiment of the present invention. [Figure 5A] This is a plan view of a second example of a semiconductor memory element according to one embodiment of the present invention, viewed from above and below. [Figure 5B] This is a plan view of a second example of a semiconductor memory element according to one embodiment of the present invention, viewed from below and above. [Figure 6] This is a cross-sectional view of a semiconductor memory element of the second example modification, cut along the line II-II' in Figures 3A and 3B. [Figure 7A] These are cross-sectional views of the semiconductor memory element of the first example (1a) cut along the line I-I' in Figures 3A and 3B. [Figure 7B] This is a cross-sectional view of the semiconductor memory element of the first example (1a) cut along the line II-II' in Figures 3A and 3B. [Figure 8] This is a cross-sectional view illustrating a method for manufacturing a semiconductor memory element of the first example according to one embodiment of the present invention, and is a cross-sectional view taken along the position corresponding to the line I-I' in Figure 3A. [Figure 9A] This is a cross-sectional view illustrating a method for manufacturing a semiconductor memory element of the first example according to one embodiment of the present invention, and is a cross-sectional view taken along the position corresponding to the line I-I' in Figures 3A and 3B. [Figure 9B] This is a cross-sectional view illustrating a method for manufacturing a semiconductor memory element of the first example according to one embodiment of the present invention, and is a cross-sectional view taken along the line II-II' in Figures 3A and 3B. [Figure 10] This is a cross-sectional view illustrating a method for manufacturing a semiconductor memory element of the first example according to one embodiment of the present invention, and is a cross-sectional view taken along the line II-II' in Figures 3A and 3B. [Figure 11A] This is a cross-sectional view illustrating a method for manufacturing a semiconductor memory element of the first example according to one embodiment of the present invention, and is a cross-sectional view taken along the position corresponding to the line I-I' in Figures 3A and 3B. [Figure 11B]A cross-sectional view illustrating a method of manufacturing a semiconductor memory device of Example 1a according to an embodiment of the present invention, which is a cross-sectional view taken along a position corresponding to line II-II' in FIGS. 3A and 3B. [Figure 12A] A cross-sectional view illustrating a method of manufacturing a semiconductor memory device of Example 1a according to an embodiment of the present invention, which is a cross-sectional view taken along a position corresponding to line I-I' in FIGS. 3A and 3B. [Figure 12B] A cross-sectional view illustrating a method of manufacturing a semiconductor memory device of Example 1a according to an embodiment of the present invention, which is a cross-sectional view taken along a position corresponding to line II-II' in FIGS. 3A and 3B. [Figure 13] A cross-sectional view of a semiconductor memory device of Example 1b taken along a position corresponding to line I-I' in FIGS. 3A and 3B. [Figure 14] A cross-sectional view taken along a position corresponding to line I-I' in FIGS. 3A and 3B for explaining a method of manufacturing a semiconductor memory device of Example 1b according to an embodiment of the present invention. [Figure 15] A cross-sectional view taken along a position corresponding to line I-I' in FIGS. 3A and 3B for explaining a method of manufacturing a semiconductor memory device of Example 1b according to an embodiment of the present invention. [Figure 16] A cross-sectional view taken along a position corresponding to line I-I' in FIGS. 3A and 3B for explaining a method of manufacturing a semiconductor memory device of Example 1b according to an embodiment of the present invention. [Figure 17] A cross-sectional view taken along a position corresponding to line I-I' in FIGS. 3A and 3B for explaining a method of manufacturing a semiconductor memory device of Example 1b according to an embodiment of the present invention. [Figure 18] A cross-sectional view taken along a position corresponding to line I-I' in FIGS. 3A and 3B for explaining a method of manufacturing a semiconductor memory device of Example 1b according to an embodiment of the present invention. [Figure 19A] A plan view of a semiconductor memory device of Example 3 according to an embodiment of the present invention as viewed from above downward. [Figure 19B]This is a plan view of a third example of a semiconductor memory element according to one embodiment of the present invention, viewed from below and above. [Figure 19C] These are cross-sectional views of a third example of a semiconductor memory element, cut along the line IV-IV' in Figures 19A and 19B. [Figure 19D] These are cross-sectional views of a third example of a semiconductor memory element, cut along the V-V' line in Figures 19A and 19B. [Figure 19E] These are cross-sectional views of a third example of a semiconductor memory element, cut along the line VI-VI' in Figures 19A and 19B. [Figure 20A] These are cross-sectional views of the semiconductor memory element of example 2a, cut along the line corresponding to IV-IV' in Figures 19A and 19B. [Figure 20B] These are cross-sectional views of the semiconductor memory element of the second example (2a) cut along the position corresponding to the V-V' line in Figures 19A and 19B. [Figure 21] This is a cross-sectional view taken along the line IV-IV' in Figures 20A and 20B, illustrating a method for manufacturing a semiconductor memory element of a second example according to one embodiment of the present invention. [Figure 22] This is a cross-sectional view taken along the line IV-IV' in Figures 20A and 20B, illustrating a method for manufacturing a semiconductor memory element of a second example according to one embodiment of the present invention. [Figure 23] This is a cross-sectional view taken along the line IV-IV' in Figures 20A and 20B, illustrating a method for manufacturing a semiconductor memory element of a second example according to one embodiment of the present invention. [Figure 24] This is a cross-sectional view taken along the line IV-IV' in Figures 20A and 20B, illustrating a method for manufacturing a semiconductor memory element of a second example according to one embodiment of the present invention. [Figure 25] This is a cross-sectional view taken along the line IV-IV' in Figures 20A and 20B, illustrating a method for manufacturing a semiconductor memory element of a second example according to one embodiment of the present invention. [Figure 26]This is a cross-sectional view of a semiconductor memory element of the second example (2b) shown in Figures 19A and 19B, taken along the line IV-IV' in the diagram. [Figure 27A] This is a cross-sectional view of a fourth example of a semiconductor memory element, cut along the portion including the position corresponding to the line I-I' in Figures 3A and 3B. [Figure 27B] This is a cross-sectional view showing a fourth example of a semiconductor memory element, cut along the portion including the position corresponding to the line II-II' in Figures 3A and 3B. [Figure 28] This is an equivalent circuit diagram showing another example of a memory cell array of a semiconductor memory element according to one embodiment of the present invention. [Modes for carrying out the invention]

[0009] Hereinafter, specific examples of embodiments for carrying out the present invention will be described in detail with reference to the drawings.

[0010] Figure 1 is an equivalent circuit diagram showing an example of a memory cell array of semiconductor memory element 1 according to one embodiment of the present invention.

[0011] Referring to Figure 1, the memory cell array of the semiconductor memory element 1 according to one embodiment of the present invention includes a plurality of subcell arrays SCA. The subcell array SCA includes a plurality of bit lines BL, a plurality of word lines WL, and a plurality of memory cells MC. Each of the plurality of memory cells MC includes a cell transistor CT and an information storage element SP. One cell transistor CT is placed between one word line WL and one bit line BL. The information storage element SP is a memory element capable of storing data.

[0012] Word lines WL are conductive patterns (e.g., metal lines) that are separated from the substrate and placed on the substrate. Multiple word lines WL extend in the first horizontal direction (X direction). Word lines WL within a single subcell array SCA are separated from each other in the vertical direction (Z direction). Bit lines BL extend vertically from the substrate (Z direction). Bit lines BL within a single subcell array SCA are separated from each other in the first horizontal direction (X direction).

[0013] In the memory cell array of semiconductor memory element 1, multiple word lines WL extend in the first horizontal direction (X direction) and are separated from each other in the second horizontal direction (Y direction) and the vertical direction (Z direction). In the memory cell array of semiconductor memory element 1, multiple bit lines BL extend in the vertical direction (Z direction) and are separated from each other in the first horizontal direction (X direction) and the second horizontal direction (Y direction). Multiple subcell arrays SCA are arranged along the second horizontal direction (Y direction). The second horizontal direction (Y direction) is orthogonal to the first horizontal direction (X direction).

[0014] In one embodiment, the information storage element SP is a memory element using a capacitor, a memory element using a magnetic tunnel junction pattern, or a memory element using a variable low antibody containing a phase change material. For example, the memory cell MC is a DRAM (dynamic random-access memory) cell, and the information storage element SP is a capacitor. In another embodiment, the information storage element SP is a transistor that can store data together with a cell transistor CT. For example, the memory cell MC is a 2T-0C (two-transistor zero-capacitor) DRAM cell. When the memory cell MC is a 2T-0C DRAM cell, the multiple word lines WL are part of a plurality of first conductive lines that extend in the first horizontal direction (X direction) and are separated from each other in the second horizontal direction (Y direction) and the vertical direction (Z direction), respectively, and the multiple bit lines BL are part of a plurality of second conductive lines that extend in the vertical direction (Z direction) and are separated from each other in the first horizontal direction (X direction) and the second horizontal direction (Y direction), respectively. The word line WL is referred to as the first conductive line, and the bit line BL is referred to as the second conductive line.

[0015] The gate of the cell transistor CT is connected to the word line WL, and the source region of the cell transistor CT is connected to the bit line BL. An information storage element SP is connected to the drain region of the cell transistor CT. In one embodiment, the information storage element SP is a capacitor including a first electrode, a second electrode, and a capacitor dielectric film interposed between the first electrode and the second electrode, the first electrode of the capacitor is connected to the drain region of the cell transistor CT, and the second electrode of the capacitor is connected to the ground wiring PP.

[0016] The memory cell array of the semiconductor memory element 1 includes a plurality of memory cells MC arranged in rows and columns, spaced apart from each other in the first horizontal direction (X direction) and the vertical direction (Z direction), and a plurality of subcell arrays SCA each containing a plurality of bit lines BL connected to the cell transistors CT of the memory cells MC arranged along the vertical direction (Z direction), extending vertically (Z direction) and spaced apart from each other along the first horizontal direction (X direction), and a plurality of word lines WL extending first horizontally (X direction) and spaced apart from each other along the vertical direction (Z direction). The plurality of subcell arrays SCA are arranged along the second horizontal direction (Y direction). The semiconductor memory element 1 includes a plurality of memory cell arrays.

[0017] The first horizontal direction (X direction), the second horizontal direction (Y direction), and the vertical direction (Z direction) are referred to as the first direction, the second direction, and the third direction, respectively. Alternatively, the first horizontal direction (X direction), the vertical direction (Z direction), and the second horizontal direction (Y direction) may be referred to as the first direction, the second direction, and the third direction, respectively. The first direction, the second direction, and the third direction are orthogonal to each other.

[0018] Two adjacent subcell arrays SCA in the second horizontal direction (Y direction) share a bit line BL. The source regions of the cell transistors CT contained in each of the two subcell arrays SCA are connected to the bit line BL shared by the two subcell arrays SCA. From each of the bit lines BL shared by the two subcell arrays SCA, the source and drain regions of the cell transistors CT of each of the two subcell arrays SCA, as well as the information storage elements SP, are arranged along directions opposite to each other. One bit line BL shared by the two subcell arrays SCA is connected to the cell transistor CT of one of the two subcell arrays SCA and the cell transistor CT of the other subcell array SCA. For example, the source region of the cell transistor CT, the drain region of the cell transistor CT, and the information storage element SP of one subcell array SCA are arranged sequentially along the second horizontal direction (Y direction), while the source region of the cell transistor CT, the drain region of the cell transistor CT, and the information storage element SP of another subcell array SCA are arranged sequentially along the opposite direction of the second horizontal direction (Y direction). For example, between a pair of bit lines BL of multiple bit lines BL that are arranged sequentially adjacent to each other along the second horizontal direction (Y direction), two memory cells MC are arranged along the second horizontal direction (Y direction) at the same vertical level.

[0019] Figure 2 is a block diagram illustrating an example of a semiconductor memory element 1000 according to one embodiment of the present invention.

[0020] Referring to Figure 2, the semiconductor memory element 1000 comprises a memory cell array 1010 including DRAM cells, which are memory cells, and various circuit blocks for driving the DRAM cells. For example, the timing register 1020 is activated when the chip selection signal CS changes from an inactivation level (e.g., logic high) to an activation level (e.g., logic low). The timing register 1020 receives command signals from an external source, such as the clock signal CLK, clock enable signal CKE, chip selection signal CSB ("B" indicates low-active; the same applies hereafter), row address strobe signal RASB, column address strobe signal CASB, write enable signal WEB, and data input / output mask signal DQM. It processes the received command signals and generates various internal command signals to control the circuit block, including LCKE (low-power clock enable), LRAS (low-active row address strobe), LCBR (low-active CVR (Channel Validity Refresh) refresh), LWE (low-active write enable), LCAS (low-active column address strobe), LWCBR (low-active write CAS before RAS), and LDQM (low-active data input / output mask).

[0021] Some internal command signals generated from the timing register 1020 are stored in the programming register 1040. For example, latency information and burst length information related to data output are stored in the programming register 1040. The internal command signals stored in the programming register 1040 are provided to the latency / burst length control unit 1060, which then provides control signals for controlling the latency and burst length of data output to the column decoder 1100 via the column address buffer 1080 or to the output buffer 1120.

[0022] The address register 1200 receives a clock signal CLK and an address signal ADD from an external source. The row address signal is provided to the row decoder 1240 via the row address buffer 1220. The column address signal is provided to the column decoder 1100 via the column address buffer 1080. The row address buffer 1220 further receives a refresh address signal generated by the refresh counter in response to refresh instructions (LRAS and LCBR) and provides either the row address signal or the refresh address signal to the row decoder 1240. The address register 1200 also provides a bank signal to the bank selection unit 1260 for selecting a bank.

[0023] The row decoder 1240 decodes the row address signal or refresh address signal input from the row address buffer 1220. The row decoder 1240 includes a plurality of subword line drivers (SWDs) 1250. The subword line drivers 1250 activate the word line WL of the memory cell array 1010. The subword line drivers 1250 are arranged in a block-like manner at predetermined intervals within the row decoder 1240 adjacent to the memory cell array 1010. For example, the subword line drivers 1250 are arranged adjacent to one end of the memory cell array 1010 perpendicular to the sensing amplifier 1300.

[0024] The column decoder 1100 decodes the column address signal and performs a selection operation on the bit line BL of the memory cell array 1010. For example, a column selection line is applied to the semiconductor memory element 1000, and the selection operation is performed via the column selection line.

[0025] The sensing amplifier 1300 amplifies the data of the memory cells selected by the row decoder 1240 and column decoder 1100, and provides the amplified data to the output buffer 1120. Data for recording the data cells is provided to the memory cell array 1010 via the data input register 1320, and the input / output controller 1340 controls the data transfer operation via the data input register 1320. The output buffer 1120 outputs the output data DQi.

[0026] Figures 3A to 3E are plan and cross-sectional views of a first example semiconductor memory element 100 according to one embodiment of the present invention. Specifically, Figure 3A is a plan view of the first example semiconductor memory element 100 according to one embodiment of the present invention, viewed from above to below; Figure 3B is a plan view of the first example semiconductor memory element 100 according to one embodiment of the present invention, viewed from below to above; Figure 3C is a cross-sectional view of the first example semiconductor memory element 100 cut along the line I-I' in Figures 3A and 3B; Figure 3D is a cross-sectional view of the first example semiconductor memory element 100 cut along the line II-II' in Figures 3A and 3B; and Figure 3E is a cross-sectional view of the first example semiconductor memory element 100 cut along the line III-III' in Figures 3A and 3B.

[0027] Referring to Figures 3A to 3E, the semiconductor memory element 100 includes a plurality of word lines WL extending in a first horizontal direction (X direction) and separated from each other in a second horizontal direction (Y direction) and a vertical direction (Z direction). The second horizontal direction (Y direction) is orthogonal to the first horizontal direction (X direction). The plurality of word lines WL include a plurality of first word lines WLA and a plurality of second word lines WLB. The plurality of word lines WL constitute a word line stack WST. The word line stack WST includes a first word line stack WSA and a second word line stack WSB that overlap each other in the vertical direction (Z direction). For example, the second word line stack WSB is located on the first word line stack WSA. The first word line stack WSA includes a plurality of first word lines WLA from the plurality of word lines WL, and the second word line stack WSB includes a plurality of second word lines WLB from the plurality of word lines WL.

[0028] In this specification, the first wordline stack WSA and the second wordline stack WSB are referred to as the lower wordline stack and the upper wordline stack, respectively. Components relating to the first wordline stack WSA, such as those including or connected to the first wordline stack WSA, are referred to with the prefix "first" or "lower," and components relating to the second wordline stack WSB, such as those including or connected to the second wordline stack WSB, are referred to with the prefix "second" or "upper." For example, the first wordline WLA included in the first wordline stack WSA is also referred to as the lower wordline, and the second wordline WLB included in the second wordline stack WSB is also referred to as the upper wordline.

[0029] Among the multiple first word lines WLA included in the first word line stack WSA, the first word line WLA aligned vertically (Z direction) has a stepped structure in which the length extending along the first horizontal direction (X direction) increases as you move from bottom to top in the vertical direction (Z direction). Among the second word lines WLB, the second word line WLB aligned vertically (Z direction) has a stepped structure in which the length extending along the first horizontal direction (X direction) decreases as you move from bottom to top in the vertical direction (Z direction). That is, among the multiple word lines WL, the word line WL aligned vertically (Z direction) has a length extending along the first horizontal direction (X direction) that increases as you move from bottom to top or from top to bottom, and then decreases after reaching its maximum length. The stepped structure of the first word line stack WSA and the stepped structure of the second word line stack WSB are mirror-image symmetric along the vertical direction (Z direction).

[0030] Figure 3C shows a configuration where the uppermost first word line WLA and the lowermost second word line WLB, aligned vertically (Z-direction), have the same length extending in the first horizontal direction (X-direction), but the configuration is not limited to this. For example, the uppermost first word line WLA, aligned vertically (Z-direction), may have a longer length extending in the first horizontal direction (X-direction) than the lowermost second word line WLB. Alternatively, for example, the uppermost first word line WLA, aligned vertically (Z-direction), may have a shorter length extending in the first horizontal direction (X-direction) than the lowermost second word line WLB.

[0031] A first word line WLA located on the same vertical level among a plurality of first word lines WLAs and spaced apart along the second horizontal direction (Y direction) has a similar length extending in the first horizontal direction (X direction), but is not limited to this. For example, as long as the length of a first word line WLA aligned vertically (Z direction) among a plurality of first word lines WLAs increases along the first horizontal direction (X direction) as it moves from bottom to top in the vertical direction (Z direction), the extending lengths of first word lines WLA located on the same vertical level may be the same or different. A second word line WLB located on the same vertical level among a plurality of second word lines WLBs and spaced apart along the second horizontal direction (Y direction) has a similar length extending in the first horizontal direction (X direction), but is not limited to this. For example, as long as the length of a second word line WLB aligned vertically (Z-direction) decreases as it moves vertically (Z-direction) from bottom to top, the lengths of second word lines WLBs located at the same vertical level may or may not be the same.

[0032] The semiconductor memory element 100 has a memory cell region MCR and a pad region WPR arranged along a first horizontal direction (X direction). A plurality of word lines WL include a plurality of word line pad portions WLP located in the pad region WPR. Each of the plurality of word line pad portions WLP means a portion of each of the plurality of word lines WL that does not overlap with the upper or lower word line WL at the end in the first horizontal direction (X direction). Figures 3A to 3C show, but are not limited to, a plurality of word lines WL including a plurality of word line pad portions WLP located at one end in the first horizontal direction (X direction). In one embodiment, each of the plurality of word lines WL includes a word line pad portion WLP at one end in the first horizontal direction (X direction), and each of the other parts includes a word line pad portion WLP at the other end in the first horizontal direction (X direction). For example, in Figure 3C, for a word line WL among multiple word lines WL, if the word line pad WLP is not located at one end in the first horizontal direction (X direction) superimposed on both the upper and lower word line WLs, then the word line pad WLP is located at the other end in the first horizontal direction (X direction).

[0033] Multiple wordline pad sections (WLP) include multiple first wordline pad sections (WLPA) contained within multiple first wordline sections (WLA), and multiple second wordline pad sections (WLPB) contained within multiple second wordline sections (WLB). A first wordline pad section (WLPA) refers to the portion of each of the multiple first wordline sections (WLA) at its first horizontal (X-direction) end that does not overlap with the other first wordline section (WLA) below it, and a second wordline pad section (WLPB) refers to the portion of each of the multiple second wordline sections (WLB) at its first horizontal (X-direction) end that does not overlap with the other second wordline section (WLB) above it.

[0034] In one embodiment, each of the multiple word lines WL has a horizontal width that increases in the second horizontal direction (Y direction) as it moves from the portion located in the memory cell area MCR to the portion located in the pad area WPR. For example, the word line pad portion WLP has a horizontal width that increases in the second horizontal direction (Y direction) as it moves from the portion of the word line WL located in the memory cell area MCR to the portion located in the second horizontal direction (Y direction). In another embodiment, each of the multiple word lines WL may have the same horizontal width in the second horizontal direction (Y direction) in both the memory cell area MCR and the pad area WPR. For example, the word line pad portion WLP and the portion of the word line WL located in the memory cell area MCR have the same horizontal width in the second horizontal direction (Y direction).

[0035] Multiple wordline pad sections (WLP) are connected to multiple wordline contact sections (WLC). Each wordline contact section (WLC) includes multiple first wordline contact sections (WLCA) and multiple second wordline contact sections (WLCB). The first wordline contact section (WLCA) is connected to the lower surface of the first wordline pad section (WLPA) and extends downward from the connected first wordline pad section (WLPA). The second wordline contact section (WLCB) is connected to the upper surface of the second wordline pad section (WLPB) and extends upward from the connected second wordline pad section (WLPB). Each of the multiple first wordline contact sections (WLCA) has a tapered shape, with its horizontal width increasing as it extends from top to bottom. For example, each of the multiple first wordline contact sections (WLCA) has a tapered shape, with its horizontal width increasing as it moves away from the connected first wordline pad section (WLPA). Each of the multiple second wordline contact sections (WLCB) has a tapered shape, with its horizontal width increasing as it extends from bottom to top. For example, each of the multiple second word line contacts WLCB has a tapered shape that widens horizontally as it moves away from the connected second word line pad portion WLPB.

[0036] Multiple word lines (WLs) are electrically connected to multiple routing pads (WRPs) via multiple word line contacts (WLCs). The multiple routing pads (WRPs) include multiple first routing pads (WRPAs) electrically connected to multiple first word lines (WLAs), and multiple second routing pads (WRPBs) electrically connected to multiple second word lines (WLBs). The first routing pads (WRPAs) and second routing pads (WRPBs) are located at the same vertical level.

[0037] The first word line contact WLCA connects the first word line pad WLPA and the first routing pad WRPA of the first word line WLA. For example, the upper end of the first word line contact WLCA is connected to the first word line pad WLPA of the first word line WLA, and the lower end is connected to the first routing pad WRPA. The second word line contact WLCB connects the second word line pad WLPB of the second word line WLB and the word line routing line WLRL. For example, the upper end of the second word line contact WLCB is connected to the word line routing line WLRL, and the lower end is connected to the second word line pad WLPB of the second word line WLB. A word line routing via WLRV is formed between the word line routing line WLRL and the second routing pad WRPB. For example, the upper end of the word line routing via WLRV is connected to the word line routing line WLRL, and the lower end is connected to the second routing pad WRPB. The second word line pad portion WLPB of the second word line WLB is electrically connected to the second routing pad WRPB via the second word line contact WLCB, the word line routing line WLRL, and the word line routing via WLRV.

[0038] Each of the multiple wordline routing vias WLRV has a tapered shape that narrows horizontally from top to bottom. For example, multiple wordline routing vias WLRV have a tapered shape that narrows horizontally towards multiple second routing pads WRPB. In one embodiment, the horizontal width of the uppermost end of each of the multiple wordline routing vias WLRV is the same as or greater than the horizontal width of each of the multiple second wordline contacts WLCB.

[0039] Multiple word line contacts (WLCs) and multiple word line routing vias (WLRVs) are arranged in a matrix-like configuration, with each row aligned in a planar direction along the first horizontal direction (X direction) and the second horizontal direction (Y direction). For example, word line contacts (WLCs) may be arranged in a row along the first horizontal direction (X direction), and word line routing vias (WLRVs) may be arranged in a row along the second horizontal direction (Y direction), with word line contacts (WLCs) and word line routing vias (WLRVs) alternating and aligned in a row. Multiple word line routing lines (WLRLs) connecting the upper ends of multiple second word line contacts (WLCBs) and the upper ends of multiple word line routing vias (WLRVs) have a horizontal shape as linear bars extending along the second horizontal direction (Y direction).

[0040] Multiple bit lines BL extend vertically (Z direction) and are spaced apart from each other in the first horizontal direction (X direction) and the second horizontal direction (Y direction). Multiple bit lines BL include bit line rows, which are bit lines BL arranged in a row spaced apart from each other along the first horizontal direction (X direction), and the bit line rows are spaced apart from each other along the second horizontal direction (Y direction). Each bit line row is positioned along an extension line that extends in the first horizontal direction (X direction) between two adjacent word line pads WLP at the same vertical level in the second horizontal direction (Y direction). In one embodiment, a bit line row and a pair of word lines WL are repeatedly arranged in a planar manner along the second horizontal direction (Y direction).

[0041] Multiple bit lines BL include multiple first bit lines BLA and multiple second bit lines BLB. Multiple first bit lines BLA extend vertically (in the Z direction) between multiple first word lines WLA, and multiple second bit lines BLB extend vertically (in the Z direction) between multiple second word lines WLB. In one embodiment, the first bit lines BLA and second bit lines BLB aligned vertically (in the Z direction) are spaced apart from each other. For example, the uppermost end of the first bit line BLA and the lowermost end of the second bit line BLB are spaced apart from each other vertically (in the Z direction). Each of the multiple first bit lines BLA has a tapered shape that narrows horizontally from bottom to top. For example, multiple first bit lines BLA have a tapered shape that narrows horizontally towards multiple second bit lines BLB superimposed vertically (in the Z direction). Each of the multiple second bit lines BLB has a tapered shape that extends from top to bottom with its horizontal width narrowing. For example, multiple second bit lines BLB have a tapered shape that extends toward multiple first bit lines BLA superimposed in the vertical direction (Z direction) with its horizontal width narrowing.

[0042] The semiconductor memory element 100 includes a plurality of memory cells MC, each containing a cell transistor CT and an information storage element SP. The cell transistor CT includes a semiconductor pattern 110. In one embodiment, the semiconductor pattern 110 extends in a second horizontal direction (Y direction). The cell transistor CT includes a semiconductor pattern 110 with source regions and drain regions located at both ends in the second horizontal direction (Y direction). The cell transistor CT is positioned between a word line WL and a bit line BL. The information storage element SP is connected to the cell transistor CT. The information storage element SP is a memory element capable of storing data. The gate of the cell transistor CT is connected to the word line WL, and the source region of the cell transistor CT is connected to the bit line BL. The information storage element SP is connected to the drain region of the cell transistor CT.

[0043] The word line WL is adjacent to the semiconductor pattern 110. In one embodiment, the word line WL surrounds the semiconductor pattern 110. A gate dielectric film Gox is interposed between the word line WL and the semiconductor pattern 110. The word line WL and the gate dielectric film Gox constitute a word line structure WLS. The semiconductor pattern 110 and the word line structure WLS constitute a cell transistor CT. The plurality of semiconductor patterns 110 include a plurality of first semiconductor patterns 110A and a plurality of second semiconductor patterns 110B. The first semiconductor pattern 110A is adjacent to the first word line WLA, and the second semiconductor pattern 110B is adjacent to the second word line WLB. The plurality of gate dielectric films Gox include a plurality of first gate dielectric films GoxA and a plurality of second gate dielectric films GoxB. A first gate dielectric film GoxA is interposed between the first word line WLA and the first semiconductor pattern 110A, and a second gate dielectric film GoxB is interposed between the second word line WLB and the second semiconductor pattern 110B. Multiple word line structures WLS include multiple first word line structures WLSA and multiple second word line structures WLSB. The first word line WLA and the first gate dielectric film GoxA constitute the first word line structure WLSA, and the second word line WLB and the second gate dielectric film GoxB constitute the second word line structure WLSB.

[0044] In one embodiment, the source region and drain region of a cell transistor CT, as well as the information storage element SP, are arranged along the second horizontal direction (Y direction) from the bit line BL connected to the source region of the cell transistor CT. The source region and drain region of a cell transistor CT and the information storage element SP connected to one of two adjacent bit line BLs in the second horizontal direction (Y direction) are arranged sequentially along opposite directions from the source region and drain region of a cell transistor CT and the information storage element SP connected to the other bit line BL. For example, the source region and drain region of a cell transistor CT and the information storage element SP connected to one of two adjacent bit line BLs in the second horizontal direction (Y direction) are arranged sequentially along the second horizontal direction (Y direction), while the source region and drain region of a cell transistor CT and the information storage element SP connected to the other bit line BL are arranged along the opposite direction of the second horizontal direction (Y direction). For example, multiple bit lines BL include a first bit line, a second bit line, a third bit line, and a fourth bit line that are sequentially adjacent to each other along a second horizontal direction (Y direction), with no memory cell MC between the first bit line and the second bit line, two memory cell MCs arranged at the same vertical level along the second horizontal direction (Y direction) between the second bit line and the third bit line, and no memory cell MC between the third bit line and the fourth bit line.

[0045] Multiple bit line contacts BLC are connected to one end of multiple bit line BLs. Multiple bit line contacts BLCs include multiple first bit line contacts BCAs and multiple second bit line contacts BCBs. The first bit line contacts BCAs are connected to one end of the first bit line BLA opposite the second bit line BLB. For example, the first bit line contact BCA is connected to the lower end of the first bit line BLA. The second bit line contacts BCBs are connected to one end of the second bit line BLB opposite the first bit line BLA. For example, the second bit line contact BCB is connected to the upper end of the second bit line BLB. Multiple bit line connection patterns BLP are connected to multiple bit line contacts BLCs. Multiple bit line connection patterns BLPs include multiple first bit line connection patterns BPAs and multiple second bit line connection patterns BPBs. A first bit line connection pattern BPA is connected to the lower end of the first bit line contact BCA, and a second bit line connection pattern BPB is connected to the upper end of the second bit line contact BCB. In one embodiment, the first bit line connection pattern BPA is located at the same vertical level as the first routing pad WRPA and the second routing pad WRPB, and the second bit line connection pattern BPB is located at the same vertical level as the word line routing line WLRL.

[0046] Multiple insulating layers 150 are interposed between word lines WL aligned along the vertical direction (Z direction). The insulating layer 150 interposed between the uppermost first word line WLA and the lowermost second word line WLB is referred to as the intermediate insulating layer 150M. Each of the intermediate insulating layers 150M is made of the same material as each of the remaining insulating layers 150 excluding the intermediate insulating layer 150M. For example, the multiple insulating layers 150 are made of oxides, but are not limited to this. The thickness of each of the intermediate insulating layers 150M is the same as or greater than the thickness of each of the remaining insulating layers 150 excluding the intermediate insulating layer 150M.

[0047] The interlayer insulating layer ILD surrounds multiple word lines WL, multiple word line contacts WLC, multiple bit lines BL, and multiple word line routing vias WLRV. The word line routing vias WLRV extend from the word line routing line WLRL to the second routing pad WRPB via the interlayer insulating layer ILD between adjacent word lines WL in the second horizontal direction (Y direction) in the pad region WPR, i.e., between the word line pad portion WLP. The interlayer insulating layer ILD is made of oxide, but is not limited to oxide. The interlayer insulating layer ILD is made of a single layer, but is not limited to oxide, and may have a multilayer structure. In one embodiment, multiple insulating layers 150 may be part of the interlayer insulating layer ILD. Figures 3C to 3E show, but are not limited to, a configuration in which the first bit line linking pattern BPA, the first routing pad WRPA, and the second routing pad WRPB are located below the lower surface of the interlayer insulating layer ILD, and the second bit line linking pattern BPB and the word line routing line WLRL are located above the upper surface of the interlayer insulating layer ILD. In one embodiment, Figures 3C to 3E show only a portion of the interlayer insulating layer ILD included in the semiconductor memory element 100. For example, the interlayer insulating layer ILD is formed to cover the first bit line concatenation pattern BPA, the first routing pad WRPA, the second routing pad WRPB, the second bit line concatenation pattern BPB, and the word line routing line WLRL.

[0048] In the semiconductor memory element 100 according to the present invention, multiple first word lines WLA included in the first word line stack WSA are connected to multiple first word line contacts WLCA extending downward from multiple first word line pads WLPA, and multiple second word lines WLB included in the second word line stack WSB are connected to multiple second word line contacts WLCB extending upward from multiple second word line pads WLPB. Furthermore, each of the multiple word line routing vias WLRV connecting the multiple second word line contacts WLCB and the multiple second routing pads WRPB is arranged between adjacent word line pads WLP in the second horizontal direction (Y direction), so no separate space is required to form the multiple word line routing vias WLRV. Therefore, the area in which the multiple word line pads WLP are arranged in a planar manner is reduced, and the integration density of the semiconductor memory element 100 can be increased.

[0049] Figures 4A, 4B, and 4C are perspective views showing various examples of memory cells (MCs) included in a semiconductor memory device according to one embodiment of the present invention.

[0050] Referring to Figure 4A, the memory cell MC includes a cell transistor CT and an information storage element SP. The cell transistor CT is positioned between the word line WL and the bit line BL. The cell transistor CT includes a semiconductor pattern 110. One end of the semiconductor pattern 110 is connected to the bit line BL, and the other end is connected to the information storage element SP. The word line WL extends in the first horizontal direction (X direction), the bit line BL extends in the vertical direction (Z direction), and the semiconductor pattern 110 extends in the second horizontal direction (Y direction). A gate dielectric film Gox, shown in Figure 3C, is interposed between the word line WL and the semiconductor pattern 110. In one embodiment, the semiconductor pattern 110 and the information storage element SP are positioned sequentially along the second horizontal direction (Y direction) from the bit line BL.

[0051] In one embodiment, the word line WL surrounds the semiconductor pattern 110. For example, the word line WL has a gate-all-around shape that covers the top surface, bottom surface, and both sides in the first horizontal direction (X direction) of a portion of the semiconductor pattern 110.

[0052] Referring to Figure 4B, the memory cell MC includes a cell transistor CT and an information storage element SP. The cell transistor CT is positioned between the word line WL and the bit line BL. The cell transistor CT includes a semiconductor pattern 110. A gate dielectric film Gox, shown in Figure 3C, is interposed between the word line WL and the semiconductor pattern 110.

[0053] The word line WL has a double gate shape that covers the upper and lower surfaces of a portion of the semiconductor pattern 110. In one embodiment, the word line WL includes a lower word line WLD located below the semiconductor pattern 110 and an upper word line WLU located above the semiconductor pattern 110. For example, the upper word line WLU covers the upper surface of a portion of the semiconductor pattern 110, and the lower word line WLD covers the lower surface of a portion of the semiconductor pattern 110.

[0054] Referring to Figure 4C, the memory cell MC includes a cell transistor CT and an information storage element SP. The cell transistor CT is positioned between the word line WL and the bit line BL. The cell transistor CT includes a semiconductor pattern 110. The gate dielectric film Gox shown in Figure 3C is interposed between the word line WL and the semiconductor pattern 110.

[0055] The word line WL has a single-gate shape that covers one of the upper and lower surfaces of a portion of the semiconductor pattern 110. For example, the word line WL covers the upper surface of a portion of the semiconductor pattern 110. In one embodiment, the word line WL may cover the lower surface of a portion of the semiconductor pattern 110.

[0056] In the following explanation, content that overlaps with Figures 3A to 3E and Figures 4A to 4C will be omitted.

[0057] Figures 5A and 5B are plan view diagrams showing a second example of a semiconductor memory element 100a according to one embodiment of the present invention. Specifically, Figure 5A is a plan view of the second example of a semiconductor memory element 100a according to one embodiment of the present invention, viewed from above to below, and Figure 5B is a plan view of the second example of a semiconductor memory element 100a according to one embodiment of the present invention, viewed from below to above.

[0058] Referring to both Figure 5A and Figure 5B, the semiconductor memory element 100a includes a plurality of word lines WL and a plurality of bit lines BL. The plurality of word lines WL include a plurality of word line pads WLP. The plurality of word lines WL include a plurality of first word lines WLA and a plurality of second word lines WLB. The plurality of word line pads WLP include a plurality of first word line pads WLPA contained within the plurality of first word lines WLA and a plurality of second word line pads WLPB contained within the plurality of second word lines WLB.

[0059] The first word line pad WLPA is connected to the first word line contact WLCA, and the second word line pad WLPB is connected to the second word line contact WLCB. A word line routing via WLRVa is placed between adjacent word lines WL in the second horizontal direction (Y direction) in the pad area WPR, i.e., between word line pads WLP. A word line routing line WLRLa is connected to both the second word line contact WLCB and the word line routing via WLRVa. The word line routing line WLRLa electrically connects the second word line contact WLCB and the word line routing via WLRVa.

[0060] Multiple word line contacts (WLCs) and multiple word line routing vias (WLRVa) are arranged in a honeycomb shape, arranged in a zigzag pattern along a first horizontal direction (X direction) or a second horizontal direction (Y direction) in a planar manner. For example, word line contacts (WLCs) may be arranged in a row along the first horizontal direction (X direction), and word line routing vias (WLRVa) may be arranged in a row, or word line contacts (WLCs) and word line routing vias (WLRVa) may be arranged alternately in a row along diagonal directions relative to the first horizontal direction (X direction) and the second horizontal direction (Y direction). Multiple word line routing lines (WLRLa) connecting the upper ends of multiple second word line contacts (WLCBs) and the upper ends of multiple word line routing vias (WLRVa) have a horizontal shape of linear bars extending along diagonal directions relative to the first horizontal direction (X direction) and the second horizontal direction (Y direction).

[0061] Since the semiconductor memory element 100a has multiple word line contacts (WLCs) and multiple word line routing vias (WLRVa) arranged in a honeycomb shape, the integration density of the semiconductor memory element 100a can be increased.

[0062] Figure 6 is a cross-sectional view showing a semiconductor memory element 100b of a second example modification according to one embodiment of the present invention. Specifically, Figure 6 is a cross-sectional view of the semiconductor memory element 100b of the second example modification, cut along the line II-II' in Figures 3A and 3B.

[0063] Referring to Figure 6, the semiconductor memory element 100b includes a plurality of bit lines BLa and a plurality of word line routing vias WLRV. The plurality of bit lines BLa include a plurality of first bit lines BLAa and a plurality of second bit lines BLBa. The plurality of first bit lines BLAa and the plurality of second bit lines BLBa extend along the vertical direction (Z direction). Each of the plurality of first bit lines BLAa has a tapered shape that extends from the bottom to the top with its horizontal width narrowing. Each of the plurality of second bit lines BLBa has a tapered shape that extends from the top to the bottom with its horizontal width narrowing.

[0064] Multiple bit line contacts BLC are connected to one end of multiple bit line BLa. Multiple bit line contacts BLC include multiple first bit line contacts BCA and multiple second bit line contacts BCB. The first bit line contact BCA is connected to one end of the first bit line BLAa opposite to the second bit line BLBa. For example, the first bit line contact BCA is connected to the lower end of the first bit line BLAa. The second bit line contact BCB is connected to one end of the second bit line BLBa opposite to the first bit line BLAa. For example, the second bit line contact BCB is connected to the upper end of the second bit line BLBa. In one embodiment, the first bit line BLAa and the second bit line BLBa, aligned vertically (Z direction), are in contact with each other. For example, the other end of the first bit line BLAa, i.e., the upper end, and the other end of the second bit line BLBa, i.e., the lower end, are in contact with each other.

[0065] Multiple bit line contacts BLC are connected to multiple bit line linkage patterns BLP. Each bit line linkage pattern BLP includes multiple first bit line linkage patterns BPA and multiple second bit line linkage patterns BPB. The lower end of the first bit line contact BCA is connected to the first bit line linkage pattern BPA, and the upper end of the second bit line contact BCB is connected to the second bit line linkage pattern BPB.

[0066] Figures 7A and 7B are cross-sectional views showing a semiconductor memory element 1a of a first example according to one embodiment of the present invention. Specifically, Figure 7A is a cross-sectional view of the semiconductor memory element 1a of the first example cut along the line I-I' in Figures 3A and 3B, and Figure 7B is a cross-sectional view of the semiconductor memory element 1a of the first example cut along the line II-II' in Figures 3A and 3B.

[0067] Referring to both Figures 7A and 7B, the semiconductor memory element 1a has a memory cell region MCR, a pad region WPR, and an external linkage region PDR arranged along a first horizontal direction (X direction). The semiconductor memory element 1a includes a peripheral circuit structure PRST, a memory cell structure MCST on the peripheral circuit structure PRST, and a pad structure PDST on the memory cell structure MCST. The peripheral circuit structure PRST, the memory cell structure MCST, and the pad structure PDST are each arbitrary divisions based on convenience of explanation and functional differences, and the divisions between each structure are not clear.

[0068] The peripheral circuit structure PRST includes a peripheral circuit board PSUB and a plurality of peripheral circuit transistors PTR. The plurality of peripheral circuit transistors PTR are arranged on the upper surface of the portion of the peripheral circuit board PSUB that is limited by the peripheral circuit element isolation film PSTI. The plurality of peripheral circuit transistors PTR are configured to transmit signals and / or power to a plurality of memory cells contained in the memory cell structure MCST. For example, the plurality of peripheral circuit transistors PTR constitute a variety of circuits such as command decoders, control logic, address buffers, row decoders, column decoders, sense amplifiers, and data input / output circuits. Figures 7A and 7B show the peripheral circuit transistors PTR as planar transistors, but are not limited to this. For example, the peripheral circuit transistors PTR are FinFETs (fin field-effect transistors) or vertical gate transistors. The plurality of peripheral circuit transistors PTR are arranged on the upper surface of the peripheral circuit board PSUB facing the memory cell structure MCST. The upper surface of the peripheral circuit board PSUB is the active surface of the peripheral circuit board PSUB. For example, the semiconductor memory element 1a has a CoP (Cell on Peripheral)-face structure in which a memory cell structure MCST is arranged on a peripheral circuit structure PRST, and the active surface of the peripheral circuit substrate PSUB and a plurality of peripheral circuit transistors PTR face the memory cell structure MCST.

[0069] The peripheral circuit structure PRST includes a plurality of peripheral circuit linkage patterns PMP on the peripheral circuit substrate PSUB, a plurality of peripheral circuit linkage vias PMV connected to the plurality of peripheral circuit linkage patterns PMP, and a peripheral circuit wiring insulation layer IMD that covers the peripheral circuit substrate PSUB while enclosing the plurality of peripheral circuit linkage patterns PMP and the plurality of peripheral circuit linkage vias PMV. If the plurality of peripheral circuit linkage patterns PMP are embedded within the peripheral circuit wiring insulation layer IMD, the peripheral circuit structure PRST further includes a peripheral circuit wiring protection layer IMP that covers the plurality of peripheral circuit linkage patterns PMP and the peripheral circuit wiring insulation layer IMD. The peripheral circuit wiring insulation layer IMD contains an oxide, and the peripheral circuit wiring protection layer IMP contains a nitride. The peripheral circuit linkage via PMV located at the bottom end of the plurality of peripheral circuit linkage vias PMV is connected to the peripheral circuit substrate PSUB and / or a plurality of peripheral circuit transistors PTR.

[0070] The peripheral circuit structure PRST further includes a peripheral circuit bonding pad BDPP placed on the peripheral circuit wiring insulation layer IMD, a peripheral circuit bonding insulation layer BDPD surrounding the peripheral circuit bonding pad BDPP, and peripheral circuit bonding vias BDPV connecting the peripheral circuit bonding pad BDPP and the peripheral circuit connection pattern PMP. The peripheral circuit bonding vias BDPV penetrate the peripheral circuit wiring insulation layer IMD and / or the peripheral circuit wiring protection layer IMP to connect the peripheral circuit bonding pad BDPP and the peripheral circuit connection pattern PMP. The upper surface of the peripheral circuit bonding pad BDPP and the upper surface of the peripheral circuit bonding insulation layer BDPD are coplanar.

[0071] The memory cell structure MCST includes multiple word lines WL, multiple bit lines BL, multiple word line contacts WLC, multiple word line routing lines WLRL, multiple word line routing vias WLRV, multiple bit line contacts BLC, multiple bit line concatenation patterns BLP, and multiple routing pads WRP that constitute the word line stack WST.

[0072] Beneath the multiple bit line coupling patterns BLP and multiple routing pads WRP are multiple cell coupling patterns CIP and multiple cell coupling contacts CIC that connect the multiple bit line coupling patterns BLP and / or the multiple routing pads WRP to the multiple cell coupling patterns CIP. The interlayer insulating layer ILD encloses the multiple cell coupling patterns CIP and the multiple cell coupling contacts CIC.

[0073] The memory cell structure MCST further includes a cell bonding pad BDCP located beneath the interlayer insulating layer ILD, a cell bonding insulating layer BDCD surrounding the cell bonding pad BDCP, and a cell bonding via BDCV connecting the cell bonding pad BDCP to the bit line coupling pattern BLP. The cell bonding via BDCV penetrates the interlayer insulating layer ILD and connects the cell bonding pad BDCP to the cell coupling pattern CIP. The lower surface of the cell bonding pad BDCP and the lower surface of the cell bonding insulating layer BDCD are coplanar.

[0074] The memory cell structure MCST is bonded to the peripheral circuit structure PRST via the cell bonding pad BDCP and peripheral circuit bonding pad BDPP, as well as the cell bonding insulating layer BDCD and peripheral circuit bonding insulating layer BDPD. For example, the cell bonding insulating layer BDCD and the peripheral circuit bonding insulating layer BDPD are joined by covalent bonds, while the cell bonding pad BDCP and the peripheral circuit bonding pad BDPP are initially placed facing each other, then expanded by heat to come into contact with each other, and bonded by diffusion bonding so that they form a single unit through the diffusion of the metal atoms they contain. The memory cell structure MCST and the peripheral circuit structure PRST are joined to each other using a hybrid bonding method. The cell bonding pad BDCP and the peripheral circuit bonding pad BDPP are made of a material containing copper (Cu). The cell bonding insulating layer BDCD and the peripheral circuit bonding insulating layer BDPD contain silicon oxide or silicon carbonaceous material (SiCN).

[0075] The memory cell structure MCST further includes cell wiring contacts CMC extending vertically (Z-direction) through the interlayer insulating layer ILD. The cell wiring contacts CMC connect the lower cell-peripheral circuit coupling pad CPDA and the upper cell-peripheral circuit coupling pad CPDB. The cell wiring contacts CMC, the lower cell-peripheral circuit coupling pad CPDA, and the upper cell-peripheral circuit coupling pad CPDB are located in the external coupling region PDR. In one embodiment, the lower cell-peripheral circuit coupling pad CPDA is located at the same vertical level as the first routing pad WRPA and the second routing pad WRPB, and the upper cell-peripheral circuit coupling pad CPDB is located at the same vertical level as the word line routing line WLRL. The lower cell-peripheral circuit coupling pad CPDA is electrically coupled to the peripheral circuit structure PRST via one of a plurality of cell coupling contacts CIC.

[0076] In one embodiment, the cell wiring contact CMC and the word line routing via WLRV are formed integrally. For example, the upper and lower ends of the cell wiring contact CMC are located at the same vertical level as the upper and lower ends of the word line routing via WLRV. For example, the cell wiring contact CMC has a tapered shape that narrows horizontally from top to bottom.

[0077] The pad structure PDST includes an external linking pad EPD on the memory cell structure MCST, an external linking via EPV connecting the external linking pad EDP and the upper cell-peripheral circuit linking pad CPDB, and a cover insulating layer CDI enclosing the external linking pad EDP and the external linking via EPV. In one embodiment, the external linking via EPV is formed to extend into the interlayer insulating layer ILD of the memory cell structure MCST. In one embodiment, a protective insulating layer PSV is disposed on the cover insulating layer CDI. At least a portion of the upper surface of the external linking pad EPD is exposed and not covered by the protective insulating layer PSV. The cover insulating layer CDI contains an oxide, and the protective insulating layer PSV contains a nitride.

[0078] Figures 8, 9A and 9B, 10, 11A and 11B, and 12A and 12B are cross-sectional views illustrating a method for manufacturing a semiconductor memory element 1a of a first example according to one embodiment of the present invention. Specifically, Figures 8 and 10 are cross-sectional views cut along positions corresponding to the lines I-I' and II-II' in Figures 3A and 3B, Figures 9A, 11A, and 12A are cross-sectional views cut along positions corresponding to the lines I-I' in Figures 3A and 3B, and Figures 9B, 11B, and 12B are cross-sectional views cut along positions corresponding to the lines II-II' in Figures 3A and 3B.

[0079] Referring to Figure 8, a laminated structure MS is formed by alternately stacking multiple sacrificial layers 124 and multiple semiconductor layers 122 one by one on a base substrate BSUB. The base substrate BSUB contains a semiconductor material. Each of the multiple sacrificial layers 124 and multiple semiconductor layers 122 is made of a semiconductor material. The sacrificial layer 124 is made of a semiconductor material having an etching selectivity ratio with respect to the semiconductor layer 122. For example, the semiconductor layer 122 is made of Si, and the sacrificial layer 124 is made of SiGe or SiGeC.

[0080] The laminated structure MS includes a first laminated structure STA and a second laminated structure STB on the first laminated structure STA. The plurality of sacrificial layers 124 include an intermediate sacrificial layer 124M. The intermediate sacrificial layer 124M is a sacrificial layer 124 that is positioned between the first laminated structure STA and the second laminated structure STB among the plurality of sacrificial layers 124. In one embodiment, the types of elements contained in the materials that make up each of the plurality of sacrificial layers 124 are the same, but the proportion of elements contained in the material that makes up the intermediate sacrificial layer 124M is different from the proportion of elements contained in the materials that make up the remaining sacrificial layers 124. For example, if the plurality of sacrificial layers 124 are made of SiGe, the proportion of Si to Ge in the material that makes up the intermediate sacrificial layer 124M is different from the proportion of Si to Ge in the material that makes up the remaining sacrificial layers 124. In one embodiment, the thickness of the intermediate sacrificial layer 124M is greater than the thickness of each of the remaining sacrificial layers 124.

[0081] Referring to Figures 8, 9A, and 9B, a portion of the semiconductor layer 122 and sacrificial layer 124 included in the second stacked structure STB is removed to form a step structure in the pad region WPR, and at least a portion of the semiconductor layer 122 and the sacrificial layer 124 are removed to form a plurality of first word lines WLA, a plurality of first bit lines BLA, a plurality of first semiconductor patterns 110A, a plurality of first gate dielectric films GoxA, an interlayer insulating layer ILD, an insulating layer 150, a plurality of first bit line contacts BCA, a plurality of first bit line linking patterns BPA, a plurality of first word line contacts WLCA, a plurality of routing pads WRP including a plurality of first routing pads WRPA and a plurality of second routing pads WRPB, a lower cell-peripheral circuit linking pad CPDA, a plurality of cell linking contacts CIC, a plurality of cell linking patterns CIP, a cell bonding via BDCV, a cell bonding pad BDCP, and a cell bonding insulating layer BDCD. The plurality of first word lines WLA constitute the first word line stack WSA. In one embodiment, the intermediate sacrificial layer 124M functions as an etching blocking film in the etching process for forming a plurality of first bit lines BLA.

[0082] Referring to Figure 10, a peripheral circuit structure PRST is formed, which includes a peripheral circuit board PSUB, multiple peripheral circuit transistors PTR, multiple peripheral circuit linkage patterns PMP, multiple peripheral circuit linkage vias PMV, a peripheral circuit wiring insulation layer IMD, a peripheral circuit wiring protection layer IMP, a peripheral circuit bonding via BDPV, a peripheral circuit bonding pad BDPP, and a peripheral circuit bonding insulation layer BDPD.

[0083] Referring to Figures 9A and 9B, Figure 10, Figure 11A and Figure 11B, the results from Figures 9A and 9B are inverted and mounted onto the result from Figure 10 so that the cell bonding pad BDCP and the peripheral circuit bonding pad BDPP are bonded, and the cell bonding insulating layer BDCD and the peripheral circuit bonding insulating layer BDPD are bonded.

[0084] Referring to Figures 11A and 11B, and Figures 12A and 12B, the base substrate BSUB is removed, and a portion of the semiconductor layer 122 and sacrificial layer 124 contained in the first stacked structure STA is removed to form a step structure in the pad region WPR. At least a portion of the semiconductor layer 122 and the sacrificial layer 124 are removed to form a plurality of second word lines WLB, a plurality of second bit lines BLB, a plurality of second semiconductor patterns 110B, a plurality of second gate dielectric films GoxB, an interlayer insulating layer ILD, an insulating layer 150, a plurality of second bit line contacts BCB, a plurality of second bit line linkage patterns BPB, a plurality of second word line contacts WLCB, a plurality of word line routing vias WLRV, a cell wiring contact CMC, a plurality of word line routing lines WLRL, and an upper cell-peripheral circuit linkage pad CPDB. The plurality of second word lines WLB constitute the second word line stack WSB. In one embodiment, the intermediate sacrificial layer 124M functions as an etching blocking film in the etching process for forming a plurality of second bit lines BLB, and the intermediate insulating layer 150M is formed in the position where the intermediate sacrificial layer 124M has been removed.

[0085] Next, a pad structure PDST, which includes the external connecting via EPV, external connecting pad EPD, cover insulating layer CDI, and protective insulating layer PSV shown in Figures 7A and 7B, is formed on the memory cell structure MCST to form a semiconductor memory element 1a.

[0086] Figure 13 is a cross-sectional view showing a semiconductor memory element 1b of a first b example according to one embodiment of the present invention. Specifically, Figure 13 is a cross-sectional view taken along the line I-I' in Figures 3A and 3B.

[0087] Referring to Figure 13, the semiconductor memory element 1b has a memory cell region MCR, a pad region WPR, and an external linkage region PDR arranged along the first horizontal direction (X direction). The semiconductor memory element 1b includes a peripheral circuit structure PRST, a memory cell structure MCST on the peripheral circuit structure PRST, and a pad structure PDST on the memory cell structure MCST. The memory cell structure MCST and pad structure PDST included in the semiconductor memory element 1b are substantially identical to the memory cell structure MCST and pad structure PDST included in the semiconductor memory element 1a shown in Figures 7A and 7B, so overlapping content is omitted.

[0088] The peripheral circuit structure PRST includes a peripheral circuit board PSUB and a plurality of peripheral circuit transistors PTR. The plurality of peripheral circuit transistors PTR are located on the underside of the portion of the peripheral circuit board PSUB that is limited by the peripheral circuit element isolation film PSTI. The plurality of peripheral circuit transistors PTR are located on the underside of the peripheral circuit board PSUB facing the memory cell structure MCST. The underside of the peripheral circuit board PSUB is the active surface of the peripheral circuit board PSUB. For example, semiconductor memory element 1b has a CoP (Cell on Periphery)-back structure in which the memory cell structure MCST is located on the peripheral circuit structure PRST, the upper surface of the peripheral circuit board PSUB, which is the inactive surface of the peripheral circuit board PSUB, faces the memory cell structure MCST, and the plurality of peripheral circuit transistors PTR face the opposite side of the memory cell structure MCST.

[0089] The peripheral circuit structure PRST includes a plurality of peripheral circuit linkage patterns PMP and a plurality of peripheral circuit linkage vias PMV located beneath the peripheral circuit board PSUB, and a peripheral circuit wiring insulation layer IMD that covers the underside of the peripheral circuit board PSUB while enclosing the plurality of peripheral circuit linkage patterns PMP and a plurality of peripheral circuit linkage vias PMV. If the plurality of peripheral circuit linkage patterns PMP are embedded within the peripheral circuit wiring insulation layer IMD, the peripheral circuit structure PRST further includes a peripheral circuit wiring protection layer IMP that covers the underside of the plurality of peripheral circuit linkage patterns PMP and the underside of the peripheral circuit wiring insulation layer IMD.

[0090] The peripheral circuit structure PRST further includes a peripheral circuit cover insulating layer PCDI covering the inert surface which is the upper surface of the peripheral circuit substrate PSUB, a peripheral circuit bonding pad BDPP disposed on the peripheral circuit cover insulating layer PCDI, a peripheral circuit bonding insulating layer BDPD surrounding the peripheral circuit bonding pad BDPP, and peripheral circuit bonding vias BDPV connecting the peripheral circuit bonding pad BDPP and the peripheral circuit connection pattern PMP. The peripheral circuit bonding vias BDPV penetrate the peripheral circuit cover insulating layer PCDI, the peripheral circuit substrate PSUB, the peripheral circuit wiring insulating layer IMD, and / or the peripheral circuit wiring protection layer IMP to connect the peripheral circuit bonding pad BDPP and the peripheral circuit connection pattern PMP. The upper surface of the peripheral circuit bonding pad BDPP and the upper surface of the peripheral circuit bonding insulating layer BDPD are coplanar.

[0091] The memory cell structure MCST is bonded onto the peripheral circuit structure PRST via the cell bonding pad BDCP, the peripheral circuit bonding pad BDPP, the cell bonding insulating layer BDCD, and the peripheral circuit bonding insulating layer BDPD.

[0092] Figures 14 to 18 are cross-sectional views illustrating a method for manufacturing a semiconductor memory element 1b of the first b example according to one embodiment of the present invention. Specifically, Figures 14 to 18 are cross-sectional views taken along the line I-I' in Figures 3A and 3B.

[0093] Referring to both Figures 14 and 15, multiple peripheral circuit transistors PTR are formed on the peripheral circuit board PSUB, and multiple peripheral circuit linkage patterns PMP, multiple peripheral circuit linkage vias PMV, peripheral circuit wiring insulation layer IMD, and peripheral circuit wiring protection layer IMP are formed on the peripheral circuit board PSUB and the multiple peripheral circuit transistors PTR.

[0094] Referring to Figure 16, the support substrate SSUB is attached to the resulting product from Figure 15, for example, on the peripheral circuit wiring protection layer IMP.

[0095] Referring to Figure 17, the result from Figure 16 is inverted so that the support substrate SSUB is at the bottom and the peripheral circuit substrate PSUB is at the top. Then, a peripheral circuit cover insulating layer PCDI is formed to cover the inert surface which is the top surface of the peripheral circuit substrate PSUB, a peripheral circuit bonding pad BDPP is placed on the peripheral circuit cover insulating layer PCDI, a peripheral circuit bonding insulating layer BDPD surrounds the peripheral circuit bonding pad BDPP, and a peripheral circuit bonding via BDPV connects the peripheral circuit bonding pad BDPP and the peripheral circuit connection pattern PMP, thereby forming the peripheral circuit structure PRST.

[0096] Referring to Figure 18, the results from Figures 9A and 9B are inverted and mounted on the result from Figure 17 so that the cell bonding pad BDCP and the peripheral circuit bonding pad BDPP are bonded, and the cell bonding insulating layer BDCD and the peripheral circuit bonding insulating layer BDPD are bonded. Next, referring to Figures 12A and 12B, the semiconductor memory element 1b is formed.

[0097] Figures 19A to 19E are plan and cross-sectional views showing a third example of a semiconductor memory element 200 according to one embodiment of the present invention. Specifically, Figure 19A is a plan view of the semiconductor memory element 200 according to one embodiment of the present invention, viewed from above to below; Figure 19B is a plan view of the semiconductor memory element 200 according to one embodiment of the present invention, viewed from below to above; Figure 19C is a cross-sectional view of the semiconductor memory element 200 cut along the line IV-IV' in Figures 19A and 19B; Figure 19D is a cross-sectional view of the semiconductor memory element 200 cut along the line V-V' in Figures 19A and 19B; and Figure 19E is a cross-sectional view of the semiconductor memory element 200 cut along the line VI-VI' in Figures 19A and 19B.

[0098] Referring to Figures 19A to 19E, the semiconductor memory element 200 includes a plurality of word lines WL and a plurality of bit lines BL. The plurality of word lines WL include a plurality of word line pads WLP. The plurality of word lines WL include a plurality of first word lines WLA and a plurality of second word lines WLB. The plurality of word line pads WLP include a plurality of first word line pads WLPA contained within the plurality of first word lines WLA and a plurality of second word line pads WLPB contained within the plurality of second word lines WLB.

[0099] The first word line pad section WLPA is connected to the first word line contact WLCA, and the second word line pad section WLPB is connected to the second word line contact WLCB. Multiple word lines WL are electrically connected to multiple routing pads WRPa via multiple word line contacts WLC. Multiple routing pads WRPa include multiple first routing pads WRPAa connected on multiple first word lines WLA, and multiple second routing pads WRPBa connected on multiple second word lines WLB. The first routing pads WRPAa and the second routing pads WRPBa are located at the same vertical level. Word line routing vias WLRV are placed between adjacent word lines WL in the second horizontal direction (Y direction) in the pad area WPR, i.e., between word line pad sections WLP. Word line routing lines WLRLb are connected below each of the first word line contact WLCA and word line routing vias WLRV. Word line routing lines WLRLb electrically connect the first word line contact WLCA and word line routing vias WLRV.

[0100] The first word line contact WLCA connects the first word line pad portion WLPA of the first word line WLA to the first routing pad WRPAa. For example, the upper end of the first word line contact WLCA is connected to the first word line pad portion WLPA of the first word line WLA, and the lower end is connected to the word line routing line WLRLb. A word line routing via WLRV is formed between the word line routing line WLRLb and the first routing pad WRPBa. The first word line pad portion WLPA of the first word line WLA is electrically connected to the first routing pad WRPAa via the first word line contact WLCA, the word line routing line WLRLb, and the word line routing via WLRV.

[0101] Figures 20A and 20B are cross-sectional views showing a semiconductor memory element 2a of a second example according to one embodiment of the present invention. Specifically, Figure 20A is a cross-sectional view of the semiconductor memory element 2a cut along the position corresponding to the line IV-IV' in Figures 19A and 19B, and Figure 20B is a cross-sectional view of the semiconductor memory element 2a cut along the position corresponding to the line V-V' in Figures 19A and 19B.

[0102] Referring to both Figures 20A and 20B, the semiconductor memory element 2a has a memory cell region MCR, a pad region WPR, and an external linkage region PDR arranged along a first horizontal direction (X direction). The semiconductor memory element 2a includes a cell routing structure CRST on a support substrate SSUB, a memory cell structure MCST on the cell routing structure CRST, a peripheral circuit structure PRST on the memory cell structure MCST, and a pad structure PDST on the peripheral circuit structure PRST.

[0103] The cell routing structure CRST includes a cell routing pad RPD on a support substrate SSUB, a cell routing via RPV connecting the cell routing pad RPD to the lower cell-peripheral circuit linkage pad CPDA, and a cell routing cover insulating layer RCDI enclosing the cell routing pad RPD and the cell routing via RPV. In one embodiment, the cell routing via RPV is formed to extend into the interlayer insulating layer ILD of the memory cell structure MCST. In one embodiment, a cell routing protective insulating layer RSV is located beneath the cell routing cover insulating layer RCDI. The cell routing cover insulating layer RCDI contains an oxide, and the cell routing protective insulating layer RSV contains a nitride.

[0104] Unlike the memory cell structure MCST included in semiconductor memory element 1a shown in Figures 7A and 7B, in which the first routing pad WRPA and the second routing pad WRPB are connected below the first word line contact WLCA and the word line routing via WLRV, respectively, and the word line routing line WLRL is connected above the second word line contact WLCB and the word line routing via WLRV, the memory cell structure MCST included in semiconductor memory element 2a shown in Figures 20A and 20B has the word line routing line WLRLb connected below the first word line contact WLCA and the word line routing via WLRV, respectively, and the first routing pad WRPAa and the second routing pad WRPBa are connected above the second word line contact WLCB and the word line routing via WLRV, respectively.

[0105] The cell bonding pad BDCP, cell bonding insulating layer BDCD, cell bonding via BDCV, cell coupling contact CIC, and cell coupling pattern CIP included in the semiconductor memory element 2a have shapes that are inverted from the cell bonding pad BDCP, cell bonding insulating layer BDCD, cell bonding via BDCV, cell coupling contact CIC, and cell coupling pattern CIP included in the semiconductor memory element 1a shown in Figures 7A and 7B. The cell coupling contact CIC is connected to one of the upper cell-peripheral circuit coupling pad CPDB, the second bit line coupling pattern BPB, the first routing pad WRPAa, and the second routing pad WRPBa.

[0106] The peripheral circuit structure PRST included in the semiconductor memory element 2a has a shape that is an inverted version of the peripheral circuit structure PRST shown in Figures 7A and 7B.

[0107] The pad structure PDST includes an external linking pad EPD on the peripheral circuit structure PRST, an external linking via EPV connecting the external linking pad EDP and the peripheral circuit bonding pad BDPP, and a cover insulating layer CDI enclosing the external linking pad EDP and the external linking via EPV. In one embodiment, the external linking via EPV is connected to the peripheral circuit bonding pad BDPP by penetrating the peripheral circuit substrate PSUB, the peripheral circuit element isolation film PSTI, the peripheral circuit wiring insulating layer IMD, and the peripheral circuit wiring protective layer IMP.

[0108] For example, the semiconductor memory element 2a has a peripheral circuit structure PRST arranged on a memory cell structure MCST, and a PoC (Peripheral on Cell)-face structure in which the active surface of the peripheral circuit substrate PSUB and a plurality of peripheral circuit transistors PTR face the memory cell structure MCST.

[0109] Figures 21 to 25 are cross-sectional views illustrating a method for manufacturing a semiconductor memory element of a second example (a) according to one embodiment of the present invention. Specifically, Figures 21 to 25 are cross-sectional views taken along the lines IV-IV' in Figures 20A and 20B.

[0110] Referring to Figure 21 and Figure 9A, a plurality of first word lines WLA, a plurality of first semiconductor patterns 110A, a plurality of first gate dielectric films GoxA, an interlayer insulating layer ILD, an insulating layer 150, a plurality of first word line contacts WLCA, a lower cell-peripheral circuit connecting pad CPDA, and a word line routing line WLRLb are formed, and a cell routing structure CRST is formed on the interlayer insulating layer ILD, including a cell routing pad RPD, a cell routing via RPV, a cell routing cover insulating layer RCDI, and a cell routing protective insulating layer RSV.

[0111] Referring to both Figures 22 and 23, the result from Figure 21 is inverted and mounted on the support substrate SSUB, and then the base substrate BSUB is removed. Next, referring to Figure 9A, a plurality of second word lines WLB, a plurality of second semiconductor patterns 110B, a plurality of second gate dielectric films GoxB, an interlayer insulating layer ILD, an insulating layer 150, a plurality of second word line contacts WLCB, an upper cell-peripheral circuit linkage pad CPDB, a cell wiring contact CMC, an upper cell-peripheral circuit linkage pad CPDB, a plurality of cell linkage contacts CIC, a plurality of cell linkage patterns CIP, a cell bonding via BDCV, a cell bonding pad BDCP, and a cell bonding insulating layer BDCD are formed.

[0112] Referring to Figure 24, a peripheral circuit structure PRST is formed, which includes a peripheral circuit board PSUB, multiple peripheral circuit transistors PTR, multiple peripheral circuit linkage patterns PMP, multiple peripheral circuit linkage vias PMV, a peripheral circuit wiring insulation layer IMD, a peripheral circuit wiring protection layer IMP, a peripheral circuit bonding via BDPV, a peripheral circuit bonding pad BDPP, and a peripheral circuit bonding insulation layer BDPD.

[0113] Referring to Figure 25, the result of Figure 24 is mounted on the result of Figure 23, inverted. That is, the peripheral circuit structure PRST is mounted on the memory cell structure MCST. Next, referring to Figures 20A and 20B, a pad structure PDST is formed on the peripheral circuit structure PRST to form the semiconductor memory element 2a.

[0114] Figure 26 is a cross-sectional view showing a semiconductor memory element 2b of a second b example according to one embodiment of the present invention. Specifically, Figure 26 is a cross-sectional view taken along the line IV-IV' in Figures 19A and 19B.

[0115] Referring to Figure 26, the semiconductor memory element 2b has a memory cell region MCR, a pad region WPR, and an external linkage region PDR arranged along a first horizontal direction (X direction). The semiconductor memory element 2b includes a cell routing structure CRST on a support substrate SSUB, a memory cell structure MCST on the cell routing structure CRST, a peripheral circuit structure PRST on the memory cell structure MCST, and a pad structure PDST on the peripheral circuit structure PRST. The cell routing structure CRST and the memory cell structure MCST are substantially identical to the cell routing structure CRST and memory cell structure MCST shown in Figures 20A and 20B, and the peripheral circuit structure PRST has an inverted shape of the peripheral circuit structure PRST shown in Figure 17.

[0116] The pad structure PDST includes an external linking pad EPD on the peripheral circuit structure PRST, an external linking via EPV connecting the external linking pad EDP and the peripheral circuit linking pattern PMP, and a cover insulating layer CDI enclosing the external linking pad EDP and the external linking via EPV. In one embodiment, the external linking via EPV is formed to extend into the interlayer insulating layer ILD of the memory cell structure MCST. In one embodiment, a protective insulating layer PSV is disposed on the cover insulating layer CDI.

[0117] For example, the semiconductor memory element 2b has a PoC (Peripheral on Cell)-back structure in which the peripheral circuit structure PRST is placed on the memory cell structure MCST, the lower surface of the peripheral circuit substrate PSUB, which is the inert surface of the peripheral circuit substrate PSUB, faces the memory cell structure MCST, and multiple peripheral circuit transistors PTR face the opposite side of the memory cell structure MCST.

[0118] Referring to Figures 21 to 23, a cell routing structure CRST and a memory cell structure MCST are formed, and referring to Figures 14 to 17, a peripheral circuit structure PRST is formed. Then, the result from Figure 17 is inverted and mounted on the memory cell structure MCST, and a pad structure PDST is formed on the peripheral circuit structure PRST to form a semiconductor memory element 2b.

[0119] Figures 27A and 27B are cross-sectional views showing a fourth example of a semiconductor memory element 3 according to one embodiment of the present invention. Specifically, Figure 27A is a cross-sectional view of the fourth example of a semiconductor memory element 3 cut along a portion including the position corresponding to the line I-I' in Figures 3A and 3B, and Figure 27B is a cross-sectional view of the fourth example of a semiconductor memory element 3 cut along a portion including the position corresponding to the line II-II' in Figures 3A and 3B.

[0120] Referring to both Figures 27A and 27B, the semiconductor memory element 3 has a memory cell region MCR that is spaced apart along a first horizontal direction (X direction) and a pad region WPR that is located between two adjacent memory cell regions MCR in the first horizontal direction (X direction). The semiconductor memory element 3 includes, but is not limited to, a peripheral circuit structure PRST, a memory cell structure MCST on the peripheral circuit structure PRST, and a pad structure PDST on the memory cell structure MCST. For example, the semiconductor memory element 3 can be modified as shown in Figures 3 to 26 (1a, 1b, 2a, 2b). The semiconductor memory element 3 includes a plurality of word lines WL and a plurality of bit lines BL.

[0121] Multiple wordline WLs include multiple first wordline WLAs and multiple second wordline WLBs. Multiple wordline WLs constitute a wordline stack WST. The wordline stack WST includes a first wordline stack WSA and a second wordline stack WSB on the first wordline stack WSA. The first wordline stack WSA includes multiple first wordline WLAs from the multiple wordline WLs, and the second wordline stack WSB includes multiple second wordline WLBs from the multiple wordline WLs. Multiple wordline WLs include multiple wordline pads WLPs. Multiple wordline pads WLPs include multiple first wordline pads WLPAs included in the multiple first wordline WLAs and multiple second wordline pads WLPBs included in the multiple second wordline WLBs. Multiple wordline WLs have approximately the same length extending along the first horizontal direction (X direction). Multiple word lines WL extend continuously along a pad area WPR located between two adjacent memory cell regions MCRs in the first horizontal direction (X direction).

[0122] A first word line contact WLCA is connected to the first word line pad section WLPA, and a second word line contact WLCB is connected to the second word line pad section WLPB. Multiple word lines WL are electrically connected to multiple routing pads WRP via multiple word line contacts WLC. Multiple routing pads WRP include multiple first routing pads WRPA connected under multiple first word lines WLA, and multiple second routing pads WRPB connected under multiple second word lines WLB. Word line routing vias WLRV are placed between adjacent word lines WL in the second horizontal direction (Y direction) in the pad area WPR, i.e., between word line pad sections WLP. A word line routing line WLRL is connected above each of the second word line contacts WLCB and word line routing vias WLRV. The word line routing line WLRL electrically connects the second word line contact WLCB and the word line routing vias WLRV.

[0123] A first word line contact WLCA connected to a first word line WLA, excluding the lowest first word line WLA, penetrates at least one first word line WLA located below the connected first word line WLA. A second word line contact WLCB connected to a second word line WLB, excluding the uppermost second word line WLB, penetrates at least one second word line WLB located above the connected second word line WLB. The first contact insulating film WCDA surrounds the sidewall of the first word line contact WLCA, and the second contact insulating film WCDB surrounds the sidewall of the second word line contact WLCB. The first contact insulating film WCDA is interposed between the first word line contact WLCA and the first word line WLA through which the first word line contact WLCA penetrates, and the second contact insulating film WCDB is interposed between the second word line contact WLCB and the second word line WLB through which the second word line contact WLCB penetrates.

[0124] Multiple bit lines BL include multiple first bit lines BLA and multiple second bit lines BLB. Multiple first bit lines BLA extend vertically (in the Z direction) between multiple first word lines WLA, and multiple second bit lines BLB extend vertically (in the Z direction) between multiple second word lines WLB.

[0125] Figure 28 is an equivalent circuit diagram showing another example of a memory cell array of semiconductor memory element 4 according to one embodiment of the present invention.

[0126] Referring to Figure 28, the memory cell array of the semiconductor memory element 4 according to one embodiment of the present invention includes a plurality of subcell arrays SCA. The subcell array SCA includes a plurality of bit lines BLD, a plurality of word lines WL, and a plurality of memory cells MC. Each of the plurality of memory cells MC includes a cell transistor CT and an information storage element SP. One cell transistor CT is placed between one word line WL and one bit line BLD. The plurality of subcell arrays SCA are arranged along the second horizontal direction (Y direction).

[0127] Multiple word lines (WL) extend in the first horizontal direction (X direction). Word lines (WL) within a single subcell array (SCA) are separated from each other in the vertical direction (Z direction). Bit lines (BLD) extend in the vertical direction (Z direction). Bit lines (BLD) within a single subcell array (SCA) are separated from each other in the first horizontal direction (X direction).

[0128] The gate of the cell transistor CT is connected to the word line WL, and the source region of the cell transistor CT is connected to the bit line BLD. An information storage element SP is connected to the drain region of the cell transistor CT.

[0129] A pair of adjacent bit line BLDs in the second horizontal direction (Y direction) perform substantially the same function as a single bit line BL shown in Figure 1. For example, if a single bit line BL shown in Figure 1 is separated into two that are spaced apart along the second horizontal direction (Y direction), it becomes a pair of adjacent bit line BLDs in the second horizontal direction (Y direction) shown in Figure 28. The source and drain regions of the cell transistor CT and the information storage element SP are arranged along the second horizontal direction (Y direction) or the opposite direction from the bit line BLD connected to the source region of the cell transistor CT. The source and drain regions of the cell transistor CT and the information storage element SP connected to each of two adjacent bit line BLDs in the second horizontal direction (Y direction) are arranged along opposing directions. For example, the source and drain regions of a cell transistor CT and an information storage element SP connected to one of two adjacent bit line BLDs in the second horizontal direction (Y direction) are arranged sequentially along the second horizontal direction (Y direction), while the source and drain regions of a cell transistor CT and an information storage element SP connected to the other bit line BLD are arranged along the opposite direction of the second horizontal direction (Y direction). For example, a plurality of bit line BLDs include a first bit line, a second bit line, a third bit line, and a fourth bit line that are arranged sequentially adjacent along the second horizontal direction (Y direction), with no memory cell MC between the first and second bit lines, two memory cell MCs arranged at the same vertical level along the second horizontal direction (Y direction) between the second and third bit lines, and no memory cell MC between the third and fourth bit lines.

[0130] Although embodiments of the present invention have been described in detail above with reference to the drawings, the present invention is not limited to the embodiments described above, and can be modified and implemented in various ways without departing from the technical spirit of the present invention. [Explanation of symbols]

[0131] 1, 1a, 1b, 2a, 2b, 3, 4, 100, 100a, 100b, 200, 1000 Semiconductor memory elements 110 Semiconductor Patterns 110A, 110B First and Second Semiconductor Patterns 122 Semiconductor layer 124 layers of victims 124M intermediate sacrifice layer 150 Insulating layer 150M Intermediate Insulation Layer 1010 memory cell array 1020 Timing Register 1040 Programming Register 1060 Latency / Burst Length Control Unit 1080 column address buffer 1100 Column Decoder 1120 Output buffer 1200 Address Registers 1220 Row Address Buffer 1240 Raw Decoder 1250 Subword Line Driver (SWD) 1260 Bank Selection Section 1320 Data Input Register 1340 Input / Output Controller ADD Address Signal BCA, BCB 1st and 2nd bit line contacts BDCD cell bonding insulating layer BDCV Cell Bonding Via BDCP Cell Bonding Pad BDPD peripheral circuit bonding insulating layer BDPP peripheral circuit bonding pad BDPV peripheral circuit bonding vias BL, BLa bit line (first conductive line) BLA, BLAa 1st bit line BLB, BLBa 2nd bit line BLC Bitline Contact BLD Bitline BLP Bitline Concatenation Pattern BPA, BPB 1st and 2nd bitline concatenation pattern BSUB base board CASB column address strobe signal CDI Cover Insulation Layer CIC Cell Linked Contact CIP Cell Concatenation Pattern CLK clock signal CKE Clock Enable Signal CMC Cell Wiring Contacts CPDA, CPDB lower and upper cell - peripheral circuit linkage pads CRST Cell Routing Structure CSB Chip Selection Signal CT cell transistor DQi Output Data DQM Data Input / Output Mask Signal EPD External Connecting Pad EPV external connection via Gox gate dielectric film GoxA, GoxB first and second gate dielectric films ILD (Interlayer Insulation Layer) IMD Peripheral Circuit Wiring Insulation Layer IMP Peripheral Circuit Wiring Protection Layer LCAS Low Active Column Address Strobe Signaling LCBR Low Active CVR Refresh LCKE low-power clock enable signal LDQM Low Active Data Input / Output Mask Signal LRAS Low Active Low Address Strobe Signal LWCBR Low Active Write CAS before RAS LWE Low Active Write Enable Signal MC memory cell MCR memory cell region MCST memory cell structure MS laminated structure PCDI peripheral circuit cover insulating layer PDR external link area PDST pad structure PMP peripheral circuit coupling pattern PMV Peripheral Circuit Connecting Via PP ground wiring PRST Peripheral Circuit Structure PSTI peripheral circuit element isolation film P-Road Peripheral Circuit Board PSV protective insulating layer PTR Peripheral Circuit Transistor RASB Low-Address Strobe Signal RCDI Cell Routing Cover Insulation Layer RPD Cell Routing Pad RPV Cellular Via RSV Cell Routing Protective Insulation Layer SCA Subcell Array SP Information Storage Element SSUB support substrate STA, STB First and Second Layered Structures WE write enable signal WL (Ward Line) (Second Conductive Line) WLA, WLB 1st and 2nd Wardlines WLC Wordline Contact WLCA, WLCB First and Second Wordline Contacts WLD, WLU (lower and upper wardlines) WLP Wordline Pad Section WLPA, WLPB 1st and 2nd Wordline Pad Sections WLRL, WLRLa, WLRLb Word line routing lines WLRV, WLRVa Wordline Routing Via WLS Wordline Structure WLSA, WLSB First and Second Wordline Structures WRP Routing Pad WRPA, WRPAa 1st Routing Pad WRPB, WRPBa 2nd Routing Pad WPR Pad Area WSA, WSB 1st and 2nd wordline stacks (lower and upper wordline stacks) WST Wordline Stack

Claims

1. A semiconductor memory element having a memory cell region and a pad region arranged along a first horizontal direction, A first word line stack comprising a plurality of first word lines, each extending in the first horizontal direction and separated from each other in the second horizontal and vertical directions perpendicular to the first horizontal direction, and the pad area including a plurality of first word line pad portions, A second word line stack that extends in the first horizontal direction and is spaced apart from each other in the second horizontal direction and the vertical direction, and consists of a plurality of second word lines, each having a plurality of second word line pad portions in the pad area, and superimposed on the first word line stack in the vertical direction, A plurality of first word line contacts having one end extending vertically and connected to the plurality of first word line pad portions, A plurality of second word line contacts having one end extending in the vertical direction and connected to the plurality of second word line pad portions, A plurality of word line routing vias extending vertically and separated from each of the plurality of first word lines and the plurality of second word lines in the pad region, A plurality of word line routing lines connecting one end of the plurality of word line routing vias to the other end of the plurality of second word line contacts, A plurality of first routing pads connected to the other end of the plurality of first word line contacts, The system comprises a plurality of second routing pads connected to the other end of the plurality of word line routing vias, A semiconductor memory element characterized in that the plurality of first routing pads and the plurality of second routing pads are located at the same vertical level.

2. The plurality of first word line contacts have a tapered shape, with their horizontal width increasing as they move away from the plurality of first word line pad portions. The semiconductor memory element according to claim 1, characterized in that the plurality of second word line contacts have a tapered shape, with their horizontal width increasing as they move away from the plurality of second word line pad portions.

3. The second word line stack is located above the first word line stack. The plurality of first word line contacts extend downward from the lower surface of the plurality of first word line pad portions. The plurality of second word line contacts extend upward from the upper surface of the plurality of second word line pad portions. The semiconductor memory element according to claim 1, characterized in that the plurality of word line routing vias have a tapered shape that extends while becoming narrower in horizontal width as it moves away from the plurality of word line routing lines.

4. The first word line stack is located above the second word line stack, The plurality of first word line contacts extend upward from the upper surface of the plurality of first word line pad portions. The plurality of second word line contacts extend downward from the lower surface of the plurality of second word line pad portions. The semiconductor memory element according to claim 1, characterized in that the plurality of word line routing vias have a tapered shape that increases in horizontal width as they move away from the plurality of word line routing lines.

5. A semiconductor memory element having a memory cell region and a pad region arranged along a first horizontal direction, The device comprises a memory cell structure and a peripheral circuit structure stacked vertically to the memory cell structure and electrically connected thereto. The peripheral circuit structure includes a peripheral circuit board and a plurality of peripheral circuit transistors located on the active surface of the peripheral circuit board. The aforementioned memory cell structure is A first word line stack comprising a plurality of first word lines, each extending in the first horizontal direction and separated from each other in the second horizontal and vertical directions perpendicular to the first horizontal direction, and the pad area including a plurality of first word line pad portions, A second word line stack that extends in the first horizontal direction and is spaced apart from each other in the second horizontal direction and the vertical direction, and consists of a plurality of second word lines, each having a plurality of second word line pad portions in the pad area, and superimposed on the first word line stack in the vertical direction, A plurality of first word line contacts having one end extending vertically and connected to the plurality of first word line pad portions, A plurality of second word line contacts having one end extending in the vertical direction and connected to the plurality of second word line pad portions, A plurality of word line routing vias extending vertically and separated from each of the plurality of first word lines and the plurality of second word lines in the pad region, A plurality of word line routing lines connecting one end of the plurality of word line routing vias to the other end of the plurality of second word line contacts, A plurality of first routing pads connected to the other end of the plurality of first word line contacts, A semiconductor memory element characterized by including a plurality of second routing pads connected to the other ends of the plurality of word line routing vias.

6. The second word line stack is located above the first word line stack. The peripheral circuit structure is located below the memory cell structure. The plurality of first routing pads and the plurality of second routing pads are located at the same vertical level below the first word line stack. The semiconductor memory element according to claim 5, characterized in that the peripheral circuit structure is electrically connected to the memory cell structure via the plurality of first routing pads and the plurality of second routing pads.

7. The second word line stack is located below the first word line stack. The peripheral circuit structure is located on top of the memory cell structure. The plurality of first routing pads and the plurality of second routing pads are located on the same vertical level on the first word line stack. The semiconductor memory element according to claim 5, characterized in that the peripheral circuit structure is electrically connected to the memory cell structure via the plurality of first routing pads and the plurality of second routing pads.

8. The plurality of first word line contacts have a tapered shape, with their horizontal width increasing as they move away from the plurality of first word line pad portions. The semiconductor memory element according to claim 5, characterized in that the plurality of second word line contacts have a tapered shape, with their horizontal width increasing as they move away from the plurality of second word line pad portions.

9. The semiconductor memory element according to claim 5, characterized in that the plurality of word line routing vias have a tapered shape, with their horizontal width narrowing as they extend from the top to the bottom.

10. A semiconductor memory element having a memory cell region and a pad region arranged along a first horizontal direction, The device comprises a memory cell structure and a peripheral circuit structure stacked vertically to the memory cell structure and electrically connected thereto. The peripheral circuit structure includes a peripheral circuit board and a plurality of peripheral circuit transistors located on the active surface of the peripheral circuit board. The aforementioned memory cell structure is A first word line stack comprising a plurality of first word lines, each extending in the first horizontal direction and separated from each other in the second horizontal and vertical directions perpendicular to the first horizontal direction, and the pad area including a plurality of first word line pad portions, A second word line stack that extends in the first horizontal direction and is spaced apart from each other in the second horizontal direction and the vertical direction, and consists of a plurality of second word lines, each having a plurality of second word line pad portions in the pad area, and superimposed on the first word line stack in the vertical direction, Between the plurality of first word lines, the plurality of first bit lines extending vertically, Between the plurality of second word lines, the plurality of second bit lines extending vertically, A plurality of first word line contacts extending in the vertical direction and connected to the lower surfaces of the plurality of first word line pad portions, A plurality of second word line contacts connected to the upper surfaces of the plurality of second word line pad portions and extending in the vertical direction, In the pad region, a plurality of word line routing vias extending vertically along the spaces between the second horizontally separated first word lines among the plurality of first word lines, and between the second horizontally separated second word lines among the plurality of second word lines, A plurality of word line routing lines connecting the upper ends of the plurality of second word line contacts and the upper ends of the plurality of word line routing vias, A plurality of first routing pads connected to the lower ends of the plurality of first word line contacts, The system includes a plurality of second routing pads connected to the lower ends of the plurality of word line routing vias and electrically connected to a plurality of second word line contacts, The plurality of first word line contacts have a tapered shape, with their horizontal width increasing as they move away from the plurality of first word line pad portions. The plurality of second word line contacts have a tapered shape, with their horizontal width increasing as they move away from the plurality of second word line pad portions. The semiconductor memory element is characterized in that the plurality of word line routing vias have a tapered shape that extends from the plurality of word line routing lines toward the plurality of second routing pads with the horizontal width becoming narrower.

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