Memory device and method for manufacturing the same
The memory device design with high-density plasma oxide insulating layers within trenches addresses the challenges of miniaturization and integration, preventing memory cell deterioration and enhancing manufacturing efficiency.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- SK HYNIX INC
- Filing Date
- 2025-11-05
- Publication Date
- 2026-06-01
AI Technical Summary
The increasing difficulty in forming memory cells due to miniaturization and high integration in memory devices, coupled with the need for efficient arrangement of elements and circuits during wafer bonding, leads to potential deterioration of memory cells.
A memory device design comprising a first substrate with a cell region and peripheral region, a memory cell array, peripheral transistors, and insulating layers, including a high-density plasma oxide layer within trenches, to enhance the integration and protection of memory cells.
Prevents degradation of memory cells by improving hydrogen supply efficiency and reducing damage during the manufacturing process, thereby maintaining the integrity and performance of the memory device.
Smart Images
Figure 2026089673000001_ABST
Abstract
Description
Technical Field
[0001] Embodiments of the present disclosure relate to a memory device and a method of manufacturing the same.
[0002] (Cross - reference to related applications) This application claims priority based on 35 U.S.C.§ 119(a) to Korean Patent Application No. 10 - 2024 - 0165843, filed on November 20, 2024, the entire contents of which are incorporated herein by reference.
Background Art
[0003] Due to characteristics such as miniaturization, multifunctionality, and / or low manufacturing cost, memory devices have been in the spotlight as important elements in the electronics industry. As the electronics industry develops highly, memory devices are becoming more and more highly integrated. For the high integration of memory devices, the line width of the wiring included in the memory device is gradually decreasing, and the size of the memory cell is also shrinking. As a result, the difficulty of the process of forming the memory cell is increasing.
[0004] On the other hand, for the high integration of memory devices, after separately manufacturing a wafer on which memory cells are arranged and a wafer on which peripheral circuits are arranged, a process of manufacturing a memory device by bonding one wafer onto the other wafer is used. As the memory device is manufactured by the wafer bonding process, it has become important to efficiently arrange various elements and circuits in the memory device.
Summary of the Invention
Problems to be Solved by the Invention
[0005] Embodiments of the present disclosure can provide a memory device capable of preventing deterioration of memory cells and a method of manufacturing the same.
Means for Solving the Problems
[0006] Embodiments of the present disclosure can provide a memory device comprising a first substrate including a cell region and a peripheral region surrounding the cell region; a memory cell array disposed in the cell region of the first substrate; a second substrate on the memory cell array; peripheral transistors disposed on the second substrate and connected to the memory cell array; a first insulating layer disposed in a trench located in the peripheral region of the first substrate and comprising a high-density plasma oxide; and a second insulating layer on the first insulating layer.
[0007] Embodiments of the present disclosure can provide a memory device comprising a first substrate, a memory cell array disposed on the first substrate, a first insulating layer disposed in a trench located on the first substrate and surrounding the region in which the memory cell array is disposed, and a second insulating layer comprising a high-density plasma oxide and covering the upper surface of the first insulating layer.
[0008] Embodiments of the present disclosure provide a memory device comprising a first semiconductor structure and a second semiconductor structure bonded onto the first semiconductor structure, wherein the first semiconductor structure comprises a first substrate including a cell region and a peripheral region surrounding the cell region, a memory cell array disposed in the cell region of the first substrate, a first insulating layer disposed in the peripheral region of the first substrate, and a second insulating layer covering the upper surface of the first insulating layer, and the second semiconductor structure comprises a second substrate and peripheral transistors disposed on the second substrate and connected to the memory cell array, wherein at least one of the peripheral transistors overlaps with the cell region.
[0009] Embodiments of the present disclosure provide a method for manufacturing a memory device comprising a first semiconductor structure including a memory cell array and a second semiconductor structure including peripheral transistors, the method comprising the steps of: forming trenches in the peripheral region of a first substrate including a cell region and a peripheral region surrounding the cell region; forming a first insulating layer containing high-density plasma oxide in the trenches; forming the memory cell array in the cell region of the first substrate; and forming the peripheral transistors on the memory cell array so as to be connected to the memory cell array. [Effects of the Invention]
[0010] According to embodiments of this disclosure, it is possible to prevent the degradation of memory cells. [Brief explanation of the drawing]
[0011] [Figure 1] This is an exemplary block diagram of a memory device according to an embodiment of the present disclosure.
[0012] [Figure 2] This figure shows an example of the circuit structure of a memory device according to an embodiment of the present disclosure.
[0013] [Figure 3] This figure shows an example of a planar structure of a memory device according to an embodiment of the present disclosure.
[0014] [Figure 4] This figure shows an example of a cross-sectional structure of a memory device according to an embodiment of the present disclosure.
[0015] [Figure 5] This is a diagram illustrating the memory device shown in Figure 4.
[0016] [Figure 6] This figure shows another example of the cross-sectional structure of a memory device according to an embodiment of the present disclosure.
[0017] [Figure 7] The figure shows an example of a memory device shown in FIG. 6.
[0018] [Figure 8] The figure shows another example of the memory device shown in FIG. 6. [Figure 9] The figure shows another example of the memory device shown in FIG. 6.
[0019] [Figure 10] The figure shows another example of the cross-sectional structure of a memory device according to an embodiment of the present disclosure.
[0020] [Figure 11] The figure shows an example of the memory device shown in FIG. 10.
Mode for Carrying Out the Invention
[0021] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.
[0022] In the accompanying drawings, three directions parallel to the upper surface of the substrate are defined as the first direction FD, the second direction SD, and the third direction TD, respectively, and the direction protruding perpendicularly from the upper surface of the substrate is defined as the fourth direction VD. The first direction FD and the second direction SD may be substantially perpendicular to each other. The fourth direction VD is perpendicular to the first direction FD, the second direction SD, and the third direction TD. In the following description, "perpendicular" or "perpendicular direction" is used to mean substantially the same as the fourth direction VD. The direction indicated by the arrow in the figure and the opposite direction thereof indicate the same direction.
[0023] FIG. 1 is an exemplary block diagram of a memory device according to an embodiment of the present disclosure.
[0024] The memory device 100 includes a memory cell array 110, a sense amplifier (SA) 120, a row decoder 130, a column decoder 140, an input / output circuit (I / O Circuit) 150, and a control logic 160.
[0025] The memory cell array 110 includes multiple memory cells for storing data.
[0026] The sense amplifier 120 is connected to multiple memory cells included in the memory cell array 110. The sense amplifier 120 can sense and amplify signals when reading or writing data stored in the memory cells. For example, when writing data, the sense amplifier 120 can amplify the signal transmitted from the input / output circuit 150 and supply it to the memory cells in the memory cell array 110. Also, when reading data, it can sense the data stored in the memory cells, amplify the signal for sensing the data, and provide it to the input / output circuit 150.
[0027] The row decoder 130 can select the corresponding word line in the memory cell array 110 according to a specified row address. The row decoder 130 can generate a word line drive signal to drive the selected word line.
[0028] The column decoder 140 can decode a column address and activate a column selection signal, and can select multiple bit lines according to a single column selection signal.
[0029] The input / output circuit 150 can write input data to the memory cell when a write operation is performed. The input / output circuit 150 can sense, amplify, and output data loaded onto the input / output line when a read operation is performed.
[0030] The control logic 160 can control the peripheral circuits of the memory device 110, including the row decoder 130 and the column decoder 140, according to the received command.
[0031] Referring to Figure 1, the components 110, 120, 130, 140, 150, and 160 of the memory device 110 described above are illustrative. Some of the components described above may be omitted. Alternatively, some of the components described above may be combined into one. In some cases, one or more other components may be included in the memory device in addition to the components described above.
[0032] Figure 2 shows an example of the circuit structure of a memory device according to an embodiment of the present disclosure.
[0033] Referring to Figure 2, the memory device 110 includes a memory cell array 110, a word line WL, a bit line BL, a memory cell MC, a first sense amplifier 120a and a second sense amplifier 120b, a first subword line driver 210a, and a second subword line driver 210b.
[0034] The bit line BL and the word line WL are each connected to a memory cell MC in the memory cell array 110. The bit line BL and the word line WL intersect with each other. The memory cell MC is located at the point where the bit line BL and the word line WL intersect.
[0035] The bit lines BL are connected to the first sense amplifier 120a and the second sense amplifier 120b. Two adjacent bit lines BL may be connected to the first sense amplifier 120a and the second sense amplifier 120b, respectively. For example, a bit line BL connected to the first sense amplifier 120a may be placed between bit lines BL connected to the second sense amplifier 120b. Each bit line BL connected to the first sense amplifier 120a may be adjacent to each bit line BL connected to the second sense amplifier 120b.
[0036] A word line WL is connected to a first sub-word line driver 210a and a second sub-word line driver 210b. The first sub-word line driver 210a and the second sub-word line driver 210b receive the signals necessary for driving the word line WL from the raw decoder 130 shown in Figure 1, and can drive a selected word line WL from among the word lines WL. Two adjacent word line WLs may be connected to the first sub-word line driver 210a and the second sub-word line driver 210b, respectively. For example, a word line WL connected to the first sub-word line driver 210a is obtained by being positioned between word line WLs connected to the second sub-word line driver 210b. Each of the word line WLs connected to the first sub-word line driver 210a may be adjacent to each of the word line WLs connected to the second sub-word line driver 210b.
[0037] Figure 3 shows an example of a planar structure of a memory device according to an embodiment of the present disclosure.
[0038] Referring to Figure 3, the memory device 100 includes a cell area CR and a peripheral area PR. The cell area CR is the area where the memory cell array 110 shown in Figures 1 and 2 is located. The peripheral area PR is the area where peripheral circuits for transmitting various voltages and signals to the memory cells located in the cell area CR are located. The peripheral area PR is located around the cell area CR. In one embodiment, the peripheral area PR can surround the cell area CR.
[0039] The memory device 100 includes bit lines BL, word lines WL, and an active area 310.
[0040] The active regions 310 may be separated from each other along a first direction FD and a second direction SD. The active regions 310 may be extended along a third direction TD. The bit line BL and the word line WL are arranged to cross the active regions 310. The bit line BL extends in the second direction SD. The word line WL extends in the first direction FD. The bit line BL and the word line WL are arranged superimposed on the cell region CR. In one embodiment, at least a portion of the bit line BL may be extended in the second direction SD to the peripheral region PR. In one embodiment, at least a portion of the word line WL may be extended in the first direction FD to the peripheral region PR.
[0041] Figure 3 shows one bit line BL and one word line WL placed in one cell area CR, but this is for illustrative purposes only. For example, the number of bit lines BL and word lines WL placed in a cell area CR may be greater than this. Also, bit lines BL and word lines WL can be placed in all cell areas CR.
[0042] A first insulating layer 300 is placed in the peripheral region PR. The first insulating layer 300 is placed between adjacent cell regions CR. In one embodiment, the first insulating layer 300 can surround the cell region CR.
[0043] Figure 4 shows an example of a cross-sectional structure of a memory device according to an embodiment of the present disclosure.
[0044] Referring to Figure 4, the memory device 100 includes a first semiconductor structure S1 and a second semiconductor structure S2. The first semiconductor structure S1 and the second semiconductor structure S2 may be fabricated on different wafers. In one embodiment, the process of fabricating the first semiconductor structure S1 may be carried out separately from the process of fabricating the second semiconductor structure S2. The second semiconductor structure S2 may be bonded to the upper surface of the first semiconductor structure S1. The interface between the first semiconductor structure S1 and the second semiconductor structure S2 may be called the bonding interface.
[0045] The first semiconductor structure S1 includes a first substrate 410, a memory cell array 110, a memory cell MC, a first insulating layer 300, and a first interlayer insulating layer 430.
[0046] In the cell region CR, a memory cell array 110 including memory cells MC is arranged on the first substrate 410. In the peripheral region PR, a first insulating layer 300 is arranged inside the first substrate 410. In one embodiment, the first insulating layer 300 can surround the region where the memory cell array 110 is arranged. A first interlayer insulating layer 430 is arranged on the memory cell array 110.
[0047] A second semiconductor structure S2 is placed on the first semiconductor structure S1. The second semiconductor structure S2 includes a second substrate 420, a first subword line driver 210a, and a second interlayer insulating layer 440.
[0048] A first subword line driver 210a is placed on the second substrate 420. In one embodiment, the first subword line driver 210a may be placed in a peripheral region PR. The first subword line driver 210a includes a first peripheral transistor TR1. The first peripheral transistor TR1 is one transistor that constitutes the first subword line driver 210a. A second interlayer insulating layer 440 is placed on the second substrate 420 and the first subword line driver 210a. Although it has been shown that the first subword line driver 210a is placed on the second substrate 420, this is illustrative. That is, a second subword line driver 210b may be placed on the second substrate 420.
[0049] A memory cell MC can be electrically connected to a first peripheral transistor TR1. For example, one memory cell MC may be connected to one word line WL, and another memory cell MC may be electrically connected to the first peripheral transistor TR1 via one word line WL.
[0050] Figure 5 is a diagram illustrating the memory device shown in Figure 4.
[0051] Referring to Figure 5, the memory device 100 includes a first semiconductor structure S1, a second semiconductor structure S2, and a word line connection contact 560. The first semiconductor structure S1 includes a first substrate 410, an element isolation layer 501, a gate structure 510, a third insulating layer 505, a bit line contact 506, a bit line BL, a lower contact plug 508, an upper contact plug 509, a landing pad 518, a capacitor 530, a support layer 550, a fourth insulating layer 521, a first contact 581, a first wiring 591, a liner insulating layer 502, a first insulating layer 300, a second insulating layer 503, and a first interlayer insulating layer 430.
[0052] The first substrate 410 may include a semiconductor substrate such as a silicon wafer or an SOI (Silicon On Insulator) wafer. The first substrate 410 may include a III-V semiconductor substrate, such as a compound semiconductor substrate like GaAs. The first substrate 410 may include single-crystal silicon, polysilicon, amorphous silicon, single-crystal silicon germanium, polycrystalline silicon germanium, carbon-doped silicon, or a combination thereof.
[0053] The first substrate 410 includes at least one device isolation layer 501 in the cell region CR and the peripheral region PR. The device isolation layer 501 may be formed using trench device isolation techniques such as STI (Shallow Trench Isolation). The device isolation layer 501 may include silicon oxide, silicon nitride, silicon oxynitride, low-K dielectrics, high-K dielectrics, or a combination thereof.
[0054] In the cell region CR, the gate structure 510 may be embedded within the first substrate 410. The gate structure 510 includes a word line WL, a gate capping layer 512, and a gate insulating layer 513. The upper surface of the word line WL is located at a lower level than the upper surface of the first substrate 410. The word line WL may be a buried gate or a buried word line. The gate capping layer 512 is placed on the word line WL. The gate insulating layer 513 surrounds the sides of the word line WL and the gate capping layer 512.
[0055] The word line WL may include conductive materials such as metals, metal oxides, metal nitrides, metal silicides, polysilicon, conductive carbon, or combinations thereof. The gate capping layer 512 may include silicon oxide, silicon nitride, silicon oxynitride, low-silicon dielectric, high-silicon dielectric, or combinations thereof. The gate insulating layer 513 may include silicon oxide, silicon nitride, silicon oxynitride, high-silicon dielectric, or combinations thereof.
[0056] A third insulating layer 505, a bit line contact 506, and contact plugs 508 and 509 are arranged on the first substrate 410.
[0057] In the cell region CR, a bit line BL is positioned on the bit line contact 506. The bit line BL may extend perpendicular to the word line WL. The bit line BL may not contact the contact plugs 508 and 509. That is, an additional insulating layer may be positioned between the bit line BL and the contact plugs 508 and 509. A landing pad 518 and a fourth insulating layer 521 are positioned on the upper contact plug 509. The landing pad 518 overlaps the upper contact plug 509 in a vertical direction VD.
[0058] The bit wire contact 506, bit wire BL, contact plugs 508, 509, and landing pad 518 may include conductive materials such as metals, metal oxides, metal nitrides, metal silicides, polysilicon, conductive carbon, or combinations thereof.
[0059] The lower electrode 531, dielectric layer 532, upper electrode 533, and support layer 550 are arranged on the fourth insulating layer 521 and landing pad 518. The lower electrode 531, dielectric layer 532, and upper electrode 533 constitute the capacitor 530 of the memory cell.
[0060] The lower electrode 531 overlaps the landing pad 518 perpendicularly. A support layer 550 is positioned on the side surface of the lower electrode 531. The support layer 550 surrounds the side surface of the lower electrode 531. A support layer 550 positioned on the side surface of one lower electrode 531 can be separated from a support layer 550 positioned on the side surface of the other lower electrode 531.
[0061] The dielectric layer 532 is positioned to cover the surfaces of the lower electrode 531 and the support layer 550. The upper electrode 533 is positioned on the dielectric layer 532. The upper surface of the upper electrode 533 can be positioned at a higher level than the upper surface of the lower electrode 531.
[0062] The lower electrode 531 and the upper electrode 533 may include conductive materials such as metals, metal oxides, metal nitrides, metal silicides, polysilicon, conductive carbon, or combinations thereof. The support layer 550 may include, but is not limited to, silicon nitride or silicon carbonitride. The dielectric layer 532 may include high dielectric materials, silicon oxides, silicon nitride, or combinations thereof.
[0063] A first interlayer insulating layer 430 is placed on the upper electrode 533. The first contact 581 penetrates the first interlayer insulating layer 430 and is connected to the upper electrode 533. A first wiring 591 is placed on the first contact 581.
[0064] In the peripheral region PR, the first substrate 410 includes at least one trench TRE. A liner insulating layer 502, a first insulating layer 300, and a second insulating layer 503 are disposed within the trench TRE. In one embodiment, the liner insulating layer 502, the first insulating layer 300, and the second insulating layer 503 can surround the region where the memory cell array 110 is located. The liner insulating layer 502 is disposed on the side and bottom surfaces of the trench TRE. The liner insulating layer 502 may contain an oxide.
[0065] The first insulating layer 300 is placed on the liner insulating layer 502. The first insulating layer 300 can fill the interior of the trench TRE. The first insulating layer 300 contains hydrogen. The first insulating layer 300 may be a layer with a higher hydrogen supply capacity compared to other layers. The first insulating layer 300 may contain an oxide with a high hydrogen content. In one embodiment, the first insulating layer 300 may contain high-density plasma oxide (HDP).
[0066] A second insulating layer 503 is placed on the first insulating layer 300. The second insulating layer 503 can completely cover the upper surface of the first insulating layer 300. In one embodiment, the upper surface of the second insulating layer 503 can form a substantially flat plane with the upper surface of the first substrate 410. In one embodiment, the second insulating layer 503 may contain silicon nitride.
[0067] A word line WL may be positioned on the second insulating layer 503. In one embodiment, the word line WL may be located on the upper surface of the first substrate 410 in at least a portion of the peripheral region PR. In one embodiment, the word line WL may extend into the peripheral region PR in a first direction FD. In one embodiment, the word line WL may overlap the first insulating layer 300.
[0068] A word line connection contact 560 and a first interlayer insulating layer 430 are arranged on the word line WL. The word line connection contact 560 penetrates the first interlayer insulating layer 430 and is connected to the word line WL. The word line connection contact 560 contacts the upper surface of the word line WL and extends in the vertical direction VD. The word line connection contact 560 may include conductive materials such as metal, metal oxide, metal nitride, metal silicide, polysilicon, conductive carbon, or a combination thereof.
[0069] A second semiconductor structure S2 is placed on the first semiconductor structure S1. The second semiconductor structure S2 includes a second substrate 420, a second interlayer insulating layer 440, a second contact 582, a third contact 583, a second wiring 592, a third wiring 593, a first peripheral transistor TR1, and source / drain contacts 574 and 575.
[0070] The second substrate 420 is placed on the first semiconductor structure S1. In one embodiment, the second substrate 420 may contain the same material as the material constituting the first substrate 410.
[0071] In the cell region CR, a second contact 582 is positioned that penetrates the second substrate 420. The second contact 582 penetrates the second substrate 420 in a vertical direction and contacts the upper surface of the first wiring 591.
[0072] A second wiring 592 is connected to the second contact 582. A third contact 583 is placed on the second wiring 592. A third wiring 593 is connected to the third contact 583. A second interlayer insulating layer 440 is placed on the second substrate 420, covering the second contact 582, the second wiring 592, the third contact 583, and the third wiring 593.
[0073] In the peripheral region PR, the word line connection contact 560 penetrates the second substrate 420. The word line connection contact 560 penetrates the second substrate 420 and contacts the lower surface of the second wiring 592.
[0074] The first peripheral transistor TR1 is located on the second substrate 420. The first peripheral transistor TR1 includes a gate electrode 570, a gate insulating layer 571, a source region 572, and a drain region 573. The first peripheral transistor TR1 is the transistor included in the first subword line driver 210a shown in Figure 4. In one embodiment, the first peripheral transistor TR1 may be located in the peripheral region PR.
[0075] The source contact 574 is connected to the source area 572 and the second wiring 592. The drain contact 575 is connected to the drain area 573 and the second wiring 592.
[0076] The first peripheral transistor TR1 may be connected to a word line WL via a drain contact 575 connected to a drain region 573, a second wiring 592 connected to the drain contact 575, and a word line connection contact 560 connected to the second wiring 592.
[0077] Figure 6 shows another example of the cross-sectional structure of a memory device according to an embodiment of the present disclosure.
[0078] Referring to Figure 6, the memory device 100 includes a first semiconductor structure S1 and a second semiconductor structure S2. The first semiconductor structure S1 includes a first substrate 410, a memory cell array 110, a memory cell MC, a first insulating layer 300, and a first interlayer insulating layer 430. The second semiconductor structure S2 is placed on the first semiconductor structure S1. The second semiconductor structure S2 includes a second substrate 420, a first sense amplifier 120a, and a second interlayer insulating layer 440.
[0079] A first sense amplifier 120a is placed on the second substrate 420. The first sense amplifier 120a may be placed in the cell region CR and the peripheral region PR. In one embodiment, the first sense amplifier 120a can be superimposed on the cell region CR. The first sense amplifier 120a includes a second peripheral transistor TR2. The second peripheral transistor TR2 is one transistor that constitutes the first sense amplifier 120a. In one embodiment, the second peripheral transistor TR2 may be placed in the peripheral region PR. A second interlayer insulating layer 440 is placed on the second substrate 420 and the first sense amplifier 120a. Although it has been shown that the first sense amplifier 120a is placed on the second substrate 420, this is illustrative. That is, a second sense amplifier 120b may be placed on the second substrate 420.
[0080] A memory cell MC can be electrically connected to a second peripheral transistor TR2. For example, one memory cell MC may be connected to one bit line BL, and another memory cell MC may be electrically connected to the second peripheral transistor TR2 via one bit line BL.
[0081] Figure 7 shows an example of the memory device shown in Figure 6.
[0082] Referring to Figure 7, the memory device 100 includes a first semiconductor structure S1, a second semiconductor structure S2, and a bit line connection contact 760.
[0083] The first semiconductor structure S1 includes a first substrate 410, an element isolation layer 501, a gate structure 510, a third insulating layer 505, a bit line contact 506, a bit line BL, a lower contact plug 508, an upper contact plug 509, a landing pad 518, a capacitor 530, a support layer 550, a fourth insulating layer 521, a first contact 581, a first wiring 591, a liner insulating layer 502, a first insulating layer 300, a second insulating layer 503, and a first interlayer insulating layer 430.
[0084] In the peripheral region PR, a bit line BL may be positioned on the second insulating layer 503. The bit line BL may be positioned at the same height as the bit line BL located in the cell region CR. The bit line BL may be separated from the upper surface of the first substrate 410 in a vertical direction VD. In one embodiment, the bit line BL may be extended into the peripheral region PR in a second direction SD. In one embodiment, the bit line BL may be superimposed on the first insulating layer 300.
[0085] A bit line connection contact 760 and a first interlayer insulating layer 430 are arranged on the bit line BL. The bit line connection contact 760 penetrates the first interlayer insulating layer 430 and is connected to the bit line BL. The bit line connection contact 760 contacts the upper surface of the word line WL and extends in the vertical direction VD. The bit line connection contact 760 may contain a conductive material such as metal, metal oxide, metal nitride, metal silicide, polysilicon, conductive carbon, or a combination thereof.
[0086] A second semiconductor structure S2 is placed on the first semiconductor structure S1. The second semiconductor structure S2 includes a second substrate 420, a second interlayer insulating layer 440, a second contact 582, a third contact 583, a second wiring 592, a third wiring 593, a second peripheral transistor TR2, and source / drain contacts 774 and 775.
[0087] A second peripheral transistor TR2 is located on the second substrate 420. The second peripheral transistor TR2 includes a gate electrode 770, a gate insulating layer 771, a source region 772, and a drain region 773. The second peripheral transistor TR2 is the transistor included in the first sense amplifier 120a shown in Figure 6. In one embodiment, the second peripheral transistor TR2 may be located in the peripheral region PR.
[0088] The source contact 774 is connected to the source area 772 and the second wiring 592. The drain contact 775 is connected to the drain area 773 and the second wiring 592.
[0089] The second peripheral transistor TR2 may be connected to one bit line BL via a drain contact 775 connected to the drain region 773, a second wiring 592 connected to the drain contact 775, and a bit line connection contact 760 connected to the second wiring 592.
[0090] Figures 8 and 9 show another example of the memory device shown in Figure 6.
[0091] Referring to Figure 8, the memory device 100 includes a first semiconductor structure S1 and a second semiconductor structure S2. The first semiconductor structure S1 can be bonded onto the second semiconductor structure S2.
[0092] The first semiconductor structure S1 includes a first substrate 410, an element isolation layer 501, a gate structure 510, a third insulating layer 505, a bit line contact 506, a bit line BL, a lower contact plug 508, an upper contact plug 509, a landing pad 518, a capacitor 530, a support layer 550, a fourth insulating layer 521, a first contact 581, a liner insulating layer 502, a first insulating layer 300, a second insulating layer 503, a first interlayer insulating layer 430, a first bonding insulating layer 811, a first bonding pad 821, and a bit line connection contact 860.
[0093] The second semiconductor structure S2 includes a second substrate 420, a second interlayer insulating layer 440, a second contact 870, a second wiring 592, a second peripheral transistor TR2, source / drain contacts 774, 775, a second bonding insulating layer 812, and a second bonding pad 822.
[0094] In the cell region CR, a first bonding insulating layer 811 and a first bonding pad 821 are arranged on the first contact 581 and the first interlayer insulating layer 430. A second bonding insulating layer 812 and a second bonding pad 822 are arranged on the first bonding insulating layer 811 and the first bonding pad 821. The second bonding pad 822 is superimposed on the first bonding pad 821. The second bonding pad 822 may be bonded to the upper surface of the first bonding pad 821. The second bonding insulating layer 812 may be bonded to the upper surface of the first bonding insulating layer 811. A second contact 870 is connected to the second bonding pad 822. The first bonding pad 821 and the second bonding pad 822 may include conductive materials such as metals, metal oxides, metal nitrides, metal silicides, polysilicon, conductive carbon, or combinations thereof.
[0095] In the peripheral region PR, the bit line connection contact 860 extends vertically while in contact with the bit line BL. The bit line connection contact 860 may be connected to a corresponding first bonding pad 821.
[0096] In the peripheral region PR, a second bonding pad 822 is bonded onto the first bonding pad 821. A second contact 870 is connected onto the second bonding pad 822.
[0097] The second peripheral transistor TR2 may be connected to a bit line BL via a drain contact 775 connected to the drain region 773, a second wiring 592 connected to the drain contact 775, a second contact 870 connected to the second wiring 592, a second bonding pad 822 connected to the second contact 870, a first bonding pad 821, and a bit line connection contact 860.
[0098] Referring to Figure 9, the first semiconductor structure S1 of the memory device 100 includes a first substrate 410, an element isolation layer 501, a gate structure 510, a third insulating layer 505, a bit line contact 506, a bit line BL, a lower contact plug 508, an upper contact plug 509, a landing pad 518, a capacitor 530, a support layer 550, a fourth insulating layer 521, a first contact 581, a first wiring 591, a first insulating layer 900, a second insulating layer 903, and a first interlayer insulating layer 430.
[0099] In the peripheral region PR, the first substrate 410 includes at least one trench TRE. A first insulating layer 900 and a second insulating layer 903 are disposed within the trench TRE. In one embodiment, the first insulating layer 900 and the second insulating layer 903 can surround the region in which the memory cell array 110 is located.
[0100] The first insulating layer 900 is positioned to fill the interior of the trench TRE. The sides and bottom surface of the first insulating layer 900 can be in contact with the first substrate 410. The first insulating layer 900 contains hydrogen. The first insulating layer 900 may be a layer with a higher hydrogen supply capacity compared to other layers. The first insulating layer 900 may include an oxide with a high hydrogen content. In one embodiment, the first insulating layer 900 may include high-density plasma oxide (HDP).
[0101] A second insulating layer 903 is placed on the first insulating layer 900. The second insulating layer 903 can completely cover the upper surface of the first insulating layer 900. The sides of the second insulating layer 903 can be in contact with the first substrate 410. In one embodiment, the upper surface of the second insulating layer 903 can form a substantially flat plane with the upper surface of the first substrate 410. In one embodiment, the second insulating layer 903 may contain silicon nitride.
[0102] Figure 10 shows another example of the cross-sectional structure of a memory device according to an embodiment of the present disclosure.
[0103] Referring to Figure 10, the memory device 100 includes a first semiconductor structure S1 and a second semiconductor structure S2. The first semiconductor structure S1 includes a first substrate 410, a memory cell array 110, a memory cell MC, a first insulating layer 300, and a first interlayer insulating layer 430. The second semiconductor structure S2 is placed on the first semiconductor structure S1. The second semiconductor structure S2 includes a second substrate 420, a first sense amplifier 120a, and a second interlayer insulating layer 440.
[0104] The first sense amplifier 120a includes a third peripheral transistor TR3. The third peripheral transistor TR3 is one of the transistors constituting the first sense amplifier 120a. In one embodiment, the third transistor TR3 may be a different transistor from the second transistor TR2 described with reference to Figure 6. In one embodiment, the third peripheral transistor TR3 may be located in the cell region CR.
[0105] A memory cell MC can be electrically connected to a third peripheral transistor TR3. For example, one memory cell MC may be connected to one bit line BL, and another memory cell MC may be electrically connected to the third peripheral transistor TR3 via one bit line BL.
[0106] Figure 11 shows an example of the memory device shown in Figure 10.
[0107] Referring to Figure 11, the memory device 100 includes a first semiconductor structure S1, a second semiconductor structure S2, and a bit line connection contact 760.
[0108] The first semiconductor structure S1 includes a first substrate 410, an element isolation layer 501, a gate structure 510, a third insulating layer 505, a bit line contact 506, a bit line BL, a lower contact plug 508, an upper contact plug 509, a landing pad 518, a capacitor 530, a support layer 550, a fourth insulating layer 521, a first contact 581, a first wiring 591, a liner insulating layer 502, a first insulating layer 300, a second insulating layer 503, and a first interlayer insulating layer 430.
[0109] A second semiconductor structure S2 is placed on the first semiconductor structure S1. The second semiconductor structure S2 includes a second substrate 420, a second interlayer insulating layer 440, a second contact 582, a third contact 583, a second wiring 592, a third wiring 593, a third peripheral transistor TR3, and source / drain contacts 1174 and 1175.
[0110] A third peripheral transistor TR3 is located on the second substrate 420. The third peripheral transistor TR3 includes a gate electrode 1170, a gate insulating layer 1171, a source region 1172, and a drain region 1173. The third peripheral transistor TR3 is a transistor included in the first sense amplifier 120a shown in Figure 6. In one embodiment, the third peripheral transistor TR3 may be located in the cell region CR. In one embodiment, the third peripheral transistor TR3 may be superimposed on the memory cell array 110.
[0111] The source contact 1174 is connected to the source area 1172 and the second wiring 592. The drain contact 1175 is connected to the drain area 1173 and the second wiring 592.
[0112] The third peripheral transistor TR3 may be connected to one bit line BL via a drain contact 1175 connected to the drain region 1173, a second wiring 592 connected to the drain contact 1175, and a bit line connection contact 760 connected to the second wiring 592.
[0113] Referring again to Figures 5 and 7, the memory device 100 includes a first semiconductor structure S1 and a second semiconductor structure S2 bonded onto the first semiconductor structure S1. The first semiconductor structure S1 includes a first substrate 410 and a first insulating layer 300. The second semiconductor structure S2 includes a second substrate 420, a first peripheral transistor TR1, and a second peripheral transistor TR2. The first insulating layer 300 is located within the first substrate 410 in the peripheral region PR. The first insulating layer 300 may include a high-density plasma oxide. The first peripheral transistor TR1 and the second peripheral transistor TR2 are located on the second substrate 420. The first peripheral transistor TR1 is a transistor constituting the first subword line driver 210a. The second peripheral transistor TR2 is a transistor constituting the first sense amplifier 120a.
[0114] According to embodiments of the present disclosure, the first sense amplifier 120a and the first subword line driver 210a are arranged on the second substrate 420 of the second semiconductor structure S2, thereby allowing the first insulating layer 300 to be arranged within the first substrate 410 of the first semiconductor structure S1.
[0115] On the other hand, during the manufacturing process of a memory device, damage to the first substrate 410 can cause lattice defects such as silicon dangling bonds to occur within the first substrate 410. Since silicon dangling bonds can act as traps that hinder the operation of carriers, it is necessary to remove them, and for this purpose, a passivation process may be performed. The passivation process is a process that can supply hydrogen into the substrate, and the hydrogen (H) penetrates into the first substrate 410 through the passivation process, forming Si-H bond structures and thereby reducing silicon dangling bonds. Therefore, for effective passivation, it is important that the hydrogen penetrates well into the interior of the first substrate 410.
[0116] If the first insulating layer 300, which has a high hydrogen content, is located on the capacitor 530, the hydrogen contained in the first insulating layer 300 must pass through many layers between the first substrate 410 and the first insulating layer 300 in order to penetrate into the first substrate 410. In this process, at least some of the layers between the first substrate 410 and the first insulating layer 300 will absorb the hydrogen, which may reduce the efficiency of hydrogen supply into the first substrate 410. Furthermore, the movement of hydrogen through the capacitor 530 may cause the capacitor 530 to deteriorate.
[0117] On the other hand, when the first insulating layer 300 is placed inside the first substrate 410, the hydrogen contained in the first insulating layer 300 can immediately penetrate into the first substrate 410 without passing through other layers, thus improving the hydrogen supply capacity. Therefore, degradation of memory cells due to silicon dangling bonds can be improved. In addition, when the first insulating layer 300 is placed inside the first substrate 410, there is a possibility that hydrogen will not pass through the capacitor 530. Therefore, degradation that may occur due to hydrogen passing through the capacitor 530 can be prevented.
[0118] The above description is merely illustrative of the technical concept of this disclosure, and any person with ordinary skill in the art to which this disclosure pertains may make various modifications and variations without departing from the essential characteristics of this disclosure. Furthermore, the embodiments of this disclosure are for illustrative purposes only, and not to limit the technical concept of this disclosure, and the scope of the technical concept of this disclosure is not limited by such embodiments. The scope of protection of this disclosure should be interpreted by the following claims, and all technical concepts within an equivalent scope should be interpreted as being included in the scope of rights of this disclosure.
Claims
1. A first substrate including a cell region and a peripheral region surrounding the cell region; A memory cell array disposed in the cell region of the first substrate; A second substrate on the memory cell array; Peripheral transistors arranged on the second substrate and connected to the memory cell array; A first insulating layer comprising a high-density plasma oxide, disposed in a trench located in the peripheral region of the first substrate; and A memory device comprising a second insulating layer on the first insulating layer.
2. The memory device according to claim 1, wherein the second insulating layer covers the upper surface of the first insulating layer.
3. The memory device according to claim 1, wherein the upper surface of the second insulating layer is substantially the same plane as the upper surface of the first substrate.
4. The memory device according to claim 1, wherein the second insulating layer comprises silicon nitride.
5. The memory device according to claim 1, wherein at least one of the peripheral transistors overlaps with the cell region.
6. The memory device according to claim 1, wherein the peripheral transistor constitutes a subword line driver or a sense amplifier.
7. Bit lines; and The bit line connection contact further includes a bit line connection contact that contacts the upper surface of the bit line, extends perpendicularly to the upper surface of the bit line, and penetrates the second substrate. The memory device according to claim 6, wherein the peripheral transistor constitutes the sense amplifier and is electrically connected to the bit line via the bit line connection contact.
8. The memory device according to claim 7, wherein the bit line connection contact is superimposed on the first insulating layer.
9. Word lines; and The system further includes a word line connection contact that contacts the upper surface of the word line, extends perpendicularly to the upper surface of the word line, and penetrates the second substrate. The memory device according to claim 6, wherein the peripheral transistor constitutes the subword line driver and is electrically connected to the word line via the word line connection contact.
10. First substrate; A memory cell array disposed on the first substrate; A first insulating layer comprising a high-density plasma oxide, disposed in a trench located on the first substrate and surrounding the region in which the memory cell array is disposed; and A memory device including a second insulating layer that covers the upper surface of the first insulating layer.
11. The memory device according to claim 10, wherein the upper surface of the second insulating layer is substantially the same plane as the upper surface of the first substrate.
12. The memory device according to claim 10, wherein the second insulating layer comprises silicon nitride.
13. The memory device according to claim 10, further comprising peripheral transistors arranged on and connected to the memory cell array.
14. The memory device according to claim 13, wherein the peripheral transistors constitute a subword line driver or a sense amplifier.
15. The memory device according to claim 13, wherein at least one of the peripheral transistors overlaps with the region in which the memory cell array is arranged.
16. A memory device comprising a first semiconductor structure and a second semiconductor structure bonded onto the first semiconductor structure, The first semiconductor structure is A first substrate including a cell region and a peripheral region surrounding the cell region; A memory cell array disposed in the cell region of the first substrate; A first insulating layer disposed in the peripheral region of the first substrate; and It includes a second insulating layer that covers the upper surface of the first insulating layer, The second semiconductor structure is Second substrate; and It includes peripheral transistors arranged on the second substrate and connected to the memory cell array, A memory device in which at least one of the peripheral transistors is superimposed on the cell region.
17. The memory device according to claim 16, wherein at least one of the peripheral transistors is superimposed on the peripheral region on the second substrate.
18. The memory device according to claim 16, wherein the first insulating layer comprises a high-density plasma oxide.
19. A method for manufacturing a memory device comprising a first semiconductor structure including a memory cell array and a second semiconductor structure including peripheral transistors, A step of forming a trench in the peripheral region of a first substrate, which includes a cell region and a peripheral region surrounding the cell region; The step of forming a first insulating layer containing a high-density plasma oxide within the trench; The steps of forming the memory cell array in the cell region of the first substrate; and A method for manufacturing a memory device, comprising the step of forming peripheral transistors on the memory cell array so as to be connected to the memory cell array.
20. A method for manufacturing a memory device according to claim 19, further comprising the step of forming a second insulating layer on the first insulating layer after the step of forming the first insulating layer.
21. The second semiconductor structure further includes a second substrate, The method for manufacturing a memory device according to claim 19, wherein the peripheral transistors are formed on the second substrate.
22. A method for manufacturing a memory device according to claim 19, further comprising the step of bonding the second semiconductor structure onto the first semiconductor structure.