Wiring board and method for manufacturing the same

Abstract

In a wiring board having a glass core layer, the fracture of the sides of the core layer is suppressed. [Solution] The wiring board 1 comprises a glass core layer 10 having one surface 10a and the other surface 10b, a first laminate 51 including a wiring layer and an insulating layer provided on one surface 10a of the core layer 10, and a first resin part 41. The first outer peripheral part 10S of one surface 10a of the core layer 10 is exposed from the first laminate 51, and the first resin part 41 covers the side surface 10c of the core layer 10.

Description

Technical Field

[0001] The present invention relates to a wiring board and a method for manufacturing the same.

Background Art

[0002] A wiring board having a core layer and a laminate including wiring layers and insulating layers alternately laminated on the core layer is known (Patent Document 1). In the manufacturing process of such a wiring board, for example, a core layer having a plurality of wiring regions that are separated into individual wiring boards and a cutting region to be cut during separation is prepared, and a laminate is formed on the upper surface of the core layer. Then, for example, a separation groove is formed in the laminate located in the cutting region, the core layer is cut at the center position in the width direction of the groove bottom of the separation groove, and individual wiring boards are produced.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In some cases, a glass core layer is used for a wiring board. In this case, after cutting for fragmentation, there is a risk of breakage such as chipping or cracking on the side surface of the glass core layer.

[0005] The present invention has been made in view of the above points, and an object thereof is to suppress breakage of the side surface of the core layer in a wiring board having a glass core layer.

Means for Solving the Problems

[0006] This wiring board comprises a glass core layer having one side and the other side, a first laminate including a wiring layer and an insulating layer provided on one side of the core layer, and a first resin portion, wherein the first outer periphery of one side of the core layer is exposed from the first laminate, and the first resin portion covers the side surface of the core layer. [Effects of the Invention]

[0007] According to the disclosed technology, in a wiring substrate having a glass core layer, it is possible to suppress fracture of the sides of the core layer. [Brief explanation of the drawing]

[0008] [Figure 1] This figure illustrates a wiring board according to the first embodiment. [Figure 2] This is a diagram (part 1) illustrating the manufacturing process of a wiring board according to the first embodiment. [Figure 3] This is a diagram (part 2) illustrating the manufacturing process of a wiring board according to the first embodiment. [Figure 4] This is a diagram (part 3) illustrating the manufacturing process of a wiring board according to the first embodiment. [Figure 5] This is a diagram (part 4) illustrating the manufacturing process of a wiring board according to the first embodiment. [Figure 6] This is a cross-sectional view illustrating a wiring board according to a modified example 1 of the first embodiment. [Figure 7] This is a cross-sectional view illustrating a wiring board according to a modified example 2 of the first embodiment. [Figure 8] This figure illustrates the manufacturing process of a wiring board according to a modified example 2 of the first embodiment. [Figure 9] This is a cross-sectional view illustrating a wiring board according to a modified example 3 of the first embodiment. [Figure 10] This is a cross-sectional view illustrating a wiring board according to a modified example 4 of the first embodiment. [Figure 11] This is a cross-sectional view illustrating a semiconductor device according to the second embodiment. [Modes for carrying out the invention]

[0009] The embodiments for carrying out the invention will be described below with reference to the drawings. In each drawing, the same reference numerals are used for identical components, and redundant explanations may be omitted.

[0010] <First Embodiment> [Structure of the wiring board according to the first embodiment] Figure 1 illustrates a wiring board according to the first embodiment, where Figure 1(a) is a plan view and Figure 1(b) is a cross-sectional view along line AA in Figure 1(a).

[0011] Referring to Figure 1, the wiring board 1 has a core layer 10 having one surface 10a and the other surface 10b which is the opposite surface of the first surface 10a, a first laminate 51 including wiring layers and insulating layers alternately laminated on one surface 10a of the core layer 10, a second laminate 52 including wiring layers and insulating layers alternately laminated on the other surface 10b of the core layer 10, and a first resin part 41. The wiring board 1 may have external connection terminals 18. The wiring board 1 can be formed, for example, in a rectangular shape in plan view.

[0012] The first laminate 51 has a wiring layer 12, an insulating layer 13, a wiring layer 14, an insulating layer 15, a wiring layer 16, and a solder resist layer 17, which are sequentially laminated on one surface 10a of the core layer 10. The second laminate 52 has a wiring layer 22, an insulating layer 23, a wiring layer 24, an insulating layer 25, a wiring layer 26, and a solder resist layer 27, which are sequentially laminated on the other surface 10b of the core layer 10. The first laminate 51 can be formed, for example, in a rectangular shape in plan view. The corners of the first laminate 51 can be formed, for example, in a curved shape. The second laminate 52 can be formed, for example, in a rectangular shape in plan view. The corners of the second laminate 52 can be formed, for example, in a curved shape.

[0013] In the first embodiment, for the sake of convenience, the side of the solder resist layer 17 of the wiring board 1 is regarded as the upper side or one side, and the side of the solder resist layer 27 is regarded as the lower side or the other side. Also, the surface on the side of the solder resist layer 17 of each part is regarded as one surface or the upper surface, and the surface on the side of the solder resist layer 27 is regarded as the other surface or the lower surface. However, the wiring board 1 can be used in an upside-down state or arranged at an arbitrary angle. Also, the plan view means viewing the object from the normal direction of one surface 10a of the core layer 10, and the planar shape means the shape of the object viewed from the normal direction of one surface 10a of the core layer 10.

[0014] The core layer 10 can be formed, for example, in a rectangular shape in plan view. The core layer 10 is made of glass. The type of glass constituting the core layer 10 is not limited, but for example, non-alkali glass, quartz glass, borosilicate glass, etc. can be used. The thickness of the core layer 10 is, for example, about 100 to 1000 μm. The core layer 10 is provided with through-holes 10x penetrating in the thickness direction. The planar shape of the through-holes 10x is, for example, circular. The diameter of the through-holes 10x can be, for example, 100 μm or more and 500 μm or less.

[0015] The first outer peripheral portion 10s of one surface 10a of the core layer 10 is exposed from the first laminate 51. The first outer peripheral portion 10s is located in a frame shape outside the first laminate 51 in plan view. The width of the first outer peripheral portion 10s can be, for example, 50 μm or more and 300 μm or less.

[0016] The side surface 51c of the first laminate 51 is composed of the side surface of the insulating layer 13, the side surface of the insulating layer 15, and the side surface of the solder resist layer 17. The side surface 51c of the first laminate 51 is inclined, for example, in a direction away from the side surface 10c of the core layer 10 as it goes toward the solder resist layer 17 in cross-sectional view. The side surface 51c of the first laminate 51 may be perpendicular to one surface 10a of the core layer 10.

[0017] The first resin part 41 covers the side surface 10c of the core layer 10. In plan view, the first resin part 41 is located in a frame shape outside the side surface 10c of the core layer 10. The distance from the side surface 10c of the core layer 10 to the side surface of the first resin part 41 is constant regardless of the position in the thickness direction of the core layer 10, for example. The distance from the side surface 10c of the core layer 10 to the side surface of the first resin part 41 may vary depending on the position in the thickness direction of the core layer 10. The distance from the side surface 10c of the core layer 10 to the side surface of the first resin part 41 is, for example, 10 μm or more and 50 μm or less. As the material of the first resin part 41, for example, a photosensitive insulating resin mainly composed of an epoxy resin or a polyimide resin can be used.

[0018] The second outer peripheral part 10t of the other surface 10b of the core layer 10 is exposed from the second laminate 52. In plan view, the second outer peripheral part 10t is located in a frame shape outside the second laminate 52. The width of the second outer peripheral part 10t can be, for example, 50 μm or more and 300 μm or less.

[0019] The side surface 52c of the second laminate 52 is composed of the side surface of the insulating layer 23, the side surface of the insulating layer 25, and the side surface of the solder resist layer 27. The side surface 52c of the second laminate 52 is inclined in a direction away from the side surface 10c of the core layer 10 as it goes toward the solder resist layer 27 side, for example, in cross-sectional view. The side surface 52c of the second laminate 52 may be perpendicular to the other surface 10b of the core layer 10.

[0020] The wiring layer 12 is disposed on one surface 10a of the core layer 10. Also, the wiring layer 22 is disposed on the other surface 10b of the core layer 10. The wiring layer 12 and the wiring layer 22 are electrically connected by a through-wiring 11 formed in the through-hole 10x. The wiring layers 12 and 22 are each patterned into a predetermined planar shape. As the material of the wiring layers 12 and 22 and the through-wiring 11, for example, copper (Cu) or the like can be used. The thickness of the wiring layers 12 and 22 is, for example, about 10 to 40 μm. Note that the wiring layer 12, the wiring layer 22, and the through-wiring 11 may be integrally formed.

[0021] The insulating layer 13 is an interlayer insulating layer that is arranged on one surface 10a of the core layer 10 and covers the wiring layer 12. As the material for the insulating layer 13, for example, an insulating resin mainly composed of epoxy resin or polyimide resin can be used. The thickness of the insulating layer 13 can be, for example, about 30 to 40 μm. The insulating layer 13 may contain fillers such as silica (SiO2).

[0022] The insulating layer 13 has via holes 13x that penetrate the insulating layer 13 and expose the upper surface of the wiring layer 12. The via holes 13x can be in the shape of an inverted truncated cone recess, where the diameter of the opening on the insulating layer 15 side is larger than the diameter of the bottom surface of the opening formed by the upper surface of the wiring layer 12.

[0023] The wiring layer 14 is formed on one side of the insulating layer 13. The wiring layer 14 comprises via wiring filled in via holes 13x and a wiring pattern formed on the upper surface of the insulating layer 13. The wiring pattern is electrically connected to the wiring layer 12 via the via wiring. The material of the wiring layer 14 and the thickness of the wiring pattern can be the same as, for example, the wiring layer 12.

[0024] The insulating layer 15 is formed so as to cover the wiring layer 14 on the upper surface of the insulating layer 13. The material and thickness of the insulating layer 15 can be the same as, for example, the insulating layer 13. The insulating layer 15 may contain fillers such as silica (SiO2).

[0025] The insulating layer 15 has via holes 15x that penetrate the insulating layer 15 and expose the upper surface of the wiring layer 14. The via holes 15x can be inverted truncated cone-shaped recesses in which the diameter of the opening that opens to the solder resist layer 17 side is larger than the diameter of the bottom surface of the opening formed by the upper surface of the wiring layer 14.

[0026] The wiring layer 16 is formed on one side of the insulating layer 15. The wiring layer 16 consists of via wiring filled in via holes 15x and a pad formed on the upper surface of the insulating layer 15. The pad is electrically connected to the wiring layer 14 via the via wiring. The material of the wiring layer 16 and the thickness of the pad can be the same as, for example, the same as the wiring layer 12. The thickness of the pad may be greater than the thickness of the wiring layer 12. In addition to the pad, the wiring layer 16 may also include a wiring pattern.

[0027] The solder resist layer 17 is a protective insulating layer located on the outermost side of the wiring substrate 1, and is formed to cover the wiring layer 16 on the upper surface of the insulating layer 15. The solder resist layer 17 has an opening 17x, and a portion of the upper surface of the wiring layer 16 is exposed within the opening 17x. The planar shape of the opening 17x can be, for example, circular. The wiring layer 16 exposed within the opening 17x can be used, for example, as a pad for electrically connecting to electronic components such as semiconductor chips. The solder resist layer 17 can be formed from, for example, a photosensitive epoxy insulating resin or an acrylic insulating resin. The thickness of the solder resist layer 17 is, for example, about 15 to 35 μm.

[0028] Furthermore, a metal layer may be formed on the surface of the wiring layer 16 exposed within the opening 17x, or an organic coating may be formed by applying an anti-oxidation treatment such as OSP (Organic Solderability Preservative) treatment. Examples of metal layers include an Au layer, a Ni / Au layer (a metal layer in which Ni and Au layers are stacked in that order), a Ni / Pd / Au layer (a metal layer in which Ni, Pd, and Au layers are stacked in that order), and a Sn layer.

[0029] If necessary, external connection terminals 18 may be provided on the wiring layer 16 exposed within the opening 17x. The external connection terminals 18 are, for example, solder bumps. As the material for the solder bumps, for example, alloys containing Pb, alloys of Sn and Cu, alloys of Sn and Ag, alloys of Sn, Ag and Cu, etc. can be used.

[0030] The insulating layer 23 is an interlayer insulating layer located on the other surface 10b of the core layer 10 and covering the wiring layer 22. The material and thickness of the insulating layer 23 can be the same as, for example, the insulating layer 13. The insulating layer 23 may contain fillers such as silica (SiO2).

[0031] The insulating layer 23 has via holes 23x that penetrate the insulating layer 23 and expose the lower surface of the wiring layer 22. The via holes 23x can be frustoconical recesses in which the diameter of the opening on the insulating layer 25 side is larger than the diameter of the bottom surface of the opening formed by the lower surface of the wiring layer 22.

[0032] The wiring layer 24 is formed on the other side of the insulating layer 23. The wiring layer 24 comprises via wiring filled in via holes 23x and a wiring pattern formed on the underside of the insulating layer 23. The wiring pattern is electrically connected to the wiring layer 22 via the via wiring. The material and thickness of the wiring layer 24 can be the same as, for example, the wiring layer 12.

[0033] The insulating layer 25 is formed on the underside of the insulating layer 23 so as to cover the wiring layer 24. The material and thickness of the insulating layer 25 can be the same as, for example, the insulating layer 13. The insulating layer 25 may contain fillers such as silica (SiO2).

[0034] The insulating layer 25 has via holes 25x that penetrate the insulating layer 25 and expose the lower surface of the wiring layer 24. The via holes 25x can be frustoconical recesses in which the diameter of the opening that opens to the solder resist layer 27 side is larger than the diameter of the bottom surface of the opening formed by the lower surface of the wiring layer 24.

[0035] The wiring layer 26 is formed on the other side of the insulating layer 25. The wiring layer 26 comprises via wiring filled in via holes 25x and a wiring pattern formed on the underside of the insulating layer 25. The wiring pattern is electrically connected to the wiring layer 24 via the via wiring. The material and thickness of the wiring layer 26 can be the same as, for example, the wiring layer 12.

[0036] The solder resist layer 27 is a protective insulating layer located on the outermost side of the wiring board 1, and is formed to cover the wiring layer 26 on the underside of the insulating layer 25. The material and thickness of the solder resist layer 27 can be the same as, for example, the solder resist layer 17. The solder resist layer 27 has an opening 27x, and a portion of the underside of the wiring layer 26 is exposed within the opening 27x. The planar shape of the opening 27x can be, for example, circular. The wiring layer 26 exposed within the opening 27x can be used as a pad for electrically connecting to a mounting board such as a motherboard. If necessary, the aforementioned metal layer may be formed on the underside of the wiring layer 26 exposed within the opening 27x, or an anti-oxidation treatment such as OSP treatment may be applied.

[0037] [Manufacturing method for wiring boards] Figures 2 to 5 illustrate the manufacturing process of a wiring board according to the first embodiment. Figure 2 is a plan view, and Figures 3 and 4 are partial cross-sectional views corresponding to the position of line BB in Figure 2. Figure 5 is a schematic diagram illustrating an example of a preferred method for forming the first resin part.

[0038] First, in the process shown in Figures 2 and 3(a), a glass core layer 10 is prepared. The core layer 10 has multiple wiring regions R that are separated into individual pieces to form a wiring substrate, and cutting regions D that are cut when the core is separated into individual pieces. In Figures 2 and 3(a), the cutting regions D are shown as lines, but they may be regions with a certain width. Next, through holes 10x that penetrate from one surface 10a to the other surface 10b are formed in the core layer 10 located in the wiring regions R.

[0039] The through-hole 10x can be formed, for example, by wet etching. Examples of etching solutions used in this process include hydrofluoric acid and strong alkaline solutions. If the through-hole 10x is formed by drilling, there is a risk of cracks occurring in the glass constituting the core layer 10, but by using wet etching, the through-hole 10x can be formed without cracking the glass.

[0040] Next, in the process shown in Figures 3(b) to 3(d), a first laminate 51 is formed on one surface 10a of the core layer 10, including alternately stacked wiring layers and insulating layers. A second laminate 52 is also formed on the other surface 10b of the core layer 10, including alternately stacked wiring layers and insulating layers. Specifically, as shown in Figure 3(b), first, wiring layers 12 are placed in each wiring region R on one surface 10a of the core layer 10, and wiring layers 22 are placed in each wiring region R on the other surface of the core layer 10, forming through-holes 10x. For example, a seed layer (copper, etc.) is formed to cover one surface 10a of the core layer 10, the other surface 10b, and the inner wall surface of the through-holes 10x by electroless plating or sputtering, and an electroplated layer (copper, etc.) is formed on the seed layer by electroplating using the seed layer as a power supply layer. As a result, the through-holes 10x are filled with an electroplated layer formed on the seed layer, and a conductive layer is formed on one surface 10a and the other surface 10b of the core layer 10, with the seed layer and the electroplated layer laminated together. Next, the conductive layer is patterned into a predetermined planar shape by subtractive method or the like to form wiring layers 12 and 22.

[0041] Next, as shown in Figure 3(c), insulating layers 13 and 23, and wiring layers 14 and 24 are formed. First, insulating layers 13 are placed in each wiring region R and each cutting region D on one surface 10a of the core layer 10 to cover the upper surface of the wiring layer 12. Specifically, for example, a semi-cured film-like epoxy resin is laminated onto one surface 10a of the core layer 10 to cover the wiring layer 12, and then cured to form the insulating layer 13. Alternatively, instead of laminating with a film-like epoxy resin, a liquid or paste-like epoxy resin may be applied and then cured to form the insulating layer 13. The material and thickness of the insulating layer 13 are as described above. Similarly, insulating layers 23 are placed in each wiring region R and each cutting region D on the other surface 10b of the core layer 10 to cover the lower surface of the wiring layer 22.

[0042] Next, via holes 13x are formed in the insulating layer 13, penetrating the insulating layer 13 and exposing the upper surface of the wiring layer 12. Similarly, via holes 23x are formed in the insulating layer 23, penetrating the insulating layer 23 and exposing the lower surface of the wiring layer 22. The via holes 13x and 23x can be formed, for example, by a laser processing method using a CO2 laser. After forming the via holes 13x and 23x, it is preferable to perform a desmear treatment to remove any resin residue adhering to the surfaces of the wiring layers 12 and 22 exposed at the bottom of the via holes 13x and 23x.

[0043] Next, a wiring layer 14 is formed on one side of the insulating layer 13. The wiring layer 14 consists of via wiring filled in via holes 13x and a wiring pattern formed on the upper surface of the insulating layer 13. The wiring layer 14 is electrically connected to the wiring layer 12 exposed at the bottom of the via holes 13x. Similarly, a wiring layer 24 is formed on the other side of the insulating layer 23. The wiring layer 24 consists of via wiring filled in via holes 23x and a wiring pattern formed on the lower surface of the insulating layer 23. The wiring layer 24 is electrically connected to the wiring layer 22 exposed at the bottom of the via holes 23x. The materials and thickness of the wiring patterns of the wiring layers 14 and 24 can be the same as those of the wiring layer 12, for example. The wiring layers 14 and 24 are formed, for example, by a semi-additive method.

[0044] Next, as shown in Figure 3(d), insulating layers 15 and 25, wiring layers 16 and 26, solder resist layers 17 and 27, and external connection terminals 18 are formed. First, the same process as in Figure 3(c) is repeated to form insulating layers 15 and 25 and wiring layers 16 and 26. Next, a solder resist layer 17 is formed on the upper surface of insulating layer 15 so as to cover the wiring layer 16. Also, a solder resist layer 27 is formed on the lower surface of insulating layer 25 so as to cover the wiring layer 26. The solder resist layer 17 can be formed, for example, by applying a liquid or paste-like photosensitive epoxy insulating resin to the upper surface of insulating layer 15 by screen printing, roll coating, or spin coating so as to cover the wiring layer 16. Alternatively, for example, a film-like photosensitive epoxy insulating resin may be laminated to the upper surface of insulating layer 15 so as to cover the wiring layer 16. The method for forming the solder resist layer 27 is the same as for the solder resist layer 17. Subsequently, the solder resist layers 17 and 27 are exposed and developed to form an opening 17x in the solder resist layer 17 that exposes the wiring layer 16. An opening 27x is also formed in the solder resist layer 27 that exposes a portion of the lower surface of the wiring layer 26. If necessary, an external connection terminal 18 may be provided on the wiring layer 16 exposed within the opening 17x. The external connection terminal 18 is, for example, a solder bump formed by solder reflow.

[0045] Next, in the process shown in Figure 4(a), a first groove 51x is formed that penetrates the first laminate 51 so as to straddle the cutting region D, exposing one surface 10a of the core layer 10. The first groove 51x is formed along the cutting region D and covers the entire cutting region D. In each wiring region R, the one surface 10a of the core layer 10 exposed in the first groove 51x is the portion that will become the first outer periphery 10s after fragmentation. Also, a second groove 52x is formed that penetrates the second laminate 52 so as to straddle the cutting region D, exposing the other surface 10b of the core layer 10. The second groove 52x is formed along the cutting region D and covers the entire cutting region D. In each wiring region R, the other surface 10b of the core layer 10 exposed in the second groove 52x is the portion that will become the second outer periphery 10t after fragmentation. The first groove 51x and the second groove 52x can be formed, for example, by irradiating the first laminate 51 and the second laminate 52 with laser light of an absorbing wavelength. When irradiating with laser light, the width of the first groove 51x and the second groove 52x increases, for example, as it moves away from the core layer 10. By adjusting the irradiation area of ​​the laser light when forming the first groove 51x and the second groove 52x, the corners of the first laminate 51 and the second laminate 52 can be formed in a curved shape. By forming the corners of the first laminate 51 and the second laminate 52 in a curved shape, it is possible to prevent the insulation layer from being lost at the corners. The first groove 51x and the second groove 52x may also be formed using a cutting blade.

[0046] After forming the first groove 51x and the second groove 52x, a laser beam L is irradiated along the cutting region D onto one surface 10a of the core layer 10 exposed within the first groove 51x. By focusing the laser beam into the core layer 10, a modified layer that serves as the starting point for the split is formed inside the core layer 10 located below the cutting region D. In this step, a laser beam with a wavelength that is transparent to the core layer 10 is irradiated.

[0047] Next, in the process shown in Figure 4(b), the core layer 10 is cut in the cutting region D shown in Figure 4(a) to produce multiple individual structures 1S. By cutting in the cutting region D, the first groove 51x is divided, and in each structure 1S, one surface 10a of the core layer 10 that was exposed within the first groove 51x becomes the first outer periphery 10s. Also, the second groove 52x is divided, and in each structure 1S, one surface 10a of the core layer 10 that was exposed within the second groove 52x becomes the second outer periphery 10t.

[0048] Cutting can be performed, for example, by attaching the structure shown in Figure 4(a) to an expandable tape and expanding the expandable tape in the direction of the outer circumference of the structure. By expanding the expandable tape, a force in the direction of the expansion of the expandable tape can be applied to the modified portion of the core layer 10. As a result, the core layer 10 is divided along the modified layer that serves as the starting point for the division.

[0049] Alternatively, instead of expanding the expandable tape, the core layer 10 may be divided by applying force near the cutting area D with, for example, a roller or a rod-shaped pressing member.

[0050] Next, in the process shown in Figure 4(c), a first resin portion 41 is formed to cover the side surface 10c of the core layer 10 of each individual structure 1S. This completes the wiring board 1. The first resin portion 41 may be formed by any method, but an example of a preferred formation method will be described with reference to Figure 5.

[0051] First, a fixing jig 300 is prepared as shown in Figure 5(a). The fixing jig 300 is, for example, an L-shaped jig having an elongated bottom and sides on which multiple structures 1S can be placed. Next, the multiple structures 1S manufactured in the process shown in Figure 4(b) are fixed to the fixing jig 300 so that they are spaced apart from each other. At this time, one of the four sides 10c of the core layer 10 constituting each structure 1S is in contact with the bottom surface of the fixing jig 300, and the side 10c adjacent to the side 10c in contact with the bottom surface is in contact with the side of the fixing jig 300. In this state, two sides of the core layer 10 of each structure 1S that are not in contact with the bottom surface or the side of the fixing jig 300 are exposed from the fixing jig 300.

[0052] Next, as shown in Figures 5(b) and 5(c), a roll of film-like photosensitive resin 410 and a heat-seal roller 510 are prepared. The photosensitive resin 410 and the heat-seal roller 510 are then positioned so as to be in contact with two sides 10c of the core layer 10 exposed from the fixing jig 300, and moved along the sides 10c. As a result, the photosensitive resin 410 heated by the heat-seal roller is laminated to the two sides 10c of the core layer 10. The photosensitive resin 410 can be laminated to two sides 10c of multiple core layers 10 at once.

[0053] Next, as shown in Figure 5(d), the roll of photosensitive resin 410 and the heat-press roller 510 are moved to a position away from the fixing jig 300, and then the photosensitive resin 410 covering the two sides 10c of the core layer 10 is exposed. For exposure, for example, a direct drawing exposure machine that can expose without using a mask can be used. Next, the exposed photosensitive resin 410 is developed and then heated to cure it, so that the first resin part 41 covering the two sides 10c of the core layer 10 is formed, as shown in Figure 5(e). For example, a negative-type photosensitive resin can be used as the photosensitive resin 410. When a negative-type photosensitive resin is used as the photosensitive resin 410, the first resin part 41 can be formed by exposing the portion of the photosensitive resin 410 that covers the two sides 10c of the core layer 10, and then developing it.

[0054] Next, a first resin portion 41 is formed to cover the other two sides 10c of the core layer 10 in the same manner as in Figures 5(a) to 5(e). This completes multiple wiring boards 1. This method allows for the formation of the first resin portion 41 on multiple structures 1S in a single step, thereby improving the manufacturing efficiency of the wiring boards 1.

[0055] In this way, the side surface 10c of the core layer 10 of the wiring board 1 is covered by the first resin part 41. This makes it possible to suppress damage such as chipping or cracking on the side surface 10c of the core layer 10.

[0056] <Variations of the first embodiment> Modifications of the first embodiment include examples where the shape of the first resin part differs from that of the first embodiment, and examples where a second resin part and a third resin part are included in addition to the first resin part. In modifications of the first embodiment, descriptions of components that are the same as those described in the previously described embodiments may be omitted.

[0057] Figure 6 is a cross-sectional view illustrating a wiring board according to Modification 1 of the First Embodiment. Referring to Figure 6, the wiring board 1A differs from the wiring board 1 (see Figure 1(b), etc.) in that the first resin part 41 is replaced by the first resin part 41A.

[0058] The first resin portion 41A extends from the side surface 10c of the core layer 10 and covers at least a portion of the first outer peripheral portion 10s and at least a portion of the second outer peripheral portion 10t. The first resin portion 41A may cover the entire first outer peripheral portion 10s and the entire second outer peripheral portion 10t. The first resin portion 41A can be formed, for example, from a photosensitive insulating resin similar to that of the first resin portion 41.

[0059] To form the first resin portion 41A, for example, when exposing the photosensitive resin 410 in the process shown in Figure 5(d), in addition to the portion in contact with the side surface 10c of the core layer 10, the portions on both sides of the portion in contact with the side surface 10c of the core layer 10 are exposed. In other words, a wider area of ​​the photosensitive resin 410 than the width of the side surface 10c of the core layer 10 is exposed. As a result, in the process shown in Figure 5(e), the portions on both sides of the portion in contact with the side surface 10c of the core layer 10 extend from the side surface 10c of the core layer 10, forming the first resin portion 41A that covers at least a part of the first outer peripheral portion 10s and at least a part of the second outer peripheral portion 10t. By increasing the thickness of the photosensitive resin 410, it is also possible to form the first resin portion 41A that covers the entire first outer peripheral portion 10s and the entire second outer peripheral portion 10t.

[0060] Thus, in the wiring board 1A, the first resin portion 41 covers the side surface 10c of the core layer 10 and extends from the side surface 10c of the core layer 10 to cover at least a portion of the first outer peripheral portion 10s and at least a portion of the second outer peripheral portion 10t. This suppresses damage such as chipping or cracking that occurs on the side surface 10c of the core layer 10, at least a portion of the first outer peripheral portion 10s, and at least a portion of the second outer peripheral portion 10t.

[0061] Figure 7 is a cross-sectional view illustrating a wiring board according to a modified example 2 of the first embodiment. Referring to Figure 7, the wiring board 1B differs from the wiring board 1 (see Figure 1(b), etc.) in that it has a second resin part 42 and a third resin part 43 in addition to the first resin part 41.

[0062] The second resin portion 42 covers the first outer periphery 10s and the side surface 51c of the first laminate 51. In the illustrated example, the second resin portion 42 covers the first outer periphery 10s and the first outer periphery 10s side of the side surface 51c of the first laminate 51. The upper surface of the second resin portion 42 may have a region where the height from one surface 10a of the core layer 10 decreases as you move from the side surface 51c of the first laminate 51 toward the side surface 10c of the core layer 10. For example, the upper surface of the second resin portion 42 has the lowest height from one surface 10a of the core layer 10 above the side surface 10c of the core layer 10.

[0063] The third resin portion 43 covers the second outer periphery 10t and the side surface 52c of the second laminate 52. In the illustrated example, the third resin portion 43 covers the second outer periphery 10t and the side surface 52c of the second laminate 52 on the side of the second outer periphery 10t. The lower surface of the third resin portion 43 may have a region where the height from the other surface 10b of the core layer 10 decreases as you move from the side surface 52c of the second laminate 52 towards the side surface 10c of the core layer 10. For example, the lower surface of the third resin portion 43 is lowest in height from the other surface 10b of the core layer 10 below the side surface 10c of the core layer 10.

[0064] To manufacture the wiring board 1B having the second resin part 42 and the third resin part 43, the process shown in Figure 8(a) is performed between the process of forming the modified layer shown in Figure 4(a) and the cutting process shown in Figure 4(b), and then the process shown in Figure 8(b) is performed. Then, the same process as in Figure 4(c) is performed. The process shown in Figure 8(b) is the same as the process in Figure 4(b), but it differs from the process shown in Figure 4(b), in that the second resin part 42, the core layer 10, and the third resin part 43 are cut in the cutting region D.

[0065] In the process shown in Figure 8(a), a second resin portion 42 is formed that covers one surface 10a of the core layer 10 exposed within the first groove 51x, and the side of the inner surface of the core layer 10 facing one surface 10a. A third resin portion 43 is also formed that covers the other surface 10b of the core layer 10 exposed within the second groove 52x, and the side of the inner surface of the core layer 10 facing the other surface 10b. For example, the second resin portion 42 can be formed by applying uncured resin into the first groove 51x by potting and curing it. The third resin portion 43 can be formed in the same manner. The second resin portion 42 and the third resin portion 43 are, for example, thinnest at the point where they overlap with the cutting region D in a plan view, and become thicker as they move away from the cutting region D in a plan view.

[0066] As the material for the second resin part 42 and the third resin part 43, for example, a photosensitive insulating resin mainly composed of epoxy resin or polyimide resin can be used. It is preferable that the second resin part 42 and the third resin part 43 do not contain fillers. Alternatively, it is preferable that they contain less filler than the resin of the insulating layer. This makes it easier to cut the second resin part 42 and the third resin part 43 when cutting the second resin part 42, the core layer 10, and the third resin part 43 in the cutting region D in the process shown in Figure 8(b).

[0067] Furthermore, the thickness of the thinnest part of the second resin portion 42 in the lamination direction of the first laminate 51 can be, for example, 10 μm or more and 50 μm or less. The thickness of the thinnest part of the third resin portion 43 in the lamination direction of the second laminate 52 can be, for example, 10 μm or more and 50 μm or less. By making the thickness of the thinnest parts of the second resin portion 42 and the third resin portion 43 10 μm or more, the first outer peripheral portion 10s exposed from the first laminate 51 can be sufficiently protected by the second resin portion 42, and the second outer peripheral portion 10t exposed from the second laminate 52 can be sufficiently protected by the third resin portion 43. In addition, by making the thickness of the thinnest parts of the second resin portion 42 and the third resin portion 43 50 μm or less, the cutting of the second resin portion 42 and the third resin portion 43 becomes easier when cutting the second resin portion 42, the core layer 10, and the third resin portion 43 in the cutting region D in the process shown in Figure 8(b).

[0068] It is preferable that the first resin part 41, the second resin part 42, and the third resin part 43 are made of a photosensitive insulating resin with the same resin as its main component. For example, it is preferable that the first resin part 41, the second resin part 42, and the third resin part 43 all use a photosensitive insulating resin with epoxy resin as its main component. Alternatively, it is preferable that the first resin part 41, the second resin part 42, and the third resin part 43 all use a photosensitive insulating resin with polyimide resin as its main component. This improves the adhesion between the first resin part 41 and the second resin part 42 and the third resin part 43.

[0069] In this way, in the wiring board 1B, the first resin part 41 covers the side surface 10c of the core layer 10. The second resin part 42 covers the first outer peripheral part 10s, and the third resin part 43 covers the second outer peripheral part 10t. This makes it possible to suppress damage such as chipping or cracking that occurs in the side surface 10c, the first outer peripheral part 10s, and the second outer peripheral part 10t of the core layer 10.

[0070] Figure 9 is a cross-sectional view illustrating a wiring board according to a modification 3 of the first embodiment. Referring to Figure 9, the wiring board 1C differs from the wiring board 1B (see Figure 7, etc.) in that the first resin part 41 is replaced by the first resin part 41B.

[0071] The first resin portion 41B extends from the side surface 10c of the core layer 10 and covers at least a portion of the side surface of the second resin portion 42 and at least a portion of the side surface of the third resin portion 43. The first resin portion 41B may cover all of the side surface of the second resin portion 42 and all of the side surface of the third resin portion 43. The first resin portion 41B can be formed, for example, from a photosensitive insulating resin similar to that of the first resin portion 41.

[0072] Thus, in the wiring board 1C, the first resin part 41B covers the side surface 10c of the core layer 10. The second resin part 42 covers the first outer peripheral part 10s, and the third resin part 43 covers the second outer peripheral part 10t. Furthermore, the first resin part 41B extends from the side surface 10c of the core layer 10 and covers at least a portion of the side surface of the second resin part 42 and at least a portion of the side surface of the third resin part 43. As a result, the corners formed by the side surface 10c of the core layer 10 and the first outer peripheral part 10s, and the corners formed by the side surface 10c of the core layer 10 and the second outer peripheral part 10t are not exposed to the outside of the wiring board 1C. This further suppresses damage such as chipping or cracking of the side surface 10c, the first outer peripheral part 10s, and the second outer peripheral part 10t of the core layer 10. In addition, the first resin part 41B can be tightly fitted to the second resin part 42 and the third resin part 43.

[0073] Figure 10 is a cross-sectional view illustrating a wiring board according to a modified example 4 of the first embodiment. Referring to Figure 10, the wiring board 1D differs from the wiring board 1B (see Figure 7, etc.) in that the second resin part 42 and the third resin part 43 are replaced with the second resin part 42A and the third resin part 43A.

[0074] The second resin portion 42A, like the second resin portion 42, covers the first outer peripheral portion 10s and the side surface 51c of the first laminate 51 on the first outer peripheral portion 10s side. The upper surface of the second resin portion 42A is flat and, for example, parallel to one surface 10a of the core layer 10. The thickness of the second resin portion 42A in the lamination direction of the first laminate 51 is constant and can be, for example, 10 μm or more and 100 μm or less.

[0075] The third resin portion 43A, like the third resin portion 43, covers the second outer periphery 10t and the side surface 52c of the second laminate 52 on the second outer periphery 10t side. The lower surface of the third resin portion 43A is flat and, for example, parallel to the other surface 10b of the core layer 10. The thickness of the third resin portion 43A in the lamination direction of the second laminate 52 is constant and can be, for example, 10 μm or more and 100 μm or less.

[0076] The second resin part 42A and the third resin part 43A can be formed, for example, from the same photosensitive insulating resin as the second resin part 42 and the third resin part 43. In this application, "parallel" means that an error of ±10 degrees from strictly parallel is permitted. Also, "constant thickness" means that the thickness of the thickest part is +10% or less of the thickness of the thinnest part.

[0077] To form the second resin portion 42A and the third resin portion 43A, for example, in the process shown in Figure 8(a), a semi-cured film-like insulating resin cut to an appropriate size is placed in the first groove 51x and the second groove 52x and cured. After that, the same process as shown in Figure 8(b) and Figure 4(c) can be carried out.

[0078] Thus, the upper surface of the second resin part 42A and the lower surface of the third resin part 43A may be flat. In this case as well, since the first outer peripheral portion 10s of one surface 10a of the core layer 10 is covered by the second resin part 42A, it is possible to suppress damage such as chipping or cracking of the first outer peripheral portion 10s. Furthermore, since the second outer peripheral portion 10t of the other surface 10b of the core layer 10 is covered by the third resin part 43A, it is possible to suppress damage such as chipping or cracking of the second outer peripheral portion 10t.

[0079] <Second Embodiment> The second embodiment shows an example of a semiconductor device in which a semiconductor chip is mounted on a wiring board according to the first embodiment. In the second embodiment, descriptions of components that are the same as those described in the previously described embodiments may be omitted.

[0080] Figure 11 is a cross-sectional view illustrating a semiconductor device according to the second embodiment. Referring to Figure 11, the semiconductor device 2 includes a wiring board 1 shown in Figure 1, a semiconductor chip 70, bumps 80, and underfill resin 90.

[0081] The semiconductor chip 70 has a chip body 71 and electrodes 72. The chip body 71 is formed by creating a semiconductor integrated circuit (not shown) on a thin semiconductor substrate (not shown) made of, for example, silicon. Electrodes 72 are formed on the semiconductor substrate (not shown) and are electrically connected to the semiconductor integrated circuit.

[0082] The bump 80 is formed on the electrode 72 of the semiconductor chip 70 and electrically connects the electrode 72 to the external connection terminal 18 of the wiring board 1. The electrode 72 can be formed from, for example, copper. The bump 80 is, for example, a solder bump. As the material for the solder bump, for example, an alloy containing Pb, an alloy of Sn and Cu, an alloy of Sn and Ag, an alloy of Sn, Ag and Cu, etc. can be used. The underfill resin 90 is filled between the semiconductor chip 70 and the upper surface of the solder resist layer 17 of the wiring board 1.

[0083] In this way, a semiconductor device can be realized by mounting a semiconductor chip on the wiring board according to the first embodiment. Instead of wiring board 1, any of wiring boards 1A to 1D may be used.

[0084] Although preferred embodiments have been described in detail above, the invention is not limited to the embodiments described above, and various modifications and substitutions can be made to the embodiments described above without departing from the scope of the claims.

[0085] For example, the above embodiment described a wiring board having a first laminate on one side of a glass core layer and a second laminate on the other side. However, the present invention can also be applied to a wiring board having a first laminate on one side of a glass core layer but not a second laminate on the other side, and will produce similar effects. In the case of a wiring board that does not have a second laminate, through-holes do not need to be provided in the core layer. [Explanation of Symbols]

[0086] 1,1A,1B,1C,1D Wiring board 2 Semiconductor devices 10 core layers 10a One side 10b The other side 10c side 10s 1st outer circumference 10t 2nd outer circumference 10x Through Hole 11. Through-wiring 12,14,16,22,24,26 wiring layer 13, 15, 23, 25 Insulating layer 13x, 15x, 23x, 25x Beer Hall 17,27 Solder Resist Layer 17x,27x opening 18 External connection terminals 41,41A,41B 1st resin part 42,42A 2nd resin part 43,43A 3rd resin part 51. First layer 51c,52c side 51x 1st groove 52. Second layer 52x Second groove 71 Chip body 72 electrode 80 Bump 90 Underfill resin 300 Fixing fixtures 410 Photosensitive resin 510 Heat-Seal Roller

Claims

1. A glass core layer having one side and the other side, A first laminate including a wiring layer and an insulating layer provided on one side of the core layer, It has a first resin part, The first outer periphery of one surface of the core layer is exposed from the first laminate, The first resin part is a wiring board that covers the side surface of the core layer.

2. The wiring board according to claim 1, wherein the first resin portion extends from the side surface of the core layer and covers at least a portion of the first outer periphery.

3. The wiring board according to claim 1, further comprising a second resin portion that covers the first outer periphery and the side surface of the first laminate.

4. The wiring board according to claim 3, wherein the first resin portion extends from the side surface of the core layer and covers at least a portion of the side surface of the second resin portion.

5. The wiring board according to claim 3 or 4, wherein the second resin portion does not contain a filler.

6. The wiring board according to claim 3 or 4, wherein the first resin portion and the second resin portion are made of a photosensitive insulating resin having the same resin as its main component.

7. The second laminate includes a wiring layer and an insulating layer provided on the other side of the core layer, The second outer periphery of the other surface of the core layer is exposed from the second laminate, The wiring board according to claim 1, wherein the first resin portion extends from the side surface of the core layer and covers at least a portion of the second outer periphery.

8. The second laminate includes a wiring layer and an insulating layer provided on the other side of the core layer, The second outer periphery of the other surface of the core layer is exposed from the second laminate, The wiring board according to claim 1, further comprising a third resin portion that covers the second outer periphery and the side surface of the second laminate.

9. The wiring board according to claim 8, wherein the first resin portion extends from the side surface of the core layer and covers at least a portion of the side surface of the third resin portion.

10. A process of preparing a glass core layer having multiple wiring regions that will be separated into individual pieces to form a wiring board, and cutting regions that will be cut during the separation process, A step of forming a first laminate including a wiring layer and an insulating layer on one side of the core layer, A step of forming a first groove that penetrates the first laminate and exposes one side of the core layer, so as to straddle the aforementioned cutting region, A step of irradiating one surface of the core layer exposed in the first groove along the cutting region with laser light to form a modified layer inside the core layer, The process involves cutting the core layer at the cutting region to produce a plurality of individual structures, A method for manufacturing a wiring board, comprising the step of forming a first resin portion that covers the side surface of the core layer of each of the structures, after the cutting step.

11. Between the step of forming the modified layer and the step of cutting, there is a step of forming a second resin portion that covers one surface of the core layer exposed in the first groove and the inner surface of the first groove. The method for manufacturing a wiring board according to claim 10, wherein in the cutting step, the second resin portion and the core layer are cut in the cutting region.

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