System and method for multi-level pulsation in RF plasma tools

Abstract

This invention provides a system and method for multi-level pulsation in radio frequency plasma tools. [Solution] The system and method receive a synchronization signal having multiple cycles that repeat periodically, generate a first radio frequency (RF) signal by a first RF generator, the first RF signal including at least two parameter levels in one cycle of the multiple cycles, and generate a second RF signal by a second generator, the second RF signal including at least three parameter levels in one cycle of the multiple cycles.

Description

[Technical Field]

[0001] This embodiment relates to a system and method for multi-level pulsation in radio frequency (RF) plasma tools. [Background technology]

[0002] The background information provided in this section is intended to provide a general overview of the circumstances of this disclosure. The works of the inventors and others named in this background information section are not explicitly or implicitly recognized as prior art to this disclosure, to the extent that they are described in this section and in manner that they may not normally qualify as prior art at the time of filing.

[0003] In a plasma tool, one or more radio frequency (RF) generators are coupled to an impedance matching circuit. The impedance matching circuit is coupled to the plasma chamber. RF signals are supplied from the RF generators to the impedance matching circuit. Upon receiving the RF signals, the impedance matching circuit outputs RF signals. The RF signals are supplied from the impedance matching circuit to the plasma chamber for processing the wafer within the plasma chamber. However, the wafer is not processed to the desired level of detail.

[0004] It is against this background that the embodiments described in this disclosure arise. [Overview of the Initiative]

[0005] Embodiments of this disclosure provide apparatus, methods, and computer programs for multi-level pulsation in radio frequency (RF) plasma tools. It should be understood that these embodiments may be implemented in multiple forms, e.g., processes, apparatus, systems, hardware, or by means of a computer-readable medium. Several embodiments are described below.

[0006] In the following description, several embodiments of multi-level pulsation are provided. Also, several benefits related to multi-level pulsation are provided. Two or more embodiments described herein can be combined to operate with each other, or each embodiment described herein can operate independently to provide a specific embodiment related to multi-level pulsation.

[0007] This section describes an RF generator that facilitates multi-level pulsation. The RF generator produces an RF signal with four or more power levels, which is supplied to an impedance matching circuit, which is coupled to the electrodes of a plasma chamber. The RF signal achieves multi-level pulsation during a clock cycle. For example, during one clock cycle, the RF signal transitions from the first power level to the second power level, then from the second power level to the third power level, and from the third power level to the fourth power level. At the end of the clock cycle, the RF signal transitions back from the fourth power level to the first power level. This multi-level pulsation is repeated periodically over multiple clock cycles.

[0008] Each of the first, second, third, and fourth power levels is a separate power level. For example, one or more power values ​​of the first power level are either exclusive or different from one or more power values ​​of the second power level, one or more power values ​​of the third power level, and one or more power values ​​of the fourth power level. Also, one or more power values ​​of the second power level are different from one or more power values ​​of the third power level, and one or more power values ​​of the fourth power level. One or more power values ​​of the third power level are different from one or more power values ​​of the fourth power level.

[0009] Multiple-state pulsation is not limited to four power levels. For example, several power levels, three or fewer, may be generated. For instance, two or three power levels may be generated by the RF generator. Another example is five, six, or seven power levels, or five or more power levels, which may be generated by the RF generator.

[0010] Multi-state pulsation is performed to achieve equilibrium between various stages of processing operations, such as equilibrium between the deposition stage and between the etching stage. For example, multi-state pulsation with two power levels is applied to perform the deposition stage, and multi-state pulsation with two higher power levels is applied to perform the etching stage. The two lower power levels have lower power than the higher power level. As an example, the etching operation is conductor etching performed in an inductively coupled plasma (ICP) chamber. The RF generator is coupled to the electrodes of the ICP plasma chamber, such as transformer-coupled plasma (TCP) electrodes or bias electrodes, via an impedance matching circuit.

[0011] One embodiment describes a pulse train calibration method for reducing power loss in a transmission line. The pulse train calibration method includes simulating a multi-state power pulse train to be generated, applying the train to a known 50-ohm load, and measuring the voltage or power of the multi-state power pulse train. For example, the voltage or power is measured for each state of the multi-state power pulse train. The power for each state of the power pulse train can be modified to account for losses based on the measured voltage or power line or measured complex voltage and current. An example of a transmission line includes a radio frequency (RF) cable coupling the output of an RF generator to the input of a matching unit, or a combination of an RF cable and an RF transmission line coupling the output of a matching unit to the electrodes of a plasma chamber.

[0012] One embodiment describes a voltage pulse equalization method for reducing line power loss. The voltage pulse equalization method includes measuring or determining the pulse shape under a known load and compensating the power so that a square RF pulse response is obtained. The pulse shape is measured using a voltage probe or power probe, or a complex voltage-power probe. This is voltage control within the pulse. The pulse is divided into several lower pulses. Voltage or power control is performed for each lower pulse. For example, portions of the pulse with too low voltage or power are modified to achieve a flat pulse with square power. The voltage pulse equalization method is performed in a manner that takes into account power loss in the line.

[0013] In one embodiment, a duty cycle calibration method for reducing power loss in a transmission line is described. The duty cycle calibration method includes measuring the duty cycle and adjusting the duration of the duty cycle for each state in a multi-state pulsed configuration to take into account transmission line power loss.

[0014] When pulsed with multiple levels (e.g., four or more power levels), reducing reflected power can be difficult for matching circuits.

[0015] In one embodiment, a transformer-coupled capacitive tuning (TCCT) matcher is provided to reduce reflected power during multi-state pulsation. The TCCT matcher is used in conjunction with a source RF generator and is modified for use with multi-level pulsation, such as four or more levels of pulsation. The TCCT matcher provides timing information for multi-level pulsation, and thus can be tuned to multi-level pulsation.

[0016] In one embodiment, a state matching device tuning method is described. The state tuning method includes tuning a TCCT matching device for one state and tuning the frequencies to reduce reflected power for the remaining three, four, or five states (e.g., tuning an RF generator).

[0017] In one embodiment, a solid-state matching device is used instead of a source TCCT matching device or bias matching device, enabling rapid tuning through multi-state pulsing and reducing reflected power. The solid-state matching device is fabricated from a transistor, a semiconductor diode, or a combination thereof.

[0018] In the case of multi-level pulsation, it is difficult for the matching circuit to cope with the multi-level pulsation and minimize reflected power.

[0019] In one embodiment, a matching circuit tuning method with a fixed frequency is described. In a four-state scenario, the matching circuit is tuned in the first state, and the fixed frequency of the RF generator is maintained in the other three states. The frequency is determined to minimize the sum of the products of the weights and reflected powers across the four states. For example, the frequency is such that C1P1 + C2P2 + C3P3 + C4P4 is minimized across states 1 to 4, where C1 to C4 are weights and P1 to P4 are reflected powers between each state. The weights C1 to C4 may be the ratio of duty cycles between each state. Instead of reflected power, the power reflection coefficient can be minimized.

[0020] When pulsed one or more transformer-coupled plasma (TCP) electrodes and bias electrodes, such as TCP coils, to have multiple states (e.g., four or more power levels), it is desirable to achieve uniformity in processing rates such as etching rate or deposition rate.

[0021] In one embodiment, a clock synchronization method is provided between the TCP and the bias electrode. In this clock synchronization method, a fine-resolution clock for multiple states is provided. The fine-resolution clock supplies a pulse signal having multiple states, such as four or more states, to an RF generator, which supplies power to the TCP electrode and the bias electrode. Synchronization facilitates the achievement of uniformity.

[0022] In one embodiment, an Ethernet for Control Automation Technology (EtherCAT® registered trademark; hereinafter the same) synchronization method and system are provided to achieve uniformity. Various devices such as TCP RF generators, bias RF generators, and matching units are synchronized using EtherCAT cables. Communication pulse trains are transmitted using EtherCAT cables to communicate with various devices. For example, a communication pulse train has a start time and a stop time. The start time is the beginning of a series of pulses, and the stop time is the time the series of pulses is stopped. The start time and stop time are repeated. Information about multiple states of various devices can be embedded in the pulse train. This information includes the start time and stop time for each state of each device. Furthermore, using EtherCAT cables for synchronization eliminates the need to supply TTL signals to various devices via multiple synchronization cables to synchronize them. Each synchronization cable carries a TTL signal. Synchronization cables are no longer necessary. An example of an EtherCAT cable is an Ethernet cable.

[0023] Furthermore, it is desirable to control the uniformity of the process and achieve a processing rate or etching depth in pulsed processing of multiple states (e.g., four or more states).

[0024] In one embodiment, a synchronization master such as a pulse master is provided to control the uniformity of processing and achieve a processing rate. As an example, the pulse master includes an analog-to-digital voltage control interface (ADVCI) that synchronizes a TCP generator and a bias RF generator. For example, the ADVCI can generate a digital pulse signal or TTL signal having two states and supply it to the TCP RF generator, and can generate another digital pulse signal or another TTL signal having four states and supply it to the bias RF generator. The two states and the four states are generated during the clock cycle of the clock signal. As another example, the ADVCI can generate a digital pulse signal or TTL signal having four states and supply it to the TCP RF generator, and can generate another digital pulse signal or another TTL signal having four states and supply it to the bias RF generator. The four states are generated during the clock cycle of the clock signal.

[0025] In one embodiment, the pulse master is used in conjunction with termination point detection to control processing uniformity and achieve processing rate. The pulse master is used to synchronize the optical emission spectrometer (OES) and the Lam spectrophotometer by pulsing multiple states, such as multiple levels. Termination points or processing points are detected by the OES and the Lam spectrophotometer. The Lam spectrophotometer (LSR) or OES measures the intensity of light reflected from the wafer.

[0026] One embodiment provides a method for modifying on / off times by selective synchronization between a source RF generator and a bias RF generator. The on / off time modification method includes changing from two plasma impedance states to four plasma impedance states, or from four plasma impedance states to eight plasma impedance states, or modifying the on and off times of RF power in each state, such as delaying or advancing them. The on / off times can be adjusted or modified within each state to achieve four plasma impedance states from two. For example, the on time for applying RF power is slightly delayed in state S1, and / or the off time is achieved slightly earlier in state S1. When the on and off times of RF power are changed for both the TCP generator and the bias RF generator, both the TCP generator and the bias generator are synchronized with each other. As an example, if multi-state power having four or eight states is generated by the source RF generator, the bias RF generator operates in continuous wave (CW) mode. As another example, if a multi-state power with four or eight states is generated by a bias RF generator, the source RF generator operates in continuous wave (CW) mode. Also, as an example, various processes may be performed in each state. For instance, deposition on the wafer may occur in one state, while etching of the wafer may occur in another.

[0027] The processing is controlled to minimize defects in the wafer caused by spikes at the transition edges and to protect the RF generator when it operates in four or more states.

[0028] In one embodiment, a pulse shaping method is provided to achieve processing control. As an example, the pulse shaping method includes shaping the rising edge and / or falling edge of the power of an RF signal generated by an RF generator. As another example, the pulse shaping method includes shaping the rising edge and / or falling edge of the frequency of an RF signal. As yet another example, the pulse shaping method includes shaping the rising edge and / or falling edge of the power of an RF signal, as well as shaping the rising edge and / or falling edge of the frequency.

[0029] It is even more desirable to control the process used to achieve uniformity when processing the substrate.

[0030] In one embodiment, a system is provided having multiple power controllers and multiple automatic frequency tuners (AFTs) to achieve uniformity.

[0031] One embodiment describes a method for tuning the frequency of the trajectories at a microsecond level to achieve uniformity. In this method, the frequency of each RF signal is tuned at a microsecond level to reduce reflected power for each recipe and generate RF signal trajectories, which are applied while the wafer processing recipes are applied. The trajectories are generated to learn the next trajectory to be applied during wafer processing.

[0032] One embodiment describes a method for introducing an off state. In this method, the off state is provided at any point in a multi-level pulse sequence. The off state can be at any point in the pulse sequence. It is not necessary to achieve the off state before repeating a first state in the pulse sequence.

[0033] Some advantages of the systems and methods described herein include using a two-state RF generator to produce multi-state plasma impedance, such as four or more plasma impedance states. Multi-state plasma impedance is generated by producing various combinations of parameter levels for the source RF generator and the bias RF generator. Multi-state plasma impedance is used to achieve uniformity when processing substrates and also for finer control during substrate processing.

[0034] Furthermore, some advantages of the systems and methods described herein with respect to multi-state pulsation include increasing the level of control over substrate processing. By implementing four or more variable levels during substrate processing, finer control of substrate processing is achieved. Moreover, by controlling the state transitions between two variable levels, even finer control of substrate processing is achieved to obtain a predetermined processing result.

[0035] The advantages of the systems and methods using EtherCAT cables described herein include achieving rapid information transmission between various components of a plasma tool or plasma system. Data such as parameter levels measured between four or more states are rapidly transmitted from the processor to the EtherCAT frame. Similarly, data such as parameter levels that generate four or more states are rapidly transmitted from the EtherCAT frame to the processor. This rapid transmission enables faster data transmission when using multi-state pulsation, thereby enabling control during substrate processing.

[0036] Other embodiments will become apparent from the following detailed description in combination with the attached drawings. [Brief explanation of the drawing]

[0037] Embodiments will be understood by referring to the following description in combination with the attached drawings.

[0038] [Figure 1] Figure 1 shows an embodiment of a plasma system, illustrating the use of a two-state radio frequency (RF) generator that generates multiple states of plasma impedance.

[0039] [Figure 2] Figure 2 is a diagram of one embodiment of the system, showing details of the RF generator.

[0040] [Figure 3A] Figure 3A is a graph of one embodiment showing the synchronization signal.

[0041] [Figure 3B] Figure 3B is a graph of one embodiment showing the source signal parameters versus time.

[0042] [Figure 3C] Figure 3C is a graph of one embodiment showing the parameters versus time of the bias RF signal.

[0043] [Figure 4A] Figure 4A is a graph of one embodiment of Figure 3A showing the synchronization signal.

[0044] [Figure 4B] Figure 4B is a graph of one embodiment of Figure 3B.

[0045] [Figure 4C] Figure 4C is a graph of one embodiment showing the parameters versus time of another bias RF signal.

[0046] [Figure 5A] Figure 5A is a graph of one embodiment showing the synchronization signal.

[0047] [Figure 5B] Figure 5B is a graph of one embodiment showing the parameters versus time of the source RF signal.

[0048] [Figure 5C] Figure 5C is a graph of one embodiment showing the parameters versus time of the bias RF signal.

[0049] [Figure 6A] Figure 6A is a graph of one embodiment showing the synchronization signal.

[0050] [Figure 6B] Figure 6B is a graph of one embodiment showing the parameters versus time of the source RF signal.

[0051] [Figure 6C] Figure 6C is a graph of one embodiment showing the parameters versus time of the bias RF signal.

[0052] [Figure 6D] Figure 6D illustrates one embodiment of on / off time correction by selective synchronization between a source RF generator and a bias RF generator.

[0053] [Figure 7] Figure 7 shows an embodiment of the plasma system, illustrating the pulsation of multiple levels of parameters.

[0054] [Figure 8] Figure 8 shows an embodiment of a plasma system, illustrating the pulsation of multiple frequency levels.

[0055] [Figure 9] Figure 9 shows an embodiment of a plasma system, illustrating the simultaneous pulsation of multiple levels of parameters and the pulsation of frequency.

[0056] [Figure 10A] Figure 10A is a graph of one embodiment of Figure 3A showing the synchronization signal.

[0057] [Figure 10B]Figure 10B is a graph of one embodiment showing the variable versus time of the RF signal in Figure 9.

[0058] [Figure 10C] Figure 10C is a graph of one embodiment showing the variable versus time of the RF signal in Figure 9.

[0059] [Figure 10D] Figure 10D is a graph of one embodiment showing the variable versus time t of the RF signal in Figure 9.

[0060] [Figure 10E] Figure 10E is a graph of one embodiment showing the variable versus time of the RF signal in Figure 9.

[0061] [Figure 10F] Figure 10F is a graph of one embodiment showing the variable versus time of the RF signal in Figure 9.

[0062] [Figure 10G] Figure 10G is a graph of one embodiment showing the variable versus time t of the RF signal in Figure 9.

[0063] [Figure 10H] Figure 10H is a graph of one embodiment showing the variable versus time of the RF signal in Figure 9.

[0064] [Figure 10I] Figure 10I is a graph of one embodiment showing the variable versus time of the RF signal in Figure 9.

[0065] [Figure 10J] Figure 10J is a diagram of one embodiment of a system having multiple power controllers and multiple automatic frequency tuners (AFTs).

[0066] [Figure 10K] Figure 10K is a diagram of one embodiment showing an RF signal having four states S(n-3), S(n-2), S(n-1), and Sn, and shows the power level of the RF signal.

[0067] [Figure 10L] Figure 10L is a diagram of one embodiment showing another RF signal having four states S(n-3), S(n-2), S(n-1) and Sn, and showing the power level of the RF signal.

[0068] [Figure 10M] Figure 10M is a diagram of another embodiment showing another RF signal having four states S(n-3), S(n-2), S(n-1) and Sn, and showing the power level of the RF signal.

[0069] [Figure 10N] Figure 10N is a diagram of one embodiment showing another RF signal having four states S(n-3), S(n-2), S(n-1) and Sn, and showing the power level of the RF signal.

[0070] [Figure 10O] Figure 10O is a diagram of one embodiment showing yet another RF signal having four states S(n-3), S(n-2), S(n-1) and Sn, and showing the power levels of the RF signal.

[0071] [Figure 10P] Figure 10P is a diagram illustrating one embodiment of a method for demonstrating that a zero power level is achieved between one or more states from S(nA) to Sn, where (nA) is an integer less than n.

[0072] [Figure 11A] Figure 11A shows an embodiment of a plasma system, illustrating gradient control of state transitions.

[0073] [Figure 11B] Figure 11B is a diagram of one embodiment of the system shown in Figure 11A, illustrating the function of the system.

[0074] [Figure 12A] Figure 12A is a graph of one embodiment showing the synchronization signal in Figure 3A.

[0075] [Figure 12B] Figure 12B is a graph of one embodiment showing the variable versus time of the RF signal in Figures 11A and 11B.

[0076] [Figure 12C] Figure 12C is a graph of one embodiment showing the variable versus time of the RF signal in Figures 11A and 11B.

[0077] [Figure 12D] Figure 12D is a graph of one embodiment showing various types of transitions between variables and time for the RF signals in Figures 11A and 11B.

[0078] [Figure 12E] Figure 12E is a graph of one embodiment showing various types of transitions between variables and time for the RF signals in Figures 11A and 11B.

[0079] [Figure 12F] Figure 12F is a diagram illustrating one embodiment of the pulse shaping method.

[0080] [Figure 12G] Figure 12G is a diagram of one embodiment of another pulse shaping method.

[0081] [Figure 12H] Figure 12H is a diagram of yet another embodiment of a pulse shaping method.

[0082] [Figure 12I] Figure 12I is a diagram of yet another embodiment of a pulse shaping method.

[0083] [Figure 12J] Figure 12J shows an embodiment of another pulse shaping method.

[0084] [Figure 12K]Figure 12K shows another embodiment of a pulse shaping method.

[0085] [Figure 12L] Figure 12L is a diagram of one embodiment of another pulse shaping method.

[0086] [Figure 13A] Figure 13A is a diagram of one embodiment of the system, illustrating the transmission of information between various components of a plasma system via one or more EtherCAT cables.

[0087] [Figure 13B] Figure 13B is a diagram of one embodiment of the system, illustrating the transmission of information between various components of a plasma system via one or more EtherCAT cables.

[0088] [Figure 14] Figure 14 is a diagram of one embodiment of an EtherCAT frame.

[0089] [Figure 15A] Figure 15A is a diagram of one embodiment of the system, illustrating the transmission of information between various components of a plasma system via one or more EtherCAT cables.

[0090] [Figure 15B] Figure 15B is a diagram of one embodiment of the system, illustrating the transmission of information between various components of a plasma system via one or more EtherCAT cables.

[0091] [Figure 16] Figure 16 is a diagram of one embodiment of an EtherCAT frame.

[0092] [Figure 17] Figure 17 shows one embodiment of the system, illustrating an RF generator coupled to an EtherCAT cable.

[0093] [Figure 18] Figure 18 shows one embodiment of a system that includes a matching circuit, which is coupled to the RF generator in Figure 17 via an RF cable and then to an EtherCAT cable.

[0094] [Figure 19A] Figure 19A shows an embodiment of an EtherCAT synchronization system, in which an EtherCAT cable is coupled between two components of a plasma system.

[0095] [Figure 19B] Figure 19B shows an embodiment of an EtherCAT synchronization system, in which an EtherCAT cable is coupled between the source radio frequency (RF) generator and the bias RF generator, and another EtherCAT cable is coupled between the source RF generator and the source matcher.

[0096] [Figure 19C] Figure 19C shows an embodiment of an EtherCAT synchronization system, in which the components of the plasma system are connected in a daisy-chain fashion.

[0097] [Figure 19D] Figure 19D shows an embodiment of an EtherCAT synchronization system, in which the components of the plasma system are connected in a daisy-chain fashion.

[0098] [Figure 20] Figure 20 shows one embodiment of a system illustrating a pulse train calibration method.

[0099] [Figure 21] Figure 21 is a diagram of one embodiment of a system that demonstrates a voltage pulse leveling method.

[0100] [Figure 22] Figure 22 is a diagram of one embodiment of a system demonstrating a duty cycle calibration method.

[0101] [Figure 23] Figure 23 is a diagram of a system using a transformer-coupled capacitive tuning (TCCT) matcher.

[0102] [Figure 24A] Figure 24A is a diagram of one embodiment of a system that shows a method for tuning a state matching device.

[0103] [Figure 24B] Figure 24B is a diagram of one embodiment of the system showing a matching circuit tuning method in a different state.

[0104] [Figure 25A] Figure 25A is a diagram of one embodiment of a system showing a source solid-state matcher.

[0105] [Figure 25B] Figure 25B shows one embodiment of a system that uses a bias solid-state matcher instead of a bias matcher.

[0106] [Figure 26A] Figure 26A is a diagram of one embodiment of a system showing a matching circuit tuning method with a fixed frequency.

[0107] [Figure 26B] Figure 26B is a diagram of one embodiment of a system demonstrating a matching circuit tuning method with a fixed frequency.

[0108] [Figure 27] Figure 27 shows one embodiment of a system illustrating a clock synchronization method between a transcoupled plasma (TCP) electrode and a bias electrode.

[0109] [Figure 28A] Figure 28A is a diagram of one embodiment of a system showing a synchronization master.

[0110] [Figure 28B] Figure 28B is a diagram of one embodiment of the system showing the synchronization master.

[0111] [Figure 29] Figure 29 shows one embodiment of the system, illustrating the use of multi-state control with endpoint detection.

[0112] [Figure 30] Figure 30 is a diagram of a system including a power controller, an automatic frequency tuner, a processor, and a power supply, illustrating how to tune the orbital frequency or power at the microsecond level. [Modes for carrying out the invention]

[0113] The following embodiments describe multi-level pulsation systems and methods in radio frequency (RF) plasma tools. It will be apparent that these embodiments can be performed without some or all of the specific details of the embodiments. In other examples, well-known process operations are not described in detail so as not to unnecessarily obscure these embodiments.

[0114] In the following description, several embodiments for multi-level pulsation are provided. Two or more embodiments described herein can be combined to operate with each other, or each embodiment described herein can operate independently to provide a specific embodiment relating to multi-level pulsation.

[0115] This section describes an RF generator that facilitates multi-level pulsation. The RF generator produces an RF signal with four or more power levels, which is supplied to an impedance matching circuit, which is coupled to electrodes in a plasma chamber. The RF signal achieves multi-level pulsation during a clock cycle. For example, during a single clock cycle, the RF signal transitions from the first power level to the second power level, then from the second power level to the third power level, and from the third power level to the fourth power level. This multi-level pulsation is repeated periodically over multiple clock cycles.

[0116] Each of the first, second, third, and fourth power levels is a separate power level. For example, one or more power values ​​of the first power level are exclusive or different from one or more power values ​​of the second power level, one or more power values ​​of the third power level, and one or more power values ​​of the fourth power level. Also, one or more power values ​​of the second power level are different from one or more power values ​​of the third power level, and one or more power values ​​of the fourth power level. One or more power values ​​of the third power level are different from one or more power values ​​of the fourth power level. For example, the difference between the highest power value and the lowest power value of the RF signal power level is less than a predetermined percentage. For example, the highest power value of the first power level is at most 20% greater than the lowest power value of the first power level. Similarly, the highest power value of the second power level is at most 20% greater than the lowest power value of the second power level.

[0117] In one embodiment, the same power level is applied between two or more states. For example, one power level is applied between the first and second states, a different power level is applied during the third state, and yet another power level is applied during the fourth state.

[0118] Multi-state pulsation is performed to achieve balance between various stages during processing operations such as deposition, etching, cleaning, and sputtering. For example, the first and second power levels of the RF signal are used to perform the deposition stage during etching, and the third and fourth power levels are used to perform the etching stage during etching. Another example is to perform different stages between each state of multi-state pulsation. Yet another example is to perform one stage between one or more states of multi-state pulsation and another stage between one or more of the remaining states of multi-state pulsation. As an example, etching is conductor etching performed in an inductively coupled plasma (ICP) chamber. The RF generator is coupled to electrodes in the ICP plasma chamber, such as transformer-coupled plasma (TCP) electrodes or bias electrodes, via an impedance matching circuit.

[0119] The RF generator receives a digital pulse signal indicating the duty cycle, such as duration, for each power level of the RF signal it generates. The digital pulse signal indicates the time period during which each power level is supplied by the RF generator. The digital pulse signal has multiple states, such as four or more states. For example, the digital pulse signal has a first logic level during the first state, a second logic level during the second state, a third logic level during the third state, and a fourth logic level during the fourth state. Each logic level is defined by the voltage level of the voltage signal generated by the digital pulse source. The digital pulse source is coupled to the RF generator and supplies the digital pulse signal to the RF generator. Furthermore, the RF generator receives a clock signal with multiple clock cycles to facilitate the repetition of multi-level pulsation. The clock signal is generated by the digital pulse source or a clock source, and the clock source is coupled to the RF generator to supply the clock signal to the RF generator.

[0120] It should be noted that the above description of the four power levels is an example. In one embodiment, the RF generator generates a further number of power levels, such as 5, 6, 7, or 8 power levels, during a clock cycle, and the power levels are repeated over multiple clock cycles. As the number of power levels increases, finer control is achieved while processing the substrate in the plasma chamber. For example, as the number of power levels increases during a clock cycle, optimal etching of the substrate, or optimal deposition of material onto the substrate, or a combination thereof, can be achieved. In one embodiment, three or fewer power levels are generated, such as three or two power levels.

[0121] The plasma chamber may also be an ICP chamber. For example, the RF generator is coupled to an electrode in the plasma chamber, such as a TCP electrode or a bias electrode, via an impedance matching circuit. To illustrate multiple states, such as multiple levels, an RF signal is supplied to the TCP electrode via a matching circuit, while a continuous wave (CW) RF signal or a dual-state RF signal is supplied to the bias electrode via another matching circuit. As another example, a multi-level RF signal is supplied to the bias electrode via a matching circuit, while a CW RF signal or a dual-state RF signal is supplied to the TCP electrode via another matching circuit. As yet another example, a multi-level RF signal is supplied to the bias electrode via a matching circuit, and a multi-level RF signal is supplied to the TCP electrode via yet another matching circuit. The bias electrode is the lower electrode located within the chuck or substrate support of the plasma chamber.

[0122] A two-state RF generator that produces four or more plasma impedance states.

[0123] Figure 1 is a diagram of one embodiment of the plasma system 100, illustrating the use of a two-state RF generator, such as a source radio frequency (RF) generator 102 or a bias RF generator 104, which generates a plasma impedance having four or more states. The system 100 includes a host computer 106, a source RF generator 102, a bias RF generator 104, a source matcher 108, a bias matcher 110, and a plasma chamber 112.

[0124] Examples of host computers used herein include desktop computers, tablets, smartphones, and laptop computers. Examples of RF generators used herein include RF generators having an operating frequency of 400 kilohertz (kHz), 2 megahertz (MHz), 27 MHz, or 60 MHz. For example, bias generator 104 may have an operating frequency of 2 MHz and source RF generator 102 may have an operating frequency of 60 MHz, and vice versa. Another example is bias generator 104 may have an operating frequency of 400 kHz and source RF generator 102 may have an operating frequency of 60 MHz, and vice versa.

[0125] Examples of impedance matching circuits used herein include networks of interconnected components such as inductors, capacitors, and resistors. For example, an impedance matching circuit includes a series of circuits and a branch circuit, each of which includes a capacitor, an inductor, or a combination thereof, and each of which includes a capacitor, an inductor, or a combination thereof. Note that in one embodiment, the terms impedance matching circuit, impedance matching network, and impedance matching network are used interchangeably herein. Examples of plasma chambers 112 include transformer-coupled plasma (TCP) plasma chambers and inductively coupled plasma (ICP) plasma chambers.

[0126] The host computer 106 includes a processor 118 and a memory device 120, the processor 118 being coupled to the memory device 120. Examples of processors used herein include central processing units (CPUs), microcontrollers, controllers, microprocessors, application-specific integrated circuits (ASICs), and programmable logic devices (PLDs). Examples of memory devices used herein include read-only memory, random-access memory, or a combination thereof. For example, the memory device may be flash memory or a redundant array of inexpensive disks.

[0127] The plasma chamber 112 includes a dielectric window 124, and above the dielectric window 124 is a TCP coil 126. For example, the dielectric window 124 forms the upper surface of the plasma chamber 112. The TCP coil 126 is an example of an electrode of the plasma chamber 112. The plasma chamber 112 further includes a substrate support 128, such as a chuck, on which to place a substrate S for processing. The substrate support 128 is an example of an electrode of the plasma chamber 112. The substrate S is placed on the upper surface of the substrate support 128. The substrate support 128 is embedded in a lower electrode. For example, the lower electrode is made of a metal such as aluminum or an aluminum alloy.

[0128] The processor 118 is coupled to the source RF generator 102 via a transmission cable system 130. Similarly, the processor 118 is coupled to the bias RF generator 104 via a transmission cable system 134. The transmission cable systems used herein include one or more transmission cables. As an example, the transmission cables used herein include a series transmission cable that transmits data in series between the processor 118 and the RFG coupled to the processor 118. When data is transmitted in series, one bit is transmitted at a time. Another example of a transmission cable includes a parallel transmission cable that transmits data in parallel between the processor 118 and the RFG coupled to the processor 118. When data is transmitted in parallel, multiple bits are transmitted simultaneously. Yet another example of a transmission cable includes a Universal Serial Bus (USB) cable.

[0129] The output 154 of the source RF generator 102 is coupled to the input 156 of the source matcher 108 via the RF cable 138, and the output 158 ​​of the source matcher 108 is coupled to the TCP coil 126 via the RF transmission line 140. Similarly, the output 160 of the bias RF generator 104 is coupled to the input 162 of the bias matcher via the RF cable 142, and the output 164 of the bias matcher 110 is coupled to the substrate support 128 via the RF transmission line 144. An example of an RF transmission line includes an RF rod. The RF rod is surrounded by insulating material, which is further surrounded by an RF sheath of the RF transmission line. The insulating material of the RF transmission line is between the RF rod and the RF sheath. Another example of an RF transmission line includes an RF sheath surrounding insulating material, an RF rod, and one or more RF straps coupled to the RF rod. Another example of an RF transmission line includes an insulating material, an RF rod, one or more RF straps, and an RF sheath surrounding an RF cylinder coupled to the RF sheath via at least one of the RF straps.

[0130] The processor 118 includes a clock source, which generates a synchronization signal 146, such as a digital clock signal or a digital pulse signal, and transmits it to the source RF generator 102 via the transmission cable system 130. One example of a clock source includes a phase-locked loop circuit that generates a synchronization signal with a 50% duty cycle. Another example of a clock source includes a phase-locked loop circuit coupled with a duty cycle control circuit at its output, which changes the duty cycle of the synchronization signal from 50% to more than 50% or less than 50%, such as 80% or 10%, and outputs a synchronization signal with a modified duty cycle. The clock source of the processor 118 also transmits the synchronization signal 146 to the bias RF generator 104 via the transmission cable system 134.

[0131] Furthermore, the processor 118 transmits source variables, such as the frequency of the RF signal 152 to be generated, or the parameters of the RF signal 152, to the source RF generator 102 via the transmission cable system 130. Examples of variables used herein include frequency and parameters. For example, the variables may be frequency or power. Examples of parameters used herein include voltage and power. For example, the parameters may be voltage or power. The processor 118 also transmits bias variables, such as the frequency of the RF signal 168 and the parameters of the RF signal 168, to the bias RF generator 104 via the transmission cable system 134.

[0132] The source RF generator 102 generates an RF signal 152 upon receiving a synchronization signal 146 and source variables via the transmission cable system 130. The RF signal 152 has source variables such as frequency and power or voltage, which are received by the source RF generator 102 from the processor 118. The RF signal 152 is transmitted from the output 154 of the source RF generator 102 to the input 156 of the source matcher 108 via the RF cable 138. The source matcher 108 receives the RF signal 152, corrects the impedance of the RF signal 152, and matches the impedance of the load coupled to the output 158 ​​of the source matcher 108 with the impedance of the source coupled to the input 156 of the source matcher 108. The source matcher 108 corrects the impedance of the RF signal 152 and outputs a corrected RF signal 166 at the output 158 ​​of the source matcher 108. The corrected RF signal 166 is transmitted from the output 158 ​​to the TCP coil 126 via the RF transmission line 140.

[0133] Similarly, the bias RF generator 104 generates an RF signal 168 upon receiving a synchronization signal 146 and source variables via the transmission cable 134. The RF signal 168 has bias variables such as frequency and power or voltage, which are received by the bias RF generator 104 from the processor 118. The RF signal 168 is transmitted from the output 160 of the bias RF generator 104 to the input 162 of the bias matcher 110 via the RF cable 142. The bias matcher 110 receives the RF signal 168, corrects the impedance of the RF signal 168, and matches the impedance of the load coupled to the output 164 of the bias matcher 110 with the impedance of the source coupled to the input 162 of the bias matcher 110. The bias matcher 110 corrects the impedance of the RF signal 168 and outputs a corrected RF signal 170 at the output 164 of the bias matcher 110. The corrected RF signal 170 is transmitted from the output 164 to the bottom electrode embedded in the substrate 128 via the RF rod of the RF transmission line 144.

[0134] In one embodiment, the modified RF signal 166 has the same number of parameter levels as the RF signal 152, and it should be noted that the modified RF signal 166 is generated from the RF signal 152. For example, each of the RF signals 152 and 166 has two parameter levels during the cycle of the synchronization signal 146. Also in one embodiment, each of the RF signal 152 and the modified RF signal 166 transitions simultaneously from one parameter level to the other. For example, when the RF signal 152 transitions from one parameter level to the other, the modified RF signal 166 also transitions from one parameter level to the other. In one embodiment, the modified RF signal 166 has the same parameter levels as the RF signal 152. For example, if the RF signal 152 has a first parameter level, the modified RF signal has the same first parameter level.

[0135] In one embodiment, the modified RF signal 170 has the same number of parameter levels as the RF signal 168, and it should be noted that the modified RF signal 170 is generated from the RF signal 168. For example, each of the RF signals 168 and 170 has three parameter levels during the cycle of the synchronization signal 146. Also in one embodiment, each of the RF signal 168 and the modified RF signal 170 transitions simultaneously from one parameter level to the other. For example, when the RF signal 168 transitions from one parameter level to the other, the modified RF signal 170 also transitions from one parameter level to the other. In one embodiment, the modified RF signal 170 has the same parameter levels as the RF signal 168. For example, if the RF signal 168 has a first parameter level, the modified RF signal has the same first parameter level.

[0136] In addition to the modified RF signals 166 and 170, supplying one or more process gases, such as an oxygen-containing gas, a fluorine-containing gas, or a combination thereof, to the housing of the plasma chamber 112 generates or maintains plasma within the housing of the plasma chamber 112. The plasma is used to process a substrate S and has a certain impedance. For example, the plasma is used to deposit material onto the substrate S, or to etch the substrate S, or to sputter the substrate S, or to clean the substrate S, or a combination thereof.

[0137] In one embodiment, instead of TCP coil 126, multiple TCP coils are placed on the dielectric window 124. In another embodiment, in addition to TCP coil 126, one or more TCP coils are placed on the side of the plasma chamber 112.

[0138] Figure 2 is a diagram of one embodiment of system 200, showing details of the RF generator 202. System 200 includes the RF generator 202 and a host computer 106. System 200 further includes a matching unit 216 and an RF cable 218. RF generator 202 is an example of a source RF generator 102 or a bias RF generator 104 (Figure 1). Matching unit 216 is an example of a source matching unit 108 or a bias matching unit 110 (Figure 1). RF cable 218 is an example of an RF cable 138 or an RF cable 142 (Figure 1), which is coupled to the output 217 of the RF power supply 222. RF generator 202 includes a digital signal processor (DSP) 204, a power controller (PRS1) 206, a power controller (PRS2) 208, a frequency controller (FC) 210, a driver system 212, and an RF power supply 222.

[0139] Examples of digital signal processors used herein include controllers, microprocessors, and microcontrollers, and these terms may be used interchangeably herein. Examples of parameter controllers used herein include combinations of processors and memory devices. The processor of the parameter controller is coupled to the memory device of the parameter controller. Similarly, examples of frequency controllers used herein include combinations of processors and memory devices. The processor of the frequency controller is coupled to the memory device of the frequency controller. Examples of driver systems used herein include circuits having one or more drivers, such as one or more transistors coupled to one another. Examples of RF power supplies used herein include electronic oscillators that generate periodic oscillating RF signals, such as sine waves.

[0140] The processor 118 is coupled to the DSP 204 via the transmission cable system 214. The transmission cable system 214 is an example of the transmission cable system 130 or transmission cable system 134 (Figure 1). The digital signal processor 202 is coupled to the parameter controllers 206 and 208, and the frequency controller 210. The parameter controllers 206 and 208 are coupled to the driver system 212, which is coupled to the RF power supply 222. The frequency controller 210 is also coupled to the driver system 212. The RF power supply 222 is coupled to the matcher 216 via the RF cable 218.

[0141] The processor 118 supplies variables such as source variables or bias variables, and a synchronization signal 146 to the DSP 204 via the transmission cable system 214. Upon receiving the variables, the DSP 204 supplies parameters such as the power level or voltage level of state S1 of the RF signal 220 to the parameter controller 206, and stores the parameters of state S1 in the memory device of the parameter controller 206. As an example, a parameter level such as a power level or voltage level is the envelope of the RF signal. As an example, a parameter level is a separate horizontal level that is higher or lower than the separate horizontal level of another parameter level. As another example, a parameter level is the magnitude from zero to the peak of one or more RF signals, or the magnitude between one or more peaks, or the magnitude between one or more peaks. The amplitude of parameter levels is within a predetermined range, such as 0 to 5%, from each other, excluding the amplitude of another or different parameter level. As another example, a parameter level has a maximum and a minimum value. The maximum value is the maximum of all values ​​for the parameter level, and the minimum value is the minimum of all values ​​for the parameter level. The first parameter level is smaller than the second parameter level if the maximum value of the first parameter level is smaller than the minimum value of the second parameter level, and the first parameter level is larger than the second parameter level if the minimum value of the first parameter level is larger than the maximum value of the second parameter level.

[0142] Furthermore, upon receiving a variable, the DSP 204 supplies parameters such as the power level or voltage level of state S2 of the RF signal 220 to the parameter controller 208, and stores the parameters of state S1 in the memory device of the parameter controller 208. Similarly, upon receiving a variable, the DSP 204 supplies the frequency level to the frequency controller 210, and stores it in the memory device of the frequency controller 210.

[0143] In one embodiment, a level, such as one level of a variable, includes one or more values. For example, a power level includes one or more power values ​​that are within a predetermined range from each other, and a voltage level includes one or more voltage values ​​that are within a predetermined range from each other. As another example, a variable level of an RF signal is the magnitude of one or more RF signals from zero to peak, or the magnitude between one or more peaks, or the magnitude between one or more peaks. The amplitude of a variable level is within a predetermined range, such as 0 to 5%, from each other, excluding the amplitude of another or different parameter level. As yet another example, a variable level is a separate horizontal level that is higher or lower than a separate horizontal level of another variable level.

[0144] In one embodiment, the values ​​at the first variable level are different from the values ​​at the second variable level. For example, the values ​​at the first variable level exclude the values ​​at the second variable level. In another example, none of the values ​​at the first variable level are the same as any of the values ​​at the second variable level.

[0145] Upon receiving the synchronization signal 146, the DSP204 identifies the cycles of the synchronization signal 146. For example, the DSP204 determines that cycle 1 of the synchronization signal 146 started in the first time and ended or stopped in the second time, and that cycle 2 of the synchronization signal 146 started in the second time and ended or stopped in the third time. For example, the DSP204 determines that the logic level of the synchronization signal 146 transitioned from 0 to 1 at the start time and again from 0 to 1 at the stop time, and that there were no other transitions from 0 to 1 that identify the cycles of the synchronization signal 146 during the transition between the start time and the stop time. The DSP204 counts each cycle and determines several cycles of the synchronization signal 146.

[0146] Furthermore, upon identifying a cycle, the DSP 204 transmits a command signal for state S1 to the parameter controller 206 during each cycle of the synchronization signal 146. For example, the DSP 204 transmits a command signal for state S1 to the parameter controller 206 when transitioning from state S2 or from state S0 to state S1. The command signal for state S1 transmitted to the parameter controller 206 includes the time period of state S1 between each cycle, and the parameter controller 206 supplies the parameter level of state S1 to the driver system 212. Upon receiving the command signal for state S1, the parameter controller 206 accesses the parameter level of state S1 from its memory device and transmits the parameter level for the time period of state S1 to the driver system 212. For example, the parameter controller 206 transmits the parameter level of state S1 to the driver system 212 when transitioning from state S2 or from state S0 to state S1. After the time period of state S1, the parameter controller 206 does not transmit the parameter level of state S1 to the driver system 212 during the cycle of the synchronization signal 146.

[0147] Similarly, upon receiving the synchronization signal 146, the DSP 204 transmits a command signal for state S2 to the parameter controller 208 during each cycle of the synchronization signal 146. For example, the DSP 204 transmits a command signal for state S2 to the parameter controller 208 when transitioning from state S1 or from state S0 to state S2. The command signal for state S2 transmitted to the parameter controller 208 includes the time period of state S2 between each cycle, and the parameter controller 208 supplies the parameter level for state S2 to the driver system 212. Upon receiving the command signal for state S2, the parameter controller 208 accesses the parameter level for state S2 from its memory device and transmits the parameter level for the time period of state S2 to the driver system 212. For example, the parameter controller 206 transmits the parameter level for state S2 to the driver system 212 when transitioning from state S1 or from state S0 to state S2. After the time period of state S2, the parameter controller 208 does not transmit the parameter level of state S2 to the driver system 212 during the cycle of the synchronization signal 146.

[0148] Furthermore, upon receiving the synchronization signal 146, the DSP 204 transmits a command signal to the frequency controller 210 during each cycle of the synchronization signal 146. Upon receiving the command signal, the frequency controller 210 accesses the frequency level from its memory device and transmits the frequency level to the driver system 212.

[0149] In response to the reception of the parameter level and frequency level of state S1, the driver system 212 generates a drive signal for state S1 for a duration of time in state S1 and transmits the drive signal to the RF power supply 222. For example, when transitioning from S2, or from state S0 to state S1, upon receiving the parameter level and frequency level of state S1, the driver system 212 generates a drive signal for state S1 for a duration of time in state S1 and transmits the drive signal to the RF power supply 222. When the RF power supply 222 receives the drive signal for state S1 from the driver system 212, it generates state S1 of the RF signal 220. For example, upon receiving the drive signal for state S1 from the driver system 212, the RF power supply 222 transitions the RF signal 220 from state S0 or state S2 to state S1. State S1 of the RF signal 220 has the parameter level and frequency level of state S1 for a duration of time in state S1.

[0150] Similarly, upon receiving the frequency level and parameter level of state S2, the driver system 212 generates a drive signal for state S2 for the duration of state S2 and transmits the drive signal to the RF power supply 222. For example, upon receiving the parameter level and frequency level of state S2 during a transition from S1 or from state S0 to state S2, the driver system 212 generates a drive signal for state S2 for the duration of state S2 and transmits the drive signal to the RF power supply 222. When the RF power supply 222 receives the drive signal for state S2 from the driver system 212, it generates state S2 for the RF signal 220. For example, upon receiving the drive signal for state S2 from the driver system 212, the RF power supply 222 transitions the RF signal 220 from state S0 or state S1 to state S2. State S2 of the RF signal 220 has the parameter level and frequency level of state S2 for the duration of state S2.

[0151] In one embodiment, there is a period of time during each cycle of the synchronization signal 146 in which the RF signal 220 has a parameter level of zero. The RF signal 220 has a parameter level of zero during periods of no state (NS), such as state S0. As an example, the parameter level of the RF signal described herein is zero when the parameter level is close to zero or substantially zero. For example, the parameter level is zero when the parameter level is less than a predetermined value. An example of a predetermined value for the parameter level is 1 watt. Another example of a predetermined value for the parameter level is 0.25 watts. Yet another example of a predetermined value for the parameter level is 0.5 watts. Upon receiving the synchronization signal 146, during each cycle of the synchronization signal 146, the DSP 204 does not transmit command signals for states S1 and S2 to the parameter controllers 206 and 208 during periods of no state.

[0152] During periods when no command signals for states S1 and S2 are received, parameter controllers 206 and 208 do not transmit or stop transmitting the parameter levels for states S1 and S2 to the driver system 212. For example, after a period of time in state S1, parameter controller 206 does not transmit the parameter level for state S1 to the driver system 212. As another example, after a period of time in state S2, parameter controller 208 does not transmit the parameter level for state S2 to the driver system 212.

[0153] If the parameter levels for states S1 and S2 are not received, the driver system 212 does not transmit a drive signal to the RF power supply 222. If the drive signal is not received during a period of no state, the RF power supply 222 generates an RF signal 220 with a parameter level of zero during the period of no state. For example, if the drive signal is not received, the power supply 222 transitions the RF signal 220 from state S1 or state S2 to no state S0.

[0154] In one embodiment, instead of parameter controller 206, one or more controllers such as parameter controller 208 and frequency controller 210, one or more processors are used to perform the functions performed by parameter controllers 206 and 208 and frequency controller 210 as described herein. Each of the one or more controllers includes a processor and a memory device, the processor being coupled to the memory device.

[0155] In one embodiment, instead of the DSP204, one or more controllers such as parameter controller 206, parameter controller 208, and frequency controller 210, and one or more processors are used to perform the functions performed by the DSP204, parameter controllers 206 and 208, and frequency 210 as described herein. Each of the one or more controllers includes a processor and a memory device, the processor being coupled to the memory device.

[0156] Figure 3A is a graph 300 of one embodiment showing the synchronization signal 302. Graph 300 graphs the logic level versus time t of the synchronization signal 302. The synchronization signal 302 is an example of the synchronization signal 146 (Figure 1). The logic level of the synchronization signal 302 is graphed on the y axis, and time t is graphed on the x axis. The logic levels used herein range from 0 to 1, where logic level 0 corresponds to a direct current (DC) of 0 volts (V), and logic level 1 corresponds to a DC of 5 volts. The synchronization signal used herein is a digital pulse signal, such as a square wave, having logic levels 1 and 0.

[0157] The synchronization signal 302 has a duty cycle of 50%. For example, the synchronization signal 302 has a logic level of 1 from time t0 to time t5. The synchronization signal 302 has a logic level of 0 from time t5 to time t10, a logic level of 1 from time t10 to time t15, and a logic level of 0 from time t15 to time t20.

[0158] The time interval between time t0 and t20 is divided into equal time intervals. For example, the time interval between time t0 and t20 is divided into the first time interval between time t0 and time t1, the second time interval between time t1 and time t2, the third time interval between time t2 and time t3, the fourth time interval between time t3 and time t4, the fifth time interval between time t4 and time t5, the sixth time interval between time t5 and time t6, the seventh time interval between time t6 and time t7, the eighth time interval between time t7 and time t8, the ninth time interval between time t8 and time t9, the tenth time interval between time t9 and time t10, and so on. It is divided into the 11th time interval between time t11, the 12th time interval between time t11 and time t12, the 13th time interval between time t12 and time t13, the 14th time interval between time t13 and time t14, the 15th time interval between time t14 and time t15, the 16th time interval between time t15 and time t16, the 17th time interval between time t16 and time t17, the 18th time interval between time t17 and time t18, the 19th time interval between time t18 and time t19, and the 20th time interval between time t19 and time t20. Each of the 1st to 12th time intervals is equal or the same.

[0159] The synchronization signal 302 has multiple cycles, such as cycle 1 and cycle 2, and between each cycle, it alternates between logic levels 1 and 0. For example, during cycle 1, the synchronization signal 302 transitions from logic level 1 to logic level 0 at time t5, and during cycle 2, it transitions from logic level 1 to logic level 0 at time t15. As another example, at time t0 of cycle 1, the synchronization signal 302 transitions from logic level 0 of cycle 0 to logic level 1 of cycle 1. Cycle 0 is the synchronization signal 302 and precedes cycle 1 of the synchronization signal 302. Similarly, at time t10 of cycle 1, the synchronization signal 302 transitions from logic level 0 of cycle 1 to logic level 1 of cycle 2. Times t0 to t10 occur during cycle 1 of the synchronization signal as described herein, and times t10 to t20 occur during cycle 2 of the synchronization signal. Cycle 1 starts at time t0 and ends at time t10, and Cycle 2 starts at time t10 and ends at time t20.

[0160] Each cycle of the synchronization signal described herein is repeated periodically. For example, Cycle 2 of the synchronization signal follows Cycle 1 of the synchronization signal, Cycle 2 of the synchronization signal follows Cycle 0 of the synchronization signal.

[0161] Figure 3B is a graph 304 of one embodiment, showing the parameters 306 versus time t of the RF signal 152, which is an RF signal. The parameters 306 are graphed on the y-axis, and time t is graphed on the x-axis.

[0162] Parameter 306 periodically transitions between parameter levels PR1 and PR2 in synchronization with the synchronization signal 302. For example, parameter 306 transitions between parameter levels PR1 and PR2 during cycle 1 of the synchronization signal 302, and similarly transitions between parameter levels PR1 and PR2 during cycle 2 of the synchronization signal 302. For example, parameter 306 has parameter level PR1 during instances of state S1 from time t0 to time t5, parameter level PR2 during instances of state S2 from time t5 to time t10, parameter level PR1 during another instance of state S1 from time t10 to time t15, and parameter level PR2 during another instance of state S2 from time t15 to time t20. During cycle 1 of the synchronization signal 302, parameter 306 transitions from parameter level PR2 to parameter level PR1 at time t0, and from parameter level PR1 to parameter level PR2 at time t5. During cycle 2 of the synchronization signal 302, parameter 306 also transitions from parameter level PR2 to parameter level PR1 at time t10, and from parameter level PR1 to parameter level PR2 at time t15. Parameter level PR1 is an example of the parameter level for state S1 of the RF signal 152, and parameter level PR2 is an example of the parameter level for state S2 of the RF signal 152.

[0163] Parameter level PR1 is less than parameter level PR2. For example, the power value at parameter level PR1 is less than the power value at parameter level PR2. Another example is that none of the power values ​​at parameter level PR1 exceed the power values ​​at parameter level PR2. Parameter level PR1 is greater than zero.

[0164] In one embodiment, the transition time, which is the time it takes to transition between two parameter levels, is the time period between the two times. For example, instead of transitioning from power level PR1 to power level PR2 at time t5, parameter 306 begins the transition from parameter level PR1 in a first time and ends the transition to parameter level PR2 in a second time. The first time is before time t5, between times t2 and t5, and the second time is after time t5, between times t5 and t8. The transition time period is the transition time between the first time and the second time.

[0165] In one embodiment, rather than transitioning between parameter levels PR1 and PR2, parameter 306 transitions between parameter level 0 and PR2, or between parameter level 0 and PR1.

[0166] In one embodiment, in addition to the synchronization signal 302, a digital pulse signal is received by the DSP 204 from the processor 118 via the transmission cable system 214. For example, the synchronization signal 302 is received via a first transmission cable of the transmission cable system 214, and the digital pulse signal is received via a second transmission cable of the transmission cable system 214. The digital pulse signal similarly transitions periodically between two logic levels, and the parameter 306 transitions between parameter levels PR1 and PR2. For example, during cycle 1 of the synchronization signal 302, the digital pulse signal transitions from logic level 1 to logic level 0 at time t0, and from logic level 0 to logic level 1 at time t5. During cycle 2 of the synchronization signal 302, the digital pulse signal transitions from logic level 1 to logic level 0 at time t10, and from logic level 0 to logic level 1 at time t15. Upon receiving a digital pulse signal, the DSP204 identifies the time periods S1 and S2 of parameter 306 from the digital pulse signal and generates an instruction signal having these time periods. For example, the time period of state S1 of parameter 306 is the same as the time period of logic level 1 of the digital pulse signal, and the time period of state S2 of parameter 306 is the same as the time period of logic level 2 of the digital pulse signal.

[0167] Figure 3C is a graph 308 of one embodiment, showing the parameter 310 versus time t of the RF signal 168 (Figure 1), which is an RF signal. The parameter 310 is graphed on the y axis, and time t is graphed on the x axis. The parameter 310 periodically transitions between parameter levels 0, PR1, and PR2 in synchronization with the synchronization signal 302. For example, the parameter 310 transitions between parameter levels 0, PR2, and PR1 during cycle 1 of the synchronization signal 302, and similarly transitions between parameter levels 0, PR2, and PR1 during cycle 2 of the synchronization signal 302. For example, the parameter 306 has parameter level 0 during instances of state S0 from time t0 to time t2, parameter level PR2 during instances of state S1 from time t2 to time t8, and parameter level PR1 during instances of state S2 from time t8 to time t10. The parameter levels 0, PR2, and PR1 are repeated during cycle 2 of the synchronization signal 302. During cycle 1 of the synchronization signal 402, parameter 310 transitions from parameter level PR1 to parameter level 0 at time t0, from parameter level 0 to parameter level PR2 at time t2, from parameter level PR2 to parameter level PR1 at time t8, and from parameter level PR1 to parameter level 0 at time t10. During cycle 2 of the synchronization signal 302, parameter 310 also transitions from parameter level PR1 to parameter level 0 at time t10, from parameter level 0 to parameter level PR2 at time t12, from parameter level PR2 to parameter level PR1 at time t18, and from parameter level PR1 to parameter level 0 at time t20.

[0168] Parameter level 0 is the parameter level for state S0 of RF signal 168, parameter level PR1 is an example of the parameter level for state S1 of RF signal 168, and parameter level PR2 is an example of the parameter level for state S2 of RF signal 168.

[0169] If the combination of parameter levels 306 and 310 during the first time period is different from the combination of parameter levels 306 and 310 during the second time period, then the plasma impedance state during the first time period is different from the plasma impedance state during the second time period. For example, during the time period between times t0 and t2, the parameter level of parameter 306 of the source RF signal is PR1, and during the time period between times t0 and t2, the parameter level of parameter 310 of the bias RF signal is 0, defining plasma impedance state PS1 in the plasma chamber 112 (Figure 1). In this specification, the plasma impedance state in the plasma chamber 112 may be referred to as the plasma impedance state (PS). During the time period between times t2 and t5, the parameter level of parameter 306 of the source RF signal is PR1, and during the time period between times t2 and t5, the parameter level of parameter 310 of the bias RF signal is PR2, defining another plasma impedance state PS2.

[0170] As another example, during the time period between times t5 and t8, the parameter level of parameter 306 of the source RF signal is PR2, and during the time period between times t5 and t8, the parameter level of parameter 310 of the bias RF signal is also PR2, defining a different plasma impedance state PS3, which is different from plasma impedance states PS1 and PS2, respectively.

[0171] As another example, during the time period between times t8 and t10, the parameter level of parameter 306 of the source RF signal is PR2, and during the time period between times t8 and t10, the parameter level of parameter 310 of the bias RF signal is PR1, defining another plasma impedance state PS4, which is different from plasma impedance states PS1, PS2, and PS3, respectively. Thus, during each cycle of the synchronization signal 302, due to the changes in the parameter levels of the bias RF signal and the source RF signal, multiple plasma impedance states such as four plasma impedance states PS1 to PS4 are generated. The plasma impedance in the plasma chamber 112 (Figure 1) having multiple plasma impedance states PS1 to PS4 is an example of a multi-state plasma impedance.

[0172] In one embodiment, parameter 306 is of RF signal 168, and parameter 310 is of RF signal 152.

[0173] In one embodiment, in addition to the synchronization signal 302, a digital pulse signal is received by the DSP 204 from the processor 118 via the transmission cable system 214. For example, the synchronization signal 302 is received via the first transmission cable of the transmission cable system 214, and the digital pulse signal is received via the second transmission cable of the transmission cable system 214. The digital pulse signal transitions periodically between three logic levels, and the parameter 310 transitions between parameter levels 0, PR2, and PR1. For example, during cycle 1 of the synchronization signal 302, the digital pulse signal transitions from logic level 1 to logic level 0 at time t0, from logic level 0 to logic level 2 at time t2, and from logic level 2 to logic level 1 at time t8. Logic level 2 is greater than logic level 1. For example, logic level 1 has a DC voltage greater than logic level 1. During cycle 2 of the synchronization signal 302, the digital pulse signal transitions from logic level 1 to logic level 0 at time t10, from logic level 0 to logic level 2 at time t12, and from logic level 2 to logic level 1 at time t18. Upon receiving the digital pulse signal, the DSP 204 identifies the time periods S0, S2, and S1 of parameter 310 from the digital pulse signal and generates an instruction signal having these time periods. For example, the time period of state S0 of parameter 310 is the same as the time period of logic level 0 of the digital pulse signal, the time period of state S1 of parameter 310 is the same as the time period of logic level 1 of the digital pulse signal, and the time period of state S2 of parameter 310 is the same as the time period of logic level 2 of the digital pulse signal.

[0174] Figure 4A is a graph 300 of one embodiment.

[0175] Figure 4B is a graph 304 of one embodiment.

[0176] Figure 4C is a graph 400 of one embodiment, showing the parameters 402 of an RF signal 168 versus time t (Figure 1). Parameter 402 is graphed on the y-axis, and time t is graphed on the x-axis. Parameter 402 periodically transitions between parameter levels 0, PR2, and PR1 in synchronization with the synchronization signal 302. For example, parameter 402 transitions between parameter levels 0, PR2, and PR1 during cycle 1 of the synchronization signal 302, and then again between parameter levels 0, PR2, and PR1 during cycle 2 of the synchronization signal 302. For example, parameter 402 has parameter level 0 during instances of state S0 from time t0 to time t2, parameter level PR2 during instances of state S1 from time t2 to time t8, parameter level PR1 during instances of state S2 from time t8 to time t9, and parameter level 0 during another instance of state S0 from time t9 to time t10. The parameter levels 0, PR2, and PR1 are repeated during cycle 2 of the synchronization signal 302. During cycle 1 of the synchronization signal 310, parameter 402 transitions from parameter level 0 to parameter level PR2 at time t2, from parameter level PR2 to parameter level PR1 at time t8, and from parameter level PR1 to parameter level 0 at time t9. During cycle 2 of the synchronization signal 310, parameter 402 also transitions from parameter level 0 to parameter level PR2 at time t12, from parameter level PR2 to parameter level PR1 at time t18, and from parameter level PR1 to parameter level 0 at time t19.

[0177] If the combination of parameter levels 306 and 402 during the first time period is different from the combination of parameter levels 306 and 402 during the second time period, then the plasma impedance state during the first time period will be different from the plasma impedance state during the second time period. For example, during the time period between times t0 and t2, the parameter level of parameter 306 of the source RF signal is PR1, and during the time period between times t0 and t2, the parameter level of parameter 402 of the bias RF signal is 0, defining plasma impedance state PS1. During the time period between times t2 and t5, the parameter level of parameter 306 of the source RF signal is PR1, and during the time period between times t2 and t5, the parameter level of parameter 402 of the bias RF signal is PR2, defining another plasma impedance state PS2.

[0178] As another example, during the time period between times t5 and t8, the parameter level of parameter 306 of the source RF signal is PR2, and during the time period between times t5 and t8, the parameter level of parameter 402 of the bias RF signal is also PR2, defining another plasma impedance state PS3, which is different from plasma impedance states PS1 and PS2, respectively.

[0179] As another example, during the time period between times t8 and t9, the parameter level of parameter 306 of the source RF signal is PR2, and during the time period between times t8 and t9, the parameter level of parameter 402 of the bias RF signal is PR1, defining another plasma impedance state PS4, which is different from plasma impedance states PS1, PS2, and PS3, respectively.

[0180] As another example, during the time period between times t9 and t10, the parameter level of parameter 306 of the source RF signal is PR2, and during the time period between times t9 and t10, the parameter level of parameter 402 of the bias RF signal is 0, defining a different plasma impedance state PS5, which is different from each of the plasma impedance states PS1, PS2, PS3, and PS4.

[0181] Therefore, during each cycle of the synchronization signal 302, multiple plasma impedance states are generated, such as five plasma impedance states PS1 to PS5, due to changes in the parameter levels of the bias RF signal and the source RF signal. The plasma impedance in the plasma chamber 112 (Figure 1) having multiple plasma impedance states PS1 to PS5 is an example of a multi-state plasma impedance.

[0182] In one embodiment, parameter 306 is of RF signal 168, and parameter 402 is of RF signal 152.

[0183] In one embodiment, in addition to the synchronization signal 310, a digital pulse signal is received by the DSP 204 from the processor 118 via the transmission cable system 214. For example, the synchronization signal 302 is received via the first transmission cable of the transmission cable system 214, and the digital pulse signal is received via the second transmission cable of the transmission cable system 214. The digital pulse signal transitions periodically between three logic levels, and the parameter 402 transitions between parameter levels 0, PR2, and PR1. For example, during cycle 1 of the synchronization signal 302, the digital pulse signal transitions from logic level 0 to logic level 2 at time t2, from logic level 2 to logic level 1 at time t8, and from logic level 1 to logic level 0 at time t9. During cycle 2 of the synchronization signal 302, the digital pulse signal transitions from logic level 0 to logic level 2 at time t12, from logic level 2 to logic level 1 at time t18, and from logic level 1 to logic level 0 at time t19. Upon receiving the digital pulse signal, the DSP 204 identifies the time periods S0, S2, and S1 of parameter 402 from the digital pulse signal and generates an instruction signal having these time periods. For example, the time period of state S0 of parameter 402 is the same as the time period of logic level 0 of the digital pulse signal, the time period of state S1 of parameter 402 is the same as the time period of logic level 1 of the digital pulse signal, and the time period of state S2 of parameter 402 is the same as the time period of logic level 2 of the digital pulse signal.

[0184] Figure 5A is a graph 500 of one embodiment showing the synchronization signal 502. Graph 500 graphs the logic level of the synchronization signal 502 against time t. The synchronization signal 502 is an example of the synchronization signal 146 (Figure 1). The logic level of the synchronization signal 502 is graphed on the y-axis, and time t is graphed on the x-axis.

[0185] Synchronization signal 502 has a duty cycle of 70%. For example, synchronization signal 502 has logic level 1 from time t0 to time t7. Synchronization signal 302 has logic level 0 from time t7 to time t10, logic level 1 from time t10 to time t17, and logic level 0 from time t17 to time t20.

[0186] The synchronization signal 502 has multiple cycles, during which it alternates between logic levels 1 and 0. For example, during cycle 1, the synchronization signal 502 transitions from logic level 1 to logic level 0 at time t7, and during cycle 2, it transitions from logic level 1 to logic level 0 at time t17. As another example, at time t0 of cycle 1, the synchronization signal 502 transitions from logic level 0 of cycle 0 to logic level 1 of cycle 1. Similarly, at time t10 of cycle 1, the synchronization signal 502 transitions from logic level 0 of cycle 1 to logic level 1 of cycle 2. Cycle 0 of the synchronization signal 502 precedes cycle 1 of the synchronization signal 502, and cycle 1 of the synchronization signal 502 precedes cycle 2 of the synchronization signal 502.

[0187] In one embodiment, the synchronization signal 502 has a different duty cycle, such as a 50% duty cycle or a 60% duty cycle, rather than a 70% duty cycle.

[0188] Figure 5B is a graph 504 of one embodiment, showing the parameters 506 versus time t of the RF signal 152, which is an RF signal. The parameters 506 are graphed on the y-axis, and time t is graphed on the x-axis.

[0189] Parameter 506 periodically transitions between parameter levels 0, PR1, and PR2 in a state synchronized with the synchronization signal 502. For example, parameter 506 transitions between parameter levels 0, PR2, and PR1 during cycle 1 of the synchronization signal 502, and similarly transitions between parameter levels 0, PR2, and PR1 during cycle 2 of the synchronization signal 502. For example, parameter 506 has parameter level 0 during instances of state S0 from time t0 to time t3, parameter level PR2 during state S1 from time t3 to time t8, parameter level PR1 during another instance of state S2 from time t8 to time t9, and parameter level 0 during another instance of state S0 from time t9 to time t10. Parameter 506 repeats the occurrence sequence of states S0, S2, S1, and S0 during cycle 2 of the synchronization signal 502. During cycle 1 of the synchronization signal 502, parameter 506 transitions from parameter level 0 to parameter level PR2 at time t3, from parameter level PR2 to parameter level PR1 at time t8, and from parameter level PR1 to parameter level 0 at time t9. During cycle 2 of the synchronization signal 502, parameter 506 repeatedly transitions between parameter levels 0, PR2, and PR1.

[0190] In one embodiment, in addition to the synchronization signal 502, a digital pulse signal is received by the DSP 204 from the processor 118 via the transmission cable system 214. For example, the synchronization signal 502 is received via the first transmission cable of the transmission cable system 214, and the digital pulse signal is received via the second transmission cable of the transmission cable system 214. The digital pulse signal similarly transitions periodically between three logic levels, and the parameter 506 transitions between parameter levels 0, PR2, and PR1. For example, during cycle 1 of the synchronization signal 502, the digital pulse signal transitions from logic level 0 to logic level 2 at time t3, from logic level 2 to logic level 1 at time t8, and from logic level 1 to logic level 0 at time t9. During cycle 2 of the synchronization signal 502, the digital pulse signal transitions from logic level 0 to logic level 2 at time t13, from logic level 2 to logic level 1 at time t18, and from logic level 1 to logic level 0 at time t19. Upon receiving the digital pulse signal, the DSP 204 identifies the time periods S0, S2, and S1 of parameter 502 from the digital pulse signal and generates an instruction signal having these time periods. For example, the time period of state S0 of parameter 506 is the same as the time period of logic level 0 of the digital pulse signal, the time period of state S2 of parameter 506 is the same as the time period of logic level 2 of the digital pulse signal, and the time period of state S1 of parameter 506 is the same as the time period of logic level 1 of the digital pulse signal.

[0191] Figure 5C is a graph 508 of one embodiment, showing the parameter 510 versus time t of the RF signal 168 (Figure 1), which is an RF signal. The parameter 510 is graphed on the y axis, and time t is graphed on the x axis. The parameter 510 periodically transitions between parameter levels PR1, PR2, and 0 in synchronization with the synchronization signal 502. For example, the parameter 510 transitions between parameter levels PR1, PR2, and 0 during cycle 1 of the synchronization signal 502, and similarly transitions between parameter levels PR1, PR2, and 0 during cycle 2 of the synchronization signal 502. Exemplify, the parameter 510 has parameter level PR1 during the instance of state S1 from time t0 to time t2, parameter level PR2 during state S2 from time t2 to time t5, parameter level PR1 during another instance of state S1 from time t5 to time t9, and parameter level 0 during state S0 from time t9 to time t10. The parameter levels PR1, PR2, and 0 are repeated during cycle 2 of the synchronization signal 502. During cycle 1 of the synchronization signal 502, parameter 510 transitions from parameter level 0 to parameter level PR1 at time t0, from parameter level PR1 to parameter level PR2 at time t2, from parameter level PR2 to parameter level PR1 at time t5, and from parameter level PR1 to parameter level 0 at time t9. During cycle 2 of the synchronization signal 502, parameter 510 again transitions from parameter level 0 to parameter level PR1 at time t10, from parameter level PR1 to parameter level PR2 at time t12, from parameter level PR2 to parameter level PR1 at time t15, and from parameter level PR1 to parameter level 0 at time t19.

[0192] If the combination of parameter levels 506 and 510 during the first time period is different from the combination of parameter levels 506 and 510 during the second time period, then the plasma impedance state during the first time period will be different from the plasma impedance state during the second time period. For example, during the time period between times t0 and t2, the parameter level of parameter 506 of the source RF signal is 0, and during the time period between times t0 and t2, the parameter level of parameter 510 of the bias RF signal is PR1, defining plasma impedance state PS1. During the time period between times t2 and t3, the parameter level of parameter 506 of the source RF signal is 0, and during the time period between times t2 and t3, the parameter level of parameter 510 of the bias RF signal is PR2, defining another plasma impedance state PS2.

[0193] As another example, during the time period between times t3 and t5, the parameter level of parameter 506 of the source RF signal is PR2, and during the time period between times t3 and t5, the parameter level of parameter 510 of the bias RF signal is PR2, defining another plasma impedance state PS1, and plasma impedance state PS3 is different from plasma impedance states PS1 and PS2, respectively. As yet another example, during the time period between times t5 and t8, the parameter level of parameter 506 of the source RF signal is PR2, and during the time period between times t5 and t8, the parameter level of parameter 510 of the bias RF signal is PR1, defining another plasma impedance state PS4, and plasma impedance state PS4 is different from plasma impedance states PS1, PS2 and PS3, respectively.

[0194] As another example, during the time period between times t8 and t9, the parameter level of parameter 506 of the source RF signal is PR1, and during the time period between times t8 and t9, the parameter level of parameter 510 of the bias RF signal is PR1, defining another plasma impedance state PS5, which is different from each of the plasma impedance states PS1, PS2, PS3, and PS4. As yet another example, during the time period between times t9 and t10, the parameter level of parameter 506 of the source RF signal is 0, and during the time period between times t9 and t10, the parameter level of parameter 510 of the bias RF signal is 0, defining another plasma impedance state PS6, which is different from each of the plasma impedance states PS1, PS2, PS3, PS4, and PS5. Thus, during each cycle of the synchronization signal 502, due to the changes in the parameter levels of the bias RF signal and the source RF signal, multiple plasma impedance states such as six plasma impedance states PS1 to PS6 are generated. The plasma impedance in a plasma chamber 112 (Figure 1) having multiple plasma impedance states PS1 to PS6 is an example of multiple plasma impedance states.

[0195] In one embodiment, parameter 506 is of RF signal 168, and parameter 510 is of RF signal 152.

[0196] In one embodiment, in addition to the synchronization signal 502, a digital pulse signal is received by the DSP 204 from the processor 118 via the transmission cable system 214. For example, the synchronization signal 502 is received via the first transmission cable of the transmission cable system 214, and the digital pulse signal is received via the second transmission cable of the transmission cable system 214. The digital pulse signal transitions periodically between three logic levels, and the parameter 510 transitions between parameter levels 0, PR1, and PR2. For example, during cycle 1 of the synchronization signal 502, the digital pulse signal transitions from logic level 0 to logic level 1 at time t0, from logic level 1 to logic level 2 at time t2, from logic level 2 to logic level 1 at time t5, and from logic level 1 to logic level 0 at time t9. During cycle 2 of the synchronization signal 502, the digital pulse signal transitions from logic level 0 to logic level 1 at time t10, from logic level 1 to logic level 2 at time t12, from logic level 2 to logic level 1 at time t15, and from logic level 1 to logic level 0 at time t19. Upon receiving the digital pulse signal, the DSP 204 identifies the time periods S0, S1, and S2 of parameter 510 from the digital pulse signal and generates an instruction signal having these time periods. For example, the time period of state S0 of parameter 510 is the same as the time period of logic level 0 of the digital pulse signal, the time period of state S2 of parameter 510 is the same as the time period of logic level 2 of the digital pulse signal, and the time period of state S1 of parameter 510 is the same as the time period of logic level 1 of the digital pulse signal.

[0197] Figure 6A is a graph 600 of one embodiment showing the synchronization signal 602. Graph 600 graphs the logic level of the synchronization signal 602 against time t. The synchronization signal 602 is an example of the synchronization signal 146 (Figure 1). The logic level of the synchronization signal 602 is graphed on the y-axis, and time t is graphed on the x-axis.

[0198] The synchronization signal 602 has a duty cycle of 30%. For example, the synchronization signal 602 has a logic level of 1 from time t0 to time t3. The synchronization signal 602 has a logic level of 0 from time t3 to time t10, a logic level of 1 from time t10 to time t13, and a logic level of 0 from time t13 to time t20.

[0199] The synchronization signal 602 has multiple cycles, during which it alternates between logic levels 1 and 0. For example, during cycle 1, the synchronization signal 602 transitions from logic level 1 to logic level 0 at time t3, and during cycle 2, it transitions from logic level 1 to logic level 0 at time t13. As another example, at time t0 of cycle 1, the synchronization signal 602 transitions from logic level 0 of cycle 0 to logic level 1 of cycle 1. Similarly, at time t10 of cycle 1, the synchronization signal 602 transitions from logic level 0 of cycle 1 to logic level 1 of cycle 2. Cycle 0 of the synchronization signal 602 precedes cycle 1 of the synchronization signal 602, and cycle 1 of the synchronization signal 602 precedes cycle 2 of the synchronization signal 602.

[0200] In one embodiment, the synchronization signal 602 has a different duty cycle, such as a 50% duty cycle or a 60% duty cycle, instead of a 30% duty cycle.

[0201] Figure 6B is a graph 604 of one embodiment, showing the parameters 606 versus time t of the RF signal 152, which is an RF signal. The parameters 606 are graphed on the y-axis, and time t is graphed on the x-axis.

[0202] Parameter 606 periodically transitions between parameter levels PR2, PR1, and 0 in synchronization with the synchronization signal 602. For example, parameter 606 transitions between parameter levels PR2, PR1, and 0 during cycle 1 of the synchronization signal 602, and similarly during cycle 2 of the synchronization signal 602. For example, parameter 606 has parameter level PR2 during state S2 from time t0 to time t3, parameter level PR1 during state S1 from time t3 to time t7, and parameter level 0 during state S0 from time t7 to time t10. Parameter 606 repeats the sequence of states S2, S1, and S0 during cycle 2 of the synchronization signal 602. Furthermore, during cycle 1 of the synchronization signal 602, parameter 606 transitions from parameter level 0 to parameter level PR2 at time t0, from parameter level PR2 to parameter level PR1 at time t3, and from parameter level PR1 to parameter level 0 at time t7. Parameter 506 repeatedly transitions between parameter levels PR2, PR1, and P0 during cycle 2 of the synchronization signal 602. For example, during cycle 2 of the synchronization signal 602, parameter 606 transitions from parameter level 0 to parameter level PR2 at time t10, from parameter level PR2 to parameter level PR1 at time t13, and from parameter level PR1 to parameter level 0 at time t17.

[0203] In one embodiment, in addition to the synchronization signal 602, a digital pulse signal is received by the DSP 204 from the processor 118 via the transmission cable system 214. For example, the synchronization signal 602 is received via the first transmission cable of the transmission cable system 214, and the digital pulse signal is received via the second transmission cable of the transmission cable system 214. The digital pulse signal transitions periodically between three logic levels, and the parameter 606 transitions between parameter levels 0, PR2, and PR1. For example, during cycle 1 of the synchronization signal 602, the digital pulse signal transitions from logic level 0 to logic level 2 at time t0, from logic level 2 to logic level 1 at time t3, and from logic level 1 to logic level 0 at time t7. During cycle 2 of the synchronization signal 602, the digital pulse signal transitions from logic level 0 to logic level 2 at time t10, from logic level 2 to logic level 1 at time t13, and from logic level 1 to logic level 0 at time t17. Upon receiving the digital pulse signal, the DSP204 identifies the time periods S2, S1, and S0 of parameter 602 from the digital pulse signal and generates an instruction signal having these time periods. For example, the time period of state S0 of parameter 606 is the same as the time period of logic level 0 of the digital pulse signal, the time period of state S2 of parameter 606 is the same as the time period of logic level 2 of the digital pulse signal, and the time period of state S1 of parameter 606 is the same as the time period of logic level 1 of the digital pulse signal.

[0204] Figure 6C is a graph 608 of one embodiment, showing the parameter 610 versus time t of the RF signal 168 (Figure 1), which is an RF signal. The parameter 610 is graphed on the y axis, and time t is graphed on the x axis. The parameter 610 periodically transitions between parameter levels 0, PR1, and PR2 in synchronization with the synchronization signal 602. For example, the parameter 610 transitions between parameter levels 0, PR1, and PR2 during cycle 1 of the synchronization signal 602, and similarly transitions between parameter levels 0, PR1, and PR2 during cycle 2 of the synchronization signal 602. Exemplarily, the parameter 610 has parameter level 0 during state S0 from time t0 to time t1, parameter level PR1 during state S1 from time t1 to time t5, parameter level PR2 during another instance of state S2 from time t5 to time t8, and parameter level 0 during another instance of state S0 from time t8 to time t10. Parameter levels 0, PR1, and PR2 are repeated during cycle 2 of the synchronization signal 602. During cycle 1 of the synchronization signal 602, parameter 610 transitions from parameter level 0 to parameter level PR1 at time t1, from parameter level PR1 to parameter level PR2 at time t5, and from parameter level PR2 to parameter level 0 at time t8. During cycle 2 of the synchronization signal 602, parameter 610 again transitions from parameter level 0 to parameter level PR1 at time t11, from parameter level PR1 to parameter level PR2 at time t15, and from parameter level PR2 to parameter level 0 at time t18.

[0205] If the combination of parameter levels 606 and 610 during the first time period is different from the combination of parameter levels 606 and 610 during the second time period, then the plasma impedance state during the first time period will be different from the plasma impedance state during the second time period. For example, during the time period between times t0 and t1, the parameter level of parameter 606 of the source RF signal is PR2, and during the time period between times t0 and t1, the parameter level of parameter 610 of the bias RF signal is 0, defining plasma impedance state PS1. During the time period between times t1 and t3, the parameter level of parameter 606 of the source RF signal is PR2, and during the time period between times t1 and t3, the parameter level of parameter 610 of the bias RF signal is PR1, defining another plasma impedance state PS2.

[0206] As another example, during the time period between times t3 and t5, the parameter level of parameter 606 of the source RF signal is PR1, and during the time period between times t3 and t5, the parameter level of parameter 610 of the bias RF signal is PR1, defining another plasma impedance state PS3, which is different from plasma impedance states PS1 and PS2, respectively. As yet another example, during the time period between times t5 and t7, the parameter level of parameter 606 of the source RF signal is PR1, and during the time period between times t5 and t7, the parameter level of parameter 610 of the bias RF signal is PR2, defining another plasma impedance state PS4, which is different from plasma impedance states PS1, PS2, and PS3, respectively.

[0207] As another example, during the time period between t7 and t8, the parameter level of parameter 606 of the source RF signal is 0, and during the time period between t7 and t8, the parameter level of parameter 610 of the bias RF signal is PR2, defining another plasma impedance state PS5, and the plasma impedance state PS5 is different from each of the plasma impedance states PS1, PS2, PS3, and PS4. As yet another example, during the time period between t8 and t10, the parameter level of parameter 606 of the source RF signal is 0, and during the time period between t8 and t10, the parameter level of parameter 610 of the bias RF signal is 0, defining another plasma impedance state PS6, and the plasma impedance state PS6 is different from each of the plasma impedance states PS1, PS2, PS3, PS4, and PS5. Therefore, due to the change in the parameter levels of the bias RF signal and the source RF signal during each cycle of the synchronization signal 602, a plurality of plasma impedance states such as six plasma impedance states PS1 to PS6 are generated. The plasma impedance in the plasma chamber 112 (FIG. 1) having the plurality of plasma impedance states PS1 to PS6 is an example of a multi-state plasma impedance.

[0208] In one embodiment, parameter 606 is of RF signal 168, and parameter 610 is of RF signal 152.

[0209] In one embodiment, in addition to the synchronization signal 602, the digital pulse signal is received by the DSP 204 from the processor 118 via the transmission cable system 214. For example, the synchronization signal 602 is received via the first transmission cable of the transmission cable system 214, and the digital pulse signal is received via the second transmission cable of the transmission cable system 214. The digital pulse signal also transitions periodically among three logic levels, and the parameter 610 transitions between the parameter level 0, PR1, and PR2. For example, during cycle 1 of the synchronization signal 502, the digital pulse signal transitions from logic level 0 to logic level 1 at time t1, from logic level 1 to logic level 2 at time t5, and from logic level 2 to logic level 1 at time t8. During cycle 2 of the synchronization signal 602, the digital pulse signal transitions from logic level 0 to logic level 1 at time t11, from logic level 1 to logic level 2 at time t15, and from logic level 2 to logic level 1 at time t18. When receiving the digital pulse signal, the DSP 204 identifies the time periods of S0, S2, and S1 of the parameter 610 from the digital pulse signal and generates command signals having these time periods. For example, the time period of the state S0 of the parameter 610 is the same as the time period of the logic level 0 of the digital pulse signal, the time period of the state S2 of the parameter 610 is the same as the time period of the logic level 2 of the digital pulse signal, and the time period of the state S1 of the parameter 610 is the same as the time period of the logic level 1 of the digital pulse signal.

[0210] In one embodiment, for any of the parameters 310 (FIG. 3C), 402 (FIG. 4C), 510 (FIG. 5C), and 610 (FIG. 6C), instead of the parameter level PR1, the parameter level PR3 is used. The parameter level PR3 is greater than or less than the parameter level PR1. Similarly, for any of the parameters 310, 402, 510, and 610, instead of the parameter level PR2, the parameter level PR4 is used. The parameter level PR4 is greater than or less than the parameter level PR3.

[0211] Figure 6D illustrates one embodiment of on / off time correction by selective synchronization between a source RF generator and a bias RF generator. As illustrated in Figure 6D, when tuning the RF signal generated by a first RF generator, such as a source RF generator or a bias RF generator, there is a time delay from time t1 to time t2 compared to a second RF generator, such as a bias RF generator or a source RF generator. Also, the time when the RF power supplied to the first RF generator is off is advanced from time t4 to time t3. Therefore, instead of two plasma impedance states S1 and S0, three or more plasma impedance states are generated, such as 6, 8, 10, or 20 plasma impedance states.

[0212] Multiple-state pulsed component

[0213] Figure 7 is a diagram of one embodiment of the plasma system 700, showing the pulsation of multiple levels of parameters. The plasma system 700 includes an RF generator 702 and a host computer 106. The RF generator 702 is an example of a source RF generator 102 (Figure 1) or a bias RF generator 104 (Figure 1). The RF generator 702 includes a DSP 204 and a plurality of parameter controllers PRS1a, PRS2a, PRS3a...PRSna, where n is an integer of 4 or greater. For example, n is 4 or greater. As an example, the RF generator 702 includes four parameter controllers, one parameter controller for state S1a, another for state S2a, another for state S3a, and another for state S4a. As another example, the RF generator 702 includes five parameter controllers, one parameter controller in state S1a, another in state S2a, another in state S3a, another in state S4a, and one parameter controller in state S5a. The RF generator 702 further includes a frequency controller FC210, a driver system 710, and an RF power supply 222.

[0214] The DSP204 is coupled to the parameter controllers PRS1a to PRSna of the RF generator 702. The parameter controllers PRS1a to PRSna are coupled to the driver system 710, which is coupled to the RF power supply 222. The frequency controller 210 is also coupled to the driver system 710.

[0215] The processor 118 supplies parameters such as parameter levels for Sna and a synchronization signal 146 from state S1a to the DSP 204 via the transmission cable system 214. Upon receiving the parameter levels for Sna from state S1a, the DSP 204 supplies the parameters of state S1a, such as the power level or voltage level, of RF signal 712 to the parameter controller PRS 1a, and stores the parameters of state S1a in the memory device of the parameter controller PRS 1a. RF signal 712 is an example of RF signal 152 or RF signal 168 (Figure 1).

[0216] Furthermore, upon receiving the parameter level for Sna from state S1a, the DSP204 supplies the parameter level, such as the power level or voltage level, of state S2a of the RF signal 712 to the parameter controller S2a, and stores the parameter level of state S2a in the memory device of the parameter controller S2a. In addition, upon receiving the parameter level for Sna from state S1a, the DSP204 supplies the parameter level, such as the power level or voltage level, of state S3a of the RF signal 712 to the parameter controller PRS3a, and stores the parameters of state PRS3a in the memory device of the parameter controller S3a. Upon receiving the parameters for Sna from state S1a, the DSP204 supplies the parameter level, such as the power level or voltage level, of state Sna of the RF signal 712 to the parameter controller PRSna, and stores the parameters of state Sna in the memory device of the parameter controller PRSna. Similarly, upon receiving the parameters of Sna from state S1a, the DSP204 supplies the frequency levels, such as a single frequency level for Sna from all states S1a, to the frequency controller 210, which stores them in the memory device of the frequency controller 210.

[0217] In one embodiment, the value of the (n-1)th parameter level is different from the value of the nth parameter level. For example, the value of the (n-1)th variable level excludes the value of the nth parameter level. As another example, none of the values ​​of the (n-1)th parameter levels are the same as any of the values ​​of the nth parameter level.

[0218] Upon receiving the synchronization signal 146, the DSP 204 transmits a command signal for state S1a to the parameter controller PRS 1a during each cycle of the synchronization signal 146. For example, the DSP 204 transmits a command signal for state S1a to the parameter controller PRS 1a when transitioning to state S1a from a state different from or other than state S1a, such as state Sna or state S0. The command signal for state S1a transmitted to the parameter controller PRS 1a includes the time period of state S1a during each cycle, and the parameter controller PRS 1a supplies the parameter level for state S1a to the driver system 710. Upon receiving the command signal for state S1a, the parameter controller PRS 1a accesses the parameter level for state S1a from its memory device and transmits the parameter level for the time period of state S1a to the driver system 710. For example, when the parameter controller PRS1a transitions from a different state to state S1a, it transmits the parameter level of state S1a to the driver system 710. After the time period of state S1a, for the duration of the synchronization signal 146, the parameter controller PRS1a does not transmit the parameter level of state S1a to the driver system 710.

[0219] Similarly, upon receiving the synchronization signal 146, the DSP 204 transmits a command signal for state S2a to the parameter controller PRS 2a during each cycle of the synchronization signal 146. For example, the DSP 204 transmits a command signal for state S2a to the parameter controller PRS 2a when transitioning to state S2a from a state different from or other than state S2a, such as state S1a, state S3a, or state S0. The command signal for state S2a transmitted to the parameter controller PRS 2a includes the time period of state S2a during each cycle, and the parameter controller PRS 2a supplies the parameter level for state S2a to the driver system 710. Upon receiving the command signal for state S2a, the parameter controller PRS 2a accesses the parameter level for state S2a from its memory device and transmits the parameter level for the time period of state S2a to the driver system 710. For example, when the parameter controller PRS2a transitions from a different state to state S2a, it transmits the parameter level of state S2a to the driver system 710. After the time period of state S2a, for the duration of the synchronization signal 146, the parameter controller PRS2a does not transmit the parameter level of state S2a to the driver system 710.

[0220] Furthermore, upon receiving the synchronization signal 146, the DSP 204 transmits a command signal for state S3a to the parameter controller PRS 3a during each cycle of the synchronization signal 146. For example, the DSP 204 transmits a command signal for state S3a to the parameter controller PRS 3a when transitioning to state S3a from a state different from or other than state S3a, such as state S2a, state S1a, or state S0. The command signal for state S3a transmitted to the parameter controller PRS 3a includes the time period of state S3a during each cycle, and the parameter controller PRS 3a supplies the parameter level for state S3a to the driver system 710. Upon receiving the command signal for state S3a, the parameter controller PRS 3a accesses the parameter level for state S3a from its memory device and transmits the parameter level for the time period of state S3a to the driver system 710. For example, when the parameter controller PRS3a transitions from a different state to state S3a, it transmits the parameter level of state S3a to the driver system 710. After the time period of state S3a, for the duration of the synchronization signal 146, the parameter controller PRS3a does not transmit the parameter level of state S3a to the driver system 710.

[0221] Furthermore, upon receiving the synchronization signal 146, the DSP 204 transmits a command signal for state Sna to the parameter controller PRSna during each cycle of the synchronization signal 146. For example, the DSP 204 transmits a command signal for state Sna to the parameter controller PRSna when transitioning to state Sna from a state different from state Sna, such as state S(n-1)a or state S0, or from a state other than state Sna. The command signal for state Sna transmitted to the parameter controller PRSna includes the time period of state Sna during each cycle, and the parameter controller PRSna supplies the parameter level of state Sna to the driver system 710. Upon receiving the command signal for state Sna, the parameter controller PRSna accesses the parameter level of state Sna from its memory device and transmits the parameter level for the time period of state Sna to the driver system 710. For example, when the parameter controller PRSna transitions to state Sna from a different state, it transmits the parameter level of state Sna to the driver system 710. After the time period of state Sna, for the duration of the synchronization signal 146, the parameter controller PRSna does not transmit the parameter level of state Sna to the driver system 710.

[0222] Furthermore, upon receiving the synchronization signal 146, the DSP 204 transmits a command signal to the frequency controller 210 during each cycle of the synchronization signal 146. Upon receiving the command signal, the frequency controller 210 accesses the frequency level from its memory device and transmits the frequency level to the driver system 710.

[0223] In response to receiving the parameter level and frequency level of state S1a, the driver system 710 generates a drive signal for state S1a during the time period of state S1a and transmits the drive signal to the RF power supply 222. For example, when transitioning to state S1a from a state different from or other than state S1a, such as state Sna, state S2a, state S3a, or state S0, upon receiving the parameter level and frequency level of state S1a, the driver system 710 generates a drive signal for state S1a during the time period of state S1a and transmits the drive signal to the RF power supply 222. When the RF power supply 222 receives the drive signal for state S1a from the driver system 710, it generates state S1a for the RF signal 712. For example, upon receiving the drive signal for state S1a from the driver system 710, the RF power supply 222 transitions the RF signal 712 from a state different from state S1a to state S1a. The state S1a of the RF signal 712 has the parameter level and frequency level of state S1a for the duration of the state S1a.

[0224] Similarly, upon receiving the parameter level and frequency level of state S2a, the driver system 710 generates a drive signal for state S2a for the duration of state S2a and transmits the drive signal to the RF power supply 222. For example, when transitioning to state S2a from a state different from or other than state S2a, such as state S1a, state S3a, state Sna, or state S0, upon receiving the parameter level and frequency level of state S2a, the driver system 710 generates a drive signal for state S2a for the duration of state S2a and transmits the drive signal to the RF power supply 222. When the RF power supply 222 receives the drive signal for state S2a from the driver system 710, it generates state S2a for the RF signal 712. For example, upon receiving the drive signal for state S2a from the driver system 710, the RF power supply 222 transitions the RF signal 712 from a state different from state S2a to state S2a. The state S2a of the RF signal 712 has the parameter level and frequency level of state S2a for the duration of the state S2a.

[0225] Furthermore, in response to the reception of the parameter level and frequency level of state S3a, the driver system 710 generates a drive signal for state S3a during the time period of state S3a and transmits the drive signal to the RF power supply 222. For example, when transitioning to state S3a from a state different from or other than state S3a, such as state S2a, state S4a, state Sna, or state S0, the driver system 710 receives the parameter level and frequency level of state S3a, generates a drive signal for state S3a during the time period of state S3a, and transmits the drive signal to the RF power supply 222. When the RF power supply 222 receives the drive signal for state S3a from the driver system 710, it generates state S3a for the RF signal 712. For example, when the RF power supply 222 receives the drive signal for state S3a from the driver system 710, it transitions the RF signal 712 from a state different from state S3a to state S3a. The RF signal 712 has a parameter level and frequency level for the duration of the time period of state S3a.

[0226] Furthermore, upon receiving the parameter level and frequency level of state Sna, the driver system 710 generates a drive signal for state Sna during the time period of state Sna and transmits the drive signal to the RF power supply 222. For example, when transitioning to state Sna from a state different from or other than state Sna, such as state S(n-1)a, state S0, state S3, or state S2, upon receiving the parameter level and frequency level of state Sna, the driver system 710 generates a drive signal for state Sna during the time period of state Sna and transmits the drive signal to the RF power supply 222. When the RF power supply 222 receives the drive signal for state Sna from the driver system 710, it generates state Sna for RF signal 712. For example, upon receiving the drive signal for state Sna from the driver system 710, the RF power supply 222 transitions RF signal 712 from a state different from state Sna to state Sna. State Sna of RF signal 712 has the parameter level and frequency level of state Sna for the time period of state Sna.

[0227] Also, in one embodiment, there is a time period during each cycle of the synchronization signal 146 in which the RF signal 712 has a parameter level of zero. The RF signal 712 has a parameter level of zero during the absence of a state such as state S0. Upon receiving the synchronization signal 146, during each cycle of the synchronization signal 146, the DSP 204 does not transmit the command signals of states S1a to Sna from the parameter controller PRS1a to PRSna during the time period of the absence of a state.

[0228] During the time period of the absence of a state when not receiving the command signals of states S1a to Sna, the parameter controllers PRS1a to PRSna do not transmit the parameter levels of states S1a to Sna to the driver system 710 or stop the transmission. For example, after the time period of state S1a, the parameter controller PRS1a does not transmit the parameter level of state S1a to the driver system 710. As another example, after the time period of state S2a, the parameter controller PRS2a does not transmit the parameter level of state S2a to the driver system 710.

[0229] When not receiving the parameter levels of states S1a to Sna, the driver system 710 does not transmit the drive signal to the RF power supply 222. When not receiving the drive signal during the time period of the absence of a state, the RF power supply 710 generates an RF signal 712 having a parameter level of zero during the absence of a state. For example, when not receiving the drive signal, the power supply 222 transitions the RF signal 712 from a state different from the absence of a state S0, such as state S1a or state S2a or state Sna, to the absence of a state S0.

[0230] States S1a to Sna and the absence of a state are the states of the parameters of the RF signal 712. For example, each of the states S1a to Sna and the absence of a state described with reference to FIG. 7 represents the parameter level of the RF signal 712. By way of illustration, state S1a of the RF signal 712 identifies the first parameter level of the RF signal 712, and state S2a of the RF signal 712 identifies the second parameter level of the RF signal 712.

[0231] In one embodiment, instead of parameter controllers PRS1a to PRSna and frequency controller 210, one or more controllers such as one or more processors are used to perform the functions performed by parameter controllers PRS1a to PRSna and frequency controller 210 as described herein.

[0232] In one embodiment, instead of the DSP204, parameter controllers PRS1a to PRSna and frequency controller 210, one or more controllers such as one or more processors are used to perform the functions described herein that are performed by the DSP204, parameter controllers PRS1a to PRSna and frequency controller 210.

[0233] Figure 8 is a diagram of one embodiment of the plasma system 800, showing pulsed signals of multiple levels of frequency. The plasma system 800 includes an RF generator 802 and a host computer 106. The RF generator 802 is an example of a source RF generator 102 (Figure 1) or a bias RF generator 104 (Figure 1). The RF generator 802 includes a DSP 204 and a number of frequency controllers FCS1a, FCS2a, FCS3a...FCSna, where n is an integer of 4 or greater. For example, n is 4 or greater. As an example, the RF generator 802 includes four frequency controllers, one frequency controller in state S1a, another in state S2a, another in state S3a, and another in state S4a. As another example, the RF generator 802 includes five frequency controllers, one in state S1a, another in state S2a, another in state S3a, another in state S4a, and one in state S5a. The RF generator 802 further includes a parameter controller 814, a driver system 810, and an RF power supply 222.

[0234] DSP204 is coupled to each of the frequency controllers FCS1a to FCSna of RF generator 802. Frequency controllers FCS1a to FCSna are coupled to driver system 810, which is coupled to RF power supply 222. Parameter controller 814 is also coupled to driver system 810.

[0235] The processor 118 supplies the frequency, such as the frequency level for Sna, from state S1a, and the synchronization signal 146 to the DSP 204 via the transmission cable system 214. Upon receiving the frequency level for Sna from state S1a, the DSP 204 supplies the frequency, such as the frequency level of state S1a, of the RF signal 812 to the frequency controller FCS 1a, and stores the frequency of state S1a in the memory device of the frequency controller FCS 1a. RF signal 812 is an example of RF signal 152 or RF signal 168 (Figure 1).

[0236] Furthermore, upon receiving the frequency level for Sna from state S1a, the DSP204 supplies the frequency level of state S2a of the RF signal 812 to the frequency controller FCS2a and stores the frequency level of state S2a in the memory device of the frequency controller FCS2a. In addition, upon receiving the frequency level for Sna from state S1a, the DSP204 supplies the frequency level of state S3a of the RF signal 812 to the frequency controller FCS3a and stores the frequency level of state S3a in the memory device of the frequency controller FCS3a. In addition, upon receiving the frequency level for Sna from state S1a, the DSP204 supplies the frequency level of state Sna of the RF signal 812 to the frequency controller FCSna and stores the frequency level of state Sna in the memory device of the frequency controller FCSna. Similarly, upon receiving parameter levels such as a single parameter level for all of Sna from state S1a, the DSP204 supplies the parameter levels to the parameter controller 814 and stores them in the memory device of the parameter controller 814.

[0237] In one embodiment, the value of the (n-1)th frequency level is different from the value of the nth frequency level. For example, the value of the (n-1)th frequency level is excluding the value of the nth frequency level. As another example, none of the values ​​of the (n-1)th frequency levels are the same as any of the values ​​of the nth frequency level.

[0238] Upon receiving the synchronization signal 146, the DSP 204 transmits a command signal for state S1a to the frequency controller FCS 1a during each cycle of the synchronization signal 146. For example, the DSP 204 transmits a command signal for state S1a to the frequency controller FCS 1a when transitioning to state S1a from a state different from or other than state S1a, such as state S2a, state S0, or state S3a. The command signal for state S1a transmitted to the frequency controller FCS 1a includes the time period of state S1a during each cycle, and the frequency controller FCS 1a supplies the frequency level of state S1a to the driver system 810. Upon receiving the command signal for state S1a, the frequency controller FCS 1a accesses the parameter level of state S1a from its memory device and transmits the frequency level for the time period of state S1a to the driver system 810. For example, when the frequency controller FCS1a transitions from a different state to state S1a, it transmits the frequency level of state S1a to the driver system 810. After the time period of state S1a, for the duration of the synchronization signal 146, the frequency controller FCS1a does not transmit the frequency level of state S1a to the driver system 810.

[0239] Similarly, upon receiving the synchronization signal 146, the DSP 204 transmits a command signal for state S2a to the frequency controller FCS 2a during each cycle of the synchronization signal 146. For example, the DSP 204 transmits a command signal for state S2a to the frequency controller FCS 2a when transitioning to state S2a from a state different from or other than state S2a, such as state S1a, state S0, or state S3a. The command signal for state S2a transmitted to the frequency controller FCS 2a includes the time period of state S2a during each cycle, and the frequency controller FCS 2a supplies the frequency level of state S2a to the driver system 810. Upon receiving the command signal for state S2a, the frequency controller FCS 2a accesses the parameter level of state S2a from its memory device and transmits the frequency level for the time period of state S2a to the driver system 810. For example, when the frequency controller FCS2a transitions from a different state to state S2a, it transmits the frequency level of state S2a to the driver system 810. After the time period of state S2a, for the duration of the synchronization signal 146, the frequency controller FCS2a does not transmit the frequency level of state S2a to the driver system 810.

[0240] Furthermore, upon receiving the synchronization signal 146, the DSP 204 transmits a command signal for state S3a to the frequency controller FCS 3a during each cycle of the synchronization signal 146. For example, the DSP 204 transmits a command signal for state S3a to the frequency controller FCS 3a when transitioning to state S3a from a state different from or other than state S3a, such as state S2a, state S1a, or state S0. The command signal for state S3a transmitted to the frequency controller FCS 3a includes the time period of state S3a during each cycle, and the frequency controller FCS 3a supplies the frequency level of state S3a to the driver system 810. Upon receiving the command signal for state S3a, the frequency controller FCS 3a accesses the parameter level of state S3a from its memory device and transmits the frequency level for the time period of state S3a to the driver system 810. For example, when the frequency controller FCS3a transitions from a different state to state S3a, it transmits the frequency level of state S3a to the driver system 810. After the time period of state S3a, for the duration of the synchronization signal 146, the frequency controller FCS3a does not transmit the frequency level of state S3a to the driver system 810.

[0241] Furthermore, upon receiving the synchronization signal 146, the DSP 204 transmits a command signal for state Sna to the frequency controller FCSna during each cycle of the synchronization signal 146. For example, the DSP 204 transmits a command signal for state Sna to the frequency controller FCSna when transitioning to state Sna from a state different from state Sna, such as state S(n-1)a or state S0, or from a state other than state Sna. The command signal for state Sna transmitted to the frequency controller FCSna includes the time period of state Sna during each cycle, and the frequency controller FCSna supplies the frequency level of state Sna to the driver system 810. Upon receiving the command signal for state Sna, the frequency controller FCSna accesses the parameter level of state Sna from its memory device and transmits the frequency level related to the time period of state Sna to the driver system 810. For example, when the frequency controller FCSna transitions to state Sna from a state different from or other than state Sn, it transmits the frequency level of state Sna to the driver system 810. After the time period of state Sna, for the duration of the synchronization signal 146, the frequency controller FCSna does not transmit the frequency level of state Sna to the driver system 810.

[0242] Furthermore, upon receiving the synchronization signal 146, the DSP 204 transmits an instruction signal to the parameter controller 814 during each cycle of the synchronization signal 146. Upon receiving the instruction signal, the parameter controller 814 accesses the parameter level from its memory device and transmits the parameter level to the driver system 810.

[0243] In response to receiving the frequency level and parameter level of state S1a, the driver system 810 generates a drive signal for state S1a for the duration of state S1a and transmits the drive signal to the RF power supply 222. For example, when transitioning to state S1a from a state different from or other than state S1a, such as state S2a, state S3a, state Sna, or state S0, upon receiving the frequency level and parameter level of state S1a, the driver system 810 generates a drive signal for state S1a for the duration of state S1a and transmits the drive signal to the RF power supply 222. When the RF power supply 222 receives the drive signal for state S1a from the driver system 810, it generates state S1a for the RF signal 812. For example, upon receiving the drive signal for state S1a from the driver system 810, the RF power supply 222 transitions the RF signal 812 from a state different from state S1a to state S1a. The RF signal 812 has a frequency level and parameter level of state S1a for the duration of the state S1a.

[0244] Similarly, upon receiving the frequency level and parameter level of state S2a, the driver system 810 generates a drive signal for state S2a for the duration of state S2a and transmits the drive signal to the RF power supply 222. For example, when transitioning to state S2a from a state different from or other than state S2a, such as state S1a, state S0, or state S3a, upon receiving the frequency level and parameter level of state S2a, the driver system 810 generates a drive signal for state S2a for the duration of state S2a and transmits the drive signal to the RF power supply 222. When the RF power supply 222 receives the drive signal for state S2a from the driver system 810, it generates state S2a for the RF signal 812. For example, upon receiving the drive signal for state S2a from the driver system 810, the RF power supply 222 transitions the RF signal 812 from a state different from state S2a to state S2a. The RF signal 712 has a frequency level and parameter level of state S2a for the duration of the state S2a.

[0245] Furthermore, in response to the reception of the frequency level and parameter level of state S3a, the driver system 810 generates a drive signal for state S3a during the time period of state S3a and transmits the drive signal to the RF power supply 222. For example, when transitioning to state S3a from a state different from or other than state S3a, such as state S2a, state S0, state S1a, or state S4a, the driver system 810 receives the frequency level and parameter level of state S3a, generates a drive signal for state S3a during the time period of state S3a, and transmits the drive signal to the RF power supply 222. When the RF power supply 222 receives the drive signal for state S3a from the driver system 810, it generates state S3a for the RF signal 812. For example, when the RF power supply 222 receives the drive signal for state S3a from the driver system 810, it causes the RF signal 812 to transition from a state different from state S3a to state S3a. The RF signal 812 has a frequency level and parameter level of state S3a for the duration of the state S3a.

[0246] Furthermore, upon receiving the frequency level and parameter level of state Sna, the driver system 810 generates a drive signal for state Sna during the time period of state Sna and transmits the drive signal to the RF power supply 222. For example, when transitioning to state Sna from a state different from or other than state Sna, such as state S(n-1)a or state S0, upon receiving the frequency level and parameter level of state Sna, the driver system 810 generates a drive signal for state Sna during the time period of state Sna and transmits the drive signal to the RF power supply 222. When the RF power supply 222 receives the drive signal for state Sna from the driver system 810, it generates state Sna for RF signal 812. For example, upon receiving the drive signal for state Sna from the driver system 810, the RF power supply 222 transitions RF signal 812 from a state different from state Sna to state Sna. State Sna of RF signal 812 has the frequency level and parameter level of state Sna for the time period of state Sna.

[0247] In one embodiment, there is a period of time during each cycle of the synchronization signal 146 in which the RF signal 812 has a frequency level of zero. The RF signal 812 has a frequency level of zero when there is no state, such as state S0. Upon receiving the synchronization signal 146, during each cycle of the synchronization signal 146, the DSP 204 does not transmit command signals from state S1a to Sna from the frequency controller FCS1a to FCSna and the parameter controller 814 during the period of no state.

[0248] During the time period between states S1a and Sna when no command signal is received, the frequency controller FCS1a to FCSna does not transmit or stops transmitting the frequency level of state S1a to Sna to the driver system 810, and the parameter controller 814 stops transmitting the parameter level to the driver system 810. For example, after the time period of state S1a, the frequency controller FCS1a does not transmit the frequency level of state S1a to the driver system 810. As another example, after the time period of state S2a, the frequency controller FCS2a does not transmit the frequency level of state S2a to the driver system 810.

[0249] If the driver system 810 does not receive the frequency level and parameter level of Sna from state S1a, it does not transmit a drive signal to the RF power supply 222. If the drive signal is not received during a stateless period, the RF power supply 810 generates an RF signal 812 with a parameter level of zero during the stateless period. For example, if the drive signal is not received, the power supply 222 transitions the RF signal 812 from a state different from or other than stateless S0, such as state S1a, state S2a, or state Sna, to stateless S0.

[0250] The states S1a through Sna and no state represent the frequency states of the RF signal 812. For example, each state S1a through Sna and no state, as described with reference to Figure 8, represents the frequency level of the RF signal 812. For example, state S1 of the RF signal 812 identifies the first frequency level of the RF signal 812, and state S2 of the RF signal 812 identifies the second frequency level of the RF signal 812.

[0251] In one embodiment, instead of frequency controllers FCS1a to FCSna and parameter controller 814, one or more controllers such as one or more processors are used to perform the functions performed by frequency controllers FCS1a to FCSna and parameter controller 814 as described herein.

[0252] In one embodiment, instead of the DSP204, frequency controllers FCS1a to FCSna and parameter controller 814, one or more controllers such as one or more processors are used to perform the functions described herein that are performed by the DSP204, frequency controllers FCS1a to FCSna and parameter controller 814.

[0253] Figure 9 is a diagram of one embodiment of the plasma system 900, showing simultaneous multi-level parameter pulsation and multi-level frequency pulsation. The plasma system 900 includes an RF generator 902 and a host computer 106. The RF generator 902 is an example of a source RF generator 102 (Figure 1) or a bias RF generator 104 (Figure 1). The RF generator 902 includes a DSP 204, frequency controllers FCS1a to FCSna, and parameter controllers PRS1a to PRSna. The RF generator 902 further includes a driver system 910 and an RF power supply 222.

[0254] DSP204 is coupled to each of the frequency controllers FCS1a to FCSna and parameter controllers PRS1a to PRSna of RF generator 902. The frequency controllers FCS1a to FCSna and power controllers PRS1 to PRSna are coupled to driver system 910, which is coupled to RF power supply 222.

[0255] The processor 118 supplies the frequency level of state S1a to Sna, the parameter level of state S1a to Sna, and the synchronization signal 146 to the DSP 204 via the transmission cable system 214. As described above with reference to Figure 8, upon receiving the frequency level for state S1a to Sna, the DSP 204 supplies the frequency level of state S1a to Sna of RF signal 912 from the frequency controller FCS1a to FCSna, and stores the frequency level of state S1a to Sna in the memory device of the frequency controller FCS1a to FCSna. RF signal 912 is an example of RF signal 152 or RF signal 168 (Figure 1). Similarly, as described above with reference to Figure 7, in response to the reception of the parameter levels for state S1a to Sna, the DSP204 supplies the parameter levels for state S1a to Sna of the RF signal 912 to the parameter controller PRS1a to PRSna, and stores the parameter levels for state S1a to Sna in the memory device of the parameter controller PRS1a to PRSna.

[0256] Upon receiving the synchronization signal 146, as described above with reference to Figure 8, the DSP 204 transmits a command signal from state S1a to Sna from the frequency controller FCS1a to FCSna during each cycle of the synchronization signal 146. Furthermore, upon receiving the synchronization signal 146, as described above with reference to Figure 7, the DSP 204 transmits a command signal from state S1a to Sna from the parameter controller PRS1a to PRSna during each cycle of the synchronization signal 146.

[0257] As described above with reference to Figure 8, upon receiving the command signal for state S1a to Sna, the frequency controller FCS1a to FCSna accesses the frequency level for state S1a to Sna from the memory device of the frequency controller FCS1a to FCSna and transmits the frequency level for the time period of state S1a to Sna to the driver system 910. Similarly, as described above with reference to Figure 7, upon receiving the command signal for state S1a to Sna, the parameter controller PRS1a to PRSna accesses the parameter level for state S1a to Sna from the memory device of the parameter controller PRS1a to PRSna and transmits the parameter level for the time period of state S1a to Sna to the driver system 910.

[0258] As described above with reference to Figures 7 and 8, in response to the reception of the frequency level of state S1a to Sna and the parameter level of state S1a to Sna, the driver system 810 generates drive signals for the frequency level of state S1a to Sna and the parameter level of state S1a to Sna, and transmits the drive signals to the RF power supply 222. For example, when transitioning to state Sna from a state different from or other than state Sna, such as state S(n-1)a or state S0, the driver system 910 receives the frequency level and parameter level of state Sna, generates drive signals for the frequency level of state Sna and the parameter level of state Sna for the duration of state Sna, and transmits the drive signals to the RF power supply 222. When the RF power supply 222 receives the drive signals for the frequency level and parameter level of state Sna from the driver system 910, it generates the frequency level of state Sna and the parameter level of state Sna of the RF signal 912. For example, when the RF power supply 222 receives a drive signal for the frequency level state Sna from the driver system 910, it transitions the frequency level of the RF signal 912 from a state different from state Sna or a state other than state Sna to state Sna. The state Sna of the RF signal 912 has the frequency level of state Sna. When the RF power supply 222 receives a drive signal for the parameter level state Sna from the driver system 910, it transitions the parameter level of the RF signal 912 from a state different from state Sna to state Sna. The state Sna of the RF signal 912 has the parameter level of state Sna.

[0259] In one embodiment, during each cycle of the synchronization signal 146, there is a period of time during which the RF signal 912 has a frequency level of zero and a parameter level of zero. The RF signal 912 has a frequency level of zero and a parameter level of zero during periods of no state, such as state S0. Upon receiving the synchronization signal 146, during each cycle of the synchronization signal 146, the DSP 204 does not transmit a command signal from state S1a to Sna from the frequency controller FCS1a to FCSna, nor does it transmit a command signal from state S1a to Sna from the parameter controller PRS1a to PRSna, during periods of no state.

[0260] As described above with reference to Figure 8, during the time period between the frequency level state S1a and the state in which no command signal is received for Sna, the frequency controllers FCS1a to FCSna do not transmit or stop transmitting the frequency level of state S1a to Sna to the driver system 910. Similarly, as described above with reference to Figure 7, during the time period between the parameter level state S1a and the state in which no command signal is received for Sna, the parameter controllers PRS1a to PRSna do not transmit or stop transmitting the parameter level of state S1a to Sna to the driver system 910.

[0261] If the driver system 910 does not receive the frequency level of state S1a to Sna and the parameter level of state S1a to Sna, it does not transmit a drive signal to the RF power supply 222. If the drive signal is not received during a period of no state, the RF power supply 222 generates an RF signal 912 with zero parameter level and zero frequency level during the period of no state. For example, if the drive signal is not received, the power supply 222 transitions the RF signal 912 from a state different from or other than no state S0, such as the frequency level state S1a, frequency level state S2a, or frequency level state Sna, to the frequency level no state S0. Similarly, if the drive signal is not received, the power supply 222 transitions the RF signal 912 from a state different from or other than no state S0, such as the parameter level state S1a, parameter level state S2a, or parameter level state Sna, to the parameter level no state S0.

[0262] In one embodiment, instead of frequency controllers FCS1a to FCSna and parameter controllers PRS1a to PRSna, one or more controllers such as one or more processors are used to perform the functions described herein that are performed by frequency controllers FCS1a to FCSna and parameter controllers PRS1a to PRSna.

[0263] In one embodiment, instead of the DSP204, frequency controllers FCS1a to FCSna, and parameter controllers PRS1a to PRSna, one or more controllers such as one or more processors are used to perform the functions described herein that are performed by the DSP204, frequency controllers FCS1a to FCSna, and parameter controllers PRS1a to PRSna.

[0264] In one embodiment, if the RF signal 152 (Figure 1) generated by the source RF generator has multiple variable levels, such as four variable levels, the bias RF generator 104 generates an RF signal 168 which is a continuous wave signal, and the RF signal 168 has a single variable level of the RF signal 152, or a different number of variable levels, such as two, three, eight, or ten. In another example, if the RF signal 168 (Figure 1) generated by the bias RF generator has multiple variable levels, such as four variable levels, the source RF generator 102 generates an RF signal 152 which is a continuous wave signal, and the RF signal 152 has a single variable level of the RF signal 168, or a different number of variable levels, such as two, three, eight, or ten.

[0265] In one embodiment, RF signals 152 and 168 have the same number of variable levels, such as six or eight variable levels.

[0266] Figure 10A is a graph 300 of one embodiment showing the synchronization signal 302.

[0267] Figure 10B is a graph 1004 of one embodiment, showing the variable 1006 versus time t of the RF signal 912 (Figure 9). The variable 1006 is graphed on the y-axis, and time t is graphed on the x-axis.

[0268] Variable 1006 periodically transitions between variable levels V8a, 0, V6a, and V2a in synchronization with the synchronization signal 302. For example, during cycle 1 of the synchronization signal 302, variable 1006 transitions between variable levels V8a, 0, V6a, and V2a, and similarly during cycle 2 of the synchronization signal 302, it transitions between variable levels V8a, 0, V6a, and V2a. To illustrate, variable 1006 has variable level V8a during state S4a from time t0 to time t2.5, has a variable level of zero during no state from time t2.5 to time t5, has variable level V6a during state S3a from time t5 to time t7.5, and has variable level V2a during state S1a from time t7.5 to time t10. Time t2.5 occurs between times t2 and t3. Similarly, time t7.5 occurs between times t7 and t8. During cycle 1 of the synchronization signal 302, variable 1006 transitions from variable level V2a to variable level V8a at time t0, from variable level V8a to the zero variable level at time t2.5, from the zero variable level to variable level V6a at time t5, and from variable level V6a to variable level V2a at time t7.5. During cycle 2 of the synchronization signal 302, variable 1006 again transitions from variable level V2a to variable level V8a at time t10, from variable level V8a to the zero variable level at time t12.5, from the zero variable level to variable level V6a at time t15, and from variable level V6a to variable level 2a at time t17.5. Time t12.5 occurs between times t12 and t13. Similarly, time t17.5 occurs between times t17 and t18. Variable level V8a is the variable level for state S4a of RF signal 912, a variable level of zero is an example of the variable level for state 0 of RF signal 912, variable level V6a is an example of the variable level for state S3a of RF signal 912, and variable level V2a is an example of the variable level for state S1a of RF signal 912.

[0269] Variable level V2a is greater than variable level 0. Also, variable level V6a is greater than variable level V2a, and variable level V8a is greater than variable level V6a. For example, the power value of variable level V6a is less than the power value of variable level V8a. As another example, none of the power values ​​of variable level V6a exceed the power value of variable level V8a. As yet another example, a variable level has a maximum and a minimum value. The maximum value is the largest of all values ​​of the variable level, and the minimum value is the smallest of all values ​​of the variable level. A first variable level is smaller than the second variable level if the maximum value of the first variable level is smaller than the minimum value of the second variable level, and a first variable level is larger than the second variable level if the minimum value of the first variable level is greater than the maximum value of the second variable level.

[0270] In one embodiment, instead of achieving variable level V2a, variable 1006 has a variable level of zero. For example, variable 1006 has a variable level of zero from time t7.5 to time t10 and from time t17.5 to time t20.

[0271] In one embodiment, the transition time, which is the transition time between two variable levels, is the time period between the transition start time and the transition end time. For example, instead of transitioning from variable level V8a to the variable level of zero at time t2.5, variable 1006 starts the transition from variable level V8a at a first time and finishes the transition to the variable level of zero at a second time. The first time is before time t2.5, between times t1 and t2.5, and the second time is after time t2.5, between times t2.5 and t4. The transition time period is the transition time between the first time and the second time.

[0272] In one embodiment, in addition to the synchronization signal 302, a digital pulse signal is received by the DSP 204 from the processor 118 via the transmission cable system 214. For example, the synchronization signal 302 is received via the first transmission cable of the transmission cable system 214, and the digital pulse signal is received via the second transmission cable of the transmission cable system 214. The digital pulse signal transitions periodically between four variable levels, and parameter 1006 transitions between variable levels V8a and zero, V6a and V2a. For example, during cycle 1 of the synchronization signal 302, the digital pulse signal transitions from logic level 1 to logic level 3 at time t0, from logic level 3 to logic level 0 at time t2.5, from logic level 0 to logic level 2 at time t5, and from logic level 2 to logic level 1 at time t7.5. Logic level 3 is greater than logic level 2. For example, logic level 3 has a DC voltage greater than the DC voltage of logic level 2. Upon receiving a digital pulse signal, the DSP204 identifies the time periods S4a, no state, S3a, and S1a of variable 1006 from the digital pulse signal and generates an instruction signal having these time periods. For example, the time period of state S4a of variable 1006 is the same as the time period of logic level 3 of the digital pulse signal, the time period of state S0 of variable 1006 is the same as the time period of logic level 0 of the digital pulse signal, the time period of state S3a of variable 1006 is the same as the time period of logic level 2 of the digital pulse signal, and the time period of state S1a of variable 1006 is the same as the time period of logic level 1 of the digital pulse signal.

[0273] Figure 10C is a graph 1008 of one embodiment, showing the variable 1010 versus time t of the RF signal 912 (Figure 9). The variable 1010 is graphed on the y-axis, and time t is graphed on the x-axis.

[0274] Variable 1010 periodically transitions between variable levels V8a, V6a, V4a, and V2a in synchronization with the synchronization signal 302. For example, during cycle 1 of the synchronization signal 302, variable 1010 transitions between variable levels V8a, V6a, V4a, and V2a, and similarly during cycle 2 of the synchronization signal 302, it transitions between variable levels V8a, V6a, V4a, and V2a. For example, variable 1010 has variable level V8a during state S4a from time t0 to time t2.5, variable level V6a during state S3a from time t2.5 to time t5, variable level V4a during state S2a from time t5 to time t7.5, and variable level V2a during state S1a from time t7.5 to time t10. During cycle 1 of the synchronization signal 302, variable 1010 transitions from variable level V2a to variable level V8a at time t0, from variable level V8a to variable level V6a at time t2.5, from variable level V6a to variable level V4a at time t5, and from variable level V4a to variable level V2a at time t7.5. During cycle 2 of the synchronization signal 302, variable 1010 again transitions from variable level V2a to variable level V8a at time t10, from variable level V8a to variable level V6a at time t12.5, from variable level V6a to variable level V4a at time t15, and from variable level V4a to variable level V2a at time t17.5. Variable level V4a is an example of the variable level of state S2a of the RF signal 912.

[0275] Variable level V4a is greater than variable level V2a and less than variable level V6a. For example, the power value of variable level V4a is less than the power value of variable level V6a and greater than the power value of variable level V2a. Another example is that none of the power values ​​of variable level V4a are greater than the power values ​​of variable level V6a, and none of the power values ​​of variable level V2a are greater than the power values ​​of variable level V4a.

[0276] In one embodiment, instead of achieving variable level V2a, variable 1010 has a variable level of zero. For example, variable 1010 has a variable level of zero from time t7.5 to time t10 and from time t17.5 to time t20.

[0277] Figure 10D is a graph 1012 of one embodiment, showing the variable 1014 versus time t of the RF signal 912 (Figure 9). The variable 1014 is graphed on the y-axis, and time t is graphed on the x-axis.

[0278] Variable 1014 periodically transitions between variable levels V8a, V2a, V6a, and zero while synchronized with the synchronization signal 302. For example, during cycle 1 of the synchronization signal 302, variable 1014 transitions between variable levels V8a, V2a, V6a, and zero, and similarly during cycle 2 of the synchronization signal 302, it transitions between variable levels V8a, V2a, V6a, and zero. To illustrate, variable 1014 has variable level V8a during state S4a from time t0 to time t2.5, variable level V2a during state S1a from time t2.5 to time t5, variable level V6a during state S3a from time t5 to time t7.5, and variable level zero during state S0 from time t7.5 to time t10. During cycle 1 of the synchronization signal 302, variable 1014 transitions from a variable level of zero to variable level V8a at time t0, from variable level V8a to variable level V2a at time t2.5, from variable level V2a to variable level V6a at time t5, and from variable level V6a to a variable level of zero at time t7.5. During cycle 2 of the synchronization signal 302, variable 1014 again transitions from a variable level of zero to variable level V8a at time t10, from variable level V8a to variable level V2a at time t12.5, from variable level V2a to variable level V6a at time t15, and from variable level V6a to a variable level of zero at time t17.5.

[0279] Figure 10E is a graph 1016 of one embodiment, showing the variable 1018 versus time t of the RF signal 912 (Figure 9). The variable 1018 is graphed on the y-axis, and time t is graphed on the x-axis.

[0280] Variable 1018 periodically transitions between variable levels V8a, V6a, V2a, and V4a while synchronized with the synchronization signal 302. For example, during cycle 1 of the synchronization signal 302, variable 1018 transitions between variable levels V8a, V6a, V2a, and V4a, and similarly during cycle 2 of the synchronization signal 302, it transitions between variable levels V8a, V6a, V2a, and V4a. To illustrate, variable 1018 has variable level V8a while in state S4a from time t0 to time t2.5, variable level V6a while in state S3a from time t2.5 to time t5, variable level V2a while in state S1a from time t5 to time t7.5, and variable level V4a while in state S2a from time t7.5 to time t10. During cycle 1 of the synchronization signal 302, variable 1018 transitions from variable level V4a to variable level V8a at time t0, from variable level V8a to variable level V6a at time t2.5, from variable level V6a to variable level V2a at time t5, and from variable level V2a to variable level V4a at time t7.5. During cycle 2 of the synchronization signal 302, variable 1018 again transitions from variable level V4a to variable level V8a at time t10, from variable level V8a to variable level V6a at time t12.5, from variable level V6a to variable level V2a at time t15, and from variable level V2a to variable level V4a at time t17.5.

[0281] In one embodiment, instead of achieving variable level V2a, variable 1018 has a variable level of zero. For example, variable 1018 has a variable level of zero from time t5 to time t7.5 and from time t15 to time t17.5.

[0282] Figure 10F is a graph 1020 of one embodiment, showing the variable 1022 versus time t of the RF signal 912 (Figure 9). The variable 1022 is graphed on the y-axis, and time t is graphed on the x-axis.

[0283] Variable 1022 periodically transitions between variable levels V6a, V8a, V4a, and V2a while synchronized with the synchronization signal 302. For example, during cycle 1 of the synchronization signal 302, variable 1022 transitions between variable levels V6a, V8a, V4a, and V2a, and similarly during cycle 2 of the synchronization signal 302, it transitions between variable levels V6a, V8a, V4a, and V2a. To illustrate, variable 1022 has variable level V6a while in state S3a from time t0 to time t2.5, variable level V8a while in state S4a from time t2.5 to time t5, variable level V4a while in state S2a from time t5 to time t7.5, and variable level V2a while in state S1a from time t7.5 to time t10. During cycle 1 of the synchronization signal 302, variable 1020 transitions from variable level V2a to variable level V6a at time t0, from variable level V6a to variable level V8a at time t2.5, from variable level V8a to variable level V4a at time t5, and from variable level V4a to variable level V2a at time t7.5. During cycle 2 of the synchronization signal 302, variable 1018 also transitions from variable level V2a to variable level V6a at time t10, from variable level V6a to variable level V8a at time t12.5, from variable level V8a to variable level V4a at time t15, and from variable level V4a to variable level V2a at time t17.5.

[0284] Figure 10G is a graph 1024 of one embodiment, showing the variable 1026 versus time t of the RF signal 912 (Figure 9). The variable 1026 is graphed on the y-axis, and time t is graphed on the x-axis.

[0285] Variable 1026 periodically transitions between variable levels V4a, V6a, V8a, and V2a while synchronized with the synchronization signal 302. For example, during cycle 1 of the synchronization signal 302, variable 1026 transitions between variable levels V4a, V6a, V8a, and V2a, and similarly during cycle 2 of the synchronization signal 302, it transitions between variable levels V4a, V6a, V8a, and V2a. To illustrate, variable 1024 has variable level V4a while in state S2a from time t0 to time t2.5, variable level V6a while in state S3a from time t2.5 to time t5, variable level V8a while in state S4a from time t5 to time t7.5, and variable level V2a while in state S1a from time t7.5 to time t10. During cycle 1 of the synchronization signal 302, variable 1026 transitions from variable level V2a to variable level V4a at time t0, from variable level V4a to variable level V6a at time t2.5, from variable level V6a to variable level V8a at time t5, and from variable level V8a to variable level V2a at time t7.5. During cycle 2 of the synchronization signal 302, variable 1026 again transitions from variable level V2a to variable level V4a at time t10, from variable level V4a to variable level V6a at time t12.5, from variable level V6a to variable level V8a at time t15, and from variable level V8a to variable level V2a at time t17.5.

[0286] In one embodiment, instead of achieving variable level V2a, variable 1026 has a variable level of zero. For example, variable 1026 has a variable level of zero from time t7.5 to time t10 and from time t17.5 to time t20.

[0287] Figure 10H is a graph 1028 of one embodiment, showing the variable 1030 versus time t of the RF signal 912 (Figure 9). The variable 1030 is graphed on the y-axis, and time t is graphed on the x-axis.

[0288] Variable 1030 periodically transitions between variable levels V8a, V6a, V4a, V2a, and zero while synchronized with the synchronization signal 302. For example, during cycle 1 of the synchronization signal 302, variable 1030 transitions between variable levels V8a, V6a, V4a, V2a, and zero, and similarly during cycle 2 of the synchronization signal 302, it transitions between variable levels V8a, V6a, V4a, V2a, and zero. To illustrate, variable 1030 has variable level V8a while in state S4a from time t0 to time t2, variable level V6a while in state S3a from time t2 to time t4, variable level V4a while in state S2a from time t4 to time t6, variable level V2a while in state S1a from time t6 to time t8, and variable level 0 while in no state from time t8 to time t10. During cycle 1 of the synchronization signal 302, variable 1030 transitions from a zero variable level to variable level V8a at time t0, from variable level V8a to variable level V6a at time t2, from variable level V6a to variable level V4a at time t4, from variable level V4a to variable level V2a at time t6, and from variable level V2a to a zero variable level at time t8. During cycle 2 of the synchronization signal 302, variable 1030 again transitions from a zero variable level to variable level V8a at time t10, from variable level V8a to variable level V6a at time t12, from variable level V6a to variable level V4a at time t14, from variable level V4a to variable level V2a at time t16, and from variable level V2a to a zero variable level at time t18.

[0289] In one embodiment, a stepwise decreasing change in the variable level is shown in Graph 1028, but it should be noted that a stepwise increasing change in the variable level may also occur. For example, during each cycle of the synchronization signal, the variable of the RF signal 912 can increase from zero to variable level V2a, from variable level V2a to variable level V4a, from variable level V4a to variable level V6a, and from variable level V6a to variable level V8a.

[0290] Figure 10I is a graph 1032 of one embodiment, showing the variable 1034 versus time t of the RF signal 912 (Figure 9). The variable 1034 is graphed on the y-axis, and time t is graphed on the x-axis.

[0291] Variable 1034 periodically transitions between variable levels V8a, V16a, V14a, V12a, V10a, V8a, V6a, V4a, V2a, and zero, while synchronized with the synchronization signal 302. For example, during cycle 1 of the synchronization signal 302, variable 1034 transitions between variable levels V18a, V16a, V14a, V12a, V10a, V8a, V6a, V4a, V2a, and zero, and similarly during cycle 2 of the synchronization signal 302, it transitions between variable levels V18a, V16a, V14a, V12a, V10a, V8a, V6a, V4a, V2a, and zero. For example, variable 1034 has a variable level V18a from time t0 to time t1 while in state S9a, a variable level V16a from time t1 to time t2 while in state S8a, a variable level V14a from time t2 to time t3 while in state S7a, a variable level V12a from time t3 to time t4 while in state S6a, a variable level V10a from time t4 to time t5 while in state S5a, a variable level V8a from time t5 to time t6 while in state S4a, a variable level V6a from time t6 to time t7 while in state S3a, a variable level V4a from time t7 to time t8 while in state S2a, a variable level V2a from time t8 to time t9 while in state S1a, and a variable level of zero from time t9 to time t10 while in state S0. During cycle 1 of the synchronization signal 302, the variable 1034 transitions from a variable level of zero to variable level V18a at time t0, from variable level V18a to variable level V16a at time t1, from variable level V16a to variable level V14a at time t2, from variable level V14a to variable level V12a at time t3, from variable level V12a to variable level V10a at time t4, from variable level V10a to variable level V8a at time t5, from variable level V8a to variable level V6a at time t6, from variable level V6a to variable level V4a at time t7, from variable level V4a to variable level V2a at time t8, and from variable level V2a to a variable level of zero at time t9.During cycle 2 of the synchronization signal 302, variable 1030 transitions from a variable level of zero to variable level V18a at time t10, from variable level V18a to variable level V16a at time t11, from variable level V16a to variable level V14a at time t12, from variable level V14a to variable level V12a at time t13, from variable level V12a to variable level V10a at time t14, from variable level V10a to variable level V8a at time t15, from variable level V8a to variable level V6a at time t16, from variable level V6a to variable level V4a at time t17, and from variable level V4a to variable level V2a at time t18. At time t19, it transitions from variable level V2a to a variable level of zero.

[0292] Variable level V10a is greater than variable level V8a. Also, variable level V12a is greater than variable level V10a, and variable level V14a is greater than variable level V12a. Variable level V16a is greater than variable level V14a, and variable level V18a is greater than variable level V16a. For example, the power value of variable level V14a is less than the power value of variable level V16a. As another example, none of the power values ​​of variable level V14a exceed the power values ​​of variable level V16a.

[0293] In one embodiment, a stepwise decrease in the variable level is shown in graph 1032, but it should be noted that a stepwise increase in the variable level may also occur. For example, during each cycle of the synchronization signal, the variable of the RF signal 912 can increase from zero to variable level V2a, from variable level V2a to variable level V4a, from variable level V4a to variable level V6a, from variable level V6a to variable level V8a, from variable level V8a to variable level V10a, and so on up to variable level V18a.

[0294] FIG. 10J is a diagram of an embodiment in which an RF generator 1070 having a plurality of power controllers and a plurality of automatic frequency tuners (AFTs) is provided. The RF generator 1070 is an example of the source RF generator 102 or the bias RF generator 104 (FIG. 1). The system 1070 further includes a DSP 204 and an RF power supply 222. The DSP 204 is an example of a receiver. The power controller is the power controller PWR S(n-A) and another power controller PWR S(n-1) and includes them in the same way until the power controller PWR Sn is included. The AFT includes the automatic frequency tuner AFT S(n-A) and another automatic frequency tuner AFT S(n-1) and includes them in the same way until the automatic frequency tuner AFT Sn is included. The automatic frequency tuner used herein is also a frequency controller.

[0295] During state S(n - A), the automatic frequency tuner AFT S(n-A) either tunes the frequency of the RF signal 220 generated by the RF power supply 222, or the power controller PWR S(n-A) modifies the power of the RF signal 220, or modifies both the frequency and the power, where (n - A) is an integer smaller than the integer n and A is an integer. For example, when n is 4 or 5 or 10, (n - A) is 1. For example, during state S(n - A), the DSP 204 supplies a control signal to the automatic frequency tuner AFT S(n-A) indicating a logic level such as the voltage level of state S(n - A). When receiving the control signal from the DSP 204, the automatic frequency tuner AFT S(n-A) accesses the frequency level related to state S(n - A) from a database in the memory device of the automatic frequency tuner AFT S(n-A) . The automatic frequency tuner AFT S(n-A) supplies the frequency level related to state S(n - A) to the RF power supply 222. When receiving the frequency level related to state S(n - A), the RF power supply 222 generates an RF signal 220 having the frequency level during state S(n - A). Similarly, during state S(n - A), the DSP 204 supplies a control signal to the power controller PWR S(n-A)It supplies power to the power controller PWR, indicating the logic level of state S(nA). When the control signal is received from the DSP204, the power controller PWR S(n-A) is a power controller (PWR) S(n-A) From the database in the memory device, the power level PL for state S(nA) S(n-A) Access the power controller (PWR). S(n-A) This is the power level PL related to state S(nA). S(n-A) This is supplied to the RF power supply 222. Power level PL for state S(nA) S(n-A) Upon receiving, the RF power supply 222 switches the power level PL during state S(nA). S(n-A) It generates an RF signal 220 having the following properties.

[0296] Similarly, during state S(n-1), the automatic frequency tuner AFT S(n-1) This either tunes the frequency of the RF signal 220 generated by the RF power supply 222, or the power controller PWR S(n-1) This modifies the power of RF signal 220, or modifies both the frequency and power. Also, during state Sn, the automatic frequency tuner AFT Sn This either tunes the frequency of the RF signal 220 generated by the RF power supply 222, or the power controller PWR Sn This modifies the power of RF signal 220, or modifies both its frequency and power.

[0297] The RF signal 220 is supplied to the impedance matching circuit 216 via an output such as the RF output port of the RF generator 1070. The impedance matching circuit 216 generates a corrected signal based on the RF signal 220 and supplies the corrected RF signal to electrodes such as the TCP electrode or bottom electrode of the plasma chamber 112 (Figure 1). The bottom electrode is located inside the chuck of the plasma chamber 112. The electrode or plasma chamber 112 is an example of a load.

[0298] The RF signal 220 is generated when the DSP 204 receives a digital pulse signal having states S(nA) through Sn from the host controller or host computer 106 (Figure 1) or another processor in the controller, or from the Analog-Digital Voltage Control Interface (ADVCI). The digital pulse signal is received at the input of the DSP 204, such as the input port shown in Figure 10J. If the DSP 204 is located within the RF generator 1070, the digital pulse signal is received at the input port of the RF generator 1070. The digital pulse signal is an example of an input signal and is generated by another processor or ADVCI. Each duty cycle from the four states S(n-4) through Sn, including duration, is identified by the digital pulse signal. The four states occur during the clock cycle of a clock signal received at another input, such as another input port of the processor, as shown in Figure 10J. The clock signal is generated by another processor or ADVCI.

[0299] In one embodiment, a level such as a power level or frequency level includes one or more values ​​or quantities within a predetermined range. For example, a first power level has one or more power values ​​within a predetermined range, and a second power level having one or more values ​​within a predetermined range. The second power level excludes the first power level. For example, none of the power values ​​of the second power level are the same as the power values ​​of the first power level.

[0300] Figure 10K is a diagram of one embodiment showing an RF signal, where the RF signal is the power level PL of the RF signal. S(n-3) PL S(n-2) PL S(n-1) and PL Sn It has four states S(n-3), S(n-2), S(n-1), and Sn, which represent the following: Stepwise decrease occurs from state S(n-3) to state Sn. For example, the power level PL of the RF signal generated by an RF generator such as the source RF generator 102 or bias RF generator 104 (Figure 1) during state Sn. Sn PL is the power level of the RF signal during state S(n-1). S(n-1)It is lower than. Similarly, the power level PL of the RF signal during state S(n-1) S(n-1) PL is the power level of the RF signal during state S(n-2). S(n-2) Lower than the power level PL of the RF signal during state S(n-2). S(n-2) PL is the power level of the RF signal during state S(n-3). S(n-3) It is lower than that.

[0301] Figure 10L is a diagram of one embodiment showing another RF signal having four states S(n-3), S(n-2), S(n-1), and Sn. The RF signal shown in Figure 10L also shows that the RF signal during state S(n-1) is the power level PL during state S(n-2). S(n-2) Higher power levels PL S(n-1) It is a signal that decreases in stages, except that it has [a certain characteristic].

[0302] Figure 10M is a diagram of one embodiment showing another RF signal having four states S(n-3), S(n-2), S(n-1), and Sn. The RF signal shown in Figure 10M also shows that the RF signal between states Sn is the power level PL between states S(n-1). S(n-1) Higher power levels PL Sn It is a signal that decreases in stages, except that it has [a certain characteristic].

[0303] Figure 10N is a diagram of another embodiment showing an RF signal having four states S(n-3), S(n-2), S(n-1), and Sn. The RF signal shown in Figure 14D is such that the RF signal during state S(n-2) is the power level PL during state S(n-3). S(n-3) Higher power levels PL S(n-2) It is a signal that decreases in stages, except that it has [a certain characteristic].

[0304] Figure 10O is a diagram of one embodiment showing yet another RF signal having four states S(n-3), S(n-2), S(n-1) and Sn. The RF signal has a power level PL between states S(n-3) and S(n-1). S(n-3) From PL S(n-1) The power level is gradually increased until the state Sn is reached, and the power level PL is increased from state S(n-1) during state Sn.S(n-1) Power level PL Sn It will be gradually reduced to that point.

[0305] During each clock cycle of the clock signal received by the RF generator processor shown in Figure 14A, the power level PL S(n-4) From PL Sn This process is repeated until the power level PL is reached. S(n-4) From PL Sn This is repeated. The clock signal is received from the clock source, or the host computer's processor, or the host controller, or the ADVCI. The clock signal is generated by the clock source, or the host computer's processor, or the host controller's processor, or the ADVCI. Similarly, the power level PL S(n-A) From PL Sn This repeats between states S(nA) and Sn during a clock cycle. The power level PL persists over multiple clock cycles. S(n-A) From PL Sn This process is repeated. Power level PL S(n-A) From PL Sn This occurs once during an instance of a clock cycle and repeats between each subsequent instance of the clock cycle.

[0306] Note that the RF signals shown in any of Figures 14B to 14F represent the envelope of the sinusoidal RF signal generated by the RF generator, either the source RF generator 102 or the bias RF generator 104 (Figure 1).

[0307] Figure 10P illustrates one embodiment of a method demonstrating that a zero power level is achieved during any of the states S(nA) through Sn. As shown in Figure 10P, the RF signal does not have a zero power level during state Sn, but rather the RF signal has a zero power level in another state such as S2 or S3.

[0308] In one embodiment, the embodiments described herein relating to power in Figures 10K to 10P are equally applicable to frequency. For example, instead of or in addition to multiple power levels, multiple frequency levels are achieved between states S(nA) and Sn.

[0309] It should be noted that in one embodiment, a zero power level is achieved when the power level is zero. In one embodiment, a zero power level is achieved when the RF power level is close to zero or substantially zero, such as within a preset range. An example of a preset range value is between 0.1 watts and 1 watt. Another example of a preset range value is between 0.1 watts and 0.25 watts. Yet another example of a preset range value is between 0.1 watts and 0.5 watts.

[0310] Transition control

[0311] Figure 11A is a diagram of one embodiment of the plasma system 1100, illustrating gradient control of state transitions. The plasma system 1100 includes an RF generator 1102 and a host computer 106. The RF generator 1102 is an example of a source RF generator 102 (Figure 1) or a bias RF generator 104 (Figure 1). The RF generator 1102 includes a DSP 204, parameter controllers PRS1a to PRSna, and a plurality of transition parameter controllers PRST1a, PRTS2a, PRST(n-1)a and PRSTna, where n is an integer of 4 or greater. For example, n is 4 or greater. As an example, RF generator 702 includes four transition parameter controllers: one for the state transition ST1a between parameter states S1a and S2a during the current cycle of the synchronization signal; another for the state transition ST2a between parameter states S2a and S3a during the current cycle of the synchronization signal; yet another for the state transition ST(n-1)a between parameter states S(n-1)a and Sna during the current cycle of the synchronization signal; and yet another for the state transition STna between parameter state Sna during the current cycle of the synchronization signal and parameter state S1a during the next cycle of the synchronization signal. The current cycle precedes the next cycle. For example, there is no cycle of the synchronization signal between the current cycle and the next cycle. As another example, RF generator 1102 includes five transition parameter controllers.

[0312] The RF generator 1102 further includes frequency controllers FCS1a to FCSna and a plurality of transition frequency controllers FCST1a, FCTS2a, FCST(n-1)a and FCSTna, where n is an integer of 4 or greater. For example, n is 4 or greater. As an example, the RF generator 1102 includes four transition frequency controllers, one for the state transition ST1 between frequency states S1a and S2a during the current cycle of the synchronization signal, another for the state transition ST2 between frequency states S2a and S3a during the current cycle of the synchronization signal, another for the state transition ST(n-1)a between frequency states S(n-1)a and Sna during the current cycle of the synchronization signal, and another for the state transition STna between frequency state Sna during the current cycle of the synchronization signal and frequency state S1a during the next cycle of the synchronization signal. As another example, the RF generator 1102 includes five transition frequency controllers. The RF generator 1102 further includes a driver system 1104 and an RF power supply 222.

[0313] DSP204 is coupled to each of the parameter controllers PRS1a to PRSna and each of the transition parameter controllers PRST1a to PRSTna of the RF generator 1102. The parameter controllers PRS1a to PRSna and the transition parameter controllers PRST1a to PRSTna are coupled to the driver system 1104, and the driver system 1104 is coupled to the RF power supply 222.

[0314] Furthermore, the DSP204 is coupled to each of the frequency controllers FCS1a to FCSna and each of the transition frequency controllers FCST1a to FCSTna of the RF generator 1102. The frequency controllers FCS1a to FCSna and the transition frequency controllers FCST1a to FCSTna are coupled to the driver system 1104. The functions of system 1110 are described below with reference to Figure 11B.

[0315] Figure 11B is a diagram of one embodiment of system 1100, illustrating the functions of system 1100. System 1100 includes an RF generator 1102 and a host computer 106. The RF generator 1102 includes a DSP 204, a parameter controller PRS(N±M)a, a transition parameter controller PRSTa, and a parameter controller PRSNa, where N is an integer greater than or equal to 1, and N±M is an integer different from N. For example, if N is 1, then N±M is 2, 3, or 4, and if N is 3, then N±M is 4, 2, or 1. The integers N±M define M, which is a positive integer. An example of a parameter controller PRSNa includes parameter controllers PRS1a, PRS2a, PRS3a, or PRSna (Figure 11A). Examples of parameter controllers PRS(N±M)a include parameter controllers PRS1a, PRS2a, PRS3a, or PRSna (Figure 11A), where parameter controller PRS(N±M) is different from parameter controller PRSNa. For example, if parameter controller PRSNa is PRS4a, then parameter controller PRS(N±M)a is PRS2a or PRS1a.

[0316] Examples of transition parameter controllers PRSTa include parameter controllers PRST1a, PRST2a, PRST3a, PRST(n-1), or PRSTna (Figure 11A). For example, if parameter controller PRSNa is parameter controller PRS1a and parameter controller PRS(N±M)a is parameter controller PRS2a, then transition parameter controller PRSTa is PRST1a, which controls the transition between parameter states S1a and S2a. As another example, if parameter controller PRSNa is parameter controller PRS3a and parameter controller PRS(N±M)a is parameter controller PRS5a, then transition parameter controller PRSTa is PRST3a, which controls the transition between parameter states S3a and S5a.

[0317] Note that the RF generator 1102 includes any number of transition parameter controllers, such as the transition parameter controller PRSTa. For example, if the parameters transition from the state S4a of the previous cycle to the state S1a of the current cycle, from the state S1a of the current cycle to the state S2a of the current cycle, from the state S2a of the current cycle to the state S3a of the current cycle, and from the state S3a of the current cycle to the state S4a of the current cycle, the RF generator 1102 includes four transition parameter controllers. The four transition parameter controllers include one transition parameter controller that controls the transition from the state S4a of the previous cycle to the state S1a of the current cycle, another transition parameter controller that controls the transition from the state S1a of the current cycle to the state S2a of the current cycle, yet another transition parameter controller that controls the transition from the state S2a of the current cycle to the state S3a of the current cycle, and yet another transition parameter controller that controls the transition from the state S3a of the current cycle to the state S4a of the current cycle. The previous cycle of synchronization signal 146 precedes the current cycle of synchronization signal 146.

[0318] The RF generator 1102 further includes a frequency controller FCS(N±M)a, a transition frequency controller FCSTa, and a frequency controller FCSNa, where M and N are defined above. An example of a frequency controller FCSNa includes a frequency controller FCS1a, FCS2a, FCS3a, or FCSna (Figure 11A). An example of a frequency controller FCS(N±M)a includes a frequency controller FCS1a, FCS2a, FCS3a, or FCSna (Figure 11A), where the frequency controller FCS(N±M) is different from the frequency controller FCSNa.

[0319] Examples of transition frequency controllers FCSTa include frequency controllers FCST1a, FCST2a, FCST3a, FCST(n-1), or FCSTna. For example, if frequency controller FCS1a is frequency controller FCS(N±M)a is frequency controller FCS2a, then transition frequency controller FCSTa is FCST1a, which controls the transition between frequency states S1a and S2a. As another example, if frequency controller FCS3a is frequency controller FCS5a, then transition frequency controller FCSTa is FCST3a, which controls the transition between frequency states S3a and S5a.

[0320] Note that the RF generator 1102 includes any number of transition frequency controllers, such as the transition frequency controller FCSTa. For example, if the frequency transitions from the state S4a of the previous cycle to the state S1a of the current cycle, from the state S1a of the current cycle to the state S2a of the current cycle, from the state S2a of the current cycle to the state S3a of the current cycle, and from the state S3a of the current cycle to the state S4a of the current cycle, then the RF generator 1102 includes four transition frequency controllers. The four transition frequency controllers include one transition frequency controller that controls the transition from the state S4a of the previous cycle to the state S1a of the current cycle, another transition frequency controller that controls the transition from the state S1a of the current cycle to the state S2a of the current cycle, yet another transition frequency controller that controls the transition from the state S2a of the current cycle to the state S3a of the current cycle, and yet another transition frequency controller that controls the transition from the state S3a of the current cycle to the state S4a of the current cycle.

[0321] DSP204 is coupled to parameter controllers PRS(N±M) and PRSNa and transition parameter controller PRSTa. DSP204 is also coupled to frequency controllers PRS(N±M) and FCSNa and transition frequency controller FCSTa. Parameter controllers PRS(N±M)a and PRSNa, transition parameter controller PRSTa, frequency controllers FCS(N±M)a and FCSNa, and transition frequency controller FCSTa are coupled to driver system 1104, which is coupled to RF power supply 222.

[0322] The processor 118 supplies the DSP 204 with parameter levels and synchronization signals 146 for states S(N±M) and SNa via the transmission cable system 214. Furthermore, the processor 118 supplies the DSP 204 with one or more parameter values ​​for the parameter state transition STa via the transmission cable system 214. For example, the processor 118 supplies one or more parameter values ​​to be achieved during the parameter state transition ST1a, one or more parameter values ​​to be achieved during the parameter state transition ST2a, one or more parameter values ​​to be achieved during the parameter state transition ST(n-1)a, and one or more parameter values ​​to be achieved during the parameter state transition STna.

[0323] A parameter state transition STa is a transition between the parameter states S(N±M) and SNa. For example, a parameter state transition STa is either a transition from parameter state S(N±M)a to parameter state SNa, or a transition from parameter state SNa to parameter state S(N±M)a.

[0324] Furthermore, the processor 118 supplies frequency levels for states S(N±M) and SNa to the DSP 204 via the transmission cable system 214. In addition, the processor 118 supplies frequency values ​​for frequency state transitions STa to the DSP 204 via the transmission cable system 214. For example, the processor 118 supplies one or more frequency values ​​to be achieved during frequency state transition ST1a, one or more frequency values ​​to be achieved during frequency state transition ST2a, one or more frequency values ​​to be achieved during frequency state transition ST(n-1)a, and one or more frequency values ​​to be achieved during frequency state transition STna.

[0325] A frequency state transition STa is a transition between frequency states S(N±M) and SNa. For example, a frequency state transition STa is either a transition from frequency state S(N±M)a to frequency state SNa, or a transition from frequency state SNa to frequency state S(N±M)a.

[0326] Upon receiving parameter levels for states S(N±M)a and SNa, the DSP204 supplies the parameter levels for state S(N±M)a of RF signal 1106 to the parameter controller PRS(N±M)a and stores the parameter levels for state S(N±M)a in the memory device of the parameter controller PRS(N±M)a. RF signal 1106 is an example of RF signal 152 or RF signal 168 (Figure 1). Also, upon receiving one or more parameter values ​​for the parameter transition state STa, the DSP204 supplies one or more parameter values ​​for the parameter transition state STa of RF signal 1106 to the transition parameter controller PRSTa and stores the parameter values ​​for the transition state STa in the memory device of the transition parameter controller PRSTa. An example of a parameter value during a state transition STa is the envelope of the RF signal 1106 parameter during the state transition STa, such as the amplitude from zero to peak or the amplitude from peak to peak. Furthermore, upon receiving the parameter level for SNa from state S(N±M)a, the DSP204 supplies the parameter level of state SNa of RF signal 1106 to the parameter controller PRSNa, and stores the parameter level of state SNa in the memory device of the parameter controller PRSNa.

[0327] Upon receiving the synchronization signal 146, the DSP 204 transmits a command signal for the parameter state S(N±M)a to the parameter controller PRS(N±M)a during each cycle of the synchronization signal 146. For example, at the end of the transition time from a state different from or other than state S(N±M)a, such as state S(N±M-1)a or state S0, to state S(N±M)a, the DSP 204 transmits a command signal for state S(N±M)a to the parameter controller PRS(N±M)a. The command signal for state S(N±M)a transmitted to the parameter controller PRS(N±M)a includes the time period of state S(N±M)a during each cycle, and the parameter controller PRS(N±M)a supplies the parameter level of state S(N±M)a to the driver system 1104. Upon receiving an instruction signal for state S(N±M)a, the parameter controller PRS(N±M)a accesses the parameter level for state S(N±M)a from its memory device and transmits the parameter level for the time period of state S(N±M)a to the driver system 1104. For example, at the end of the transition time from a different state to state S(N±M)a, the parameter controller PRS(N±M)a transmits the parameter level for state S(N±M)a to the driver system 1104. After the time period of state S(N±M)a, the parameter controller PRS(N±M)a does not transmit the parameter level for state S(N±M)a to the driver system 1104 during the cycle of the synchronization signal 146.

[0328] Similarly, upon receiving the synchronization signal 146, the DSP 204 transmits a command signal for state transition STa to the transition parameter controller PRSTa during each cycle of the synchronization signal 146. For example, the DSP 204 transmits a command signal for state transition STa to the transition parameter controller PRSTa at the start of the transition time from state S(N±M)a to state SNa, or at the start of the transition time from state S0 to state SNa. The command signal for state transition STa transmitted to the transition parameter controller PRSTa includes the time period of state transition STa during each cycle, and the transition parameter controller PRSTa supplies one or more parameter values ​​for state transition STa to the driver system 1104. Upon receiving the command signal for state transition STa, the transition parameter controller PRSTa accesses one or more parameter values ​​for state transition STa from its memory device and transmits one or more parameter values ​​to the driver system 1104 during the time period of state transition STa. For example, at the end of the state S(N±M)a time period, the transition parameter controller PRSTa transmits one or more parameter values ​​of the state transition STa to the driver system 1104. After the time period of the state transition STa, for the duration of the synchronization signal 146, the transition parameter controller PRSTa does not transmit one or more parameter levels of the state transition STa to the driver system 1104.

[0329] Upon receiving the synchronization signal 146, the DSP 204 transmits a command signal for state SNa to the parameter controller PRSNa during each cycle of the synchronization signal 146. For example, the DSP 204 transmits a command signal for state transition SNa to the parameter controller PRSNa at the end of the transition time from state S(N±M)a to state SNa. The command signal for state SNa transmitted to the parameter controller PRSna includes the time period of state Sna between each cycle, and the parameter controller PRSNa supplies the parameter level of state SNa to the driver system 1104. Upon receiving the command signal for state SNa, the parameter controller PRSNa accesses the parameter level of state SNa from the memory device of the parameter controller PRSna and transmits the parameter level to the driver system 1104 for the time period of state SNa. For example, the parameter controller PRSNa transmits the parameter level of state SNa to the driver system 1104 at the end of the transition time from state S(N±M)a to state SNa. After a period of time in state SNa, for the duration of the synchronization signal 146 cycle, the parameter controller PRSNa does not transmit the parameter level of state SNa to the driver system 1104.

[0330] Similarly, upon receiving frequency levels for states S(N±M)a and SNa, the DSP204 supplies the frequency level of state S(N±M)a of the RF signal 1106 frequency to the frequency controller FCS(N±M)a and stores the frequency level of state S(N±M)a in the memory device of the frequency controller FCS(N±M)a. Also, upon receiving one or more frequency values ​​of the frequency state transition STa, the DSP204 supplies one or more frequency values ​​of the frequency state transition STa of the RF signal 1106 frequency to the transition frequency controller FCSTa and stores the frequency values ​​of the state transition STa in the memory device of the transition frequency controller FCSTa. An example of a frequency value between state transitions STa is the envelope of the RF signal 1106 frequency between state transitions STa, such as the amplitude from zero to the peak or the amplitude from peak to peak. Furthermore, upon receiving the frequency level for state S(N±M)a to SNa, the DSP204 supplies the frequency level of state SNa of the RF signal 1106 to the frequency controller FCSNa, and stores the frequency level of state SNa in the memory device of the frequency controller FCSNa.

[0331] Upon receiving the synchronization signal 146, the DSP 204 transmits a command signal for the frequency state S(N±M)a to the frequency controller FCS(N±M)a during each cycle of the synchronization signal 146. For example, at the end of the transition time from a state different from state S(N±M)a, such as state S(N±M-1)a or state S0, to state S(N±M)a, the DSP 204 transmits a command signal for state S(N±M)a to the frequency controller FCS(N±M)a. The command signal for state S(N±M)a transmitted to the frequency controller FCS(N±M)a includes the time period of state S(N±M)a during each cycle, and the frequency controller FCS(N±M)a supplies the frequency level of state S(N±M)a to the driver system 1104. Upon receiving a command signal for state S(N±M)a, the frequency controller FCS(N±M)a accesses the frequency level of state S(N±M)a from its memory device and transmits the frequency level for the time period of state S(N±M)a to the driver system 1104. For example, at the end of the transition time from a different state to state S(N±M)a, the frequency controller FCS(N±M)a transmits the frequency level of state S(N±M)a to the driver system 1104. After the time period of state S(N±M)a, for the duration of the synchronization signal 146, the frequency controller FCS(N±M)a does not transmit the frequency level of state S(N±M)a to the driver system 1104.

[0332] Similarly, upon receiving the synchronization signal 146, the DSP 204 transmits a command signal for the state transition STa frequency to the transition frequency controller FCSTa during each cycle of the synchronization signal 146. For example, the DSP 204 transmits a command signal for the state transition STa frequency to the transition frequency controller FCSTa at the start of the transition time from state S(N±M)a to state SNa, or at the start of the transition time from state S0 to state SNa. The command signal for the state transition STa transmitted to the transition frequency controller FCSTa includes the time period of the state transition STa during each cycle, and the transition frequency controller FCSTa supplies one or more frequency values ​​of the state transition STa to the driver system 1104. Upon receiving the command signal for the state transition STa frequency controller FCSTa, the transition frequency controller FCSTa accesses one or more parameter values ​​of the state transition STa from its memory device and transmits one or more frequency values ​​to the driver system 1104 during the time period of the state transition STa. For example, the transition frequency controller FCSTa transmits one or more frequency values ​​of state transition STa to the driver system 1104 at the end of the state S(N±M)a time period. After the time period of state transition STa, the transition frequency controller FCSTa does not transmit one or more frequency values ​​of state transition STa to the driver system 1104 during the cycle of the synchronization signal 146.

[0333] Upon receiving the synchronization signal 146, the DSP 204 transmits a command signal for state SNa to the frequency controller FCSNa during each cycle of the synchronization signal 146. For example, the DSP 204 transmits a command signal for state transition SNa to the frequency controller FCSNa at the end of the transition time from state S(N±M)a to state SNa. The command signal for state SNa transmitted to the frequency controller FCSNa includes the time period of state SNa between each cycle, and the frequency controller FCSNa supplies the frequency level of state SNa to the driver system 1104. Upon receiving the command signal for state SNa, the frequency controller FCSNa accesses the frequency level of state SNa from its memory device and transmits the parameter level to the driver system 1104 for the time period of state SNa. For example, the frequency controller FCSNa transmits the frequency level of state SNa to the driver system 1104 at the end of the transition time from state S(N±M)a to state SNa. After a period of time in state SNa, for the duration of the synchronization signal 146, the frequency controller FCSNa does not transmit the frequency level of state SNa to the driver system 1104.

[0334] In response to the reception of the parameter level of state S(N±M)a and the frequency level of state S(N±M)a, the driver system 1104 generates a drive signal for state S(N±M)a for the duration of the parameter level state S(N±M)a and the frequency level state S(N±M)a, and transmits the drive signal to the RF power supply 222. For example, when the parameter level of state S(N±M)a is received at the end of the transition time from parameter state S(N±M-1)a or state S0 to state S(N±M)a, and when the frequency level of state S(N±M)a is received at the end of the transition time from frequency state S(N±M-1)a or state S0 to state S(N±M)a, the driver system 1104 generates a drive signal for parameter level state S(N±M)a and the frequency level state S(N±M)a for the duration of the state S(N±M)a, and transmits the drive signal to the RF power supply 222. When the RF power supply 222 receives a drive signal of state S(N±M)a from the driver system 1104, it generates the parameter state S(N±M)a and frequency state S(N±M)a of the RF signal 1106. For example, when the RF power supply 222 receives a drive signal of parameter state S(N±M)a and frequency state S(N±M)a from the driver system 1104, it generates the parameter state S(N±M)a and frequency state S(N±M)a of the RF signal 1106. The parameter state S(N±M)a of the RF signal 1106 has a parameter level of state S(N±M)a for the duration of the parameter state S(N±M)a. Similarly, the frequency state S(N±M)a of the RF signal 1106 has a frequency level of state S(N±M)a for the duration of the frequency state S(N±M)a.

[0335] Similarly, upon receiving one or more parameter values ​​and one or more frequency values ​​of the state transition STa, the driver system 1104 generates a drive signal for the state transition STa for the duration of the parameter state transition STa and frequency state transition STa of the RF signal 1106, and transmits the drive signal to the RF power supply 222. For example, upon receiving one or more parameter values ​​of the parameter state transition STa at the end of the time for parameter state S(N±M)a or state S0, and upon receiving one or more frequency values ​​of the frequency state transition STa at the end of the time for frequency state S(N±M)a or state S0, the driver system 1104 generates a drive signal for the parameter state transition STa and frequency state transition STa for the duration of the frequency and parameter state transition STa, and transmits the drive signal to the RF power supply 222. Upon receiving the drive signals for the frequency and parameter state transition STa from the driver system 1104, the RF power supply 222 generates the parameter state transition STa and frequency state transition STa of the RF signal 1106. For example, upon receiving drive signals for parameter state transition STa and frequency state transition STa from the driver system 1104, the RF power supply 222 initiates the transition of RF signal 1106 from parameter state S(N±M)a or parameter state S0 to parameter state SNa, and from frequency state S(N±M)a or frequency state S0 to frequency state SNa. The parameter state STa of RF signal 1106 has one or more parameter values ​​for the duration of the parameter state transition STa. The frequency state STa of RF signal 1106 has the frequency level for the duration of the frequency state transition STa.

[0336] In response to receiving the parameter level and frequency level of state SNa, the driver system 1104 generates a drive signal for the duration of the parameter level state SNa and the frequency level state SNa, and transmits the drive signal to the RF power supply 222. For example, when the parameter level of state SNa is received at the end of the transition time from parameter state S(N±M)a or state S0 to state SNa, and when the frequency level of state SNa is received at the end of the transition time from frequency state S(N±M)a or state S0 to state SNa, the driver system 1104 generates a drive signal for the parameter level state SNa and the frequency level state SNa for the duration of the state SNa, and transmits the drive signal to the RF power supply 222. When the RF power supply 222 receives the drive signal for state SNa from the driver system 1104, it generates the parameter level state SNa and the frequency level state SNa of the RF signal 1106. For example, upon receiving drive signals of parameter state SNa and frequency state SNa from the driver system 1104, the RF power supply 222 generates parameter state SNa and frequency state SNa for the RF signal 1106. The parameter state SNa of the RF signal 1106 has the parameter level of state SNa for the duration of the parameter state SNa. The frequency state SNa of the RF signal 1106 also has the frequency level of state SNa for the duration of the frequency state SNa.

[0337] In one embodiment, instead of parameter controllers PRS(N±M)a and PRSNa, transition parameter controller PRSTa, frequency controllers FCS(N±M)a and FCSNa, and transition frequency controller FCSTa, one or more controllers such as one or more processors are used to perform the functions performed by the parameter controllers PRS(N±M)a and PRSNa, transition parameter controller PRSTa, frequency controllers FCS(N±M)a and FCSNa, and transition frequency controller FCSTa as described herein.

[0338] In one embodiment, instead of the DSP204, parameter controllers PRS(N±M)a and PRSNa, transition parameter controller PRSTa, frequency controllers FCS(N±M)a and FCSNa, and transition frequency controller FCSTa, one or more controllers such as one or more processors are used to perform the functions performed by the DSP204, parameter controllers PRS(N±M)a and PRSNa, transition parameter controller PRSTa, frequency controllers FCS(N±M)a and FCSNa, and transition frequency controller FCSTa as described herein.

[0339] Figure 12A is a graph 300 of one embodiment showing the synchronization signal 302.

[0340] Figure 12B is a graph 1204 of one embodiment, showing the variables 1206 of the RF signal 1106 (Figures 11A and 11B), such as frequency or parameters, against time t. The variables 1206 are graphed on the y-axis, and time t is graphed on the x-axis.

[0341] Variable 1206 periodically transitions between variable levels V8a, V6a, V4a, and V2a in synchronization with the synchronization signal 302. For example, during cycle 1 of the synchronization signal 302, variable 1206 transitions between variable levels V8a, V6a, V4a, and V2a, and similarly during cycle 2 of the synchronization signal 302, it transitions between variable levels V8a, V6a, V4a, and V2a. For example, variable 1206 has a variable level V8a during state S4a of the RF signal 1106 from time t0 to time t1.5, has one or more variable values ​​during the variable state transition ST3a from time t1.5 to time t2.5, has a variable level V6a during state S3a from time t2.5 to time t4, has one or more variable values ​​during the variable state transition ST2a from time t4 to time t5, has a variable level V4a during state S2a from time t5 to time t6.5, has one or more variable values ​​during the variable state transition ST1a from time t6.5 to time t7.5, has a variable level V2a during state S1a from time t7.5 to time t9, and has one or more variable values ​​during the variable state transition ST4a from time t9 to time t10. Please note that time t1.5 is between time t1 and t2, and time 6.5 is between time t6 and t7.

[0342] During cycle 1 of the synchronization signal 302, variable 1206 begins a transition from variable level V8a to variable level V6a at time t1.5 and ends the transition at time t2.5. Also during cycle 1 of the synchronization signal 302, variable 1206 begins a transition from variable level V6a to variable level V4a at time t4 and ends the transition at time t5. During cycle 1 of the synchronization signal 302, variable 1206 begins a transition from variable level V4a to variable level V2a at time t6.5 and ends the transition at time t7.5. Also during cycle 1 of the synchronization signal 302, variable 1206 begins a transition from variable level V2a to variable level V8a at time t9 and ends the transition at time t10.

[0343] During cycle 2 of the synchronization signal 302, variable 1206 begins its transition from variable level V8a to variable level V6a at time t11.5 and ends the transition at time t12.5. Also during cycle 2 of the synchronization signal 302, variable 1206 begins its transition from variable level V6a to variable level V4a at time t14 and ends the transition at time t15. During cycle 2 of the synchronization signal 302, variable 1206 begins its transition from variable level V4a to variable level V2a at time t16.5 and ends the transition at time t17.5. Also during cycle 2 of the synchronization signal 302, variable 1206 begins its transition from variable level V2a to variable level V8a at time t19 and ends the transition at time t20. Note that time t11.5 is between time t11 and t12, and time 16.5 is between time t16 and t17.

[0344] In the state transition ST3a between variable levels V8a and V6a, one or more variable values ​​are smaller than those of variable level V8a and larger than those of variable level V6a. Similarly, in the state transition ST2a between variable levels V6a and V4a, one or more variable values ​​are smaller than those of variable level V6a and larger than those of variable level V4a. Also, in the state transition ST1a between variable levels V4a and V2a, one or more variable values ​​are smaller than those of variable level V4a and larger than those of variable level V2a. In the state transition ST4a between variable levels V2a and V8a, one or more variable values ​​are smaller than those of variable level V8a and larger than those of variable level V2a.

[0345] In one embodiment, instead of transitioning state S1a to variable level V2a, the variable of RF signal 1106 transitions to a variable level of zero.

[0346] In one embodiment, in addition to the synchronization signal 302, a digital pulse signal is received by the DSP 204 from the processor 118 via a transmission cable system 214 (Figure 11B). For example, the synchronization signal 302 is received via a first transmission cable of the transmission cable system 214, and the digital pulse signal is received via a second transmission cable of the transmission cable system 214. The digital pulse signal similarly transitions periodically between four logic levels 8, 6, 4, and 2, and the variable 1206 transitions between variable levels V8a, V6a, V4a, and V2a. For example, during cycle 1 of the synchronization signal 302, the digital pulse signal starts transitioning from logic level 8 to logic level 6 at time t1.5 and ends the transition at time t2.5. Also, during cycle 1 of the synchronization signal 302, the digital pulse signal starts transitioning from logic level 6 to logic level 4 at time t4 and ends the transition at time t5. During cycle 1 of the synchronization signal 302, the digital pulse signal begins a transition from logic level 4 to logic level 2 at time t6.5 and ends the transition at time t7.5. Also during cycle 1 of the synchronization signal 302, the digital pulse signal begins a transition from logic level 2 to logic level 8 at time t9 and ends the transition at time t10. Logic level 8 is greater than logic level 6, logic level 6 is greater than logic level 4, and logic level 4 is greater than logic level 2. For example, the DC voltage at logic level 8 is greater than the DC voltage at logic level 6, the DC voltage at logic level 6 is greater than the DC voltage at logic level 4, and the DC voltage at logic level 4 is greater than the DC voltage at logic level 2.

[0347] In this embodiment, during cycle 2 of the synchronization signal 302, the digital pulse signal begins a transition from logic level 8 to logic level 6 at time t11.5 and ends at time t12.5. Also during cycle 2 of the synchronization signal 302, the digital pulse signal begins a transition from logic level 6 to logic level 4 at time t14 and ends at time t15. During cycle 2 of the synchronization signal 302, the digital pulse signal begins a transition from logic level 4 to logic level 2 at time t16.5 and ends at time t17.5. Also during cycle 2 of the synchronization signal 302, the digital pulse signal begins a transition from logic level 2 to logic level 8 at time t19 and ends at time t20. Upon receiving the digital pulse signal, the DSP 204 identifies the time periods of states S1a to S4a and state transitions ST1a to ST4a of variable 1206 from the digital pulse signal and generates an instruction signal having these time periods. For example, the time duration of state transition ST1 of variable 1206 is the same as the transition time duration from logic level 4 to logic level 2 of a digital pulse signal, and the time duration of state ST2 of variable 1206 is the same as the transition time duration from logic level 6 to logic level 4 of a digital pulse signal.

[0348] Figure 12C is a graph 1208 of one embodiment, showing the variables 1210 versus time t of the RF signal 1106 (Figures 11A and 11B), such as frequency or parameters. The variables 1210 are graphed on the y-axis, and time t is graphed on the x-axis.

[0349] Variable 1210 periodically transitions between variable levels V8a, V6a, V4a, and V2a in synchronization with the synchronization signal 302. For example, during cycle 1 of the synchronization signal 302, variable 1210 transitions between variable levels V8a, V6a, V4a, and V2a, and similarly, during cycle 2 of the synchronization signal 302, it transitions between variable levels V8a, V6a, V4a, and V2a. For example, variable 1210 has a variable level V8a during state S4a of the RF signal 1106 from time t0 to time t1.5, has one or more variable values ​​during the variable state transition ST3a from time t1.5 to time t3.5, has a variable level V6a during state S3a from time t3.5 to time t4, has one or more variable values ​​during the variable state transition ST2a from time t4 to time t5, has a variable level V4a during state S2a from time t5 to time t6.5, has one or more variable values ​​during the variable state transition ST1a from time t6.5 to time t7.5, has a variable level V2a during state S1a from time t7.5 to time t9, and has one or more variable values ​​during the variable state transition ST4a from time t9 to time t10. Note that time t3.5 is between time t3 and t4.

[0350] During cycle 1 of the synchronization signal 302, variable 1210 begins its transition from variable level V8a to variable level V6a at time t1.5 and ends its transition at time t3.5. Also, during cycle 1 of the synchronization signal 302, the remaining transitions of variable 1210 are the same as the transitions of variable 1206 (Figure 12B).

[0351] During cycle 2 of the synchronization signal 302, variable 1210 begins its transition from variable level V8a to variable level V6a at time t11.5 and ends the transition at time t13.5. Also, during cycle 2 of the synchronization signal 302, the remaining transitions of variable 1210 are the same as the transitions of variable 1206. Note that time t13.5 is between times t13 and t14. The gradient of state transition ST3a is greater than the gradients of state transition ST2a and state transition ST1a.

[0352] In one embodiment, instead of transitioning state S1a to variable level V2a, variable 1210 transitions to a variable level of zero.

[0353] In one embodiment, the gradient of state transition ST3a is smaller than the gradients of state transition ST2a and state transition ST1a.

[0354] In one embodiment, one or more of the state transitions ST1a to STna of the variables described herein have a different gradient from the other one or more of the state transitions ST1a to STna. For example, state transition ST1a has a different gradient, such as being greater than or smaller than the gradient of state transition ST2a, state transition ST3a, and state transition ST4a. For example, state transition ST1a has an angle greater than the angle of state transition ST2a and state transition ST3a, and an angle smaller than the angle of state transition ST4a.

[0355] Figure 12D is a graph 1212 of one embodiment, showing various types of transitions between time t and variables 1214, such as frequency or parameters, of the RF signal 1106 (Figures 11A and 11B). Variables 1214 are graphed on the y-axis, and time t is graphed on the x-axis.

[0356] Variable 1214 periodically transitions between variable levels VRa and VSa in synchronization with the synchronization signal 302, where R and S are real numbers, and S is greater than R. For example, variable 1214 transitions between variable levels VRa and VSa during cycle 1 of the synchronization signal 302, and similarly transitions between variable levels VRa and VSa for the remaining cycles of the synchronization signal 302 (Figure 12A), such as cycle 2. For example, variable 1214 has variable level VSa during the variable state 1216 of the RF signal 1106 from time t1 to time t2.5, has one or more variable values ​​during the variable state transition 1220 from time t2.5 to time t3.5, and has variable level VRa during state 1218 from time t3.5 to time t5.

[0357] During state transition 1220, variable 1214 has multiple values ​​1222 and 1224 that define the negative linear gradient of state transition 1220 between states 1216 and 1218. Values ​​1222 and 1224 are less than the value at variable level VSa and greater than the value at variable level VRa. Note that during state transition 1220, variable 1214 may have more or less than two values.

[0358] In one embodiment, during the state transition 1220, the variable 1214 has a plurality of values ​​1226 and 1228 that define the convex gradient of the state transition 1220 between states 1216 and 1218.

[0359] In one embodiment, during state transition 1220, the variable 1214 has a plurality of values ​​1230 and 1232 that define the concave gradient of state transition 1220 between states 1216 and 1218. Each of the convex gradients and convex gradients of the variable 1214 is an example of a curved gradient.

[0360] Figure 12E is a graph 1250 of one embodiment, showing various types of transitions between time t and variables 1252 of an RF signal 1106 (Figures 11A and 11B), such as frequency or parameters. Variables 1252 are graphed on the y-axis, and time t is graphed on the x-axis.

[0361] Variable 1252 periodically transitions between variable levels VRa and VSa in a state synchronized with the synchronization signal 302. For example, variable 1252 transitions between variable levels VRa and VSa during cycle 1 of the synchronization signal 302, and similarly transitions between variable levels VRa and VSa during the remaining cycles of the synchronization signal 302 (Figure 12A), such as cycle 2. For example, variable 1252 has variable level VSa during the variable state 1218 of the RF signal 1106 from time t1 to time t2.5, has one or more variable values ​​during the variable state transition 1260 from time t2.5 to time t3.5, and has variable level VSa during state 1216 from time t3.5 to time t5.

[0362] During state transition 1260, variable 1252 has multiple values ​​1262 and 1264 that define the positive linear gradient of state transition 1260 between states 1216 and 1218. Values ​​1262 and 1264 are less than the value at variable level VSa and greater than the value at variable level VRa. Note that during state transition 1260, variable 1252 may have more or less than two values.

[0363] In one embodiment, during the state transition 1260, the variable 1252 has a plurality of values ​​1266 and 1268 that define the convex gradient of the state transition 1260 between states 1216 and 1218.

[0364] In one embodiment, during state transition 1260, the variable 1252 has a plurality of values ​​1270 and 1272 that define the concave gradient of the state transition 1260 between states 1216 and 1218. Each of the convex and convex gradients of the variable 1252 is an example of a curved gradient.

[0365] Figure 12F is a diagram of one embodiment of a pulse shaping method. As shown with respect to Figure 12F, the transition of the RF signal 1106 (Figure 11B) generated by the RF generator 1102 (Figure 11B) has a negative gradient and is modified to reduce the pulse width of one or more pulses from state S(nA) to Sn. For example, a gradient transition with a negative gradient is provided between state S(n-1) and Sn, rather than a vertical or substantially vertical transition from state S(n-1) to state Sn. Due to the negative gradient, the power level PL of the RF signal 1106 S(n-1) The pulse width is reduced during state S(n-1). The power level required to achieve the gradient transition is supplied to the RF generator 1102 from the host computer or host controller to achieve the gradient transition.

[0366] In one embodiment, a gradient transition occurs between frequency levels. For example, one frequency level transitions to another frequency level via a positive or negative gradient transition. The frequency level during the gradient transition is supplied from the host computer to the RF generator 1102, which generates an RF signal 1106 having this frequency level.

[0367] Figure 12G is a diagram of one embodiment of another pulse shaping method. As shown in Figure 12G, the transition gradient of the RF signal 1106 (Figure 11B) generated by the RF generator 1102 (Figure 11B) from state S(nA) to state S(n-A+1) is steeper, for example, greater than the transition gradient of the RF signal 1106 from state S(n-1) to state Sn.

[0368] In one embodiment, the transition gradient of the RF signal 1106 generated by the RF generator 1102 from state S(nA) to state S(n-A+1) is not very steep, such as being smaller than the transition gradient of the RF signal 1106 from state S(n-1) to state Sn.

[0369] Figure 12H is a diagram of another embodiment of a pulse shaping method. In Figure 12H, the transition gradient of the RF signal 1106 (Figure 11B) generated by the RF generator 1102 (Figure 11B) from state S(n-A+1) is curved, such as semiparabolic or exponential. Also, the transition gradient of the RF signal 1106 from state S(n-1) to state Sn is curved.

[0370] Figure 12I is a diagram of one embodiment of another pulse shaping method. As shown in Figure 12I, the transition gradient from state S(nA) to state S(n-A+1) of the RF signal 1106 (Figure 11B) generated by the RF generator 1102 (Figure 11B) is curved, and the transition gradient from state S(n-1) to state Sn of the RF signal 1106 is linear.

[0371] Figure 12J is a diagram of yet another embodiment of another pulse shaping method. As shown with respect to Figure 12J, the transitions of the RF signal 1106 (Figure 11B) generated by the RF generator 1102 (Figure 11B) have a positive or negative gradient and are modified to reduce the pulse width of one or more RF signals 1106 from state S(nA) to Sn. For example, a gradient transition with a negative gradient, rather than a vertical or substantially vertical transition from state S(n-1) to state Sn, is provided between states S(nA) and S(n-A+1). Due to the negative gradient, the power level PL of the RF signal 1106 S(n-A)The pulse width is reduced during state S(nA). As another example, a gradient transition with a positive gradient, rather than a vertical or substantially vertical transition from state S(n-1) to state Sn, is provided between states S(n-1) and Sn. Due to the positive gradient, the power level PL of RF signal 1106 Sn The pulse width is reduced during state Sn.

[0372] Figure 12K is a diagram of one embodiment of another pulse shaping method. In Figure 12K, the transition of the RF signal 1106 (Figure 11B) generated by the RF generator 1102 (Figure 11B) from state S(nA) to state S(n-A+1) has a linear gradient, such as a negative straight slope, and the transition of the RF signal 1106 from state S(n-1) to state Sn has a curved gradient, such as a concave slope. The curved gradient has a positive slope.

[0373] Figure 12L is a diagram of one embodiment of another pulse shaping method. In Figure 12L, the transition of the RF signal 1106 (Figure 11B) generated by the RF generator 1102 (Figure 11B) from state S(nA) to state S(n-A+1) has a linear gradient, such as a negative straight slope, and the transition of the RF signal 1106 from state S(n-1) to state Sn has a curved gradient, such as a convex slope. The curved gradient has a positive slope.

[0374] EtherCAT cable

[0375] Figure 13A is a diagram of one embodiment of System 1300, illustrating the transmission of information between various components of a plasma system via one or more Ethernet for Control Automation (EtherCAT) cables. An example of an EtherCAT cable is an Ethernet cable. EtherCAT is an Ethernet-based protocol used for real-time distributed control of information and is suitable for automation technologies. EtherCAT slave devices read the data to be handled, while EtherCAT frames or packets pass through the EtherCAT slave device and are processed in place. Similarly, input data is inserted into EtherCAT frames from the EtherCAT slave device, while EtherCAT frames pass through the EtherCAT slave device. EtherCAT frames are not fully received by the EtherCAT slave device until they are processed; instead, processing is initiated as quickly as possible. Transmission of input data from the EtherCAT slave device is performed with minimal delay of only a few bit times.

[0376] System 1300 includes a host computer 106, a source RF generator 102, a bias RF generator 104, a source matcher 108, and a bias matcher 110, each being an example of a component of a plasma tool or plasma system. A component of a plasma tool that transmits one or more EtherCAT frames is referred to herein as a master EtherCAT device, and a component of a plasma tool that receives one or more EtherCAT frames is referred to herein as a slave EtherCAT device. For example, the bias RF generator 104, the source matcher 108, and the bias matcher 110 are each examples of slave EtherCAT devices, and the source RF generator 102 is an example of a master EtherCAT device. The source RF generator 102, the bias RF generator 104, the source matcher 108, and the bias matcher 110 are each examples of components of a plasma system. One or more EtherCAT frames may be referred to herein as a pulse train.

[0377] The host computer 106 includes a processor 118 and a communications controller 1302. Examples of communications controllers used herein include ASICs, PLDs, controllers, and processors.

[0378] The processor 118 is coupled to the communication controller 1302. The communication controller 1302 is coupled to port 1308 of the source RF generator 102 via an EtherCAT cable 1304. Examples of Ethernet cables used herein include twisted-pair cables. For example, the Ethernet cable is a 100BASE-TX® or 100BASE-T4® cable capable of transmitting data at speeds of 100 megabits per second (Mbps) or more. Furthermore, another port 1310 of the source RF generator 102 is coupled to port 1312 of the bias RF generator 104 via an EtherCAT cable 1306.

[0379] The processor 118 transmits processor data 1311, including timing information for the synchronization signal 146 (Figure 7), variable information for the source RF generator, and bias RF variable information, to the communication controller 1302. An example of the timing information for the synchronization signal 146 includes the time when the synchronization signal 146 changed its logic level (e.g., from 1 to 0 or 0 to 1), the intervals between each cycle of the synchronization signal 146, and several cycles of the synchronization signal 146. The timing information also includes the logic levels 0 and 1 of the synchronization signal 146. An example of the variable information for the source RF generator includes variable levels such as parameter levels or frequency levels for each operating state of the source RF generator 102. For example, the variable information for the source RF generator includes power levels and frequency levels from the variable states S1a to Sna of the RF signal 152 generated by the source RF generator 102. An example of the variable information for the bias RF generator includes variable levels such as parameter levels or frequency levels for each operating state of the bias RF generator 104. For example, the variable information of the bias RF generator includes the power level and frequency level of the variable states S1a to Sna of the RF signal 168 generated by the bias RF generator 104.

[0380] The communication controller 1302 receives the processor data 1311, applies the EtherCAT protocol, embeds the processor data 1311, generates one or more EtherCAT frames 1314 containing the processor data 1311, and transmits one or more EtherCAT frames 1314 to port 1308 of the source RF generator 102 via the EtherCAT cable 1304. The communication controller of the source RF generator 102 receives one or more EtherCAT frames 1314 via port 1308, identifies source RF generator variable information and timing information for the synchronization signal 146 from one or more EtherCAT frames 1314, and transmits the source RF generator variable information and timing information to the DSP 204 of the source RF generator 102.

[0381] Furthermore, the communication controller of the source RF generator 102 transmits a request for information such as source RF generator measurement information to the DSP 204 of the source RF generator 102. An example of source RF generator measurement information includes factors determined or identified by the DSP 204 of the source RF generator 102. An example of factors identified by the DSP 204 of the source RF generator 102 includes criteria such as complex voltage-current, complex voltage or complex power, complex current, or complex impedance. The criteria are measured by a sensor for each state of the RF signal 152. The sensor that measures the criteria is located inside or outside the source RF generator 102 and is coupled to the output 154 of the source RF generator 102. Complex factors include magnitude and phase. For example, complex voltage includes the magnitude and phase of the complex voltage. Complex voltage-current includes the magnitude of the voltage, the magnitude of the current, and the phase between the voltage and the current. The sensor measures the criteria and supplies the criteria to the DSP 204 of the source RF generator 102. The DSP 204 of the source RF generator 102 identifies a reference from a measurement reference and / or determines a reference frequency for each state of the RF signal 152. For example, the DSP 204 of the source RF generator 102 applies a Fourier transform to the reference value to determine the reference frequency. The reference frequency is an example of a factor.

[0382] Upon receiving a request for information, the DSP 204 of the source RF generator 102 supplies source RF generator measurement information to the communication controller of the source RF generator 102. Upon receiving the source RF generator measurement information, the communication controller of the source RF generator 102 embeds the source RF generator measurement information into one or more EtherCAT frames 1314 and transmits one or more EtherCAT frames 1314 to the port 1312 of the bias RF generator 104 via the port 1310 of the source RF generator 102 and the EtherCAT cable 1306.

[0383] The communication controller of the bias RF generator 104 receives one or more EtherCAT frames 1314 via port 1312, identifies bias RF generator variable information and synchronization signal 146 timing information from one or more EtherCAT frames 1314, and transmits the bias RF generator variable information and timing information to the DSP 204 of the bias RF generator 104.

[0384] Furthermore, the communication controller of the bias RF generator 104 transmits a request for information such as bias RF generator measurement information to the DSP 204 of the bias RF generator 104. An example of bias RF generator measurement information includes factors determined or identified by the DSP 204 of the bias RF generator 104. An example of factors identified by the DSP 204 of the bias RF generator 104 includes a reference such as complex voltage / current, complex voltage or complex power, complex current, or complex impedance. The reference is measured by a sensor for each state of the RF signal 168. The sensor that measures the reference is located inside or outside the bias RF generator 104 and is coupled to the output 160 of the bias RF generator 104. The sensor measures the reference and supplies the reference to the DSP 204 of the bias RF generator 104. The DSP 204 of the bias RF generator 104 identifies the reference from the measured reference for each state of the RF signal 168 and determines the reference frequency. For example, the DSP204 of the bias RF generator 104 applies a Fourier transform to the reference value to determine the reference frequency.

[0385] Upon receiving a request for information, the DSP 204 of the bias RF generator 104 supplies bias RF generator measurement information to the communication controller of the source RF generator 104. Upon receiving the bias RF generator measurement information, the communication controller of the bias RF generator 104 embeds the bias RF generator measurement information in one or more EtherCAT frames 1314 and transmits one or more EtherCAT frames 1314 to port 1310 of the source RF generator 102 via port 1312 of the bias RF generator 104 and EtherCAT cable 1306. The communication controller of the source RF generator 102 receives one or more EtherCAT frames 1314 via port 1310 and transmits one or more EtherCAT frames 1314 to the communication controller 1302 of the host computer 106 via port 1308 and EtherCAT cable 1304.

[0386] The communication controller 1302 of the host computer 106 applies the EtherCAT protocol to one or more EtherCAT frames 1314 and obtains or extracts source RF generator measurement information for each state of the variables of the source RF signal 152 and bias RF generator measurement information for each state of the variables of the bias RF signal 168 from one or more EtherCAT frames 1314. The communication controller 1302 supplies the source RF generator measurement information and bias RF generator measurement information to the processor. The processor 118 decides whether to modify the variables of the source RF generator 102 between each state of the variables of the RF signal 152, or the variables of the bias RF generator 104 between each state of the variables of the RF signal 168, or a combination thereof, based on the source RF generator measurement information or bias RF generator measurement information or a combination thereof. The processor 118 controls the state of each variable of the RF signal 152 generated by the source RF generator 102 based on the modification variables of the source RF generator 102, and / or controls the state of each variable of the RF signal 168 generated by the bias RF generator 104 based on the modification variables of the bias RF generator 104.

[0387] In one embodiment, it should be noted that there is no storage for one or more EtherCAT frames 1314 in the source RF generator 102, and there is no storage for one or more EtherCAT frames 1314 in the bias RF generator 104. For example, one or more EtherCAT frames 1314 are in a constant state of movement in the memory device of the communication controller of the source RF generator 102, and one or more EtherCAT frames 1314 are in a constant state of movement in the memory device of the communication controller of the bias RF generator 104. For example, one or more EtherCAT frames 1314 move within the memory device, such as moving from one register to another in the register sequence of the communication controller of the source RF generator 102, while source RF generator variable information and source RF generator measurement information are transmitted between the communication controller of the source RF generator 102 and the DSP 204 of the source RF generator 102. As another example, one or more EtherCAT frames 1314 move within the memory device, such as moving from one register to another in the register sequence of the bias RF generator 104's communication controller, while bias RF generator variable information and bias RF generator measurement information are transmitted between the bias RF generator 104's communication controller and the bias RF generator 104's DSP 204.

[0388] Figure 13B is a diagram of one embodiment of system 1350, illustrating information transmission between various components of a plasma system via one or more EtherCAT cables. System 1350 includes a host computer 106, a source RF generator 102, a bias RF generator 104, a source matcher 108, and a bias matcher 110. A communication controller 1302 is coupled to port 1312 of the bias RF generator 104 via EtherCAT cable 1306.

[0389] The processor 118 transmits processor data 1311 to the communication controller 1302. The communication controller 1302 receives the processor data 1311, applies the EtherCAT protocol, embeds the timing information of the synchronization signal 146 and the source RF generator variable information of the processor data 1311, generates one or more EtherCAT frames 1352 containing the timing information of the synchronization signal 146 and the source RF generator variable information, and transmits one or more EtherCAT frames 1352 to port 1308 of the source RF generator 102 via the EtherCAT cable 1304. The communication controller of the source RF generator 102 receives one or more EtherCAT frames 1352 via port 1308, identifies the source RF generator variable information, and performs the same functions as described above with reference to Figure 13A until it receives source RF generator measurement information from the DSP 204 of the source RF generator 102. Upon receiving source RF generator measurement information, the communication controller of the source RF generator 102 embeds the source RF generator measurement information into one or more EtherCAT frames 1352 and transmits one or more EtherCAT frames 1352 to the communication controller 1302 of the host computer 106 via port 1308 of the source RF generator 102 and EtherCAT cable 1306.

[0390] In a similar manner, the communication controller 1302 receives the processor data 1311, applies the EtherCAT protocol, embeds the timing information of the synchronization signal 146 and the bias RF generator variable information of the processor data 1311, generates one or more EtherCAT frames 1354 containing the timing information of the synchronization signal 146 and the bias RF generator variable information, and transmits one or more EtherCAT frames 1354 to port 1312 of the bias RF generator 104 via the EtherCAT cable 1306. The communication controller of the bias RF generator 104 receives one or more EtherCAT frames 1354 via port 1312, identifies the bias RF generator variable information, and performs the same functions as described above with reference to Figure 13A until the bias RF generator measurement information is received from the DSP 204 of the bias RF generator 104. Upon receiving bias RF generator measurement information, the communication controller of the bias RF generator 104 embeds the bias RF generator measurement information into one or more EtherCAT frames 1354 and transmits one or more EtherCAT frames 1354 to the communication controller 1302 of the host computer 106 via port 1312 of the bias RF generator 104 and EtherCAT cable 1306.

[0391] The communication controller 1302 of the host computer 106 applies the EtherCAT protocol to one or more EtherCAT frames 1352 and obtains or extracts source RF generator measurement information from one or more EtherCAT frames 1352. The communication controller 1302 supplies the source RF generator measurement information to the processor 118.

[0392] Similarly, the communication controller 1302 of the host computer 106 applies the EtherCAT protocol to one or more EtherCAT frames 1354 and obtains or extracts bias RF generator measurement information from one or more EtherCAT frames 1354. The communication controller 1302 supplies the bias RF generator measurement information to the processor 118. The processor 118 performs the same functions as described above with reference to Figure 13A.

[0393] In one embodiment, it should be noted that there is no storage for one or more EtherCAT frames 1352 in the source RF generator 102, and there is no storage for one or more EtherCAT frames 1354 in the bias RF generator 104. For example, one or more EtherCAT frames 1352 are in a constant state of movement within the memory device of the communication controller of the source RF generator 102, and one or more EtherCAT frames 1354 are in a constant state of movement within the memory device of the communication controller of the bias RF generator 104. For example, one or more EtherCAT frames 1352 move within the memory device, such as moving from one register to another in the register sequence of the communication controller of the source RF generator 102, while source RF generator variable information and source RF generator measurement information are transmitted between the communication controller of the source RF generator 102 and the DSP 204 of the source RF generator 102. As another example, one or more EtherCAT frames 1352 move within the memory device, such as moving from one register to another in the register sequence of the bias RF generator 104's communication controller, while bias RF generator variable information and bias RF generator measurement information are transmitted between the bias RF generator 104's communication controller and the bias RF generator 104's DSP 204.

[0394] Figure 14 is a diagram of one embodiment of an EtherCAT frame 1400. An EtherCAT frame 1400 is an example of one or more EtherCAT frames 1314 (Figure 13A). Also, an EtherCAT frame 1400 is an example of one or more EtherCAT frames 1352 (Figure 13B) and one or more EtherCAT frames 1354 (Figure 13B).

[0395] In one embodiment, term frames and packets are used interchangeably herein. The EtherCAT frame 1400 includes fields 1401, 1403, 1402, 1404, 1406, 1408, 1410, 1412, 1414, 1416, and 1418.

[0396] Field 1401 contains the start of the frame delimiter, which identifies the beginning of the EtherCAT frame 1400. Field 1402 contains the source address of the EtherCAT frame 1400. An example of a source address is the address of the communication controller 1302 of the host computer 106 that generates the EtherCAT frame 1400. Field 1403 of the EtherCAT frame 1400 contains the sequence that circulates the EtherCAT frame 1400 through various components of the plasma system. An example of a sequence includes the sequence from the communication controller 1302 to the source RF generator 102, from the source RF generator 102 to the bias RF generator 104, from the bias RF generator 104 back to the source RF generator 102, and from the source RF generator 102 back to the processor 102. Another example of a sequence includes the sequence from the communication controller 1302 to the source RF generator 102, and from the source RF generator 102 back to the communication controller 1302.

[0397] Field 1404 contains the destination address of the EtherCAT frame 1400. An example of a destination address is the address of the communication controller 1302 on the host computer 106, and the address of the communication controller 1302 is the final destination of the EtherCAT frame 1400.

[0398] Field 1406 contains an address that identifies the source RF generator 102 (Figure 13A), which distinguishes the source RF generator 102 from other RF generators in the plasma system, such as a media access control (MAC) address. Field 1408 contains source RF generator variable information, and field 1410 contains source RF generator measurement information. The address that identifies the source RF generator 102 is used by the communication controller of the source RF generator 102 to determine whether the data in field 1408 should be supplied to the DSP 204 of the source RF generator 102, and whether the data received from the DSP 204 of the source RF generator 102 should be stored in field 1410.

[0399] Field 1412 contains an address that identifies the bias RF generator 104 (Figure 13A), which distinguishes the bias RF generator 104 from other RF generators in the plasma system, such as its MAC address. Field 1414 contains bias RF generator variable information, and field 1416 contains bias RF generator measurement information. The address that identifies the bias RF generator 104 is used by the bias RF generator 104's communication controller to determine whether the data in field 1414 should be supplied to the bias RF generator 104's DSP 204, and whether the data received from the bias RF generator 104's DSP 204 should be stored in field 1416.

[0400] Field 1418 includes a cyclic redundancy check (CRC) for one or more of fields 1408 and 1414. For example, the CRC is performed by the communication controller 1302 (Figure 13A) after receiving the EtherCAT frame 1400 to determine whether the source RF generator variable information in field 1408 transmitted by the communication controller 1302 matches the source RF generator variable information in field 1408 received by the communication controller 1302, thereby determining the validity of the EtherCAT frame 1400.

[0401] In one embodiment, any of fields 1406, 1408, and 1410, or fields 1412, 1414, and 1416 are not included in the EtherCAT frame 1400. For example, if the EtherCAT frame 1400 is an example of one or more EtherCAT frames 1452 transmitted to the source RF generator 102 (Figure 13B), the EtherCAT frame 1400 excludes fields 1412, 1414, and 1416 of the bias RF generator 104.

[0402] In one embodiment, any of fields 1406, 1408, and 1410, or fields 1412, 1414, and 1416 are included in the EtherCAT frame 1400 but are empty. For example, if the EtherCAT frame 1400 is an example of one or more EtherCAT frames 1452 transmitted to the source RF generator 102 (Figure 13B), the EtherCAT frame 1400 excludes any data or information from fields 1412, 1414, and 1416 of the bias RF generator 104.

[0403] Figure 15A is a diagram of one embodiment of system 1500, illustrating the transmission of information between various components of a plasma system via one or more EtherCAT cables. System 1500 includes a host computer 106, a source RF generator 102, a bias RF generator 104, a source matcher 108, and a bias matcher 110.

[0404] Port 1310 of the source RF generator 102 is connected to port 1502 of the source matcher 108 via EtherCAT cable 1306. Another port 1505 of the source matcher 108 is connected to port 1312 of the bias RF generator 104 via EtherCAT cable 1504. Another port 1506 of the bias RF generator 104 is connected to port 1510 of the bias matcher 110 via EtherCAT cable 1508.

[0405] The processor 118 transmits processor data 1501, which includes processor data 1302 (Figure 13A) for the source RF generator 102 and the bias RF generator 104, as well as matching data such as bias matching data, source matching data, or a combination thereof. The processor data 1501 is transmitted to the communication controller 1302. An example of source matching data includes one or more specifications for one or more components of the source matching device 108, and one or more specifications for one or more components of the bias matching device 110. An example of one or more specifications for one or more components of the source matching device 108 includes the capacitance value of the capacitor of the source matching device 108 and the inductance value of the inductor of the source matching device 108. An example of one or more specifications for one or more components of the bias matching device 110 includes the capacitance value of the capacitor of the bias matching device 110 and the inductance value of the inductor of the bias matching device 110.

[0406] The communication controller 1302 receives the processor data 1501, applies the EtherCAT protocol, embeds the processor data 1501, generates one or more EtherCAT frames 1512 containing the processor data 1501, and transmits one or more EtherCAT frames 1512 to port 1308 of the source RF generator 102 via the EtherCAT cable 1304. The communication controller of the source RF generator 102 receives one or more EtherCAT frames 1512 via port 1308, identifies source RF generator variable information and timing information for the synchronization signal 146 from one or more EtherCAT frames 1512, and transmits the source RF generator variable information and timing information to the DSP 204 of the source RF generator 102.

[0407] Furthermore, the communication controller of the source RF generator 102 transmits requests for information such as source RF generator measurement information and source state information of the RF signal 152 to the DSP 204 of the source RF generator 102. An example of source state information of the RF signal 152 includes timing information of the state of the RF signal 152 and / or timing information of state transitions. For example, the timing information of the state of the RF signal 152 includes the time when the RF signal 152 changes its variable level and the time while the RF signal 152 remains at that variable level. Referring further to Figure 10B, the timing information for state S4a of the RF signal 152 includes the time t0 when the variable 1006 of the RF signal 152 transitions from variable level V2a to variable level V8a, the time period between t0 and t2.5 when the variable 1006 of the RF signal 152 remains at variable level V8a, the time t2.5 when the variable 1006 of the RF signal 152 transitions from variable level V8a to a variable level of zero, the time t5 when the variable 1006 of the RF signal 152 transitions from a variable level of zero to variable level V6a, the time period between t5 and t7.5 when the variable 1006 of the RF signal 152 remains at variable level V6a, the time t7.5 when the variable 1006 transitions from variable level V6a to variable level V2a, and the time period between t7.5 and t10 when the variable 1006 of the RF signal 152 remains at variable level V2a.

[0408] As another example referring to Figure 12B, the timing information for state S4a of RF signal 152 includes the time t0 when variable 1206 of RF signal 152 transitions from variable level V2a to variable level V8a, and the time period between t0 and t1.5 when variable 1206 of RF signal 152 remains at variable level V8a. The timing information for state transition ST4a of variable 1206 of RF signal 152 includes the time t1.5 when the variable of RF signal 152 begins its transition from variable level V8a to variable level V6a, and the time t2.5 when variable 1206 of RF signal 152 stops its transition. Similarly, the timing information for the state transition ST3a of the RF signal 152 variable 1206 includes the time t4 when the RF signal 152 variable 1206 begins its transition from variable level V6a to variable level V4a, and the time t5 when the RF signal 152 variable 1206 stops its transition; the timing information for the state transition ST2a of the RF signal 152 variable 1206 includes the time t6.5 when the RF signal 152 variable 1206 begins its transition from variable level V4a to variable level V2a, and the time t7.5 when the RF signal 152 variable 1206 stops its transition; and the timing information for the state transition ST4a of the RF signal 152 variable 1206 includes the time t9 when the RF signal 152 variable 1206 begins its transition from variable level V2a to variable level V8a, and the time t10 when the RF signal 152 variable 1206 stops its transition.

[0409] Upon receiving a request for information, the DSP 204 of the source RF generator 102 supplies source RF generator measurement information and source status information to the communication controller of the source RF generator 102. Upon receiving the source RF generator measurement information and source status information, the communication controller of the source RF generator 102 embeds the source RF generator measurement information and source status information into one or more EtherCAT frames 1512 and transmits one or more EtherCAT frames 1512 to port 1502 of the source matching unit 108 via port 1310 of the source RF generator 102 and EtherCAT cable 1306.

[0410] The communication controller of the source matcher 108 receives one or more EtherCAT frames 1512 via the port 1502 of the source matcher 108, extracts source matching data and source state information from the one or more EtherCAT frames 1512, and transmits the source matching data and source state information to the processor of the source matcher 108. The processor of the source matcher 108 controls one or more components of the source matcher 108 according to the source matching data and source state information. For example, the processor of the source matcher 108 does not control the components of the source matcher 108 between one or more states S1a to Sna, but controls the components between the remaining states S1a to Sna. The processor of the source matcher 108 controls the components of the source matcher 108 to achieve the capacitance and inductance values ​​in the source matching data.

[0411] Furthermore, the communication controller of the source matcher 108 transmits requests for information such as source matcher measurement information to the processor of the source matcher 108. An example of source matcher measurement information is a reference measured by a sensor connected to a component of the source matcher 108 or to the output 158 ​​of the source matcher 108. The sensor is located inside or outside the source matcher 108. Upon receiving a request for information, the processor of the source matcher 108 supplies the source matcher measurement information to the communication controller of the source matcher 108. The communication controller of the source matcher 108 embeds the source matcher measurement information in one or more EtherCAT frames 1512 and transmits one or more EtherCAT frames 1512 to port 1312 of the bias RF generator 104 via port 1505 and EtherCAT cable 1504.

[0412] The communication controller of the bias RF generator 104 receives one or more EtherCAT frames 1512 via port 1312, identifies bias RF generator variable information and synchronization signal 146 timing information from one or more EtherCAT frames 1512, and transmits the bias RF generator variable information and timing information to the DSP 204 of the bias RF generator 104.

[0413] Furthermore, the communication controller of the bias RF generator 104 transmits requests for information such as bias RF generator measurement information and bias state information of the RF signal 168 to the DSP 204 of the bias RF generator 104. An example of bias state information of the RF signal 168 includes timing information of the state of the RF signal 168 and / or timing information of state transitions. For example, the timing information of the state of the RF signal 168 includes the time when the RF signal 168 changes its variable level and the time while the RF signal 168 remains at that variable level. Referring further to Figure 10B, the timing information for state S4a of the RF signal 168 includes the time t0 when the variable 1006 of the RF signal 168 transitions from variable level V2a to variable level V8a, the time period between t0 and t2.5 when the variable 1006 of the RF signal 168 remains at variable level V8a, the time t2.5 when the variable 1006 of the RF signal 168 transitions from variable level V8a to a variable level of zero, the time t5 when the variable 1006 of the RF signal 168 transitions from a variable level of zero to variable level V6a, the time period between t5 and t7.5 when the variable 1006 of the RF signal 168 remains at variable level V6a, the time t7.5 when the variable 1006 transitions from variable level V6a to variable level V2a, and the time period between t7.5 and t10 when the variable 1006 of the RF signal 168 remains at variable level V2a.

[0414] As another example referring to Figure 12B, the timing information for state S4a of RF signal 168 includes the time t0 when variable 1206 of RF signal 168 transitions from variable level V2a to variable level V8a, and the time period between t0 and t1.5 when variable 1206 of RF signal 168 remains at variable level V8a. The timing information for state transition ST4a of variable 1206 of RF signal 168 includes the time t1.5 when variable 1206 of RF signal 168 begins its transition from variable level V8a to variable level V6a, and the time t2.5 when variable 1206 of RF signal 168 stops its transition. Similarly, the timing information for the state transition ST3a of the RF signal 168 variable 1206 includes the time t4 when the RF signal 168 variable 1206 begins its transition from variable level V6a to variable level V4a, and the time t5 when the RF signal 168 variable 1206 stops its transition; the timing information for the state transition ST2a of the RF signal 168 variable 1206 includes the time t6.5 when the RF signal 168 variable 1206 begins its transition from variable level V4a to variable level V2a, and the time t7.5 when the RF signal 168 variable 1206 stops its transition; and the timing information for the state transition ST4a of the RF signal 168 variable 1206 includes the time t9 when the RF signal 168 variable 1206 begins its transition from variable level V2a to variable level V8a, and the time t10 when the RF signal 168 variable 1206 stops its transition.

[0415] Upon receiving a request for information, the DSP 204 of the bias RF generator 104 supplies bias RF generator measurement information and bias status information to the communication controller of the bias RF generator 104. Upon receiving the bias RF generator measurement information and bias status information, the communication controller of the bias RF generator 104 embeds the bias RF generator measurement information and bias status information into one or more EtherCAT frames 1512 and transmits one or more EtherCAT frames 1512 to the port 1510 of the bias matcher 110 via port 1506 of the bias RF generator 104 and EtherCAT cable 1508.

[0416] The communication controller of the bias matcher 110 receives one or more EtherCAT frames 1512 via the port 1510 of the bias matcher 110, extracts bias matcher data and bias state information from the one or more EtherCAT frames 1512, and transmits the bias matcher data and bias state information to the processor of the source matcher 110. The processor of the bias matcher 110 controls one or more components of the bias matcher 110 according to the bias matcher data and bias state information. For example, the processor of the bias matcher 110 does not control the components of the bias matcher 110 during one or more states S1a to Sna, but controls the components during the remaining states S1a to Sna. The processor of the bias matcher 110 controls the components of the bias matcher 110 to achieve the capacitance and inductance values ​​in the bias matcher data.

[0417] Furthermore, the communication controller of the bias matcher 110 transmits requests for information such as bias matcher measurement information to the processor of the bias matcher 110. An example of bias matcher measurement information includes a reference measured by a component of the bias matcher 110 or a sensor coupled to the output 164 of the bias matcher 110. The sensor is located inside or outside the bias matcher 110. Upon receiving a request for information, the processor of the bias matcher 110 supplies the bias matcher measurement information to the communication controller of the bias matcher 110. The communication controller of the bias matcher 110 embeds the bias matcher measurement information in one or more EtherCAT frames 1512 and transmits one or more EtherCAT frames 1512 to port 1506 of the bias RF generator 104 via port 1510 and EtherCAT cable 1508.

[0418] The communication controller of the bias RF generator 104 receives one or more EtherCAT frames 1512 from the bias matcher 110 via port 1506 and transmits one or more EtherCAT frames 1512 to port 1505 of the source matcher 108 via port 1312 and EtherCAT cable 1504. The communication controller of the source matcher 108 receives one or more EtherCAT frames 1512 from the bias RFG 104 via port 1505 and transmits one or more EtherCAT frames 1512 to port 1310 of the source RF generator 102 via port 1502 and EtherCAT cable 1306. The communication controller of the source RF generator 102 receives one or more EtherCAT frames 1512 via port 1310 and transmits one or more EtherCAT frames 1512 to the communication controller 1302 of the host computer 106 via port 1308 and EtherCAT cable 1304.

[0419] The communication controller 1302 of the host computer 106 applies the EtherCAT protocol to one or more EtherCAT frames 1512 and obtains or extracts source RF generator measurement information and bias RF generator measurement information from one or more EtherCAT frames 1314. The communication controller 1302 supplies the source RF generator measurement information and bias RF generator measurement information to the processor 118.

[0420] Figure 15B is a diagram of one embodiment of system 1550, illustrating information transmission between various components of a plasma system via one or more EtherCAT cables. System 1550 includes a host computer 106, a source RF generator 102, a bias RF generator 104, a source matcher 108, and a bias matcher 110. A communication controller 1302 is coupled to port 1505 of source matcher 108 via EtherCAT cable 1508, and the communication controller 1302 is coupled to port 1510 of bias matcher 110 via EtherCAT cable 1504.

[0421] The processor 118 transmits processor data 1501 to the communication controller 1302. The communication controller 1302 receives the processor data 1501, applies the EtherCAT protocol, embeds the timing information of the synchronization signal 146 and the source harmonizer data in the processor data 1311, generates one or more EtherCAT frames 1552 containing the timing information of the synchronization signal 146 and the source harmonizer data, and transmits one or more EtherCAT frames 1552 to port 1505 of the source harmonizer 108 via the EtherCAT cable 1508. The communication controller of the source harmonizer 108 receives one or more EtherCAT frames 1552 via port 1505, identifies the source harmonizer data, and performs the same functions as described above with reference to Figure 15A until it receives source harmonizer measurement information from the processor of the source harmonizer 108. Upon receiving source matching unit measurement information, the communication controller of the source matching unit 108 embeds the source matching unit measurement information into one or more EtherCAT frames 1552 and transmits one or more EtherCAT frames 1552 to the communication controller 1302 of the host computer 106 via the port 1505 of the source matching unit 108 and the EtherCAT cable 1508.

[0422] Similarly, the communication controller 1302 receives the processor data 1501, applies the EtherCAT protocol, embeds the timing information of the synchronization signal 146 and the bias matcher data in the processor data 1311, generates one or more EtherCAT frames 1554 having the timing information of the synchronization signal 146 and the bias matcher data, and transmits one or more EtherCAT frames 1554 to the port 1510 of the bias matcher 110 via the EtherCAT cable 1504. The communication controller of the bias matcher 110 receives one or more EtherCAT frames 1554 via port 1510, identifies the bias matcher data, and performs the same functions as described above with reference to Figure 15A until bias matcher measurement information is received from the processor of the bias matcher 110. Upon receiving bias matcher measurement information, the communication controller of the bias matcher 110 embeds the source matcher measurement information into one or more EtherCAT frames 1554 and transmits one or more EtherCAT frames 1554 to the communication controller 1302 of the host computer 106 via the port 1510 of the bias matcher 110 and the EtherCAT cable 1504.

[0423] The communication controller 1302 of the host computer 106 applies the EtherCAT protocol to one or more EtherCAT frames 1552 and obtains or extracts source matcher measurement information from one or more EtherCAT frames 1552. The communication controller 1302 supplies the source matcher measurement information to the processor 118. Upon receiving the source matcher measurement information, the processor 1108 controls one or more of the source RF generator 102, source matcher 108, bias RF generator 104, and bias matcher 110 based on the source matcher measurement information.

[0424] Similarly, the communication controller 1302 of the host computer 106 applies the EtherCAT protocol to one or more EtherCAT frames 1554 and obtains or extracts bias matcher measurement information from one or more EtherCAT frames 1554. The communication controller 1302 supplies the bias matcher measurement information to the processor 118. Upon receiving the bias matcher measurement information, the processor 1108 controls one or more of the source RF generator 102, source matcher 108, bias RF generator 104, and bias matcher 110 based on the bias matcher measurement information.

[0425] In one embodiment, it should be noted that there is no storage for one or more EtherCAT frames 1552 in the source matcher 108 and no storage for one or more EtherCAT frames 1554 in the bias matcher 110. For example, one or more EtherCAT frames 1552 are in a constant state of movement in the source matcher 108, and one or more EtherCAT frames 1554 are in a constant state of movement in the bias matcher 110. For example, one or more EtherCAT frames 1552 move within the memory device, such as moving from one register to another in the register sequence of the communication controller of the source matcher 108, while source matcher data and source matcher measurement information are transmitted between the communication controller of the source matcher 108 and the processor of the source matcher 108. As another example, one or more EtherCAT frames 1554 move within the memory device, such as moving from one register to another in the register sequence of the bias matcher 110's communication controller, while bias matcher data and bias matcher measurement information are transmitted between the bias matcher 110's communication controller and the bias matcher 110's processor.

[0426] Figure 16 shows one embodiment of an EtherCAT frame 1600. An EtherCAT frame 1600 is an example of one or more EtherCAT frames 1512 (Figure 15A). An EtherCAT frame 1600 is an example of one or more EtherCAT frames 1552 (Figure 15B). An EtherCAT frame 1600 is also an example of one or more EtherCAT frames 1554 (Figure 15B).

[0427] The EtherCAT frame 1600 includes several fields 1401, 1403, 1402, 1404, 1406, 1408, 1410, 1602, 1604, 1606, 1608, 1412, 1414, 1416, 1610, 1612, 1614, 1616, and 1418. Field 1401 includes the start of the frame delimiter, which identifies the beginning of the EtherCAT frame 1600. Field 1402 includes the source address of the EtherCAT frame 1600. An example of a source address is the address of the host computer 106 that generates the EtherCAT frame 1600.

[0428] Field 1403 of the EtherCAT frame 1600 contains the sequence for circulating the EtherCAT frame 1600 through various components of the plasma system. An example of a sequence for circulating the EtherCAT frame 1600 includes a sequence from the communication controller 1302 to the source RF generator 102, from the source RF generator 102 to the source matcher 108, from the source matcher 108 to the bias RF generator 104, from the bias RF generator 104 to the bias matcher 110, from the bias matcher 110 back to the bias RF generator 104, from the bias RF generator 104 to the source matcher 108, from the source matcher 108 to the source RF generator 102, and from the source RF generator 102 to the communication controller 1302. Another example of a sequence for cycling through EtherCAT frames 1600 includes a sequence from the communication controller 1302 to the source RF generator 102, and then back from the source RF generator 102 to the communication controller 1302.

[0429] Field 1404 contains the destination address of the EtherCAT frame 1600. An example of a destination address is the address of the communication controller 1302 on the host computer 106, and the address of the communication controller 1302 is the final destination of the EtherCAT frame 1600.

[0430] Field 1602 contains source status information. The address identifying the source RF generator 102 is used by the communication controller of the source RF generator 102 to determine whether the data received from the source RF generator 102's DSP 204 should be stored in field 1602.

[0431] Field 1604 contains the address of source matcher 108, which identifies source matcher 108 (Figure 13A) and distinguishes it from other RF generators in the plasma system, such as its MAC address. Field 1606 contains source matcher data, and field 1608 contains source matcher measurement information. The address identifying source RF generator 108 is used by the communication controller of source matcher 108 to determine whether the data in field 1606 should be supplied to the processor of source matcher 108 and whether the data received from the processor of source matcher 108 should be stored in field 1608.

[0432] Field 1610 contains bias status information. The address identifying the bias RF generator 104 is used by the communication controller of the bias RF generator 104 to determine whether the data received from the bias RF generator 104's DSP 204 should be stored in field 1610.

[0433] Field 1612 contains the address of bias matcher 110, which identifies bias matcher 110 (Figure 13A) and distinguishes it from other RF generators in the plasma system, such as its MAC address. Field 1614 contains bias matcher data, and field 1616 contains bias matcher measurement information. The address identifying bias matcher 110 is used by the bias matcher 110's communication controller to determine whether the data in field 1614 should be supplied to the bias matcher 110's processor and whether the data received from the bias matcher 110's processor should be stored in field 1616.

[0434] Field 1418 includes a CRC for one or more of fields 1408, 1410, 1602, 1606, 1608, 1414, 1416, 1610, 1614, and 1616. For example, the CRC is performed by the communication controller 1302 (Figure 13A) after receiving the EtherCAT frame 1600 to determine whether the source RF generator variable information in field 1408 transmitted by the communication controller 1302 matches the source RF generator variable information in field 1408 received by the communication controller 1302, thereby determining the validity of the EtherCAT frame 1400.

[0435] In one embodiment, fields 1408, 1410, and 1602, or fields 1606 and 1608, or fields 1414, 1416, and 1610, or fields 1614 and 1616, or any combination thereof, are not included in the EtherCAT frame 1600. For example, if EtherCAT frame 1600 is an example of one or more EtherCAT frames 1552 (Figure 15B) transmitted to source matcher 108 (Figure 15B), then EtherCAT frame 1600 excludes fields 1408, 1410, 1602, 1414, 1416, 1610, 1614, and 1616 of source RF generator 102, bias RF generator 104, and bias matcher 110.

[0436] In one embodiment, fields 1408, 1410, and 1602, or fields 1606 and 1608, or fields 1414, 1416, and 1610, or fields 1614 and 1616, or any combination thereof, are included in the EtherCAT frame 1600 but are empty. For example, if the EtherCAT frame 1600 is an example of one or more EtherCAT frames 1552 sent to the source matcher 108, the EtherCAT frame 1600 excludes all data or information in fields 1408, 1410, 1602, 1414, 1416, 1610, 1614, and 1616 of the source RF generator 102, bias RF generator 104, and bias matcher 110.

[0437] In one embodiment, it should be noted that the addresses of the components of the plasma system described herein are the addresses of the communication controllers of the components. For example, the MAC address of the source RF generator 102 is the address of the communication controller of the source RF generator 102, the MAC address of the bias RF generator 104 is the address of the communication controller of the bias RF generator 104, the MAC address of the source matcher 108 is the address of the communication controller of the source matcher 108, and the MAC address of the bias matcher 110 is the address of the communication controller of the bias matcher 110.

[0438] Figure 17 shows one embodiment of system 1700, and shows an RF generator 1702 coupled to EtherCAT cables 1706 and 1708. RF generator 1702 is an example of source RF generator 102 or bias RF generator 104 (Figure 15A). EtherCAT cable 1706 is an example of any of EtherCAT cables 1304 (Figure 13A), 1306 (Figure 13B), and 1504 (Figure 15A). EtherCAT cable 1708 is an example of any of EtherCAT cables 1306 and 1508 (Figures 13A and 15A).

[0439] The RF generator 1702 includes a communication controller 1704, a DSP 204, an RF power supply 222, and a sensor 1710. Examples of the sensor 1710 include a complex voltage / current sensor, a complex impedance sensor, a complex power sensor, and a complex voltage sensor. RF generator 202 (Figure 2) is an example of RF generator 1702, except that the DSP 204 is coupled to the processor 118 of the host computer 106 via the communication controller 1704. Also, any of the RF generators 702 (Figure 7), 802 (Figure 8), 902 (Figure 9), and 1102 (Figure 11A) are examples of RF generator 1702, except that the DSP 204 is coupled to the processor 118 of the host computer 106 via the communication controller 1704.

[0440] The communication controller 1704 is connected to EtherCAT cable 1706 via port 1714 of the communication controller 1704, and to EtherCAT cable 1708 via another port 1716 of the communication controller 1704. The communication controller 1704 is also connected to DSP 204. Sensor 1710 is connected to DSP 204 and to output 1712 of RF generator 1702. Outputs 158 and 164 (Figure 1) are examples of output 1712.

[0441] The communication controller 1704 receives one or more EtherCAT frames 1712 from the plasma system components via port 1714. For example, the communication controller 1704 receives one or more EtherCAT frames 1314 (Figure 13A), 1352 (Figure 13B), 1354 (Figure 13C), or 1512 (Figure 15A) from the plasma system components via port 1714. The communication controller 1704 processes one or more EtherCAT frames 1712 and identifies the address of the RF generator 1702. For example, the communication controller 1704 compares the address of the RF generator 1702 with the address of the RF generator 1702 pre-stored in the memory device of the communication controller 1704 and determines whether the two addresses match. If it determines that the two addresses match, the communication controller 1704 identifies the address of the RF generator 1702 from one or more EtherCAT frames 1712.

[0442] Upon identifying an address, the communication controller 1704 identifies the data, extracts it from one or more EtherCAT frames 1712, and supplies it to the DSP 204. For example, the data supplied to the DSP 204 from the RF generator 1702 is identified as data between the address of the RF generator 1702 in one or more EtherCAT frames 1712 and the next address in one or more EtherCAT frames 1712. Using Figure 14 as an example, the source RF generator variable information in field 1408 is between the source RF generator address in field 1406 and the bias RF generator address in field 1412. An example of data supplied to the DSP 204 includes the source RF generator variable information in field 1408 or the bias RF generator variable information in field 1414. Upon identifying the data, the communication controller 1704 extracts (obtains, reads, copies, etc.) the data to be supplied to the DSP 204 from one or more EtherCAT frames 1712 and transmits the data to the DSP 204.

[0443] Sensor 1710 measures a reference for one or more of the conditions described above and supplies the reference to DSP 204. DSP 204 supplies the reference to communication controller 1714, or calculates factors from the reference and supplies the factors to communication controller 1714, or a combination thereof. Communication controller 1704 also receives data from DSP 204 and includes the data in the field of RF generator 1702 in one or more EtherCAT frames 1712. For example, communication controller 1704 receives factors from DSP 204, embeds the factors in one or more EtherCAT frames 1712, and transmits the factors via port 1714 and EtherCAT cable 1706 to source components such as the plasma system's processor 118 or source RF generator 102 or source matcher 108, or transmits one or more EtherCAT frames 1712 via port 1716 to destination components such as the plasma system's source matcher 108 or bias RF generator 104. For example, to send one or more EtherCAT frames 1712 to a component such as a source component, destination component, or any other component of a plasma system, the communication controller 1704 reads the sequence field 1403 of one or more EtherCAT frames 1712 and identifies the address of the component from one or more EtherCAT frames 1712. To further example, to identify the address of the component, the communication controller 1704 compares the address of the destination component stored in one or more EtherCAT frames 1712 with the address of the component previously stored in the memory device of the communication controller 1704 and determines whether the two addresses match. If it determines that the two addresses match, the communication controller 1704 identifies the address of the component from one or more EtherCAT frames 1712 and sends one or more EtherCAT frames 1712 to the component. The source component is the component on which one or more EtherCAT frames 1712 are received by the RF generator 1702, and the destination component is the component on which one or more EtherCAT frames 1712 are transmitted by the RF generator 1702.When one or more EtherCAT frames 1712 are transmitted to the destination component of the plasma system via port 1716, one or more EtherCAT frames 1712 are then received from the destination component via port 1716 and transmitted to the destination component via port 1714 by the communication controller 1704.

[0444] In one embodiment, multiple sensors are associated with an RF generator 1702. For example, another sensor is coupled to a point on an RF cable 138 or 142 (Figure 1) and also to a DSP 204, which measures a reference and supplies it to the DSP 204.

[0445] In one embodiment, system 1700 excludes the EtherCAT cable 1708, and communication controller 1702 excludes port 1716.

[0446] Figure 18 shows an embodiment of system 1800, which includes a matching circuit 1802. The matching circuit 1802 is coupled to an RF generator 1702 (Figure 17) via an RF cable 1804 and to EtherCAT cables 1806 and 1808. RF cable 1804 is an example of any of RF cables 138 and 142 (Figure 1) and 218 (Figure 2). Matching circuit 1802 is an example of a source matching circuit 108 (Figure 15A) or a bias matching circuit 110 (Figure 15B). EtherCAT cable 1806 is an example of any of EtherCAT cables 1306 (Figure 15A), 1508 (Figure 15B), and 1504 (Figures 15A and 15B). EtherCAT cable 1808 is an example of EtherCAT cable 1504 (Figure 15A).

[0447] The matching unit 1802 includes a communication controller 1810, a processor 1812, a driver system 1814, a sensor system 1816, a circuit component system 1818, and a motor system 1820. An example of the sensor system 1816 includes one or more sensors, such as sensor 1710 (Figure 17). An example of the driver system 1814 includes one or more drivers, such as one or more transistors coupled together. An example of the circuit component system 1818 includes one or more circuit components, such as one or more inductors and capacitors coupled together. An example of the motor system 1820 includes one or more electric motors. Each electric motor is coupled to its respective circuit component, such as an inductor or capacitor, in the circuit component system 1818.

[0448] Source matcher 108 or bias matcher 110 is an example of matcher 1802, except that matcher 1802 includes communication controller 1810 and processor 1812. Communication controller 1810 is coupled to EtherCAT cable 1806 via port 1826 of communication controller 1810 and to EtherCAT cable 1808 via port 1828 of communication controller 1810. Communication controller 1810 is also coupled to processor 1812. Processor 1812 is coupled to sensor system 1816 and driver system 1814, and driver system 1814 is coupled to motor system 1820. Motor system 1820 is coupled to circuit component system 1818, and circuit component system 1818 is coupled to RF cable 1804 and plasma chamber 112 via RF transmission line 1822. Circuit component system 1818 is coupled to sensor system 1816. For example, the first sensor of sensor system 1816 is coupled to the first circuit component of circuit component system 1818, and the second sensor of sensor system 1816 is coupled to the second circuit component of circuit component system 1818. Either of the transmission lines 140 and 144 (Figure 1) is an example of an RF transmission line 1822.

[0449] The communication controller 1810 receives one or more EtherCAT frames 1824 from the plasma system components via port 1826. For example, the communication controller 1810 receives one or more EtherCAT frames 1512 (Figure 15A), 1552 (Figure 15B), or 1554 (Figure 15C) from the plasma system components via port 1826. The communication controller 1810 processes one or more EtherCAT frames 1824 and identifies the address of the matching unit 1802. For example, the communication controller 1810 compares the address of the matching unit 1802 with the address of the matching unit 1802 pre-stored in the memory device of the communication controller 1810 and determines whether the two addresses match. If it determines that the two addresses match, the communication controller 1810 identifies the address of the matching unit 1802 from one or more EtherCAT frames 1824.

[0450] Upon identifying an address, the communication controller 1810 identifies the data, extracts it from one or more EtherCAT frames 1824, and supplies it to the processor 1812. For example, the data supplied to the processor 1812 for a matcher 1802 is identified as the data between the address of the matcher 1802 in one or more EtherCAT frames 1824 and the next address in one or more EtherCAT frames 1824. Using Figure 16 as an example, the source matcher data in field 1606 is between the source matcher address in field 1604 and the bias RF generator address in field 1412. An example of data supplied to the processor 1812 includes the source matcher data in field 1606 or the bias matcher data in field 1614. The communication controller 1810 extracts (reads, obtains, copies, etc.) the data to be supplied to the processor 1812 from one or more EtherCAT frames 1512 and transmits the data to the processor 1812.

[0451] The sensor system 1816 measures a reference at one or more outputs of one or more circuit components of the circuit component system 1818 and supplies the reference to the processor 1812. The processor 1812 supplies the reference to the communication controller 1810. The communication controller 1810 also receives data from the processor 1812 and includes the data in the fields of the matching unit 1802 in one or more EtherCAT frames 1824. For example, the communication controller 1810 receives the reference from the processor 1812, embeds the reference in one or more EtherCAT frames 1824, and transmits the reference via port 1826 and EtherCAT cable 1806 to a source component such as the plasma system's source RF generator 108 or bias RF generator 104 or host computer 106, or transmits one or more EtherCAT frames 1824 via port 1828 to a destination component such as the plasma system's bias RF generator 104. For example, to transmit one or more EtherCAT frames 1824 to a component such as a source component, destination component, or any other component of a plasma system, the communication controller 1810 reads the sequence field 1403 of one or more EtherCAT frames 1824 and identifies the destination address from one or more EtherCAT frames 1824. For example, to identify the address of a destination component, the communication controller 1810 compares the address of the destination component stored in one or more EtherCAT frames 1824 with the address of the destination component previously stored in the memory device of the communication controller 1810 and determines whether the two addresses match. If it determines that the two addresses match, the communication controller 1810 identifies the address of the destination component from one or more EtherCAT frames 1824 and transmits one or more EtherCAT frames 1824 to the destination component.

[0452] The source component is a single component from which one or more EtherCAT frames 1824 are received by the matching unit 1802. The destination component is a component from which one or more EtherCAT frames 1824 are transmitted by the matching unit 1802. Once one or more EtherCAT frames 1824 are transmitted to the destination component of the plasma system via port 1828, one or more EtherCAT frames 1824 are subsequently received from the destination component via port 1828 and transmitted to the destination component via port 1826 by the communication controller 1810.

[0453] In one embodiment, multiple sensors are associated with a matching unit 1802. For example, another sensor is coupled to a point on an RF transmission line 1804 and also to a processor 1812 to measure a reference and supply it to the processor 1812.

[0454] In one embodiment, system 1800 excludes the EtherCAT cable 1808, and communication controller 1810 excludes port 1828.

[0455] Figure 19A shows another embodiment of the EtherCAT synchronization system 1920, such as a plasma system, where multiple EtherCAT cables are coupled between any two components of the EtherCAT synchronization system 1920. For example, one EtherCAT cable is coupled from the output port of the master controller to the input port of the source RF generator 102, another EtherCAT cable is coupled from another output port of the master controller to the input port of the bias RF generator 104, another EtherCAT cable is coupled from the output port of the source RF generator 102 to the input port of the source matcher 108, and another EtherCAT cable is coupled from the output port of the bias RF generator 104 to the input port of the bias matcher 110. An example of a master controller includes a host controller or host computer 106 (Figure 1) or ADVCI or another controller.

[0456] State information for the source RF generator 102 and source matcher 108 is supplied in pulse trains, which are transmitted from the master controller to the source RF generator 102 and from the source RF generator 102 to the source matcher 108. For example, the duty cycle from state S(nA) to Sn, power level, and frequency level of the variable of the RF signal 152 generated by the source RF generator 102, as well as source matcher data, are supplied in pulse trains transmitted from the master controller to the source RF generator 102, and the duty cycle from state S(nA) to Sn is supplied in pulse trains transmitted from the source RF generator 102 to the source matcher 108. Similarly, the duty cycle, power level, and frequency level of the RF signal 168 variables from state S(nA) to Sn, as well as bias matcher data, are supplied by another pulse train transmitted from the master controller to the source RF generator 104, and the duty cycle from state S(nA) to Sn is supplied by another pulse train transmitted from the bias RF generator 104 to the bias matcher 110.

[0457] Figure 19B shows one embodiment of an EtherCAT synchronization system 1930 for a plasma system, where an EtherCAT cable is connected between the output port of the master controller and the input port of the source RF generator 102, between the output port of the source RF generator 102 and the input port of the bias RF generator 104, between the output port of the source RF generator 102 and the input port of the source matcher 108, and from the output port of the source matcher 108 to the input port of the bias matcher 110.

[0458] The status information of the source RF generator 102, source matcher 108, bias RF generator 104, and bias matcher 110 is supplied by pulse trains transmitted from the master controller to the source RF generator 102. For example, the duty cycle from the state S(nA) to Sn of the variables of RF signals 152 and 168, the power level and frequency level, source matcher data, and bias matcher data are supplied by pulse trains transmitted from the master controller to the source RF generator 102. The pulse trains are transmitted from the source RF generator 102 to the bias RF generator 104. The pulse trains transmitted from the source RF generator 102 to the source matcher 108 are then transmitted from the source matcher 108 to the bias matcher 110.

[0459] In one embodiment, an EtherCAT cable is connected from the output port of the bias RF generator 104 to the input of the source RF generator 102, and an EtherCAT cable is connected from the output port of the bias matcher 110 to the input port of the source matcher 108. In this embodiment, an EtherCAT cable is used that connects the output port of the master controller to the input port of the bias RF generator 104, rather than an EtherCAT cable that connects the master controller to the source RF generator 102. Also, an EtherCAT cable is connected from the output port of the bias RF generator 104 to the input port of the bias matcher 110. Status information of the source RF generator 102, source matcher 108, bias RF generator 104, and bias matcher 110 is supplied by a pulse train transmitted from the master controller to the bias RF generator 104. For example, a pulse train is transmitted from the master controller to the bias RF generator 104, from the bias RF generator 104 to the source RF generator 102, from the bias RF generator 104 to the bias matcher 110, and from the bias matcher 110 to the source matcher 108.

[0460] Figure 19C shows an embodiment of an EtherCAT synchronization system 1950 for plasma systems, etc., in which the components are connected in a daisy-chain fashion. For example, an EtherCAT cable is connected from the output port of the master controller to the input port of the source RF generator 102, an EtherCAT cable is connected from the output port of the source RF generator 102 to the input port of the source matcher 108, an EtherCAT cable is connected from the output port of the source matcher 108 to the input port of the bias matcher 110, and an EtherCAT cable is connected from the output port of the bias matcher 110 to the input port of the bias RF generator 104.

[0461] Status information for the source RF generator 102, source matcher 108, bias RF generator 104, and bias matcher 110 is supplied by a pulse train transmitted from the master controller to the source RF generator 102. The pulse train is then transmitted from the source RF generator 102 to the source matcher 108, then from the source matcher 108 to the bias matcher 110, and finally from the bias matcher 110 to the bias RF generator 104.

[0462] Figure 19D shows one embodiment of an EtherCAT synchronization system 1960 for plasma systems, etc., in which the components are connected in a daisy-chain fashion. For example, an EtherCAT cable is connected from the output port of the master controller to the input port of the bias RF generator 104, an EtherCAT cable is connected from the output port of the bias RF generator 104 to the input port of the bias matcher 110, an EtherCAT cable is connected from the output port of the bias matcher 110 to the input port of the source matcher 108, and an EtherCAT cable is connected from the output port of the source matcher 108 to the input port of the source RF generator 102.

[0463] Status information for the source RF generator 102, source matcher 108, bias RF generator 104, and bias matcher 110 is supplied by a pulse train transmitted from the master controller to the bias RF generator 104. The pulse train is then transmitted from the bias RF generator 104 to the bias matcher 110, then from the bias matcher 110 to the source matcher 108, and finally from the source matcher 108 to the source RF generator 102.

[0464] calibration

[0465] Figure 20 is a diagram of one embodiment of system 2000 showing a pulse train calibration method. As shown in Figure 20, the host computer 106 (Figure 1) or a radio frequency generator (RFG) such as a digital signal processor or ADVCI provides PL to the radio frequency generator RFG for multiple states S(nA), S(n-A+1)...S(n-1) and Sn. S(n-A) PL S(n-A+1) ···PL S(n-1) and PL SnIt supplies power levels such as A, where A is a positive integer. For example, some states S(nA) through Sn range from 4 to 36. For example, the number of states could be 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, or 16. Each state lasts for at least 1 microsecond. For example, each duty cycle from state S(nA) through Sn is the same. For example, state S(nA) lasts for several microseconds, state S(n-A+1) lasts for the same microseconds, and so on until state Sn lasts for the same microseconds. As another example, the duty cycle of one or more states is different from the duty cycle of one or more of the remaining states. For example, state S(nA) occurs for a first microsecond, and state Sn occurs for a second microsecond. Another example is state S(nA) occurring for a first microsecond, state S(n-A+1) occurring for a second microsecond, and state Sn occurring for a third microsecond. An example of a radio frequency generator RFG is RF generator 702 (Figure 7). Another example of a radio frequency generator RFG is RF generator 902 (Figure 9).

[0466] The radio frequency generator (RFG) is a power level PL (Power Level). S(n-A) PL S(n-A+1) ···PL S(n-1) and PL Sn An RF signal is generated and supplied to a known load, such as a 50-ohm load. A voltage sensor coupled to the known load measures the voltage value and supplies the voltage value to the RFG controller. For example, the voltage sensor is coupled to the input of the known load. In another example, the voltage sensor is coupled to an RF cable, which is coupled between the radio frequency generator RFG and the known load. The RFG controller calculates the state S(nA), S(n-A+1) from the voltage value received from the voltage sensor. S(n-A) , V S(n-A+1) ···V S(n-1)The RFG controller determines the voltage values ​​of VSn, etc. For each state, it determines whether the power level of the state should be changed based on the voltage value of the state, and based on that decision, sets the power level PL S(n-A) PL S(n-A+1) ···PL S(n-1) and PL Sn Adjust one or more of these. For example, an RFG controller determines whether the voltage value of a state is outside a preset range and adjusts the power level of the state until the voltage value is within the preset range.

[0467] Figure 21 is a diagram of one embodiment of system 2000 showing a voltage pulse leveling method. As described above with respect to system 2000 in Figure 20, the power level PL S(n-A) PL S(n-A+1) ···PL S(n-1) and PL Sn An RF signal having is supplied to a known load, and a voltage sensor measures the voltage value. The voltage value is supplied to the RFG controller. Referring back to system 2000 in Figure 21, the RFG controller divides each state into multiple substates or subpulses. For example, state S(nA) is divided similarly until substates S(nA)1, S(nA)2, and substate S(nA)m are determined, and so on, where m is an integer greater than or equal to 3. As another example, state S(n-1) is divided into substates S(n-1)1 and S(n1-1)2, and state Sn is divided similarly until substates Sn1, Sn2, and substate Snm are determined. For each substate, the RFG controller determines the voltage value from the measured voltage value received from the voltage sensor. As an example, the RFG controller determines the voltage value V S(n-A)1 , V S(n-A)2 and the voltage value V from lower state S(nA)1 to state S(nA)m S(n-A)m Continue the calculations in the same manner until you have calculated the following. For example, the voltage value V S(n-A)1 This is a statistical measurement of the voltage value, such as the mean or median, measured during the lower state S(nA)1, and the voltage value V S(n-A)2 This is a statistical measurement of the voltage value measured during the lower state S(nA)2. Similarly, the RFG controller uses the voltage value V S(n-1)1 , V S(n-1)2and the voltage values V from the lower states S(n - 1)1 to S(n - 1)m S(n-1)m are calculated in the same way hereinafter until the voltage value V Sn1 , V Sn2 and the voltage values V from the lower states Sn1 to the state Snm Snm are calculated. Based on the calculated voltage values of each lower state, the RFG controller adjusts the power level PL of the lower state S(n - A)2 of the state S(n - A) S(n-A)2 and the power level PL of the lower state S(n - 1)1 of the state S(n - 1) S(n-1)1 etc., of the lower states until the voltage value is within a predetermined range. In this way, the RFG controller adjusts one or more of the power levels PL S(n-A) , PL S(n-A+1) ···PL S(n-1) and PL Sn .

[0468] FIG. 22 is a diagram of an embodiment of a system 2000 showing a duty cycle calibration method. As described with respect to FIG. 20, the voltage sensor measures the voltage value and supplies the voltage value to the RFG controller. Referring to system 100, the RFG controller determines the duty cycles of the power levels PL S(n-A) , PL S(n-A+1) ···PL S(n-1) and PL Sn from state S(n - A) to Sn based on the voltage values of the states. For example, a plurality of voltage values of state Sn are measured during a duration, and a plurality of voltage values of state S(n - A) are measured during the same or different durations. The voltage values of state S(n - A) are different from the voltage values of state Sn.

[0469] The determined duty cycles are the duty cycle DC of the power level PL S(n-A) of the state S(n - A), such as the duty cycle DC of the power level PL S(n-1) of the state S(n - 1), and the duty cycle DC of the power level PL S(n-1) of the state Sn S(n-1) and the duty cycle DC of the power level PL Sn of the state Sn SnThe following is also included until a determination is made. The RFG controller determines whether each of the duty cycles for the corresponding state is within a preset duty cycle range. The RFG controller adjusts one or more of the duty cycles for one or more of the corresponding states until one or more duty cycles are within the corresponding preset duty cycle range. For example, the RFG controller adjusts the duty cycle DC Sn However, in response to the determination that state Sn is not within the preset duty cycle range, the power level PL Sn Duty cycle DC of state Sn Sn To increase or decrease.

[0470] Note that in one embodiment, instead of using the voltage sensor in the system shown in Figures 20, 21, or 22, a power sensor for measuring power, or a complex voltage / current sensor for measuring complex voltage / current, may be used.

[0471] Tuning of four or more states (tuning the TCCT matching unit to the average impedance)

[0472] Figure 23 shows a system 2300 including a controller (CTRL) and a source matcher 108 such as a source-transformer coupled capacitive tuning (TCCT) matcher. An example of a controller includes an RFG controller (Figure 20). Further examples of controllers include a host computer 106 (Figure 1) and a host controller. An example of a TCCT matcher is provided in U.S. Patent No. 10,056,231, which is incorporated herein by reference in its entirety.

[0473] The controller CTRL is coupled to the source RF generator 102, the bias RF generator 104, the source matcher 108, and the bias matcher 110. The source matcher 108 is coupled to the TCP coil 126 of the plasma chamber 112. The substrate support 128 or the lower electrode of the substrate support 128 may be referred to herein as the bias electrode.

[0474] The controller CTRL supplies timing information to the source matcher 108 regarding states S(nA) through Sn. For example, the controller CTRL supplies the source matcher 108 with duty cycles including start and end times for each state from S(nA) through Sn. The timing information is supplied to the source matcher 108, enabling it to tune between one or more states from S(nA) through Sn, matching the impedance of the load coupled to the output of the source matcher 108 with the impedance of the source coupled to the input of the source matcher 108, and ...

Claims

1. A method for generating multiple states of plasma impedance, wherein the method is Receiving a synchronization signal that has multiple cycles that repeat periodically, The method involves generating a first radio frequency (RF) signal using a first RF generator, wherein the first RF signal includes at least two parameter levels within one cycle of the plurality of cycles. The method involves generating a second RF signal using a second RF generator, wherein the second RF signal includes at least three parameter levels within one cycle of the plurality of cycles. Methods that include...

2. The method according to claim 1, The first RF signal is supplied to an impedance matching network coupled to the first electrode of the plasma chamber, The second RF signal is supplied to an impedance matching network coupled to the second electrode of the plasma chamber. Methods that further include the above.

3. A method according to claim 1, wherein the synchronization signal is a digital pulse signal having a duty cycle, and the duty cycle is repeated between the plurality of cycles.

4. A method according to claim 1, wherein the synchronization signal repeatedly transitions between a first logic level and a second logic level during the plurality of cycles, and the first logic level is greater than the second logic level.

5. A method according to claim 1, wherein the at least two parameter levels of the first RF signal include a first positive parameter level and a second positive parameter level, the second positive parameter level of the first RF signal being greater than the first positive parameter level of the first RF signal, and the at least three parameter levels of the second RF signal include a zero parameter level, a first positive parameter level, and a second positive parameter level, the second positive parameter level of the second RF signal being less than the first positive parameter level of the second RF signal.

6. A method according to claim 1, wherein a combination of one of the at least two parameter levels of the first RF signal and one of the at least three parameter levels of the second RF signal defines a plasma impedance state.

7. A method according to claim 1, wherein the at least two parameter levels of the first RF signal include two parameter levels, including a first parameter level and a second parameter level; the at least three parameter levels of the second RF signal include three parameter levels, including a first parameter level, a second parameter level, and a third parameter level; the first RF signal transitions between the first parameter level and the second parameter level in two transition times during one cycle of the plurality of cycles; the second RF signal transitions between the first parameter level, the second parameter level, and the third parameter level in three transition times during one cycle of the plurality of cycles; and at least one of the three transition times of the second RF signal is different from at least one of the two transition times of the first RF signal in order to generate the plurality of state plasma impedances.

8. The method according to claim 1, wherein the at least two parameter levels of the first RF signal include two parameter levels, including a first parameter level and a second parameter level, and the at least three parameter levels of the second RF signal include three parameter levels, including a zero parameter level, a second parameter level and a first parameter level, and the method is During one of the aforementioned multiple cycles, the first RF signal is transitioned from the second parameter level to the first parameter level in a first transition time, During one of the aforementioned multiple cycles, the first RF signal is transitioned from the first parameter level to the second parameter level in a second transition time, During one of the aforementioned multiple cycles, the second RF signal is transitioned from the first parameter level to the zero parameter level in a third transition time, During one of the aforementioned multiple cycles, the second RF signal is transitioned from the zero parameter level to the second parameter level in a fourth transition time, During one of the aforementioned multiple cycles, the second RF signal is transitioned from the second parameter level to the first parameter level in a fifth transition time. A method further comprising the first transition time and at least one of the second transition time being different from at least one of the third transition time, the fourth transition time and the fifth transition time during one cycle of the plurality of cycles in order to generate the plasma impedance of the plurality of states.

9. A control system that generates multiple states of plasma impedance, wherein the control system is A first processor of a first radio frequency (RF) generator, configured to receive a synchronization signal having multiple cycles that repeat periodically, A second processor of a second RF generator, configured to receive the aforementioned synchronization signal, Equipped with, The first processor is configured to control a first RF power supply of the first RF generator in order to generate a first RF signal, the first RF signal including at least two parameter levels within one cycle of the plurality of cycles. A controller system wherein the second processor is configured to control a second RF power supply of the second RF generator to generate a second RF signal, the second RF signal having at least three parameter levels within one cycle of the plurality of cycles.

10. A controller system according to claim 9, wherein the first RF power supply is configured to supply the first RF signal to an impedance matching network coupled to a first electrode of a plasma chamber, and the second RF power supply is configured to supply the second RF signal to an impedance matching network coupled to a second electrode of the plasma chamber.

11. A controller system according to claim 9, wherein the synchronization signal is a digital pulse signal having a duty cycle, and the duty cycle is repeated between the plurality of cycles.

12. A controller system according to claim 9, wherein the synchronization signal repeatedly transitions between a first logic level and a second logic level during the plurality of cycles, and the first logic level is greater than the second logic level.

13. A controller system according to claim 9, wherein the at least two parameter levels of the first RF signal include a first positive parameter level and a second positive parameter level, the second positive parameter level of the first RF signal being greater than the first positive parameter level of the first RF signal, and the at least three parameter levels of the second RF signal include a zero parameter level, a first positive parameter level, and a second positive parameter level, the second positive parameter level of the second RF signal being less than the first positive parameter level of the second RF signal.

14. A controller system according to claim 9, wherein a combination of one of the at least two parameter levels of the first RF signal and one of the at least three parameter levels of the second RF signal defines a plasma impedance state.

15. A controller system according to claim 9, wherein the at least two parameter levels of the first RF signal include two parameter levels, including a first parameter level and a second parameter level; the at least three parameter levels of the second RF signal include three parameter levels, including a first parameter level, a second parameter level, and a third parameter level; the first RF signal transitions between the first parameter level and the second parameter level in two transition times during one cycle of the plurality of cycles; the second RF signal transitions between the first parameter level, the second parameter level, and the third parameter level in three transition times during one cycle of the plurality of cycles; and at least one of the three transition times of the second RF signal is different from at least one of the two transition times of the first RF signal in order to generate the plurality of state plasma impedances.

16. A controller system according to claim 9, wherein the at least two parameter levels of the first RF signal include two parameter levels, including a first parameter level and a second parameter level, the at least three parameter levels of the second RF signal include three parameter levels, including a zero parameter level, a second parameter level and a first parameter level, and the first processor is The first RF power supply is controlled, and during one cycle of the plurality of cycles, the first RF signal is transitioned from the second parameter level to the first parameter level in a first transition time. The first RF power supply is controlled to transition the first RF signal from the first parameter level to the second parameter level during one of the plurality of cycles, with a second transition time. The second processor is further configured as follows: Control the second RF power supply and, during one cycle of the plurality of cycles, transition the second RF signal from the first parameter level to the zero parameter level in a third transition time. Control the second RF power supply and, during one cycle of the plurality of cycles, transition the second RF signal from the zero parameter level to the second parameter level in a fourth transition time. The second RF power supply is controlled to transition the second RF signal from the second parameter level to the first parameter level during a fifth transition time within one of the multiple cycles. It is configured in such a way, A controller system wherein at least one of the first transition time and the second transition time is different from at least one of the third transition time, the fourth transition time and the fifth transition time during one cycle of the plurality of cycles in order to generate the plasma impedance of the plurality of states.

17. A plasma system that generates multiple states of plasma impedance, wherein the plasma system is A first RF generator configured to generate a first radio frequency (RF) signal, A second RF generator configured to generate a second RF signal, The first RF generator and the second RF generator are each configured to receive a synchronization signal having a plurality of cycles that repeat periodically. The first RF signal includes at least two parameter levels within one cycle of the plurality of cycles, The plasma system wherein the second RF signal includes at least three parameter levels within one of the plurality of cycles.

18. A plasma system according to claim 17, wherein the first RF generator is coupled to an RF coil of a plasma chamber via a first impedance matching network, and the first RF generator is configured to supply the first RF signal to the first impedance matching network; and the second RF power generator is coupled to a substrate support of the plasma chamber via a second impedance matching network, and the second RF generator is configured to supply the second RF signal to the second impedance matching network.

19. A plasma system according to claim 17, wherein the at least two parameter levels of the first RF signal include two parameter levels, including a first parameter level and a second parameter level; the at least three parameter levels of the second RF signal include three parameter levels, including a first parameter level, a second parameter level, and a third parameter level; the first RF signal transitions between the first parameter level and the second parameter level in two transition times during one cycle of the plurality of cycles; the second RF signal transitions between the first parameter level, the second parameter level, and the third parameter level in three transition times during one cycle of the plurality of cycles; and at least one of the three transition times of the second RF signal is different from at least one of the two transition times of the first RF signal in order to generate the plurality of state plasma impedance.

20. A plasma system according to claim 17, wherein the at least two parameter levels of the first RF signal include two parameter levels, including a first parameter level and a second parameter level, the at least three parameter levels of the second RF signal include three parameter levels, including a zero parameter level, a second parameter level and a first parameter level, and the first RF generator is During one of the plurality of cycles, the first RF signal is transitioned from the second parameter level to the first parameter level in a first transition time. During one of the aforementioned multiple cycles, the first RF signal is transitioned from the first parameter level to the second parameter level during a second transition time. The second RF generator is configured as follows: During one of the aforementioned multiple cycles, the second RF signal is transitioned from the first parameter level to the zero parameter level in a third transition time. During one of the aforementioned multiple cycles, the second RF signal is transitioned from the zero parameter level to the second parameter level in a fourth transition time. During one of the aforementioned multiple cycles, the second RF signal is transitioned from the second parameter level to the first parameter level at a fifth transition time. It is configured in such a way, A plasma system in which at least one of the first transition time and the second transition time is different from at least one of the third transition time, the fourth transition time and the fifth transition time during one cycle of the plurality of cycles in order to generate the plasma impedance of the plurality of states.

21. A method for pulsing multiple states, wherein the method is Receiving the synchronization signal, Identifying multiple cycles from the aforementioned synchronization signal, During one cycle of the aforementioned plurality of cycles, a radio frequency (RF) signal having four or more variable levels is generated. A method comprising, wherein each of the four or more variable levels defines the maximum amplitude of the RF signal, and the four or more variable levels are repeated during another cycle of the plurality of cycles.

22. A method according to claim 21, wherein the receiving is performed by an RF generator, the synchronization signal is a digital pulse signal, the digital pulse signal is periodically repeated and has a plurality of cycles, each of which has a duty cycle.

23. A method according to claim 21, wherein identifying the plurality of cycles includes identifying a first cycle of the plurality of cycles and a second cycle of the plurality of cycles, and identifying the first cycle of the plurality of cycles and the second cycle of the plurality of cycles includes identifying the start time and stop time of the first cycle of the plurality of cycles and the start time and stop time of the second cycle of the plurality of cycles.

24. A method according to claim 21, wherein each of the four or more variable levels is a parameter level, each of the four or more parameter levels has a plurality of amplitudes, the maximum amplitude is the maximum amplitude of the plurality of amplitudes in each of the four or more parameter levels, and the maximum amplitude is the envelope of the RF signal.

25. A method according to claim 21, wherein each of the four or more variable levels is a separate horizontal level, and the RF signal is an oscillation signal.

26. A method according to claim 21, wherein each of the four or more variable levels is frequency or power.

27. A method according to claim 21, wherein during one cycle of the plurality of cycles, the RF signal transitions from a first variable level of the four or more variable levels to a second variable level of the four or more variable levels, from the second variable level of the four or more variable levels to a third variable level of the four or more variable levels, and from the third variable level of the four or more variable levels to a fourth variable level of the four or more variable levels.

28. A method according to claim 21, wherein each of the four or more variable levels defines the minimum amplitude of the RF signal, and the minimum amplitude of the first variable level of the four or more variable levels is greater than the maximum amplitude of the second variable level of the four or more variable levels.

29. The method according to claim 21, wherein during one cycle of the plurality of cycles, the RF signal transitions from a first variable level of the four or more variable levels to a second variable level of the four or more variable levels, from the second variable level of the four or more variable levels to a third variable level of the four or more variable levels, and from the third variable level of the four or more variable levels to a fourth variable level of the four or more variable levels, and the method is Controlling the transition gradient from the first variable level to the second variable level of the four or more variable levels, Controlling the transition gradient from the second variable level to the third variable level of the four or more variable levels, Controlling the transition gradient from the third variable level to the fourth variable level of the four or more variable levels. Methods that further include the above.

30. A radio frequency (RF) generator for pulse generation of multiple states, wherein the RF generator is A processor configured to receive a synchronization signal, and configured to identify a plurality of cycles from the synchronization signal, RF power supply and An RF generator comprising, wherein the processor is configured to control the RF power supply to generate a radio frequency (RF) signal having four or more variable levels during one cycle of the plurality of cycles, each of the four or more variable levels defining the maximum amplitude of the RF signal, and the four or more variable levels are repeated during another cycle of the plurality of cycles.

31. An RF generator according to claim 30, wherein the synchronization signal is a digital pulse signal, the digital pulse signal is periodically repeated and has a plurality of cycles, each of which has a duty cycle.

32. RF generator according to claim 30, wherein the processor is configured to identify a first cycle and a second cycle of the plurality of cycles in order to identify the plurality of cycles, and the processor is configured to identify the start time and stop time of the first cycle and the start time and stop time of the second cycle of the plurality of cycles in order to identify the first cycle and the second cycle of the plurality of cycles.

33. An RF generator according to claim 30, wherein each of the four or more variable levels is a parameter level, each of the four or more parameter levels has a plurality of amplitudes, the maximum amplitude is the maximum amplitude of the plurality of amplitudes in each of the four or more parameter levels, and the maximum amplitude is the envelope of the RF signal.

34. An RF generator according to claim 30, wherein each of the four or more variable levels is a separate horizontal level, and the RF signal is an oscillation signal.

35. An RF generator according to claim 30, wherein each of the four or more variable levels is frequency or power.

36. RF generator according to claim 30, wherein during one cycle of the plurality of cycles, the processor is configured to control the RF power supply and transition from a first variable level of the four or more variable levels to a second variable level of the four or more variable levels, from the second variable level of the four or more variable levels to a third variable level of the four or more variable levels, and from the third variable level of the four or more variable levels to a fourth variable level of the four or more variable levels.

37. An RF generator according to claim 30, wherein each of the four or more variable levels defines the minimum amplitude of the RF signal, and the minimum amplitude of the first variable level of the four or more variable levels is greater than the maximum amplitude of the second variable level of the four or more variable levels.

38. A controller for pulse generation of multiple states, wherein the controller is A processor configured to generate a synchronization signal containing multiple cycles, The memory device coupled to the processor and A controller comprising a processor configured to control a radio frequency (RF) generator and generate an RF signal having four or more variable levels during one cycle of the plurality of cycles, each of the four or more variable levels defining the maximum amplitude of the RF signal, and the four or more variable levels being repeated during another cycle of the plurality of cycles.

39. A controller according to claim 38, wherein the synchronization signal is a digital pulse signal, the digital pulse signal is periodically repeated and has a plurality of cycles, each of which has a duty cycle.

40. A controller according to claim 38, wherein the plurality of cycles includes a first cycle of the plurality of cycles and a second cycle of the plurality of cycles, the first cycle of the plurality of cycles includes a start time and a stop time, and the second cycle of the plurality of cycles includes a start time and a stop time.

41. A controller according to claim 38, wherein each of the four or more variable levels is a parameter level, each of the four or more parameter levels has a plurality of amplitudes, the maximum amplitude is the maximum amplitude of the plurality of amplitudes in each of the four or more parameter levels, and the maximum amplitude is the envelope of the RF signal.

42. A method for communicating information between multiple components of a plasma tool, wherein the method is Receiving one or more Ethernet for Control Automation (EtherCAT) frames with a radio frequency (RF) generator, wherein the RF generator is one of the plurality of components of the plasma tool, The RF generator extracts multiple variable levels from one or more Ethernet frames, The RF generator generates an RF signal having the plurality of variable levels for one cycle of the synchronization signal, Identifying the destination address of one or more of the aforementioned Ethernet frames, Sending one or more Ethernet frames to another component of the plurality of components at the destination address: Methods that include...

43. A method according to claim 42, wherein the plurality of variable levels include a first variable level, a second variable level, a third variable level, and a fourth variable level, and the RF signal transitions from the first variable level to the second variable level, from the second variable level to the third variable level, and from the third variable level to the fourth variable level during the cycle.

44. A method according to claim 42, further comprising identifying the address of the RF generator within one of the one or more Ethernet frames, wherein the extraction comprises obtaining the plurality of variable levels from a field between a field having the address and a field having another address of the other one of the plurality of components.

45. A method according to claim 42, wherein the other one component of the plurality of components includes an impedance matching circuit coupled to the RF generator.

46. A method according to claim 42, wherein each of the plurality of variable levels is a frequency level or a power level.

47. The method according to claim 42, wherein the one or more Ethernet frames are received by a processor, and the method is Receiving one or more Ethernet frames from one of the other components of the plurality of components, Transmitting one or more of the aforementioned Ethernet frames to the processor Methods that further include the above.

48. A method according to claim 42, wherein each of the one or more Ethernet frames has a field for receiving measurement data from the RF generator and a field for supplying the plurality of variable levels to the RF generator.

49. A radio frequency (RF) generator, wherein the RF generator is A communication controller configured to receive one or more Ethernet for Control Automation (EtherCAT) frames, wherein the RF generator is one of several components of a plasma tool, and the communication controller The RF power supply coupled to the aforementioned communication controller and The communication controller is configured to extract multiple variable levels from one or more Ethernet frames, The RF power supply is configured to generate an RF signal having the plurality of variable levels during one cycle of the synchronization signal. The communication controller is configured to identify the destination address of one or more Ethernet frames. The communication controller is an RF generator configured to transmit the one or more Ethernet frames to another component of the plurality of components at the destination address.

50. RF generator according to claim 49, wherein the plurality of variable levels include a first variable level, a second variable level, a third variable level, and a fourth variable level, and the RF signal transitions from the first variable level to the second variable level, from the second variable level to the third variable level, and from the third variable level to the fourth variable level during the cycle.

51. RF generator according to claim 49, wherein the communication controller is configured to identify the address of the RF generator within one of the one or more Ethernet frames, and in order to extract the plurality of variables, the communication controller is configured to obtain the plurality of variable levels from a field between a field having the address and a field having another address of another component of the plurality of components.

52. An RF generator according to claim 49, wherein the other one component of the plurality of components includes an impedance matching circuit coupled to the RF generator.

53. An RF generator according to claim 49, wherein each of the plurality of variable levels is a frequency level or a power level.

54. The RF generator according to claim 49, wherein the one or more Ethernet frames are received by a processor, and the communication controller Receiving one or more Ethernet frames from one of the other components of the plurality of components, The one or more Ethernet frames are transmitted to the processor. An RF generator configured as follows.

55. RF generator according to claim 49, wherein the RF generator includes a processor coupled to the communication controller, and each of the one or more Ethernet frames has a field for receiving data from the processor of the RF generator and a field for supplying the plurality of variable levels to the processor of the RF generator.

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