Design and method of insulated-gate bipolar transistors
The silicon-based IGBT design with narrow mesas and precise alignment addresses the limitations of existing IGBTs by improving conduction modulation and reducing losses, leveraging a high-concentration n-type inversion layer as a hole barrier.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- SEMICON COMPONENTS IND LLC
- Filing Date
- 2025-11-17
- Publication Date
- 2026-06-03
AI Technical Summary
Existing IGBT designs face challenges in reducing on-state and switching losses and increasing current density, especially with the rise of wide-bandgap semiconductors like GaN and SiC, necessitating improvements in silicon-based field-stop insulated-gate bipolar transistors.
A silicon-based IGBT design with narrow mesas and reduced distance between gate and emitter trenches, utilizing a high-concentration n-type inversion layer as a hole barrier, and precise alignment through dry etching to enhance conduction modulation and reduce forward drop.
The design achieves high injection effect and reduced conduction losses by minimizing the distance between trenches, enhancing electron conduction and reducing the forward drop of the IGBT.
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Figure 2026091270000001_ABST
Abstract
Description
[Technical Field]
[0001] High-voltage insulated-gate bipolar transistors (IGBTs) are used in medium to high-power electronic systems such as industrial drives, uninterruptible power supplies (UPS), renewable energy, electric vehicles, and traction motors. Advances in increasing power density have been achieved by reducing on-state and switching losses and increasing current density and maximum junction temperature. As wide-bandgap (WBG) semiconductors such as gallium nitride (GaN) and silicon carbide (SiC) gain prominence in the power semiconductor market, IGBT designs are being considered as a potential competitor to WBG solutions.
[0002] Therefore, those skilled in the art continue their research and development efforts in the field of silicon-based field-stop insulated gate bipolar transistors with narrow mesas. [Overview of the project]
[0003] This specification provides an insulated-gate bipolar transistor (IGBT). The IGBT comprises a plurality of semiconductor layers having a semiconductor surface. A plurality of gate trenches and a plurality of emitter trenches are formed penetrating the semiconductor surface. Trench material is disposed within the trenches. A mesa separates the gate trenches and the emitter trenches. An electrical insulating layer is formed on top of the semiconductor layers. The electrical insulating layer aligns with the mesa and defines a plurality of openings extending across the emitter trenches. The electrical insulating layer does not extend into the emitter trenches. An emitter conductive layer is formed on top of the electrical insulating layer. The emitter conductive layer is in direct contact with the trench material in each of the mesa and each of the emitter trenches. The emitter conductive layer also extends across the emitter trenches.
[0004] The above summary is not intended to represent all embodiments or aspects of the present disclosure. Rather, the above summary exemplifies certain novel embodiments and features described herein. The above and other features and advantages of the present disclosure will be readily apparent from the following "Modes for Carrying Out the Invention" of representative embodiments and aspects for carrying out the present disclosure, in relation to the accompanying drawings and the accompanying "Claims". [Brief explanation of the drawing]
[0005] The drawings described herein are for illustrative purposes only, are schematic in nature, and are intended to be illustrative rather than limiting the scope of this disclosure. [Figure 1] This is a schematic perspective cross-sectional view of an insulated-gate bipolar transistor (IGBT) according to one or more exemplary embodiments. [Figure 2] This is a schematic plan view of another IGBT according to one or more exemplary embodiments. [Figure 3] This is a schematic perspective cross-sectional view of an IGBT having an additional layer according to one or more exemplary embodiments. [Figure 4] This is an electrical schematic diagram of an IGBT according to one or more exemplary embodiments. [Figure 5] This is a schematic perspective cross-sectional view of another IGBT according to one or more exemplary embodiments. [Figure 6] This is a schematic perspective cross-sectional view of yet another IGBT according to one or more exemplary embodiments. [Figure 7] This is a schematic perspective cross-sectional view of yet another IGBT according to one or more exemplary embodiments. [Figure 8] This is a schematic cross-sectional view of a starting semiconductor material for manufacturing an IGBT according to one or more exemplary embodiments. [Figure 9] This is a schematic cross-sectional view of the manufacture of trenches and trench material within an IGBT according to one or more exemplary embodiments. [Figure 10] This is a schematic cross-sectional view of the production of deposits into a mesa within an IGBT according to one or more exemplary embodiments. [Figure 11] This is a schematic cross-sectional view of the fabrication of additional trenches within an IGBT according to one or more exemplary embodiments. [Figure 12] This is a schematic cross-sectional view of the fabrication of an electrical insulating layer and an emitter conductive layer in an IGBT according to one or more exemplary embodiments.
[0006] This disclosure may be modified or embodied in alternative forms, representative embodiments of which are shown in the drawings and described in detail below. The inventive aspects of this disclosure are not limited to the disclosed embodiments. Rather, this disclosure is intended to encompass alternative forms that fall within the scope of this disclosure as defined by the attached "Claims". [Modes for carrying out the invention]
[0007] Embodiments of this disclosure generally provide a design and fabrication method for silicon-based field-stop (FS) insulated-gate bipolar transistors (IGBTs). This design and / or method reduces the distance between the gate trench and the emitter trench formed in the semiconductor substrate. The reduced distance is comparable to the thickness of the inversion layer. The inversion layer also functions as a hole barrier and is a high-concentration n-type (n) + These can exist within the semiconductor. Trenches are separated by very narrow mesas (e.g., spacing of 0.5 micrometers (μm) or less). Contacts to the narrow mesas are provided across the emitter trench. Dry etching with precise alignment can achieve such mesas and contacts. The resulting structure generally achieves high injection effect and high conduction modulation in the IGBT drift region. This structure can also reduce the forward drop of the IGBT.
[0008] Referring to FIG. 1, a schematic perspective cross-sectional view of an exemplary implementation of an insulated gate bipolar transistor (IGBT) 100 according to one or more exemplary embodiments is shown. The IGBT 100 generally includes a plurality of semiconductor layers including at least a first doped layer 102 (or simply "the first layer"), a second doped layer 104 (or simply "the second layer"), and a third doped layer 106 (or simply "the third layer"). A plurality of conductive layers (one is shown) 112 are used to interconnect the features of the IGBT 100.
[0009] In various embodiments, the first doped layer 102 may initially be fabricated as a lightly doped semiconductor layer or an intrinsic semiconductor layer. During subsequent manufacturing steps, the first doped layer 102 may be doped at a low concentration as a p - layer or doped as a p layer. In some embodiments, the first doped layer 102 may be formed as a p-well layer within the second doped layer 104.
[0010] The second doped layer 104 may be a lightly doped n - layer. The second doped layer 104 may provide the drift region of the IGBT 100. In various embodiments, the second doped layer 104 may be formed as an epitaxial layer on the third doped layer 106.
[0011] The third doped layer 106 may be a highly doped n + layer. The third doped layer 106 may initially be a semiconductor wafer. The wafer is generally a silicon wafer.
[0012] The conductive layer 112 may be formed of one or more metals and / or other conductive materials. The conductive layer 112 may include an emitter conductive layer 114. The emitter conductive layer 114 may be a metal (e.g., aluminum, gold, or other conductive metal), a polysilicon layer, or other conductive material.
[0013] A plurality of trenches 116 are formed through the first doped layer 102 into the second doped layer 104 and extend from the semiconductor surface 118 toward the third doped layer 106. Some of the trenches 116 form gate trenches 120 for the gate of the IGBT 100. Other trenches 116 form emitter trenches 122 for the emitter of the IGBT 100. The collector conductive layer 110 and the fourth doped layer 108 (see FIG. 3) can be formed in contact with the third doped layer 106. The collector conductive layer 110 generally forms the collector of the IGBT 100.
[0014] Each trench 116 has an inner wall coated / layered with an electrically insulating coating / layer 124. The electrically insulating coating / layer (or insulating sidewall) 124 can be silicon dioxide (SiO2). The electrically insulating coating / layer 124 electrically isolates between the gate trench 120 and the emitter trench 122 from the surrounding first doped layer 102 and second doped layer 104. Other electrically insulating materials may be used to meet the design criteria of specific applications.
[0015] Each trench 116 is filled with a trench material 126. The trench material 126 can be a conductor, a metal, a doped polysilicon material, etc.
[0016] The combination of the gate trench 120 and the emitter trench 122 forms a mesa 160 therebetween. In various embodiments, each mesa 160 can have a narrow width 162 of 0.5 μm or less. The emitter conductive layer 114 is deposited on the mesa 160 and within additional trenches 140 and extends over the emitter trench 122, so that each mesa 160 is in contact with the emitter conductive layer 114 (e.g., not a "floating" mesa).
[0017] An inclined trench sidewall implantation region 130 is formed within a first doped layer 102 in the mesa 160. The inclined trench sidewall implantation region 130 generally includes a first side surface 132 adjacent to the emitter trench 122. A second side surface 134 of the inclined trench sidewall implantation region 130 is parallel to and can be aligned with the semiconductor surface 118. A third side surface 136 of the inclined trench sidewall implantation region 130 joins the first side surface 132 and the second side surface 134. In various embodiments, the inclined trench sidewall implantation region 130 can be manufactured by ion implantation into the first doped layer 102 of the mesa 160. The resulting inclined trench sidewall implantation region 130 is highly doped with p + It can be injected as a region.
[0018] An additional trench 140 (one is shown) is formed above the emitter trench 122 and extends from the semiconductor surface 118 toward the second doped layer 104. The trench depth 142 of the additional trench 140 may be less than the thickness (or well depth) 144 of the first doped layer 102.
[0019] In various embodiments, an optional ballast resistor 150 may be formed within the first doping layer 102. The ballast resistor 150 generally overlaps the inclined trench sidewall injection region 130. As shown, the ballast contacts 152 of the ballast resistor 150 may be exposed at the trench sidewall of the trench 116. The trench sidewall is the interface between the trench 116 and the adjacent mesa 160. In various embodiments, the ballast resistor 150 may extend beyond the inclined trench sidewall injection region 130 toward the gate trench 120. In some embodiments, the ballast resistor 150 may be manufactured by ion implantation into the first doping layer 102 and the inclined trench sidewall injection region 130 via the semiconductor surface 118. In other embodiments, the ballast resistor 150 may be manufactured by diffusion into the first doping layer 102. The resulting ballast resistor 150 is highly doped n + It can be injected as a region. Therefore, when viewed from top to bottom in the figure, p +n overlapping the region (e.g., 130) + may include the structure of the region (e.g., 150).
[0020] Ballast contacts 152 are formed at both ends of each ballast resistor 150. The ballast contacts 152 are also manufactured by ion implantation or diffusion into the inclined trench sidewall implantation region 130 through the semiconductor surface 118. The ballast contacts 152 can be implemented as highly doped n + regions. In some designs, the ballast contacts 152 extend (left and right as shown) through the inclined trench sidewall implantation region 130 and are exposed into additional trenches 140 at the sidewalls of the mesa 160. In other designs, the ballast contacts 152 do not extend to the trench sidewall additional trenches 140.
[0021] To aid in understanding the structure of the IGBT 100, a portion of the device as seen along arrow 154 on the semiconductor surface 118 is shown on the right side of the figure. According to the arrow 154 from right to left in the figure, it is shown that the emitter conductive layer 114 abuts against the first side surface 132 of the inclined trench sidewall implantation region 130 and the ballast contacts 152. The ballast resistor 150 is seen between the inclined trench sidewall implantation region 130 and an electrical insulation coating / layer 124 (e.g., gate oxide) adjacent to the trench material 126 (e.g., gate polysilicon material).
[0022] Referring to FIG. 2, a schematic plan view of an exemplary implementation of another IGBT 100a according to one or more exemplary embodiments is shown. The IGBT 100a can be a variant of the IGBT 100. The figure shows a design where the trenches alternate between gate trenches 120 and emitter trenches 122. In other designs, the order of the trenches can be, for example, gate trench 120, emitter trench 122, emitter trench 122, gate trench, emitter trench 122, etc. Other orders and numbers of trenches may be implemented to meet the design criteria for specific applications.
[0023] The mesa 160 may include a broad section 170 and a narrow section 172. The narrow section 172 may have a width of 0.5 μm or less. The broad section 170 may have a width of approximately 0.7 to 1.0 μm. Broad sections 170 of other dimensions may be implemented to meet the design criteria for a particular application.
[0024] The emitter conductive layer 114 is created on each mesa 160. The width 174 of the emitter conductive layer 114 can be consistent across the mesa 160.
[0025] In various embodiments, the emitter conductive layer 114 does not overlap with the electrical insulating coating / layer 124 (as shown in Figure 2). Therefore, n + Region 176 may be located within a broad portion 170 between the emitter conductive layer 114 and the electrical insulating coating / layer 124.
[0026] Referring to Figure 3, schematic perspective cross-sectional views of an insulated gate bipolar transistor 100 having an additional layer are shown according to one or more exemplary embodiments. A fourth doping layer 108 (or abbreviated as "the fourth layer") may be deposited or formed on the back surface of the third doping layer 106. The fourth doping layer 108 may be created by either deposition or injection. The fourth doping layer 108 is highly doped with p + It could be a layer.
[0027] The collector conductive layer 110 is formed in contact with the fourth dope layer 108. The collector conductive layer 110 is generally a metal (e.g., aluminum, gold, or other conductive metal), a polysilicon layer, or another conductive material. The collector conductive layer 110 forms the collector node of the IGBT 100.
[0028] The electrical insulation layer 180 is formed on the gate trench 120 from an insulator such as borophosphosilicate glass (BPSG) or thick silicon dioxide. Other electrical insulation materials may be used to meet the design criteria of a particular application. In various embodiments, the electrical insulation layer 180 may extend over the gate trench 120 and partially or completely over the first doped layer 102 to (but not into) the edge of an additional trench 140 (as shown).
[0029] A drift region 182 exists within a second doped layer 104 between the gate trench 120 and the emitter trench 122. An electrically insulating coating / layer 124 adjacent to the gate trench 120 within the first doped layer 102 functions as the gate oxide 184. While the gate is positively biased, an inversion layer forms near the gate oxide 184 within the first doped layer 102. The inversion layer acts as a barrier to holes and enhances conduction modulation of electrons within the drift region 182. Thus, the insulated gate bipolar transistor 100 is characterized by the absence of a hole storage region below the first doped well layer 102 within the mesa 160. Electrons are introduced into the drift region 182 from the collector conductive layer 110. The plasma concentration below trench 116 is generally higher in the case of a narrow mesa (e.g., <0.5 μm) design than in the case of a wider mesa (e.g., >0.7 μm) design during the transistor's ON state, thereby reducing conduction losses.
[0030] Referring to Figure 4, an electrical schematic diagram of an IGBT 100 according to one or more exemplary embodiments is shown. A first (PNP) transistor 190 and a series resistor 192(Ra) are formed by layers 102-108 between the collector conductive layer 110 and the emitter conductive layer 114. A second (NPN) transistor 194 and a ballast resistor 150 are formed between the base of the first transistor 190 and the emitter conductive layer 114 (the emitter node of the IGBT). The base of the second transistor 194 is connected to the collector of the first transistor 190. A third metal oxide semiconductor (MOS) transistor 196 is formed between the ballast resistor 150 and the base of the first transistor 190. The gate of the third transistor 196 is the gate node 115 of the IGBT 100.
[0031] Referring to Figure 5, schematic perspective cross-sectional views of exemplary mounting configurations of IGBT100b according to one or more exemplary embodiments are shown. IGBT100b may be a variation of IGBT100 shown in Figure 1 and / or IGBT100a shown in Figure 2. IGBT100b generally represents a first ballast resistor contact option.
[0032] The electrical insulating layer 180 of the IGBT 100b is etched to open vias 198 (or additional openings) to ballast contacts 150a at one end of the ballast resistor 152, in order to provide electrical contacts to the emitter conductive layer 114 (see Figure 1) along the semiconductor surface 118. The other ballast contact 152b at the other end of the ballast resistor 150 is embedded beneath the electrical insulating layer 180 and provides electrical contacts to the first doping layer 102. The size of the ballast contact 152a generally does not extend to the trench sidewalls of the additional trench 140.
[0033] Referring to Figure 6, schematic perspective cross-sectional views of exemplary mounting configurations of an insulated-gate bipolar transistor (IGBT) 100c according to one or more exemplary embodiments are shown. IGBT100c may be a variation of IGBT100, IGBT100a, and / or IGBT100b. IGBT100c generally exhibits a second ballast resistor contact option.
[0034] The electrical insulating layer 180 of the IGBT100c is etched to open vias / additional openings 198 to ballast contacts 152c at one end of the ballast resistor 150, in order to provide electrical contacts to the emitter conductive layer 114 (see Figure 1) located along the semiconductor surface 118 and on the first side 132 of the inclined trench sidewall injection region 130. The other ballast contact 152b at the other end of the ballast resistor 150 is embedded beneath the electrical insulating layer 180 and provides electrical contacts to the first doping layer 102. The size of the ballast contacts 152c generally extends to the trench sidewall of the additional trench 140.
[0035] Referring to Figure 7, schematic perspective cross-sectional views of exemplary mounting configurations of an insulated-gate bipolar transistor (IGBT) 100d according to one or more exemplary embodiments are shown. IGBT100d may be a variation of IGBT100, IGBT100a, IGBT100b, and / or IGBT100c. IGBT100d generally exhibits a third ballast resistor contact option.
[0036] The electrical insulation layer 180 of the IGBT 100d covers the ballast contact 152d outside the additional trench 140 at one end of the ballast resistor 150. The emitter conductive layer 114 (see Figure 1) directly contacts the ballast contact 152d at the first side surface 132 of the inclined trench sidewall injection region 130. The other ballast contact 152b at the other end of the ballast resistor 150 is embedded beneath the electrical insulation layer 180 and provides an electrical contact to the first doping layer 102.
[0037] Referring to Figures 8 to 12, schematic cross-sectional views of exemplary methods for manufacturing IGBT 100 according to one or more exemplary embodiments are shown. The order of steps is shown as a typical example. Other step sequences may be implemented to meet the criteria of a particular application.
[0038] Referring to Figure 8, schematic cross-sectional views of starting semiconductor materials for manufacturing IGBT100 according to one or more exemplary embodiments are shown.
[0039] The doped layers 102, 104, and 106 are initially formed in a stacked / layered configuration, and the oxide mask layer 200 is bonded to the first doped layer 102 on the semiconductor surface 118. The first doped layer 102 is p - It may not start as a semiconductor layer, however, if doped at a low concentration of p - The layer may be modified later in the manufacturing process to become a semiconductor layer or a p-doped semiconductor layer. Subsequently, the oxide mask layer 200 is patterned to form vias 202 on the trench 116 (see Figure 9).
[0040] Referring to Figure 9, schematic cross-sectional views of IGBTs having trenches and trench material are shown according to one or more exemplary embodiments.
[0041] Trench 116 is formed by etching through a pattern in the oxide mask layer 200 (Figure 8) into the first doped layer 102. Etching can be achieved by dry etching with precise alignment to create a narrow mesa. The oxide mask layer 200 can then be removed and an electrical insulating coating / layer 124 can be grown. Trench material 126 is then deposited to fill the trench 116.
[0042] Referring to Figure 10, schematic cross-sectional views of sediments within a mesa are shown according to one or more exemplary embodiments.
[0043] After the excess trench material 126 is removed, inclined trench sidewall injection regions 130, optional ballast resistors 150, and optional ballast contacts 152 can be formed on the mesa 160. In various embodiments, the ballast resistors 150 and ballast contacts 152 can be formed using ion implantation or diffusion via the semiconductor surface 118. In embodiments without ballast resistors 150, a contact layer 153 (see Figure 11) can be formed on the mesa 160. The contact layer 153 is n + It may be a layer. Subsequently, a mask is placed over the n-doped area, and the inclined trench sidewall implantation region 130 is manufactured using ion implantation to achieve the inclined third side surface 136. In other embodiments, the inclined trench sidewall implantation region 130 is manufactured first. Subsequently, a mask is placed over the inclined trench sidewall implantation region 130, and then n + High doses of phosphorus or arsenic are used to create the ballast resistor 150 and ballast contact 152, or n + A contact layer 153 is created.
[0044] Referring to Figure 11, schematic cross-sectional views of additional trenches according to one or more exemplary embodiments are shown. Figure 11 generally shows n + This shows an implementation configuration that has a contact layer 153 but does not have a ballast resistor 150 and ballast contacts 152. + Contact layer 153 and p + The inclined trench sidewall injection region 130 contacts the emitter conductive layer 114 (see Figure 12) through the inside 141 of an additional trench 140. In various embodiments, n + The upper side of the contact layer 153 may be covered with an insulator (not shown).
[0045] A mask can be used to define additional trenches 140 aligned with the emitter trench 122. Dry etching can be used to remove a portion of the trench material 126 from the emitter trench 122. The additional trenches 140 may be located below the semiconductor surface 118 to a trench depth 142 (see Figure 1). The trench depth 142 of each additional trench 140 is shallower than the well depth 144 of the first doped p-well layer 102. The trench material 126 within the gate trench 120 may not be altered by the formation of the additional trenches 140.
[0046] Referring to Figure 12, schematic cross-sectional views of an electrical insulating layer and an emitter conductive layer according to one or more exemplary embodiments are shown.
[0047] An electrical insulating layer 180 (see Figure 1) is generally formed on the semiconductor surface 118. In some embodiments, the electrical insulating layer 180 can be patterned to create an opening 204a above the mesa 160, thereby allowing full contact of the emitter conductive layer 114 along the mesa 160 (see Figure 2). In other embodiments, the electrical insulating layer 180 can be patterned to create an opening 204b above the mesa 160 and an additional trench 140, thereby allowing contact of the emitter conductive layer 114 along the mesa 160 and the first side surface 132 of the inclined trench sidewall injection region 130. Such an emitter conductive layer 114 extends across the emitter trench 122. In yet another embodiment, the electrical insulating layer 180 can be patterned to open above an additional trench 140 and a portion of the mesa 160. In such embodiments, the inclined trench sidewall injection area 130 and the ballast resistor 150 may be covered by an electrical insulating layer 180, and contact with the inclined trench sidewall injection area 130 and the ballast resistor 150 is achieved through the inner wall of an additional trench 140.
[0048] Clause 1: An insulated gate bipolar transistor comprising: a plurality of semiconductor layers having (i) a semiconductor surface and (ii) a plurality of gate trenches and a plurality of emitter trenches separated by a plurality of mesas formed through the semiconductor surface; trench material disposed within the plurality of emitter trenches; an electrical insulating layer formed on the plurality of semiconductor layers, wherein (i) the electrical insulating layer aligns with the plurality of mesas and defines a plurality of openings extending across the plurality of emitter trenches, and (ii) the electrical insulating layer does not extend into the plurality of emitter trenches; and an emitter conductive layer formed on the electrical insulating layer, wherein the emitter conductive layer directly contacts (i) the trench material in each of the plurality of mesas and (ii) the trench material in each of the plurality of emitter trenches through a plurality of openings and extends across the plurality of emitter trenches.
[0049] Clause 2: The insulated gate bipolar transistor according to Clause 1, further comprising: a first doping layer formed on each of a plurality of mesas, penetrating the semiconductor surface; and a second doping layer formed overlapping each of the first doping layers, wherein the emitter conductive layer is in direct contact with each of the first and second doping layers on the plurality of mesas through a plurality of openings.
[0050] Clause 3: The insulated gate bipolar transistor according to Clause 2, further comprising: a plurality of insulating sidewalls around a plurality of emitter trenches; and a plurality of inclined trench sidewall injection regions formed (i) through the semiconductor surface into a first doped layer and (ii) adjacent to the plurality of insulating sidewalls.
[0051] Clause 4: An insulated gate bipolar transistor according to any one of Clauses 1 to 3, wherein the multiple semiconductor layers include a well layer having a well depth and a plurality of additional trenches formed through the semiconductor surface into the well layer and aligned with a plurality of emitter trenches.
[0052] Clause 5: The insulated gate bipolar transistor described in Clause 4, wherein the trench depth of each of the multiple additional trenches is shallower than the well depth of the well layer, and the multiple additional trenches expose multiple first side walls of multiple inclined trench side wall injection regions.
[0053] Clause 6: The insulated gate bipolar transistor according to Clause 5, wherein the emitter conductive layer is in direct contact with multiple first sidewalls of multiple inclined trench sidewall injection regions through multiple additional openings.
[0054] Clause 7: The insulated gate bipolar transistor according to Clause 6, further comprising a plurality of ballast resistors formed in a second dope layer of a plurality of mesa, wherein the plurality of ballast resistors include a plurality of ballast contacts formed in a plurality of inclined trench sidewall injection regions, the plurality of ballast contacts being isolated from a plurality of first sidewalls of the plurality of inclined trench sidewall injection regions, and the emitter conductive layer being in direct contact with the plurality of ballast contacts through a plurality of openings.
[0055] Clause 8: The insulated gate bipolar transistor according to Clause 6, further comprising a plurality of ballast resistors formed in a second dope layer of a plurality of mesa, wherein the plurality of ballast resistors include a plurality of ballast contacts formed in a plurality of inclined trench sidewall injection regions, the plurality of ballast contacts being exposed at a plurality of first sidewalls of the plurality of inclined trench sidewall injection regions, and the emitter conductive layer being in direct contact with the plurality of ballast contacts at the plurality of first sidewalls through a plurality of openings.
[0056] Clause 9: The insulated gate bipolar transistor according to Clause 6, further comprising a plurality of ballast resistors formed in a second dope layer of a plurality of mesa, wherein the plurality of ballast resistors include a plurality of ballast contacts formed in a plurality of inclined trench sidewall injection regions, the plurality of ballast contacts being exposed at a plurality of first sidewalls of the plurality of inclined trench sidewall injection regions, an electrical insulating layer covering the plurality of ballast contacts outside the plurality of additional trenches, and an emitter conductive layer in direct contact with the plurality of ballast contacts at the plurality of first sidewalls.
[0057] Clause 10: An insulated gate bipolar transistor as described in Clause 9, wherein the emitter conductive layer directly connects multiple inclined trench sidewall injection regions to multiple ballast contacts.
[0058] Clause 11: An insulated gate bipolar transistor as described in Clause 9, wherein a subset of multiple ballast contacts is electrically connected to a first doping layer.
[0059] Clause 12: An insulated-gate bipolar transistor as described in Clause 4, characterized by the absence of multiple hole storage regions beneath the well layers in multiple mesas.
[0060] Clause 13: An insulated gate bipolar transistor as described in any of Clauses 1 to 3, wherein the width of each of the multiple mesas is 0.5 micrometers or less.
[0061] Clause 14: An insulated gate bipolar transistor comprising: a plurality of semiconductor layers having (i) a semiconductor surface and (ii) a plurality of gate trenches and a plurality of emitter trenches separated by a plurality of mesas formed through the semiconductor surface; trench material disposed within the plurality of emitter trenches; a first doping layer formed on each of the plurality of mesas through the semiconductor surface; a second doping layer formed overlapping each of the first doping layers; an electrical insulating layer formed on the plurality of semiconductor layers, wherein (i) the electrical insulating layer aligns with the plurality of mesas and defines a plurality of openings extending across the plurality of emitter trenches, and (ii) the electrical insulating layer does not extend into the plurality of emitter trenches; and an emitter conductive layer formed on the electrical insulating layer, wherein the emitter conductive layer directly contacts (i) each of the second doping layers and (ii) the trench material in each of the plurality of emitter trenches through a plurality of openings.
[0062] Clause 15: The insulated gate bipolar transistor according to Clause 14, further comprising: a plurality of insulating sidewalls around a plurality of emitter trenches; and a plurality of inclined trench sidewall injection regions formed (i) through the semiconductor surface into a first doped layer and (ii) adjacent to the plurality of insulating sidewalls.
[0063] Clause 16: An insulated gate bipolar transistor according to Clause 14 or 15, wherein the plurality of semiconductor layers include a well layer having a well depth and a plurality of additional trenches formed through the semiconductor surface into the well layer and aligned with a plurality of emitter trenches.
[0064] Clause 17: The insulated gate bipolar transistor described in Clause 16, wherein the trench depth of each of the multiple additional trenches is shallower than the well depth of the well layer, and the multiple additional trenches expose multiple first sidewalls of multiple inclined trench sidewall injection regions.
[0065] Clause 18: The insulated gate bipolar transistor according to Clause 17, wherein the emitter conductive layer is in direct contact with a plurality of first sidewalls of a plurality of inclined trench sidewall injection regions through a plurality of openings.
[0066] Clause 19: An insulated gate bipolar transistor as described in paragraph 14 or 15, wherein the width of each of the multiple mesas is 0.5 micrometers or less.
[0067] Clause 20: A method for manufacturing an insulated gate bipolar transistor, comprising: forming a plurality of semiconductor layers having semiconductor surfaces; forming a plurality of gate trenches and a plurality of emitter trenches separated by a plurality of mesas through the semiconductor surfaces of the plurality of semiconductor layers; filling the plurality of emitter trenches with trench material; forming an electrical insulating layer on the plurality of semiconductor layers, wherein the electrical insulating layer is formed to (i) define a plurality of openings aligned with the plurality of mesas and extending across the plurality of emitter trenches, and (ii) not extending into the plurality of emitter trenches; and forming an emitter conductive layer on the electrical insulating layer, wherein the emitter conductive layer is formed to extend across the plurality of emitter trenches and to (i) directly contact the trench material in each of the plurality of mesas and (ii) in each of the plurality of emitter trenches through a plurality of openings.
[0068] These and other advantages of this teaching will be readily apparent to those skilled in the art who have the advantages of the aforementioned disclosure. While several modes for carrying out many aspects of this teaching have been described in detail, those skilled in the art who relate to these teachings will recognize various alternative modes for carrying out this teaching, which are contained in the attached "Claims." The above description and accompanying drawings are examples and illustrations of the entire scope of alternative embodiments that those skilled in the art will recognize as being structurally and / or functionally equivalent based on the content included, or as implied by otherwise being revealed, and are not limited to the embodiments explicitly shown and / or described. Furthermore, this concept explicitly includes combinations and partial combinations of the elements and features described. The "Modes for Carrying Out the Invention" and drawings supplement and illustrate this teaching, and the scope of this teaching is defined solely by the "Claims."
Claims
1. (i) a semiconductor surface, and (ii) a plurality of gate trenches and a plurality of emitter trenches separated by a plurality of mesas formed through the semiconductor surface, The trench material disposed within the plurality of emitter trenches, An electrical insulating layer formed on the plurality of semiconductor layers, wherein (i) it defines a plurality of openings aligned with the plurality of mesas and extending across the plurality of emitter trenches, and (ii) it does not extend into the plurality of emitter trenches, An emitter conductive layer formed on the aforementioned electrical insulating layer, Through the plurality of openings, (i) the trench material in each of the plurality of mesa and (ii) the trench material in each of the plurality of emitter trenches, An emitter conductive layer extending across the plurality of emitter trenches, An insulated gate bipolar transistor equipped with [a specific feature].
2. A first doped layer is formed on each of the plurality of mesas, penetrating the semiconductor surface, The emitter conductive layer further comprises a second doping layer formed overlapping each of the first doping layers, wherein the emitter conductive layer is in direct contact with each of the first doping layers and the second doping layers on the plurality of mesas through the plurality of openings. The insulated gate bipolar transistor according to claim 1.
3. Multiple insulating side walls around the multiple emitter trenches, (i) A plurality of inclined trench sidewall injection regions are formed by passing through the semiconductor surface into the first dope layer and (ii) adjacent to the plurality of insulating sidewalls, The insulated bipolar transistor according to claim 2, further comprising the above.
4. The plurality of semiconductor layers are A well layer having well depth, A plurality of additional trenches are formed in the well layer, penetrating the semiconductor surface and aligned with the plurality of emitter trenches, The insulated gate bipolar transistor according to claim 3, including the following:
5. The trench depth of each of the aforementioned additional trenches is shallower than the well depth of the well layer. The insulated gate bipolar transistor according to claim 4, wherein the plurality of additional trenches expose the plurality of first side walls of the plurality of inclined trench side wall injection regions.