Capacitor structure and method for manufacturing the same

Abstract

The present invention provides a semiconductor device and a method for manufacturing the same that improve the electrical performance of a capacitor structure. [Solution] The capacitor structure 10 includes a lower electrode 140, an insulating layer 150, an upper electrode 170, and an interface layer 160. The insulating layer is placed on the lower electrode. The upper electrode is placed on top of the insulating layer. The interface layer is placed between the insulating layer and the upper electrode. The composition of the interface layer includes at least one element common to the elements contained in the insulating layer and at least one element common to the elements contained in the upper electrode.

Description

Technical Field

[0001] The present invention relates to a semiconductor device, and particularly to a capacitor structure and a manufacturing method thereof in a semiconductor device.

Background Art

[0002] In semiconductor devices such as dynamic random-access memory (DRAM), a high capacitance is required for data storage and reading. As the shrinking requirements of semiconductor devices increase, the aspect ratio of the capacitor structure becomes high, which affects the step coverage rate of the upper electrode of the capacitor structure, and thereby the capacitance of the capacitor structure may decrease.

Summary of the Invention

Problems to be Solved by the Invention

[0003] The aspect ratio of the capacitor structure becomes high, which affects the step coverage rate of the upper electrode of the capacitor structure, and thereby the capacitance of the capacitor structure may decrease.

Means for Solving the Problems

[0004] The capacitor structure of the present invention includes a lower electrode, an insulating layer, an upper electrode, and an interface layer. The insulating layer is disposed on the lower electrode. The upper electrode is disposed on the insulating layer. The interface layer is disposed between the insulating layer and the upper electrode. The composition of the interface layer has at least one element common to the elements contained in the insulating layer and at least one element common to the elements contained in the upper electrode.

[0005] In one embodiment of the capacitor structure of the present invention, the material of the interface layer is TiO x N y including, where 0 < x ≦ 1 and x + y = 1.

[0006] In one embodiment of the capacitor structure of the present invention, the oxygen concentration in the interfacial layer is higher than the oxygen concentration in the upper electrode.

[0007] In one embodiment of the capacitor structure of the present invention, the nitrogen concentration in the interfacial layer is lower than the nitrogen concentration in the upper electrode.

[0008] In one embodiment of the capacitor structure of the present invention, the interface layer includes a first interface layer and a second interface layer. The first interface layer is disposed between the insulating layer and the upper electrode. The second interface layer is disposed between the first interface layer and the upper electrode. The oxygen concentration of the first interface layer is higher than that of the second interface layer.

[0009] In one embodiment of the capacitor structure of the present invention, the nitrogen concentration in the first interface layer is lower than the nitrogen concentration in the second interface layer.

[0010] In one embodiment of the capacitor structure of the present invention, the thickness of the interface layer is 1 to 30 angstroms.

[0011] In one embodiment of the capacitor structure of the present invention, the materials for the upper and lower electrodes include TiN, and the material for the insulating layer includes a high dielectric constant dielectric material.

[0012] In one embodiment of the capacitor structure of the present invention, the lower electrode is doped with Si.

[0013] In one embodiment of the capacitor structure of the present invention, the insulating layer comprises hafnium oxide, aluminum oxide, zirconium oxide, silicon oxide, lanthanum oxide, or magnesium oxide.

[0014] The method for manufacturing the capacitor structure of the present invention includes the following steps: forming a lower electrode; forming an insulating layer on the lower electrode; forming an interface layer on the insulating layer; and forming an upper electrode on the interface layer. The composition of the interface layer includes at least one element common to the elements contained in the insulating layer and at least one element common to the elements contained in the upper electrode.

[0015] In one embodiment of the manufacturing method for the capacitor structure of the present invention, the interface layer is formed by atomic layer deposition, and the interface layer and the upper electrode share the common element N.

[0016] In one embodiment of the method for manufacturing the capacitor structure of the present invention, the nitrogen concentration in the interfacial layer is lower than the nitrogen concentration in the upper electrode.

[0017] In one embodiment of the method for manufacturing the capacitor structure of the present invention, forming an interface layer includes the following steps: A first interface layer is formed on an insulating layer. A second interface layer is formed on the first interface layer. The oxygen concentration of the first interface layer is higher than the oxygen concentration of the second interface layer.

[0018] In one embodiment of the method for manufacturing the capacitor structure of the present invention, forming the lower electrode and the insulating layer includes the following steps: A laminated structure is formed on a substrate. The laminated structure includes alternately stacked support layers and sacrificial layers. An opening is formed through the laminated structure. The lower electrode is deposited on the side wall of the opening and on a portion of the substrate exposed by the opening. The sacrificial layer of the laminated structure is removed to expose the lower electrode and a portion of the support layer. The insulating layer is deposited on the exposed surfaces of the lower electrode and the support layer. [Effects of the Invention]

[0019] Based on the above, the capacitor structure of the present invention includes an interface layer between the insulating layer and the upper electrode, which can improve the step coverage of the upper electrode and thereby improve the electrical performance of the capacitor structure.

[0020] To make the above content easier to understand, several embodiments, accompanied by drawings, are described in detail below. [Brief explanation of the drawing]

[0021] The accompanying drawings are included to provide a further understanding of the present disclosure, are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure. [Figure 1] It is a schematic diagram of a method for manufacturing a capacitor structure according to an embodiment of the present invention. [Figure 2] It is a schematic diagram of a method for manufacturing a capacitor structure according to an embodiment of the present invention. [Figure 3] It is a schematic diagram of a method for manufacturing a capacitor structure according to an embodiment of the present invention. [Figure 4] It is a schematic diagram of a method for manufacturing a capacitor structure according to an embodiment of the present invention. [Figure 5A] It is a schematic diagram of a method for manufacturing a capacitor structure according to an embodiment of the present invention. [Figure 5B] It is a schematic diagram of a method for manufacturing a capacitor structure according to an embodiment of the present invention. [Figure 6A] It is a schematic diagram of a method for manufacturing a capacitor structure according to an embodiment of the present invention. [Figure 6B] It is a schematic diagram of a method for manufacturing a capacitor structure according to an embodiment of the present invention. [Figure 7A] It is a schematic diagram of a method for manufacturing a capacitor structure according to an embodiment of the present invention. [Figure 7B] It is a schematic diagram of a method for manufacturing a capacitor structure according to an embodiment of the present invention. [Figure 8] It is a schematic diagram of a method for manufacturing a capacitor structure according to an embodiment of the present invention. [Figure 9] It is a schematic diagram of a method for manufacturing a capacitor structure according to an embodiment of the present invention. [Figure 10] It is a schematic diagram of a method for manufacturing a capacitor structure according to an embodiment of the present invention. [Figure 11] It is a schematic diagram of a method for manufacturing a capacitor structure according to an embodiment of the present invention. [Figure 12] It is a schematic cross-sectional view of a capacitor structure according to another embodiment of the present invention. [Modes for carrying out the invention]

[0022] The embodiments will be described in detail below with reference to the attached drawings, but these embodiments do not limit the scope of the present invention. Furthermore, the drawings are for illustrative purposes only and are not depicted in actual dimensions. For ease of understanding, identical elements will be denoted by the same reference numerals in the following description.

[0023] The terms "include," "equip," "contain," and "possess" mentioned in the text are all open-ended terms, meaning "include, but not limited to."

[0024] When terms such as "first" and "second" are used to describe the components, they are used solely to distinguish between the components and do not limit the order or importance of the device. Therefore, in some cases, the first element may be called the second element, and the second element may be called the first element, but this does not exceed the scope of the present invention.

[0025] Furthermore, terms indicating direction, such as "up," "top," "down," and "bottom," as described in the specification are used solely to indicate the direction in the drawings and are not intended to limit the present invention.

[0026] Furthermore, in this specification, the range expressed as "from one value to another" is a general expression used to avoid listing all values ​​within the scope of the specification. Therefore, the description of a particular numerical range includes any number within that range, and smaller numerical ranges limited by any number within that range.

[0027] Figures 1 to 4, 5A, 6A, 7A, and 8 to 11 are schematic cross-sectional views of a method for manufacturing a capacitor structure according to one embodiment of the present invention. Figure 5B is a schematic top view of Figure 5A, and Figure 5A is shown along the cutting line A-A' of Figure 5B. Figure 6B is a schematic top view of Figure 6A, and Figure 6A is shown along the cutting line B-B' of Figure 6B. Figure 7B is a schematic top view of Figure 7A, and Figure 7A is shown along the cutting line C-C' of Figure 7B.

[0028] Referring to Figures 1 to 3, a laminated structure 110 is formed on a substrate 100. The laminated structure 110 includes alternately stacked support layers 112 (including a first support layer 112a, a second support layer 112b, and a third support layer 112c) and sacrificial layers 144 (including a first sacrificial layer 114A and a second sacrificial layer 114b) on the substrate 100. For example, in Figure 1, the first support layer 112a, the first sacrificial layer 114A, and the second support layer 112b are formed in order on the substrate 100. Then, in Figure 2, a first opening OP1 is formed in the second support layer 112b, exposing the first sacrificial layer 114a below it. In some embodiments, the first opening OP1 is formed by an etching process that removes a portion of the second support layer 112b. In some embodiments, a portion of the first sacrificial layer 114 may be removed during the etching process. In some embodiments, the etching process may be, but is not limited to, a wet etching or a dry etching process. In Figure 3, the second sacrificial layer 114b and the third sacrificial layer 112c are formed sequentially on the second support layer 112b. In some embodiments, the second sacrificial layer 114b extends into the first opening OP1 and is in direct contact with the first sacrificial layer 114a. In other embodiments, the first opening OP1 may not be formed during the formation of the laminated structure 110.

[0029] In some embodiments, the support layer 112 (including the first support layer 112a, the second support layer 112b, and the third support layer 112c) and the sacrificial layer 144 (including the first sacrificial layer 114A and the second sacrificial layer 114b) may be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), or other suitable methods, but are not limited thereto. In some embodiments, the material of the support layer 112 includes nitrides or other suitable materials. In some embodiments, the material of the sacrificial layer 144 includes oxides or other suitable materials.

[0030] In some embodiments, the substrate 100 includes a landing pad 102 and a transistor (not shown) electrically connected to the corresponding landing pad 102. In some embodiments, the material of the landing pad 102 includes copper, aluminum, tungsten, gold, silver, an alloy of the aforementioned materials, or other suitable conductive material. In some embodiments, the substrate 100 further includes a drive circuit (bit lines, word lines, etc.) (not shown) electrically connected to the transistor.

[0031] Referring to Figure 4, a hard mask layer 120 is formed on the laminated structure 110 by chemical vapor deposition (CVD), physical vapor deposition (PVD), or other suitable method. A patterned photoresist layer 130 is then formed on the hard mask layer 120, defining the position of the second opening to be formed thereafter. For example, a photoresist material layer (not shown) is formed on the hard mask layer 120 by spin coating, slit coating, slit spin coating, or other suitable method. Then, using a photomask with a designed pattern, an exposure process is performed on the photoresist material layer to form the patterned photoresist layer 130.

[0032] Referring to Figures 5A and 5B, a second opening OP2 is formed through the laminated structure 100, exposing the grounding pad 102. For example, the hard mask layer 120 is patterned using the patterned photoresist layer 120 as an etching mask, and the pattern of the patterned photoresist layer 130 is transferred to the hard mask layer 120. The photoresist layer 130 is then removed by an ashing process, an etching process, or other suitable method. Subsequently, one or more etching processes are performed using the patterned hard mask layer 120 as an etching mask, and a portion of the laminated structure 110 is removed until the grounding pad 102 is exposed, thereby forming the second opening OP2 in the laminated structure 110. Next, the hard mask layer 102 is removed.

[0033] Referring to Figures 6A and 6B, the lower electrode 140 is formed on the laminated structure 110. For example, the conductive layer is deposited on the upper surface of the laminated structure 110, the sidewall of the second opening OP2, and a portion of the substrate 100 exposed by the second opening OP2 (i.e., the grounding pad 102). In some embodiments, the conductive layer is formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), electroplating, or other suitable method. In some embodiments, the conductive layer or lower electrode 140 is conformally formed on the laminated structure 110. A planarization process is then performed until the upper surface of the laminated structure 110 is exposed, thereby forming the lower electrode 140. That is, a portion of the conductive layer formed on the third support layer 112c is removed during the planarization process. In some embodiments, the planarization process includes chemical mechanical polishing, mechanical grinding, or other suitable treatment.

[0034] In some embodiments, the material of the conductive layer or the lower electrode 140 includes titanium nitride (TiN). In some embodiments, the lower electrode 140 is doped with silicon (Si) to increase the hardness of the lower electrode 140 and reduce the likelihood of etching during the subsequent removal process of the sacrificial layer 114. In embodiments in which the lower electrode 140 is doped with silicon, the lower electrode 140 may include titanium silicon nitride (TiSiN). However, the material of the lower electrode 140 is not limited in the present invention. In other embodiments, the material of the conductive layer may include a metal (such as copper (Cu), tungsten (W), gold (Au), silver (Ag), titanium (Ti), aluminum (Al)) or other suitable conductive material.

[0035] In some embodiments, the thickness of the lower electrode 140 is 2 nm to 10 nm, but is not limited to this.

[0036] Referring to Figures 7A and 7B, a portion of the third support layer 112c is removed to form a third opening OP3 in the third support layer 112c, exposing the second sacrificial layer 114b beneath it. In some embodiments, the third opening OP3 is formed by an etching process that removes a portion of the third support layer 112c. In some embodiments, a portion of the second sacrificial layer 114b and a portion of the lower electrode 140 are removed during the etching process. In some embodiments, the orthogonal projection of the third opening OP3 on the substrate 100 overlaps with the orthogonal projection of the first opening OP1 on the substrate 100. In some embodiments, the first opening OP1 and the third opening OP3 are located between an adjacent second opening OP2.

[0037] Referring to Figure 8, the sacrificial layer 114 is removed by an etching process that selectively etches the sacrificial layer 114, but does not etch the support layer 112 and the lower electrode 140, or etches them very little. Since the second sacrificial layer 114b is exposed by the third opening OP3 and the first opening OP1 is formed in the second support layer 112b, the first sacrificial layer 114A and the second sacrificial layer 114b can be removed in the same process.

[0038] In embodiments where the first opening OP1 is not formed during the formation of the laminated structure 110, the first sacrificial layer 114a and the second sacrificial layer 114b may be removed by different process steps. For example, a first etching step may be performed to remove the second sacrificial layer 114b. Then, after removing the second sacrificial layer 114b, the first opening OP1 may be formed in the second support layer 112b. Subsequently, a second etching step may be performed to remove the first sacrificial layer 114a.

[0039] After the sacrificial layer 114 is removed, the space between adjacent support layers 112 is opened, and a portion of the outer surface S2 of the lower electrode 140 is exposed. The outer surface S2 is on the side facing the inner surface S1, and the outer surface S2 is directly connected to the support layer 112 and the grounding pad 102. Also, after the sacrificial layer 114 is removed, the support layer 112 (including the first support layer 112a, the second support layer 112b, and the third support layer 112c) is exposed.

[0040] Referring to Figure 9, the insulating layer 150 is formed on the lower electrode 140. For example, the insulating layer 150 is formed by the ALD method or other suitable method. In some embodiments, the insulating layer 150 is conformally formed on the substrate 100 and is positioned on the exposed surfaces of the lower electrode 140 (such as the inner surface S1 and outer surface S2) and the exposed surfaces of the support layer 112.

[0041] In some embodiments, the insulating layer 150 includes a high dielectric constant dielectric material having a dielectric constant greater than or equal to that of silicon oxide. For example, the material of the insulating layer 150 includes hafnium oxide, aluminum oxide, zirconium oxide, silicon oxide, lanthanum oxide, magnesium oxide, or other suitable high dielectric constant dielectric materials.

[0042] In some embodiments, the thickness of the insulating layer 150 is 3 nm to 7 nm, but is not limited to this.

[0043] Referring to FIG. 10, the interface layer 160 is formed on the insulating layer 150. For example, the interface layer 160 is formed by the ALD method or other suitable methods. In some embodiments, the interface layer 160 is conformally formed on the substrate 100, and the interface layer 160 extends along the surface of the insulating layer 150.

[0044] In some embodiments, the composition of the interface layer 160 has at least one element in common with the elements included in the insulating layer 150. Thereby, the interface layer 160 can be easily formed on the insulating layer 150, and the interface layer 160 has a good step coverage rate. For example, the interface layer 160 and the insulating layer 150 have a common element O.

[0045] In some embodiments, the composition of the interface layer 160 has at least one element in common with the elements included in the upper electrode (for example, the upper electrode 170 described later) to be formed thereafter. Thereby, in a subsequent process, the upper electrode can be easily formed on the interface layer 160.

[0046] In some embodiments, the material of the interface layer 160 is TiO x N y where 0 < x ≦ 1 and x + y = 1.

[0047] In some embodiments, the thickness of the interface layer 160 is 1 to 30 angstroms. Thereby, the interface layer 160 can effectively improve the step coverage of the upper electrode to be formed thereafter without significantly affecting the space for forming the upper electrode.

[0048] Referring to FIG. 11, the upper electrode 170 is formed on the interface layer 160. For example, the upper electrode 170 is formed by the ALD method or other suitable methods. In some embodiments, the upper electrode !70 is conformally formed on the substrate 100, and the upper electrode !70 extends along the surface of the interface layer 160.

[0049] In some embodiments, the material of the upper electrode 170 includes titanium nitride (TiN). Since the composition of the interface layer 160 has at least one element (e.g., Ti or N, etc.) in common with the elements included in the upper electrode 170, compared with the case of directly forming the upper electrode 170 on the insulating layer 150, the upper electrode 170 can be easily formed on the interface layer 160, thereby improving the step coverage of the upper electrode 170.

[0050] In some embodiments, the thickness of the upper electrode 170 is 1 to 5 nm. In some embodiments, the upper electrode 170 can fill the sacrificial layer 114 and the remaining space released by the opening.

[0051] Thus, the formation of the capacitor structure 10 is substantially completed.

[0052] Referring to FIG. 11, the capacitor structure 10 includes a lower electrode 140, an insulating layer 150, an interface layer 160, and an upper electrode 170. The insulating layer 150 is disposed on the lower electrode 140. The upper electrode 170 is disposed on the insulating layer 150. The interface layer 160 is disposed between the insulating layer 150 and the upper electrode 170. The composition of the interface layer 160 has at least one element in common with the elements included in the insulating layer 150 and at least one element in common with the elements included in the upper electrode 170. Since the composition of the interface layer 160 has at least one element in common with the elements included in the upper electrode 170, the step coverage rate of the upper electrode 170 can be improved, thereby improving the electrical performance of the capacitor structure 10.

[0053] In some embodiments, the materials of the upper electrode 170 and the lower electrode 140 include TiN, and the material of the insulating layer 150 includes a high-k dielectric material.

[0054] In some embodiments, the material of the interface layer 160 is different from the material of the insulating layer 150. In some embodiments, the material of the interface layer 160 includes TiO x N y where 0 < x ≦ 1 and x + y = 1.

[0055] In some embodiments, the nitrogen concentration in the interfacial layer 160 is lower than the nitrogen concentration in the upper electrode 170, and the oxygen concentration in the interfacial layer 160 is higher than the oxygen concentration in the upper electrode 170.

[0056] In some embodiments, the thickness of the interface layer 160 is less than the thickness of the insulating layer 150. In some embodiments, the thickness of the interface layer 160 is less than the thickness of the upper electrode 170.

[0057] In some embodiments, the lower electrode 140 of the capacitor structure 10 is surrounded by a support layer 112. In some embodiments, the support layer 112 includes a first support layer 112a, a second support layer 112b, and a third support layer 112c. The second support layer 112b is positioned between the first support layer 112a and the third support layer 112c. The first support layer 112a surrounds the lower part of the lower electrode 140. The second support layer 112b surrounds the middle part of the lower electrode 140. The third support layer 112c surrounds the upper part of the lower electrode 140.

[0058] In some embodiments, the insulating layer 150 is further extended into a support layer.

[0059] In some embodiments, the capacitor structure 10 is placed on a substrate 100 and electrically connected to the substrate 100. In some embodiments, the substrate 100 includes a grounding pad 102 and a transistor (not shown) electrically connected to the corresponding grounding pad 102. The capacitor structure 10 is electrically connected to the corresponding transistor via the corresponding grounding pad 102 and can form a memory cell such as a DRAM cell.

[0060] Figure 12 is a schematic cross-sectional view of a capacitor structure according to another embodiment of the present invention. Here, the embodiment in Figure 12 continues to use some of the reference numerals and descriptions of the components in the embodiment in Figure 11, where the same or similar reference numerals are used to indicate the same or similar components, and the same technical content is omitted. For explanations of the omitted parts, refer to the embodiments described above, and the details will not be repeated here.

[0061] Referring to Figure 12, the main difference between the capacitor structure 20 and the capacitor structure 10 in this embodiment is that the interface layer 160 of the capacitor structure 20 has a multilayer structure. Each layer of the multilayer structure is made of the same material, but with different composition ratios. For example, the oxygen concentration in the layer closer to the insulating layer 150 in the multilayer structure is higher than the oxygen concentration in the layer closer to the upper electrode 170 in the multilayer structure. In other words, the oxygen concentration in the multilayer structure gradually decreases from the side closer to the insulating layer 150 towards the other side closer to the upper electrode 170. In some embodiments, the nitrogen concentration in the layer closer to the insulating layer 150 in the multilayer structure is lower than the nitrogen concentration in the layer closer to the upper electrode 170 in the multilayer structure. In other words, the nitrogen concentration in the multilayer structure gradually increases from the side closer to the insulating layer 150 towards the other side closer to the upper electrode 170. Because the interface layer 160 has a multilayer structure, the multilayer structure can gradually change its composition to adapt to the different materials of the insulating layer 150 and the upper electrode 170, thereby improving the step coverage of the interface layer 160 and the upper electrode 170.

[0062] In some embodiments, the interface layer 160 includes a first interface layer 162 and a second interface layer 164. The first interface layer 162 is located between the insulating layer 150 and the upper electrode 170. The second interface layer 164 is located between the first interface layer 162 and the upper electrode 170. In some embodiments, the formation of the interface layer 160 includes the following steps: First, the first interface layer 162 is deposited on the insulating layer 150, and then the second interface layer 164 is deposited on the first interface layer 162. The first interface layer 162 and the second interface layer 164 may be formed by ALD or other suitable method.

[0063] In some embodiments, the first interface layer 162 and the second interface layer 164 contain TiO x N y . The oxygen concentration of the first interface layer 162 is higher than that of the second interface layer 164. For example, the first interface layer 162 may be TiO 0.5 N 0.5 , and the second interface layer 164 may be TiO 0.25 N 0.75 . In some embodiments, the nitrogen concentration of the first interface layer 162 is lower than that of the second interface layer 164.

[0064] In some embodiments, as long as the total thickness of the interface layer 160 is 1 to 30 angstroms, the thicknesses of the first interface layer 162 and the second interface layer 164 are not limited.

[0065] Note that in FIG. 12, the interface layer 160 is shown in a two-layer structure, but the present invention is not limited thereto. The number of layers of the interface layer 160 can be adjusted according to actual requirements.

[0066] Based on the above, the capacitor structure of the present invention includes an interface layer between the insulating layer and the upper electrode, which can improve the step coverage rate of the upper electrode, thereby improving the electrical performance of the capacitor structure.

[0067] It is clear to those skilled in the art that various modifications and changes can be made to the disclosed embodiments without departing from the scope or spirit of the present disclosure. Considering the above, the present disclosure intends to include modifications and changes as long as they are within the scope of the following claims and their equivalents.

Industrial Applicability

[0068] The capacitor structure of the present invention and its manufacturing method can be applied to a memory device and its manufacturing method.

Explanation of Reference Numerals

[0069] 10, 20: Capacitor structure 100: Substrate 102: Grounding pad 112: Supporter layer 112a: 1st support layer 112b: 2nd support layer 112c: Third support layer 114: Sacrificial Layer 114a: First layer of victims 114b: Second layer of victims 140: Lower electrode 150: Insulating layer 160: Interface layer 162: 1st interface layer 164: 2nd interface layer 170: Upper electrode

Claims

1. Lower electrode and An insulating layer disposed on the lower electrode, An upper electrode placed on the insulating layer, The insulating layer includes an interface layer disposed between the upper electrode, The composition of the interface layer includes at least one element common to the elements contained in the insulating layer and at least one element common to the elements contained in the upper electrode. Capacitor structure.

2. The material of the aforementioned interface layer is TiO ｘ N ｙ This includes, where 0 < x ≤ 1 and x + y = 1. The capacitor structure according to claim 1.

3. The oxygen concentration in the interfacial layer is higher than the oxygen concentration in the upper electrode. The capacitor structure according to claim 2.

4. The nitrogen concentration of the interface layer is lower than the nitrogen concentration of the upper electrode. The capacitor structure according to claim 2.

5. The aforementioned interface layer is A first interface layer is disposed between the insulating layer and the upper electrode, The first interface layer and the upper electrode are disposed between the two interfaces, The oxygen concentration of the first interface layer is higher than the oxygen concentration of the second interface layer. The capacitor structure according to claim 1.

6. The nitrogen concentration of the first interface layer is lower than the nitrogen concentration of the second interface layer. The capacitor structure according to claim 5.

7. The thickness of the interface layer is 1 to 30 angstroms. The capacitor structure according to claim 1.

8. The materials of the upper electrode and the lower electrode include TiN, and the material of the insulating layer includes a high dielectric constant dielectric material. The capacitor structure according to claim 1.

9. The lower electrode is doped with Si. The capacitor structure according to claim 8.

10. The insulating layer comprises hafnium oxide, aluminum oxide, zirconium oxide, silicon oxide, lanthanum oxide, or magnesium oxide. The capacitor structure according to claim 8.

11. Forming the lower electrode, Forming an insulating layer on the lower electrode, Forming an interface layer on the insulating layer, This includes forming an upper electrode on the interface layer, The composition of the interface layer includes at least one element common to the elements contained in the insulating layer and at least one element common to the elements contained in the upper electrode. A method for manufacturing a capacitor structure.

12. The interface layer is formed by atomic layer deposition, and the interface layer and the upper electrode have a common element N. The manufacturing method according to claim 11.

13. The nitrogen concentration of the interface layer is lower than the nitrogen concentration of the upper electrode. The manufacturing method according to claim 12.

14. Forming the aforementioned interface layer means Forming a first interface layer on the insulating layer, This includes forming a second interface layer on the first interface layer, The oxygen concentration of the first interface layer is higher than the oxygen concentration of the second interface layer. The manufacturing method according to claim 11.

15. Forming the lower electrode and the insulating layer is The process involves forming a laminated structure on a substrate, wherein the laminated structure includes alternately stacked support layers and sacrificial layers. To form an opening that penetrates the aforementioned laminated structure, The lower electrode is deposited on the side wall of the opening and on a portion of the substrate exposed by the opening. By removing the sacrificial layer of the laminated structure, the lower electrode and a portion of the support layer are exposed. This includes depositing the insulating layer on the exposed surfaces of the lower electrode and the support layer. The manufacturing method according to claim 11.

Images