Semiconductor device, power converter, and method for manufacturing a semiconductor device

Abstract

The objective is to provide a technology that can improve the insulating properties of the interlayer insulating film in the terminal region. [Solution] The semiconductor device comprises a semiconductor layer having a first trench in an active region and a second trench wider than the first trench in a terminal region; a gate electrode provided in the first trench via a first insulating film; a first interlayer insulating film provided in the first trench above the gate electrode; and a second interlayer insulating film provided on the bottom surface of the second trench and on all sides on the active region side via a second insulating film, wherein the upper end of the first interlayer insulating film is located below the upper end of the semiconductor layer.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device, a power conversion device, and a method for manufacturing a semiconductor device.

Background Art

[0002] As a configuration of a semiconductor device, a configuration in which a sidewall electrode is provided from a wide trench in a terminal region to the outside thereof is known (for example, Patent Document 1). On the other hand, as a configuration of a semiconductor device, a configuration has been proposed in which a gate electrode is provided in a gate trench in an active region via a gate insulating film, and an entire interlayer insulating film is provided in the gate trench on the gate electrode.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] Generally, the gate electrode and the sidewall electrode are formed by etching the same conductive film. When manufacturing a configuration in which an entire interlayer insulating film is provided in a gate trench, the gate electrode is etched more than before in order to lower the upper end of the gate electrode in the gate trench. Along with this, the sidewall electrode is also etched more than before, and the sidewall electrode is provided in a wide trench and has a tapered portion that tapers upward.

[0005] However, the out-of-plane direction of the upper surface of the tapered portion is greatly different from the deposition direction in which the interlayer insulating film easily accumulates on the tapered portion. Therefore, when the sidewall electrode has only the tapered portion, there is a problem that the thickness of the interlayer insulating film on the tapered portion becomes partially thin, and the insulating property of the interlayer insulating film in the terminal region deteriorates.

[0006] Therefore, this disclosure has been made in view of the above-mentioned problems, and aims to provide a technology that can improve the insulating properties of the interlayer insulating film in the terminal region. [Means for solving the problem]

[0007] The semiconductor device according to this disclosure comprises a semiconductor layer having a first trench in an active region and a second trench wider than the first trench in a terminal region; a gate electrode provided in the first trench via a first insulating film; a first interlayer insulating film provided in the first trench above the gate electrode; and a second interlayer insulating film provided via a second insulating film on the bottom surface of the second trench and on all sides on the active region side, wherein the upper end of the first interlayer insulating film is located below the upper end of the semiconductor layer. [Effects of the Invention]

[0008] According to this disclosure, the insulating properties of the interlayer insulating film in the terminal region can be improved.

[0009] The purpose, features, aspects, and advantages of this disclosure will become clearer from the following detailed description and accompanying drawings. [Brief explanation of the drawing]

[0010] [Figure 1] This is a plan view showing the configuration of a semiconductor device according to Embodiment 1. [Figure 2] This is a cross-sectional view showing the configuration of a semiconductor device according to Embodiment 1. [Figure 3] This is a cross-sectional view showing the configuration of a semiconductor device according to Embodiment 1. [Figure 4] This is a cross-sectional view showing the configuration of a semiconductor device according to Embodiment 1. [Figure 5] This is a flowchart showing the method for manufacturing a semiconductor device according to Embodiment 1. [Figure 6] This is a cross-sectional view illustrating the manufacturing method of a semiconductor device according to Embodiment 1. [Figure 7] This is a cross-sectional view showing the configuration of the related device. [Figure 8] This is a cross-sectional view showing the configuration of a semiconductor device according to Embodiment 1. [Figure 9] This is a cross-sectional view showing the configuration of a semiconductor device according to a modified example 2. [Figure 10] This is a cross-sectional view showing the configuration of a semiconductor device according to a modified example 2. [Figure 11] This is a cross-sectional view showing the configuration of a semiconductor device according to a modified example 2. [Figure 12] This is a cross-sectional view showing the configuration of a semiconductor device according to Embodiment 2. [Figure 13] This is a cross-sectional view showing the configuration of a semiconductor device according to Embodiment 2. [Figure 14] This is a cross-sectional view showing the configuration of a semiconductor device according to Embodiment 2. [Figure 15] This is a flowchart showing the method for manufacturing a semiconductor device according to Embodiment 2. [Figure 16] This is a block diagram showing the configuration of a power conversion system to which the power conversion device according to Embodiment 3 is applied. [Modes for carrying out the invention]

[0011] Hereinafter, embodiments will be described with reference to the accompanying drawings. The features described in the following embodiments are examples, and not all features are necessarily essential. Also, in the explanations given below, the same or similar reference numerals are assigned to the same components in multiple embodiments, and different components will be mainly described. Further, in the explanations described below, specific positions and directions such as "top", "bottom", "left", "right", "front" or "back" do not necessarily have to match the positions and directions during actual implementation. Also, that a certain part has a higher density than another part may, for example, mean that the average density of a certain part is higher than the average density of another part. Conversely, that a certain part has a lower density than another part may, for example, mean that the average density of a certain part is lower than the average density of another part. Also, in the following, it is described that the first conductivity type is n-type and the second conductivity type is p-type, but the first conductivity type may be p-type and the second conductivity type may be n-type.

[0012] <Embodiment 1> FIG. 1 is a plan view showing the configuration of a semiconductor device according to Embodiment 1 of the present invention. FIG. 2 is a cross-sectional view taken along line A-A of FIG. 1, and FIG. 3 is a cross-sectional view taken along line B-B of FIG. 1. FIG. 4 is an enlarged cross-sectional view of a part of FIG. 3. In FIGS. 2 and 3, for convenience, some illustrations of the components of FIG. 4 are omitted and simplified.

[0013] Hereinafter, the case where the semiconductor device according to Embodiment 1 is a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) will be described, but it is not limited thereto. The semiconductor device according to Embodiment 1 may be, for example, an IGBT (Insulated Gate Bipolar Transistor), or an RC-IGBT (Reverse Conducting - IGBT) which is a semiconductor switching element including a diode.

[0014] As shown in Figure 4, the semiconductor device according to this first embodiment comprises a semiconductor layer 1, a gate insulating film 2 which is a first insulating film, a gate electrode 3, a first interlayer insulating film 4, a termination insulating film 5 which is a second insulating film, a sidewall electrode 6 which is a termination electrode, a second interlayer insulating film 7, and a source electrode 8.

[0015] The semiconductor layer 1 is made of, for example, silicon (Si) or a wide-bandgap semiconductor, and includes at least one of a normal semiconductor wafer and an epitaxial growth layer. In this specification, for example, at least one of A, B, C, ..., and Z means any one of all combinations selected from the groups A, B, C, ..., and Z. Wide-bandgap semiconductors include, for example, silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga2O3), and diamond. When the semiconductor layer 1 is made of a wide-bandgap semiconductor, stable operation of the semiconductor device under high temperature and high voltage, and high-speed switching are possible.

[0016] As shown in Figure 4, the semiconductor layer 1 is defined as having an active region 1j and a termination region 1k. A semiconductor cell that functions as a MOSFET is provided in the active region 1j. The termination region 1k is the region surrounding the active region 1j, and a voltage-resistant structure such as a guard ring (not shown) is provided in the termination region 1k. Note that the gate pad 31 in Figure 1 is generally provided above the semiconductor layer 1 in the termination region 1k, and the source pad 32 is generally provided above the semiconductor layer 1 in the active region 1j. The configuration of the active region 1j will be described below, followed by the configuration of the termination region 1k.

[0017] <Active area 1j> As shown in Figure 4, the semiconductor layer 1 of the active region 1j includes a drift region 1a, a low-resistance region 1b, a well region (also called the base region) 1c, a source region 1d, a contact region 1e, and an electric field relaxation region 1f.

[0018] The drift region 1a is n -This is a region of type n. The low-resistance region 1b is an n-type region and is located above the drift region 1a. Note that the low-resistance region 1b is part of the drift region 1a. The well region 1c is a p-type region and is located on the low-resistance region 1b. The source region 1d is n + This is a region of type and is located on the well region 1c.

[0019] Contact area 1e is p + This is a type region, and is provided on the well region 1c where the source region 1d is not provided. As shown in Figure 2, depending on the position in the extension direction of the gate trench 1p described later, a contact region 1e may or may not be provided.

[0020] As shown in Figure 4, the active region 1j of the semiconductor layer 1 is provided with a gate trench 1p, which is a first trench that penetrates from the upper surface of the source region 1d through the well region 1c. In a plan view, the multiple gate trenches 1p may or may not have a stripe shape. The electric field relaxation region 1f is a p-type region and is provided at the bottom surface of the gate trench 1p.

[0021] Note that the configuration of the semiconductor layer 1 is not limited to the configuration shown in Figure 1. For example, in the configuration shown in Figure 4, a p-type impurity region (not shown) may be provided along the gate trench 1p, connecting the well region 1c and the field relaxation region 1f. Also, for example, the well region 1c and the source region 1d may be partially omitted.

[0022] The gate insulating film 2 is provided within the gate trench 1p, and the gate electrode 3 is provided within the gate trench 1p via the gate insulating film 2. A recess is provided in the center of the upper part of the gate electrode 3. Although not shown, the gate electrode 3 is electrically connected to the gate pad 31 in Figure 1.

[0023] As shown in Figure 4, the first interlayer insulating film 4 is provided in the gate trench 1p above the gate electrode 3. A recess is provided in the center of the upper part of the first interlayer insulating film 4. In this embodiment 1, the entire first interlayer insulating film 4 is provided in the gate trench 1p, and the upper end of the first interlayer insulating film 4 is located below the upper end of the semiconductor layer 1 (i.e., the upper end of the source region 1d). In this configuration, where the entire first interlayer insulating film 4 is provided in the gate trench 1p, the size of the first interlayer insulating film 4 in plan view can be reduced, thereby enabling improved performance of the semiconductor device by reducing the cell pitch.

[0024] The source electrode 8 is provided on the first interlayer insulating film 4 and is electrically connected to the source region 1d and the contact region 1e. The source electrode 8 may also be provided on the second interlayer insulating film 7 as well as the first interlayer insulating film 4. Although not shown, the source electrode 8 is electrically connected to the source pad 32 in Figure 1. A drain electrode (not shown) is provided on the underside of the semiconductor layer 1. When a voltage above the threshold voltage is applied to the gate electrode 3, a channel is formed in the portion of the well region 1c on the gate electrode 3 side, and current flows between the source electrode 8 and the drain electrode through this channel.

[0025] <Terminal area 1k> As shown in Figure 4, the termination region 1k of the semiconductor layer 1 is provided with a wide trench 1q, which is a second trench wider than the gate trench 1p, extending from the upper surface of the source region 1d through the well region 1c. Here, width corresponds to the distance in the left-right direction in Figure 4. The mesa region 1r, which is the upper part of the semiconductor layer 1, is provided between the gate trench 1p and the wide trench 1q. Preferably, the depth of the gate trench 1p and the depth of the wide trench 1q are the same or substantially the same. With this configuration, the depth of the depletion layer within the drift region 1a can be made uniform, thereby suppressing the breakdown voltage of the semiconductor device due to electric field concentration at the outer periphery of the active region 1j.

[0026] However, if the depth of the depletion layer within the drift region 1a can be standardized by impurity distribution, the wide trench 1q may be deeper than the gate trench 1p. In this case as well, the breakdown voltage reduction of the semiconductor device due to electric field concentration at the outer periphery of the active region 1j can be suppressed.

[0027] The sidewall electrode 6 is provided on the bottom surface 1q1 and the side surface 1q2 on the active region 1j side of the wide trench 1q via a terminating insulating film 5. The sidewall electrode 6 is formed from the same conductive film as the gate electrode 3, and the material of the sidewall electrode 6 is the same as the material of the gate electrode 3. The fact that the material of the sidewall electrode 6 is the same as the material of the gate electrode 3 means that the sidewall electrode 6 is formed from the same conductive film as the gate electrode 3, and errors of a certain degree of manufacturing variation are acceptable. If the opening sizes of the gate trench 1p and the wide trench 1q were the same, the vertical thickness of the gate electrode 3 and the sidewall electrode 6 would be the same, but in this embodiment 1, the opening sizes of these trenches are different, so the thicknesses of these electrodes are slightly different from each other.

[0028] Although not shown in the diagram, in this embodiment 1, the sidewall electrode 6 is continuous with the gate electrode 3, and the termination insulating film 5 is continuous with the gate insulating film 2. In other words, the sidewall electrode 6 is electrically connected to the gate electrode 3.

[0029] As shown in Figure 4, the sidewall electrode 6 includes a tapered portion 6a and a continuous portion 6b. The tapered portion 6a is provided along the side surface 1q2 of the wide trench 1q and tapers towards the top. The continuous portion 6b is provided along the bottom surface 1q1 of the wide trench 1q and is continuous with the tapered portion 6a. In this embodiment 1, the tapered portion 6a includes a first portion and a second portion that is closer to the continuous portion 6b than the first portion, and the out-of-plane direction D1 of the first portion is closer to the vertical direction than the out-of-plane direction D2 of the second portion.

[0030] The second interlayer insulating film 7 is provided on the sidewall electrode 6. In this embodiment 1, the second interlayer insulating film 7 is provided on the tapered portion 6a, the continuous portion 6b, and the mesa portion 1r.

[0031] <Manufacturing method> Figure 5 is a flowchart showing the manufacturing method of a semiconductor device according to this embodiment 1. Since each region of the semiconductor layer 1 can be formed using general semiconductor device manufacturing processes, the formation of the gate electrode 3 and sidewall electrodes 6 will be mainly described here.

[0032] In step S1, a gate trench 1p is formed in the active region 1j of the semiconductor layer 1, and a wide trench 1q is formed in the terminal region 1k of the semiconductor layer 1. In step S2, as shown in Figure 6, an insulating film 9 is formed in the gate trench 1p and the wide trench 1q. The insulating film 9 in the gate trench 1p and the insulating film 9 in the wide trench 1q may be formed in parallel or individually. Also, the thickness of the insulating film 9 in the gate trench 1p and the thickness of the insulating film 9 in the wide trench 1q may be different.

[0033] In step S3, a conductive film 10 is formed on the insulating film 9 as shown in Figure 6. In step S4, the conductive film 10 is patterned as shown in Figure 6 to form the gate electrode 3 and the sidewall electrode 6 in parallel. Note that, in the sidewall electrode 6, the continuous portion 6b can be made continuous with the tapered portion 6a by adjusting the position of the mask used to pattern the conductive film 10, the thickness of the continuous portion 6b, and the etching conditions. For etching the conductive film 10, for example, isotropic etching is used, but it is not limited to this.

[0034] In step S5, an interlayer insulating film is formed in the gate trench 1p above the gate electrode 3, and an interlayer insulating film is formed on the sidewall electrode 6. Then, the interlayer insulating film is patterned to form the first interlayer insulating film 4 and the second interlayer insulating film 7, and the insulating film 9 is patterned to form the gate insulating film 2 and the termination insulating film 5. The first interlayer insulating film 4 and the second interlayer insulating film 7 may be formed in parallel or individually. After that, the source electrode 8 and drain electrode, etc., are formed, and the semiconductor device is completed.

[0035] <Summary of Embodiment 1> Figure 7 is a cross-sectional view showing the configuration of a related device, which is a semiconductor device related to the semiconductor device according to this embodiment 1. In the related device, the sidewall electrode 6 includes a tapered portion 6a but does not include a continuous portion 6b.

[0036] The out-of-plane direction D of the upper surface of the tapered portion 6a is significantly different from the deposition direction (corresponding to the vertical direction in Figure 7) in which the second interlayer insulating film 7 is easily deposited on the tapered portion 6a. Therefore, when the sidewall electrode 6 has only the tapered portion 6a, the thickness of the second interlayer insulating film 7 in the out-of-plane direction D becomes thin, resulting in a problem where the insulating properties of the second interlayer insulating film 7 in the terminal region 1k decrease.

[0037] In contrast, according to the semiconductor device of this embodiment 1 shown in Figure 4, the sidewall electrode 6 includes a tapered portion 6a and a continuous portion 6b that is continuous with the tapered portion 6a. With this configuration, the upper surface of the tapered portion 6a, which is far from the deposition direction in the out-of-plane direction, can be reduced by the continuous portion 6b. As a result, the thickness of the second interlayer insulating film 7 can be increased, and the insulating properties of the second interlayer insulating film 7 in the terminal region 1k can be improved.

[0038] Furthermore, in a configuration where the sidewall electrode 6 is electrically connected to the gate electrode 3, the gate voltage can be maintained by increasing the insulating properties of the second interlayer insulating film 7 in the termination region 1k as described above.

[0039] Furthermore, in this embodiment 1, as shown in Figure 4, the tapered portion 6a includes a first portion and a second portion that is closer to the continuous portion 6b than the first portion, and the out-of-plane direction D1 of the first portion is closer to the vertical direction than the out-of-plane direction D2 of the second portion. With this configuration, the out-of-plane direction of the tapered portion 6a can be brought closer to the deposition direction of the second interlayer insulating film 7, so that the thickness of the second interlayer insulating film 7 near the side surface 1q2 at the boundary between the active region 1j and the terminal region 1k can be increased. Note that this is not limited to the configuration in Figure 4, and can also be achieved in a configuration where the portion of the continuous portion 6b on the tapered portion 6a side is thinner than other parts of the continuous portion 6b, as shown in the configuration in Figure 8.

[0040] <Example 1> In Embodiment 1, the sidewall electrode 6 was electrically connected to the gate electrode 3, but this is not the only possible configuration. As a first example, the sidewall electrode 6 may be electrically connected to the source electrode 8 instead of the gate electrode 3. In such a configuration, the source voltage can be maintained by increasing the insulation of the second interlayer insulating film 7 in the termination region 1k as described above. As a second example, the sidewall electrode 6 may be a floating electrode that is not electrically connected to either the gate electrode 3 or the source electrode 8. In such a configuration, by increasing the insulation of the second interlayer insulating film 7 in the termination region 1k as described above, it is possible to reduce the increase in resistance caused by a short circuit between the gate electrode 3 or the source electrode 8 and the floating electrode, the sidewall electrode 6.

[0041] <Modification 2> In Embodiment 1, as shown in Figure 9, the upper end of the tapered portion 6a of the sidewall electrode 6, which is the termination electrode, may be configured to be located below the upper end of the gate electrode 3. With this configuration, the height difference between the tapered portion 6a and the continuous portion 6b can be reduced, thereby reducing the portion where the out-of-plane direction D of the upper surface of the tapered portion 6a differs significantly from the deposition direction of the second interlayer insulating film 7 (corresponding to the vertical direction in Figure 9). As a result, the thickness of the second interlayer insulating film 7 can be increased, thereby improving the insulating properties of the second interlayer insulating film 7 in the termination region 1k.

[0042] Furthermore, methods to reduce the height difference between the tapered portion 6a and the continuous portion 6b include increasing the film thickness of the portion that becomes the continuous portion 6b when forming the conductive film 10 as shown in Figure 6, or increasing the amount of etching in the portion that becomes the tapered portion 6a when etching the conductive film 10. However, both of these methods require adding a new process to the manufacturing method described in Embodiment 1, thus increasing the manufacturing load.

[0043] Therefore, as a method to reduce the height difference between the tapered portion 6a and the continuous portion 6b, it is preferable to perform the process of step S4 as in Embodiment 1, that is, to form the gate electrode 3 and the sidewall electrode 6 in parallel. Since the width of the wide trench 1q is wider than the width of the gate trench 1p, etching the conductive film 10 in Figure 6 allows the upper end of the tapered portion 6a of the sidewall electrode 6 to be positioned lower than the upper end of the gate electrode 3. As a result, not only can the height difference between the tapered portion 6a and the continuous portion 6b be reduced, but an increase in manufacturing load can be suppressed because no additional process is required.

[0044] The minimum film thickness of the continuous portion 6b is, for example, 0.5 μm. For example, if the width of gate trench 1p is 1.0 μm and the depth of gate trench 1p is 2.0 μm, the distance from the top surface of the source region 1d to the top end of the gate electrode 3 (i.e., the etching amount) is 0.4 to 0.7 μm.

[0045] In the configurations shown in Figures 10 and 11, the n-type region closest to the active region 1j functions as the source region 1d because it is electrically connected to the source electrode 8. However, in the process of forming the wide trench 1q, the surface of the side wall of the wide trench 1q tends to become rough. Therefore, in the configurations shown in Figures 10 and 11, there is a possibility of leakage occurring between the source region 1d closest to the active region 1j and the sidewall electrode 6.

[0046] Therefore, the configuration in Figure 9, in which the upper end of the tapered portion 6a of the sidewall electrode 6 is located below the upper end of the gate electrode 3, may be applied to the configurations in Figures 10 and 11. With such a configuration, not only can the thickness of the second interlayer insulating film 7 be increased, but the area in which the source region 1d closest to the active region 1j and the sidewall electrode 6 face each other can be reduced, thereby suppressing the occurrence of the above-mentioned leakage.

[0047] <Embodiment 2> Figure 12 is a cross-sectional view showing the configuration of the semiconductor device according to this second embodiment, and specifically corresponds to the cross-sectional view in Figure 4. Hereinafter, among the components of this second embodiment, components that are the same as or similar to the components described above will be denoted by the same or similar reference numerals, and the different components will be described mainly.

[0048] In this second embodiment, the sidewall electrode 6, including the tapered portion 6a described in the related device section, is not provided within the wide trench 1q. The second interlayer insulating film 7 is provided on the bottom surface 1q1 of the wide trench 1q and on all sides 1q2 on the active region 1j side, via the terminating insulating film 5.

[0049] Furthermore, sidewall electrodes that do not include the tapered portion 6a may be provided within the wide trench 1q. That is, as shown in Figure 13, a bottom electrode 6c corresponding to the continuous portion 6b of the sidewall electrode may be provided along the bottom surface of the wide trench 1q on the side opposite to the second interlayer insulating film 7. Alternatively, as shown in Figure 14, the second interlayer insulating film 7 may be provided on the entire bottom surface of the wide trench 1q.

[0050] <Manufacturing method> Figure 15 is a flowchart showing the method for manufacturing a semiconductor device according to this second embodiment. Since steps S1 to S3 in Figure 15 are the same as steps S1 to S3 in Figure 5, steps S4a and S5a will be mainly described below.

[0051] In step S4a, the conductive film 10 is patterned to form the gate electrode 3, but the sidewall electrode 6 is not formed in the wide trench 1q. The conductive film 10 in the wide trench 1q may be removed using a mask, or it may be removed without using a mask by appropriately adjusting the opening size of the wide trench 1q.

[0052] In step S5a, a first interlayer insulating film 4 is formed in the gate trench 1p above the gate electrode 3, and a second interlayer insulating film 7 is formed on the bottom surface 1q1 and side surface 1q2 of the wide trench 1q via a termination insulating film 5. The first interlayer insulating film 4 and the second interlayer insulating film 7 may be formed in parallel or individually. Subsequently, the source electrode 8 and drain electrode, etc., are formed, and the semiconductor device is completed.

[0053] <Summary of Embodiment 2> In the semiconductor device according to this second embodiment described above, instead of providing a sidewall electrode 6 including a tapered portion 6a that reduces the thickness of the second interlayer insulating film 7 in the wide trench 1q, the second interlayer insulating film 7 is provided in the wide trench 1q via a terminating insulating film 5. Specifically, the second interlayer insulating film 7 is provided on the bottom surface 1q1 of the wide trench 1q and on all side surfaces 1q2 on the active region 1j side via a terminating insulating film 5. With this configuration, since the tapered portion 6a that caused the second interlayer insulating film 7 to become thinner is not provided, the thickness of the second interlayer insulating film 7 can be increased, and as a result, the insulating properties of the second interlayer insulating film 7 in the terminating region 1k can be improved.

[0054] <Variation> In embodiments 1 and 2, the sidewall electrode 6 was described as being continuous with the gate electrode 3 and the termination insulating film 5 as being continuous with the gate insulating film 2, but this is not the only configuration. For example, depending on the planar layout of the semiconductor device, the sidewall electrode 6 may be separated from the gate electrode 3, and the termination insulating film 5 may be separated from the gate insulating film 2.

[0055] Furthermore, in embodiments 1 and 2, the sidewall electrode 6, including the tapered portion 6a and the continuous portion 6b, was applied to a cross-sectional configuration along line BB in Figure 1, but this is not the only option. For example, depending on the planar layout of the semiconductor device, the sidewall electrode 6 may also be applied to a cross-sectional configuration along line AA in Figure 1.

[0056] <Embodiment 3> The power converter according to this third embodiment has the semiconductor device according to the embodiments 1 and 2 described above. The power converter according to this third embodiment is not limited to a specific power converter, but the following describes the case in which the power converter according to this third embodiment is applied to a three-phase inverter.

[0057] Figure 16 is a block diagram showing the configuration of a power conversion system to which the power conversion device 200 according to this third embodiment is applied. The power conversion system shown in Figure 16 consists of a power supply 100, a power conversion device 200, and a load 300. The power supply 100 is a DC power supply and supplies DC power to the power conversion device 200. The power supply 100 can be composed of various power sources, for example, a DC grid, a solar cell, or a storage battery, or a rectifier circuit or AC / DC converter connected to an AC grid. Alternatively, the power supply 100 may be composed of a DC / DC converter that converts DC power output from a DC grid into a predetermined power.

[0058] The power converter 200 is a three-phase inverter connected between the power supply 100 and the load 300. The power converter 200 converts the DC power supplied from the power supply 100 into AC power and supplies the AC power to the load 300. As shown in Figure 16, the power converter 200 includes a main conversion circuit 201, which is a conversion circuit that converts DC power into AC power and outputs it; a drive circuit 202, which outputs drive signals to drive each switching element of the main conversion circuit 201; and a control circuit 203, which outputs control signals to the drive circuit 202 to control the drive circuit 202.

[0059] Load 300 is a three-phase motor driven by AC power supplied from power converter 200. Note that Load 300 is not limited to a specific application; it is a motor installed in various electrical devices, such as hybrid vehicles, electric vehicles, railway vehicles, elevators, or air conditioning equipment.

[0060] The details of the power converter 200 are described below. The main conversion circuit 201 includes switching elements and freewheeling diodes (not shown). For example, the freewheeling diodes may be built into the switching elements. By switching the switching elements, the main conversion circuit 201 converts the DC power supplied from the power supply 100 into AC power and supplies the AC power to the load 300. Various specific circuit configurations can be envisioned for the main conversion circuit 201, but the main conversion circuit 201 according to this embodiment 3 is a two-level three-phase full-bridge circuit and can be composed of six switching elements and six freewheeling diodes antiparallel to each switching element. As the switching elements of the main conversion circuit 201, semiconductor devices according to any of the embodiments 1 and 2 described above or their modified versions are used. The six switching elements are connected in series in pairs to form upper and lower arms, and each upper and lower arm constitutes each phase (U phase, V phase, W phase) of the full-bridge circuit. The output terminals of each upper and lower arm, i.e., the three output terminals of the main conversion circuit 201, are connected to the load 300.

[0061] The drive circuit 202 generates drive signals to drive the switching elements of the main conversion circuit 201 and supplies them to the control electrodes of the switching elements of the main conversion circuit 201. Specifically, the drive circuit 202 outputs drive signals to turn on the switching elements and drive signals to turn off the switching elements to the control electrodes of each switching element, according to the control signals from the control circuit 203, which will be described later. When the switching element is kept in the ON state, the drive signal is a voltage signal greater than the threshold voltage of the switching element (ON signal), and when the switching element is kept in the OFF state, the drive signal is a voltage signal less than the threshold voltage of the switching element (OFF signal).

[0062] The control circuit 203 controls the switching elements of the main converter circuit 201 so that the desired power is supplied to the load 300. Specifically, the control circuit 203 calculates the time (on time) that each switching element of the main converter circuit 201 should be in the ON state, based on the power to be supplied to the load 300. For example, the control circuit 203 calculates the time so that the main converter circuit 201 can be controlled by pulse width modulation (PWM) control, which modulates the on time of the switching elements according to the voltage to be output. Then, the control circuit 203 outputs a control command (control signal) to the drive circuit 202 so that an ON signal is output to the switching elements that should be in the ON state at each point in time, and an OFF signal is output to the switching elements that should be in the OFF state. The drive circuit 202 outputs an ON signal or an OFF signal as a drive signal to the control electrode of each switching element according to this control signal.

[0063] In the power conversion device according to this third embodiment, the semiconductor devices according to embodiments 1 and 2 are used as semiconductor devices constituting the main conversion circuit 201, thereby improving the insulation of the termination region.

[0064] In this third embodiment, an example of applying the semiconductor device according to embodiments 1 and 2 to a two-level three-phase inverter was described. However, this third embodiment is not limited to this and can be applied to various power conversion devices. Although the power conversion device according to this third embodiment is described as a two-level power conversion device, it may also be a three-level or multi-level power conversion device, or the power conversion device may be applied to a single-phase inverter when supplying power to a single-phase load. Furthermore, when supplying power to a DC load, the power conversion device can also be applied to a DC / DC converter or an AC / DC converter.

[0065] Furthermore, the power conversion device according to this third embodiment is not limited to cases where the load is an electric motor, but can also be used, for example, as a power supply device for an electrical discharge machine, a laser processing machine, an induction heating cooker, or a contactless power supply system, and can even be used as a power conditioner for a solar power generation system or an energy storage system.

[0066] In this disclosure in English, 'a' and 'an' mean one or more. Therefore, 'a', 'an', 'one or more', and 'at least one' can be used interchangeably.

[0067] Furthermore, it is possible to freely combine each embodiment and each variation, and to modify or omit each embodiment and each variation as appropriate.

[0068] The above explanation is illustrative and not limiting in all respects. It should be understood that countless variations not illustrated are conceivable. [Explanation of Symbols]

[0069] 1 Semiconductor layer, 1j active region, 1k termination region, 1p gate trench, 1q wide trench, 1q1 bottom surface, 1q2 side surface, 1r mesa region, 2 gate insulating film, 3 gate electrode, 4 first interlayer insulating film, 5 termination insulating film, 6 sidewall electrode, 6a tapered portion, 6b continuous portion, 6c bottom electrode, 7 second interlayer insulating film, 8 source electrode, 200 power converter, 201 main converter circuit, 202 drive circuit, 203 control circuit.

Claims

1. A semiconductor layer having a first trench in the active region and a second trench wider than the first trench in the terminal region, A gate electrode provided in the first trench via a first insulating film, A first interlayer insulating film is provided in the first trench above the gate electrode, A second interlayer insulating film is provided on the bottom surface of the second trench and on all sides of the active region via a second insulating film. Equipped with, A semiconductor device in which the upper end of the first interlayer insulating film is located below the upper end of the semiconductor layer.

2. A semiconductor device according to claim 1, A semiconductor device further comprising a bottom electrode provided along the bottom surface of the second trench, on the side of the second trench opposite to the side surface of the second trench, with respect to the second interlayer insulating film.

3. A semiconductor device according to claim 1, A semiconductor device wherein the second interlayer insulating film is provided on all bottom surfaces of the second trench.

4. A semiconductor device as described in claim 1, comprising a conversion circuit that converts and outputs input power, A drive circuit that outputs a drive signal to the semiconductor device to drive the semiconductor device, A control circuit that outputs a control signal to the drive circuit to control the drive circuit, A power conversion device equipped with the following features.

5. A first trench is formed in the active region of the semiconductor layer, and a second trench wider than the first trench is formed in the terminal region of the semiconductor layer. A gate electrode is formed in the first trench via a first insulating film, but no terminal electrode is formed in the second trench, which includes a tapered portion that narrows towards the top and is made of the same material as the gate electrode. A first interlayer insulating film is formed in the first trench above the gate electrode, and a second interlayer insulating film is formed on the bottom surface of the second trench and on all sides on the active region side via the second insulating film. A method for manufacturing a semiconductor device, wherein the upper end of the first interlayer insulating film is located below the upper end of the semiconductor layer.

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