Oxide thin-film transistor, method for manufacturing the same, and display device.

Abstract

This improves the conductivity of oxide semiconductor thin-film transistors under the influence of high-temperature processes. [Solution] The oxide thin-film transistor (100) includes a base substrate (101), an oxide semiconductor layer (105) installed on the base substrate (101), and an insulating layer (108) installed on the side of the oxide semiconductor layer (105) away from the base substrate (101). The insulating layer (108) is made of an oxide, and the insulating layer (108) includes a first insulating layer (108b) and a second insulating layer (108a) that are stacked together. The density of the second insulating layer (108a) is greater than that of the first insulating layer (108b), and the second insulating layer (108a) is further away from the base substrate (101) than the first insulating layer. The embodiments of this disclosure adjust the density and thickness of at least the first and second insulating layers and fix oxygen in the oxide semiconductor layer, thereby reducing the loss of oxygen elements in the oxide semiconductor layer during the subsequent high-temperature annealing process and ensuring the stability of the characteristics of the oxide thin-film transistor.

Description

[Technical Field]

[0001] The embodiments of this disclosure relate to oxide thin-film transistors, display devices, and methods for manufacturing oxide thin-film transistors. [Background technology]

[0002] Oxide semiconductor thin-film transistors have advantages such as high mobility, excellent stability, and a simple manufacturing process. Oxide semiconductor materials, such as indium gallium zinc oxide (IGZO), are widely used in display fields such as thin-film transistor liquid crystal displays (TFT-LCDs) and active-matrix organic light-emitting diode panels (AMOLEDs), as well as in non-display fields (e.g., chip storage).

[0003] Thin-film transistors are classified into top-gate and bottom-gate structures depending on the position of the gate electrode relative to the active region, and into top-contact and bottom-contact structures depending on the position of the source and drain electrodes relative to the active region. In other words, thin-film transistors generally have four structures: bottom-gate top-contact (bottom-gate staggered), bottom-gate bottom-contact (bottom-gate coplanar), top-gate top-contact (top-gate coplanar), and top-gate bottom-contact (top-gate staggered). Currently, in oxide semiconductor layer thin-film transistor structures, the bottom-gate structure mainly has three types: etching barrier type, back-channel etching type, and coplanar type. The process for manufacturing back-channel etching type metal oxide thin-film transistors is simple and requires fewer photolithography processes than the etching barrier type, thus reducing equipment investment and improving production efficiency. [Overview of the Initiative] [Means for solving the problem]

[0004] At least one embodiment of the present disclosure provides an oxide thin-film transistor comprising a base substrate, an oxide semiconductor layer installed on the base substrate, and an insulating layer installed on the side of the oxide semiconductor layer away from the base substrate, wherein the insulating layer is made of an oxide, and the insulating layer comprises a laminated first insulating layer and a second insulating layer, wherein the density of the second insulating layer is greater than that of the first insulating layer, and the second insulating layer is further away from the base substrate than the first insulating layer.

[0005] For example, in an oxide thin-film transistor according to at least one embodiment of the present disclosure, the oxide semiconductor layer is a metal oxide semiconductor layer, and the insulating layer material is an oxide of a non-metallic material.

[0006] For example, in an oxide thin-film transistor according to at least one embodiment of the present disclosure, the materials of the first insulating layer and the second insulating layer contain at least O and Si atoms.

[0007] For example, in an oxide thin-film transistor according to at least one embodiment of the present disclosure, the insulating layer further includes a third insulating layer, the third insulating layer is located on the side of the first insulating layer closer to the base substrate, the density of the third insulating layer is greater than that of the first insulating layer, and the third insulating layer is in contact with the oxide semiconductor layer.

[0008] For example, in an oxide thin-film transistor according to at least one embodiment of the present disclosure, the oxide semiconductor layer includes a stacked first oxide semiconductor layer and a second oxide semiconductor layer, the density of the second oxide semiconductor layer is greater than that of the first oxide semiconductor layer, and the second oxide semiconductor layer is further away from the base substrate than the first oxide semiconductor layer.

[0009] For example, in an oxide thin-film transistor according to at least one embodiment of the present disclosure, a source and a drain are provided between the oxide semiconductor layer and the insulating layer, spaced apart from each other, and the oxide semiconductor layer and the insulating layer are in contact in the region between the source and the drain.

[0010] For example, in an oxide thin-film transistor according to at least one embodiment of the present disclosure, a gate is provided between the base substrate and the oxide semiconductor layer, a gate insulating layer is provided between the gate and the oxide semiconductor layer, and the material of the portion of the gate insulating layer that contacts the oxide semiconductor layer is an oxide insulating material.

[0011] For example, in an oxide thin-film transistor according to at least one embodiment of the present disclosure, the gate insulating layer includes a first gate insulating layer, a second gate insulating layer, a third gate insulating layer, and a fourth gate insulating layer that are stacked, the materials of the first gate insulating layer, the second gate insulating layer, and the third gate insulating layer are all nitrides, the thickness of the first gate insulating layer and the thickness of the third gate insulating layer are both smaller than the thickness of the second gate insulating layer, the density of the first gate insulating layer and the density of the third gate insulating layer are both smaller than the density of the second gate insulating layer, the material of the fourth gate insulating layer is the oxide insulating material, and the fourth gate insulating layer is in contact with the oxide semiconductor layer.

[0012] For example, in an oxide thin-film transistor according to at least one embodiment of the present disclosure, a gate is provided between the layer on which the source and the drain are located and the oxide semiconductor layer, the insulating layer further includes a fourth insulating layer provided between the first insulating layer and the second insulating layer, and the gate is provided between the fourth insulating layer and the first insulating layer.

[0013] For example, in an oxide thin-film transistor according to at least one embodiment of the present disclosure, the insulating layer further includes a fifth insulating layer placed between the first insulating layer and the fourth insulating layer, the density of the fifth insulating layer is greater than that of the first insulating layer, and both the material of the fifth insulating layer and the material of the first insulating layer contain Si and O.

[0014] For example, in an oxide thin-film transistor according to at least one embodiment of the present disclosure, a gate is provided between the layer on which the source and drain are located and the oxide semiconductor layer, the insulating layer further includes a sixth insulating layer provided on the side of the second insulating layer away from the base substrate, and the gate is provided between the sixth insulating layer and the first insulating layer.

[0015] For example, in an oxide thin-film transistor according to at least one embodiment of the present disclosure, the difference in etching rates between the first insulating layer and the second insulating layer is 20 to 40 Å / s.

[0016] For example, in an oxide thin-film transistor according to at least one embodiment of the present disclosure, the etching rate for etching the first insulating layer is 55 to 90 Å / s, and the etching rate for etching the second insulating layer is 35 to 50 Å / s.

[0017] For example, in an oxide thin-film transistor according to at least one embodiment of the present disclosure, the difference in etching rates between the first insulating layer and the second insulating layer is 20 to 40 Å / s, and the difference in etching rates between the first insulating layer and the third insulating layer is 10 to 20 Å / s.

[0018] For example, in an oxide thin-film transistor according to at least one embodiment of the present disclosure, the etching rate for etching the first insulating layer is 55 to 90 Å / s, the etching rate for etching the second insulating layer is 35 to 50 Å / s, and the etching rate for etching the third insulating layer is 45 to 70 Å / s.

[0019] For example, in an oxide thin-film transistor according to at least one embodiment of the present disclosure, the etching solution used for etching the first insulating layer, the second insulating layer, and the third insulating layer is a mixture of NH3F and HF, and the mass percentage contents of NH3F and HF in the mixture of NH3F and HF are 29.8% to 30.2% and 5.9% to 6.1%, respectively.

[0020] For example, in an oxide thin film transistor according to at least one embodiment of the present disclosure, the thickness of the first insulating layer is 1000 to 4000 Å, the thickness of the second insulating layer is 100 to 2000 Å, and the thickness of the third insulating layer is 700 to 1000 Å.

[0021] For example, in an oxide thin film transistor according to at least one embodiment of the present disclosure, under a temperature condition of 200°C to 350°C, the oxygen release amount of the second insulating layer, the first insulating layer, and the third insulating layer stacked is smaller than the total oxygen release amount of the single-layer second insulating layer, the first insulating layer, and the third insulating layer within the same temperature range.

[0022] For example, in an oxide thin film transistor according to at least one embodiment of the present disclosure, when the temperature is higher than 300°C, the oxygen release amount of the first insulating layer is higher than the oxygen release amount of the second insulating layer when the temperature is higher than 300°C.

[0023] For example, in an oxide thin film transistor according to at least one embodiment of the present disclosure, when the temperature is higher than 300°C, the oxygen release amount of the first insulating layer is higher than the oxygen release amount of the second insulating layer or the third insulating layer when the temperature is higher than 300°C.

[0024] At least one embodiment of the present disclosure further provides a display device including the oxide thin film transistor according to any one of the above items.

[0025] At least one embodiment of the present disclosure further provides a method for manufacturing an oxide thin film transistor, the manufacturing method including the steps of providing a base substrate, forming an oxide semiconductor layer on the base substrate, forming a first insulating layer on a side of the oxide semiconductor layer away from the base substrate, and forming a second insulating layer on a side of the first insulating layer away from the base substrate, wherein the density of the second insulating layer is greater than the density of the first insulating layer, and the second insulating layer is farther from the base substrate than the first insulating layer.

[0026] The manufacturing method according to at least one embodiment of the present disclosure further includes a step of forming a third insulating layer on the side of the first insulating layer close to the base substrate, and the density of the third insulating layer is greater than the density of the first insulating layer.

[0027] For example, in the manufacturing method according to at least one embodiment of the present disclosure, the step of forming the oxide semiconductor layer includes a step of applying a first oxide semiconductor thin film and performing a patterning process to form a first oxide semiconductor layer, and a step of applying a second oxide semiconductor thin film on the first oxide semiconductor layer and performing a patterning process to form a second oxide semiconductor layer, and the density of the second oxide semiconductor layer is greater than the density of the first oxide semiconductor layer.

[0028] For example, the manufacturing method according to at least one embodiment of the present disclosure further includes a step of applying a metal electrode thin film on the side of the oxide semiconductor layer away from the base substrate and performing a patterning process on the metal electrode thin film to form a source and a drain spaced apart from each other, and the oxide semiconductor layer and the insulating layer are in contact with each other in the region between the source and the drain.

[0029] For example, the manufacturing method according to at least one embodiment of the present disclosure further includes a step of applying a gate thin film on the base substrate, performing a patterning process on the gate thin film to form a gate, and applying a gate insulating layer thin film on the gate to form a gate insulating layer before forming the oxide semiconductor layer, and the material of the portion of the gate insulating layer in contact with the oxide semiconductor layer is an oxide insulating material.

[0030] For example, the manufacturing method according to at least one embodiment of the present disclosure further includes a step of applying a gate thin film between the layer where the source and the drain are located and the oxide semiconductor layer, performing a patterning process on the gate thin film to form a gate, and forming a fourth insulating layer on the gate.

[0031] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the drawings of the embodiments are briefly introduced below, and as will be apparent, the drawings described below relate only to some embodiments of this disclosure and do not limit this disclosure. [Brief explanation of the drawing]

[0032] [Figure 1] Figure 1 is a schematic diagram of the cross-sectional structure of an oxide thin-film transistor. [Figure 2] Figure 2 is a schematic diagram of the cross-sectional structure of an oxide thin-film transistor according to one embodiment of the present disclosure. [Figure 3] Figure 3 is a schematic diagram of the cross-sectional structure of another oxide thin-film transistor according to one embodiment of the present disclosure. [Figure 4] Figure 4 is a schematic cross-sectional diagram of yet another oxide thin-film transistor according to one embodiment of the present disclosure. [Figure 5] Figure 5 is a schematic diagram of the cross-sectional structure of yet another oxide thin-film transistor according to one embodiment of the present disclosure. [Figure 6] Figure 6 is a schematic diagram of the cross-sectional structure of yet another oxide thin-film transistor according to one embodiment of the present disclosure. [Figure 7A] Figure 7A is a test diagram showing the oxygen release capacity of the laminated insulating layers and each individual layer shown in Figure 3. [Figure 7B] Figure 7B is a test diagram showing the oxygen release capacity of the laminated insulating layers and each individual layer shown in Figure 3. [Figure 7C] Figure 7C is a test diagram showing the oxygen release capacity of the laminated insulating layers and each individual layer shown in Figure 3. [Figure 7D] Figure 7D is a test diagram showing the oxygen release capacity of the laminated insulating layers and each individual layer shown in Figure 3. [Figure 8A] Figure 8A is a test diagram showing the nitric oxide emission capacity of laminated and single-layer insulating layers as shown in Figure 3. [Figure 8B] Figure 8B is a test diagram showing the nitric oxide emission capacity of laminated and single-layer insulating layers as shown in Figure 3. [Figure 8C]Figure 8C is a test diagram showing the nitric oxide emission capacity of laminated and single-layer insulating layers as shown in Figure 3. [Figure 8D] Figure 8D is a test diagram showing the nitric oxide emission capacity of laminated and single-layer insulating layers as shown in Figure 3. [Figure 9] Figure 9 is a block diagram of a display device according to one embodiment of the present disclosure. [Figure 10] Figure 10 is a flowchart of a method for manufacturing an oxide thin-film transistor according to one embodiment of the present disclosure. [Figure 11] Figure 11 is a flowchart of a method for manufacturing another thin-film transistor according to one embodiment of the present disclosure. [Figure 12A] Figure 12A shows the process of a method for manufacturing a thin-film transistor according to one embodiment of the present disclosure. [Figure 12B] Figure 12B shows the process of a method for manufacturing a thin-film transistor according to one embodiment of the present disclosure. [Figure 12C] Figure 12C shows the process of a method for manufacturing a thin-film transistor according to one embodiment of the present disclosure. [Figure 12D] Figure 12D shows the process of a method for manufacturing a thin-film transistor according to one embodiment of the present disclosure. [Figure 12E] Figure 12E shows the process of a method for manufacturing a thin-film transistor according to one embodiment of the present disclosure. [Figure 12F] Figure 12F shows the process of a method for manufacturing a thin-film transistor according to one embodiment of the present disclosure. [Figure 12G] Figure 12G shows the process of a method for manufacturing a thin-film transistor according to one embodiment of the present disclosure. [Figure 12H] Figure 12H shows the process of a method for manufacturing a thin-film transistor according to one embodiment of the present disclosure. [Figure 12I] Figure 12I shows the process of a method for manufacturing a thin-film transistor according to one embodiment of the present disclosure. [Figure 13A] Figure 13A shows a process for yet another thin-film transistor manufacturing method according to one embodiment of the present disclosure. [Figure 13B]Figure 13B shows a process for manufacturing yet another thin-film transistor according to one embodiment of the present disclosure. [Figure 13C] Figure 13C shows a process for yet another thin-film transistor manufacturing method according to one embodiment of the present disclosure. [Figure 13D] Figure 13D shows a process for yet another thin-film transistor manufacturing method according to one embodiment of the present disclosure. [Figure 13E] Figure 13E shows a process for yet another thin-film transistor manufacturing method according to one embodiment of the present disclosure. [Figure 13F] Figure 13F shows the process of yet another thin-film transistor manufacturing method according to one embodiment of the present disclosure. [Figure 13G] Figure 13G shows the process of yet another thin-film transistor manufacturing method according to one embodiment of the present disclosure. [Figure 13H] Figure 13H shows a process for manufacturing yet another thin-film transistor according to one embodiment of the present disclosure. [Figure 13I] Figure 13I shows a process for manufacturing yet another thin-film transistor according to one embodiment of the present disclosure. [Modes for carrying out the invention]

[0033] To further clarify the purpose, technical solutions, and advantages of the embodiments of this disclosure, the technical solutions of the embodiments of this disclosure will be described clearly and completely below with reference to the drawings of the embodiments of this disclosure. Clearly, the embodiments described are a part of the embodiments of this disclosure, but not all of them. Any other embodiments that a person skilled in the art could obtain without creative work based on the embodiments of this disclosure described are all within the scope of this disclosure.

[0034] Unless otherwise defined, technical or scientific terms used in this disclosure have the general meanings that a person skilled in the art would understand. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, number, or importance, but are merely used to distinguish different components. Similar terms such as “includes” or “incorporates” are intended to cover the elements or components listed after the term and their equivalents, but not to exclude other elements or components. Similar terms such as “connected” or “linked” are not limited to physical or mechanical connections, but may include direct or indirect electrical connections. “Up,” “down,” “left,” “right,” etc., are merely used to indicate relative positions, and such relative positions may change as the absolute position of the object being described changes.

[0035] Compared to silicon-based and organic semiconductor thin-film transistors, oxide semiconductor thin-film transistors (FIBCs) have higher mobility, making them increasingly important in the high-end display field. With the gradual development of electronic products, the development of high-mobility oxide semiconductor thin-film transistors has become a focus of research and development for display panel manufacturers. However, as the mobility of oxide semiconductor thin-film transistors improves, the requirements for their stability also increase. High-temperature processes are increasingly used to improve the stability of high-mobility materials in oxide semiconductor thin-film transistors, resulting in higher requirements for the oxygen supply capacity of the insulating layer in contact with or adjacent to the oxide semiconductor. This solves the problem of current oxide semiconductor thin-film transistors becoming conductive under the influence of high-temperature processes, for example, by reducing the oxide semiconductor to a pure metal, causing the semiconductor to become conductive and thus losing its semiconductor properties. In subsequent high-temperature processes, the metal oxide semiconductor layer functions as a channel layer, and the chemical bond between the metal and oxygen is easily broken, and the formed oxygen easily escapes. Therefore, the above-mentioned problem exists when the metal oxide semiconductor layer functions as a channel layer.

[0036] For example, Figure 1 is a schematic cross-sectional diagram of an oxide thin-film transistor. As shown in Figure 1, the oxide thin-film transistor 10 includes a base substrate 01, a gate 02 installed on the base substrate 01, a gate insulating layer 03, a metal oxide semiconductor layer 04, a source 05, a drain 06, and a passivation layer 07. The passivation layer 07 on the oxide semiconductor layer 04 plays a role in protecting the metal oxide semiconductor, preventing external impurities such as H and O from entering the metal oxide semiconductor. The material of the passivation layer 07 is, for example, one or more of silicon oxide, silicon nitride, and silicon oxynitride, or a laminate formed of at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0037] In some embodiments, a passivation layer (also called a non-metallic oxide insulating layer) is directly placed on the metal oxide semiconductor layer. In some embodiments, a metal oxide insulating layer, such as insulating aluminum oxide or insulating copper oxide, is placed between the passivation layer and the metal oxide semiconductor layer, serving, for example, to insulate the source and drain.

[0038] As needs to be explained, there is a clear difference in the nitrogen content between silicon oxide and silicon oxynitride in the embodiments of this disclosure. As those skilled in the art will know, when actually testing the SiO film layer, a certain amount of nitrogen is present because it is necessary to use a gas component containing nitrogen when manufacturing silicon oxide, and a certain amount of nitrogen is unavoidable.

[0039] First, silicon nitride is obtained by reacting silane and ammonia under appropriate conditions. The formed silicon nitride has a high hydrogen content, and some hydrogen elements remain in the silicon nitride. In the subsequent high-temperature process, the hydrogen present in the silicon nitride reacts with the free oxygen remaining in the oxide semiconductor layer 04, further causing the loss of oxygen elements in the oxide semiconductor layer 04. Furthermore, the remaining hydrogen breaks the silicon-oxygen bonds in silicon dioxide at high temperatures. The remaining hydrogen consumes the oxygen atoms generated after the silicon-oxygen bonds are broken. Finally, the remaining hydrogen breaks the metal-oxygen bonds in the oxide semiconductor layer, making the oxide semiconductor layer conductive. Next, when patterning the passivation layer thin film in a photolithography process to form the passivation layer 07, the etching solution used is a mixture of NH3F and HF, which also introduces hydrogen elements. These hydrogen elements also react with the free oxygen remaining in the oxide semiconductor layer 04, further causing the loss of oxygen elements in the oxide semiconductor layer 04.

[0040] The inventors of this disclosure recognize that by adjusting the structure, material, thickness, number of layers, and density of an insulating layer adjacent to or in contact with an oxide semiconductor layer, the insulating layer adjacent to or in contact with the oxide semiconductor layer can have sufficient oxygen supply capacity to the oxide semiconductor layer. For example, by placing an insulating layer formed of a multilayer insulating oxide (e.g., silicon oxide, titanium oxide, etc.) of two or three layers on an oxide semiconductor layer and adjusting the density of the multilayer insulating oxide, it is possible to increase the difficulty of liquids or gases entering the dense insulating layer from the outside, thereby reducing the risk of hydrogen elements in the upper silicon nitride layer entering the lower insulating layer, preventing the free oxygen in the lower layer from volatilizing and escaping, firmly fixing the oxygen elements in the oxide semiconductor layer, reducing the loss of oxygen elements in the subsequent high-temperature annealing process, thereby ensuring the stability of the properties of the oxide thin-film transistor, and also providing greater room for adjustment in the development of subsequent processes, allowing for more flexible selection of subsequent processes.

[0041] For example, at least one embodiment of the present disclosure provides an oxide thin-film transistor comprising a base substrate, an oxide semiconductor layer installed on the base substrate, and an insulating layer installed on the side of the oxide semiconductor layer away from the base substrate, wherein the insulating layer is made of an oxide, and the insulating layer comprises a first insulating layer and a second insulating layer stacked together, wherein the density of the second insulating layer is greater than that of the first insulating layer, and the second insulating layer is further away from the base substrate than the first insulating layer, and the embodiment of the present disclosure adjusts the density and thickness of at least the first and second insulating layers to fix oxygen in the oxide semiconductor layer, thereby reducing the loss of oxygen elements in the oxide semiconductor layer during a subsequent high-temperature annealing process, and thereby ensuring the stability of the properties of the oxide thin-film transistor.

[0042] For example, Figure 2 is a schematic cross-sectional diagram of an oxide thin-film transistor according to one embodiment of the present disclosure. As shown in Figure 2, the oxide thin-film transistor 100 includes a base substrate 101, an oxide semiconductor layer 105 installed on the base substrate 101, and an insulating layer 108 installed on the side of the oxide semiconductor layer 105 away from the base substrate 101. The insulating layer 108 is made of an oxide, and the insulating layer 108 includes a laminated first insulating layer 108b and a second insulating layer 108a. The density of the second insulating layer 108a is greater than that of the first insulating layer 108b, and the second insulating layer 108a is further away from the base substrate 101 than the first insulating layer 108b. In Figure 2, the first insulating layer 108b of the insulating layer 108 is in contact with the oxide semiconductor layer 105.

[0043] For example, in the structure shown in Figure 2, the material of the insulating layer 108 is an oxide, and this oxide includes insulating oxides such as silicon dioxide (SiO2), aluminum oxide (Al2O3), titanium dioxide (TiO2), hafnium oxide (HfO2), tantalum oxide (Ta2O5), and zirconium oxide (ZrO2). When the oxide is silicon dioxide, silicon dioxide can be formed by the reaction of silane with nitrous oxide. In the structure shown in Figure 1, the insulating layer located on, adjacent to, or in contact with the semiconductor oxide is made of silicon nitride, which is formed by the reaction of silane and ammonia. Due to the difference in the reaction raw materials, the hydrogen content in oxide insulating materials, such as silicon dioxide, is smaller than that in nitride insulating materials. Both the first and second insulating layers are made of oxides, and the denser second insulating layer 108a separates from the base substrate 101, thereby preventing hydrogen elements in the passivation layer formed of hydrogen nitride on the side of the second insulating layer 108a away from the base substrate 101 from entering the oxide semiconductor layer 105.

[0044] As needs to be explained, the density of the first insulating layer 108b refers to the difficulty of a liquid or gas entering the first insulating layer 108b from the outside. The greater the density of the first insulating layer 108b, the more difficult it is for a liquid or gas to enter the first insulating layer 108b from the outside, or even if it is impossible for it to enter the first insulating layer 108b. The density of the second insulating layer 108a refers to the difficulty of a liquid or gas entering the second insulating layer 108a from the outside. The greater the density of the second insulating layer 108a, the more difficult it is for a liquid or gas to enter the second insulating layer 108a from the outside, or even if it is impossible for it to enter the second insulating layer 108a.

[0045] As shown in Figure 2, the materials of the first insulating layer 108b and the second insulating layer 108a may be the same or different. For example, both may be at least one of insulating oxides such as silicon dioxide (SiO2), aluminum oxide (Al2O3), titanium dioxide (TiO2), hafnium oxide (HfO2), tantalum oxide (Ta2O5), and zirconium oxide (ZrO2). The oxygen content in the denser second insulating layer 108a is lower than the oxygen content in the first insulating layer 108b.

[0046] For example, in one case, the materials of the first insulating layer 108b and the second insulating layer 108a contain at least O and Si atoms.

[0047] For example, when the materials of both the first insulating layer 108b and the second insulating layer 108a are silicon oxide (SiO2), the reaction equation for forming the first insulating layer 108b is Equation 1 [ka] The reaction temperature is between 200 and 350°C, for example, the reaction temperatures used are 210°C, 230°C, 250°C, 280°C, 300°C, or 340°C, and it can be determined that the molar ratio of Si:O in the first insulating layer 108b is 1:2, and the reaction equation for forming the second insulating layer 108a is Equation 2 [ka] The reaction temperature is between 200 and 350°C, for example, the reaction temperatures used are 210°C, 230°C, 250°C, 280°C, 300°C, or 340°C, and it can be determined that the molar ratio of Si:O in the second insulating layer 108a is 1:1.4, and that the molar ratio of silicon to oxygen in the second insulating layer 108a is greater than the molar ratio of silicon to oxygen in the first insulating layer 108b.

[0048] For example, by adjusting the molar ratio during the reaction between silane and nitrous oxide, the power of the reaction chamber, and the atmospheric pressure, it is possible to achieve different densities in the formed silicon dioxide. The smaller the molar ratio of Si:O in the first insulating layer 108b or the second insulating layer 108a, the denser the formed first insulating layer 108b or the second insulating layer 108a becomes. For example, the density of the second insulating layer 108a is greater than that of the first insulating layer 108b. The denser second insulating layer 108a is located on the side of the first insulating layer 108b that is further away from the base substrate 101. This makes it difficult for the etching solution used during the patterning process to enter the first insulating layer 108b, and further prevents the etching solution from entering the oxide semiconductor layer 105, thus reducing the risk of damage to the oxide semiconductor layer 105.

[0049] For example, as shown in Figure 2, the thickness of the second insulating layer 108a is smaller than the thickness of the first insulating layer 108b. Since the oxygen content in the denser second insulating layer 108a is smaller than the oxygen content in the less dense first insulating layer 108b, the first insulating layer 108b, which has a higher oxygen content, can be installed thicker, achieving the purpose of oxygen fixation. By supplying oxygen to the oxide semiconductor layer in this way, the risk of the oxide semiconductor layer 105 becoming conductive can be reduced.

[0050] For example, the base substrate 101 is formed of a rigid material or a flexible material. For example, the rigid material includes one of rigid glass and silicon wafer. The flexible material includes one of polyethylene naphthalate, polyethylene terephthalate, polyimide and flexible glass.

[0051] For example, Figure 3 is a schematic cross-sectional diagram of another oxide thin-film transistor according to one embodiment of the present disclosure, and as shown in Figure 3, the insulating layer 108 further includes a third insulating layer 108c, the material of the third insulating layer 108c is at least one of insulating oxides such as silicon dioxide (SiO2), aluminum oxide (Al2O3), titanium dioxide (TiO2), hafnium oxide (HfO2), tantalum oxide (Ta2O5), and zirconium oxide (ZrO2), and the material of the third insulating layer 108c may be the same as or different from the material of the first insulating layer 108b and the second insulating layer 108a. The insulating layer 108 shown in Figure 3 has a stacked three-layer structure, with the third insulating layer 108c installed on the side of the first insulating layer 108b closer to the base substrate 101. The density of the third insulating layer 108c is greater than that of the first insulating layer 108b, but less than or equal to that of the second insulating layer 108a. In this way, the third insulating layer 108c further prevents etching solution or hydrogen elements from entering the oxide semiconductor layer 105, further reducing the risk of the oxide semiconductor layer 105 becoming conductive.

[0052] For example, in one case, the molar ratio of Si:O in the third insulating layer 108c is 1:1.6, meaning that the density of the third insulating layer 108c is between that of the first insulating layer 108b and the second insulating layer 108a. If the density of the third insulating layer 108c is too high, the oxygen content in the third insulating layer 108c will be low, and its ability to supply oxygen to the first oxide semiconductor layer 105a and the second oxide semiconductor layer 105b, as described later, will be insufficient. If the density of the third insulating layer 108c is too low, the ability of the third insulating layer 108c to prevent external water, oxygen, etching solution, etc. from entering the first oxide semiconductor layer 105a and the second oxide semiconductor layer 105b will be poor.

[0053] For example, as shown in Figures 2 and 3, the oxide semiconductor layer 105 includes a stacked first oxide semiconductor layer 105a and a second oxide semiconductor layer 105b, where the density of the second oxide semiconductor layer 105b is greater than that of the first oxide semiconductor layer 105a, the second oxide semiconductor layer 105b is further away from the base substrate 101 than the first oxide semiconductor layer 105a, and the denser second oxide semiconductor layer 105b further prevents etching solution or hydrogen elements from entering the second oxide semiconductor layer 105b, that is, further reduces the risk of the first oxide semiconductor layer 105a becoming conductive, and ensures the semiconductor properties of the first oxide semiconductor layer 105a.

[0054] As needs to be explained, the mobility of the denser second oxide semiconductor layer 105b is lower than that of the first oxide semiconductor layer 105a. The second oxide semiconductor layer 105b primarily serves to prevent damage to the first oxide semiconductor layer 105a due to etching, while the first oxide semiconductor layer 105a plays the role of the main semiconductor.

[0055] Furthermore, as needs to be explained, the density of the first oxide semiconductor layer 105a refers to the difficulty of a liquid or gas entering the first oxide semiconductor layer 105a from the outside. The greater the density of the first oxide semiconductor layer 105a, the more difficult it becomes for a liquid or gas to enter the first oxide semiconductor layer 105a from the outside, or even if it becomes impossible for it to enter the first oxide semiconductor layer 105a. The density of the second oxide semiconductor layer 105b refers to the difficulty of a liquid or gas entering the second oxide semiconductor layer 105b from the outside. The greater the density of the second oxide semiconductor layer 105b, the more difficult it becomes for a liquid or gas to enter the second oxide semiconductor layer 105b from the outside, or even if it becomes impossible for it to enter the second oxide semiconductor layer 105b.

[0056] For example, the materials of the first oxide semiconductor layer 105a and the second oxide semiconductor layer 105b may be the same or different. The materials of the first oxide semiconductor layer 105a and the second oxide semiconductor layer 105b include at least one n-type semiconductor material such as zinc oxide (ZnO), indium oxide (In2O3), indium zinc oxide (IZO), aluminum-doped zinc oxide (AZO), boron-doped zinc oxide (BZO), magnesium-doped zinc oxide (MZO), zinc tin oxide (ZTO), indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), gallium zinc oxide (GZO), indium tin oxide (ITO), hafnium-indium zinc oxide (HIZO), and tin oxide (SnO2), and at least one p-type semiconductor material such as stannous oxide (SnO) and cuprous oxide (Cu2O). For example, the first oxide semiconductor layer 105a and the second oxide semiconductor layer 105b can be formed by methods such as magnetron sputtering, reactive sputtering, anodizing, or spin coating.

[0057] For example, the thicknesses of the first oxide semiconductor layer 105a and the second oxide semiconductor layer 105b may be equal or not. For example, the thickness of the first oxide semiconductor layer 105a may be greater than the thickness of the second oxide semiconductor layer 105b. The thickness of the first oxide semiconductor layer 105a may be 5 nm to 200 nm, and the thicknesses of the second oxide semiconductor layer 105b may be 3 nm to 150 nm. For example, the thickness of the first oxide semiconductor layer 105a may be 50 nm, 100 nm, 150 nm, or 200 nm. The thickness of the second oxide semiconductor layer 105b may be 30 nm, 80 nm, 120 nm, or 150 nm.

[0058] For example, as shown in Figures 2 and 3, a source 106 and a drain 107 are placed between the oxide semiconductor layer 105 and the insulating layer 108, spaced apart from each other.

[0059] For example, the materials of the source 106 and drain 107 may include one or more combinations of metals such as molybdenum (Mo), chromium (Cr), titanium (Ti), aluminum (Al), aluminum alloys, and copper (Cu).

[0060] For example, in one case, the materials of the source 106 and drain 107 are copper-based metals. Copper metals have low resistivity and excellent conductivity, and therefore, the signal transmission speed of the source 106 and drain 107 can be improved, and the display quality can be improved.

[0061] For example, the copper-based metal is a copper-based metal alloy with stable properties, such as copper (Cu), copper-zinc alloy (CuZn), copper-nickel alloy (CuNi), or copper-zinc-nickel alloy (CuZnNi).

[0062] For example, the thickness of the source 106 and drain 107 may be 150 to 500 nm, for example, 150 nm, 220 nm, 280 nm, 320 nm, 370 nm, 400 nm, 450 nm, and 500 nm, respectively.

[0063] For example, in Figure 2, the surfaces of the source 106 and drain 107 that are away from the base substrate 101 are in contact with the first insulating layer 108b, and the surfaces of the source 106 and drain 107 that are close to the base substrate 101 are in contact with the second oxide semiconductor layer 105b. The oxide semiconductor layer 105 and the insulating layer 108 are in contact in the region between the source 106 and the drain 107. Specifically, the second oxide semiconductor layer 105b and the first insulating layer 108b are in contact in the region between the source 106 and the drain 107, thereby separating the source 106 and drain 107, which are installed in the same layer, by the lamination formed by the first insulating layer 108b and the second insulating layer 108a.

[0064] For example, in Figure 3, the surfaces of the source 106 and drain 107 that are away from the base substrate 101 are in contact with the third insulating layer 108c, and the surfaces of the source 106 and drain 107 that are close to the base substrate 101 are in contact with the second oxide semiconductor layer 105b. The oxide semiconductor layer 105 and the insulating layer 108 are in contact in the region between the source 106 and drain 107, and specifically, the second oxide semiconductor layer 105b and the third insulating layer 108c are in contact in the region between the source 106 and drain 107, thereby separating the source 106 and drain 107, which are installed in the same layer, by the lamination formed by the first insulating layer 108b, the second insulating layer 108a, and the third insulating layer 108c.

[0065] For example, as shown in Figures 2 and 3, a gate 102 is placed between the base substrate 101 and the oxide semiconductor layer 105, and a gate insulating layer 103 is placed between the gate 102 and the oxide semiconductor layer 105. The material of the portion of the gate insulating layer 103 that contacts the oxide semiconductor layer 105 is an oxide insulating material. The gate insulating layer 103 may be a single-layer structure or a multi-layer structure.

[0066] For example, the material of the gate 102 may be a combination of copper and other metals, such as copper / molybdenum (Cu / Mo), copper / titanium (Cu / Ti), copper / molybdenum-titanium alloy (Cu / MoTi), copper / molybdenum-tungsten alloy (Cu / MoW), copper / molybdenum-niobium alloy (Cu / MoNb), etc. The material of the gate 102 may also be a chromium-based metal, or a combination of chromium and other metals, such as chromium / molybdenum (Cr / Mo), chromium / titanium (Cr / Ti), chromium / molybdenum-titanium alloy (Cr / MoTi), etc., and for example, the gate thickness is 1000 to 10000 Å.

[0067] For example, in Figures 2 and 3, on the main surface of the base substrate 101 on which each film layer structure is installed, the gate insulating layer 103 includes a first gate insulating layer 103a, a second gate insulating layer 103b, a third gate insulating layer 103c, and a fourth gate insulating layer 103d, which are stacked in the direction from the side closer to the base substrate 101 to the side further away from the base substrate 101. In other words, the gate insulating layer 103 has a four-layer stacked structure, and the layer structure of the gate insulating layer 103 that is in contact with the oxide semiconductor layer 105 is the fourth gate insulating layer. The fourth gate insulating layer 103d is made of at least one insulating oxide such as silicon dioxide (SiO2), aluminum oxide (Al2O3), titanium dioxide (TiO2), hafnium oxide (HfO2), tantalum oxide (Ta2O5), and zirconium oxide (ZrO2), and the materials of the first gate insulating layer 103a, the second gate insulating layer 103b, and the third gate insulating layer 103c are all insulating nitrides, for example, the insulating nitride is silicon nitride (SiN x ) and aluminum nitride (AlN x ) and include at least one of the following.

[0068] For example, the thickness of the second gate insulating layer 103b is greater than the thickness of the first gate insulating layer 103a and greater than the thickness of the third gate insulating layer 103c, and the thicknesses of the first gate insulating layer 103a and the third gate insulating layer 103c may each be 50 to 100 angstroms, the density of the first gate insulating layer 103a and the density of the third gate insulating layer 103c are both greater than the density of the second gate insulating layer 103b, the hydrogen content in the first gate insulating layer 103a and the third gate insulating layer 103c is low, and the content of silane and ammonia in the reaction raw materials used is low, therefore the first gate insulating layer It is not possible to form 103a and the third gate insulating layer 103c on a large scale. In the structure of the display panel including the thin-film transistor, a transparent conductive metal oxide formed of indium tin oxide or the like exists on the side of the gate 102 closer to the base substrate 101. Therefore, in order to prevent the transparent conductive metal oxide from being reduced, the first gate insulating layer 103a needs to be formed under low hydrogen conditions. Similarly, in order to prevent the hydrogen element in the third gate insulating layer 103c from diffusing into the oxide semiconductor layer 105 and becoming conductive, the third gate insulating layer 103c needs to be formed under low hydrogen conditions. The thickness of the second gate insulating layer 103b is 2000 to 4000 angstroms. The formation of the second gate insulating layer 103b requires high-speed deposition. This improves the film deposition rate and enables large-scale production. However, the formed second gate insulating layer 103b has a high silane content, resulting in a high content of silicon hydrogen bonds.

[0069] As needs to be explained, the dielectric constant of silicon dioxide is 3.9 F / m, and the dielectric constant of silicon nitride is 7 F / m. Under the condition that silicon dioxide and silicon nitride have the same film thickness, silicon nitride has a higher capacitance. For example, the formula for capacitance is C = εS / 4πkd, where ε is the dielectric constant. Methods for increasing capacitance include using a high dielectric constant material and reducing the film thickness of the high dielectric constant material. However, the formula for the electric field is E = U / d, where d is the film thickness. As the film thickness decreases, the electric field strength increases, which makes the space between electrodes more susceptible to destruction. Therefore, typically, high dielectric constant materials are used to increase capacitance. For example, if the entire gate insulating layer is placed in the silicon oxide layer without a silicon nitride layer, the required thickness of the silicon oxide layer becomes very large. As the thickness of the silicon oxide layer increases, the mobility of the thin-film transistor decreases. Furthermore, without the underlying silicon nitride layer, sodium or potassium ions in the base substrate affect the characteristics of the thin-film transistor, reducing its stability and ultimately affecting the mobility of the final oxide thin-film transistor.

[0070] For example, Figure 4 is a schematic cross-sectional diagram of yet another oxide thin-film transistor according to one embodiment of the present disclosure. Unlike the structure of the bottom-gate type oxide thin-film transistors shown in Figures 2 and 3, the oxide thin-film transistor in Figure 4 is a top-gate type thin-film transistor. In the oxide thin-film transistor 100 shown in Figure 4, the gate 102 is located between the layer where the source 106 and drain 107 are located and the oxide semiconductor layer 105. The insulating layer 108 further includes a fourth insulating layer 108d located between the first insulating layer 108b and the second insulating layer 108a. The gate 102 is located between the fourth insulating layer 108d and the first insulating layer 108b. The oxide semiconductor layer 105 includes a first oxide semiconductor layer 105a and a second oxide semiconductor layer 105b.

[0071] For example, the material of the fourth insulating layer 108d may be at least one of insulating oxides such as silicon dioxide (SiO2), aluminum oxide (Al2O3), titanium dioxide (TiO2), hafnium oxide (HfO2), tantalum oxide (Ta2O5), and zirconium oxide (ZrO2), and the thickness of the fourth insulating layer 108d is in the range of 10 nm to 180 nm, for example, the thickness of the fourth insulating layer 108d may be 15 nm, 35 nm, 45 nm, 90 nm, 100 nm, 130 nm, 160 nm, or 180 nm.

[0072] For example, Figure 5 is a schematic cross-sectional diagram of yet another oxide thin-film transistor according to one embodiment of the present disclosure, and the structure of the oxide thin-film transistor shown in Figure 5 is also a top-gate type structure, and as shown in Figure 5, the insulating layer 108 further includes a fifth insulating layer 108e installed between the first insulating layer 108b and the fourth insulating layer 108d, the density of the fifth insulating layer 108e is greater than the density of the first insulating layer 108a, thereby preventing etching solution or hydrogen elements used when forming the source 106 and drain 107 from entering the oxide semiconductor layer 105.

[0073] For example, the material of the fifth insulating layer 108e and the first insulating layer 108b may be the same, and may be at least one of insulating oxides such as silicon dioxide (SiO2), aluminum oxide (Al2O3), titanium dioxide (TiO2), hafnium oxide (HfO2), tantalum oxide (Ta2O5), and zirconium oxide (ZrO2), but the density of the fifth insulating layer 108e is greater than the density of the fourth insulating layer 108d. For example, the thicknesses of the first insulating layer 108a and the fifth insulating layer 108e may be equal or unequal, and in one example, the thickness of the first insulating layer 108a is greater than the thickness of the fifth insulating layer 108e. For example, the thickness of the first insulating layer 108a may be 20 nm, 45 nm, 65 nm, 90 nm, 100 nm, or 200 nm, and the thickness of the fifth insulating layer 108e may be in the range of 8 nm to 150 nm, for example, 10 nm, 15 nm, 30 nm, 50 nm, 80 nm, 120 nm, or 150 nm.

[0074] For example, in one case, the materials of the fifth insulating layer 108e and the first insulating layer 108b both contain Si and O.

[0075] For example, Figure 6 is a schematic cross-sectional diagram of yet another oxide thin-film transistor according to one embodiment of the present disclosure, where, as shown in Figure 6, a gate 102 is located between the layer in which the source 106 and drain 107 are located and the oxide semiconductor layer 105, and the insulating layer 108 further includes a sixth insulating layer 108f located on the side of the second insulating layer 108b away from the base substrate 101, and the gate 102 is located between the sixth insulating layer 108f and the first insulating layer 108b. For example, the thickness of the sixth insulating layer 108f is greater than the thickness of the first insulating layer 108a and greater than the thickness of the second insulating layer 108b, and the material of the sixth insulating layer 108f may be at least one of insulating oxides such as silicon dioxide (SiO2), aluminum oxide (Al2O3), titanium dioxide (TiO2), hafnium oxide (HfO2), tantalum oxide (Ta2O5), and zirconium oxide (ZrO2), and the density of the sixth insulating layer 108f may be less than the density of the first insulating layer 108a.

[0076] As needs to be explained, the density of the fifth insulating layer 108e refers to the difficulty of a liquid or gas entering the fifth insulating layer 108e from the outside. The greater the density of the fifth insulating layer 108e, the more difficult it is for a liquid or gas to enter the fifth insulating layer 108e from the outside, or even if it is impossible for it to enter the fifth insulating layer 108e. The density of the sixth insulating layer 108f refers to the difficulty of a liquid or gas entering the sixth insulating layer 108f from the outside. The greater the density of the sixth insulating layer 108f, the more difficult it is for a liquid or gas to enter the sixth insulating layer 108f from the outside, or even if it is impossible for it to enter the sixth insulating layer 108f.

[0077] For example, as shown in Figure 3, the insulating layer 108 includes a first insulating layer 108b, a second insulating layer 108a, and a third insulating layer 108c, which are stacked in order. A thermal volatile mass spectrometer (model: ESCO TDS1200) was used to test the amount of oxygen released from individual layers of the first insulating layer 108b, the second insulating layer 108a, and the third insulating layer 108c contained in the insulating layer 108, and the test results are as follows. [Table 1]

[0078] As shown in Table 1, when a second insulating layer of 500 Å, a first insulating layer of 3000 Å, and a third insulating layer of 500 Å are laminated, when heated to 550°C, the oxygen release from the laminated second insulating layer of 500 Å, the first insulating layer of 3000 Å, and the third insulating layer of 500 Å is essentially equal to the sum of the oxygen release from single layers of the second insulating layer of 500 Å, the first insulating layer of 3000 Å, and the third insulating layer of 500 Å in the same temperature range, and at 550°C, the oxygen in the first insulating layer, the second insulating layer, and the third insulating layer is basically and completely released. For example, in the temperature range of 200°C to 350°C, the oxygen release from single layers of the second insulating layer of 500 Å, the first insulating layer of 3000 Å, and the third insulating layer of 500 Å is 1.0 × 10⁻¹⁰ Å, respectively. 13 , 5.6×10 13 and 2.2 × 10 13 Therefore, when a second insulating layer of 500 Å, a first insulating layer of 3000 Å, and a third insulating layer of 500 Å are laminated, the amount of oxygen released from the laminated second insulating layer of 500 Å, the first insulating layer of 3000 Å, and the third insulating layer of 500 Å when heated to a temperature of 350°C is 2.8 × 10⁻¹⁰ 13 The oxygen release amount is much smaller than the sum of the oxygen release amounts of the single-layer second insulating layer (500 Å), first insulating layer (3000 Å), and third insulating layer (500 Å) within the same temperature range. Therefore, within the same heating temperature range, the oxygen release amount of the laminated structure formed after laminating the second insulating layer (500 Å), first insulating layer (3000 Å), and third insulating layer (500 Å) is clearly reduced, thereby demonstrating that the laminated insulating layers have an excellent oxygen fixation effect in a typical high-temperature process (temperature 200°C to 350°C). Similarly, a laminated structure formed with a second insulating layer (500 Å), first insulating layer (2000 Å), and third insulating layer (500 Å) also has very good oxygen fixation ability, and a laminated structure formed with a second insulating layer (500 Å), first insulating layer (1000 Å), and third insulating layer (500 Å) also has excellent oxygen fixation ability.

[0079] Similar tests have shown that other insulating layer lamination structures according to embodiments of this disclosure, such as the second insulating layer 500 Å / first insulating layer 2000 Å / third insulating layer 500 Å, and the second insulating layer 500 Å / first insulating layer 1000 Å / third insulating layer 500 Å, also exhibit excellent oxygen fixation capabilities, which are omitted here in detail.

[0080] For example, Figures 7A to 7D are test diagrams of the oxygen release capacity of the laminated insulating layers and each single layer shown in Figure 3. As shown in Figure 7A, the oxygen release of the single-layer third insulating layer of 500 Å is maximized when the heating temperature reaches 397°C. As shown in Figure 7B, the oxygen release of the single-layer first insulating layer of 3000 Å is maximized when the heating temperature reaches 398°C. As shown in Figure 7C, the oxygen release of the single-layer second insulating layer of 500 Å is maximized when the heating temperature reaches 389°C, and because the density of the second insulating layer of 500 Å is maximized, the maximum oxygen release from the single-layer second insulating layer of 500 Å is smaller than the maximum oxygen release from the single-layer third insulating layer of 500 Å, and also smaller than the maximum oxygen release from the single-layer first insulating layer of 3000 Å. As shown in Figure 7D, the stacked second insulating layer 500 Å, first insulating layer 3000 Å, and third insulating layer 500 Å exhibit maximum oxygen release when the heating temperature reaches 423°C, and the maximum amount of oxygen released is clearly smaller than the sum of the maximum oxygen releases from the single layers of the second insulating layer 500 Å, first insulating layer 3000 Å, and third insulating layer 500 Å. When this occurs, the oxygen release rate is at its maximum, and the temperature is significantly higher than the temperature at which the oxygen release rate is at its maximum with a single layer of the second insulating layer 500 Å, the first insulating layer 3000 Å, and the third insulating layer 500 Å. In other words, compared to a single layer of the second insulating layer 500 Å, the first insulating layer 3000 Å, and the third insulating layer 500 Å, the temperature required to reach maximum oxygen release is 20-30°C higher with the stacked second insulating layer 500 Å, the first insulating layer 3000 Å, and the third insulating layer 500 Å.

[0081] For example, in one instance, the amount of oxygen released from the first insulating layer at temperatures above 300°C is higher than the amount of oxygen released from the second insulating layer at temperatures above 300°C.

[0082] For example, in another case, the amount of oxygen released from the first insulating layer at temperatures above 300°C is higher than the amount of oxygen released from the second or third insulating layer at temperatures above 300°C.

[0083] For example, Figures 8A to 8D are test diagrams of the nitric oxide emission capacity of laminated and single-layer insulating layers shown in Figure 3. As shown in Figure 8A, the single-layer third insulating layer of 500 Å emits the maximum amount of nitric oxide when the heating temperature reaches 300°C. As shown in Figure 8B, the single-layer first insulating layer of 3000 Å emits the maximum amount of nitric oxide when the heating temperature reaches 301°C. As shown in Figure 8C, the single-layer second insulating layer of 500 Å emits the maximum amount of nitric oxide when the heating temperature reaches 370°C, and because the density of the second insulating layer of 500 Å is at its maximum, the maximum amount of nitric oxide emitted by the single-layer second insulating layer of 500 Å is smaller than the maximum amount of nitric oxide emitted by the single-layer third insulating layer of 500 Å, and also smaller than the maximum amount of nitric oxide emitted by the single-layer first insulating layer of 3000 Å. As shown in Figure 8D, the stacked second insulating layer 500 Å, first insulating layer 3000 Å, and third insulating layer 500 Å released the maximum amount of nitric oxide when the heating temperature reached 335°C, and the maximum amount of nitric oxide released was clearly lower than the sum of the maximum nitric oxide releases from the single layers of the second insulating layer 500 Å, first insulating layer 3000 Å, and third insulating layer 500 Å. Furthermore, the stacked second insulating layer 500 Å, first insulating layer 3000 Å, and third insulating layer 500 Å released the maximum amount of nitric oxide when the heating temperature reached 345°C, and this temperature is clearly higher than the temperature at which the maximum nitric oxide releases from the single layers of the second insulating layer 500 Å, first insulating layer 3000 Å, and third insulating layer 500 Å were maximized.

[0084] For example, the density of the film layer can be evaluated by the wet etching rate. The etching solution used is a mixture of NH3F and HF, with mass percentage contents of NH3F and HF being 29.8% to 30.2% and 5.9% to 6.1%, respectively. When the wet etching rate is higher than 60 Å / s, the oxygen fixation effect cannot be achieved.

[0085] For example, in the structure shown in Figure 3, when the material of the second insulating layer 108a is silicon dioxide, the wet etching rate of the second insulating layer 108a is 35-50 Å / s, and the wet etching rate of the third insulating layer is 45-70 Å / s. If the third insulating layer is too loose, a problem arises in which the third insulating layer breaks. The insulating layers are arranged in a three-layer structure, and the density of each layer of the insulating layer gradually decreases from the direction away from the base substrate towards the base substrate, which is advantageous for oxygen to be replenished in the oxide semiconductor layer from the direction away from the base substrate towards the base substrate. Subsequently, since an oxygen supply process is required after the passivation layer is formed, if the density of the second insulating layer 108a is too high or the thickness of the second insulating layer 108a is too large, it will be disadvantageous to carry out the oxygen supply process. Therefore, the thickness of the second insulating layer 108a is limited to 100-2000 Å. For example, in one example, the thickness of the first insulating layer 108b is 1000-4000 Å, the thickness of the second insulating layer 108a is 100-2000 Å, and the thickness of the third insulating layer 108c is 700-1000 Å. For example, in one example, the thickness of the second insulating layer 108b is 300-500 Å.

[0086] For example, in one case, the etching solution used to etch the first insulating layer 108b, the second insulating layer 108a, and the third insulating layer 108c is a mixture of NH3F and HF, with the mass percentage contents of NH3F and HF in the mixture being 29.8% to 30.2% and 5.9% to 6.1%, respectively. The difference in etching rates between the first insulating layer 108b and the second insulating layer 108a is 20 to 40 Å / s, the difference in etching rates between the first insulating layer 108b and the third insulating layer 108c is 10 to 20 Å / s, the etching rate for etching the first insulating layer 108b is 55 to 90 Å / s, the etching rate for etching the second insulating layer 108a is 35 to 50 Å / s, and the etching rate for etching the third insulating layer 108c is 45 to 70 Å / s.

[0087] At least one embodiment of the present disclosure further provides a display device, comprising an oxide thin-film transistor of any of the above embodiments. For example, Figure 9 is a block diagram of a display device according to one embodiment of the present disclosure. As shown in Figure 9, the display device 200 comprises the oxide thin-film transistor 100, and the display device 200 may be any product or component with display functions, such as a liquid crystal display device, electronic paper, organic light-emitting diode (OLED) display device, active-matrix organic light-emitting diode (AMOLED) display device, mobile phone, tablet computer, television, display, notebook computer, digital photo frame, or navigator.

[0088] At least one embodiment of the present disclosure further provides a method for manufacturing an oxide thin-film transistor, the method comprising the steps of providing a base substrate, forming an oxide semiconductor layer on the base substrate, forming a first insulating layer on the side of the oxide semiconductor layer away from the base substrate, and forming a second insulating layer on the side of the first insulating layer away from the base substrate, wherein the density of the second insulating layer is greater than that of the first insulating layer, and the second insulating layer is further away from the base substrate than the first insulating layer, and the embodiment of the present disclosure adjusts the density and thickness of at least the first and second insulating layers to fix oxygen in the oxide semiconductor layer, thereby reducing the loss of oxygen elements in the oxide semiconductor layer during a subsequent high-temperature annealing process, and thereby ensuring the stability of the properties of the oxide thin-film transistor.

[0089] For example, Figure 10 is a flowchart of a method for manufacturing a thin-film transistor according to one embodiment of the present disclosure, and as shown in Figure 10, the manufacturing method includes steps S11 to S14.

[0090] S11, the base substrate is provided.

[0091] S12, an oxide semiconductor layer is formed on the base substrate.

[0092] S13, A first insulating layer is formed on the side of the oxide semiconductor layer that is away from the base substrate.

[0093] S14, a second insulating layer is formed on the side of the first insulating layer that is away from the base substrate, the density of the second insulating layer is greater than that of the first insulating layer, and the second insulating layer is further away from the base substrate than the first insulating layer.

[0094] For example, the manufacturing method further includes the step of applying a thin film of the third insulating layer to the side of the first insulating layer closer to the base substrate to form the third insulating layer, wherein the density of the third insulating layer is greater than that of the first insulating layer.

[0095] For example, in this manufacturing method, the step of forming an oxide semiconductor layer includes applying a first oxide semiconductor thin film and performing a patterning process to form a first oxide semiconductor layer, and applying a second oxide semiconductor thin film on the first oxide semiconductor layer and performing a patterning process to form a second oxide semiconductor layer, wherein the density of the second oxide semiconductor layer is greater than that of the first oxide semiconductor layer.

[0096] For example, the manufacturing method further includes applying a metal electrode thin film to the side of the oxide semiconductor layer away from the base substrate, and performing a patterning process on the metal electrode thin film to form a spaced-out source and drain, wherein the oxide semiconductor layer and the insulating layer are in contact in the region between the source and drain.

[0097] For example, a manufacturing method according to at least one embodiment of the present disclosure further includes the steps of applying a gate thin film to a base substrate, performing a patterning process on the gate thin film to form a gate, and applying a gate insulating layer thin film on the gate to form a gate insulating layer, wherein the material of the portion of the gate insulating layer that contacts the oxide semiconductor layer is an oxide insulating material.

[0098] For example, Figure 11 is a flowchart of a method for manufacturing another thin-film transistor according to one embodiment of the present disclosure, and as shown in Figure 11, the manufacturing method includes steps S21 to S29.

[0099] S21 provides the base substrate.

[0100] S22, a gate thin film is applied to the base substrate, and a patterning process is performed on the gate thin film to form a gate.

[0101] S23, A gate insulating layer is formed by applying a gate insulating layer thin film to the gate.

[0102] In S24, a first oxide semiconductor thin film is applied to the gate insulating layer and a patterning process is performed to form a first oxide semiconductor layer.

[0103] In S25, a second oxide semiconductor thin film is applied to the first oxide semiconductor layer and a patterning process is performed to form a second oxide semiconductor layer, the density of which the second oxide semiconductor layer is greater than the density of the first oxide semiconductor layer.

[0104] In S26, a metal electrode thin film is applied to the side of the second oxide semiconductor layer away from the base substrate, and a patterning process is performed on the metal electrode thin film to form a source and drain that are spaced apart from each other.

[0105] S27, a first insulating layer is formed on the source and drain sides away from the base substrate.

[0106] S28, a second insulating layer is formed on the side of the first insulating layer that is away from the base substrate, and the density of the second insulating layer is greater than the density of the first insulating layer.

[0107] For example, the oxide semiconductor layer and the insulating layer are in contact in the region between the source and the drain.

[0108] S29, A passivation layer is formed by applying a passivation layer thin film onto the second insulating layer.

[0109] For example, Figures 12A to 12I show the process of a thin-film transistor manufacturing method according to one embodiment of the present disclosure.

[0110] As shown in Figure 12A, a base substrate 101 is provided, and the base substrate 101 uses either a rigid material or a flexible material. For example, the rigid material includes one of rigid glass and silicon wafer. The flexible material includes one of polyethylene naphthalate, polyethylene terephthalate, polyimide and flexible glass.

[0111] As shown in Figure 12B, a gate thin film 102' is applied to the base substrate 101, and a patterning process is performed on the gate thin film 102' to form the gate 102.

[0112] For example, the process includes depositing a gate thin film 102' on a base substrate 101 to form a gate thin film 102' of a metallic material by methods such as magnetron sputtering, electron beam deposition, or thermal deposition. Alternatively, a gate thin film 102' of a transparent conductive material may be formed by methods such as magnetron sputtering or optical coating. Subsequently, a single layer of photoresist (not shown) is coated onto the gate thin film 102', and a pattern of the gate 102 is formed by processes such as exposure, development, etching, and photoresist peeling. For example, spin coating, knife coating, or roll coating can be used for the photoresist coating.

[0113] For example, the material for gate 102 can be found in the related explanation above, and a detailed explanation is omitted here.

[0114] As shown in Figure 12C, a gate insulating layer thin film is applied to the gate 102 to form the gate insulating layer 103.

[0115] For example, a layer of photoresist (not shown) is coated on the gate insulating layer thin film, and processes such as exposure, development, etching, and photoresist stripping are performed to form a pattern of the gate insulating layer 103. For example, spin coating, knife coating, or roll coating can be used for the coating of the photoresist.

[0116] For example, the gate insulating layer 103 may have a multilayer stacked structure. As the formation process of each layer in the multilayer stacked structure, first, a layer of photoresist is coated on the corresponding gate insulating layer thin film, and then processes such as exposure, development, etching, and photoresist stripping are performed to form the layer structure of the corresponding gate insulating layer.

[0117] For example, the gate insulating layer 103 includes a first gate insulating layer 103a, a second gate insulating layer 103b, a third gate insulating layer 103c, and a fourth gate insulating layer 103d that are stacked. That is, the gate insulating layer 103 has a four-layer stacked structure. The layer structure in contact with the oxide semiconductor layer 105 of the gate insulating layer 103 is the fourth gate insulating layer 103d. The material of the fourth gate insulating layer 103d is at least one of insulating oxides such as silicon oxide (SiO2), aluminum oxide (Al2O3), titanium oxide (TiO2), hafnium oxide (HfO2), tantalum oxide (Ta2O5), and zirconium oxide (ZrO2). The materials of the first gate insulating layer 103a, the second gate insulating layer 103b, and the third gate insulating layer 103c are all insulating nitrides. For example, silicon nitride (SiN x ) and aluminum nitride (AlN x ) and the like.

[0118] For example, silicon oxide (SiO2) or silicon nitride (SiN x ) can also be deposited by a plasma enhanced chemical vapor deposition (PECVD) method to form the gate insulating layer thin film.

[0119] For example, the thickness of the second gate insulating layer 103b is greater than the thickness of the first gate insulating layer 103a and greater than the thickness of the third gate insulating layer 103c, and the thicknesses of the first gate insulating layer 103a and the third gate insulating layer 103c may each be 50 to 100 angstroms, and the density of both the first gate insulating layer 103a and the third gate insulating layer 103c is greater than the density of the second gate insulating layer 103b, and the hydrogen content in the first gate insulating layer 103a and the third gate insulating layer 103c is low, and the silane and ammonia content in the reaction raw materials used is also low, so it cannot be formed on a large scale. The thickness of the second gate insulating layer 103b is 2000 to 4000 angstroms, and the formation of the second gate insulating layer 103b can be carried out by rapid deposition and produced on a large scale, and the hydrogen content in the formed second gate insulating layer 103b is high.

[0120] As shown in Figure 12D, a first oxide semiconductor thin film is applied to the gate insulating layer 103 and a patterning process is performed to form the first oxide semiconductor layer 105a.

[0121] For example, the first oxide semiconductor layer 105a can be formed by methods such as magnetron sputtering, reactive sputtering, anodizing, or spin coating. The material and thickness of the first oxide semiconductor layer 105a can be described in the related explanations above, and a detailed explanation is omitted here.

[0122] As shown in Figure 12E, a second oxide semiconductor thin film is applied to the first oxide semiconductor layer 105a and a patterning process is performed to form a second oxide semiconductor layer 105b, and the density of the second oxide semiconductor layer 105b is greater than the density of the first oxide semiconductor layer 105a.

[0123] For example, the material of the second oxide semiconductor layer 105b may be the same as the material of the first oxide semiconductor layer, or it may be different. When the material of the second oxide semiconductor layer 105b is the same as the material of the first oxide semiconductor layer, the molar ratio of metal elements to oxygen elements in the first oxide semiconductor layer is smaller than the molar ratio of metal elements to oxygen elements in the second oxide semiconductor layer, and as a result the density of the second oxide semiconductor layer 105b is greater than the density of the first oxide semiconductor layer 105a.

[0124] For example, the second oxide semiconductor layer 105b can also be formed by methods such as magnetron sputtering, reactive sputtering, anodizing, or spin coating.

[0125] As shown in Figure 12F, a metal electrode thin film 106' is applied to the side of the second oxide semiconductor layer 105b that is away from the base substrate 101, and a patterning process is performed on the metal electrode thin film 106' to form a source 106 and drain 107 that are spaced apart from each other.

[0126] For example, the material and thickness of source 106 and drain 107 can be found in the related descriptions above, and a detailed explanation is omitted here.

[0127] As shown in Figure 12G, a first oxide insulating thin film is applied to the side of the source 106 and drain 107 away from the base substrate 101 to form the first insulating layer 108b.

[0128] For example, the material, thickness, and formation method of the first insulating layer 108b can be found in the related explanations above, and a detailed explanation is omitted here.

[0129] As shown in Figure 12H, a second insulating layer 108a is formed by applying a second oxide insulating thin film to the side of the first insulating layer 108b that is away from the base substrate 101. The density of the second insulating layer 108a is greater than that of the first insulating layer 108b, and the first insulating layer 108b is in contact with the second oxide semiconductor layer 105b.

[0130] For example, the second oxide semiconductor layer 105b and the first insulating layer 108b are in contact in the region between the source 106 and the drain 107.

[0131] For example, the material, thickness, and formation method of the second insulating layer 108a can be found in the related explanations above, and a detailed explanation is omitted here.

[0132] As shown in Figure 12I, a passivation layer thin film is applied on the second insulating layer 108a to form a passivation layer 109.

[0133] For example, a passivation layer can be formed by plasma chemical vapor deposition, and the material of the passivation layer 109 includes silicon nitride (SiNx), silicon oxide (SiOx), acrylic resin, etc. The passivation layer 109 can prevent external impurities or water vapor from entering the thin-film transistor and affecting its performance.

[0134] For example, a passivation layer thin film can be deposited on the second insulating layer 108a, and a photoresist can be coated onto the passivation layer thin film. The passivation layer thin film can then be processed by processes such as exposure, development, etching, and photoresist stripping to form the passivation layer.

[0135] For example, the passivation layer 109 prevents external impurities or water vapor from entering the thin-film transistor 100, thereby avoiding any impact on the performance of the thin-film transistor.

[0136] For example, Figures 13A to 13I illustrate the process of yet another thin-film transistor manufacturing method according to one embodiment of the present disclosure, and as shown in Figure 13A, the manufacturing method includes the following steps.

[0137] As shown in Figure 13A, a base substrate 101 is provided, and the material of the base substrate 101 can be found in the related description above, so a detailed explanation is omitted here.

[0138] As shown in Figure 13B, a buffer layer 104 is formed on the base substrate 101.

[0139] For example, the material of the buffer layer 104 includes at least one of silicon nitride (SiNx), silicon oxide (SiOx), etc.

[0140] As shown in Figure 13C, a first oxide semiconductor layer 105a is formed on the buffer layer 104. The material and thickness of the first oxide semiconductor layer 105a can be found in the related explanation above, and a detailed explanation is omitted here.

[0141] As shown in Figure 13D, a second oxide semiconductor layer 105b is formed on the first oxide semiconductor layer 105a. The material and thickness of the second oxide semiconductor layer 105b can be found in the related explanation above, and a detailed explanation is omitted here.

[0142] As shown in Figure 13E, a first insulating layer 108b is formed on the second oxide semiconductor layer 105b. The material, thickness, and formation method of the first insulating layer 108b can be found in the related explanations above, and a detailed explanation is omitted here.

[0143] As shown in Figure 13F, a gate thin film is applied to the first insulating layer 108b, and a patterning process is performed on the gate thin film to form the gate 102.

[0144] For example, the material, thickness, and formation method of the gate 102 can be found in the related explanations above, and a detailed explanation is omitted here.

[0145] As shown in Figure 13G, a fourth insulating thin film is applied to the gate 102 to form a fourth insulating layer 108d.

[0146] For example, the material and thickness of the fourth insulating layer 108d can be found in the related explanation above, and a detailed explanation is omitted here.

[0147] As shown in Figure 13H, a second insulating layer 108a is formed on the fourth insulating layer 108d. For example, the material and thickness of the second insulating layer 108a can be found in the related explanation above, and a detailed explanation is omitted here.

[0148] For example, in another example, for instance, in an example further comprising a fifth insulating layer 108e as shown in Figure 5, the material and thickness of the fifth insulating layer 108e can be found in the related description above, and a detailed explanation is omitted here.

[0149] As shown in Figure 13I, a via hole structure (not shown) is formed in the insulating layer 108, which is composed of a first insulating layer 108b, a second insulating layer 108a, and a fourth insulating layer 108d, penetrating the insulating layer 108. Next, a metal electrode thin film is applied to the second insulating layer 108a, and a patterning process is performed on the metal electrode thin film to form a source 106 and a drain 107 that are spaced apart from each other.

[0150] For example, in another example, for instance, in an example where a fifth insulating layer 108e is further formed, a via hole structure can be formed penetrating the insulating layer 108 in the insulating layer 108 composed of the first insulating layer 108b, the second insulating layer 108a, the fourth insulating layer 108d, and the fifth insulating layer 108e.

[0151] For example, in another example, for instance, in the example having a sixth insulating layer 108f as shown in Figure 6, a via-hole structure can be formed in the insulating layer 108 composed of the first insulating layer 108b, the second insulating layer 108a, and the sixth insulating layer 108f, with the material and thickness of the sixth insulating layer 108f referring to the related explanation above, and a detailed explanation is omitted here.

[0152] For example, the oxide thin-film transistor, display device, and method for manufacturing the oxide thin-film transistor according to the embodiments of this disclosure have at least one beneficial effect.

[0153] (1) The oxide thin-film transistor according to the embodiment of the present disclosure adjusts the structure, material, thickness, number of layers and density of the insulating layer so that the insulating layer adjacent to or in contact with the oxide semiconductor layer has sufficient oxygen supply capacity to the oxide semiconductor layer, thereby preventing the oxide semiconductor layer from becoming conductive.

[0154] (2) The oxide thin-film transistor according to the embodiment of the present disclosure reduces the loss of oxygen elements in the subsequent high-temperature annealing process by adjusting the density of the multilayer insulating oxide and fixing oxygen in the oxide semiconductor layer within the oxide semiconductor layer, thereby ensuring the stability of the properties of the oxide thin-film transistor and providing greater room for adjustment in the development of subsequent processes, allowing for more flexible selection of subsequent processes.

[0155] The following points need to be explained.

[0156] (1) The drawings of the embodiments of this disclosure relate only to the structures relating to the embodiments of this disclosure, and other structures should be referred to by conventional designs.

[0157] (2) For clarity, in the drawings illustrating embodiments of the present disclosure, the thickness of layers or regions is enlarged or reduced, i.e., these drawings are not drawn in actual proportion. To make it clear, when an element such as a layer, film, region or substrate is described as being located "above" or "below" another element, the element may be located "directly" above or below the other element, or an intermediate element may be present.

[0158] (3) Where there is no contradiction, new embodiments can be obtained by combining the embodiments and features of the embodiments of this disclosure with each other.

[0159] The above are merely specific embodiments of the present disclosure, but the scope of protection of the present disclosure is not limited thereto, and the scope of protection of the present disclosure should be in accordance with the scope of protection of the claims described above.

Claims

1. Oxide thin-film transistor, Base board and The oxide semiconductor layer installed on the base substrate, The oxide semiconductor layer includes an insulating layer installed on the side of the oxide semiconductor layer away from the base substrate, The insulating layer includes a first insulating layer and a second insulating layer that are stacked, wherein the density of the second insulating layer is greater than that of the first insulating layer, and the second insulating layer is further away from the base substrate than the first insulating layer. The materials of the first insulating layer and the second insulating layer contain at least O and Si atoms. The oxide semiconductor layer includes a stacked first oxide semiconductor layer and a second oxide semiconductor layer, wherein the density of the second oxide semiconductor layer is greater than that of the first oxide semiconductor layer. An oxide thin-film transistor in which the second oxide semiconductor layer is further away from the base substrate than the first oxide semiconductor layer.

2. An oxide thin-film transistor according to claim 1, wherein a source and a drain are provided between the oxide semiconductor layer and the insulating layer, spaced apart from each other, and the oxide semiconductor layer and the insulating layer are in contact in the region between the source and the drain.

3. The oxide thin-film transistor according to claim 2, wherein a passivation layer is provided on the side of the second insulating layer that is away from the base substrate.

4. The oxide thin-film transistor according to claim 3, wherein the material of the passivation layer contains silicon nitride.

5. An oxide thin-film transistor according to any one of claims 1 to 4, wherein a gate is provided between the base substrate and the oxide semiconductor layer, a gate insulating layer is provided between the gate and the oxide semiconductor layer, and the material of the portion of the gate insulating layer that contacts the oxide semiconductor layer is an oxide insulating material.

6. The oxide thin-film transistor according to claim 5, wherein the gate insulating layer includes a first gate insulating layer, a second gate insulating layer, a third gate insulating layer, and a fourth gate insulating layer that are stacked, and the material of the first gate insulating layer, the second gate insulating layer, and the third gate insulating layer is a nitride.

7. The oxide thin-film transistor according to claim 6, wherein the nitride comprises at least one of silicon nitride and aluminum nitride.

8. The oxide thin-film transistor according to claim 6, wherein the material of the first gate insulating layer, the second gate insulating layer, and the third gate insulating layer is silicon nitride.

9. The oxide thin-film transistor according to claim 6, wherein the thickness of the first gate insulating layer and the thickness of the third gate insulating layer are both smaller than the thickness of the second gate insulating layer.

10. The oxide thin-film transistor according to claim 9, wherein the thickness of both the first gate insulating layer and the third gate insulating layer is 50 angstroms to 100 angstroms.

11. The oxide thin-film transistor according to claim 6, wherein the density of the first gate insulating layer and the density of the third gate insulating layer are both greater than the density of the second gate insulating layer.

12. The oxide thin-film transistor according to any one of claims 6 to 11, wherein the material of the fourth gate insulating layer is the oxide insulating material, and the fourth gate insulating layer is in contact with the oxide semiconductor layer.

13. The oxide thin-film transistor according to claim 12, wherein the material of the fourth gate insulating layer is at least one of silicon oxide, aluminum oxide, titanium oxide, hafnium oxide, tantalum oxide, and zirconium oxide.

14. The oxide thin-film transistor according to claim 12, wherein the material of the fourth gate insulating layer is silicon oxide.

15. A display device comprising an oxide thin-film transistor according to any one of claims 1 to 14.

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