substrate

Abstract

To provide a circuit board that can accurately measure the temperature of components. [Solution] The substrate 1 comprises a plurality of conductive layers CL laminated via an insulating layer IL, the plurality of conductive layers CL include a first conductive layer CL1 on which a component to be measured for temperature is provided, and a second conductive layer CL2 different from the first conductive layer CL1, which is provided with a temperature information acquisition unit 32 that acquires temperature information indicating the temperature of the component 22, and at least a portion of the first region 41 on the first conductive layer CL1 on which the component 22 is provided and the second region 42 on the second conductive layer CL2 on which the temperature information acquisition unit 32 is provided overlap with each other when viewed along the lamination direction Z in which the plurality of conductive layers CL are laminated.

Description

Technical Field

[0001] The present invention relates to a substrate having a plurality of conductive layers.

Background Art

[0002] Conventionally, substrates on which components such as electronic components are mounted have been used. Among such components, there are those having temperature dependence in electrical characteristics. Therefore, when using components under an environment with temperature fluctuations, in order to make the components satisfy the intended electrical characteristics, it is conceivable to sense the temperature of the components and their surroundings and correct the electrical characteristics based on the sensed results. As a technique related to the sensing of the temperature of such components, for example, there is one described in Patent Document 1 whose citation is shown below.

[0003] Patent Document 1 describes a semiconductor device that measures the temperature of a component (a "semiconductor element" in Patent Document 1) using a temperature sensor. In this semiconductor device, two components are arranged to face each other with a conductive layer (a "conductor layer" in Patent Document 1) interposed therebetween, and each component is connected to the conductive layer via a via. A temperature sensor for detecting the temperature of the component is arranged on one side of these two components. The conductive layer extends laterally toward the side of the temperature sensor, and a thermally connected heat conduction member is provided. The heat of the component is transmitted to this heat conduction member via the via and the conductive layer, and further transmitted to the temperature sensor via an insulating layer (an "insulating film" in Patent Document 1).

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] As described above, in the semiconductor device described in Patent Document 1, heat from the component is transferred to the temperature sensor via vias, a conductive layer, a heat conductive member, and an insulating layer. Therefore, even if the substrate on which the component and the temperature sensor are mounted is configured as in the semiconductor device described in Patent Document 1, the component and the temperature sensor are spaced apart, making it difficult to accurately measure the temperature of the component with the temperature sensor.

[0006] Therefore, a circuit board capable of accurately measuring the temperature of components is required. [Means for solving the problem]

[0007] The characteristic configuration of the substrate according to the present invention is that it comprises a plurality of conductive layers laminated with an insulating layer in between, the plurality of conductive layers including a first conductive layer on which a component to be measured for temperature is provided, and a second conductive layer different from the first conductive layer, which is provided with a temperature information acquisition unit that acquires temperature information indicating the temperature of the component, and at least a portion of the first region on the first conductive layer on which the component is provided and the second region on the second conductive layer on which the temperature information acquisition unit is provided overlap with each other when viewed along the lamination direction in which the plurality of conductive layers are laminated.

[0008] With this configuration, the temperature information acquisition unit can be positioned in close proximity to the component to be measured, by arranging it so that at least a portion of it overlaps with the component along the stacking direction. Therefore, a substrate capable of accurately measuring the temperature of the component can be realized. [Brief explanation of the drawing]

[0009] [Figure 1] This is a circuit diagram of a circuit installed on a circuit board. [Figure 2] This is an image illustrating a cross-section of a circuit board. [Figure 3] This is a plan view of the first layer of the conductive layer. [Figure 4] This is a plan view of the second layer of the conductive layer. [Figure 5] This is a plan view of the third conductive layer. [Figure 6] This is a plan view of the fourth conductive layer. [Modes for carrying out the invention]

[0010] The substrate according to the present invention is configured to accurately measure the temperature of components. The substrate 1 of this embodiment will be described below. However, the substrate 1 is not limited to the following embodiment and can be modified in various ways without departing from the spirit of the invention.

[0011] Figure 1 is a circuit diagram of which a part is formed on the substrate 1 (see Figure 2) of this embodiment. Figure 1 shows a circuit consisting of a calculation unit 10, a potential detection circuit unit 20, and a temperature detection circuit unit 30.

[0012] The potential detection circuit 20 is configured to include at least two resistors connected in series with each other. In this embodiment, the potential detection circuit 20 is configured to include resistor 21 and resistor 22. A voltage V1 is applied to one terminal 21A of resistor 21, and the other terminal 21B of resistor 21 is connected to one terminal 22A of resistor 22. The other terminal 22B of resistor 22 is connected to ground potential. In this embodiment, "connection" means "electrically connected" unless otherwise specified.

[0013] The temperature detection circuit section 30 is composed of a resistor 31 and a thermistor 32 (an example of a "temperature information acquisition section") connected in series with each other. A voltage V2 is applied to one terminal 31A of the resistor 31, and the other terminal 31B of the resistor 31 is connected to one terminal 32A of the thermistor 32. The other terminal 32B of the thermistor 32 is connected to ground potential.

[0014] The calculation unit 10 detects the potential based on the output of the potential detection circuit unit 20, and compensates for the potential detected based on the output of the potential detection circuit unit 20 based on the output of the temperature detection circuit unit 30. The output of the potential detection circuit unit 20 corresponds to the voltage across the terminals of the resistor 22. The voltage across the terminals of the resistor 22 is the potential difference between terminal 22A and terminal 22B of the resistor 22. In this embodiment, terminal 22A of the resistor 22 is connected to terminal T1 of the calculation unit 10, and terminal 22B of the resistor 22 is connected to terminal T2 of the calculation unit 10. Therefore, the resistor 22 corresponds to a so-called sense resistor for potential detection (voltage measurement).

[0015] The output of the temperature detection circuit 30 corresponds to the terminal voltage of the thermistor 32. The terminal voltage of the thermistor 32 is the potential difference between terminal 32A and terminal 32B of the thermistor 32. In this embodiment, terminal 32A of the thermistor 32 is connected to terminal T3 of the calculation unit 10, and terminal 32B of the thermistor 32 is connected to terminal T4 of the calculation unit 10.

[0016] Temperature compensation means correcting the output of the potential detection circuit 20 so that the temperature fluctuations included in the output of the potential detection circuit 20 are reduced. Therefore, the calculation unit 10 detects the potential based on the potential difference between terminals 22A and 22B of the resistor 22, and corrects the potential detected based on the potential difference between terminals 32A and 32B of the thermistor 32 so that the temperature fluctuations included in the potential detected based on the potential difference between terminals 22A and 22B of the resistor 22 are reduced.

[0017] Figure 2 is an illustrative diagram showing a cross-section of the substrate 1 on which the circuit diagram of Figure 1 is provided. As shown in Figure 2, the substrate 1 is made up of multiple (four in this embodiment) conductive layers CL stacked with insulating layers IL in between. Hereinafter, the four conductive layers CL will be referred to as conductive layer CL1, conductive layer CL2, conductive layer CL3, and conductive layer CL4, and will be assumed to be stacked in that order from top to bottom. In addition, insulating layer IL1 is interposed between conductive layer CL1 and conductive layer CL2, insulating layer IL2 is interposed between conductive layer CL2 and conductive layer CL3, and insulating layer IL3 is interposed between conductive layer CL3 and conductive layer CL4.

[0018] Here, the direction in which the four conductive layers CL are stacked is defined as the stacking direction Z. In the present embodiment, as shown in FIG. 2, a thermistor 32 is incorporated in the central portion of the substrate 1 in the stacking direction Z. Specifically, the thermistor 32 is incorporated across the conductive layer CL2 and the conductive layer CL3. In the stacking direction Z, the side of the conductive layer CL1 as viewed from the thermistor 32 is defined as the stacking direction Z1 side, and the side of the conductive layer CL4 as viewed from the thermistor 32 is defined as the stacking direction Z2 side. Resists R are provided on the stacking direction Z1 side of the conductive layer CL1 and on the stacking direction Z2 side of the conductive layer CL4, respectively.

[0019] The conductive layer CL1 corresponds to the first conductive layer provided at one end (the end in the stacking direction Z1) along the stacking direction Z among the plurality of conductive layers CL. The conductive layer CL3 corresponds to the second conductive layer different from the conductive layer CL1. Therefore, in the present embodiment, the second conductive layer corresponds to the conductive layer CL provided on the central side along the stacking direction Z among the plurality of conductive layers CL, that is, the so-called inner layer. Further, as described above, the thermistor 32 is provided across the conductive layer CL2 and the conductive layer CL3, and the top of the thermistor 32 coincides with the conductive layer CL2 in the stacking direction Z. For this reason, in the present embodiment, the conductive layer CL1 and the thermistor 32 are adjacent to each other along the stacking direction Z via the insulating layer IL1 which is a single insulating layer IL.

[0020] FIG. 3 shows a plan view of the conductive layer CL1, and FIG. 4 shows a plan view of the conductive layer CL2. Further, FIG. 5 shows a plan view of the conductive layer CL3, and FIG. 6 shows a plan view of the conductive layer CL4.

[0021] As shown in FIG. 3, on the conductive layer CL1, there are mounted a connector CN1 to which a voltage V1 is applied, a connector CN2 to which a ground potential is applied, a connector CN3 to which a voltage V2 is applied, a connector CN4 connected to the terminal T1 of the arithmetic unit 10, and a connector CN5 connected to the terminal T3 of the arithmetic unit 10. The connector CN2 is connected to the terminals T2 and T4 of the arithmetic unit 10. In this embodiment, a resistor 22, which is a component to be temperature-measured, is provided on the conductive layer CL1. Further, a resistor 21 and a resistor 31 are also mounted on the conductive layer CL1.

[0022] Also, on the conductive layer CL1, there are provided a pattern 1P1 connecting a land where the connector CN1 is welded and fixed, for example, by soldering, and a land where the terminal 21A of the resistor 21 is welded and fixed, a pattern 1P2 connecting a land where the terminal 21B of the resistor 21 is welded and fixed and a land where the terminal 22A of the resistor 22 is welded and fixed, and a pattern 1P3 connecting a land where the terminal 22B of the resistor 22 is welded and fixed and a land where the connector CN2 is welded and fixed. Further, on the conductive layer CL1, there are provided a pattern 1P4 connecting a land where the connector CN3 is welded and fixed and a land where the terminal 31A of the resistor 31 is welded and fixed, and a pattern 1P5 connecting a land where the terminal 31B of the resistor 31 is welded and fixed and a land 1L1 where the connector CN5 is welded and fixed.

[0023] As shown in FIG. 4, the conductive layer CL2 is formed by a pattern 2P1 obtained by cutting out a conductor portion in a region including at least a thermistor 32, a via 60 described later, and a via 61 that electrically connects a land 1L1 where the connector CN5 of the conductive layer CL1 is welded and fixed and a pattern 3P1 of the conductive layer CL3 to each other. Thereby, the influence of heat from parts other than the resistor 22 on the thermistor 32 can be suppressed, and the temperature of the resistor 22 can be measured more accurately.

[0024] As shown in Figure 5, conductive layer CL3 includes pattern 3P1 connected to land 1L1 of conductive layer CL1 via via 61. Conductive layer CL3 is provided with a thermistor 32 that acquires temperature information indicating the temperature of resistor 22. Temperature information indicating the temperature of resistor 22 refers to information indicating the temperature around resistor 22. The thermistor 32 acquires the resistance value that fluctuates according to the temperature around resistor 22 as temperature information. Pattern 3P2 is provided between pattern 3P1 and terminal 32A of thermistor 32. Terminal 32B of thermistor 32 is connected to pattern 3P3.

[0025] As shown in Figures 3 and 5, the first region 41 in the conductive layer CL1 where the resistor 22 is provided and the second region 42 in the conductive layer CL3 where the thermistor 32 is provided are configured to overlap at least partially when viewed along the stacking direction Z. The first region 41 is the region in the conductive layer CL1 that includes not only the resistor 22 but also the land on which the resistor 22 is fixed (mounted) to the conductive layer CL1. The second region 42 is the region in the conductive layer CL3 that includes not only the thermistor 32 but also the land on which the thermistor 32 is fixed (mounted) to the conductive layer CL3. In this embodiment, the resistor 22 and the thermistor 32 are provided so that they completely overlap when viewed along the stacking direction Z. Therefore, the thermistor 32 is provided directly below the resistor 22 along the stacking direction Z.

[0026] In this embodiment, vias 60 are provided in the overlapping region 43, which overlaps with each other, to electrically connect the terminal 22B of the resistor 22 and the terminal 32B of the thermistor 32. The overlapping region 43 is the region where the first region 41 and the second region 42 overlap with each other. In this embodiment, the resistor 22 and the thermistor 32 completely overlap with each other along the stacking direction Z. Therefore, it corresponds to both the first region 41 and the second region 42. Also, in this embodiment, the thermistor 32 is provided across the conductive layer CL2 and the conductive layer CL3, and the position of the terminal 32B of the thermistor 32 along the stacking direction Z corresponds to the position of the conductive layer CL2. Thus, vias 60 are provided across the terminal 22B of the resistor 22 and the terminal 32B of the thermistor 32, penetrating the insulating layer IL1 along the stacking direction Z. Therefore, via 60 connects terminal 22B of resistor 22 and terminal 32B of the thermistor 32 via the shortest possible distance.

[0027] As shown in Figure 6, the conductive layer CL4 includes a pattern 4P1 formed across its entire surface. Pattern 4P1 can be connected, for example, to the housing of another device via harnesses or screws.

[0028] Although not shown in the diagram, conductive layers CL1-CL4 may have grounded patterns in locations different from the patterns and lands described above. Furthermore, the patterns and lands described above can be modified.

[0029] [Other Embodiments] Next, other embodiments of the substrate 1 will be described.

[0030] In the above embodiment, the substrate 1 was described as having four conductive layers CL laminated with an insulating layer IL in between. However, the substrate 1 may have two conductive layers CL1 laminated with an insulating layer IL in between, or six or more conductive layers CL laminated with an insulating layer IL in between.

[0031] In the above embodiment, the component whose temperature is measured was described as a resistor 22. However, the component whose temperature is measured may be a semiconductor element such as a switching element or a rectifier element, or it may be a capacitor, etc. Of course, it may be a component other than these.

[0032] In the above embodiment, the first conductive layer was described as a conductive layer CL1 provided at one end of the plurality of conductive layers CL along the stacking direction Z (the end in the stacking direction Z1). However, it may also be a conductive layer CL (conductive layer CL4 in the above embodiment) provided at the other end of the plurality of conductive layers CL along the stacking direction Z (the end in the stacking direction Z2), or a conductive layer CL (a so-called inner layer, which in the above embodiment is conductive layer CL2 or conductive layer CL3) provided on the central side of the plurality of conductive layers CL along the stacking direction Z.

[0033] In the above embodiment, the second conductive layer was described as conductive layer CL3, which is located on the central side along the stacking direction Z of the plurality of conductive layers CL, i.e., the so-called inner layer. However, as long as it is different from the conductive layer CL on which the component to be measured for temperature (resistor 22 in the above embodiment) is located, it may be conductive layer CL (conductive layer CL1 in the above embodiment) located at one end along the stacking direction Z (end in the stacking direction Z1) of the plurality of conductive layers CL, or conductive layer CL (conductive layer CL4 in the above embodiment) located at the other end along the stacking direction Z (end in the stacking direction Z2) of the plurality of conductive layers CL. Of course, it may also be another conductive layer CL (conductive layer CL2 in the above embodiment) located on the central side along the stacking direction Z of the plurality of conductive layers CL.

[0034] In the above embodiment, the resistor 22 is provided in the conductive layer CL1, and the thermistor 32 is provided across the conductive layers CL2 and CL3. If the resistor 22 is provided in an inner layer of the multiple conductive layers CL, the resistor 22 may be provided across the multiple conductive layers CL. Alternatively, the thermistor 32 may be provided in a single conductive layer CL among the multiple conductive layers CL.

[0035] In the above embodiment, it was explained that the terminal 22B of the resistor 22 is connected to the ground potential, but it may be connected to a potential different from the ground potential.

[0036] In the above embodiment, it was explained that the terminal 32B of the thermistor 32 is connected to the ground potential, but it may be connected to a potential different from the ground potential.

[0037] In the above embodiment, the temperature information acquisition unit was described as a thermistor 32. However, the temperature information acquisition unit may be a temperature sensor other than the thermistor 32.

[0038] In the above embodiment, resistor 22 was described as a so-called sense resistor for potential detection (voltage measurement). However, resistor 22 may also be a so-called shunt resistor for current detection (current measurement).

[0039] In the above embodiment, it was explained that an insulating layer IL1 is interposed between the conductive layer CL1 and the thermistor 32 in the overlapping regions 43 that overlap with each other. However, the insulating layer IL1 may be, for example, an insulating heat transfer material. In this case, the temperature of the resistor 22 can be measured with greater accuracy.

[0040] In the above embodiment, it was explained that the first region 41 and the second region 42 completely overlap each other when viewed along the stacking direction Z. However, the first region 41 and the second region 42 may partially overlap each other when viewed along the stacking direction Z.

[0041] Furthermore, in the above embodiment, it was explained that the resistor 22 and the thermistor 32 completely overlap each other when viewed along the stacking direction Z. However, the resistor 22 and thermistor 32 may partially overlap each other when viewed along the stacking direction Z.

[0042] In the above embodiment, it was explained that vias 60, which electrically connect the terminals 22B of the resistor 22 and the terminals 32B of the thermistor 32 in the overlapping region 43, are provided extending from the terminals 22B of the resistor 22 to the terminals 32B of the thermistor 32, penetrating the insulating layer IL1 along the lamination direction Z. However, vias 60 may also be provided extending from the terminals 22B of the resistor 22 and the terminals 32B of the thermistor 32 along the surface direction of the substrate 1 perpendicular to the lamination direction Z, penetrating the insulating layer IL1 along the lamination direction Z.

[0043] In the above embodiment, the first conductive layer on which the resistor 22 is provided and the second conductive layer on which the thermistor 32 is provided are described as being adjacent to each other with a single insulating layer IL in between. However, multiple insulating layers IL and at least one other conductive layer CL may be interposed between the first conductive layer on which the resistor 22 is provided and the second conductive layer on which thermistor 32 is provided.

[0044] [Summary of the above embodiment] The following describes the overview of the substrate 1 as explained above.

[0045] (1) The substrate 1 comprises a plurality of conductive layers CL laminated via an insulating layer IL, the plurality of conductive layers CL include a conductive layer CL1 (first conductive layer) on which a resistor 22 (component) to be measured for temperature is provided, and a conductive layer CL2 (second conductive layer) different from conductive layer CL1, on which a thermistor 32 (temperature information acquisition unit) that acquires temperature information indicating the temperature of the resistor 22 is provided, and at least a portion of the first region 41 on conductive layer CL1 on which the resistor 22 is provided and the second region 42 on conductive layer CL2 on which the thermistor 32 is provided overlap with each other when viewed along the lamination direction Z in which the plurality of conductive layers CL are laminated.

[0046] With this configuration, the thermistor 32 can be positioned in close proximity to the resistor 22, which is the component whose temperature is to be measured, by arranging the thermistor 32 so that at least a portion of it overlaps with the resistor 22 along the stacking direction Z. Therefore, it becomes possible to accurately measure the temperature of the resistor 22.

[0047] (2) The substrate 1 described in (1) preferably has vias 60 that electrically connect the terminal 22B of the resistor 22 and the terminal 32B of the thermistor 32 in overlapping regions 43 that overlap with each other.

[0048] With this configuration, the heat from the resistor 22 can be transferred to the thermistor 32 via the via 60. Therefore, a substrate 1 can be realized that can measure the temperature of the resistor 22 with greater accuracy.

[0049] (3) In the substrate 1 described in (1) or (2), the conductive layer CL1 is preferably a conductive layer CL provided at one end of a plurality of conductive layers CL along the stacking direction Z.

[0050] With this configuration, the resistor 22 can be mounted on either the front or back surface of the substrate 1. Therefore, since the resistor 22 can be mounted on the substrate 1 in an exposed state, it is possible to improve the heat dissipation of the resistor 22 itself.

[0051] (4) In the substrate 1 described in (1) to (3), it is preferable that the conductive layer CL1 and the thermistor 32 are adjacent to each other in overlapping regions 43, separated by a single insulating layer IL.

[0052] This configuration allows the resistor 22 and the thermistor 32 to be placed closer together along the stacking direction Z. Therefore, heat from the resistor 22 can be more easily transferred to the thermistor 32. [Industrial applicability]

[0053] The technology described herein can be used in substrates. [Explanation of Symbols]

[0054] 1: Substrate, 22: Resistor (component), 32: Thermistor (temperature information acquisition unit), 41: First region, 42: Second region, 43: Overlapping region, 60: Via, CL: Conductive layer, CL1: Conductive layer (first conductive layer), CL2: Conductive layer (second conductive layer), IL: Insulating layer, Z: Lamination direction

Claims

1. It comprises multiple conductive layers stacked with an insulating layer in between, The plurality of conductive layers include a first conductive layer on which a component to be measured for temperature is provided, and a second conductive layer different from the first conductive layer, which is provided with a temperature information acquisition unit that acquires temperature information indicating the temperature of the component. A substrate in which a first region of the first conductive layer on which the component is provided and a second region of the second conductive layer on which the temperature information acquisition unit is provided overlap in at least a portion when viewed along the stacking direction in which the plurality of conductive layers are stacked.

2. The substrate according to claim 1, having vias in the overlapping regions that overlap with each other, which electrically connect one of the terminals of the component and one of the terminals of the temperature information acquisition unit.

3. The substrate according to claim 1 or 2, wherein the first conductive layer is a conductive layer provided at one end of a plurality of conductive layers along the stacking direction.

4. The substrate according to claim 1 or 2, wherein in the overlapping regions that overlap each other, the first conductive layer and the temperature information acquisition unit are adjacent to each other via a single insulating layer.

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