Semiconductor device and method for manufacturing a semiconductor device

Abstract

The objective is to provide a technology that can suppress the delamination of the mold resin in semiconductor devices, starting from a reference pattern used during manufacturing. [Solution] The semiconductor device includes a semiconductor element 100 having a semiconductor substrate 110 that defines an active region 101 through which the main current flows, a terminal region 104 which is the outer peripheral region of the active region 101, and a dicing line region 105 which is the outer peripheral region of the terminal region 104. A metal pattern 106a is provided on the upper surface of the semiconductor substrate 110 in the dicing line region 105, and the metal pattern 106a is arranged in the dicing line region 105 but is not arranged in at least one corner of the dicing line region 105.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device.

Background Art

[0002] In general, a semiconductor device for power, commonly referred to as a power device, is equipped with a switching element that controls power supply such as a motor load. As the switching element, an insulated gate semiconductor element such as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) or an IGBT (Insulated Gate Bipolar Transistor) is widely used.

[0003] Semiconductor devices for power are evolving towards higher current, higher voltage, and lower losses and are used in various fields. Semiconductor devices for power are often used in harsh environments such as high altitude, high temperature, and high humidity environments. In addition to lower losses, high reliability such as temperature cycle and moisture resistance is required. Furthermore, these characteristics are required to be realized at low cost.

[0004] These semiconductor devices for power are generally manufactured by using a semiconductor wafer using silicon (Si) as a semiconductor material and techniques such as lithography, etching, or deposition. In recent years, however, high-performance semiconductor devices using a semiconductor wafer using a wide bandgap semiconductor such as silicon carbide (SiC) as a semiconductor material have also been manufactured.

[0005] After a series of manufacturing processes of the above semiconductor elements are completed, individual semiconductor elements are cut out by a dicing process and assembled into a module or the like, and the manufacturing process is completed.

[0006] In the semiconductor device manufacturing process described above, alignment patterns for the semiconductor wafer or patterns for measuring film thickness during manufacturing are required, and it is common practice to place these patterns on the semiconductor wafer. However, placing these patterns on the dicing line sometimes caused problems during dicing.

[0007] As a countermeasure to such problems, for example, Patent Document 1 discloses a technique in which a metal mark is not placed in the center of the dicing line so that the metal mark does not obstruct the laser light and hinder dicing during laser dicing.

[0008] Furthermore, for example, Patent Document 2 discloses a technique for suppressing the generation of foreign matter during dicing by forming a dedicated pattern in the semiconductor element region between the pressure-resistant holding region and the dicing line. [Prior art documents] [Patent Documents]

[0009] [Patent Document 1] Japanese Patent Publication No. 2015-106693 [Patent Document 2] Japanese Patent Publication No. 2010-129695 [Overview of the Initiative] [Problems that the invention aims to solve]

[0010] However, the technology described in Patent Document 1 discloses an example in which a pattern is placed on the dicing line, including the intersection of the dicing line, which affects the delamination of the molded resin. In particular, when a pattern is placed on the intersection of the dicing line, a strong localized stress is applied to the intersection of the dicing line where the pattern is placed, that is, to the corner of the semiconductor element, which could cause delamination of the molded resin to occur starting from the pattern.

[0011] Similarly, in the technology described in Patent Document 2, if a pattern is placed in the corner area of ​​the semiconductor element region, there was a possibility that delamination of the mold resin would occur starting from the pattern.

[0012] Therefore, the present disclosure aims to provide a technology that can suppress the occurrence of delamination of the mold resin in a semiconductor device, starting from a pattern used for reference during manufacturing. [Means for solving the problem]

[0013] The semiconductor device according to this disclosure comprises a semiconductor element having a semiconductor substrate defined with an active region through which a main current flows, a terminal region which is the outer peripheral region of the active region, and a dicing line region which is the outer peripheral region of the terminal region, wherein a manufacturing reference metal pattern is provided on the upper surface of the semiconductor substrate in the dicing line region, and the manufacturing reference metal pattern is arranged in the dicing line region and is not arranged in at least one corner portion of the dicing line region. [Effects of the Invention]

[0014] According to this disclosure, localized strong stress is suppressed at at least one corner of the dicing line region, i.e., at least one corner of the semiconductor device. This prevents the manufacturing reference metal pattern from becoming the starting point for delamination of the mold resin. [Brief explanation of the drawing]

[0015] [Figure 1] This is a top view of a semiconductor wafer on which semiconductor elements of the semiconductor device according to Embodiment 1 are formed. [Figure 2] This is a top view of a semiconductor element provided in the semiconductor device according to Embodiment 1. [Figure 3] This is an enlarged view of region 202 in Figure 1. [Figure 4] This is a cross-sectional view along line AA' in Figure 2. [Figure 5] This is a cross-sectional view along line BB' in Figure 2. [Figure 6] It is a cross-sectional view taken along line C-C' of FIG. 2. [Figure 7] It is a cross-sectional view of an end portion of a semiconductor device for explaining the effects of Embodiment 1. [Figure 8] It is a top view of a semiconductor device for explaining the effects of Embodiment 1. [Figure 9] It is a top view of a semiconductor element included in the semiconductor device according to Embodiment 2. [Figure 10] It is an enlarged view corresponding to region 202 of FIG. 1 in Embodiment 2. [Figure 11] It is a cross-sectional view taken along line D-D' of FIG. 9. [Figure 12] It is a cross-sectional view taken along line E-E' of FIG. 9. [Figure 13] It is a cross-sectional view taken along line F-F' of FIG. 9. [Figure 14] It is a top view of a semiconductor element included in the semiconductor device according to Embodiment 3. [Figure 15] It is an enlarged view corresponding to region 202 of FIG. 1 in Embodiment 3. [Figure 16] It is a cross-sectional view taken along line G-G' of FIG. 14. [Figure 17] It is a cross-sectional view taken along line H-H' of FIG. 14. [Figure 18] It is a cross-sectional view taken along line I-I' of FIG. 14. [Figure 19] It is a top view of a semiconductor element included in the semiconductor device according to Embodiment 4. [Figure 20] It is a cross-sectional view taken along line J-J' of FIG. 19. [Figure 21] It is a cross-sectional view of a semiconductor element included in the semiconductor device according to Modification 1 of Embodiment 4. [Figure 22] It is a cross-sectional view of a semiconductor element included in the semiconductor device according to Modification 2 of Embodiment 4.

Embodiments for Carrying Out the Invention

[0016] <Embodiment 1> Embodiment 1 will be described below with reference to the drawings. This is a top view of a semiconductor wafer 200 on which a semiconductor element 100, which is part of the semiconductor device according to Embodiment 1, is formed.

[0017] As shown in Figure 1, the semiconductor wafer 200 is cut in the longitudinal and transverse directions along multiple dicing lines 107 (see Figure 3) in the wafer region 201. Multiple semiconductor elements 100 are formed on the semiconductor wafer 200 by dicing. Here, the longitudinal and transverse directions refer to the longitudinal and transverse directions of the paper in Figure 1.

[0018] Figure 2 is a top view of a semiconductor element 100 provided in the semiconductor device according to Embodiment 1. Figure 3 is an enlarged view of region 202 in Figure 1. Figure 2 shows the semiconductor element 100 in a state cut out by dicing. As shown in Figure 2, the semiconductor element 100 includes a semiconductor substrate 110. The semiconductor substrate 110 has defined active region 101, gate pad region 103, termination region 104, and dicing line region 105.

[0019] The active region 101 is the region through which the main current flows. One of the main electrodes, the source electrode 11 (see Figure 5), is formed in the active region 101. The gate pad region 103 extends from the center of one side of the active region 101 toward the center of the active region 101. An annular gate wiring 102 is provided along the outer periphery of the active region 101. The gate wiring 102 is connected to the gate pad region 103. The termination region 104 is the region on the outer periphery of the active region 101 and is formed to surround the active region 101, the gate wiring 102, and the gate pad region 103 for voltage resistance maintenance. The dicing line region 105 is the region on the outer periphery of the termination region 104.

[0020] On the upper surface of the semiconductor substrate 110 in the dicing line region 105, a metal pattern 106a and a groove pattern 106b are provided as reference metal patterns during manufacturing. The metal pattern 106a is a film deposited or sputtered from the surface of the semiconductor substrate 110 during the metal process for forming wiring. The groove pattern 106b is a groove formed by etching the semiconductor substrate 110. In Embodiment 1, the groove pattern 106b is formed in the etching process, and then the metal pattern 106a is formed in the metal process.

[0021] Here, the metal pattern 106a and groove pattern 106b are patterns used for alignment to position the semiconductor wafer 200 in a predetermined location on the stage during the manufacturing process of the semiconductor device 100, patterns used for detailed lithography overlay, inspection marks, or patterns used to measure the film thickness during the manufacturing process of the semiconductor device 100 or to confirm its electrical properties. Since the shapes of the metal pattern 106a and groove pattern 106b vary depending on the purpose and manufacturing process, the detailed shapes of the metal pattern 106a and groove pattern 106b are not shown, and they are shown as simple patterns.

[0022] Next, the cross-sectional structure of the semiconductor device 100 will be described. Figure 4 is a cross-sectional view along line AA' in Figure 2, showing a cross-section obtained by cutting out the dicing line region 105 in a cross-section parallel to the dicing line 107 (see Figure 3). Figure 5 is a cross-sectional view along line BB' in Figure 2, showing a cross-section of the region including the metal pattern 106a. Figure 6 is a cross-sectional view along line CC' in Figure 2, showing a cross-section of the region not including the metal pattern 106a and the groove pattern 106b.

[0023] As shown in Figures 4 to 6, the semiconductor substrate 110 is n + Substrate 1 and n + n provided on the upper surface of substrate 1 - Drift layer 2 and n - p-well layer 3, pFLR layer 4, p +It comprises a contact layer 5 and an n-channel stopper layer 6. A drain electrode 13 is provided on the lower surface of the semiconductor substrate 110 via a silicide layer 12.

[0024] In Figures 5 and 6, the region to the left of the dicing line region 105 is the end of the active region 101 (see Figure 2) to the terminal region 104 (see Figure 2). This is also true in Figures 12, 13, 17, 18, 20, 21, and 22 below.

[0025] As shown in Figures 5 and 6, the ends of the active region 101 and the gate wiring 102 (see Figure 2) are located on the upper side of the p-well layer 3. The terminal region 104 forms a pressure-resistant holding structure consisting of a pFLR layer 4 and an n-channel stopper layer 6, with an underlay insulating film 7, a field insulating film 8, and an interlayer insulating film 9 provided on top of these. The interlayer insulating film 9 is covered with an insulating film 16 made of a silicon nitride film and an organic protective film 17 made of polyimide. Note that the insulating film 16 may be made of a silicon oxide film. Also, the organic protective film 17 may be made of polyamide.

[0026] As shown in Figures 5 and 6, at the edge of the active region 101, a source electrode 11 is provided on the field insulating film 8 via a silicide layer 10. A gate electrode 14 is also provided on the field insulating film 8 via gate wiring 15. The source electrode 11 and gate electrode 14 are also covered with an insulating film 16 and an organic protective film 17.

[0027] As shown in Figure 4, in Embodiment 1, the upper surface of the semiconductor substrate 110 is exposed in the dicing line region 105, and a metal pattern 106a and a groove pattern 106b are partially arranged on the exposed upper surface of the semiconductor substrate 110. The metal pattern 106a is formed in a stepped shape that protrudes upward from the upper surface of the semiconductor substrate 110. The metal pattern 106a is covered with a protective film 19. Here, in Figures 2 and 3, the protective film 19 covering the metal pattern 106a is not shown.

[0028] Although a planar MOSFET or trench MOSFET structure is used as the semiconductor element 100, the structure of the active region 101 is not related to the features of Embodiment 1, so the details of the active region 101 are omitted.

[0029] Furthermore, since the semiconductor element 100 in Embodiment 1 can be manufactured using general methods such as lithography, etching, or deposition, details of the manufacturing method will be omitted.

[0030] The first feature of Embodiment 1 is that the metal pattern 106a and groove pattern 106b are arranged in the dicing line region 105, and are not arranged in at least one corner (more specifically, four corners) of the dicing line region 105.

[0031] A second feature of Embodiment 1 is that the metal pattern 106a and groove pattern 106b are arranged in the straight portion of the dicing line region 105. Here, the straight portion of the dicing line region 105 is the straight portion that connects the corner portions of the dicing line region 105.

[0032] A third feature of Embodiment 1 is that the metal pattern 106a is covered with a protective film 19.

[0033] Next, the features and effects of Embodiment 1 will be described using Figures 7 and 8. Figure 7 is a cross-sectional view of the end of a semiconductor device to illustrate the effects of Embodiment 1. Figure 8 is a top view of the semiconductor device to illustrate the effects of Embodiment 1.

[0034] As shown in Figure 7, the semiconductor device comprises a semiconductor element 100, a base substrate 25, and a molding resin 26. The base substrate 25 is bonded to the lower surface of the semiconductor element 100 via a bonding layer 24 such as solder. The upper and side surfaces of the semiconductor element 100 are sealed with the molding resin 26.

[0035] In molded semiconductor devices, each material constituting the semiconductor element 100, the base substrate 25, and the molding resin 26 have different coefficients of linear expansion. Therefore, stresses X1 and X2 are generated at each interface due to reasons such as changes in the ambient temperature during use or temperature rise caused by the application of current.

[0036] In particular, the interface between the molding resin 26 and the semiconductor element 100 tends to experience high stress due to the difference in the coefficient of thermal expansion between the molding resin 26 and the semiconductor element 100, as well as the size difference between the semiconductor element 100 and the molding resin 26 that houses and seals it. As a result, delamination of the molding resin 26 progresses from the edge of the dicing line region 105, leading to moisture intrusion and other issues that can degrade the moisture resistance of the semiconductor device.

[0037] As shown in Figure 8, the magnitude of the stress differs depending on the position of the semiconductor element 100. In the straight sections, a unidirectional stress X4 or Y4 is applied, while in the corner sections, stresses X3 and Y3 are applied two-dimensionally from the horizontal and vertical directions, making it easier for the mold resin 26 to peel off from the corner sections. Here, the horizontal and vertical directions refer to the horizontal and vertical directions of the paper in Figure 8.

[0038] Here, using Figures 5 and 6, we consider how the metal pattern 106a and groove pattern 106b are affected. The size or shape of the metal pattern 106a and groove pattern 106b is limited by the pattern recognition capability or alignment accuracy of the semiconductor device manufacturing equipment (not shown). For example, the metal pattern 106a and groove pattern 106b may be asymmetrical patterns with predetermined sizes and steps for recognition, or a uniform pattern may be required over a certain area to improve measurement accuracy.

[0039] Since the vicinity of such patterns is prone to becoming a starting point for delamination of the mold resin 26, it is undesirable to place patterns in areas of high stress.

[0040] In particular, aluminum or copper wiring is often used in the manufacturing process of semiconductor devices. When it is necessary to form patterns with these metals, placing the patterns in areas with high stress can cause the pattern to deform due to metal corrosion, leading to a problem where the delamination of the molding resin 26 is accelerated.

[0041] In contrast, in Embodiment 1, the semiconductor device includes a semiconductor element 100 having a semiconductor substrate 110 that defines an active region 101 through which the main current flows, a terminal region 104 which is the outer peripheral region of the active region 101, and a dicing line region 105 which is the outer peripheral region of the terminal region 104. A metal pattern 106a is provided on the upper surface of the semiconductor substrate 110 in the dicing line region 105, and the metal pattern 106a is arranged in the dicing line region 105 but is not arranged in at least one corner of the dicing line region 105.

[0042] Furthermore, a groove pattern 106b is provided on the upper surface of the semiconductor substrate 110 in the dicing line region 105. The groove pattern 106b is located in the dicing line region 105, but is not located in at least one corner of the dicing line region 105.

[0043] More specifically, both the metal pattern 106a and the groove pattern 106b are not located at the four corners of the dicing line region 105, but are located in the straight sections of the dicing line region 105.

[0044] Therefore, strong localized stress is suppressed at the corners of the dicing line region 105, that is, at the corners of the semiconductor element 100. This prevents the metal pattern 106a and groove pattern 106b from becoming the starting points for delamination of the mold resin 26. As a result, the reliability of the semiconductor device, such as its moisture resistance, can be improved without taking special measures such as increasing the size of the semiconductor element 100.

[0045] Furthermore, the metal pattern 106a is formed in a stepped shape that protrudes upward from the upper surface of the semiconductor substrate 110. In addition, since the metal pattern 106a is covered with a protective film 19, the resistance of the metal pattern 106a to corrosion can be improved.

[0046] <Embodiment 2> Next, Embodiment 2 will be described. Figure 9 is a top view of a semiconductor element 100 provided in the semiconductor device according to Embodiment 2. Figure 10 is an enlarged view corresponding to region 202 in Figure 1 in Embodiment 2. Figure 11 is a cross-sectional view taken along the line DD' in Figure 9. Figure 12 is a cross-sectional view taken along the line EE' in Figure 9. Figure 13 is a cross-sectional view taken along the line FF' in Figure 9. In Embodiment 2, the same reference numerals are used for components that are the same as those described in Embodiment 1, and their descriptions are omitted.

[0047] As shown in Figures 9 to 13, the first feature of Embodiment 2 is that the dicing line region 105 and the groove pattern 106c formed in the dicing line region 105 as a reference pattern during manufacturing are covered with an interlayer insulating film 9, and the region in contact with the mold resin 26 corresponding to the groove pattern 106c is flattened.

[0048] A second feature of the second embodiment is that the groove pattern 106c is located at at least one corner of the dicing line region 105.

[0049] A third feature of Embodiment 2 is that the metal pattern 106a is arranged in the dicing line region 105, but is not arranged in the four corners of the dicing line region 105.

[0050] In the same procedure as in Embodiment 1, first, a groove pattern 106c is formed in the etching process, and then a metal pattern 106a is formed in the metal process.

[0051] As described above, in Embodiment 2, the groove pattern 106c is arranged at least one corner of the dicing line region 105, and the region in contact with the mold resin 26 corresponding to the groove pattern 106c is flattened by the interlayer insulating film 9. Therefore, it is possible to suppress the groove pattern 106b from becoming the starting point for delamination of the mold resin 26 while improving the degree of freedom in arranging the groove pattern 106c.

[0052] <Embodiment 3> Next, Embodiment 3 will be described. Figure 14 is a top view of a semiconductor element 100 provided in the semiconductor device according to Embodiment 3. Figure 15 is an enlarged view corresponding to region 202 in Figure 1 in Embodiment 3. Figure 16 is a cross-sectional view taken along the line GG' in Figure 14. Figure 17 is a cross-sectional view taken along the line HH' in Figure 14. Figure 18 is a cross-sectional view taken along the line II' in Figure 14. In Embodiment 3, the same reference numerals are used for components that are the same as those described in Embodiments 1 and 2, and their descriptions are omitted.

[0053] As shown in Figures 14 to 18, the characteristic of Embodiment 3 is that, compared to Embodiment 1, in addition to the metal pattern 106, multiple types of stepped patterns are arranged that protrude upward from the upper surface of the semiconductor substrate 110.

[0054] The stepped patterns include a polysilicon pattern 106d, which is a reference pattern used during manufacturing and is made of polysilicon, often used in the gate structure of MOSFETs, and an insulating film pattern 106e, which is a reference pattern used during manufacturing and is formed by etching the interlayer insulating film 9. The polysilicon pattern 106d and the insulating film pattern 106e are provided on the upper surface of the semiconductor substrate 110 via the insulating film 21, and each reference pattern during manufacturing includes an exposed portion. In particular, due to the structure of the reference pattern during manufacturing, there are cases in which the reference pattern during manufacturing is exposed from the organic protective film 17. In this case, under high temperature and high humidity conditions, the portion exposed from the organic protective film 17 may oxidize, and this portion may become the starting point for delamination.

[0055] As described above, in Embodiment 3, even if the patterns have different structures, such as a metal pattern for reference during manufacturing, a reference pattern for manufacturing with exposed parts, and a reference pattern for manufacturing with stepped protruding parts, by avoiding the corners of the dicing line region 105 in the arrangement of the patterns, it is possible to suppress the patterns from becoming the starting point for delamination of the mold resin 26.

[0056] <Embodiment 4> Next, Embodiment 4 will be described. Figure 19 is a top view of the semiconductor element 100 provided in the semiconductor device according to Embodiment 4. Figure 20 is a cross-sectional view taken along the JJ' line in Figure 19. In Embodiment 4, the same reference numerals are used for components that are the same as those described in Embodiments 1 to 3, and their descriptions are omitted.

[0057] As shown in Figures 19 and 20, the characteristic of Embodiment 4 is that, compared to Embodiment 1, instead of the metal pattern 106a and groove pattern 106b, the metal pattern 106f, which serves as a metal pattern for reference during manufacturing, is provided not in the dicing line region 105, but on the upper surface of the semiconductor substrate 110 corresponding to the corner portion on the dicing line region 105 side of the termination region 104, and on the outer periphery side of the depletion layer end formed in the termination region 104 when the maximum rated voltage is applied.

[0058] In Figure 19, the dotted line labeled 108 indicates the depletion layer edge when the maximum rated voltage is applied. The area outside this dotted line is basically at approximately the same potential as the applied voltage. Here, the distance from the source side edge of the termination region 104 to the depletion layer edge 108 (the width of the depleted region) can be designed to be almost the same in the straight section and the corner section, so the corner section is wider than the straight section. Therefore, by considering the distance outside the depletion layer edge 108 and the size of the metal pattern 106f in the corner section, it is possible to place the metal pattern 106f in the corner section. Since the area outside the depletion layer edge 108 is basically at the same potential as the applied voltage, the placement of the metal pattern 106f does not affect the electric field distribution of the termination region 104.

[0059] Furthermore, by placing the stepped metal pattern 106f on the dicing line region 105 side of the termination region 104 instead of on the dicing line region 105, it is possible to suppress large stresses on the edges of the semiconductor element 100, including the corners of the semiconductor element 100. This prevents the metal pattern 106f from becoming the starting point for delamination of the mold resin 26.

[0060] The metal pattern 106f is covered with an insulating film 16 and an organic protective film 17. Here, the metal pattern 106f may be covered with at least one of the insulating film 16 or the organic protective film 17.

[0061] Furthermore, at the corners of the semiconductor element 100, the termination structure, which is the structure of the termination region 104, has curvature. Therefore, even if the metal pattern 106f is placed on the upper surface of the semiconductor substrate 110 corresponding to the corner on the dicing line region 105 side of the termination region 104, it is easy to ensure a distance between the metal pattern 106f and the termination structure of the semiconductor element 100. For example, even if electrical or mechanical migration occurs in the metal pattern 106f due to stress in the product's operating environment or environmental testing, it is relatively easy to ensure a distance between the metal pattern 106f and the termination structure of the semiconductor element 100. As a result, the impact of migration on the termination structure of the semiconductor element 100 can be minimized.

[0062] In particular, semiconductor elements 100 using silicon carbide (SiC) as the semiconductor material often do not require an annular wiring pattern to be placed on the outer periphery of the termination region 104. Even if a metal pattern 106f is placed on the upper surface of the semiconductor substrate 110 corresponding to the corner portion on the dicing line region 105 side of the termination region 104, the distance between the metal pattern 106f and the gate wiring 102 can be increased. This allows for the securing of as much margin as possible against delamination without creating any excess area.

[0063] In semiconductor devices 100 using silicon (Si) as the semiconductor material, an n-channel stopper layer 6 and an annular wiring pattern are often provided on top of it to suppress the depletion layer from extending and reaching the dicing line 107 (see Figure 3). However, when the distance between this wiring pattern and the metal pattern is small, delamination that occurs in the metal pattern can progress to the wiring pattern, making it easier for the entire wiring pattern to delaminate, and ultimately the entire termination structure to delaminate.

[0064] In contrast, in Embodiment 4, the semiconductor device includes a semiconductor element 100 having a semiconductor substrate 110 that defines an active region 101 through which the main current flows, a terminal region 104 which is the outer peripheral region of the active region 101, and a dicing line region 105 which is the outer peripheral region of the terminal region 104. A metal pattern 106f is provided on the upper surface of the semiconductor substrate 110 corresponding to the corner portion of the terminal region 104 on the dicing line region 105 side, and on the outer peripheral side of the depletion layer end 108 formed in the terminal region 104 when the maximum rated voltage is applied, and no annular wiring pattern is provided.

[0065] Therefore, since the metal pattern 106f is positioned in the termination region 104, avoiding the dicing line region 105, it is possible to suppress large stresses on the edges of the semiconductor element 100, including the corners of the semiconductor element 100. As a result, it is possible to suppress the metal pattern 106f from becoming the starting point for delamination of the mold resin 26 (see Figure 7). In addition, since it is relatively easy to secure a distance between the metal pattern 106f and the termination structure of the semiconductor element 100, the influence of migration on the termination structure of the semiconductor element 100 can be reduced as much as possible.

[0066] Furthermore, the metal pattern 106f is covered with at least one of the insulating film 16 or the organic protective film 17. Therefore, the metal pattern 106f can be suitably protected from stress from the mold resin 26 (see Figure 7).

[0067] Furthermore, the insulating film 16 consists of at least one of a silicon oxide film or a silicon nitride film, and the organic protective film 17 consists of polyimide or polyamide. Therefore, the insulating film 16 and the organic protective film 17 can be formed in a general semiconductor device manufacturing process.

[0068] <Modified form of Embodiment 4> Next, a modified example of Embodiment 4 will be described. Figure 21 is a cross-sectional view of a semiconductor element 100 provided in a semiconductor device according to Modification 1 of Embodiment 4. Specifically, Figure 21(a) is a cross-sectional view of the active region 101 of the semiconductor element 100, and Figure 21(b) is a cross-sectional view of the end of the semiconductor element 100.

[0069] As shown in Figures 21(a) and (b), the semiconductor device 100 is a trench-gate type semiconductor device having a gate electrode 14 embedded in a trench 28 formed in the active region 101. A p-type diffusion layer 27 is provided at the bottom of the trench 28. An interlayer insulating film 9 is provided on top of the gate electrode 14. A source electrode 11 is provided on top of the interlayer insulating film 9.

[0070] The height of the upper surface of the semiconductor substrate 110 in the termination region 104 is lower than the height of the upper surface of the gate electrode 14. The metal pattern 106f is positioned on the upper surface of the semiconductor substrate 110 in the termination region 104, which is formed at a lower height than the upper surface of the gate electrode 14. This is because, when a trench-gate type MOSFET structure is formed on the upper surface of the semiconductor element 100, the termination region 104 can be structured so that its height is lower by the trench depth relative to the upper surface of the gate electrode 14 of the active region 101. In this case, by not lowering the height of the wiring pattern by the trench depth, the height of the area around the metal pattern 106f on the upper surface of the semiconductor substrate 110 is higher than the height of the upper surface of the metal pattern 106f. This allows the semiconductor substrate 110 to surround the metal pattern 106f.

[0071] As a result, the metal pattern 106f does not directly receive stress from the mold resin 26 (see Figure 7), making it less likely for the mold resin 26 to peel off starting from the metal pattern 106f. Furthermore, even if peeling of the mold resin 26 does occur, the step in the semiconductor substrate 110 can suppress the progression of the peeling, thus more effectively suppressing the peeling of the mold resin 26.

[0072] Next, a modified example 2 of Embodiment 4 will be described. Figure 22 is a cross-sectional view of a semiconductor element 100 provided in a semiconductor device according to modified example 2 of Embodiment 4.

[0073] As shown in Figure 22, in Embodiment 4, the metal pattern 106f is positioned at the corners of both ends of the straight section of the termination region 104 where at least the gate pad region 103, which serves as a control pad for the semiconductor element 100, is located. Therefore, the metal pattern 106f can also be used as a recognition mark during wire bonding.

[0074] After the semiconductor element 100 is mounted, it is wire-bonded to the signal terminals. At this time, a wire bonding device (not shown) detects the position information of the semiconductor element 100 to determine the wire bonding position. Therefore, by placing metal patterns 106f, which function as recognition marks, at the corners of both ends of the straight section of the terminal region 104 where the gate pad region 103 of the semiconductor element 100 is located, the wire bonding accuracy can be improved.

[0075] As shown in Figure 22, the semiconductor element 100 is provided with an insulating film 16 and an organic protective film 17 as protective films covering the active region 101 and the termination region 104 on the upper surface of the semiconductor substrate 110. At least a portion of the upper surface of the metal pattern 106f is exposed from the insulating film 16 and the organic protective film 17. Therefore, the wire bonding apparatus can easily recognize the metal pattern 106f.

[0076] <Other variations> In Embodiments 1 to 4, a MOSFET was described as being used as the semiconductor element 100, but the invention is not limited to this, and other structures such as IGBTs or diodes may be used. Furthermore, it is possible to design the device to obtain the same effect when the polarity is reversed as when it is not. In addition, silicon (Si), silicon carbide (SiC), or gallium nitride (GaN) can be used as the semiconductor material for the semiconductor element 100.

[0077] Furthermore, while it is desirable that the metal pattern 106a is not placed in the four corners of the dicing line region 105, it is also possible to suppress a decrease in peel resistance and moisture resistance by not placing the metal pattern 106a in at least one corner.

[0078] Furthermore, it is possible to freely combine each embodiment, or to modify or omit each embodiment as appropriate.

[0079] The various aspects of this disclosure are summarized below as an appendix.

[0080] (Note 1) A semiconductor element comprising a semiconductor substrate having defined active region through which the main current flows, a terminal region which is the outer peripheral region of the active region, and a dicing line region which is the outer peripheral region of the terminal region, A metal pattern for reference during manufacturing is provided on the upper surface of the semiconductor substrate in the dicing line region. A semiconductor device wherein the manufacturing reference metal pattern is located in the dicing line region and is not located in at least one corner of the dicing line region.

[0081] (Note 2) The semiconductor device according to Appendix 1, wherein the metal pattern for reference during manufacturing is not located in the four corner portions of the dicing line region.

[0082] (Note 3) The semiconductor device according to Appendix 2, wherein the metal pattern for reference during manufacturing is arranged in the straight portion of the dicing line region.

[0083] (Note 4) The semiconductor device according to any one of the appendices 1 to 3, wherein the aforementioned manufacturing reference metal pattern is covered with a protective film.

[0084] (Note 5) A semiconductor element comprising a semiconductor substrate having defined active region through which the main current flows, a terminal region which is the outer peripheral region of the active region, and a dicing line region which is the outer peripheral region of the terminal region, A manufacturing reference pattern having an exposed portion is provided on the upper surface of the semiconductor substrate in the dicing line region. A semiconductor device wherein the manufacturing reference pattern is located in the dicing line region and is not located in at least one corner of the dicing line region.

[0085] (Note 6) The semiconductor device according to Appendix 5, wherein the manufacturing reference pattern having an exposed portion is not located in the four corner portions of the dicing line region.

[0086] (Note 7) The semiconductor device according to Appendix 6, wherein the manufacturing reference pattern having an exposed portion is located in the straight portion of the dicing line region.

[0087] (Note 8) A semiconductor element comprising a semiconductor substrate having defined active region through which the main current flows, a terminal region which is the outer peripheral region of the active region, and a dicing line region which is the outer peripheral region of the terminal region, A manufacturing reference pattern having stepped protrusions is provided on the upper surface of the semiconductor substrate in the dicing line region. A semiconductor device wherein the manufacturing reference pattern is located in the dicing line region and is not located in at least one corner of the dicing line region.

[0088] (Note 9) The semiconductor device according to Appendix 8, wherein the manufacturing reference pattern having the stepped protruding portion is not located in the four corner portions of the dicing line region.

[0089] (Note 10) The semiconductor device according to Appendix 9, wherein the manufacturing reference pattern having the stepped protruding portion is arranged in the straight portion of the dicing line region.

[0090] (Note 11) A semiconductor element comprising a semiconductor substrate having defined active region through which the main current flows, a terminal region which is the outer peripheral region of the active region, and a dicing line region which is the outer peripheral region of the terminal region, A semiconductor device wherein a manufacturing reference metal pattern is provided on the upper surface of the semiconductor substrate corresponding to the corner portion on the dicing line region side of the termination region, and on the outer periphery of the depletion layer edge formed in the termination region when the maximum rated voltage is applied, and no annular wiring pattern is provided.

[0091] (Note 12) The semiconductor device according to Appendix 11, wherein the aforementioned manufacturing reference metal pattern is covered with at least one of an insulating film or an organic protective film.

[0092] (Note 13) The semiconductor device according to Appendix 12, wherein the insulating film is made of at least one of a silicon oxide film or a silicon nitride film.

[0093] (Note 14) The semiconductor device according to Appendix 12, wherein the organic protective film is made of polyimide or polyamide.

[0094] (Note 15) The semiconductor element is a trench-gate type semiconductor element having a gate electrode embedded in a trench formed in the active region, The height position of the upper surface of the semiconductor substrate in the termination region is lower than the height position of the upper surface of the gate electrode. The semiconductor device according to any one of the appendices 11 to 14, wherein the metal pattern for reference during manufacturing is located on the upper surface of the semiconductor substrate in the termination region, which is formed at a lower height than the upper surface of the gate electrode.

[0095] (Note 16) The semiconductor device according to any one of the appendices 11 to 15, wherein the height position around the manufacturing reference metal pattern on the upper surface of the semiconductor substrate is higher than the height position of the upper surface of the manufacturing reference metal pattern.

[0096] (Note 17) The semiconductor device according to any one of the appendices 11 to 16, wherein the metal pattern for reference during manufacturing is located at the corners at both ends of the straight portion of the termination region where the control pads of the semiconductor element are located.

[0097] (Note 18) The semiconductor element further comprises a protective film covering the active region and the termination region on the upper surface of the semiconductor substrate. The semiconductor device according to Appendix 17, wherein at least a portion of the upper surface of the aforementioned reference metal pattern during manufacturing is exposed from the protective film.

[0098] (Note 19) A manufacturing method for a semiconductor device described in any one of the following items: Appendix 1 to Appendix 4, or Appendix 11 to Appendix 18, A method for manufacturing a semiconductor device, comprising manufacturing the semiconductor device by performing the manufacturing process of the semiconductor device using the aforementioned reference metal pattern during manufacturing.

[0099] (Note 20) A manufacturing method for a semiconductor device described in any one of the appendices 5 to 10, A method for manufacturing a semiconductor device, comprising manufacturing the semiconductor device by performing the manufacturing process of the semiconductor device using the aforementioned manufacturing reference pattern. [Explanation of symbols]

[0100] 1 n + substrate, 2 n - Drift layer, 3 p well layer, 4 p FLR layer, 5 p + 101 Contact layer, 102 n-channel stopper layer, 103 underlay insulating film, 104 field insulating film, 105 interlayer insulating film, 106 silicide layer, 11 source electrode, 12 silicide layer, 13 drain electrode, 14 gate electrode, 15 gate wiring, 16 insulating film, 17 organic protective film, 19 protective film, 21 insulating film, 24 junction layer, 25 base substrate, 26 mold resin, 27 p-type diffusion layer, 28 trench, 100 semiconductor element, 101 active region, 102 gate wiring, 103 gate pad region, 104 termination region, 105 dicing line region, 106a metal pattern, 106b,106c groove pattern, 106d polysilicon pattern, 106e insulating film pattern, 106f metal pattern, 107 dicing line, 108 depletion layer edge, 110 semiconductor substrate, 200 semiconductor wafer, 201 Wafer area, 202 area.

Claims

1. A semiconductor element comprising a semiconductor substrate having defined active region through which the main current flows, a terminal region which is the outer peripheral region of the active region, and a dicing line region which is the outer peripheral region of the terminal region, A metal pattern for reference during manufacturing is provided on the upper surface of the semiconductor substrate in the dicing line region. A semiconductor device wherein the manufacturing reference metal pattern is located in the dicing line region and is not located in at least one corner of the dicing line region.

2. The semiconductor device according to claim 1, wherein the metal pattern for reference during manufacturing is not located in the four corner portions of the dicing line region.

3. The semiconductor device according to claim 2, wherein the metal pattern for reference during manufacturing is arranged in the straight portion of the dicing line region.

4. The semiconductor device according to claim 1, wherein the metal pattern used for reference during manufacturing is covered with a protective film.

5. A semiconductor element comprising a semiconductor substrate having defined active region through which the main current flows, a terminal region which is the outer peripheral region of the active region, and a dicing line region which is the outer peripheral region of the terminal region, A manufacturing reference pattern having an exposed portion is provided on the upper surface of the semiconductor substrate in the dicing line region. A semiconductor device wherein the manufacturing reference pattern is located in the dicing line region and is not located in at least one corner of the dicing line region.

6. The semiconductor device according to claim 5, wherein the manufacturing reference pattern having an exposed portion is not located at the four corners of the dicing line region.

7. The semiconductor device according to claim 6, wherein the manufacturing reference pattern having an exposed portion is arranged in the straight portion of the dicing line region.

8. A semiconductor element comprising a semiconductor substrate having defined active region through which the main current flows, a terminal region which is the outer peripheral region of the active region, and a dicing line region which is the outer peripheral region of the terminal region, A manufacturing reference pattern having stepped protrusions is provided on the upper surface of the semiconductor substrate in the dicing line region. A semiconductor device wherein the manufacturing reference pattern is located in the dicing line region and is not located in at least one corner of the dicing line region.

9. The semiconductor device according to claim 8, wherein the manufacturing reference pattern having stepped protrusions is not located in the four corners of the dicing line region.

10. The semiconductor device according to claim 9, wherein the manufacturing reference pattern having the stepped protruding portion is arranged in the straight portion of the dicing line region.

11. A semiconductor element comprising a semiconductor substrate having defined active region through which the main current flows, a terminal region which is the outer peripheral region of the active region, and a dicing line region which is the outer peripheral region of the terminal region, A semiconductor device wherein a manufacturing reference metal pattern is provided on the upper surface of the semiconductor substrate corresponding to the corner portion on the dicing line region side of the termination region, and on the outer periphery of the depletion layer edge formed in the termination region when the maximum rated voltage is applied, and no annular wiring pattern is provided.

12. The semiconductor device according to claim 11, wherein the metal pattern used for reference during manufacturing is covered with at least one of an insulating film or an organic protective film.

13. The semiconductor device according to claim 12, wherein the insulating film comprises at least one of a silicon oxide film or a silicon nitride film.

14. The semiconductor device according to claim 12, wherein the organic protective film is made of polyimide or polyamide.

15. The semiconductor element is a trench-gate type semiconductor element having a gate electrode embedded in a trench formed in the active region, The height position of the upper surface of the semiconductor substrate in the termination region is lower than the height position of the upper surface of the gate electrode. The semiconductor device according to claim 11, wherein the metal pattern for reference during manufacturing is located on the upper surface of the semiconductor substrate in the termination region, which is formed at a lower height than the upper surface of the gate electrode.

16. The semiconductor device according to claim 11, wherein the height position around the manufacturing reference metal pattern on the upper surface of the semiconductor substrate is higher than the height position on the upper surface of the manufacturing reference metal pattern.

17. The semiconductor device according to claim 11, wherein the metal pattern for reference during manufacturing is located at the corners at both ends of the straight portion of the termination region where the control pads of the semiconductor element are located.

18. The semiconductor element further comprises a protective film covering the active region and the termination region on the upper surface of the semiconductor substrate. The semiconductor device according to claim 17, wherein at least a portion of the upper surface of the metal pattern used for reference during manufacturing is exposed from the protective film.

19. A manufacturing method for manufacturing a semiconductor device according to any one of claims 1 to 4 or 11 to 18, A method for manufacturing a semiconductor device, comprising manufacturing the semiconductor device by performing the manufacturing process of the semiconductor device using the aforementioned reference metal pattern during manufacturing.

20. A manufacturing method for manufacturing a semiconductor device according to any one of claims 5 to 10, A method for manufacturing a semiconductor device, comprising manufacturing the semiconductor device by performing the manufacturing process of the semiconductor device using the aforementioned manufacturing reference pattern.

Images