Semiconductor device and method for manufacturing the same

Abstract

To provide a semiconductor device and a method for manufacturing the same that improve reliability. [Solution] The semiconductor device package includes a die pad DP, a semiconductor chip CHP1 mounted on the die pad DP via a conductive member BD1, and a lead terminal LD1 electrically connected to the source electrode SE1 of the semiconductor chip CHP1 via a bonding member BW1. Here, the source electrode SE1 includes a detection point for detecting the value of the current flowing through a power transistor provided on the semiconductor chip CHP1, and a bonding point BW1a to which the bonding member BW1 is bonded. The sense transistor provided on the semiconductor chip CHP1, the detection point, and the bonding point BW1a do not overlap with the first region FE1 of the die pad DP, but they overlap with the second region FE2 of the die pad DP. Furthermore, the thickness of the conductive member BD1 provided in the second region FE2 is greater than the thickness of the conductive member BD1 provided in the first region FE1.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same.

Background Art

[0002] A semiconductor device in which a power semiconductor chip having a power transistor and a control semiconductor chip having a control circuit for controlling the gate potential of the power transistor are encapsulated is known. In addition, the control semiconductor chip may have a function of detecting the value of the load current of the power transistor. In order to detect the value of the load current, a sense transistor for current sensing is provided in the power semiconductor chip in addition to the power transistor used as a main cell, and a detection location for detecting the value of the current is provided at a part of the source electrode of the power transistor. In the sense circuit provided in the control semiconductor chip, the value of the current flowing through the power transistor is measured based on the value of the current flowing through the sense transistor and a preset sense ratio.

[0003] For example, Patent Document 1 (U.S. Patent Application Publication No. 2023 / 0369278) discloses a semiconductor device in which the source electrode of a power semiconductor chip mounted on a die pad via a die bonding material is electrically connected to a lead terminal via a wire.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] As mentioned above, in order to detect the load current, a sense transistor for current sensing may be provided on the semiconductor chip, or a detection point for detecting the value of the current may be provided on a part of the source electrode of a power transistor provided on the semiconductor chip. However, the electrical characteristics of the semiconductor device may fluctuate due to changes in the state of the die bond material.

[0006] Other challenges and novel features will become apparent from the description and accompanying drawings in this specification. [Means for solving the problem]

[0007] A semiconductor device according to one embodiment includes a die pad, a first semiconductor chip mounted on the die pad, a first lead terminal positioned away from the die pad, a conductive member positioned between the first semiconductor chip and the die pad, and a conductive first bonding member. The first semiconductor chip includes a sense transistor, a power transistor, and a first source electrode electrically connected to the source region of the power transistor. The first source electrode is electrically connected to the first lead terminal via the first bonding member, and the first source electrode includes a detection location for detecting the value of the current flowing through the power transistor and a first bonding location to which the first bonding member is bonded. In a transmitted plan view, the die pad has a first region overlapping with the first semiconductor chip and a second region overlapping with the first semiconductor chip but different from the first region. In a transmitted plan view, the sense transistor, the detection location, and the first bonding location do not overlap with the first region but overlap with the second region. In a cross-sectional view, the thickness of the conductive member provided in the second region is greater than the thickness of the conductive member provided in the first region.

[0008] A method for manufacturing a semiconductor device according to one embodiment includes the steps of: (a) preparing a die pad having a first region and a second region different from the first region; (b) mounting a first semiconductor chip having a sense transistor, a power transistor, and a first source electrode electrically connected to the source region of the power transistor onto the die pad via a conductive member; and (c) bonding a conductive first bonding member to the first source electrode. The first source electrode includes a detection location for detecting the value of the current flowing through the power transistor and a first bonding location to which the first bonding member is bonded. In step (b), the first semiconductor chip is mounted on the die pad such that, in a transmitted planar view, the sense transistor, the detection location, and the first bonding location to which the first bonding member is bonded in step (c) do not overlap with the first region but overlap with the second region. After step (b), in a cross-sectional view, the thickness of the conductive member provided in the second region is greater than the thickness of the conductive member provided in the first region. [Effects of the Invention]

[0009] According to one embodiment, the reliability of semiconductor devices can be improved. [Brief explanation of the drawing]

[0010] [Figure 1] Figure 1 is an equivalent circuit diagram showing a semiconductor device in one embodiment. [Figure 2] Figure 2 is a plan view showing the mounting configuration of a semiconductor device in one embodiment. [Figure 3A] Figure 3A is a cross-sectional view along line AA shown in Figure 2. [Figure 3B] Figure 3B is a cross-sectional view along line BB shown in Figure 2. [Figure 4] Figure 4 is a plan view of the main part, which is an enlarged portion of Figure 2. [Figure 5] Figure 5 is a plan view of the main part, which is an enlarged portion of Figure 2. [Figure 6]FIG. 6 is a plan view for explaining the configuration of a die pad in one embodiment. [Figure 7] FIG. 7 is a cross-sectional view showing the mounting configuration of a semiconductor device in a study example. [Figure 8] FIG. 8 is a cross-sectional view showing a power transistor and a sense transistor in one embodiment. [Figure 9] FIG. 9 is a cross-sectional view showing a MOSFET in one embodiment. [Figure 10] FIG. 10 is a plan view for explaining the position of a detection location in one embodiment. [Figure 11] FIG. 11 is a plan view for explaining the configuration of a die pad in one embodiment. [Figure 12] FIG. 12 is a flowchart of a method for manufacturing a semiconductor device in one embodiment. [Figure 13A] FIG. 13A is a cross-sectional view showing a method for manufacturing a semiconductor device in one embodiment. [Figure 13B] FIG. 13B is a cross-sectional view when cut in a direction different from that of FIG. 13A. [Figure 14A] FIG. 14A is a cross-sectional view showing a method for manufacturing a semiconductor device following FIGS. 13A and 13B. [Figure 14B] FIG. 14B is a cross-sectional view when cut in a direction different from that of FIG. 14A.

DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, embodiments will be described in detail based on the drawings. In all the drawings for explaining the embodiments, members having the same function are denoted by the same reference numerals, and repeated explanations thereof are omitted. Further, in the following embodiments, explanations of the same or similar parts are not repeated as a rule, unless particularly necessary.

[0012] In this application, the description of the embodiments is divided into multiple sections or the like for convenience as necessary. However, unless otherwise explicitly stated, these are not mutually independent and separate. Regardless of the order of description, each part of a single example, one is a detailed part, a partial or complete modification example, etc. of the other. Also, in principle, repeated explanations of similar parts are omitted. Further, each component in the embodiments is not essential unless otherwise explicitly stated, limited in number theoretically, or clearly not so from the context.

[0013] Also, the X direction, Y direction, and Z direction described in this application intersect and are orthogonal to each other. In this application, the Z direction is described as the vertical direction, depth direction, or thickness direction of a certain structure. Further, expressions such as "plan view" or "plan view" used in this application mean looking at the plane composed of the X direction and Y direction from the Z direction with this "plane" being the "plane".

[0014] Also, in the accompanying drawings, conversely, when it becomes complicated or the distinction from voids is clear, hatching or the like may be omitted even for a cross-section. In this regard, in some cases where it is clear from the description or the like, even for a planar closed hole, the background contour line may be omitted. Further, in order to indicate that it is not a void or to indicate the boundary of a region, hatching or a dot pattern may be added even if it is not a cross-section.

[0015] <Equivalent Circuit of Semiconductor Device> Hereinafter, with reference to FIG. 1, the semiconductor device PKG according to this embodiment will be described. The semiconductor device PKG is a semiconductor package including a semiconductor chip CHP1 and a semiconductor chip CHP2.

[0016] As shown in FIG. 1, the semiconductor chip CHP1 has a power transistor 11 and a sense transistor 12. The power transistor 11 constitutes the main cell of the semiconductor chip CHP1. The sense transistor 12 is used when detecting the value of the current flowing through the power transistor 11.

[0017] For example, the power transistor 11 and the sense transistor 12 form a current mirror circuit such that the ratio of the current flowing through the power transistor 11 to the current flowing through the sense transistor 12 is 10000:1 (sense ratio).

[0018] Furthermore, the source electrode SE1 of the power transistor 11 includes a detection point 13 for detecting the value of the current flowing through the power transistor 11.

[0019] The semiconductor chip CHP2 has a gate potential control circuit 21 and a sense circuit 22. The gate potential control circuit 21 is electrically connected to the gate electrodes of the power transistor 11 and the sense transistor 12, respectively. The gate potential control circuit 21 controls the gate potential supplied to the power transistor 11, thereby controlling the on / off state of the power transistor 11.

[0020] The sense circuit 22 is electrically connected to the source electrode SE1 via the detection point 13 and is also electrically connected to the source region of the sense transistor 12. The sense circuit 22 measures the value of the current flowing through the power transistor 11 based on the value of the current flowing through the sense transistor 12 and a preset sense ratio.

[0021] In detail, the sense circuit 22 receives the source voltage of the sense transistor 12 from pad PD2, which is electrically connected to the sense transistor 12, and the source voltage of the power transistor 11 from pad PD1, which is electrically connected to source electrode SE1. The sense circuit 22 then corrects the difference between the source voltage of the sense transistor 12 and the source voltage of the power transistor 11 so that it becomes zero. In other words, the sense circuit 22 corrects the source voltage of the sense transistor 12 and the source voltage of the power transistor 11 so that they become equal. After that, the sense circuit 22 converts the sense current input from pad PD2 into a voltage signal. In this way, the value of the current flowing through the power transistor 11 is measured based on the voltage signal and a preset sense ratio.

[0022] The sense ratio is calculated as "the value of the current flowing through power transistor 11 / the value of the current flowing through sense transistor 12". The "value of the current flowing through sense transistor 12" can be calculated by substituting it with "the source voltage of power transistor 11 input from pad PD1 / the resistance value of sense transistor 12".

[0023] If an abnormal value, such as an overcurrent, is detected in the current flowing through the power transistor 11, the gate potential control circuit 21 controls the gate potential supplied to the power transistor 11, for example, by turning off the power transistor 11.

[0024] <Implementation configuration of semiconductor device> The mounting configuration of the semiconductor device package will be described below with reference to Figures 2, 3A, and 3B. Figure 3A is a cross-sectional view along line AA shown in Figure 2. Figure 3B is a cross-sectional view along line BB shown in Figure 2.

[0025] As shown in Figures 2, 3A, and 3B, the semiconductor device package comprises a semiconductor chip CHP1, a semiconductor chip CHP2, a die pad DP, a lead terminal LD1, a lead terminal LD2, multiple lead terminals LD3, a wire BW1, a wire BW2, multiple wires BW3, and a resin encapsulant MR.

[0026] The die pad DP, lead terminal LD1, lead terminal LD2, and multiple lead terminals LD3 are arranged apart from each other and are made of a metallic material such as a copper alloy.

[0027] The semiconductor chip CHP1 has an upper surface TS1 and a lower surface BS1. The lower surface BS1, when the semiconductor chip CHP1 is mounted on the die pad DP, has a region FE11 that overlaps with region FE1 of the die pad DP, and a region FE12 that overlaps with region FE2 of the die pad DP, as shown in Figures 3A and 3B. The semiconductor chip CHP1 has a source electrode SE1, a gate pad GP, a pad PD1, and a pad PD2 formed on the upper surface TS1. The source electrode SE1 and pad PD1 are electrically connected to the source region of the power transistor 11, respectively. The gate pad GP is electrically connected to the gate electrodes of the power transistor 11 and the sense transistor 12, respectively. Pad PD2 is electrically connected to the source region of the sense transistor 12.

[0028] Furthermore, the semiconductor chip CHP1 has a drain electrode DE formed on its lower surface BS1. The drain electrode DE is electrically connected to the drain regions of the power transistor 11 and the sense transistor 12, respectively.

[0029] The semiconductor chip CHP1 is mounted on the die pad DP via a conductive bonding material (die bond material) BD1, with its bottom surface BS1 facing the die pad DP. That is, the drain electrode DE is electrically connected to the die pad DP via the conductive bonding material BD1. The conductive bonding material BD1 is, for example, solder and silver paste. As shown in Figures 3A and 3B, the die pad DP has grooves formed on its sides and bottom surface (corresponding to the top surface DPa, which will be described later). The detailed structure of the die pad DP will be described later.

[0030] The semiconductor chip CHP2 has an upper surface TS2 and a lower surface BS2. The semiconductor chip CHP2 has a plurality of pads PD3 formed on the upper surface TS2. The semiconductor chip CHP2 is mounted on the source electrode SE1 via an insulating bonding material (die bond material) BD2 such that the lower surface BS2 faces the upper surface TS1 of the semiconductor chip CHP1. The insulating bonding material BD2 is, for example, a DAF (Die Attach Film) material.

[0031] The source electrode SE1 is electrically connected to the lead terminal LD1 via a conductive bonding wire BW1. The source electrode SE1 is electrically connected to the lead terminal LD2 via a conductive bonding wire BW2. As shown in Figure 2, the semiconductor chip CHP2 is located between wires BW1 and BW2. The gate pad GP, pad PD1, and pad PD2 are each electrically connected to a portion of a plurality of pads PD3 via a conductive bonding wire BW3. The remaining portions of the plurality of pads PD3 are each electrically connected to a plurality of lead terminals LD3 via wire BW3.

[0032] To reduce the resistance component connected to the source electrode SE1, wires BW1 and BW2 are each thicker than wire BW3. That is, the diameter of each wire BW1 and BW2 is greater than the diameter of wire BW3. Wires BW1 and BW2 are each made of, for example, aluminum or an aluminum alloy. Wire BW3 is made of, for example, gold.

[0033] The semiconductor chips CHP1 and CHP2, die pad DP, lead terminals LD1 and LD2, multiple lead terminals LD3, wires BW1, BW2, and multiple wires BW3 are sealed by a resin encapsulator MR. A portion of each of the die pad DP, lead terminals LD1, LD2, and multiple lead terminals LD3 is exposed to the outside of the resin encapsulator MR. The resin encapsulator MR is made of a thermosetting resin material, such as epoxy resin.

[0034] The detailed structure around detection point 13 will be explained below using Figure 4. Note that the joint point BW1a shown in Figure 4 is the point where wire BW1 is joined to the source electrode SE1.

[0035] As shown in Figure 4, the source electrode SE1 includes a detection point 13 near the junction BW1a for detecting the value of the current flowing through the power transistor 11.

[0036] The source wiring SW1, drawn from detection point 13, is routed around source electrode SE1 and electrically connected to pad PD1. A portion of source electrode SE1 is modified to secure an area for positioning source wiring SW1. In other words, the part of source electrode SE1 to which source wiring SW1 is connected is detection point 13. For convenience, separate symbols are used here, but source electrode SE1, source wiring SW1, and pad PD1 are made of the same conductive film and are integrated.

[0037] The source electrode SE1 is electrically connected to the sense circuit 22 of the semiconductor chip CHP2 via the detection point 13, source wiring SW1, pad PD1, wire BW3, and pad PD3.

[0038] The detailed structure around the sense transistor 12 is described below using Figure 5. Note that the junction BW2a shown in Figure 5 is the point where wire BW2 is connected to the source electrode SE1.

[0039] As shown in Figure 5, the semiconductor chip CHP1 has a source electrode SE2 formed on its upper surface TS1. The source electrode SE2 is physically separated from the source electrode SE1. The power transistor 11 is formed below the source electrode SE1. The sense transistor 12 is formed below the source electrode SE2. The source region of the sense transistor 12 is electrically connected to the source electrode SE2.

[0040] The source wiring SW2, which is drawn from the source electrode SE2, is electrically connected to the pad PD2. Note that the source electrode SE2, source wiring SW2, and pad PD2 are made of the same conductive film and are integrated into a single unit.

[0041] The source region of the sense transistor 12 is electrically connected to the sense circuit 22 of the semiconductor chip CHP2 via the source electrode SE2, source wiring SW2, pad PD2, wire BW3, and pad PD3.

[0042] Furthermore, as shown in Figures 4 and 5, the gate wiring GW drawn from the gate pad GP is routed around the source electrode SE1. Although not shown, the gate wiring GW is electrically connected to the gate electrodes of the power transistor 11 and the sense transistor 12, respectively. The gate pad GP and the gate wiring GW are made of the same conductive film and are integrated together.

[0043] The gate electrodes of the power transistor 11 and the sense transistor 12 are electrically connected to the gate potential control circuit 21 of the semiconductor chip CHP2 via gate wiring GW, gate pad GP, wire BW3, and pad PD3.

[0044] Furthermore, the semiconductor chip CHP2 is mounted on the source electrode SE1 so as to be located between junction BW1a and junction BW2a.

[0045] The structure of the die pad DP will be described below using Figures 3A, 3B, and 6. As shown in Figure 6, the die pad DP has region FE1 and region FE2, which is different from region FE1. Region FE1 is the region enclosed by the solid line L1 in Figure 6. Region FE1 overlaps with semiconductor chips CHP1 and CHP2 when they are mounted on the die pad DP. On the other hand, region FE2 is the region enclosed by the solid line L2 in Figure 6, excluding the region enclosed by the solid line L1. That is, as shown in Figure 6, region FE1 is enclosed by region FE2. Region FE2 overlaps with semiconductor chip CHP1 when they are mounted on the die pad DP, but does not overlap with semiconductor chip CHP2. In other words, region FE2 is the region sandwiched between the outer periphery of semiconductor chip CHP1 and the outer periphery of region FE1 when semiconductor chips CHP1 and CHP2 are mounted on the die pad DP. After semiconductor chip CHP1 is mounted on the die pad DP, as shown in Figures 3A and 3B, the distance between the upper surface DPa (corresponding to the bottom surface of the groove) of the die pad DP in region FE2 and the lower surface of semiconductor chip CHP1 in region FE12 is greater than the distance between the upper surface DPa of the die pad DP in region FE2 and the lower surface of semiconductor chip CHP1 in region FE11. Also, in Figures 3A and 3B, the thickness of the die pad DP in region FE2 is smaller than the thickness of the die pad DP in region FE1. The difference between the thickness of the die pad DP in region FE2 and the thickness of the die pad DP in region FE1 is, for example, 5 μm or more and 90 μm or less. In this embodiment, the difference between the thickness of the die pad DP in region FE2 and the thickness of the die pad DP in region FE1 is 30 μm or more and 60 μm or less. The difference between the thickness of region FE2 and the thickness of region FE1 is the thickness of region FE1 minus the thickness of region FE2.

[0046] As shown in Figure 6, the sense transistor 12 does not overlap with region FE1, but it does overlap with region FE2. That is, in a transmitted plan view, the sense transistor 12 is located within region FE2. As shown in Figure 6, the detection point 13 does not overlap with region FE1, but it does overlap with region FE2. That is, in a transmitted plan view, the detection point 13 is located within region FE2. As shown in Figure 6, the junction point BW1a does not overlap with region FE1, but it does overlap with region FE2. That is, in a transmitted plan view, the junction point BW1a is located within region FE2. As shown in Figure 6, the junction point BW2a does not overlap with region FE1, but it does overlap with region FE2. That is, in a transmitted plan view, the junction point BW2a is located within region FE2.

[0047] As shown in Figure 6, the semiconductor chip CHP2 overlaps with region FE1. However, in this embodiment, as shown in Figure 6, the semiconductor chip CHP2 does not overlap with region FE2. That is, in a transmitted planar view, the semiconductor chip CHP2 is located within region FE1.

[0048] As shown in Figure 6, region FE2 is provided circumferentially along the edge of the semiconductor chip CHP1. Also, in a plan view, the area of ​​region FE1 is larger than the area of ​​region FE2.

[0049] As shown in Figures 3A and 3B, the thickness of the conductive bonding material BD1 provided in region FE2 is greater than the thickness of the conductive bonding material BD1 provided in region FE1. The conductive bonding material BD1 is formed to fill the grooves formed in the die pad DP.

[0050] The thickness of the conductive bonding material BD1 provided in region FE1 is, for example, 10 μm or more and 40 μm or less. The thickness of the conductive bonding material BD1 provided in region FE2 is, for example, 40 μm or more and 100 μm or less. The difference between the thickness of the conductive bonding material BD1 provided in region FE1 and the thickness of the conductive bonding material BD1 provided in region FE2 is, for example, 5 μm or more and 90 μm or less. In particular, the difference between the thickness of the conductive bonding material BD1 provided in region FE1 and the thickness of the conductive bonding material BD1 provided in region FE2 is 30 μm and 60 μm or less. The difference between the thickness of the conductive bonding material BD1 provided in region FE1 and the thickness of the conductive bonding material BD1 provided in region FE2 is the thickness of the conductive bonding material BD1 provided in region FE2 minus the thickness of the conductive bonding material BD1 provided in region FE1.

[0051] Next, the effects of the semiconductor device package according to this embodiment will be described. In a semiconductor device package that includes a semiconductor chip CHP1 on which a power transistor 11 is formed, there is a semiconductor device package that has a sense transistor 12 mounted on the semiconductor chip CHP1 in order to detect the current flowing through the power transistor 11.

[0052] In such a semiconductor device package, an external shunt resistor, which is typically used to detect the current flowing through the power transistor 11, becomes unnecessary. Therefore, a semiconductor device package including the sense transistor 12 is effective in reducing mounting area and the number of components.

[0053] In a system where the current flowing through a load is controlled by a power transistor 11, high-precision detection of the current flowing through the power transistor 11 is crucial for achieving highly efficient control. Therefore, it is desirable that the sense transistor 12, which has the function of detecting the current flowing through the power transistor 11, has a high-precision current detection function. In other words, it is desirable to improve the current sensing function of the sense transistor 12.

[0054] Furthermore, a market requirement for semiconductor device packages equipped with power transistors 11 is to reduce on-resistance. Therefore, the on-resistance of power transistors 11 is reduced by optimizing the channel region and drift region NV of MOSFET 1Q, which constitutes the power transistor 11, and thereby reducing the resistance of MOSFET 1Q.

[0055] However, as the resistance of MOSFET1Q was reduced, the current flowing through power transistor 11 and sense transistor 12 became susceptible to manufacturing variations in the semiconductor device and changes in the state of the die bond material.

[0056] Specifically, when the MOSFET 1Q constituting the power transistor 11 is ON, the current flows through the die pad DP, the conductive bonding material (die bond material) BD1, the drain electrode DE, the power transistor 11, and the source electrode SE1. In other words, when the MOSFET 1Q is ON, the current flows mainly in the thickness direction of the semiconductor chip CHP1. Therefore, if a crack occurs in the die bond material, which is located directly beneath the detection point 13, the junction point BW1a, and the junction point BW2a and serves as the current path, the current flowing through the power transistor 11 will also change. That is, the electrical characteristics of the semiconductor device will fluctuate. Furthermore, it is preferable to position the detection point 13 so that a representative value (average value) of the potential output from the source of the power transistor 11 can be obtained, and it is desirable to ensure that it is not affected by manufacturing variations in the semiconductor device or changes in the state of the die bond material. The same applies to the sense transistor 12 that detects the value of the current flowing through the power transistor 11.

[0057] Figure 7 shows a semiconductor device PKG01 of a study example that the inventors of the present invention have examined. As can be seen by comparing Figure 7 with Figures 3A and 3B, in the study example, no grooves are formed on the die pad DP.

[0058] In contrast, in the semiconductor device package according to this embodiment, grooves are provided in the region FE2 that overlaps with the sense transistor 12, the detection location 13, the junction location BW1a, and the junction location BW2a. Therefore, the thickness of the conductive bonding material BD1 located directly beneath the sense transistor 12, the detection location 13, the junction location BW1a, and the junction location BW2a can be increased. The greater the thickness of the conductive bonding material BD1, the less likely cracks are to occur. This makes it possible to suppress the occurrence of cracks in the conductive bonding material BD1 located directly beneath the sense transistor 12, the detection location 13, the junction location BW1a, and the junction location BW2a due to the thermal history and temperature differences of the semiconductor device package. Furthermore, since cracks do not occur in the conductive bonding material BD1 located directly beneath the sense transistor 12, the detection location 13, the junction location BW1a, and the junction location BW2a, the current detection accuracy of the sense transistor 12 can be improved.

[0059] Here, the greater the thickness of the conductive bonding material BD1, the less likely cracks are to occur, but the greater the resistance of the conductive bonding material BD1. Therefore, increasing the overall thickness of the conductive bonding material BD1 increases the overall resistance of the conductive bonding material BD1. In other words, the on-resistance of the power transistor 11 increases. However, in the semiconductor device package according to this embodiment, the thickness of the conductive bonding material BD1 provided in region FE1 is smaller than the thickness of the conductive bonding material BD1 provided in region FE2. That is, the overall thickness of the conductive bonding material BD1 is not increased. Therefore, the increase in the on-resistance of the power transistor 11 can be suppressed. As a result, the reliability of the semiconductor device package is improved. Furthermore, since region FE1, where the thickness of the conductive bonding material BD1 is small, does not overlap with the sense transistor 12, detection point 13, bonding point BW1a, and bonding point BW2a, even if a crack occurs in region FE1 where the thickness of the conductive bonding material BD1 is small, the current detection accuracy of the sense transistor 12 is less likely to decrease. Therefore, it is possible to achieve both improved current detection accuracy and reduced on-resistance.

[0060] Next, other effects will be described. In the semiconductor device package according to this embodiment, region FE2 is provided circumferentially along the edge of the semiconductor chip CHP1. This makes it possible to increase the thickness of the edge portion of the conductive bonding material BD1, which is prone to cracking. As a result, cracks are less likely to occur in the conductive bonding material BD1. Consequently, the current detection accuracy of the sense transistor 12 can be further improved.

[0061] Furthermore, in a plan view, the area of ​​region FE1 is larger than the area of ​​region FE2. This allows for a larger area where the thickness of the conductive bonding material BD1 is small. As a result, the on-resistance of the power transistor 11 can be further reduced.

[0062] <Cross-sectional structure of power transistors and sense transistors> The cross-sectional structures of the multiple MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) constituting the power transistor 11 and sense transistor 12 will be described below with reference to Figures 8 and 9.

[0063] As shown in Figure 8, multiple n-type MOSFETs 1Q are formed on the semiconductor substrate SUB. The power transistor 11 shown in Figure 1 is composed of multiple MOSFETs 1Q connected in parallel. The sense transistor 12 shown in Figure 1 is composed of at least one MOSFET 1Q. The sense transistor 12 may also be composed of multiple MOSFETs 1Q connected in parallel, in which case the number of MOSFETs 1Q constituting the sense transistor 12 is less than the number of MOSFETs 1Q constituting the power transistor 11.

[0064] The sense ratio is substantially determined by the ratio of the area on which the MOSFET1Q constituting the power transistor 11 is formed to the area on which the MOSFET1Q constituting the sense transistor 12 is formed.

[0065] The detailed structure of MOSFET1Q is described below with reference to Figure 9.

[0066] As shown in Figure 9, the semiconductor substrate SUB has an upper surface TS3 and a lower surface BS3 and is made of n-type silicon. The semiconductor substrate SUB has an n-type drift region NV and an n-type drain region ND. The drain region ND is formed in the semiconductor substrate SUB with a predetermined thickness extending from the lower surface BS3 to the upper surface TS3 of the semiconductor substrate SUB. The drain region ND has a higher impurity concentration than the drift region NV.

[0067] The semiconductor substrate SUB may be a single-crystal n-type silicon substrate, or it may be a laminate of an n-type silicon substrate and an n-type semiconductor layer grown on the n-type silicon substrate by epitaxial growth while introducing phosphorus (P).

[0068] A drain electrode DE is formed beneath the lower surface BS3 of the semiconductor substrate SUB. The drain electrode DE consists of a single layer of metal film, such as an aluminum film, titanium film, nickel film, gold film, or silver film, or a multilayer film formed by appropriately stacking these metal films. The drain region ND and the drain electrode DE are formed across the entire lower surface BS3 of the semiconductor substrate SUB. Drain potential is supplied to the semiconductor substrate SUB (drain region ND, drift region NV) from the drain electrode DE.

[0069] A trench TR is formed in the semiconductor substrate SUB, extending to a predetermined depth from the upper surface TS3 of the semiconductor substrate SUB. Inside the trench TR, a gate electrode GE is formed via a gate insulating film GI. The gate insulating film GI is made of, for example, a silicon oxide film. The gate electrode GE is made of, for example, a polycrystalline silicon film into which n-type impurities have been introduced.

[0070] A p-type body region PB is formed on the semiconductor substrate SUB, extending to a predetermined depth from the top surface TS3 of the semiconductor substrate SUB. The depth of the body region PB from the top surface TS3 of the semiconductor substrate SUB is shallower than the depth of the trench TR from the top surface TS3 of the semiconductor substrate SUB. An n-type source region NS is formed within the body region PB. The source region NS has a higher impurity concentration than the drift region NV. Of the body region PB, the portion adjacent to the gate electrode GE via the gate insulating film GI and located between the source region NS and the drift region NV constitutes the channel region of MOSFET1Q.

[0071] An interlayer insulating film IL is formed on the upper surface TS3 of the semiconductor substrate SUB, covering the trench TR. The interlayer insulating film IL is made of, for example, a silicon oxide film.

[0072] Pores CH are formed in the interlayer insulating film IL. The pores CH penetrate the interlayer insulating film IL and the source region NS, and reach the body region PB. Although not shown here, pores CH reaching the gate electrode GE are also formed in the interlayer insulating film IL. A plug PG is embedded inside the pores CH. The plug PG consists of, for example, a first barrier metal film and a first conductive film formed on the first barrier metal film. The first barrier metal film consists of, for example, a laminate of a titanium film and a titanium nitride film. The first conductive film is, for example, a tungsten film.

[0073] A source electrode SE1 is formed on the interlayer insulating film IL. The source electrode SE1 is electrically connected to the source region NS and the body region PB via a plug PG, supplying a source potential to these impurity regions. A source electrode SE2 is formed above the MOSFET 1Q that constitutes the sense transistor 12.

[0074] Although not shown here, the interlayer insulating film IL also has a gate pad GP, gate wiring GW, pad PD1, source wiring SW1, pad PD2, and source wiring SW2, as shown in Figures 4 and 5. The gate pad GP is electrically connected to the gate electrode GE via the gate wiring GW and plug PG, supplying the gate potential to the gate electrode GE.

[0075] Source electrode SE1, source electrode SE2, gate pad GP, gate wiring GW, pad PD1, source wiring SW1, pad PD2, and source wiring SW2 each consist of, for example, a second barrier metal film and a second conductive film formed on the second barrier metal film. The second barrier metal film is, for example, a titanium-tungsten film. The second conductive film is, for example, an aluminum alloy film with copper or silicon added.

[0076] <Variation> Next, a modified example of the semiconductor device according to this embodiment will be described. Figure 10 is a plan view of the main parts of the semiconductor device. Figure 11 is a plan view illustrating the configuration of the die pad in one embodiment. The semiconductor device package shown in Figure 10 differs from the semiconductor device package shown in Figure 4 in that it further has a detection location 14. The bonding location BW1a shown in Figure 10 is the location where the wire BW1 of the source electrode SE1 is bonded.

[0077] As shown in Figure 10, the source electrode SE1 includes detection points 13 and 14 near the junction BW1a for detecting the value of the current flowing through the power transistor 11. Detection points 13 and 14 are positioned to sandwich the junction BW1a.

[0078] The source wiring SW1, drawn from detection points 13 and 14, is routed around the source electrode SE1 and electrically connected to the pad PD1. A portion of the source electrode SE1 is machined to secure space for the source wiring SW1. In other words, the parts of the source electrode SE1 to which the source wiring SW1 is connected are detection points 13 and 14. For convenience, separate symbols are used here, but the source electrode SE1, source wiring SW1, and pad PD1 are made of the same conductive film and are integrated.

[0079] The source electrode SE1 is electrically connected to the sense circuit 22 of the semiconductor chip CHP2 via detection point 13, detection point 14, source wiring SW1, pad PD1, wire BW3, and pad PD3. As shown in Figure 11, detection point 14 does not overlap with region FE1, but it overlaps with region FE2. That is, in a transmitted planar view, detection point 14 is located within region FE2.

[0080] According to the semiconductor device package shown in Figure 10, detection points 13 and 14 are positioned to sandwich the junction BW1a. Therefore, even if assembly variations occur at the junction BW1a, the voltages detected at the two points, detection points 13 and 14, can be averaged. This suppresses fluctuations in the rate of change of the sense ratio. As a result, the current detection accuracy of the sense transistor can be further improved.

[0081] <Manufacturing method for semiconductor devices> The following describes each manufacturing process included in the manufacturing method of a semiconductor device package, using Figures 12, 13A, 13B, 14A, and 14B.

[0082] As shown in Figures 12, 13A, and 13B, first, semiconductor chip CHP1, semiconductor chip CHP2, and lead frame LF are prepared. The lead frame LF includes lead terminals LD1, LD2, LD3, and die pad DP.

[0083] As shown in Figures 13A and 13B, a groove is provided in region FE2 of the die pad DP. The thickness of the die pad DP in region FE1 is greater than the thickness of the die pad DP in region FE2. In the lead frame preparation process, a die pad DP with a groove already formed may be used. Alternatively, in the lead frame preparation process, a die pad DP without a groove may be prepared and then grooves may be formed on the die pad DP.

[0084] Next, the semiconductor chip CHP1 is mounted on the upper surface DPa of the die pad DP via a conductive bonding material BD1 such that the lower surface BS1 of the semiconductor chip CHP1 faces the upper surface DPa of the die pad DP. The semiconductor chip CHP1 can be the semiconductor chip CHP1 of the semiconductor device package according to this embodiment. In other words, the semiconductor chip CHP1 has a power transistor 11, a sense transistor 12, and a source electrode SE1 electrically connected to the source region NS of the power transistor 11. The source electrode SE1 also includes a detection point 13 for detecting the value of the current flowing through the power transistor 11, and bonding points BW1a and BW2a, respectively, to which wires BW1 and BW2 will be bonded in a later wire bonding process.

[0085] As shown in Figure 6, in the process of mounting the semiconductor chip CHP1, the semiconductor chip CHP1 is mounted on the die pad DP such that, in a transmitted planar view, the sense transistor 12, detection area 13, junction area BW1a, and junction area BW2a do not overlap with area FE1 but overlap with area FE2.

[0086] As shown in Figures 3A and 3B, the thickness of the conductive bonding material (conductive member) BD1 provided in region FE2 is greater than the thickness of the conductive bonding material BD1 provided in region FE1.

[0087] Next, the semiconductor chip CHP2 is mounted on the source electrode SE1 via an insulating bonding material BD2 so that the lower surface BS2 of the semiconductor chip CHP2 faces the upper surface TS1 of the semiconductor chip CHP1.

[0088] Next, wire bonding is performed as shown in Figures 14A and 14B. Wire BW1 electrically connects the source electrode SE1 and the lead terminal LD1. Wire BW3 electrically connects pad PD3, which is electrically connected to the gate potential control circuit 21, and the gate pad GP. Although not shown here, wire BW2 electrically connects the source electrode SE1 and the lead terminal LD2. Wire BW3 electrically connects pad PD3, which is electrically connected to the gate potential control circuit 21, and the gate pad GP, which is connected to the gate of the power transistor 11, to each other and electrically connects them. Wire BW3 electrically connects pad PD3, which is electrically connected to the sense circuit 22, and pad PD2, which is electrically connected to the sense transistor 12. Multiple wires BW3 electrically connect multiple other pads PD3 and multiple lead terminals LD3.

[0089] Furthermore, in this wire bonding process, a portion of the wire BW1 (the bonding area) is bonded to the part of the source electrode SE1 that does not overlap with region FE1 but overlaps with region FE2 (bonding points BW1a and BW2a in Figure 6).

[0090] Subsequently, the semiconductor device package shown in Figures 2, 3A, and 3B is manufactured by following the manufacturing process described below. First, semiconductor chips CHP1 and CHP2, die pad DP, lead terminal LD1, lead terminal LD2, multiple lead terminals LD3, wire BW1, wire BW2, and multiple wires BW3 are sealed with resin to form a resin encapsulation body MR. Note that a portion of each of the die pad DP, lead terminal LD1, lead terminal LD2, and multiple lead terminals LD3 is exposed outside the resin encapsulation body MR.

[0091] Next, the die pad DP, lead terminals LD1, LD2, and LD3 are cut out from the lead frame LF. Then, lead terminals LD1, LD2, and LD3 are bent. This completes the manufacturing of the semiconductor device package.

[0092] Although the present invention has been specifically described above based on the embodiments described above, the present invention is not limited to the embodiments described above and can be modified in various ways without departing from the spirit of the invention.

[0093] For example, in the above embodiment, wires BW1, BW2, and BW3 were used as conductive joining members to connect to the lead terminals LD1, LD2, and LD3. However, if the clip has a small width (area) of the portion that connects to the source electrode SE1 or pad PD3, a clip may be used as a conductive joining member to connect to the lead terminals LD1 and LD2. [Explanation of Symbols]

[0094] 11 Power Transistors 12 sense transistors 13, 14 Detection locations 21 Gate potential control circuit 22 Sense Circuit BD1 Conductive bonding material BD2 insulating bonding material BS1, BS2, BS3 bottom side BW1 Wire BW1a Joint BW2 Wire BW2a Joint BW3 Wire CH hole CHP1, CHP2 semiconductor chips DE drain electrode DP Die Pad DPa top surface FE1, FE2, FE11, FE12 area GE Terminal GI gate insulating film GP Gate Pad GW gate wiring IL interlayer film LD1, LD2, LD3 lead terminals LF Lead Frame MR resin encapsulant ND drain area NS source area NV drift region PB Body Area PD1, PD2, PD3 pads PG Plug PKG, PKG01 Semiconductor Equipment SE1, SE2 source electrodes SUB Semiconductor Substrate SW1, SW2 Source Wiring TR Trench TS1, TS2, TS3 top side

Claims

1. Die pad and, A first semiconductor chip mounted on the die pad, A first lead terminal positioned away from the die pad, A conductive member disposed between the first semiconductor chip and the die pad, A conductive first bonding member, Equipped with, The first semiconductor chip includes a sense transistor, a power transistor, and a first source electrode electrically connected to the source region of the power transistor. The first source electrode is electrically connected to the first lead terminal via the first bonding member. The first source electrode is A detection point for detecting the value of the current flowing through the power transistor, The first joining point to which the first joining member is joined, Includes, In a transparent planar view, the die pad is The first region overlapping with the first semiconductor chip, A second region that overlaps with the first semiconductor chip and is different from the first region, It has, In a transparent planar view, the sense transistor, the detection location, and the first junction location do not overlap with the first region, but they overlap with the second region. A semiconductor device wherein, in a cross-sectional view, the thickness of the conductive member provided in the second region is greater than the thickness of the conductive member provided in the first region.

2. In the semiconductor device described in claim 1, A semiconductor device in which, in a cross-sectional view, the distance between the upper surface of the die pad in the second region and the lower surface of the first semiconductor chip in the fourth region is greater than the distance between the upper surface of the die pad in the first region and the lower surface of the first semiconductor chip in the third region.

3. In the semiconductor device described in claim 1, A semiconductor device wherein, in a plan view, the area of ​​the first region is larger than the area of ​​the second region.

4. In the semiconductor device described in claim 1, In a transparent planar view, the second region is a semiconductor device arranged circumferentially along the edge of the first semiconductor chip.

5. In the semiconductor device described in claim 1, Furthermore, the device comprises a second semiconductor chip, a second lead terminal positioned away from the die pad and the first lead terminal, and a conductive second bonding member. The first source electrode is electrically connected to the second lead terminal via the conductive second bonding member, The second semiconductor chip is mounted on the first source electrode such that it is located between the second bonding location where the conductive second bonding member is bonded to the first source electrode and the first bonding location. In a transparent planar view, the second semiconductor chip overlaps with the first region, and is a semiconductor device.

6. In the semiconductor device described in claim 5, The first semiconductor chip further comprises a source wiring drawn out from the detection location and a first pad electrically connected to the source wiring.

7. In the semiconductor device described in claim 6, The first semiconductor chip further has a second pad electrically connected to the source region of the sense transistor, The second semiconductor chip further includes a sense circuit for measuring the value of the current flowing through the power transistor based on the value of the current flowing through the sense transistor and a preset sense ratio, a third pad electrically connected to the sense circuit, and a fourth pad electrically connected to the sense circuit. The first pad is electrically connected to the third pad via a conductive third bonding member. A semiconductor device wherein the second pad is electrically connected to the fourth pad via a conductive fourth bonding member.

8. In the semiconductor device according to claim 7, A semiconductor device in which the diameters of the conductive first bonding member and the conductive second bonding member are greater than the diameters of the conductive third bonding member and the conductive fourth bonding member.

9. In the semiconductor device described in claim 2, A semiconductor device in which the difference between the thickness of the conductive member arranged in the first region and the thickness of the conductive member arranged in the second region is 5 μm or more and 90 μm or less.

10. (a) A step of preparing a die pad having a first region and a second region different from the first region, (b) A step of mounting a first semiconductor chip having a sense transistor, a power transistor, and a first source electrode electrically connected to the source region of the power transistor onto the die pad via a conductive member. (c) A step of joining a conductive first bonding member to the first source electrode, Equipped with, The first source electrode is A detection point for detecting the value of the current flowing through the power transistor, The first joining point to which the first joining member is joined, Includes, In step (b), the first semiconductor chip is mounted on the die pad such that, in a transparent planar view, the sense transistor, the detection location, and the first bonding location to which the first bonding member is bonded in step (c) do not overlap with the first region but overlap with the second region. A method for manufacturing a semiconductor device, wherein, after step (b), in a cross-sectional view, the thickness of the conductive member provided in the second region is greater than the thickness of the conductive member provided in the first region.

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