Semiconductor device and method for manufacturing a semiconductor device

Abstract

The present invention provides a semiconductor device and a method for manufacturing a semiconductor device that have a stable structure and improved characteristics. [Solution] The semiconductor device includes channel pillars 12 arranged in a first direction I and a second direction II intersecting the first direction, having a first spacing W1 in the first direction and a second spacing W2 in the second direction, with the first spacing being smaller than the second spacing; selection lines 13 surrounding the channel pillars arranged in the first direction and extending in the first direction; word lines stacked on top of the selection lines; and local bit lines that penetrate the word lines and are connected to the channel pillars.

Description

Technical Field

[0001] The present invention relates to an electronic device, and more particularly to a semiconductor device and a method of manufacturing the semiconductor device.

Background Art

[0002] The integration degree of a semiconductor device is mainly determined by the area occupied by a unit memory cell. Recently, since the improvement of the integration degree of a semiconductor device forming a memory cell in a single layer on a substrate has reached a limit, a three-dimensional semiconductor device in which memory cells are stacked on a substrate has been proposed. Also, in order to improve the operation reliability of such a semiconductor device, various structures and manufacturing methods have been developed.

Summary of the Invention

Problems to be Solved by the Invention

[0003] Embodiments of the present invention provide a semiconductor device and a method of manufacturing the semiconductor device having a stable structure and improved characteristics.

Means for Solving the Problems

[0004] A semiconductor device according to an embodiment of the present invention may include channel pillars arranged in a first direction and a second direction intersecting the first direction, having a first interval in the first direction and a second interval in the second direction, the first interval being smaller than the second interval; a selection line surrounding the channel pillars arranged in the first direction and extending in the first direction; a word line stacked on an upper portion of the selection line; and a local bit line penetrating the word line and connected to the channel pillars.

[0005] A semiconductor device according to one embodiment of the present invention may include local lines arranged in a first direction and a second direction intersecting the first direction and extending in a third direction perpendicular to the first and second directions, global lines extending in the second direction, and select transistors including channel pillars connected between the local lines and the global lines, having a first spacing in the first direction and a second spacing in the second direction, wherein the first spacing is smaller than the second spacing.

[0006] A method for manufacturing a semiconductor device according to one embodiment of the present invention may include the steps of: forming channel pillars arranged in a first direction and a second direction intersecting the first direction; forming a selection line surrounding the channel pillars and extending in the first direction; forming an insulating pillar penetrating the selection line; and forming a contact plug between the insulating pillars that is electrically connected to the selection line.

[0007] A method for manufacturing a semiconductor device according to one embodiment of the present invention may include the steps of: forming a global bit line; forming channel pillars above the global bit line, arranged in a first direction and a second direction intersecting the first direction, such that the spacing in the first direction is smaller than the spacing in the second direction; forming a selection line surrounding the channel pillars and extending in the first direction; forming local bit lines above the selection line, each connected to the channel pillars and extending in a third direction perpendicular to the first and second directions; and forming a word line surrounding the local bit line and stacked in the third direction. [Effects of the Invention]

[0008] By stacking memory cells in three dimensions, the integration density of semiconductor devices can be improved. Furthermore, it is possible to provide semiconductor devices with a stable structure and improved reliability. [Brief explanation of the drawing]

[0009] [Figure 1A] This figure shows the structure of a semiconductor device according to one embodiment of the present invention. [Figure 1B] This figure shows the structure of a semiconductor device according to one embodiment of the present invention. [Figure 1C] This figure shows the structure of a semiconductor device according to one embodiment of the present invention. [Figure 1D] This figure shows the structure of a semiconductor device according to one embodiment of the present invention. [Figure 2A] This figure shows the structure of a semiconductor device according to one embodiment of the present invention. [Figure 2B] This figure shows the structure of a semiconductor device according to one embodiment of the present invention. [Figure 2C] This figure shows the structure of a semiconductor device according to one embodiment of the present invention. [Figure 2D] This figure shows the structure of a semiconductor device according to one embodiment of the present invention. [Figure 3A] This figure illustrates a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 3B] This figure illustrates a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 3C] This figure illustrates a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 4A] This figure illustrates a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 4B] This figure illustrates a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 4C] This figure illustrates a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 5A] This figure illustrates a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 5B] This figure illustrates a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 5C] This figure illustrates a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 6A]It is a diagram for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 6B] It is a diagram for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 6C] It is a diagram for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 7A] It is a diagram for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 7B] It is a diagram for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 7C] It is a diagram for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 8A] It is a diagram for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 8B] It is a diagram for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 9A] It is a diagram for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 9B] It is a diagram for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 10A] It is a diagram for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 10B] It is a diagram for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 11A] It is a diagram showing the structure of a semiconductor device according to an embodiment of the present invention. [Figure 11B] It is a diagram showing the structure of a semiconductor device according to an embodiment of the present invention. [Figure 12] It is a circuit diagram showing a cell array of a semiconductor device according to an embodiment of the present invention. [Figure 13] It is a flowchart for explaining the flow of a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 14A] It is a diagram for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 14B] This figure illustrates a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 14C] This figure illustrates a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 14D] This figure illustrates a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 14E] This figure illustrates a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 14F] This figure illustrates a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 15A] This figure illustrates a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 15B] This figure illustrates a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 16A] This figure illustrates a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 16B] This figure illustrates a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 17A] This figure illustrates a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 17B] This figure illustrates a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 18] This is a cross-sectional view showing the structure of a semiconductor device according to one embodiment of the present invention. [Figure 19] This is a configuration diagram of a semiconductor device according to one embodiment of the present invention. [Figure 20] This is a configuration diagram of a semiconductor device according to one embodiment of the present invention. [Modes for carrying out the invention]

[0010] The following describes embodiments based on the technical concept of the present invention with reference to the attached drawings.

[0011] Figures 1A to 1D show the structure of a semiconductor device according to one embodiment of the present invention. Figure 1A is a plan view, Figure 1B is a cross-sectional view of Figure 1A along line A-A', Figure 1C is a cross-sectional view of Figure 1A along line B-B', and Figure 1D is a circuit diagram.

[0012] Referring to Figures 1A to 1C, the semiconductor device may include a channel pillar 12, a selection line 13, and a local line 17. The semiconductor device may further include at least one of a global line 11, a gap fill insulating film 14, an interlayer insulating film 15, a gate insulating film 16, a contact plug 18, and an insulating pillar 19. Here, the global line 11 may be a global bit line, and the local line 17 may be a local bit line.

[0013] The channel pillars 12 may be arranged in a first direction I and a second direction II intersecting the first direction I. The channel pillars 12 have a first spacing W1 in the first direction I and a second spacing W2 in the second direction II. The first spacing W1 and the second spacing W2 may be different, and the first spacing W1 may be smaller than the second spacing W2.

[0014] Each channel pillar 12 may include a first semiconductor film 12A, a second semiconductor film 12B, and a third semiconductor film 12C. The first semiconductor film 12A, the second semiconductor film 12B, and the third semiconductor film 12C may be stacked in a third direction III. The third direction III may be perpendicular to the first direction I and the second direction II. The second semiconductor film 12B may be located between the first semiconductor film 12A and the third semiconductor film 12C.

[0015] The first semiconductor film 12A and the third semiconductor film 12C may be junctions, and the second semiconductor film 12B may be a channel region. The first semiconductor film 12A, the second semiconductor film 12B, and the third semiconductor film 12C may contain N-type impurities, P-type impurities, or be intrinsic semiconductors. For example, the first semiconductor film 12A may contain N-type impurities, the second semiconductor film 12B may contain P-type impurities, and the third semiconductor film 12C may contain N-type impurities. The first semiconductor film 12A may contain P-type impurities, the second semiconductor film 12B may contain N-type impurities, and the third semiconductor film 12C may contain P-type impurities. The first semiconductor film 12A may contain N-type impurities, the second semiconductor film 12B may be an intrinsic semiconductor, and the third semiconductor film 12C may contain N-type impurities. The first semiconductor film 12A contains p-type impurities, the second semiconductor film 12B is an intrinsic semiconductor, and the third semiconductor film 12C may contain p-type impurities.

[0016] The selection line 13 may surround channel pillars 12 arranged in a first direction I. Channel pillars 12 arranged in a first direction I may share the selection line 13. In an example, the selection line 13 may surround the second semiconductor film 12B of the channel pillar 12, but may not surround the first semiconductor film 12A and the third semiconductor film 12C.

[0017] The selection line 13 may extend in a first direction I. The selection line 13 may include a first portion 13A extending in the first direction I and a second portion 13B connecting the first portion 13A. The second portion 13B may be located between channel pillars 12, between insulating pillars 19, or between channel pillars 12 and insulating pillars 19. The gate insulating film 16 may surround the side walls of the channel pillars 12, and the gate insulating film 16 may be interposed between the channel pillars 12 and the selection line 13.

[0018] The global line 11 may extend in the second direction II. Channel pillars 12 may be located on the global line 11. The global line 11 may be connected to channel pillars 12 arranged in the second direction II. The first semiconductor film 12A and the global line 11 may be connected.

[0019] The local lines 17 may be arranged in a first direction I and a second direction II, and may be positioned corresponding to the channel pillars 12. The local lines 17 may have a pillar shape. The local lines 17 may extend in a third direction III, for example, vertically. The local lines 17 may be positioned above the channel pillars 12. The third semiconductor film 12C and the local lines 17 may be connected. In one embodiment, the channel pillars 12 may be connected between the global bit line and the local bit lines.

[0020] A selection transistor ST may be located in the region where the global line 11 and the selection line 13 intersect. Each selection transistor ST may include a channel pillar 12, which may include a first semiconductor film 12A, a second semiconductor film 12B, and a third semiconductor film 12C. Here, the first semiconductor film 12A may be a first junction, the third semiconductor film 12C may be a second junction, and the second semiconductor film 12B may be a channel region. The selection line 13 may surround the channel region.

[0021] A gap fill insulating film 14 may be located between the global lines 11. The gap fill insulating film 14 may extend between the first semiconductor films 12A. An interlayer insulating film 15 may be located above the selection line 13. The local line 17 may penetrate the interlayer insulating film 15 and be connected to the channel pillar 12.

[0022] The insulating pillar 19 may penetrate the selection line 13 and be located on the global line 11. The insulating pillar 19 may be arranged in a first direction I and a second direction II. The insulating pillar 19 may be formed by filling the region where the channel pillar 12 has been removed with insulating material. The insulating pillar 19 may be a film integrally connected to the interlayer insulating film 15.

[0023] The contact plug 18 may penetrate the interlayer insulating film 15 and be electrically connected to the selection line 13. The contact plug 18 may be connected to the second portion 13B of the selection line 13 between adjacent insulating pillars 19 in the first direction I. The contact plug 18 may surround the top surface and side walls of the second portion 13B. A selection signal is applied to the selection line 13 via the contact plug 18, and the selection transistor ST may be turned on or turned off in response to the selection signal.

[0024] Referring to Figure 1D, the semiconductor device may include selection lines SL0~SLm, global lines GL0~GLk, local lines LL00~LLkm, selection transistor ST, global line decoder GL decoder, and selection line decoder SL decoder. The selection transistor ST may be connected between the global lines GL0~GLk and the local lines LL00~LLkm. Here, the global lines GL0~GLk may be global bit lines, and the local lines LL00~LL33 may be local bit lines. The global line decoder GL decoder may be a global bit line decoder. k and m may be non-negative integers.

[0025] Global lines GL0 to GLk can be connected to a global line decoder, GL decoder. The global line decoder, GL decoder, may include switches connected to each of the global lines GL0 to GLk. By turning the switches on or off, the global line corresponding to the address can be selected and activated.

[0026] The gate electrodes of the selection transistor ST may be connected to selection lines SL0 to SLm, and the selection lines SL0 to SLm may be connected to a selection line decoder SL decoder. The selection line decoder SL decoder may include switches connected to each of the selection lines SL0 to SLm. By turning the switches on or off, the selection line corresponding to the address can be selected and activated.

[0027] With the configuration described above, the connection between the global lines GL0~GLk and the local lines LL00~LLkm can be controlled by the selection transistor ST. The local lines LL00~LLkm, for example, the local bit lines, can be selected using the selection line decoder SL decoder and the global line decoder GL decoder.

[0028] Figures 2A to 2D show the structure of a semiconductor device according to one embodiment of the present invention. Figure 2A is a plan view, Figure 2B is a cross-sectional view of Figure 2A taken along the line A1-A1', Figure 2C is a cross-sectional view of Figure 2A taken along the line B1-B1', and Figure 2D is a circuit diagram.

[0029] Referring to Figures 2A to 2C, the semiconductor device may include a channel pillar 22, a selection line 23, and a local line 27. The semiconductor device may further include at least one of a global line 21, a gap fill insulating film 24, an interlayer insulating film 25, a gate insulating film 26, a contact plug 28, and an insulating pillar 29. Here, the global line 21 may be a global bit line, and the local line 27 may be a local bit line.

[0030] The channel pillars 22 may be arranged in a first direction I and a second direction II intersecting the first direction I. Channel pillars 22 adjacent to each other in the second direction II may be arranged with their centers staggered and in a zigzag pattern. Each channel pillar 22 may include a first semiconductor film 22A, a second semiconductor film 22B, and a third semiconductor film 22C.

[0031] The channel pillar 22 has a first spacing W1 in the first direction I and a second spacing W2 or a third spacing W3 in the second direction II. The first spacing W1 and the second spacing W2 may be different, and the second spacing W2 and the third spacing W3 may be different. The first spacing W1 may be smaller than the second spacing W2, and the third spacing W3 may be smaller than the second spacing W2.

[0032] A selection line 23 may surround a channel pillar 22 and may extend in a first direction I. In an embodiment, channel pillars 22 arranged in a first direction may constitute a row, and a selection line 23 may surround at least two rows. Channel pillars 22 surrounded by the same selection line 23 may be separated by a first interval W1 and a third interval W3. Channel pillars 22 surrounded by different selection lines 23 may be separated by a second interval W2.

[0033] Referring to Figure 2D, the semiconductor device may include selection lines SL0 to SLm, global lines GL00 to GLk1, local lines LL00_0 to LLkm_1, a selection transistor ST, a global line decoder GL decoder, and a selection line decoder SL decoder. The selection transistor ST may be connected between the global lines GL00 to GLk1 and the local lines LL00_0 to LLkm_1.

[0034] Global lines GL00 to GLk1 can be connected to the global line decoder GL decoder. Selection lines SL0 to SLm can be connected to the gate electrode of the selection transistor ST, and selection lines SL0 to SLm can be connected to the selection line decoder SL decoder.

[0035] With the configuration described above, the connection between the global lines GL00~GLk1 and the local lines LL00_0~LLkm_1 can be controlled by the selection transistor ST. The local lines LL00_0~LLkm_1, for example, the local bit lines, can be selected using the selection line decoder SL decoder and the global line decoder GL decoder.

[0036] Figures 3A to 10A, 3B to 10B, and 3C to 7C are diagrams illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. Figures 3A to 10A are plan views, Figures 3B to 7B are cross-sectional views taken along the line C-C' of Figures 3A to 7A, Figures 3C to 7C are cross-sectional views taken along the line D-D' of Figures 3A to 7A, and Figures 8B to 10B are cross-sectional views taken along the line E-E' of Figures 8A to 10A.

[0037] Referring to Figures 3A to 3C, a semiconductor film 32 is formed on the first conductive film 31. In an example, an N-type first semiconductor film 32A is formed on the first conductive film 31, a P-type second semiconductor film 32B is formed on the first semiconductor film 32A, and an N-type third semiconductor film 32C is formed on the second semiconductor film 32B.

[0038] Referring to Figures 4A to 4C, the semiconductor film 32 is etched to form a semiconductor line 32L extending in the second direction II. Subsequently, the first conductive film 31 is etched to form a global line 31A extending in the second direction II. Here, the global line 31A may be a global bit line.

[0039] Next, a first gap fill insulating film 33A may be formed between the semiconductor lines 32L and the global line 31A. The first gap fill insulating film 33A may extend in the second direction II.

[0040] Referring to Figures 5A to 5C, the semiconductor line 32L is etched to form channel pillars 32P. The channel pillars 32P may be arranged in a first direction I and a second direction II. The channel pillars 32P may have a first spacing W1 in the first direction I and a second spacing W2 in the second direction II, with the first spacing W1 being smaller than the second spacing W2. In one embodiment, the semiconductor line 32L and the first gap fill insulating film 33A are etched to form trenches extending in the first direction I. The trenches may separate channel pillars 32P adjacent to each other in the second direction II. Subsequently, a second gap fill insulating film 33B may be formed in the trenches.

[0041] Referring to Figures 6A to 6C, the first gap fill insulating film 33A and the second gap fill insulating film 33B are etched to expose the sidewalls of the channel pillars 32P. In one example, the first and second gap fill insulating films 33A and 33B are etched by an etch-back process. This allows the second semiconductor film 32B and the third semiconductor film 32C of each channel pillar 32P to be exposed.

[0042] Next, a gate insulating film 34 can be formed on the channel pillar 32P. The gate insulating film 34 can be formed so as to surround the side walls of the channel pillar 32P. The gate insulating film 34 may contain an oxide.

[0043] Next, a second conductive film 35 is formed on the gate insulating film 34. Since the channel pillars 32P adjacent to each other in the first direction I have relatively narrow spacing, the second conductive film 35 can fill the space between the channel pillars 32P adjacent to each other in the first direction I. Since the channel pillars 32P adjacent to each other in the second direction II have relatively wide spacing, the second conductive film 35 can fill only a portion of the space between the channel pillars 32P adjacent to each other in the second direction II. The second conductive film 35 may contain a metal such as tungsten.

[0044] Referring to Figures 7A to 7C, the second conductive film 35 is etched to form a selected line 35A extending in the first direction I. In one example, the second conductive film 35 is etched using an etch-back process. By etching the second conductive film 35, the upper surface of the channel pillar 32P, the gate insulating film 34, and the upper surface of the second gap fill insulating film 33B can be exposed.

[0045] Next, a treatment process can be performed on the channel pillar 32P. For example, a CO2 laser annealing process can be performed. This can increase the electron mobility of the channel pillar 32P and improve the channel characteristics.

[0046] Each selection line 35A may fill the space between adjacent channel pillars 32P in a first direction I. Each selection line 35A may extend in the first direction I so as to surround the side walls of the channel pillars 32P arranged in the first direction I. A selection line 35A may have a height that surrounds the second semiconductor film 32B, but may not surround the third semiconductor film 32C. Each selection line 35A may include a second portion 35AB that is located between a first portion 35AA and the channel pillars 32P extending in the first direction I, and connects the first portion 35AA.

[0047] Referring to Figures 8A and 8B, a portion of the channel pillar 32P is removed to form the first opening OP1. The global line 31A may be exposed through the first opening OP1. In one embodiment, a mask pattern may be formed that exposes the end of the selected line 35A, and the channel pillar 32P exposed by the mask pattern may be removed. The channel pillar 32P may be removed using a dip-out process. The dip-out process may be a wet etching process with a high etching selectivity ratio for the channel pillar 32P. During the dip-out process, the gate insulating film 34 may be removed along with the channel pillar 32P.

[0048] Referring to Figures 9A and 9B, an insulating pillar 36 can be formed within the first opening OP1. The insulating pillar 36 may penetrate the selection line 35A and be located above the global line 31A. The selection line 35A may fill the space between the insulating pillars 36 arranged in the first direction I and may extend in the first direction I while enclosing the side walls of the insulating pillars 36.

[0049] An insulating film 37 can be formed on the upper part of the insulating pillar 36 and the channel pillar 32P. The insulating film 37 can fill the space between the channel pillars 32P. The insulating pillar 36 and the insulating film 37 can be formed simultaneously and may be a single, integrally connected film.

[0050] Referring to Figures 10A and 10B, an interlayer insulating film 38 may be formed above the selection line 35A. An interlayer insulating film 38 may be formed above the insulating film 37. Subsequently, second openings OP2 are formed that expose the selection line 35A. The second openings OP2 may extend through the interlayer insulating film 38 and the insulating film 37. In the process of forming each second opening OP2, a pair of insulating pillars 36 adjacent in the first direction I may be partially etched, and the sidewalls of the second portion 35AB located between the pair of insulating pillars 36 may be exposed.

[0051] Next, contact plugs 39 can be formed within the second opening OP2. Each contact plug 39 can be electrically connected to a selection line 35A. Each contact plug 39 can be located between insulating pillars 36 and electrically connected to a selection line. A contact plug 39 can be connected to a second portion 35AB of the selection line 35A exposed between a pair of insulating pillars 36 adjacent in the first direction I.

[0052] An insulating pillar 36 may be positioned between the contact plug 39 and the global line 31A, thereby insulating the contact plug 39 and the global line 31A from each other. Multiple contact plugs 39 may be arranged in a zigzag pattern or in an alternating pattern.

[0053] On the other hand, although not shown in the figure, local lines can be formed connected to each channel pillar 32P. The local lines may have a pillar shape and may extend through the interlayer insulating film 38 and insulating film 37. The local lines may be local bit lines.

[0054] According to the manufacturing method described above, selection transistors ST arranged in a first direction I and a second direction II can be formed. Contact plugs 39 can be formed connected to each selection line 35A. A selection signal can be applied to the selection line 35A via the contact plugs 39, and the selection transistors ST can be turned off or turned off in response to the selection signal.

[0055] Figures 11A and 11B show the structure of a semiconductor device according to one embodiment of the present invention. Further explanations that overlap with the above may be omitted.

[0056] Referring to Figure 11A, the semiconductor device may include a cell region CELL in which stacked memory cells are located. The semiconductor device may also include peripheral circuits located around the cell region CELL. Here, the peripheral circuits may include a global bit line decoder GBL decoder, a selection line decoder SL decoder, and a word line decoder WL decoder.

[0057] Cell regions (CELLs) can be arranged in a first direction (I) and a second direction (II). A selection line decoder (SL decoder) may be located between adjacent cell regions (CELLs) in the first direction (I). A global bit line decoder (GBL decoder) may be located between adjacent cell regions (CELLs) in the second direction (II). Word line decoders (WL decoder) and selection line decoders (SL decoder) can be adjacent in the first direction (I), and cell regions (CELLs) may be located between adjacent word line decoders (WL decoder) and selection line decoders (SL decoder).

[0058] The cell region and peripheral circuits may be located at the same level or at different levels. In one embodiment, the peripheral circuits may be located below the cell region. Cell regions and peripheral circuits located at different levels may be electrically connected by an interconnection structure. The interconnection structure may include vias and wiring.

[0059] Referring to Figure 11B, the semiconductor device may include peripheral circuits PC, global bit line GBL, selection line SL, word line WL, local bit line LBL, contact plug CT, selection line contact plug SLCT, word line contact plug WLCT, first interconnection structure IC1, and second interconnection structure IC2. For reference, Figure 11B omits the insulating film and interlayer insulating film for ease of explanation.

[0060] The peripheral circuit PC may be located below the global bit line GBL, the selection line SL, and the word line WL. The peripheral circuit PC may include a global bit line decoder GBL decoder, a selection line decoder SL decoder, and a word line decoder WL decoder. The global bit line decoder GBL decoder may be located below the global bit line GBL and may be connected to the global bit line GBL. The selection line decoder SL decoder may be located below the global bit line GBL and may be connected to the selection line SL.

[0061] A global bit line GBL may be located above the peripheral circuit PC, a selection line SL may be located above the global bit line GBL, and a word line WL may be located above the selection line SL. The word line WL surrounds the local bit line LBL and can be stacked in a third direction III. The global bit line GBL and the selection line SL may extend in directions that intersect each other.

[0062] A contact plug CT may be electrically connected to the selection line SL, and a selection line contact plug SLCT may be electrically connected to the contact plug CT. The selection line contact plug SLCT may be electrically connected to the second interconnection structure IC2.

[0063] The channel pattern CP may pass through the selection line SL. The lower end of the channel pattern CP may be connected to the global bit line GBL, and the upper end of the channel pattern CP may be connected to the local bit line LBL. A selection transistor ST may be located in the region where the channel pattern CP and the selection line SL intersect.

[0064] The first interconnection structure IC1 may be located above the peripheral circuit PC and below the selection line SL. The first interconnection structure IC1 may be electrically connected to the peripheral circuit PC. The first interconnection structure IC1 may include wiring UM0, UM1 and via UMC. The second interconnection structure IC2 may be located at a different level than the first interconnection structure IC1 and above the word line WL. The second interconnection structure IC2 may be electrically connected to the word line contact plug WLCT, the selection line contact plug SLCT, the first interconnection structure IC1, etc. The second interconnection structure IC2 may include wiring M1, M2, M3 and vias M1C, M2C, M3C.

[0065] The global bit line GBL can be connected to the global bit line decoder via the first interconnection structure IC1. The selection line SL can be connected to the contact plug CT and the selection line contact plug SLCT, and the selection line SL can be connected to the selection line decoder via the first interconnection structure IC1 and the second interconnection structure IC2.

[0066] A word line WL may be stacked on top of a selection line SL, and a local bit line LBL may penetrate the word line WL and be connected to the channel pillar of a selection transistor ST. Memory cells MC may be located in the region where the local bit line LBL and the word line WL intersect. Memory cells MC may be stacked along the local bit line LBL, and memory cells MC stacked along the same local bit line LBL may constitute a memory unit MU.

[0067] Each memory cell MC may include a variable resistive film. The variable resistive film may have the property of reversibly transitioning between mutually different resistance states depending on the voltage or current applied to the memory cell MC. In one example, when the variable resistive film is in a low resistance state, data "1" may be stored, and when the variable resistive film is in a high resistance state, data "0" may be stored.

[0068] As an example, the variable resistive film may contain a resistive material. Data can be stored by the creation or disappearance of electrical paths within the variable resistive film. As an example, the variable resistive film may contain a transition metal oxide or a metal oxide such as a perovskite material.

[0069] As an example, the variable resistive film may have an MTJ structure including a magnetized fixed layer, a tunnel barrier layer, and a magnetized free layer. Data can be stored in response to a change in the magnetization direction of the magnetized free layer relative to the magnetization direction of the magnetized fixed layer. As an example, the magnetized fixed layer and the magnetized free layer may contain a magnetic material, and the tunnel barrier layer may contain a metal oxide.

[0070] As an example, the variable resistive film may contain a phase-change material, and may contain a chalcogenide-based material. The variable resistive film may undergo a phase change in accordance with programmed operation. As an example, the variable resistive film may have a low-resistance crystalline state due to a set operation. As an example, the variable resistive film may have a high-resistance amorphous state due to a reset operation. Therefore, data can be stored in the memory cell MC by utilizing the resistance difference caused by the phase of the variable resistive film.

[0071] As an example, the variable resistive film may include a variable resistive material whose resistance changes without a phase change, and may include a chalcogenide-based material. The variable resistive film may maintain its phase after a program operation. As an example, the variable resistive film may have an amorphous state and may maintain the amorphous state without changing to a crystalline state after a program operation. Depending on the program voltage applied to the memory cell MC, the threshold voltage of the memory cell MC may change, and the memory cell MC may be programmed into at least two states. As an example, the memory cell MC may be programmed into a set state or a reset state using program voltages of different polarities. Therefore, data can be stored in the memory cell MC by utilizing the threshold voltage difference of the memory cell MC.

[0072] Word line contact plugs WLCT can be connected to each word line WL. In one embodiment, word line WLs may be stacked in a stepped shape, and word line contact plugs WLCT can be connected to each end of the word line WLs. The word line WL can be connected to a word line decoder WL decoder via word line contact plugs WLCT, a second interconnection structure IC2, and a first interconnection structure IC1.

[0073] For reference, it is also possible for the word line WL to be stacked flat without using a stepped shape, and the word line contact plug WLCT can extend through the word line WL. In this case, the penetrating word line WL and the word line contact plug WLCT can be insulated from each other, and the word line WL and the word line contact plug WLCT can be connected one-to-one.

[0074] According to the structure described above, the integration density of the semiconductor device can be improved by positioning the peripheral circuit PC below the cell region CELL. By positioning the selection transistor ST below the stacked word line WL and connecting the selection transistor ST between the global bit line GBL and the local bit line LBL, the desired local bit line LBL can be selected.

[0075] Figure 12 is a circuit diagram showing a cell array of a semiconductor device according to one embodiment of the present invention. The following explanations may be omitted if they overlap with the content described above.

[0076] Referring to Figure 12, the semiconductor device may include selection lines SL0 to SLm, global bit lines GBL0 to GBLk, local bit lines LBL00 to LBLkm, word lines WL0 to WLn, memory cell MC, selection transistor ST, and memory unit MU, where m, n, and k can be non-negative integers.

[0077] Memory cells MC can be connected between local bit lines LBL00~LBLkm and word lines WL0~WLn, and memory cells MC can be stacked in a third direction III, where the third direction III may be a direction orthogonal to the plane defined by the first direction I and the second direction II. Word lines WL0~WLn can be connected to the gate electrodes of memory cells MC. Memory cells MC connected to the same local bit lines LBL00~LBLkm can constitute a single memory unit MU.

[0078] A selection transistor ST may be connected to each memory unit MU. Selection lines SL1 to SLm may be connected to the gate electrodes of the selection transistors ST, and the selection lines SL1 to SLm may extend in the first direction I. Global bit lines GBL0 to GBLk may extend in the second direction II, and a selection transistor ST may be connected between the local bit lines LBL00 to LBLkm and the global bit lines GBL0 to GBLk.

[0079] With the configuration described above, a desired memory unit MU can be selected using the selection transistor ST. Therefore, set operations or reset operations can be performed on a per-memory unit MU basis.

[0080] Figure 13 is a flowchart illustrating the flow of a method for manufacturing a semiconductor device according to one embodiment of the present invention. The following explanations may be omitted if they overlap with the content described above.

[0081] First, peripheral circuits can be formed on the substrate (S10). The peripheral circuits may include a selection line decoder (SL decoder), a global bit line decoder (GBL decoder), and a word line decoder (WL decoder). Subsequently, a first interconnection structure electrically connected to the peripheral circuits can be formed (S20). The first interconnection structure IC1 may include wiring, vias, etc.

[0082] Next, a selection transistor ST may be formed (S30). A global bit line GBL may be formed, and the selection transistor ST may be formed on top of the global bit line GBL.

[0083] Next, a memory cell MC may be formed (S40). A word line WL stacked on top of the selection transistor ST and a local bit line LBL extending through the word line WL may be formed. The memory cell MC may be connected between the word line WL and the local bit line LBL. The selection transistor ST may be connected between the local bit line LBL and the global bit line GBL.

[0084] Next, a second interconnection structure IC2 may be formed (S50). The second interconnection structure IC2 may be electrically connected to the selection line SL, the word line WL, the first interconnection structure IC1, etc. The second interconnection structure IC2 may include wiring, vias, etc.

[0085] In this embodiment, the case in which peripheral circuits and cell arrays are sequentially formed on a substrate has been described, but the present invention is not limited thereto. It is also possible to manufacture a chip including peripheral circuits and a chip including cell arrays separately, and then bond the peripheral circuit chip and the cell chip.

[0086] Figures 14A to 14F are diagrams illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and are cross-sectional views of a cell region. The following explanations may be omitted if they overlap with the above.

[0087] Referring to Figure 14A, a laminate ST1 is formed. The laminate ST1 may be formed on top of the selection transistor ST. The global bit line GBL, selection line SL, selection transistor ST, and interlayer insulating film IL may have the structure according to the embodiment described with reference to Figures 1A to 1C, and may be formed by the manufacturing method according to the embodiment described with reference to Figures 3A to 10A, Figures 3B to 10B, and Figures 3C to 7C.

[0088] The laminate ST1 may include alternatingly stacked first material films 41 and second material films 42. The first material film 41 may be for forming word lines, and the second material film 42 may be for insulating the stacked word lines from each other. The first material film 41 may contain a material with a higher etching selectivity ratio than the second material film 42. In examples, the first material film 41 may contain a sacrificial material such as a nitride, and the second material film 42 may contain an insulating material such as an oxide. The first material film 41 may contain a conductive material such as polysilicon, tungsten, or molybdenum, and the second material film 42 may contain an insulating material such as an oxide.

[0089] Next, an opening OP is formed that extends through the laminate ST1. The opening OP can penetrate the laminate ST1 and expose the interlayer insulating film IL. The opening OP can be located corresponding to a selected transistor ST, and can be located corresponding to the channel pillar of the selected transistor ST. In an example, the openings OP may be arranged in a first direction I and a second direction II, and the spacing in the first direction I may be smaller than the spacing in the second direction II.

[0090] Referring to Figure 14B, the first material film 41 exposed through the opening OP is etched to form a recess region. The recess region allows the opening OP to extend horizontally to a level corresponding to the first material film 41. Subsequently, a first electrode film 43 can be formed along the surface of the laminate ST1 exposed by the opening OP. The first electrode film 43 can be formed with a thickness that fills the recess region.

[0091] Referring to Figure 14C, the first electrode film 43 is etched to form the first electrode 43A. The first electrode 43A may be located within the recess region. Subsequently, a variable resistive material 44 is formed. The variable resistive material 44 may be formed along the surface of the laminate ST1 and the first electrode 43A exposed through the opening OP. The variable resistive material 44 may be formed with a thickness that fills the recess region.

[0092] Referring to Figure 14D, the variable resistive material 44 is etched to form a variable resistive film 44A. The variable resistive films 44A may be located within recessed regions. Subsequently, a second electrode film 45 is formed. The second electrode film 45 may be formed along the surface of the laminate ST1 and the variable resistive film 44A exposed through the opening OP.

[0093] Referring to Figure 14E, the portion of the second electrode film 45 formed on the surface of the interlayer insulating film IL can be etched. Subsequently, the interlayer insulating film IL can be etched to expand the opening OP downwards. This allows the channel pillar of the selected transistor ST to be exposed. Next, a conductive film 46 is formed on the second electrode film 45. The conductive film 46 can be formed along the surfaces of the second electrode film 45 and the interlayer insulating film IL, and can fill the opening OP. The conductive film 46 may contain a metal such as tungsten.

[0094] Referring to Figure 14F, the conductive film 46 and the second electrode film 45 can be etched. The conductive film 46 and the second electrode film 45 can be planarized until the upper surface of the laminate ST1 is exposed to form the second electrode 45A and the local bit line 46A. The planarization process can be performed using the CMP (Chemical Mechanical Polish) method.

[0095] Each local bit line 46A may have a pillar shape, and the second electrode 45A may surround the side wall of the local bit line 46A. The variable resistive film 44A and the first electrode 43A may surround the second electrode 45A. The variable resistive film 44A and the first electrode 43A may be located between the laminated second material films and may have a ring shape. The local bit lines 46A may extend through the laminate ST1 and may be connected to the channel pillars, respectively.

[0096] According to the manufacturing method described above, memory cells MC can be formed stacked along the local bit line 46A. Each memory cell MC may include a first electrode 43A, a variable resistive film 44A, and a second electrode 45A. Memory cell MCs sharing the local bit line 46A may constitute a single memory unit MU.

[0097] Figures 15A to 17A and 15B to 17B are diagrams illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and show the selection line decoder region, the cell region, and the word line decoder region. Figures 15A to 17A show the layout, and Figures 15B to 17B are cross-sectional views taken along line F-F' of Figures 15A to 17A. Further explanations that overlap with the above may be omitted.

[0098] Referring to Figures 15A and 15B, the global bit line GBL, selection line SL, selection transistor ST, interlayer insulating film IL, and contact plug CT are formed. The global bit line GBL, selection line SL, selection transistor ST, interlayer insulating film IL, and contact plug CT may have the structure according to the embodiment described with reference to Figures 1A to 1C, and may be formed by the manufacturing method according to the embodiment described with reference to Figures 3A to 10A, Figures 3B to 10B, and Figures 3C to 7C.

[0099] Next, the laminate ST1 and the memory unit MU are formed. The laminate ST1 may be formed in a selection line decoder region SD, a cell region CELL, and a word line decoder region WLD. The memory unit MU may be positioned corresponding to the selection transistor ST, and the spacing W3 in the first direction I may be smaller than the spacing W4 in the second direction II. The laminate ST1 and the memory unit MU may have the structure according to the embodiment described with reference to Figures 11A and 11B, and may be formed by the manufacturing method according to the embodiment described with reference to Figures 14A to 14F.

[0100] Next, the word line decoder region WLD of the laminate ST1 can be patterned in a step shape. The step structure allows each of the first material films 51 to be exposed. Subsequently, an interlayer insulating film ILD can be formed on the laminate ST1.

[0101] Referring to Figures 16A and 16B, a slit SLI is formed extending through the laminate ST1. The first material film 51 can be exposed through the slit SLI. In one example, a slit SLI may be formed in the selective line decoder region SD of the laminate ST1. For reference, although not shown, a slit SLI may also be formed in the cell region CELL and / or the word line decoder region WLD.

[0102] Next, the first material film 51 can be replaced with a third material film 53 through the slit SLI. In one example, the first material film 51 can be removed to form a recess region, and the third material film 53 can be formed within the recess region. The third material film 53 is for forming a word line and may contain metals such as tungsten or molybdenum. This makes it possible to form a word line laminate WLST containing alternately stacked second material films 52 and third material films 53. Subsequently, a gap fill insulating film GFI can be formed within the slit SLI.

[0103] For reference, if the first material film 51 contains a conductive material, the step of replacing the first material film 51 with the third material film 53 may be omitted. In this case, the first material film 51 may be used as a wordline, and the laminate ST1 may be used as a wordline laminate WLST.

[0104] Referring to Figures 17A and 17B, a word line contact plug WLCT is formed. The word line contact plug WLCT may be located in the word line decoder region WLD. The word line contact plug WLCT may penetrate the interlayer insulating film ILD and be connected to the third material film 53, respectively.

[0105] A selective line contact plug SLCT is formed. The selective line contact plug SLCT may be located in the selective line decoder region SD. The selective line contact plug SLCT may penetrate the gap fill insulating film GFI and be connected to the contact plug CT, respectively.

[0106] According to the manufacturing method described above, a word line contact plug WLCT connected to a word line and a selection line contact plug SLCT connected to a selection line can be formed.

[0107] Figure 18 is a cross-sectional view showing the structure of a semiconductor device according to one embodiment of the present invention. The following explanations may be omitted if they overlap with the content described above.

[0108] Referring to Figure 18, the semiconductor device may include a first semiconductor structure S1, a second semiconductor structure S2, and a bonding structure BS located between the first semiconductor structure S1 and the second semiconductor structure S2. The first semiconductor structure S1 and the second semiconductor structure S2 may be formed by separate processes and may be electrically connected by the bonding structure BS. In an example, the first semiconductor structure S1 may include a peripheral circuit PC, and the second semiconductor structure S2 may include a memory cell array CA.

[0109] The first semiconductor structure S1 may include a substrate 100, a transistor TR, a first interconnection structure IC1, and a first interlayer insulating film IL1. An active region may be defined by an element isolation film 104 within the substrate 100, and the transistor TR may be located in the active region. The transistor TR may include a gate insulating film 101, a gate electrode 102, and a junction 103. The transistor TR may belong to a peripheral circuit PC.

[0110] The first interconnection structure IC1 may be located within the first interlayer insulating film IL1 and may include vias 105, wiring 106, etc. The first interconnection structure IC1 may be electrically connected to a peripheral circuit PC and may be electrically connected to a transistor TR.

[0111] The second semiconductor structure S2 may include a global bit line GBL, a selection line SL, a selection transistor ST, a word line WL, a memory unit MU, a contact plug CT, a selection line contact plug SLCT, a word line contact plug WLCT, a second interconnection structure IC2, and a second interlayer insulating film IL2. The word line WL may be stacked in a stepped shape or in an inverted stepped shape. The selection line SL may be located above or below the word line WL. The selection transistor ST may be located above or below the memory unit MU.

[0112] The second interconnection structure IC2 may be located within the second interlayer insulating film IL2 and may include vias 207, wiring 208, etc. The second interconnection structure IC2 may be electrically connected to the global bit line GBL, selection line SL, word line WL, etc.

[0113] The bonding structure BS may include a first bonding film BL1, a second bonding film BL2, a first bonding pad BP1, and a second bonding pad BP2. The first bonding film BL1 and the second bonding film BL2 may be in contact, and the first bonding pad BP1 and the second bonding pad BP2 may be in contact. The first bonding film BL1 and the second bonding film BL2 may include SiCN, TEOS (Tetra Ethyl Ortho Silicate), etc. The first bonding pad BP1 may be electrically connected to a first interconnection structure IC1, and the second bonding pad BP2 may be electrically connected to a second interconnection structure IC2. The memory cell array CA and the peripheral circuit PC may be electrically connected via the first bonding pad BP1 and the second bonding pad BP2.

[0114] The structure and manufacturing method according to the above-described embodiment can be applied to semiconductor devices of various structures. Figures 19 and 20 show a schematic configuration of a semiconductor device to which the above-described embodiment can be applied.

[0115] Figure 19 is a configuration diagram of a semiconductor device according to one embodiment of the present invention.

[0116] Referring to Figure 19, the semiconductor device may include a substrate SUB, peripheral circuits PC, and a memory cell array CA. Here, the peripheral circuits PC and the memory cell array CA may be formed on the same substrate.

[0117] The substrate SUB may include a semiconductor material. In examples, the semiconductor material may include at least one of a group IV semiconductor, a group III-V compound semiconductor, and a group II-VI compound semiconductor. Here, the group IV semiconductor may include single-crystal silicon Si, polycrystalline silicon, germanium Ge, or silicon germanium SiGe. The group III-V compound semiconductor may include GaAs, GaN, GaP, GaAsP, GaInAsP, AlAs, AlGa, InP, InSb, or InGaAs. The group II-VI compound semiconductor may include ZnS, ZnO, or CdS.

[0118] The substrate SUB may include a dielectric film. The substrate SUB may be an SOI (silicon-on-insulator) substrate, a GeOI (germanium-on-insulator) substrate, or a glass substrate. The substrate SUB may include an organic material. For example, the substrate SUB may include graphene.

[0119] The substrate SUB may be a bulk wafer or an epitaxial film grown by selective epitaxial growth (SEG). The substrate SUB may be a film formed by MILC (Metal Induced Lateral Crystallization) and may partially contain metal. The substrate SUB may be single-crystal, polycrystalline, or amorphous. The substrate SUB may contain impurities of group II, III, IV, V, or VI. For example, the substrate SUB may contain n-well regions doped with N-type impurities and / or p-well regions doped with P-type impurities.

[0120] The peripheral circuit PC may be located between the substrate SUB and the memory cell array CA. The peripheral circuit PC may include a low decoder, column decoder, page buffer, logic circuit, control circuit, sense amplifier, input / output circuit, etc. In an embodiment, the peripheral circuit PC may include NMOS transistors, PMOS transistors, resistors, capacitors, etc. The peripheral circuit PC may further include an interconnection structure. The interconnection structure may be used as a path for transmitting operating voltage and may include contact plugs, wiring, etc.

[0121] A memory cell array CA may include memory cells. For example, a memory cell array CA may include memory strings connected between source lines and bit lines, each memory string may include stacked memory cells. For example, a memory cell array CA may include memory cells connected between word lines and bit lines. A memory cell array CA may further include interconnection structures.

[0122] Figure 20 is a configuration diagram of a semiconductor device according to one embodiment of the present invention.

[0123] Referring to Figure 20, the semiconductor device may include a substrate SUB, a peripheral circuit PC, a bonding structure BS, and a memory cell array CA. Here, the peripheral circuit PC and the memory cell array CA may be formed on separate substrates and then bonded together. The semiconductor device may further include a support base SP_B.

[0124] The substrate SUB may have been used as a support in the process of forming the peripheral circuit PC. The support base SP_B may have been used as a support in the process of forming the memory cell array CA. In one example, after manufacturing a first wafer containing the memory cell array CA and a second wafer containing the peripheral circuit PC, the first wafer and the second wafer may be electrically bonded by a bonding structure BS. After bonding, at least a portion of the support base SP_B of the first wafer may be removed. The support base SP_B may be completely removed or partially remain on the memory cell array CA.

[0125] The support base SP_B may be a semiconductor substrate, an insulating substrate, an SOI (silicon-on-insulator) substrate, a GeOI (germanium-on-insulator) substrate, etc. The support base SP_B may be a bulk wafer, an epitaxial film grown by selective epitaxial growth (SEG) method, or a film formed by MILC (Metal Induced Lateral Crystallization) method. The support base SP_B may be single-crystal, polycrystalline, or amorphous. The support base SP_B may contain impurities of group II, group III, group IV, group V, or group VI.

[0126] The bonding structure BS may be used to connect the memory cell array CA and the peripheral circuit PC. Examples include wafer-on-wafer bonding, chip-on-wafer bonding, and chip-on-chip bonding to bond the memory cell array CA and the peripheral circuit PC. The bonding structure BS may include a bonding pad, a bonding film, and a bonding interface. The bonding pad may include metals and / or alloys such as copper and aluminum. The bonding interface may include non-metallic-non-metallic interfaces and metal-metallic interfaces. The bonding structure BS can electrically connect the memory cell array CA and the peripheral circuit PC.

[0127] For reference, interconnection structures included in a memory cell array CA and / or peripheral circuit PC can also be directly connected without bonding pads. In one example, a bonding film included in the memory cell array CA and a bonding film included in the peripheral circuit PC can be bonded to form a bonding interface, and the interconnection structure included in the memory cell array CA and the interconnection structure included in the peripheral circuit PC can be directly connected. This allows contact plugs, wiring, etc., formed on different wafers to be electrically connected without separate bonding pads.

[0128] Other configurations may be the same as or similar to those described with reference to Figure 19 above.

[0129] On the other hand, the semiconductor device may have a structure that combines or partially modifies the embodiments described with reference to Figures 19 and 20. In the embodiments described with reference to Figures 19 and 20, the positions of the memory cell array CA and the peripheral circuit PC may be changed. In the embodiments described with reference to Figures 19 and 20, at least one memory cell array CA and / or at least one peripheral circuit PC may be additionally bonded. In one embodiment, a portion of the peripheral circuit PC may be located within the memory cell array CA.

[0130] The above describes embodiments of the technical concept of the present invention with reference to the attached drawings. However, this is merely to explain embodiments of the concept of the present invention, and the present invention is not limited to the above embodiments. Within the scope of the technical concept of the present invention, various shapes can be substituted, modified, changed, and combined by persons with ordinary skill in the art to which the present invention belongs, and these can also be said to fall within the scope of the present invention. [Explanation of Symbols]

[0131] 11: Global Line 12: Channel pillar 12A: First semiconductor film 12B: Second semiconductor film 12C: Third semiconductor film 13: Selection Line 14: Gap fill insulating film 15: Interlayer insulating film 16: Gate Insulator 17: Local Line 18: Contact plug 19: Insulating pillar 31: First conductive film 31A: Global Line 32: Semiconductor film 32A: First semiconductor 32B: Second semiconductor film 32C: Third semiconductor film 32L: Semiconductor Line 32P: Channel pillar 33A: First gap fill insulating film 33B: Second gap fill insulating film 34: Gate insulating film 35: Second conductive film 35A: Selection Line 36: Insulating pillar 37: Insulating Film 38: Interlayer insulating film 39: Contact plug 41:First substance film 42:Second substance film 43:First electrode film 43A: 1st electrode 44: Variable Resistive Material 44A: Variable Resistor 45:Second electrode film 45A: 2nd electrode 46: Conductive film 46A: Local bit line 51:First substance film 52:Second substance film 53:Third material film

Claims

1. A channel pillar arranged in a first direction and a second direction intersecting the first direction, having a first spacing in the first direction and a second spacing in the second direction, wherein the first spacing is smaller than the second spacing, A selection line that surrounds the channel pillars arranged in the first direction and extends in the first direction, The word line stacked on top of the aforementioned selection line, A local bit line that penetrates the word line and is connected to the channel pillar and Semiconductor equipment including

2. Further including an insulating pillar that penetrates the aforementioned selection line, The semiconductor device according to claim 1.

3. Further including a contact plug electrically connected to the selected line between the insulating pillars, The semiconductor device according to claim 2.

4. The selection line includes a first portion extending in the first direction and a second portion located between the insulating pillars and connecting the first portion, and the contact plug is connected to the second portion. The semiconductor device according to claim 3.

5. The channel pillars arranged in the first direction constitute one row, and the selection line surrounds at least two rows. The semiconductor device according to claim 1.

6. Channel pillars enclosed by the same selection line have a third spacing in the second direction, and the third spacing is smaller than the second spacing. The semiconductor device according to claim 5.

7. Channel pillars enclosed by the same selection line are arranged in a zigzag pattern. The semiconductor device according to claim 5.

8. Further including a global bit line connected to channel pillars arranged in the second direction and extending in the second direction, The semiconductor device according to claim 1.

9. The system further includes selection transistors located in the region where the selection line and the global bit line intersect, and connected between the global bit line and the local bit line, respectively. The semiconductor device according to claim 8.

10. Further including a global bitline decoder located below the global bitline and connected to the global bitline, The semiconductor device according to claim 8.

11. Further including a selection line decoder located below the selection line and connected to the selection line, The semiconductor device according to claim 1.

12. Further including a word line decoder located below the selection line and connected to the word line, The semiconductor device according to claim 1.

13. Each of the channel pillars includes a first junction, a second junction, and a channel region located between the first and second junctions. The semiconductor device according to claim 1.

14. The aforementioned selection line encloses the channel region. The semiconductor device according to claim 13.

15. The first junction and the second junction contain P-type impurities, and the channel region is an intrinsic semiconductor or contains N-type impurities. The semiconductor device according to claim 13.

16. The first junction and the second junction contain N-type impurities, and the channel region is an intrinsic semiconductor or contains P-type impurities. The semiconductor device according to claim 13.

17. Peripheral circuits located below the aforementioned selection line, A first interconnection structure located below the selection line and electrically connected to the peripheral circuit, The semiconductor device according to claim 1, further comprising:

18. The system further includes a second interconnection structure located above the word line and electrically connected to the word line. The semiconductor device according to claim 1.

19. Local lines arranged in a first direction and a second direction intersecting the first direction, and extending in a third direction perpendicular to the first and second directions, A global line extending in the second direction, A selection transistor comprising a channel pillar connected between the local line and the global line, having a first spacing in the first direction and a second spacing in the second direction, wherein the first spacing is smaller than the second spacing, and Semiconductor equipment including

20. The selection line further includes a selection line connected to the gate electrode of the selection transistor and extending in the first direction, The semiconductor device according to claim 19.

21. The channel pillars arranged in the first direction constitute a row, and the selection line surrounds at least one row. The semiconductor device according to claim 20.

22. Channel pillars enclosed by the same selection line have a third spacing in the second direction, and the third spacing is smaller than the second spacing. The semiconductor device according to claim 21.

23. The aforementioned local line is a local bit line, and the aforementioned global line is a global bit line. The semiconductor device according to claim 19.

24. Surrounding the aforementioned local line, the word lines stacked in the third direction, A memory cell connected between the local line and the word line. The semiconductor device according to claim 19, further comprising:

25. The following further includes a global line decoder located below the global line and connected to the global line: The semiconductor device according to claim 19.

26. A selection line connected to the gate electrode of the selection transistor and extending in the first direction, A selection line decoder located below the global line and connected to the selection line, The semiconductor device according to claim 19, further comprising:

27. The steps include forming channel pillars arranged in a first direction and a second direction intersecting the first direction, The steps include forming a selection line that surrounds the channel pillar and extends in the first direction, The steps include forming an insulating pillar that penetrates the selected line, The steps include forming a contact plug electrically connected to the selected line between the insulating pillars, A method for manufacturing a semiconductor device containing [a specific component].

28. The channel pillar has a first spacing in a first direction and a second spacing in a second direction, wherein the first spacing is smaller than the second spacing. The method for manufacturing a semiconductor device according to claim 27.

29. The channel pillars arranged in the first direction constitute a row, and the selection line surrounds at least one row. The method for manufacturing a semiconductor device according to claim 28.

30. Channel pillars enclosed by the same selection line have a third spacing in the second direction, and the third spacing is smaller than the second spacing. The method for manufacturing a semiconductor device according to claim 29.

31. The step further includes forming a global bit line extending in the second direction, The method for manufacturing a semiconductor device according to claim 27.

32. The step of forming the channel pillar is: The steps include forming a first conductive film, The steps include forming a semiconductor film on top of the first conductive film, The steps include etching the semiconductor film to form a semiconductor line extending in the second direction, The steps include etching the first conductive film to form a global bit line extending in the second direction, The steps of etching the semiconductor line to form the channel pillar and A method for manufacturing a semiconductor device according to claim 27, including the method described in claim 27.

33. The step of forming the semiconductor film is, The steps include forming an N-type first semiconductor film, The steps include forming a P-type second semiconductor film on the first semiconductor film, The steps include forming an N-type third semiconductor film on the second semiconductor film and A method for manufacturing a semiconductor device according to claim 32, including the method described above.

34. The step of forming the selection line is, The steps include forming a gate insulating film on the channel pillar, The steps include forming a second conductive film on the gate insulating film such that it fills the space between adjacent channel pillars in the first direction and opens the space between adjacent channel pillars in the second direction, The steps include etching the second conductive film to form a selective line extending in the first direction, and A method for manufacturing a semiconductor device according to claim 27, including the method described in claim 27.

35. The step of forming the insulating pillar is: The steps include removing a portion of the channel pillar to form a first opening, The steps of forming the insulating pillar within the first opening and A method for manufacturing a semiconductor device according to claim 27, including the method described in claim 27.

36. The step of forming the contact plug is, The steps include forming an interlayer insulating film on the upper part of the selected line, The steps include forming a second opening that extends through the interlayer insulating film and exposes the selected line, The steps of forming the contact plug in the second opening and A method for manufacturing a semiconductor device according to claim 27, including the method described in claim 27.

37. The selection line includes a first portion extending in the first direction and a second portion located between the channel pillars and extending in the second direction. The second opening exposes the second portion. The method for manufacturing a semiconductor device according to claim 36.

38. The steps of forming a global bit line, The steps include forming channel pillars above the global bit line, arranged in a first direction and a second direction intersecting the first direction, such that the spacing in the first direction is smaller than the spacing in the second direction, The steps include forming a selection line that surrounds the channel pillar and extends in the first direction, The steps include forming local bit lines on the upper part of the selection line, which are connected to the channel pillars and extend in a third direction perpendicular to the first and second directions, The steps include: forming a word line that surrounds the local bit line and is stacked in the third direction; A method for manufacturing a semiconductor device containing [a specific component].

39. The step further includes forming selection line contact plugs connected to the respective selection lines, The method for manufacturing a semiconductor device according to claim 38.

40. The steps include removing a portion of the channel pillar to form a first opening, The steps of forming an insulating pillar in the first opening and A method for manufacturing a semiconductor device according to claim 39, further comprising:

41. The selection line contact plug is connected to the selection line between the insulating pillars. A method for manufacturing a semiconductor device according to claim 40.

42. The step further includes forming word line contact plugs connected to the word lines, respectively. The method for manufacturing a semiconductor device according to claim 38.

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