Semiconductor equipment

Abstract

One of the objectives is to provide a semiconductor device with a novel structure. [Solution] A first wire, a second wire, a third wire, a fourth wire, and a first gate A first transistor having electrodes, a first source electrode, and a first drain electrode, A second transient having two gate electrodes, a second source electrode, and a second drain electrode. A transistor has a first transistor provided on a substrate containing a semiconductor material, and a second transistor A semiconductor device is composed of an oxide semiconductor layer.

Description

Technical Field

[0001] The disclosed invention relates to a semiconductor device using semiconductor elements and a method for manufacturing the same.

Background Art

[0002] Memory devices using semiconductor elements are roughly classified into volatile memory devices in which stored contents are lost when power supply is cut off and non-volatile memory devices in which stored contents are retained even when power supply is cut off.

[0003] A typical example of a volatile memory device is DRAM (Dynamic Random Access Memory). DRAM stores information by selecting a transistor constituting a memory element and accumulating electric charges in a capacitor.

[0004] From the above principle, in DRAM, when information is read, the electric charges in the capacitor are lost. Therefore, after data is read, a rewrite operation is required again to store information again. Also, there is a leakage current in the transistor constituting the memory element, and electric charges flow out or flow in even when not selected, so the data retention period is short. For this reason, a rewrite operation (refresh operation) is required at a predetermined cycle, and it is difficult to sufficiently reduce power consumption. Also, since stored contents are lost when power supply is cut off, another memory device using a magnetic material or an optical material is required for long-term storage.

[0005] Another example of a volatile memory device is SRAM (Static Random Access Memory). SRAM stores stored contents using a circuit such as a flip-flop. ​​​​​​​​​​​​ Because it retains data, a refresh operation is unnecessary, which is an advantage over DRAM in this respect. However, because it uses circuits such as flip-flops, the cost per unit of memory capacity is high. There is a problem that it will become less effective. Also, there is the issue that if the power supply is cut off, the memory contents will be lost. Therefore, it is no different from DRAM.

[0006] A typical example of a non-volatile memory device is flash memory. Flash memory is a type of non-volatile memory device. The transistor has a floating gate between its gate electrode and channel formation region, Because memory is stored by holding an electric charge in a floating gate, the data retention period is extremely short. It has the advantage of being extremely long-lasting (semi-permanent) and not requiring the refresh operations necessary for volatile memory devices. It has points (see, for example, Patent Document 1).

[0007] However, the gate insulating layer that makes up the memory element is affected by the tunnel current generated during writing. Due to degradation, a problem arises where the memory element ceases to function after a predetermined number of write cycles. To mitigate the effects of this problem, for example, the number of write cycles for each memory element can be made uniform. While this method is employed, achieving it requires complex peripheral circuits. However, even if such methods are adopted, the fundamental problem of lifespan will not be resolved. Therefore, flash memory is unsuitable for applications where information needs to be rewritten frequently.

[0008] Also, in order to retain charge on the floating gate, or to remove that charge This requires a high voltage. Furthermore, it takes a relatively long time to retain or remove the charge. There is also the problem that it takes time, and it is not easy to speed up writing and erasing. [Prior art documents] [Patent Documents]

[0009] [Patent Document 1] Japanese Patent Application Publication No. 57-105889 [Overview of the Initiative] [Problems that the invention aims to solve]

[0010] In view of the above-mentioned problems, in one aspect of the disclosed invention, the stored contents are stored even when power is not supplied. To provide a new semiconductor device structure that allows for data retention and has no limit on the number of write cycles. One of the objectives is to provide a semiconductor device with a configuration that facilitates multi-level control. It shall be one of them. [Means for solving the problem]

[0011] One aspect of the present invention relates to a transistor formed using an oxide semiconductor and other materials This is a semiconductor device relating to a stacked structure with transistors formed using the following: A configuration can be adopted.

[0012] One aspect of the present invention comprises a source line, a bit line, a first signal line, a plurality of second signal lines, and a plurality Between the word line, source line, and bit line, there are multiple memory cells connected in parallel, An address signal is input, and among multiple memory cells, the memory cell specified by the address signal is selected. The second signal drives multiple second signal lines and multiple word lines to select a recell. The drive circuits for the line and word line, and the selection of one of several write potentials to the first signal line. The first signal line is output, and the potential of the bit line and multiple reference potentials are input to it. A readout circuit that reads data by comparing the potential of a wire with multiple reference potentials, and multiple Generates write potential and multiple reference potentials for the drive circuit and read circuit of the first signal line. It has a potential generation circuit that supplies power to a potential generation circuit and a boost circuit that supplies power to the potential generation circuit, and multiple One of the memory cells consists of a first gate electrode, a first source electrode, and a first drain electrode. A first transistor having a second gate electrode, a second source electrode, and a second do A second transistor having a rain electrode, a third gate electrode, a third source electrode, and The first transistor has a third transistor having a third drain electrode, The second transistor is provided on a substrate containing semiconductor material and is composed of an oxide semiconductor layer. The first gate electrode and either the second source electrode or the second drain electrode are electrically connected. The source wire and the first source electrode are electrically connected, and the first drain The electrode and the third source electrode are electrically connected, and the bit line and the third drain electrode are connected. It is electrically connected to the first signal line and the second source electrode or the second drain electrode. One of the two is electrically connected, and one of the multiple second signal lines and the second gate electrode are electrically connected. A semiconductor device that is connected and electrically connected to one of several word lines and a third gate electrode. That is the case.

[0013] Furthermore, in the above configuration, the first gate electrode and the second source electrode or second drain This is a semiconductor device having a capacitive element electrically connected to one of its electrodes.

[0014] Furthermore, one aspect of the present invention includes a source line, a bit line, a first signal line, and a plurality of second signal lines. Multiple word lines, source lines, and bit lines are connected in parallel to multiple memory cells. When an address signal is input, one of the multiple memory cells is designated by the address signal. Multiple second signal lines and multiple word lines are driven to select a memory cell. The drive circuit for the two signal lines and the word line, and the first signal selects one of several write potentials. The drive circuit for the first signal line, which outputs to the line number, and the potential of the bit line and multiple reference potentials are input. , has a reference memory cell, and the conductance of the specified memory cell and the reference memory cell A readout circuit that reads data by comparing it with conductance, and multiple write potentials Multiple reference potentials are generated and supplied to the drive circuit and readout circuit of the first signal line. It has a generation circuit and a boost circuit that supplies potential to the potential generation circuit, and one of a plurality of memory cells This comprises a first gate electrode, a first source electrode, and a first drain electrode. It comprises a lampistor, a second gate electrode, a second source electrode, and a second drain electrode. A second transistor, a third gate electrode, a third source electrode, and a third drain A third transistor having electrodes, and the first transistor comprising a semiconductor material. The second transistor is provided on the substrate and is composed of an oxide semiconductor layer, and the first gate The electrode and either the second source electrode or the second drain electrode are electrically connected, The wire and the first source electrode are electrically connected, and the first drain electrode and the third source The drain electrode is electrically connected to the bit wire and the third drain electrode. The first signal line and the other of the second source electrode or the second drain electrode are electrically connected. The second gate electrode is electrically connected to one of the multiple second signal lines, This is a semiconductor device in which one of the word lines and the third gate electrode are electrically connected.

[0015] Furthermore, one aspect of the present invention includes a source line, a bit line, a first signal line, and a plurality of second signal lines. Multiple word lines, source lines, and bit lines are connected in parallel to multiple memory cells. When the address signal and multiple reference potentials are input, among the multiple memory cells, the address signal Multiple second signal lines and multiple worker lines are used to select the memory cell specified by the number. It drives the do line and outputs one of several reference potentials to the selected word line. , a drive circuit for the second signal line and word line, and a selector for one of several write potentials. A drive circuit for the first signal line, which outputs to the first signal line, and a specified note connected to the bit line. A readout circuit that reads data by reading the conductance of the recell, and multiple Generates write potential and multiple reference potentials for the drive circuit and read circuit of the first signal line. It has a potential generation circuit that supplies power to a potential generation circuit and a boost circuit that supplies power to the potential generation circuit, and multiple One of the memory cells consists of a first gate electrode, a first source electrode, and a first drain electrode. A first transistor having a second gate electrode, a second source electrode, and a second do The first transistor has a second transistor having a rain electrode and a capacitive element, and the first transistor is The second transistor is provided on a substrate containing semiconductor material, and the second transistor is configured to include an oxide semiconductor layer. The first gate electrode and either the second source electrode or the second drain electrode, and a capacitance One electrode of the element is electrically connected, and the source wire and the first source electrode are electrically connected. The bit line and the first drain electrode are electrically connected, and the first signal line and the The other of the two source electrodes or the second drain electrode is electrically connected to multiple second signals One of the word lines and the second gate electrode are electrically connected, and one of the word lines and a capacitive element This is a semiconductor device that is electrically connected to the other electrode of this child.

[0016] In the above, the first transistor is a channel forming device provided on a substrate containing a semiconductor material. A region, an impurity region provided so as to sandwich the channel formation region, and on the channel formation region A first gate insulating layer, a first gate electrode on the first gate insulating layer, an impurity region and an electrical It has a first source electrode and a first drain electrode that are connected to each other.

[0017] Furthermore, in the above, the second transistor is a second gate electrode on a substrate containing semiconductor material. The electrode, the second gate insulating layer on the second gate electrode, and the oxide semiconductor on the second gate insulating layer. A body layer and a second source electrode and a second drain electrode electrically connected to the oxide semiconductor layer. It has, and

[0018] Furthermore, in the above, the third transistor is a channel provided on a substrate containing semiconductor material. An impurity region is provided so as to sandwich the channel formation region and the channel formation region A third gate insulating layer on the region, a third gate electrode on the third gate insulating layer, and an impurity region. It has a third source electrode and a third drain electrode that are electrically connected to it.

[0019] Furthermore, in the above, a single-crystal semiconductor substrate is used as the substrate containing the semiconductor material. It is preferable. In particular, silicon is preferred as the semiconductor material. Also, the semiconductor material is SOI substrates may be used as the substrate.

[0020] Furthermore, in the above, the oxide semiconductor layer is an In-Ga-Zn-O based oxide semiconductor material. It is preferable to include it. In particular, the oxide semiconductor layer contains crystals of In2Ga2ZnO7. The following is preferable. Furthermore, the hydrogen concentration of the oxide semiconductor layer is 5 × 10 19 atoms / cm 3 The following is preferable. Also, the off-current of the second transistor is 1 × 10⁻⁶. -13 A The following is preferable:

[0021] Furthermore, in the above, the second transistor is provided in a region that overlaps with the first transistor. It can be configured in this way.

[0022] In this specification, the terms "above" and "below" refer to the relative position of the constituent elements, meaning "directly above". Or it does not limit to being "directly below". For example, "the first on the gate insulating layer If the expression is "gate electrode," then there are other components between the gate insulating layer and the first gate electrode. It does not exclude anything that is included. Also, the terms "upper" and "lower" are used for the sake of explanation. This is merely a generalization, and unless otherwise specified, it also includes variations where the order is reversed.

[0023] Furthermore, in this specification, the terms "electrode" and "wiring" refer to these components functionally. It is not limited to that. For example, "electrode" can be used as part of "wiring". And the reverse is also true. Furthermore, the terms "electrode" and "wiring" can refer to multiple "electrodes." This also includes cases where "or wiring" is formed as a single unit.

[0024] Furthermore, the "source" and "drain" functions are used when employing transistors with different polarities. However, this can change when the direction of current changes during circuit operation. In this specification, the terms "source" and "drain" are interchangeable. It is assumed that this is possible.

[0025] In this specification, etc., "electrically connected" means "having some kind of electrical effect." This includes cases where the connection is made via ". Here, "something that has some electrical effect" The term "connection" is not particularly limited as long as it enables the exchange of electrical signals between connected objects.

[0026] For example, "something that has some kind of electrical effect" includes not only electrodes and wiring, but also... Switching elements such as inverters, resistive elements, inductors, capacitors, and various other components. This includes elements that possess certain capabilities.

[0027] Furthermore, generally speaking, an "SOI substrate" is a substrate in which a silicon semiconductor layer is provided on an insulating surface. However, in this specification, etc., a semiconductor layer made of a material other than silicon is provided on the insulating surface. It is used as a concept that also includes the substrate with the specified configuration. In other words, the semiconductor that the "SOI substrate" possesses The layer is not limited to a silicon semiconductor layer. Also, the substrate in "SOI substrate" is silicon This applies not only to semiconductor substrates such as wafers, but also to glass substrates, quartz substrates, sapphire substrates, and metal substrates. This also includes non-semiconductor substrates such as conductive substrates and insulating substrates. Those having the above characteristics are also broadly included in the term "SOI substrate". Furthermore, in this specification, etc., "semiconductor The term "substrate" refers not only to a substrate made solely of semiconductor materials, but to all substrates containing semiconductor materials. This shall indicate that. In other words, in this specification, "SOI substrate" is also broadly referred to as "semiconductor substrate". It is included in.

[0028] Furthermore, in this specification, etc., semiconductor materials other than oxide semiconductors refer to semiconductor materials other than oxide semiconductors. Any semiconductor material can be used as a conductive material. For example, silicon, germanium Examples include silicon germanium, silicon carbide, gallium arsenide, etc. In addition, there are organic semiconductors. Materials can also be used. Note that there is no particular mention of materials that make up semiconductor devices. If not, use either an oxide semiconductor material or a semiconductor material other than an oxide semiconductor. That's good too. [Effects of the Invention]

[0029] In one aspect of the present invention, the lower part has a channel formation region in which a material other than an oxide semiconductor is used. It has a transistor, and the upper part has a transistor using an oxide semiconductor in the channel formation region. A semiconductor device is provided.

[0030] Transistors using oxide semiconductors have extremely low off-currents, so we decided to use them. It is possible to retain memory content for an extremely long period of time. In other words, refresh function This eliminates the need for manual operation, or makes it possible to significantly reduce the frequency of refresh operations. Therefore, power consumption can be significantly reduced. Also, even if there is no power supply... It is possible to retain memory content over a long period of time.

[0031] Furthermore, it does not require high voltage for writing information, and there are no problems with element degradation. Because it does not require the injection and extraction of electrons into and out of the floating gate, as in non-volatile memory, No deterioration occurs at all, such as deterioration of the insulating layer. In other words, according to this embodiment, the semi-insulating layer Conductor devices do not have the limitations on the number of rewrite cycles that are a problem with conventional non-volatile memory. Reliability improves dramatically. Furthermore, information is obtained depending on the on and off states of the transistor. Because the data is written, high-speed operation can be easily achieved. Also, when rewriting information Another advantage is that it eliminates the need to perform an action to erase previous information.

[0032] Furthermore, transistors using materials other than oxide semiconductors are capable of sufficiently high-speed operation, By using this method, it is possible to read the contents of memory at high speed.

[0033] Furthermore, the presence of a boost circuit makes it easier to perform multi-level conversion, thus improving memory capacity. It is possible.

[0034] Thus, transistors using materials other than oxide semiconductors and transistors using oxide semiconductors By integrating a transistor, a semiconductor device with unprecedented features can be realized. It is possible. [Brief explanation of the drawing]

[0035] [Figure 1] A circuit diagram used to explain a semiconductor device. [Figure 2] Cross-sectional and plan views illustrating a semiconductor device. [Figure 3] A cross-sectional diagram illustrating the manufacturing process of semiconductor devices. [Figure 4] A cross-sectional diagram illustrating the manufacturing process of semiconductor devices. [Figure 5] A cross-sectional diagram illustrating the manufacturing process of semiconductor devices. [Figure 6] Cross-sectional view of a transistor using an oxide semiconductor. [Figure 7] The energy band diagram (schematic diagram) in the A-A' section of Figure 6. [Figure 8](A) shows the state where a positive potential (+VG) is applied to the gate (GE1), and (B) shows the state where a negative potential (VG<0) is applied to the gate (GE1). [Figure 9] This diagram shows the relationship between the vacuum level, the work function (φM) of metals, and the electron affinity (χ) of oxide semiconductors. [Figure 10] A diagram showing the CV characteristics. [Figure 11] A diagram showing the relationship between Vg and (1 / C)². [Figure 12] A cross-sectional diagram illustrating a semiconductor device. [Figure 13] A cross-sectional diagram illustrating a semiconductor device. [Figure 14] A cross-sectional diagram illustrating a semiconductor device. [Figure 15] A cross-sectional diagram illustrating a semiconductor device. [Figure 16] A circuit diagram illustrating a memory element. [Figure 17] A circuit diagram used to explain a semiconductor device. [Figure 18] A circuit diagram to explain the drive circuit. [Figure 19] A circuit diagram to explain the drive circuit. [Figure 20] A circuit diagram illustrating the readout circuit. [Figure 21] A circuit diagram illustrating a potential generation circuit. [Figure 22] A circuit diagram to explain a boost converter circuit. [Figure 23] A circuit diagram illustrating a differential sense amplifier. [Figure 24] A circuit diagram illustrating a latch-type sense amplifier. [Figure 25] A diagram showing a timing chart to explain the operation. [Figure 26] A circuit diagram used to explain a semiconductor device. [Figure 27] A circuit diagram illustrating the readout circuit. [Figure 28] A diagram showing a timing chart to explain the operation. [Figure 29]A diagram illustrating the readout circuit. [Figure 30] A diagram showing a timing chart to explain the operation. [Figure 31] A circuit diagram illustrating a memory element. [Figure 32] A circuit diagram used to explain a semiconductor device. [Figure 33] A circuit diagram illustrating the readout circuit. [Figure 34] A circuit diagram to explain the drive circuit. [Figure 35] A diagram showing a timing chart to explain the operation. [Figure 36] A diagram showing the relationship between node A and the word line potential. [Figure 37] A diagram used to explain electronic devices. [Modes for carrying out the invention]

[0036] An example of an embodiment of the present invention will be described below with reference to the drawings. However, the present invention is as follows The description is not limited to the present invention, and without departing from the spirit and scope of the present invention, its form and Those skilled in the art will readily understand that the details can be modified in various ways. Therefore, the present invention is as follows: The description of the embodiment shown is not to be limited to the content described therein.

[0037] Note that the position, size, and scope of each component shown in the drawings, etc., are for ease of understanding. The position, size, and extent of the boundary may not be shown. Therefore, it is not always possible to see this in drawings, etc. It is not limited to the indicated location, size, or range.

[0038] Furthermore, the ordinal numbers such as "1st," "2nd," and "3rd" used in this specification, etc., are intended to avoid confusion of constituent elements. This is added to avoid any misunderstandings and does not mean that the number is limited.

[0039] (Embodiment 1) In this embodiment, the configuration and manufacturing method of a semiconductor device according to one aspect of the disclosed invention are described below. This will be explained with reference to Figures 1 to 15.

[0040] <Circuit configuration of semiconductor device> Figure 1 shows an example of the circuit configuration of a semiconductor device. This semiconductor device is made of materials other than oxide semiconductors. It consists of a transistor 160 made of material and a transistor 162 made of oxide semiconductor. This is achieved. Furthermore, in Figure 1, it is clear that transistor 162 uses an oxide semiconductor. To indicate this, the OS code is included.

[0041] Here, the gate electrode of transistor 160 and the source electrode or dot of transistor 162 It is electrically connected to one of the rain electrodes. Also, the first line The source wire (also called the source line) and the source electrode of transistor 160 are electrically connected, and the second The wiring (2nd Line: also called the bit line) and the drain electrode of transistor 160 and They are electrically connected. And the third wire (3rd Line: also known as the 1st signal line) The other of the source electrode or drain electrode of transistor 162 is electrically connected. And the fourth wire (4th Line: also called the second signal line) and transistor 162 The gate electrode is electrically connected.

[0042] Transistor 160, which uses materials other than oxide semiconductors, is capable of sufficiently high-speed operation, By using this, it is possible to perform tasks such as reading stored contents at high speed. Furthermore, The oxide semiconductor transistor 162 has the characteristic of having an extremely low off-current. Therefore, by turning off transistor 162, transistor 160 It is possible to maintain the potential of the gate electrode for an extremely long period of time.

[0043] By taking advantage of the characteristic that the potential of the gate electrode can be maintained for a long period of time, the following As described above, information can be written to, stored, and read.

[0044] First, we will explain how to write and retain information. First, the potential of the fourth wire is... The potential at which transistor 162 turns on is set to the ON state, and transistor 162 is turned ON. As a result, the potential of the third wire is applied to the gate electrode of transistor 160 (write (Including). Then, the potential of the fourth wire is set as the potential at which transistor 162 is in the off state. By turning off transistor 162, the gate electrode of transistor 160 The electric potential is maintained (held).

[0045] Since the off-current of transistor 162 is extremely small, the gate electrode of transistor 160 The potential is maintained for a long time. For example, the potential of the gate electrode of transistor 160 is If the potential is such that transistor 160 is turned on, then transistor 160 will remain in the turned-on state for a long time. This will be maintained over time. Also, the potential of the gate electrode of transistor 160 If the potential is such that transistor 160 is in the off state, then transistor 160 will remain in the off state for a long time. It is retained over time.

[0046] Next, we will explain how to read the information. As mentioned above, the ON state of transistor 160 Alternatively, when the OFF state is maintained, a predetermined potential (low potential) is applied to the first wiring. When this happens, the potential of the second wiring differs depending on whether transistor 160 is on or off. It takes the following value. For example, when transistor 160 is ON, the potential of the first wiring is As a result, the potential of the second wiring decreases. Conversely, transistor 160 is In the "F" state, the potential of the second wiring does not change.

[0047] In this way, while the information is retained, the potential of the first wiring and the potential of the second wiring are By comparing them, we can extract information.

[0048] Next, we will explain how to rewrite information. Rewriting information involves writing the information as described above and This is done in the same way as holding. In other words, the potential of the fourth wire is set when transistor 162 is ON. To achieve this potential, transistor 162 is turned ON. This results in the potential of the third wiring. (A potential related to new information) is applied to the gate electrode of transistor 160. Then, The potential of the fourth wire is set to the potential at which transistor 162 is in the OFF state, By turning off 62, the new information is retained.

[0049] Thus, the semiconductor device relating to the disclosed invention directly generates information through subsequent writing. It is possible to rewrite the information. Therefore, it is necessary in flash memory and other applications. This eliminates the need for an erase operation, thus suppressing the decrease in operating speed caused by the erase operation. In other words, high-speed operation of semiconductor devices will be achieved.

[0050] Note that the above explanation refers to an n-type transistor (n-channel transistor) that uses electrons as carriers. This concerns the case where ) is used, but instead of an n-type transistor, holes are used as carriers. It goes without saying that a p-type transistor can be used.

[0051] Furthermore, in order to facilitate the maintenance of the potential of the gate electrode of transistor 160, It goes without saying that capacitive elements or the like can be added to the gate electrode of the 160.

[0052] <Planar and cross-sectional configurations of semiconductor devices> Figure 2 shows an example of the configuration of the semiconductor device described above. Figure 2(A) shows a cross-section of the semiconductor device. Figure 2(B) shows the planes of the semiconductor device. Here, Figure 2(A) is the same as Figure 2(B). This corresponds to the cross-section along lines A1-A2 and B1-B2. Figures 2(A) and 2(B) The semiconductor device shown in ) has a transistor 160 at the bottom that uses a material other than an oxide semiconductor. It has a transistor 162 made of oxide semiconductor on its upper part. Transistor 160 and transistor 162 are both described as n-type transistors. However, a p-type transistor may also be used. In particular, transistor 160 should be a p-type transistor. This is possible.

[0053] The transistor 160 is located in a channel formation region 11 provided on a substrate 100 containing semiconductor material. 6 and the impurity region 114 and high concentration impurity region provided so as to sandwich the channel formation region 116. The pure material region 120 (these are also simply called the impurity region) and the channel-forming region 11 A gate insulating layer 108a provided on 6, and a gate provided on the gate insulating layer 108a The electrode 110a and the impurity region 114 provided on one side of the channel formation region 116 are connected. The source electrode or drain electrode 130a is connected by gas, and the channel forming region 116 is also connected to the source electrode or drain electrode 130a. A source electrode or drain electrode electrically connected to an impurity region 114 provided on one side. It has 130b.

[0054] Here, a sidewall insulating layer 118 is provided on the side surface of the gate electrode 110a. Furthermore, the substrate 100 is provided with a sidewall insulating layer 118 sandwiched between them when viewed in plan. It has a high-concentration impurity region 120, and a metal compound region 124 is located on the high-concentration impurity region 120. Furthermore, on the substrate 100, element isolation and insulation are provided so as to surround the p-type transistor 160. A layer 106 is provided, and an interlayer insulating layer 126 is provided so as to cover the p-type transistor 160. An interlayer insulating layer 128 is provided. Through the opening formed, the source electrode or drain electrode 130a enters the channel forming region 1 A metallic compound region 124 provided on one side of 16 is electrically connected to the source electrode or The drain electrode 130b is a metal compound provided on the other side of the channel forming region 116. It is electrically connected to region 124, that is, to the source electrode or drain electrode 130a. The channel is formed through a metal compound region 124 located on one side of the channel-forming region 116. A high-concentration impurity region 120 and channel formation are provided on one side of the channel formation region 116. It is electrically connected to the impurity region 114 located on one side of region 116, and to the source electrode. Alternatively, the drain electrode 130b is a metallized compound provided on the other side of the channel forming region 116. High-concentration impurity region provided on the other side of the channel-forming region 116 via the material region 124 120 and the impurity region 114 provided on the other side of the channel forming region 116 and electrical It is connected to the gate electrode 110a, and the source electrode or drain electrode 13 Electrode 130c, which is provided similarly to 0a and the source electrode or drain electrode 130b, is electrically Connected.

[0055] The transistor 162 has a gate electrode 136d provided on the interlayer insulating layer 128, and a gate A gate insulating layer 138 provided on electrode 136d, and a gate insulating layer 138 provided on An oxide semiconductor layer 140, and provided on the oxide semiconductor layer 140, and The electrically connected source electrode or drain electrode 142a, source electrode or drain It has an in electrode 142b.

[0056] Here, the gate electrode 136d is embedded in the insulating layer 132 formed on the interlayer insulating layer 128. It is provided so as to be inserted. Also, similar to the gate electrode 136d, the source electrode or Electrode 136a is in contact with drain electrode 130a, and is connected to source electrode or drain electrode 130b Electrode 136b is formed in contact with electrode 130c, and electrode 136c is formed in contact with electrode 130c. ru.

[0057] Furthermore, a protective layer is placed on top of the transistor 162 so as to be in contact with a portion of the oxide semiconductor layer 140. An insulating layer 144 is provided, and an interlayer insulating layer 146 is provided on the protective insulating layer 144. Here, the protective insulating layer 144 and the interlayer insulating layer 146 have a source electrode or drain. An opening is provided that reaches the source electrode 142a, or the drain electrode 142b. Furthermore, through the opening, electrodes 150d and 150e are connected to the source electrode or drain electrode. It is formed in contact with electrode 142a, source electrode or drain electrode 142b. Similar to pole 150d and electrode 150e, the gate insulating layer 138, protective insulating layer 144, and interlayer insulating layer Through the opening provided in layer 146, electrodes 136a, 136b, and 136c are in contact. Electrodes 150a, 150b, and 150c are formed.

[0058] Here, it is desirable that the oxide semiconductor layer 140 is sufficiently purified by removing impurities such as hydrogen. Specifically, the hydrogen concentration in the oxide semiconductor layer 140 is 5×10 19 atoms / cm 3 or less, preferably 5×10 18 atoms / cm 3 or less, more preferably 5×10 17 atoms / cm 3 or less. Further, it is desirable that the oxide semiconductor layer 140 contains sufficient oxygen so that defects caused by oxygen deficiency are reduced. When the hydrogen concentration is sufficiently reduced and the oxide semiconductor layer 140 is highly purified and defects caused by oxygen deficiency are reduced, in the oxide semiconductor layer 140, the carrier concentration is 1×10 / cm 12 or less, preferably 1×10 3 / cm 11 or less. 3 Thus, by using an i - type (intrinsic) or substantially i - type oxide semiconductor, a transistor 162 with extremely excellent off - current characteristics can be obtained. For example, when the drain voltage Vd is +1V or +10V and the gate voltage Vg is in the range from - 5 V to - 20V, the off - current is 1×10<00> A or less. -13 Thus, by applying an oxide semiconductor layer 140 in which the hydrogen concentration is sufficiently reduced and highly purified and defects caused by oxygen deficiency are reduced, and reducing the off - current of the transistor 162, a new - configuration semiconductor device can be realized. Note that the hydrogen concentration in the above - mentioned oxide semiconductor layer 140 is measured by secondary ion mass spectrometry (SIMS). ctroscopy).

[0059] Furthermore, an insulating layer 152 is provided on the interlayer insulating layer 146, and embedded in the insulating layer 152. Electrodes 154a, 154b, 154c, and 154d are provided so as to be inserted. Here, electrode 154a is in contact with electrode 150a, and electrode 154b is in contact with electrode 150 It is in contact with b, and electrode 154c is in contact with electrode 150c and electrode 150d, and electrode 1 Electrode 54d is in contact with electrode 150e.

[0060] In other words, in the semiconductor device shown in Figure 2, the gate electrode 110a of transistor 160 and The source electrode or drain electrode 142a of transistor 162 is connected to electrode 130c, electrode Electrodes 136c, 150c, 154c and 150d are electrically connected. Yes, they are.

[0061] <Method for fabricating semiconductor devices> Next, we will describe an example of a method for manufacturing the above semiconductor device. Below, we will first explain the lower part The method for fabricating the transistor 160 will be explained with reference to Figure 3, and then the upper transistor The method for manufacturing Ta162 will be explained with reference to Figures 4 and 5.

[0062] <Method for fabricating the lower transistor> First, prepare a substrate 100 containing semiconductor material (see Figure 3(A)). The plate 100 can be a single-crystal semiconductor substrate such as silicon or silicon carbide, or a polycrystalline semiconductor substrate. Compound semiconductor substrates such as silicon germanium, SOI substrates, etc. can be applied. Here, we will use a single-crystal silicon substrate as the substrate 100 containing semiconductor material. An example will be shown. Generally speaking, an "SOI substrate" is a substrate with silicon semiconductor on an insulating surface. This refers to a substrate having a conductive layer, but in this specification, it refers to a substrate having a silicon on the insulating surface. This concept is used to include substrates with a semiconductor layer made of materials other than those mentioned above. The semiconductor layer of the "SOI substrate" is not limited to a silicon semiconductor layer. The substrate has a configuration in which a semiconductor layer is provided on an insulating substrate such as a glass substrate, with an insulating layer in between. It shall include the following.

[0063] A protective layer 102 is formed on the substrate 100, which serves as a mask for forming an element isolation insulating layer. (See Figure 3(A)). The protective layer 102 can be, for example, silicon oxide or silicon nitride. An insulating layer made of silicon nitride or similar material can be used. In order to control the threshold voltage of the transistor, an impurity is imparted to impart n-type conductivity. Monochemical elements or impurity elements that impart p-type conductivity may be added to the substrate 100. In the case of ricon, impurities that impart n-type conductivity include, for example, phosphorus and arsenic. This can be achieved. Furthermore, examples of impurities that impart p-type conductivity include boron and aluminum. Materials such as nium and gallium can be used.

[0064] Next, etching is performed using the protective layer 102 as a mask, and the material covered by the protective layer 102 is then... A portion of the substrate 100 in the area that is not present (exposed area) is removed. This separates the half A conductive region 104 is formed (see Figure 3(B)). Dry etching is used for this etching process. It is preferable to use an etching gas, but wet etching may also be used. The etching solution can be appropriately selected depending on the material to be etched.

[0065] Next, an insulating layer is formed to cover the semiconductor region 104, and the region superimposed on the semiconductor region 104 By selectively removing the insulating layer, an element isolation insulating layer 106 is formed (see Figure 3(B)). The insulating layer is formed using silicon oxide, silicon nitride, silicon nitride oxide, etc. There are methods for removing the insulating layer, such as polishing treatments like CMP and etching, but Either of the above may be used. Note that after the formation of the semiconductor region 104, or the element isolation insulating layer 1 After the formation of 06, the protective layer 102 is removed.

[0066] Next, an insulating layer is formed on the semiconductor region 104, and a layer containing a conductive material is formed on the insulating layer. ru.

[0067] The insulating layer will later become the gate insulating layer, and can be obtained using methods such as CVD or sputtering. Silicon oxide, silicon nitride, silicon nitride, hafnium oxide, aluminum oxide A single-layer or multi-layer structure of a film containing aluminum, tantalum oxide, etc. is preferable. By oxidizing and nitriding the surface of the semiconductor region 104 through lazma treatment or thermal oxidation treatment, The above insulating layer may be formed. High-density plasma treatment can be performed using, for example, He, Ar, Kr, X Mixture gases are formed by combining noble gases such as e with oxygen, nitrogen oxides, ammonia, nitrogen, hydrogen, etc. This can be done using a smudger. Furthermore, the thickness of the insulating layer is not particularly limited, but for example, 1n It can be between m and 100 nm.

[0068] The layer containing conductive material is made of metallic materials such as aluminum, copper, titanium, tantalum, and tungsten. It can be formed using semiconductor materials such as polycrystalline silicon containing conductive materials. A layer containing a conductive material may be formed using [a specific method]. The formation method is not particularly limited and may include vapor deposition, C [another specific method]. Various film deposition methods such as the VD method, sputtering method, and spin coating method can be used. In this embodiment, an example of forming a layer containing a conductive material using a metal material is described below. This shall be shown.

[0069] Subsequently, the insulating layer and the layer containing the conductive material are selectively etched to form the gate insulating layer 108 a. Form the gate electrode 110a (see Figure 3(C)).

[0070] Next, an insulating layer 112 is formed to cover the gate electrode 110a (see Figure 3(C)). Then, By adding phosphorus (P) or arsenic (As) to the semiconductor region 104, impurity regions with shallow junction depths are created. Region 114 is formed (see Figure 3(C)). Note that here an n-type transistor is formed. Although phosphorus and arsenic are added for this purpose, when forming a p-type transistor, boron (B) or Adding impurity elements such as aluminum (Al) is sufficient. As a result, a channel formation region 116 is formed below the gate insulating layer 108a of the semiconductor region 104. This is formed (see Figure 3(C)). Here, the concentration of the added impurities can be set as appropriate. It is possible, but when semiconductor devices are miniaturized to a high degree, it is desirable to increase the concentration. Furthermore, in this process, the impurity region 114 is formed after the insulating layer 112 is formed. Although this method is used, it is also acceptable to form the insulating layer 112 after forming the impurity region 114. stomach.

[0071] Next, the sidewall insulating layer 118 is formed (see Figure 3(D)). Layer 118 is formed to cover the insulating layer 112, and then an insulating layer is formed to provide high anisotropy to the insulating layer. By applying etching, it can be formed in a self-aligned manner. Also, at this time, The insulating layer 112 is partially etched, and the upper surface of the gate electrode 110a and the impurity region 11 It's best to expose the top surface of 4.

[0072] Next, cover the gate electrode 110a, impurity region 114, sidewall insulating layer 118, etc. Then, an insulating layer is formed. And in the region in contact with the impurity region 114, phosphorus (P) and arsenic (As), etc., are added to form a high-concentration impurity region 120 (see Figure 3(E)). Next, the above insulating layer is removed, and the gate electrode 110a, sidewall insulating layer 118, high concentration A metal layer 122 is formed to cover the pure material region 120, etc. (see Figure 3(E)). 122 uses various film deposition methods such as vacuum deposition, sputtering, and spin coating. It can be formed. The metal layer 122 reacts with the semiconductor material constituting the semiconductor region 104. Therefore, it is desirable to form it using a metal material that results in a low-resistance metal compound. Examples of related materials include titanium, tantalum, tungsten, nickel, cobalt, and platinum. These include:

[0073] Next, heat treatment is performed to react the metal layer 122 with the semiconductor material. This results in high A metal compound region 124 is formed adjacent to the concentration impurity region 120 (see Figure 3(F)). Furthermore, if polycrystalline silicon or the like is used as the gate electrode 110a, A metal compound region will also be formed in the area of ​​0a that is in contact with the metal layer 122.

[0074] As for the above heat treatment, for example, heat treatment by irradiation with a flash lamp can be used. Of course, other heat treatment methods may be used, but the chemical reaction involved in the formation of metal compounds is important. To improve controllability, it is desirable to use a method that enables very short heat treatment times. It appears that the above-mentioned metal compound region 124 is formed by the reaction between the metal material and the semiconductor material. This is a region where conductivity is sufficiently enhanced. (Metal compound region 124) By forming this structure, electrical resistance can be sufficiently reduced, and the characteristics of the element can be improved. After forming the metal compound region 124, the metal layer 122 is removed.

[0075] Next, an interlayer insulating layer 126 and an interlayer insulating layer are formed to cover each of the components formed by the above process. Forms 128 (see Figure 3(G)). Interlayer insulating layers 126 and 128 are formed of oxides Silicon nitride, silicon nitride, hafnium oxide, aluminum oxide, tahnix oxide It can be formed using materials containing inorganic insulating materials such as tar. Also, polyimide, It is also possible to form it using organic insulating materials such as acrylic. The structure consists of two layers: an edge layer 126 and an interlayer insulating layer 128. However, the configuration of the interlayer insulating layer is not limited to this. It is not done. After the formation of the interlayer insulating layer 128, its surface is treated by CMP or etching. It is desirable to flatten it out.

[0076] Subsequently, an opening is formed in the interlayer insulating layer that extends to the metal compound region 124, and the opening Then, the source electrode or drain electrode 130a and the source electrode or drain electrode 130b are connected. Form (see Figure 3(H)). Source electrode or drain electrode 130a or source electrode or The drain electrode 130b is, for example, subjected to PVD or CVD methods in the region including the opening. After forming the conductive layer, a portion of the conductive layer is removed using methods such as etching or CMP. It can be formed by removing.

[0077] Furthermore, a portion of the above conductive layer can be removed to form the source electrode or drain electrode 130a or source electrode. Alternatively, when forming the drain electrode 130b, the surface is processed to be flat. This is desirable. For example, after forming a thin titanium film or titanium nitride film in the region including the opening, When forming a tungsten film to fill an opening, subsequent CMP (Chemical Polishing) can cause problems. The necessary tungsten film, titanium film, titanium nitride film, etc., are removed, and the flatness of the surface is improved. This can improve the source electrode or drain electrode 130a, By planarizing the surface including the drain electrode 130b, in subsequent processes This makes it possible to form good electrodes, wiring, insulating layers, semiconductor layers, etc.

[0078] In this case, the source electrode or drain electrode 130 that comes into contact with the metal compound region 124 Although only a and the source electrode or drain electrode 130b are shown, in this process, An electrode that comes into contact with electrode 110a (for example, electrode 130c in Figure 2(A)) They can be formed together. Source electrode or drain electrode 130a, source electrode or There are no particular limitations on the material that can be used as the drain electrode 130b, and various conductive materials are available. Electrical materials can be used. For example, molybdenum, titanium, chromium, tantalum, tungsten. Conductive materials such as stainless steel, aluminum, copper, neodymium, and scandium can be used. Cut.

[0079] As a result, a transistor 160 is formed using a substrate 100 containing semiconductor material. After the above process, electrodes, wiring, insulating layers, etc. may be formed. Furthermore, by adopting a multilayer wiring structure consisting of a laminated structure of interlayer insulating layers and conductive layers, high We can provide a semiconductor device with integrated components.

[0080] <Method for fabricating the upper transistor> Next, using Figures 4 and 5, the process of fabricating the transistor 162 on the interlayer insulating layer 128 is described. The process will be explained. Figures 4 and 5 show various electrodes on the interlayer insulating layer 128 and the trap. This shows the manufacturing process for transistor 162, and is therefore located at the bottom of transistor 162. Details regarding transistor 160 and other components have been omitted.

[0081] First, the interlayer insulating layer 128, the source electrode or drain electrode 130a, the source electrode or drain An insulating layer 132 is formed on the rain electrode 130b and electrode 130c (see Figure 4(A)). The marginal layer 132 can be formed using methods such as PVD or CVD. Silicon nitride, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide It can be formed using materials containing inorganic insulating materials such as ru.

[0082] Next, the source electrode or drain electrode 130a, source electrode or An opening is formed that extends to the drain electrode 130b and electrode 130c. An opening is also formed in the region where the gate electrode 136d is formed. A conductive layer 134 is formed to embed it (see Figure 4(B)). The above opening is made using a mask. It can be formed by methods such as etching. The mask is a photomask. It can be formed by methods such as exposure. Etching can be done using wet etching. Either etching or dry etching can be used, but from the perspective of microfabrication, dry etching is preferable. It is preferable to use a ching. The conductive layer 134 is formed by methods such as PVD or CVD. This can be done using a film method. Materials that can be used to form the conductive layer 134 include Molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium Examples include conductive materials such as scandium, as well as alloys and compounds of these materials (e.g., nitrides). It is possible.

[0083] More specifically, for example, a thin titanium film is formed in the region including the opening by the PVD method, and CV After forming a thin titanium nitride film using method D, a tungsten film was formed to embed it in the opening. A method can be applied to achieve this. Here, the titanium film formed by the PVD method is The oxide film on the surface is reduced, and the lower electrode (here, the source electrode or drain electrode 130a, sole Function to reduce contact resistance with the drain electrode or electrode 130b, electrode 130c, etc. It has. Furthermore, the titanium nitride film formed thereafter suppresses the diffusion of conductive materials. It has the function of [unclear]. In addition, after forming a barrier film with titanium or titanium nitride, plating is performed. A copper film may be formed according to the law.

[0084] After forming the conductive layer 134, the conductive layer 134 is processed using methods such as etching and CMP. Remove a portion of it to expose the insulating layer 132, and then remove electrodes 136a, 136b, and 136 c. Form the gate electrode 136d (see Figure 4(C)). Note that a part of the conductive layer 134 is also formed. Remove the material to form electrodes 136a, 136b, 136c, and gate electrode 136d. In this case, it is desirable to process the surface so that it becomes flat. Thus, the insulating layer 132, The surfaces of electrodes 136a, 136b, 136c, and gate electrode 136d are planarized. This allows for the formation of good electrodes, wiring, insulating layers, semiconductor layers, etc., in subsequent processes. This becomes possible.

[0085] Next, insulating layer 132, electrode 136a, electrode 136b, electrode 136c, gate electrode 136d A gate insulating layer 138 is formed to cover it (see Figure 4(D)). Gate insulating layer 138 This can be formed using methods such as CVD or sputtering. Also, the gate insulating layer 138 is silicon oxide, silicon nitride, silicon oxide nitride, silicon oxide nitride, aluminum oxide, oxide It is preferable to form the gate insulation to include hafnium, tantalum oxide, etc. Layer 138 may be a single-layer structure or a multi-layer structure. For example, as a raw material gas By plasma CVD using silane (SiH4), oxygen, and nitrogen, silicon oxide nitride is produced. A gate insulating layer 138 can be formed. The thickness of the gate insulating layer 138 is not particularly limited. However, it is not possible to set it to, for example, 10 nm to 500 nm. For example, a first gate insulating layer with a film thickness of 50 nm or more and 200 nm or less, and the first gate insulating It is preferable to laminate a second gate insulating layer with a thickness of 5 nm to 300 nm on the layer.

[0086] Furthermore, by removing impurities, the oxide semiconductor can be made i-type or substantially i-type (high Purified oxide semiconductors are extremely sensitive to interface states and interface charges, therefore When using oxide semiconductors like the one shown in the image for the oxide semiconductor layer, the interface with the gate insulating layer is important. Therefore, the gate insulating layer 138 in contact with the highly purified oxide semiconductor layer is made of high-grade material. This will require a change in quality.

[0087] For example, high-density plasma CVD using μ-wave (2.45 GHz) is a method that produces dense materials with high dielectric strength. It is suitable in that it can form a high-quality gate insulating layer 138. The close contact between the conductor layer and the high-quality gate insulating layer reduces the interface state and improves the interface properties. Because it can be made into something desirable.

[0088] Of course, if it can form a good insulating layer as a gate insulating layer, then high-purity material Even when using an oxide semiconductor layer, other methods such as sputtering and plasma CVD are used. The method can be applied. Furthermore, the film quality and interface properties can be modified by heat treatment after formation. An insulating layer may be applied. In any case, the film quality of the gate insulating layer 138 is good. Furthermore, it reduces the interface state density with the oxide semiconductor layer, enabling the formation of a good interface. You just need to form it.

[0089] Furthermore, at a temperature of 85°C and an electric field strength of 2 × 10⁻⁶, 6 V / cm, 12-hour gate bias, thermal strain In the BT test, if impurities are added to the oxide semiconductor, the impurities and The bond with the main component of the oxide semiconductor is broken by a strong electric field (B: bias) and high temperature (T: temperature). When disconnected, the resulting unconnected hands induce a drift in the threshold voltage (Vth). .

[0090] In contrast, impurities in oxide semiconductors, especially hydrogen and water, are eliminated as much as possible, and as described above, By improving the interface characteristics with the gate insulating layer, a stable transistor can be obtained even for the BT test.

[0091] Next, an oxide semiconductor layer is formed on the gate insulating layer 138, and the oxide semiconductor layer is processed by a method such as etching using a mask to form an island-shaped oxide semiconductor layer 140 (see Fig. 4(E)).

[0092] As the oxide semiconductor layer, an In-Sn-Ga-Zn-O which is a quaternary metal oxide, or a ternary metal oxide such as In-Ga-Zn-O, In-Sn-Zn-O, In-Al-Zn- O, Sn-Ga-Zn-O, Al-Ga-Zn-O, Sn-Al-Zn-O, or a binary metal oxide such as In-Zn-O, Sn-Zn-O, Al-Zn-O, Zn-Mg-O, S n-Mg-O, In-Mg-O, or a single-element metal oxide such as In-O, Sn-O, Zn- O, etc. can be applied. Also, SiO2 may be included in the above oxide semiconductor material.

[0093] Also, for the oxide semiconductor layer, a thin film represented by InMO3(ZnO) m (m>0) can be used. Here, M represents one or more metal elements selected from Ga, Al, Mn, and Co. For example, as M, there are Ga, Ga and Al, Ga and Mn, or Ga and Co, etc. Among the oxide semiconductor films having a structure represented by InMO3(ZnO) (m>0), an oxide semiconductor having a structure containing Ga as M is called an In-Ga-Zn-O-based oxide semiconductor, and its thin film is called an In-Ga-Zn-O-based oxide semiconductor film (In-Ga-Zn-O-based m amorphous film), etc. ​​​​​​​

[0094] In this embodiment, an amorphous oxide semiconductor layer is formed by sputtering using a target for forming an In-Ga-Zn-O-based oxide semiconductor film as the oxide semiconductor layer. Note that by adding silicon to the amorphous oxide semiconductor layer, its crystallization can be suppressed. Therefore, for example, a target containing 2 wt% or more and 10 wt% or less of SiO2 may be used to form the oxide semiconductor layer. As a target for producing an oxide semiconductor layer by sputtering, for example, a target of a metal oxide mainly composed of zinc oxide can be used. Also, a target for forming an oxide semiconductor film containing In, Ga, and Zn (composition ratio: In2O3:Ga2O3:ZnO = 1:1:1 [mole ratio]) can be used. Further, as a target for forming an oxide semiconductor film containing In, Ga, and Zn, a target having a composition ratio of In2O3:Ga2O3:ZnO = 1:1:2 [mole ratio], or In2O3:Ga2O3:ZnO = 1:1:4 [mole ratio] may be used. The filling rate of the target for forming an oxide semiconductor film is 90% or more and 100% or less, preferably 95% or more (for example, 99.9%

[0095] ). By using a target for forming an oxide semiconductor film with a high filling rate, a dense oxide semiconductor layer is formed. The formation atmosphere of the oxide semiconductor layer is preferably a noble gas (typically argon) atmosphere, an oxygen atmosphere, or a mixed atmosphere of a noble gas (typically argon) and oxygen. Specifically, for example, impurities such as hydrogen, water, hydroxyl groups, and hydrides are at a concentration of about several ppm (desirable ). ). ). ). ). ). ). ).

[0096] ). ). ). It is preferable to use a high-purity gas that has been reduced to a concentration of several ppb or less.

[0097] During the formation of the oxide semiconductor layer, the substrate is held in a processing chamber under reduced pressure, and the substrate temperature is controlled. The temperature should be between 100°C and 600°C, preferably between 200°C and 400°C. Heat the substrate. By forming an oxide semiconductor layer while doing so, the impurity concentration contained in the oxide semiconductor layer is reduced. It can be reduced. Also, damage caused by sputtering is reduced. And the processing chamber Sputtered gas, from which hydrogen and water have been removed while removing residual moisture from the inside, is introduced, and metal oxides To form an oxide semiconductor layer targeting [the target], in order to remove residual moisture in the processing chamber, Therefore, it is preferable to use an adsorption-type vacuum pump. For example, a cryopump or an ion pump. A titanium sublimation pump can be used. In addition, as an exhaust means, A cold trap may be added to the pump. Exhaust using a cryopump. The deposition chamber is, for example, a compound containing hydrogen atoms such as water (H2O) (preferably Because compounds containing carbon atoms are exhausted, oxide semiconductors formed in the deposition chamber are affected. The concentration of impurities in the layer can be reduced.

[0098] Forming conditions include, for example, a distance of 100 mm between the substrate and the target, and a pressure of 0.6 Pa, DC power of 0.5 kW, atmosphere is oxygen (oxygen flow rate ratio 100%). These conditions can be applied. Furthermore, when using a pulsed DC power supply, film deposition can be performed. The amount of powdery material (also called particles or dust) that is sometimes generated can be reduced, and the film thickness distribution can be made uniform. Therefore, it is suitable. The thickness of the oxide semiconductor layer is preferably 2 nm or more and 200 nm or less. It shall be 5 nm or more and 30 nm or less. Note that the appropriate thickness varies depending on the oxide semiconductor material to be applied, so the thickness may be appropriately selected according to the material used. Therefore, the thickness may be appropriately selected according to the material used.

[0099] Note that before forming the oxide semiconductor layer by sputtering, it is preferable to perform reverse sputtering in which argon gas is introduced to generate plasma to remove dust adhering to the surface of the gate insulating layer 138. Here, reverse sputtering means a method of modifying the surface by colliding ions with the processing surface, contrary to the normal sputtering where ions are collided with the sputtering target. As a method of colliding ions with the processing surface, there is a method of applying a high-frequency voltage to the processing surface side in an argon atmosphere to generate plasma near the substrate. Note that a nitrogen atmosphere, a helium atmosphere, an oxygen atmosphere, or the like may be used instead of the argon atmosphere.

[0100]

[0101]

[0102]

[0103] <了 HF3, etc., hydrogen bromide (HBr), oxygen (O2), and helium (He) in these gases Gases to which noble gases such as argon (Ar) have been added may also be used.

[0102] As for dry etching methods, parallel plate type RIE (Reactive Ion Etching) Methods such as the ing method and ICP (Inductively Coupled Plasma: induction) A coupled plasma etching method can be used. It can etch into the desired shape. Etching conditions (amount of power applied to the coil-type electrode, amount of power applied to the electrode on the substrate side) The power consumption, electrode temperature on the substrate, etc., should be set as appropriate.

[0103] The etching solution used for wet etching is a solution of phosphoric acid, acetic acid, and nitric acid, Ammonia Hydrogenated Water (31% hydrogen peroxide by weight: 28% ammonia by weight: water = 5:2:2) These can be used. In addition, etching solutions such as ITO07N (manufactured by Kanto Chemical Co., Ltd.) can be used. It's okay to be there.

[0104] Next, it is desirable to perform a first heat treatment on the oxide semiconductor layer. This first heat treatment This allows for the dehydration or dehydrogenation of the oxide semiconductor layer. The temperature of the first heat treatment is The temperature should be between 300°C and 750°C, preferably above 400°C and below the substrate's strain point. For example, The substrate is introduced into an electric furnace using a resistance heating element, and the oxide semiconductor layer 140 is exposed to a nitrogen atmosphere. A heat treatment is performed at 450°C under atmospheric pressure for 1 hour. During this time, the oxide semiconductor layer 140 is exposed to the atmosphere. Avoid contact and prevent the re-introduction of water or hydrogen.

[0105] Furthermore, heat treatment equipment is not limited to electric furnaces; it also includes heat conduction from a heated medium such as gas, or It may also be a device that heats the object to be processed by thermal radiation. For example, LRTA (Lamp Rapid Thermal Annealing (GRTA) equipment, GRTA (Gas Rapid RTA (Rapid Thermal Anneal) for Thermal Anneal devices, etc. A device can be used. The LRTA device uses halogen lamps and metal halide lamps. Lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, high-pressure water A device that heats an object to be processed by radiating light (electromagnetic waves) from a lamp such as a silver lamp. Yes, there is. A GRTA device is a device that performs heat treatment using high-temperature gas. As for the gas, Inert gases such as argon or nitrogen, which do not react with the material being treated during heat treatment. A gas is used.

[0106] For example, as a first heat treatment, a substrate is placed in an inert gas heated to a high temperature of 650°C to 700°C. After adding the inert gas and heating for several minutes, the substrate is removed from the inert gas in a GRTA treatment. It is also possible to use GRTA treatment, which allows for high-temperature heat treatment in a short time. Because it is a heat treatment, it can be applied even under temperature conditions that exceed the strain point of the substrate.

[0107] Furthermore, the first heat treatment mainly uses nitrogen or noble gases (helium, neon, argon, etc.) It is desirable to carry out the procedure in an atmosphere that does not contain water, hydrogen, etc. For example The purity of nitrogen, or noble gases such as helium, neon, and argon, introduced into the heat treatment apparatus, 6N (99.9999%) or higher, preferably 7N (99.99999%) or higher (i.e.) The impurity concentration shall be 1 ppm or less, preferably 0.1 ppm or less.

[0108] Depending on the conditions of the first heat treatment, or the material of the oxide semiconductor layer, the oxide semiconductor layer may crystallize. Furthermore, it may be microcrystalline or polycrystalline. For example, the crystallinity rate may be 90% or more, or 80%. In some cases, a microcrystalline oxide semiconductor layer of % or more may be formed. Also, depending on the conditions of the first heat treatment, Depending on the material of the oxide semiconductor layer, it may become an amorphous oxide semiconductor layer that does not contain crystalline components. There are also combinations.

[0109] Furthermore, crystals (particle size 1 nm or larger) can form on amorphous oxide semiconductors (for example, on the surface of an oxide semiconductor layer). In some cases, oxide semiconductor layers with a mixture of wavelengths (typically between 2nm and 4nm) may be present. be.

[0110] Furthermore, by providing a crystalline layer on the amorphous surface, the electrical properties of the oxide semiconductor layer can be altered. It is also possible to use an In-Ga-Zn-O-based oxide semiconductor film deposition target. When forming an oxide semiconductor layer using In2Ga2ZnO7, which has electrical anisotropy, By forming oriented crystalline regions, the electrical properties of the oxide semiconductor layer are altered. It is possible.

[0111] More specifically, for example, if the c-axis of In2Ga2ZnO7 is perpendicular to the surface of the oxide semiconductor layer By orienting the material in a specific direction, the conductivity in the direction parallel to the surface of the oxide semiconductor layer is improved. This allows for improved insulation in the direction perpendicular to the surface of the oxide semiconductor layer. Crystalline regions like these have the function of suppressing the intrusion of impurities such as water and hydrogen into the oxide semiconductor layer. To possess.

[0112] Furthermore, the oxide semiconductor layer having the crystalline portion described above is formed by GRTA treatment of the oxide semiconductor layer surface. It can be formed by surface heating. Also, the Zn content is greater than the In or Ga content. By using a smaller sputtering target, it is possible to form the material more favorably.

[0113] The first heat treatment of the oxide semiconductor layer 140 involves processing it into island-shaped oxide semiconductor layers 140. This can also be done on the previous oxide semiconductor layer. In that case, after the first heat treatment, a heating device or The substrate is then removed and subjected to the photolithography process.

[0114] Furthermore, the above heat treatment has the effect of dehydrating or dehydrogenating the oxide semiconductor layer 140. Therefore, it can also be called dehydration treatment, dehydrogenation treatment, etc. Such dehydration treatment, dehydration The chemical treatment involves, after the formation of the oxide semiconductor layer, a source electrode or draining process on the oxide semiconductor layer 140. After stacking the in electrodes, a protective insulating layer is formed on the source electrode or drain electrode, This can be done at times such as those mentioned above. The chemical treatment can be performed multiple times, not just once.

[0115] Next, the source electrode or drain electrode 142a is brought into contact with the oxide semiconductor layer 140. A source electrode or drain electrode 142b is formed (see Figure 4(F)). The drain electrode 142a, the source electrode or drain electrode 142b are oxide semiconductor layer 1 After forming a conductive layer to cover 40, selectively etch the conductive layer by It can be formed.

[0116] The conductive layer is produced using PVD methods such as sputtering, or CVD methods such as plasma CVD. It can be formed by [doing something]. Also, the conductive layer material can be aluminum, chromium, copper, Elements selected from tantalum, titanium, molybdenum, and tungsten, or the elements mentioned above, are used as components. Alloys such as manganese, magnesium, zirconium, and beryllium can be used. Materials containing one or more elements selected from thorium may also be used. Also, aluminum can be combined with titanium, tantalum, tungsten, molybdenum, chromium, and ne Even when using materials made from one or more elements selected from odymium and scandium, good.

[0117] Furthermore, the conductive layer may be formed from a conductive metal oxide. Examples of conductive metal oxides include acid Indium oxide (In2O3), tin oxide (SnO2), zinc oxide (ZnO), indium oxide Indium tin oxide alloy (In2O3-SnO2, sometimes abbreviated as ITO), indi oxide Zinc oxide alloy (In2O3-ZnO) or the aforementioned metal oxide material with silicon or A material containing silicon oxide can be used.

[0118] The conductive layer may be a single layer or a laminated structure of two or more layers. For example, sil A single-layer structure of an aluminum film containing condensate, and a two-layer structure in which a titanium film is laminated on top of an aluminum film. Examples include a three-layer structure in which a titanium film, an aluminum film, and another titanium film are stacked.

[0119] Here, the exposure used during mask formation for etching includes ultraviolet light, KrF laser light, and ArF Using laser light is preferable.

[0120] As shown in Figure 4(F), the channel length (L) of the transistor is on the oxide semiconductor layer 140. The lower end of the source electrode or drain electrode 142a and the source on the oxide semiconductor layer 140 This is determined by the distance between the electrode or the lower end of the drain electrode 142b. When exposing patterns with a length (L) of less than 25 nm, the range is extremely small, from a few nanometers to several tens of nanometers. Using short-wavelength extreme ultraviolet light, mask formation Exposure is performed. Exposure with ultra-ultraviolet light has high resolution and a large depth of field. Therefore, later formation The channel length (L) of the transistor can be set to between 10 nm and 1000 nm. It is capable of increasing the operating speed of the circuit. Furthermore, because the off-current value is extremely small, it consumes power. This avoids the need for increased power consumption.

[0121] Furthermore, when etching the conductive layer, care is taken to ensure that the oxide semiconductor layer 140 is not removed. Adjust the materials and etching conditions as appropriate. In this process, a portion of the oxide semiconductor layer 140 is etched, and grooves (recesses) are formed. ) can also form an oxide semiconductor layer having ).

[0122] Furthermore, between the oxide semiconductor layer 140 and the source electrode or drain electrode 142a, and the oxide semiconductor An oxide conductive layer is formed between the conductive layer 140 and the source electrode or drain electrode 142b. It may also be an oxide conductive layer and a source electrode or drain electrode 142a or source electrode or The conductive layer for forming the drain electrode 142b is formed continuously (continuous deposition). It is possible. The oxide conductive layer can function as either a source region or a drain region. By providing a conductive oxide layer, the resistance of the source region or drain region can be reduced. This enables high-speed operation of transistors.

[0123] Furthermore, in order to reduce the number of masks used and the number of processes, exposure is performed in which transmitted light has multiple intensities. A resist mask is formed using a multi-gradation mask, and this is used for etching. The process may be carried out. A resist mask formed using a multi-gradation mask has multiple thicknesses. It takes on a stepped shape, and the shape can be further deformed by ashing, It can be used in multiple etching processes to process different patterns. In other words, one sheet A multi-gradation mask allows for registration masks that correspond to at least two different patterns. A cavity can be formed. Therefore, the number of exposure masks can be reduced, and the corresponding cavity can be formed. Since the trisography process can also be reduced, the process can be simplified.

[0124] Furthermore, after the above-mentioned process, plasma treatment is performed using gases such as N2O, N2, or Ar. It is preferable to perform the following: The plasma treatment will cause the surface of the exposed oxide semiconductor layer to Adhered water and other substances are removed. Also, oxygen-containing gases such as a mixture of oxygen and argon are removed. Plasma treatment using a plasma can also be performed. This supplies oxygen to the oxide semiconductor layer. It is possible to reduce defects caused by oxygen deficiency.

[0125] Next, a protective insulating layer 14 that is in contact with a portion of the oxide semiconductor layer 140 without being exposed to the atmosphere. Form 4 (see Figure 4(G)).

[0126] The protective insulating layer 144 is formed by methods such as sputtering, which introduces impurities such as water and hydrogen into the protective insulating layer 144. It can be formed using appropriate methods that do not cause damage. Furthermore, its thickness should be 1 nm or more. Materials that can be used for the protective insulating layer 144 include silicon oxide, silicon nitride, and silicon oxide-nitride. Examples include silicon dioxide and silicon nitride. Furthermore, its structure can be a single layer or a multilayer structure. It is permissible to do so. The substrate temperature when forming the protective insulating layer 144 shall be between room temperature and 300°C. It is preferable that the atmosphere be a noble gas atmosphere (typically argon), an oxygen atmosphere, or a rare gas atmosphere. A mixed atmosphere of gas (typically argon) and oxygen is preferable.

[0127] If hydrogen is present in the protective insulating layer 144, the hydrogen may penetrate into the oxide semiconductor layer, and the hydrogen may... This can lead to oxygen abstraction in the oxide semiconductor layer, and the back channel side of the oxide semiconductor layer This can lead to a decrease in resistance and the formation of parasitic channels. Therefore, protective insulating layer 1 It is important to avoid using hydrogen in the formation process of 44, as it contains as little hydrogen as possible. That is the case.

[0128] Furthermore, it is preferable to form the protective insulating layer 144 while removing residual moisture in the processing chamber. The ion semiconductor layer 140 and the protective insulating layer 144 are free from hydrogen, hydroxyl groups, or moisture. This is for the purpose of doing so.

[0129] To remove residual moisture from the processing chamber, it is preferable to use an adsorption-type vacuum pump. For example, cryopumps, ion pumps, and titanium sublimation pumps are preferred. It is suitable. Furthermore, as an exhaust method, a turbo pump with a cold trap is used. It is also acceptable. The deposition chamber, which has been evacuated using a cryopump, contains, for example, hydrogen atoms and water (H2 Because compounds containing hydrogen atoms, such as O), are removed, the protective insulation formed in the deposition chamber is The concentration of impurities in layer 144 can be reduced.

[0130] The sputtering gas used when forming the protective insulating layer 144 may be hydrogen, water, hydroxyl groups or Impurities such as hydrides are removed to a concentration of several ppm (preferably several ppb). It is preferable to use a highly purified gas from which impurities have been removed.

[0131] Next, a second heat treatment (preferably 20) is performed under an inert gas atmosphere or an oxygen gas atmosphere. It is desirable to perform the procedure at temperatures between 0°C and 400°C (for example, between 250°C and 350°C). Next, a second heat treatment is performed at 250°C for 1 hour under a nitrogen atmosphere. After the second heat treatment, This can reduce variations in the electrical characteristics of the inverter. Furthermore, the second heat treatment This makes it possible to supply oxygen to the oxide semiconductor layer.

[0132] Furthermore, even if heat treatment is performed in air at temperatures between 100°C and 200°C for 1 hour to 30 hours Good. This heat treatment may be performed by heating while maintaining a constant heating temperature, or from room temperature to 100°C or higher. The process involves repeatedly raising the temperature to a heating temperature of 200°C or lower, and then lowering it from the heating temperature back to room temperature. This may be done. Alternatively, this heat treatment may be performed under reduced pressure before the formation of the protective insulating layer. Performing heat treatment under reduced pressure can shorten the heating time. Note that this heat treatment is as described above. This can be performed in place of the second heat treatment, or before or after the second heat treatment.

[0133] Next, an interlayer insulating layer 146 is formed on the protective insulating layer 144 (see Figure 5(A)). The marginal layer 146 can be formed using methods such as PVD or CVD. Silicon nitride, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide Formation of interlayer insulating layer 146 is possible using materials containing inorganic insulating materials such as ru. Afterward, it is desirable to planarize the surface using methods such as CMP or etching. It's nice.

[0134] Next, the interlayer insulating layer 146, the protective insulating layer 144, and the gate insulating layer 138 are treated with electrode 1 36a, electrode 136b, electrode 136c, source electrode or drain electrode 142a, source An opening is formed that reaches the electrode or drain electrode 142b, and the electrode is embedded in the opening. A conductive layer 148 is formed (see Figure 5(B)). The above opening is made by etching using a mask, etc. It can be formed by the following method. The mask can be formed by methods such as exposure using a photomask. Therefore, it is possible to form it. Etching methods include wet etching and dry etching. Either etching method can be used, but from the perspective of microfabrication, dry etching is recommended. The following is preferable. The conductive layer 148 is formed using a film deposition method such as PVD or CVD. This is possible. Materials that can be used to form the conductive layer 148 include molybdenum, cyanoacrylate, and cyanoacrylate. Tan, chromium, tantalum, tungsten, aluminum, copper, neodymium, scandium Examples include conductive materials, their alloys, and compounds (such as nitrides).

[0135] Specifically, for example, a thin titanium film is formed in the region including the opening by the PVD method, and then the CVD method is applied. After forming a thin titanium nitride film, a tungsten film is formed to fill the opening. The following method can be applied. Here, the titanium film formed by the PVD method is at the interface The oxide film is reduced, and the lower electrode (here, electrode 136a, electrode 136b, electrode 136c, so (Such as a source electrode or drain electrode 142a, a source electrode or drain electrode 142b, etc.) It has the function of reducing contact resistance. Furthermore, the titanium nitride formed thereafter is conductive. It has a barrier function that suppresses the diffusion of materials. It also has a barrier function using titanium or titanium nitride. After the film is formed, a copper film may be formed by a plating method.

[0136] After forming the conductive layer 148, the conductive layer 148 is formed using methods such as etching and CMP. By removing a portion of it and exposing the interlayer insulating layer 146, electrodes 150a, 150b, and 1 50c, electrode 150d, and electrode 150e are formed (see Figure 5(C)). Note that the above conductive layer Remove a portion of 148 to obtain electrodes 150a, 150b, 150c, 150d, and When forming the 150e pole, it is desirable to process the surface so that it is flat. Sea urchin, interlayer insulating layer 146, electrode 150a, electrode 150b, electrode 150c, electrode 150d, By flattening the surface of electrode 150e, a good electrode, wiring, and insulation can be achieved in subsequent processes. This makes it possible to form marginal layers, semiconductor layers, and the like.

[0137] Furthermore, an insulating layer 152 is formed, and electrodes 150a, 150b, and 1 An opening is formed that extends to electrode 50c, electrode 150d, and electrode 150e, and the material is embedded in the opening. After forming a conductive layer, a portion of the conductive layer is removed using methods such as etching or CMP. , exposing the insulating layer 152, electrode 154a, electrode 154b, electrode 154c, electrode 154 Form d (see Figure 5(D)). This step is the same as when forming electrode 150a, etc. Since there is some information available, I will omit the details.

[0138] When transistor 162 is fabricated using the method described above, the hydrogen concentration of the oxide semiconductor layer 140 The degree is 5x10 19 / cm3 The following applies, and the off-current of transistor 162 is 1 × 10⁻⁶. -13 It becomes A or less. In this way, the hydrogen concentration is sufficiently reduced and the purity is increased, and oxygen deficiency By applying an oxide semiconductor layer 140 with reduced defects caused by [unspecified factor], excellent properties can be achieved. A transistor 162 can be obtained. In addition, a transistor using a material other than an oxide semiconductor at the bottom can be obtained. An excellent transistor having a transistor 160 and an oxide semiconductor transistor 162 on top. It is possible to fabricate semiconductor devices with specific characteristics.

[0139] Furthermore, in oxide semiconductors, the Institute for Solid State Physics (IPSJ) has established DOS (density of state) and other properties. Although much research has been done, these studies have not focused on the localized levels within the energy gap themselves. It does not include the idea of ​​sufficiently reducing. In one aspect of the disclosed invention, the cause of the localized state is By removing water and hydrogen from the oxide semiconductor, a highly purified oxide semiconductor is produced. This is based on the idea of ​​significantly reducing the localized levels themselves. This makes it possible to manufacture extremely high-quality industrial products.

[0140] Furthermore, when removing hydrogen or water, oxygen may also be removed at the same time. Therefore, oxygen is supplied to the unbonded metals that occur due to oxygen deficiency, and localization due to oxygen vacancies. It is preferable to further increase the purity (to type i) of oxide semiconductors by reducing the number of existing energy levels. For example, an oxygen-rich oxide film is formed in close proximity to the channel-forming region, and at 200°C~ By performing heat treatment at temperatures of 400°C, typically around 250°C, the oxide film can be removed. It is possible to reduce localized energy levels caused by oxygen vacancies by supplying oxygen to oxide semiconductors. Furthermore, during the second heat treatment, the inert gas may be switched to an oxygen-containing gas. Following the heat treatment, cooling is performed in an oxygen atmosphere or an atmosphere from which hydrogen and water have been thoroughly removed. Through a certain process, it is also possible to supply oxygen to the oxide semiconductor.

[0141] The deterioration of oxide semiconductor properties is due to the shallow energy levels of 0.1-0.2 eV below the conduction band caused by excess hydrogen. These are thought to be caused by factors such as deep energy levels due to oxygen deficiency. Therefore, the technological concept of thoroughly removing hydrogen and supplying sufficient oxygen is correct. Ro.

[0142] In the disclosed invention, the oxide semiconductor is made highly pure, therefore the carrier density in the oxide semiconductor is It's small enough.

[0143] Furthermore, using the Fermi-Dirac distribution law at room temperature, the energy gap is 3.0 The intrinsic carrier density of oxide semiconductors, which is 5-3.15 eV, is 1 × 10⁻¹⁶. -7 / cm 3 next The true carrier density is 1.45 × 10⁻⁶ 10 / cm 3 It is much smaller than silicon. stomach.

[0144] Therefore, the number of holes, which are minority carriers, is extremely small, and IGFET (Insulated In the off state of a Gate Field Effect Transistor The leakage current is 100 aA / μm or less at room temperature, preferably 10 aA / μm or less, and Preferably, a level of 1 aA / μm or less can be achieved. The notation is 1 aA per 1 μm of transistor channel width (1 × 10⁻¹⁶). -18 The current in A) It indicates that something is flowing.

[0145] However, as a wide-bandgap semiconductor with an energy gap of 3 eV or more, SiC (3. Examples include 26eV (GaN) and 3.42eV (GaN), which can be used to obtain similar transistor characteristics. It is expected that this will be possible. However, these semiconductor materials require a process temperature of 1500°C or higher. Because it goes through this process, thinning is practically impossible. Also, three-dimensional on silicon integrated circuits Attempting to stack these materials is impossible due to the process temperature being too high. On the other hand, oxide semiconductors The conductor can be formed into a thin film by heated sputtering at room temperature to 400°C, and dehydration and dehydrogenation are possible. (removing hydrogen and water from the oxide semiconductor layer) and oxidation (supplying oxygen to the oxide semiconductor layer) Because it can supply (amount of heat) at 450-700°C, on top of a silicon integrated circuit It can form a three-dimensional layered structure.

[0146] Although oxide semiconductors are generally considered to be n-type, in one aspect of the disclosed invention, water and hydrogen By removing impurities such as these, and by supplying oxygen, which is a constituent element of oxide semiconductors, i To achieve mold formation. In this respect, unlike mold formation by adding impurities as with silicon, It can be said that it includes technological concepts that have not been seen before.

[0147] In this embodiment, the transistor 162 using an oxide semiconductor is a bottom gate type. Although one configuration has been described, the present invention is not limited thereto. Transistor 1 The 62 configuration may be either top-gate or dual-gate. A gate-type transistor is a transistor with two gates positioned above and below the channel region, separated by a gate insulating layer. This refers to a transistor that has a galvanic electrode layer.

[0148] <Conductivity mechanism of transistors using oxide semiconductors> Here, the conductivity mechanism of an oxide semiconductor transistor will be explained using Figures 6 to 9. It should be noted that the following explanation is merely one consideration, and the validity of the invention should not be denied based on it. I would like to add that it is not a thing.

[0149] Figure 6 shows a dual-gate type transistor (thin-film transistor) using an oxide semiconductor. This is a cross-sectional view. An oxide semiconductor layer is placed on the gate electrode (GE) via a gate insulating layer (GI). An OS (operating system) is provided, and a source electrode (S) and a drain electrode (D) are provided on it. An insulating layer is provided to cover the drain electrode (S) and the drain electrode (D).

[0150] Figure 7 shows the energy band diagram (schematic diagram) in the A-A' section of Figure 6. In diagram 7, the black circles (●) represent electrons, and the white circles (○) represent holes, with their respective charges (-q, +q). ) has.

[0151] A positive voltage (V) is applied to the drain electrode. D After applying >0), the dashed line shows the voltage applied to the gate electrode. If not (V G (=0), the solid line represents a positive voltage (V) across the gate electrode. G This shows the case where >0) is applied. If no voltage is applied to the gate electrode, the high potential barrier prevents oxide semiconductors from being released from the electrode. This indicates an off state where no carriers (electrons) are injected into the conductor, and no current flows. On the other hand, the gate... When a positive voltage is applied, the potential barrier decreases, and it enters an ON state where current flows.

[0152] Figure 8 shows a schematic diagram of the energy bands in the cross-section B-B' in Figure 6. Figure 8(A) shows a positive voltage (V) applied to the gate electrode (GE1). G The given state is >0. This indicates the ON state, where carriers (electrons) flow between the source electrode and the drain electrode. Furthermore, Figure 8(B) shows a negative voltage (V) applied to the gate electrode (GE1). G With <0) applied This indicates the off state (where minority carriers are not flowing).

[0153] Figure 9 shows the vacuum level and the work function of the metal (φ M ), the relationship of electron affinity (χ) of oxide semiconductors show.

[0154] At room temperature, electrons in metals are degenerate, and the Fermi level is located within the conduction band. On the other hand, Conventional oxide semiconductors are n-type, and their Fermi level (E F ) is at the center of the band gap The intrinsic Fermi level (E) is located there. i It is located away from the conduction band and closer to it. In semiconductor materials, it is known that some hydrogen acts as a donor, which is one of the factors that causes n-type semiconductors. Yes, they are.

[0155] In contrast, the oxide semiconductor according to one aspect of the disclosed invention uses hydrogen, which is a factor in n-type formation, as an acid By removing elements from oxide semiconductors, the oxide semiconductor contains as few elements other than the main components (impurity elements) as possible. By increasing the purity in such a way, it becomes true (Type i), or something that comes as close to true as possible. That is, rather than adding impurity elements to make it i-type, impurities such as hydrogen and water are extremely... By removing the force, it is possible to obtain a highly purified type i (intrinsic semiconductor) or something close to it. This is a characteristic feature. As a result, the Fermi level (E f ) is the true Fermi level (E i ) It can be expressed as a degree.

[0156] Band gap (E) of oxide semiconductors g If the voltage is 3.15 eV, then the electron affinity (χ) is It is said to be 4.3 eV. Work done by titanium (Ti) that makes up the source electrode and drain electrode. The function is approximately equal to the electron affinity (χ) of the oxide semiconductor. In this case, it is a metal-oxide semiconductor. At the interface, no Schottky-type barrier is formed for electrons.

[0157] At this time, as shown in Figure 8(A), electrons are in the gate insulating layer and the highly purified oxide semiconductor. It moves near the interface (the lowest, most energetically stable part of the oxide semiconductor).

[0158] Furthermore, as shown in Figure 8(B), when a negative potential is applied to the gate electrode (GE1), a decimal Since the number of holes, which act as carriers, is virtually zero, the current will be extremely close to zero.

[0159] In this way, high purity is achieved by minimizing the presence of elements other than the main components of oxide semiconductors (impurity elements). By degree conversion, it becomes intrinsic (type i) or substantially intrinsic, thus the gate insulating layer The interfacial properties with the semiconductor become apparent. Therefore, the gate insulating layer has a good interface with the oxide semiconductor. The ability to form such a thing is required. Specifically, for example, power supply frequencies in the VHF band to microwave band. Insulating layers fabricated by CVD using high-density plasma generated in large quantities, and sputtering It is preferable to use an insulating layer manufactured by law.

[0160] To improve the purity of the oxide semiconductor while ensuring a good interface between the oxide semiconductor and the gate insulating layer. By doing so, for example, the channel width (W) of the transistor becomes 1 × 10 4 μm, channel length If (L) is 3 μm, then 10 -13Off-current of less than A, sub-voltage of 0.1V / dec. A threshold swing value (S value) (gate insulating layer thickness: 100 nm) can be achieved.

[0161] In this way, the oxide semiconductor is processed to minimize the presence of elements other than its main component (impurity elements). Purification can improve the operation of transistors.

[0162] <Career density> The technical concept of the disclosed invention is to sufficiently reduce the carrier concentration in the oxide semiconductor layer. The aim is to make it as close to true (type i) as possible. Below is how to calculate the carrier concentration. The carrier concentrations measured will be explained with reference to Figures 10 and 11. .

[0163] First, let's briefly explain how to determine the carrier concentration. The carrier concentration is calculated using MOS capacity. This can be determined by fabricating a MOS capacitor and evaluating the results of the CV measurement (CV characteristics). This is possible.

[0164] More specifically, the relationship between the gate voltage Vg and capacitance C of a MOS capacitor is plotted as C. -V characteristics are obtained, and from these CV characteristics, the gate voltage Vg and (1 / C) 2 The relationship is represented by A rough sample is obtained, and in the graph, the (1 / C) in the weak inversion region is... 2 Find the derivative of and Substituting the fractional values ​​into equation (1), the carrier concentration N d The magnitude of can be determined. In (1), e is the elementary charge, ε0 is the permittivity of vacuum, and ε is the relative permittivity of the oxide semiconductor. ru.

[0165]

number

[0166] Next, we will explain the carrier concentration that was actually measured using the method described above. A titanium film is formed on a lath substrate to a thickness of 300 nm, and a titanium nitride film is formed on the titanium film. Formed with a thickness of nm, an In-Ga-Zn-O based oxide semiconductor is used on the titanium nitride film. An oxide semiconductor layer is formed with a thickness of 2 μm, and a silver film is applied on the oxide semiconductor layer with a thickness of 300 nm. A sample (MOS capacitor) formed using the following was used. The oxide semiconductor layer consisted of In, Ga, and a target for deposition of oxide semiconductor films containing Zn (In2O3:Ga2O3:ZnO=1 It was formed by a sputtering method using a 1:1 [molar ratio]. The atmosphere for forming the body layer is a mixed atmosphere of argon and oxygen (flow ratio: Ar:O2 = 30 (sc) The value was set to 15 (sccm).

[0167] Figure 10 shows the CV characteristics, and Figure 11 shows Vg and (1 / C). 2 The relationship between each is shown in the figure. (1 / C) in the weak inversion region of 11 2 The carrier obtained from the derivative of using equation (1) The concentration is 6.0 × 10 10 / cm 3 That was the case.

[0168] Thus, an i-type or substantially i-type oxide semiconductor (for example, with a carrier concentration of 1 x 10 12 / cm 3 The following is preferable: 1 × 10 11 / cm 3 By using the following, It is possible to obtain transistors with extremely excellent off-current characteristics.

[0169] <Variation> Figures 12 to 15 show modified configurations of semiconductor devices. In the following description, these are modified configurations. Next, I will explain a configuration of transistor 162 that differs from the above. The configuration of the Zista 160 is the same as described above.

[0170] Figure 12 shows a gate electrode 136d located beneath an oxide semiconductor layer 140, and a source electrode or The drain electrode 142a, or the source electrode or drain electrode 142b, is located in the oxide semiconductor layer 1 The transistor 162 has a configuration in which it is in contact with the oxide semiconductor layer 140 on the lower surface of 40. An example of a semiconductor device is shown. Note that the planar structure can be modified as appropriate to correspond to the cross-section. Here, we will only show the cross-section.

[0171] A major difference between the configuration shown in Figure 12 and the configuration shown in Figure 2 is the source electrode or drain electrode. The contact between the electrode 142a, or the source electrode or drain electrode 142b, and the oxide semiconductor layer 140. There is a continuation position. In other words, in the configuration shown in Figure 2, the upper surface of the oxide semiconductor layer 140 is so Contact with the source electrode or drain electrode 142a, or the source electrode or drain electrode 142b In contrast, in the configuration shown in Figure 12, the lower surface of the oxide semiconductor layer 140 is the source electrode. Alternatively, it contacts the drain electrode 142a, or the source electrode or drain electrode 142b. As a result of this difference in contact, the arrangement of other electrodes, insulating layers, etc. will be different. The details of each component are the same as in Figure 2.

[0172] Specifically, the semiconductor device has a gate electrode 136d provided on the interlayer insulating layer 128, and A gate insulating layer 138 provided on the gate electrode 136d, and a gate insulating layer 138 provided on the gate insulating layer 138 Source electrode or drain electrode 142a, source electrode or drain electrode 142b and source electrode or drain electrode 142a, source electrode or drain electrode 142b It has an oxide semiconductor layer 140 in contact with the upper surface.

[0173] Here, the gate electrode 136d is embedded in the insulating layer 132 formed on the interlayer insulating layer 128. It is provided so as to be inserted. Also, similar to the gate electrode 136d, the source electrode or Electrode 136a is in contact with drain electrode 130a, and is connected to source electrode or drain electrode 130b Electrode 136b is formed in contact with electrode 130c, and electrode 136c is formed in contact with electrode 130c. ru.

[0174] Furthermore, a protective layer is placed on top of the transistor 162 so as to be in contact with a portion of the oxide semiconductor layer 140. An insulating layer 144 is provided, and an interlayer insulating layer 146 is provided on the protective insulating layer 144. Here, the protective insulating layer 144 and the interlayer insulating layer 146 have a source electrode or drain. An opening is provided that reaches the source electrode 142a, or the drain electrode 142b. Furthermore, through the opening, electrodes 150d and 150e are connected to the source electrode or drain electrode. It is formed in contact with electrode 142a, source electrode or drain electrode 142b. Similar to pole 150d and electrode 150e, the gate insulating layer 138, protective insulating layer 144, and interlayer insulating layer Through the opening provided in layer 146, electrodes 136a, 136b, and 136c are in contact. Electrodes 150a, 150b, and 150c are formed.

[0175] Furthermore, an insulating layer 152 is provided on the interlayer insulating layer 146, and embedded in the insulating layer 152. Electrodes 154a, 154b, 154c, and 154d are provided so as to be inserted. Here, electrode 154a is in contact with electrode 150a, and electrode 154b is in contact with electrode 150 It is in contact with b, and electrode 154c is in contact with electrode 150c and electrode 150d, and electrode 1 Electrode 54d is in contact with electrode 150e.

[0176] Figure 13 shows an example of a configuration having a gate electrode 136d on an oxide semiconductor layer 140. Here, Figure 13(A) shows the source electrode or drain electrode 142a, or the source electrode or drain The rain electrode 142b is located on the lower surface of the oxide semiconductor layer 140. This is an example of a configuration in which the source electrode or drain electrode 142a is in contact with the following: Figure 13(B) shows the source electrode or drain electrode 142a, The source electrode or drain electrode 142b is acid on the upper surface of the oxide semiconductor layer 140. This is an example of a configuration in which the ionized semiconductor layer 140 is in contact with the semiconductor layer.

[0177] The main difference between the configurations shown in Figures 2 and 12 and the configuration shown in Figure 13 is the oxide semiconductor layer 140. The point is that it has a gate electrode 136d on top. Also, the configuration shown in Figure 13(A) and Figure 13(B) The major difference in the configuration shown is the source electrode or drain electrode 142a, or the source electrode Alternatively, the drain electrode 142b is either on the lower or upper surface of the oxide semiconductor layer 140. The point is whether or not contact occurs in that situation. And due to these differences, other electricity The arrangement of electrodes, insulating layers, etc., differs. Details of each component are the same as in Figure 2, etc. That is the case.

[0178] Specifically, in Figure 13(A), the semiconductor device has a source provided on the interlayer insulating layer 128. Electrode or drain electrode 142a, source electrode or drain electrode 142b, and source electrode Contact the upper surface of the electrode or drain electrode 142a, or the source electrode or drain electrode 142b. An oxide semiconductor layer 140 and a gate insulating layer 138 provided on the oxide semiconductor layer 140 And the gate electrode 136d in the region overlapping with the oxide semiconductor layer 140 on the gate insulating layer 138. It has the following characteristics.

[0179] Furthermore, in Figure 13(B), the oxide semiconductor layer 140 provided on the interlayer insulating layer 128 and acid Source electrode or drain electrode provided so as to be in contact with the upper surface of the ionized semiconductor layer 140 142a, source electrode or drain electrode 142b, oxide semiconductor layer 140, source electrode On the electrode or drain electrode 142a and the source electrode or drain electrode 142b The gate insulating layer 138 is superimposed on the oxide semiconductor layer 140 on the gate insulating layer 138. It has a gate electrode 136d in the region.

[0180] In addition, in the configuration shown in Figure 13, compared to the configuration shown in Figure 2, etc., some components can be omitted. There are combinations (for example, electrode 150a and electrode 154a). In this case, the manufacturing process is simplified. This also provides the secondary effect of... It goes without saying that some components can be omitted.

[0181] Figure 14 shows the case where the device size is relatively large, with a gauge below the oxide semiconductor layer 140. This is an example of a configuration having an electrode 136d. In this case, the flatness of the surface and coverage Since the requirements are not particularly stringent, it is necessary to form the structure so that wiring, electrodes, etc., are embedded within the insulating layer. There is no such thing. For example, by performing patterning after the formation of the conductive layer, gate electrode 136d etc. It is possible to form this. Although not shown in the diagram here, regarding transistor 160 However, it is possible to manufacture them in the same way.

[0182] The main difference between the configuration shown in Figure 14(A) and the configuration shown in Figure 14(B) is the source electrode or The drain electrode 142a, or the source electrode or drain electrode 142b, is located in the oxide semiconductor layer 1 The point is whether contact occurs on the lower or upper surface of 40. These differences result in variations in the arrangement of other electrodes, insulating layers, and other components. The details of each component are the same as in Figure 2, etc.

[0183] Specifically, in Figure 14(A), the semiconductor device has a gate provided on the interlayer insulating layer 128. Electrode 136d, gate insulating layer 138 provided on gate electrode 136d, gate insulating A source electrode or drain electrode 142a is provided on layer 138, source electrode or drain Rain electrode 142b and source electrode or drain electrode 142a, source electrode or drain It has an oxide semiconductor layer 140 in contact with the upper surface of the in electrode 142b.

[0184] Furthermore, in Figure 14(B), the gate electrode 136d provided on the interlayer insulating layer 128 and the gate A gate insulating layer 138 provided on the electrode 136d, and the gate electrode on the gate insulating layer 138 An oxide semiconductor layer 140 is provided in the region overlapping with pole 136d, and the oxide semiconductor layer 140 Source electrode or drain electrode 142a provided so as to be in contact with the upper surface, source electrode It has an electrode or drain electrode 142b.

[0185] Furthermore, in the configuration shown in Figure 14, some components are omitted compared to the configuration shown in Figure 2, etc. This can sometimes be the case. In this case as well, the benefit of simplifying the manufacturing process can be obtained.

[0186] Figure 15 shows the case where the device size is relatively large, with a gauge on the oxide semiconductor layer 140. This is an example of a configuration having an electrode 136d. In this case as well, surface flatness and coverage Since the requirements are not particularly strict, the wiring and electrodes are formed so that they are embedded in the insulating layer. It is not necessary. For example, by performing patterning after the formation of the conductive layer, the gate electrode 136d It is possible to form such as the above. Although not shown in the diagram here, transistor 160 It is possible to manufacture them in the same way.

[0187] The main difference between the configuration shown in Figure 15(A) and the configuration shown in Figure 15(B) is the source electrode or The drain electrode 142a, or the source electrode or drain electrode 142b, is located in the oxide semiconductor layer 1 The point is whether contact occurs on the lower or upper surface of 40. These differences result in variations in the arrangement of other electrodes, insulating layers, and other components. The details of each component are the same as in Figure 2, etc.

[0188] Specifically, in Figure 15(A), the semiconductor device has a source provided on the interlayer insulating layer 128. Electrode or drain electrode 142a, source electrode or drain electrode 142b, and source electrode Contact the upper surface of the electrode or drain electrode 142a, or the source electrode or drain electrode 142b. The oxide semiconductor layer 140, the source electrode or drain electrode 142a, and the source electrode The drain electrode 142b and the gate insulating layer 138 provided on the oxide semiconductor layer 140, A gate electrode 1 is provided in the region that overlaps with the oxide semiconductor layer 140 on the gate insulating layer 138. It has 36d and .

[0189] Furthermore, in Figure 15(B), the semiconductor device is an oxide semiconductor provided on the interlayer insulating layer 128. The layer 140 and the source electrode provided so as to be in contact with the upper surface of the oxide semiconductor layer 140 The drain electrode 142a, the source electrode or drain electrode 142b, and the source electrode or Drain electrode 142a, source electrode or drain electrode 142b, oxide semiconductor layer 140 A gate insulating layer 138 provided on top, and an oxide semiconductor layer 140 on the gate insulating layer 138 It has a gate electrode 136d provided in the overlapping region.

[0190] Furthermore, in the configuration shown in Figure 15, compared to the configuration shown in Figure 2, etc., some components can be omitted. In some cases, this is possible. In this case as well, the benefit of simplifying the manufacturing process can be obtained.

[0191] As described above, one aspect of the disclosed invention realizes a semiconductor device with a new configuration. In this embodiment, transistors 160 and 162 are stacked to form the transistor. Although an example has been given, the configuration of the semiconductor device is not limited to this. In this configuration, the channel length directions of transistors 160 and 162 are perpendicular to each other. I have explained an example, but the positional relationship between transistor 160 and transistor 162 is not the same. It is not limited. Furthermore, by superimposing transistor 160 and transistor 162 It is permissible to set one up.

[0192] Furthermore, in this embodiment, for the sake of ease of understanding, the semiconductor device is the smallest memory unit (1 bit). As explained above, the configuration of semiconductor devices is not limited to this. Multiple semiconductor devices can be used. By connecting them appropriately, it is also possible to configure more advanced semiconductor devices. For example, the above semiconductor device By using multiple units, it is possible to configure NAND and NOR type semiconductor devices. The configuration is not limited to Figure 1 and can be changed as appropriate.

[0193] The semiconductor device according to this embodiment is extremely efficient due to the low off-current characteristics of the transistor 162. It is possible to retain information for a long period of time. In other words, it is required for DRAM, etc. Refresh operations are unnecessary, and power consumption can be reduced. Furthermore, it is virtually non-volatile. It can be used as a semiconductor device that generates electricity.

[0194] Furthermore, information is written through the switching operation of transistor 162, It does not require high voltage and there are no issues with component degradation. Furthermore, the transistor can be turned on or off. Because information is written and erased using this method, high-speed operation can be easily achieved. Furthermore, it eliminates the need for operations to erase information required in flash memory, etc. There is also that advantage.

[0195] Furthermore, transistors using materials other than oxide semiconductors are capable of sufficiently high-speed operation, By using this method, it is possible to read the contents of memory at high speed.

[0196] The configurations and methods shown in this embodiment may be combined with the configurations and methods shown in other embodiments as appropriate. They can be used together.

[0197] (Embodiment 2) This embodiment describes the circuit configuration and operation of a semiconductor device according to one aspect of the present invention. do.

[0198] Figure 16 shows an example of a circuit diagram of a memory element (hereinafter also referred to as a memory cell) in a semiconductor device. The memory cell 200 shown in Figure 16 is a multi-level type, and has a source line SL and a bit line BL. , first signal line S1, second signal line S2, word line WL, transistor 201, tra It consists of a transistor 202, a transistor 203, and a capacitive element 205. The transistor 201 and transistor 203 are formed using materials other than oxide semiconductors. Transistor 202 is formed using an oxide semiconductor.

[0199] Here, the gate electrode of transistor 201 and the source electrode or dot of transistor 202 It is electrically connected to one of the rain electrodes. Also, the source wire SL and the transistor The source electrode of transistor 201 is electrically connected to the drain electrode of transistor 201, and The source electrode of the transistor 203 is electrically connected. And the bit line BL and The drain electrode of transistor 203 is electrically connected to the first signal line S1, and the transistor The source electrode or drain electrode of the converter 202 is electrically connected to the other, and the second signal Line S2 and the gate electrode of transistor 202 are electrically connected to the word line WL. It is electrically connected to the gate electrode of transistor 203. Also, capacitive element 205 One electrode of the transistor, the gate electrode of transistor 201, and the source electrode of transistor 202. Alternatively, one of the drain electrodes is electrically connected, and the other electrode of the capacitive element 205 is connected to, A predetermined potential is applied. This predetermined potential is, for example, GND (ground).

[0200] Next, we will explain the operation of the memory cell 200 shown in Figure 16. We will explain the case of a quaternary type. The four states of memory cell 200 are data "00b", "01b", "10b", and "11b". "Then, the potentials of node A at that time are V00, V01, V10, V11 (V00 <V01<V10<V11)とする。

[0201] When writing to memory cell 200, set source line SL to 0[V] and word line WL to 0[V] Let V], bit line BL be 0[V], and second signal line S2 be 2[V]. The data "00b" When writing, set the first signal line S1 to V00[V]. Write the data "01b". In this case, the first signal line S1 is set to V01[V]. When writing data "10b" The first signal line S1 is set to V10[V]. When writing data "11b", the first signal Let line S1 be V11[V]. At this time, transistor 203 is in the off state, T202 will be in the ON state. Note that when writing is complete, the potential of the first signal line S1 will be Before the change occurs, set the second signal line S2 to 0[V] and turn off transistor 202. .

[0202] As a result, after writing data "00b", "01b", "10b", and "11b", The potentials of the node connected to the gate electrode of the transistor 201 (hereinafter referred to as node A) are The voltages are approximately V00[V], V01[V], V10[V], and V11[V]. Node A A charge corresponding to the potential of the first signal line S1 is accumulated, but when transistor 202 is off-voltage... Because the current is extremely small, or practically zero, the gate electrode of transistor 201 The electrical potential is maintained for an extended period.

[0203] To read out memory cell 200, first precharge the bit line BL, and then Vp Let c[V] be the source line SL, and let Vs_read[V] be the word line WL. Let the voltage be 2[V], the second signal line S2 be 0[V], and the first signal line S1 be 0[V]. In this case, Transistor 203 is in the ON state, and transistor 202 is in the OFF state. Note that the potential Vp c should be lower than V00-Vth. Vs_read should be higher than V11-Vth.

[0204] As a result, current flows from the source line SL to the bit line BL, and the bit line BL is (the current at node A). It is charged to a potential represented by (position) - (threshold voltage Vth of transistor 201). As a result, the bit line BL potential is for data "00b", "01b", "10b", "11b" In contrast, V00-Vth, V01-Vth, V10-Vth, and V11-Vth are respectively Yes. The readout circuit connected to the bit line BL detects the data "0" due to these potential differences. It is possible to read "0b", "01b", "10b", and "11b".

[0205] Figure 17 shows a block of a semiconductor device according to one embodiment of the present invention having an m × n bit memory capacity. The circuit diagram is shown.

[0206] A semiconductor device according to one aspect of the present invention comprises m word lines WL and a second signal line S2, and n lines Bit line BL, first signal line S1, and source line SL, and multiple memory cells 200(1,1) ~200(m, n) in a matrix with m rows and n columns (m and n are natural numbers) The arranged memory cell array 210, the read circuit 211, and the first signal line drive circuit 21 2, and peripheral circuits such as the drive circuit 213 for the second signal line and word line, and the potential generation circuit 214. It is composed of paths. Other peripheral circuits, such as refresh circuits, may also be provided. stomach.

[0207] Consider each memory cell, for example, memory cell 200(i, j). Here, i is between 1 and m. An integer (where j is an integer between 1 and n). Memory cell 200(i,j) is connected to the bit line BL(j ), first signal line S1(j), source line SL(j), word line WL(i), and second signal line S Each is connected to 2(i). Also connected to bit lines BL(1)~BL(n) and source Lines SL(1) to SL(n) are connected to the readout circuit 211, and the first signal lines S1(1) to S1(n) are connected to the readout circuit 211. ) is connected to the first signal line drive circuit 212, the word lines WL(1)~WL(m) and the second signal line S2 (1)~S2(m) are connected to the drive circuit 213 for the second signal line and word line, respectively. ru.

[0208] Figure 18 shows an example of the drive circuit 213 for the second signal line and word line. The drive circuit 213 for the second signal line S has a decoder 215, and the decoder 215 drives the second signal line S It is connected to the word line WL and the second signal line S2 via a switch. The word line WL is connected to GND (ground potential) via a switch. The signal is controlled by either a read enable signal (RE signal) or a write enable signal (WE signal). It is controlled in this way. The decoder 215 receives an external address signal ADR.

[0209] When the address signal ADR is input to the drive circuit 213 for the second signal line and word line, The row specified by S (hereinafter also referred to as the selected row) is asserted (activated), and all other rows (hereinafter The lines below (also referred to as unselected lines) will be deasserted (deactivated). Also, the word lines WL will be RE When the signal is asserted, it is connected to the output of decoder 215, and the RE signal is deasserted. It is connected to GND. The second signal line S2 is connected to decoder 215 when the WE signal is asserted. It is connected to the output and connected to GND when the WE signal is deasserted.

[0210] Figure 19 shows an example of the first signal line drive circuit 212. The first signal line drive circuit 212 is... It has a chipplexer (MUX1). The multiplexer (MUX1) has input data DI, and The write potentials V00, V01, V10, and V11 are input. Multiplexer (MUX The output terminal of 1) is connected to the first signal line S1 via a switch. Line S1 is connected to GND via a switch. The above switch is a light enable It is controlled by the WE signal.

[0211] When DI is input to the first signal line drive circuit 212, the multiplexer (MUX1) will... Depending on the value, select one of the following write potentials Vw: V00, V01, V10, or V11. The behavior of the multiplexer (MUX1) is shown in Table 1. When the WE signal is asserted, The selected write potential Vw is applied to the first signal line S1, and the WE signal is deasserted. Then, 0[V] is applied to the first signal line S1 (the first signal line S1 is connected to GND). ).

[0212] [Table 1]

[0213] Figure 20 shows an example of the readout circuit 211. The readout circuit 211 has multiple sense units. It has a switch circuit and a logic circuit 229, etc. One input terminal of each sense amplifier circuit is a switch The bit line BL is connected via the switch, or Vpc is applied. One of the reference potentials Vref0, Vref1, or Vref2 is input to the input terminal of the other party. Also, the output terminals of each sense amplifier circuit are connected to the input terminals of the logic circuit 229. The switch is controlled by a read enable signal (RE signal).

[0214] By setting the values of the reference potentials Vref0, Vref1, and Vref2 to satisfy V00 - Vth < Vref0 < V01 - Vth < Vref1 < V10 - Vth < Vref2 < V11 - Vth, the state of the memory cell can be read as a 3-bit digital signal. For example, in the case of data "00b", the potential of the bit line BL is V00 - Vth. Since this value is smaller than any of the reference potentials Vref0, Vref1, and Vref2, the outputs SA_OUT0, SA_OUT1, and SA_OUT2 of the sense amplifier circuit are all "0", "0", "0". Similarly, in the case of data "01b", the potential of the bit line BL is V01 - Vth, and the outputs SA_OUT0, SA_OUT1, and SA_OUT2 of the sense amplifier circuit are "1", "0", "0" respectively. In the case of data "10b", the potential of the bit line BL is V10 - Vth, and the outputs SA_OUT0, SA_OUT1, and SA_OUT2 of the sense amplifier circuit are "1", "1", "0" respectively. In the case of data "11b", the potential of the bit line BL is V11 - Vth, and the outputs SA_OUT0, SA_OUT1, and SA_OUT2 of the sense amplifier circuit are "1", "1", "1" respectively. After that, 2-bit data DO is generated using the logic circuit 229 represented by the logic value table shown in Table 2 and output from the read circuit 211.

[0215] ​​​​​​​​ [Table 2]

[0216] In the illustrated readout circuit 211, when the RE signal is deasserted, the source line SL When connected to GND, 0[V] is applied to the source line SL, and the bit line BL and A potential Vpc [V] is applied to the terminal of the sense amplifier circuit connected to the bit line BL. When the E signal is asserted, Vs_read[V] is applied to the source line SL, and the result As a result, the bit line BL is charged with a potential that reflects the data. Then, the readout described above This will be done. Note that the potential Vpc will be lower than V00-Vth. Vs_read will be V11- Make it higher than Vth.

[0217] Note that the "potential of bit line BL" used for comparison during reading is determined via a switch. The potential of the node at the input terminal of the sense amplifier connected to line BL is included. Furthermore, the potentials compared in the readout circuit 211 are strictly identical to the potential of the bit line BL. It's not necessary.

[0218] Figure 21 shows an example of a potential generation circuit 214. In the potential generation circuit 214, the desired potential is generated. It can be generated by dividing the resistance between Vdd and GND. Then, the generated potential is The output is routed through the analog buffer 220. In this way, the write potentials V00, V0 1, V10, V11, and reference potentials Vref0, Vref1, Vref2 are generated. Note that in the diagram, V00 <Vref0<V01<Vref1<V10<Vref2<V11 The configuration shown is as described above, but the relationship between potentials is not limited to this. Resistors and reference nodes can be used. By adjusting it, the necessary potential can be generated as needed. Also, V00, V01, V10, V11 and Vref0, Vref1, Vref2 are generated using a separate potential generation circuit. You can do that.

[0219] The potential generation circuit 214 is supplied with a potential boosted by the boost circuit instead of the power supply potential Vdd. This is also good. By supplying the output of the boost circuit to the potential generation circuit, the absolute value of the potential difference can be increased. This is because it becomes possible to do so, and thus a higher potential can be supplied.

[0220] Furthermore, even when the power supply potential Vdd is supplied directly to the potential generation circuit, the potential is divided into many different potentials. It is possible to divide it. However, in this case, it becomes difficult to distinguish between adjacent potentials. This would lead to an increase in write and read errors. In this regard, the output of the boost circuit By supplying it to the potential generation circuit, it becomes possible to increase the absolute value of the potential difference. Therefore, even if the number of divisions is increased, a sufficient difference in potential between adjacent points can be ensured.

[0221] This allows for the storage of a single memory cell without increasing write or read errors. It is possible to increase the capacity.

[0222] Figure 22(A) shows a boost circuit 219 as an example of a boost circuit that performs a four-stage boost. In (A), the power supply potential Vdd is supplied to the input terminal of the first diode 402. The output terminal of the first diode 402 is connected to the input terminal of the second diode 404 and the first capacitor One terminal of the element 412 is connected. Similarly, the output terminal of the second diode 404 is connected. The input terminal of the third diode 406 and one terminal of the second capacitive element 414 are connected to the child. It is done. The same applies below, so a detailed explanation will be omitted, but the output terminal of the nth diode It can also be said that one terminal of the nth capacitive element is connected to the child (n: a natural number). Furthermore, the output of the fifth diode 410 becomes the output Vout of the boost circuit 219.

[0223] Furthermore, the other terminal of the first capacitive element 412 and the other terminal of the third capacitive element 416 are A clock signal CLK is input. Also, the other terminal and the 4 The other terminal of the capacitive element 418 is input to the inverting clock signal CLKB. The other terminal of the 2k-1 capacitance element is input to the clock signal CLK, and the 2k capacitance The other terminal of the element is input to an inverting clock signal CLKB (k: a natural number). However, the other terminal of the final stage capacitive element is input to the ground potential (GND).

[0224] When the clock signal CLK is High, that is, when the inverted clock signal CLKB is Low In some cases, the first capacitive element 412 and the third capacitive element 416 are charged, and the clock The potentials of nodes N1 and N3, which are capacitively coupled to the signal CLK, are lowered by a predetermined voltage. It can be raised. Meanwhile, node N2 and node are capacitively coupled with the inverted clock signal CLKB. The potential of N4 is lowered by a predetermined voltage.

[0225] As a result, the first diode 402, the third diode 406, and the fifth diode 41 Charge moves through 0, raising the potentials of nodes N2 and N4 to predetermined values. It is possible.

[0226] Next, when the clock signal CLK goes low and the inverted clock signal CLKB goes high... The potentials of nodes N2 and N4 are further increased. Meanwhile, the potentials of nodes N1 and N4 are raised. The potentials at nodes N3 and N5 are lowered by a predetermined voltage.

[0227] As a result, charge moves through the second diode 404 and the fourth diode 408. As a result, the potentials of nodes N3 and N5 will be raised to a predetermined level. Thus, the potential at each node is V N5 >V N4(CLKB=High) >V N3(CLK=High) >V N2(CLKB=High) >V N1(CLK=Hi gh) The voltage is boosted when it reaches >Vdd. The configuration of the boost circuit 219 is 4 This is not limited to devices that perform voltage boosting in stages. The number of boosting stages can be changed as appropriate.

[0228] Furthermore, the output Vout of the boost circuit 219 is greatly affected by variations in the diode characteristics. For example, a diode connects the source electrode and gate electrode of a transistor. This can be achieved, but in this case, it will be affected by variations in the transistor threshold. .

[0229] To precisely control the output Vout, a configuration that feeds back the output Vout is adopted. You can use it. Figure 22(B) shows the circuit configuration when the output Vout is fed back. Here is an example. The boost circuit 219 in Figure 22(B) is the same as the boost circuit 219 shown in Figure 22(A). It is equivalent to that.

[0230] The output terminal of the boost circuit 219 is connected to one of the input terminals of the sense amplifier circuit via resistor R1. They are connected. Also, one input terminal of the sense amplifier circuit is connected to ground via resistor R2. It is. That is, the potential V1 corresponding to the output Vout is input to one input terminal of the sense amplifier circuit. Here, V1 = Vout·R2 / (R1+R2). It is.

[0231] Also, the reference potential Vref is input to the other input terminal of the sense amplifier circuit. That is, in the sense amplifier circuit, V1 and Vref are compared. The output terminal of the sense amplifier circuit is connected to the control circuit. Also, the clock signal CLK0 is input to the control circuit. The control circuit outputs the clock signal CLK and the inverted clock signal CLKB to the boost circuit 219 according to the output from the sense amplifier circuit. That is, in the sense amplifier circuit, V1 and Vref are compared. The output terminal of the sense amplifier circuit is connected to the control circuit. Also, the clock signal CLK0 is input to the control circuit. The control circuit outputs the clock signal CLK and the inverted clock signal CLKB to the boost circuit 219 according to the output from the sense amplifier circuit. The output terminal of the sense amplifier circuit is connected to the control circuit. Also, the clock signal CLK0 is input to the control circuit. The control circuit outputs the clock signal CLK and the inverted clock signal CLKB to the boost circuit 219 according to the output from the sense amplifier circuit. The output terminal of the sense amplifier circuit is connected to the control circuit. Also, the clock signal CLK0 is input to the control circuit. The control circuit outputs the clock signal CLK and the inverted clock signal CLKB to the boost circuit 219 according to the output from the sense amplifier circuit. The output terminal of the sense amplifier circuit is connected to the control circuit. Also, the clock signal CLK0 is input to the control circuit. The control circuit outputs the clock signal CLK and the inverted clock signal CLKB to the boost circuit 219 according to the output from the sense amplifier circuit.

[0232] When V1 > Vref, the output sig_1 of the sense amplifier circuit is asserted, and the control circuit stops supplying the clock signal CLK and the inverted clock signal CLKB to the boost circuit 219. As a result, the boosting operation stops, so the rise of the potential Vout stops. Then, as the circuit connected to the output of the boost circuit 219 consumes power, the potential Vout gradually decreases. When V1 > Vref, the output sig_1 of the sense amplifier circuit is asserted, and the control circuit stops supplying the clock signal CLK and the inverted clock signal CLKB to the boost circuit 219. As a result, the boosting operation stops, so the rise of the potential Vout stops. Then, as the circuit connected to the output of the boost circuit 219 consumes power, the potential Vout gradually decreases. When V1 > Vref, the output sig_1 of the sense amplifier circuit is asserted, and the control circuit stops supplying the clock signal CLK and the inverted clock signal CLKB to the boost circuit 219. As a result, the boosting operation stops, so the rise of the potential Vout stops. Then, as the circuit connected to the output of the boost circuit 219 consumes power, the potential Vout gradually decreases. When V1 > Vref, the output sig_1 of the sense amplifier circuit is asserted, and the control circuit stops supplying the clock signal CLK and the inverted clock signal CLKB to the boost circuit 219. As a result, the boosting operation stops, so the rise of the potential Vout stops. Then, as the circuit connected to the output of the boost circuit 219 consumes power, the potential Vout gradually decreases. When V1 > Vref, the output sig_1 of the sense amplifier circuit is asserted, and the control circuit stops supplying the clock signal CLK and the inverted clock signal CLKB to the boost circuit 219. As a result, the boosting operation stops, so the rise of the potential Vout stops. Then, as the circuit connected to the output of the boost circuit 219 consumes power, the potential Vout gradually decreases.

[0233] When V1 < Vref, the output sig_1 of the sense amplifier circuit is de-asserted, and the control circuit starts supplying the clock signal CLK and the inverted clock signal CLKB to the boost circuit 219. As a result, the boosting operation is performed, so the potential Vout gradually rises. When V1 < Vref, the output sig_1 of the sense amplifier circuit is de-asserted, and the control circuit starts supplying the clock signal CLK and the inverted clock signal CLKB to the boost circuit 219. As a result, the boosting operation is performed, so the potential Vout gradually rises. When V1 < Vref, the output sig_1 of the sense amplifier circuit is de-asserted, and the control circuit starts supplying the clock signal CLK and the inverted clock signal CLKB to the boost circuit 219. As a result, the boosting operation is performed, so the potential Vout gradually rises.

[0234] In this way, by feeding back the output potential Vout of the boost circuit 219, it is possible to keep the output potential Vout of the boost circuit 219 at a constant value. This configuration is a diode In this way, by feeding back the output potential Vout of the boost circuit 219, it is possible to keep the output potential Vout of the boost circuit 219 at a constant value. This configuration is a diode ​This is particularly effective when there are variations. Also, it is effective when generating a predetermined potential based on the reference potential Vref. In the boost circuit 219, it is also possible to generate a plurality of potentials by using a plurality of different reference potentials. By supplying the output of the boost circuit to the potential generation circuit, the absolute value of the potential difference can be increased. Therefore, it is possible to generate a higher potential without changing the minimum unit of the potential difference. That is, it is possible to increase the storage capacity of one memory cell. Figure 23 shows a differential sense amplifier as an example of a sense amplifier circuit. The differential sense amplifier has input terminals Vin(+) and Vin(-) and an output terminal Vout, and amplifies the difference between Vin(+) and Vin(-). If Vin(+) > Vin(-), Vout is generally a High output, and if Vin(+) < Vin(-), Vout is generally a Low output.

[0235]

[0236]

[0237] Figure 24 shows a latch-type sense amplifier as an example of a sense amplifier circuit. The latch-type sense amplifier has input / output terminals V1 and V2 and input terminals for control signals Sp and Sn. First, the signal Sp is set to High, the signal Sn is set to Low, and the power supply is cut off. Then, potentials for comparison are applied to V1 and V2. After that, when the signal Sp is set to Low, the signal Sn is set to High, and the power supply is supplied, if the potential before power supply is V1 > V2, V1 is a High output, V2 is a Low output, and if V1 < V2, V1 is a Low output, V2 is a High output. In this way, the difference between V1 and V2 is amplified.

[0238] ​​​​​​​​​​​​​An example of a timing chart for write operations is shown in Figure 25(A). The figure shows memory This is a timing chart for writing data "10b" to a cell. The second message selected... Line S2 becomes 0[V] earlier than the first signal line S1. The voltage of the first signal line S1 during the writing period. The position is V10. Note that the word line WL, bit line BL, and source line SL are 0[V]. Furthermore, an example of a timing chart for read operations is shown in Figure 25(B). The figure shows This is a timing chart for reading data "10b" from a memory cell. When the word line WL is asserted and the source line SL becomes Vs_read[V], Line BL corresponds to the memory cell data "10b" and is charged to V10-Vth[V]. As a result, SA_OUT0, SA_OUT1, and SA_OUT2 are each set to "1". The values ​​become "1" and "0". Note that the first signal line S1 and the second signal line S2 are 0[V].

[0239] Here is an example of a specific operating potential (voltage). For example, the threshold of transistor 201 Assuming a value voltage of approximately 0.3V and a power supply potential of VDD=2V, V11=1.6V and V10=1.2V V, V01=0.8V, V00=0V, and Vref0=0.6V, Vref1=1.0 V and Vref2 can be set to 1.4V. The potential Vpc can be set to, for example, 0V. stomach.

[0240] Furthermore, in this embodiment, the first signal line S1 is arranged in the direction of the bit line BL (column direction), and the second The signal line S2 is positioned in the direction of the word line WL (row direction), but this configuration is not necessarily limited to this. It is not that it can be done. For example, if the first signal line S1 is placed in the direction of the word line WL (row direction), The two signal lines S2 may be arranged in the direction of the bit line BL (column direction). In that case, the The drive circuit to which the first signal line S1 is connected and the drive circuit to which the second signal line S2 is connected are as appropriate. Just place them.

[0241] In this embodiment, a quad-value memory cell operates, that is, one memory cell contains four different We have explained how to write and read either state, but the circuit configuration can be changed as needed. By doing so, the operation of an n-value memory cell, that is, any one of n different states (n It is possible to write and read integers (2 or greater).

[0242] For example, an 8-level memory cell has three times the memory capacity compared to a 2-level memory cell. In this approach, eight different write potentials are prepared to determine the potential of node A, thereby generating eight different states. For reading, seven different reference potentials are prepared, which are capable of distinguishing between eight states. In the heading, one sense amplifier is installed, and it is possible to read the data after performing seven comparisons. Furthermore, by providing feedback on the comparison results, it is possible to reduce the number of comparisons to three. In the readout method that drives the source line SL, seven sense amplifiers are provided, It is also possible to read the results after multiple comparisons. Furthermore, multiple sense amplifiers can be used to perform multiple comparisons. It is also possible to configure it in this way.

[0243] Generally, 2 k In memory cells with a value (where k is an integer greater than or equal to 1), compared to the case of a binary value, The capacity will be k times greater. For writing, the write potential that determines the potential of node A is set to 2 k Prepare different types And, 2 k It generates a number of states. In reading, 2 k Two states that can distinguish between individual states k -It is good to prepare one type of reference potential. 2. Provide one sense amplifier. k -1 comparison It is possible to go and read the data. Also, by providing feedback on the comparison results, the comparison process can be repeated. It is also possible to reduce the number to k times. In the readout method that drives the source line SL, sense Two amplifiers k - You can also set up one and read it in a single comparison. Also, multiple senses are possible. It is also possible to configure the system to include an amplifier and perform multiple comparisons.

[0244] The semiconductor device according to this embodiment is extremely efficient due to the low off-current characteristics of the transistor 202. It is possible to retain information for a long period of time. In other words, it is required for DRAM, etc. Refresh operations are unnecessary, and power consumption can be reduced. Furthermore, it is virtually non-volatile. It can be used as a memory device.

[0245] Furthermore, information is written through the switching operation of transistor 202, It does not require high voltage and there are no issues with component degradation. Furthermore, the on / off switching of the transistor... Therefore, because information is written to and erased, high-speed operation can be easily achieved. Also, By controlling the potential input to a transistor, it is possible to directly rewrite the information. This eliminates the need for erasure operations required in flash memory and other devices. This can suppress the decrease in operating speed caused by the operation.

[0246] Furthermore, transistors using materials other than oxide semiconductors are capable of sufficiently high-speed operation, By using this method, it is possible to read the contents of memory at high speed.

[0247] Furthermore, since the semiconductor device according to this embodiment is a multi-level type, the memory capacity per unit area can be increased. This makes it possible to miniaturize and highly integrate semiconductor devices. In the loading operation, the potential of floating nodes can be directly controlled. Therefore, it is possible to easily perform high-precision threshold voltage control of semiconductor devices required for multi-level memory. This allows for the elimination of the post-write state check required for multi-value memory. It is also possible to do so, in which case the time required for writing can be shortened.

[0248] (Embodiment 3) This embodiment describes the circuit configuration and operation of a semiconductor device according to one aspect of the present invention. do.

[0249] In this embodiment, the circuit configuration of the memory element shown in Figure 16 is used, which differs from that of Embodiment 2. This shows the case where a read operation is performed. Note that in Figure 16, the capacitive element 205 is not present. There are also cases where this is the case. The memory element is multi-level, and we will explain the case of a quaternary type. Let the states be data "00b", "01b", "10b", and "11b", and at that time, node A The potentials are V00, V01, V10, V11 (V00 <V01<V10<V11)とする。

[0250] When writing to memory cell 200, set source line SL to 0[V] and word line WL to 0[V] Let V], bit line BL be 0[V], and second signal line S2 be 2[V]. The data "00b" When writing, set the first signal line S1 to V00[V]. Write the data "01b". In this case, the first signal line S1 is set to V01[V]. When writing data "10b" The first signal line S1 is set to V10[V]. When writing data "11b", the first signal Let line S1 be V11[V]. At this time, transistor 203 is in the off state, T202 will be in the ON state. Note that when writing is complete, the potential of the first signal line S1 will be Before the change occurs, set the second signal line S2 to 0[V] and turn off transistor 202. .

[0251] As a result, after writing data "00b", "01b", "10b", and "11b", a trap occurred. The potentials of the nodes connected to the gate electrode of the converter 201 (hereinafter referred to as node A) are as follows: The voltages will be approximately V00[V], V01[V], V10[V], and V11[V]. In this case, a charge corresponding to the potential of the first signal line S1 is accumulated, but the off-current of transistor 202 Since it is extremely small or virtually zero, the electrical charge of the gate electrode of transistor 201 The position will be held for a long period of time.

[0252] Next, when reading from memory cell 200, set the source line SL to 0[V] and the word line W Let L be VDD, the second signal line S2 be 0[V], the first signal line S1 be 0[V], and the bit line BL The connected readout circuit 211 is set to the operating state. At this time, transistor 203 The first transistor is in the ON state, and transistor 202 is in the OFF state.

[0253] As a result, depending on the state of the memory cell 200, the source line SL of the memory cell 200 corresponds to The effective resistance between bit lines BL is determined. The higher the potential at node A, the greater the effective resistance. The value will be lower. The reading circuit uses the difference in potential resulting from this difference in resistance to read the data. You can read "00b", "01b", "10b", and "11b". Note that the node Except for the lowest potential state "00b" at A, transistor 201 should ideally be in the ON state. It is suitable.

[0254] Figure 26 shows a block of a semiconductor device according to one embodiment of the present invention having an m × n bit memory capacity. Here is another example of a circuit diagram.

[0255] The semiconductor device shown in Figure 26 has m word lines WL and a second signal line S2, and n bit lines BL and the first signal line S1, and multiple memory cells 200(1,1) to 200(m,n) are arranged vertically. Memory cells arranged in a matrix of m rows x n columns (where m and n are natural numbers) Ray 210, readout circuit 211, first signal line drive circuit 212, second signal line and It is composed of peripheral circuits such as the drive circuit 213 for the lead wire and the potential generation circuit 214. Other peripheral circuits, such as a refresh circuit, may be provided.

[0256] Consider each memory cell, for example, memory cell 200(i, j). Here, i is between 1 and m. Let i and j be integers, and j be an integer between 1 and n (inclusive). Memory cell 200(i, j) is connected to bit line BL. (j), first signal line S1(j), word line WL(i) and second signal line S2(i), source Each wire is connected to a source wire. A voltage is applied. Also, the bit lines BL(1) to BL(n) are connected to the readout circuit 211, and the first signal is applied. Lines S1(1) to S1(n) are connected to the first signal line drive circuit 212, and word lines WL(1) to WL (m) and the second signal lines S2(1) to S2(m) are driven by the second signal line and word line drive circuit 21 Each of them is connected to 3.

[0257] Furthermore, the potential generation circuit 214, the second signal line and word line drive circuit 213, and the first signal line drive The configuration of circuit 212 is similar to, for example, the configuration in Figure 21, the configuration in Figure 18, and the configuration in Figure 19. It can be considered a success.

[0258] Figure 27 shows an example of the readout circuit 221. The readout circuit 221 is a sense amplifier circuit Reference cell 225, logic circuit 229, multiplexer (MUX2), flip-flop circuit It has circuits FF0, FF1, FF2, bias circuit 223, etc. Reference cell 225 is transistor It has transistor 216, transistor 217, and transistor 218. It has reference cell 225. Transistors 216, 217, and 218 are the transistors 201 and 2 that the memory cell has 02 and 203 correspond to each other and have the same circuit configuration as the memory cell. Transistor 21 6 and transistor 218 are formed using materials other than oxide semiconductors, ZISTA 217 is preferably formed using an oxide semiconductor. If the reference cell 225 has a capacitive element 205, it is preferable that the reference cell 225 also has a capacitive element. The two output terminals of the bias circuit 223 are connected to the bit line BL and via a switch, respectively. It is connected to the drain electrode of transistor 218 of reference cell 225. Also, via The output terminal of circuit 223 is connected to the input terminal of the sense amplifier circuit. The output terminals of the circuit are connected to the flip-flop circuits FF0, FF1, and FF2. The output terminals of the flop circuits FF0, FF1, and FF2 are connected to the input terminals of the logic circuit 229. The multiplexer (MUX2) receives signals RE0, RE1, RE2, and a reference potential Vr. ef0, Vref1, Vref2, and GND are input. Multiplexer (MUX2) The output terminal is connected to the source electrode or drain electrode of transistor 217 of reference cell 225. It is connected to one of the poles. Also, the transients of bit line BL and reference cell 225 The drain electrode of sta218 is connected to wiring Vpc via a switch. The switch is controlled by signal ΦA.

[0259] The read circuit 221 reads the potential output from the memory cell and the potential output from the reference cell 225. This configuration compares the conductance of the memory cell and the reference cell 225 by comparing their potentials. This configuration has one sense amplifier circuit and performs three comparisons to read out the four states. Let's assume that, for three different reference potentials, the memory cell and the reference cell 225 are... The conductances are compared. The three comparisons are performed using signals RE0, RE1, RE2, and ΦA. It is controlled in this way. The multiplexer (MUX2) responds to the values ​​of signals RE0, RE1, and RE2. Then, one of the three reference potentials Vref0, Vref1, Vref2, or GND. Select either. The behavior of the multiplexer (MUX2) is shown in Table 3. Also, flipf The r-stop circuits FF0, FF1, and FF2 are controlled by signals RE0, RE1, and RE2, respectively. It is controlled and stores the value of the sense amplifier's output signal SA_OUT.

[0260] [Table 3]

[0261] The reference potential is V00 <Vref0<V01<Vref1<V10<Vref2<V11と Determine the values ​​accordingly. By doing this, you can read out four states as a result of three comparisons. It is possible. In the case of data "00b", the values ​​of FF0, FF1, and FF2 are "0". If the data is "0", "0", then the values ​​of FF0, FF1, and FF2 are "1", If the data is 0", "0", then the values ​​of FF0, FF1, and FF2 are "1", "1 If the values ​​are ", "0", and the data is "11b", then the values ​​of FF0, FF1, and FF2 are "1", "1". This results in "1". In this way, the state of the memory cell is read out as a 3-bit digital signal. This can be done. Then, using the logic circuit 229 represented by the logic value table shown in Table 2, 2B The data DO is generated and output from the readout circuit.

[0262] In the readout circuit shown in Figure 27, when the signal RE is deasserted, the bit line BL and Then, connect reference cell 225 to wiring Vpc and perform pre-charging. Signal RE is asserted. Then, the bit line BL and bias circuit 223, and the reference cell 225 and bias circuit 223 are respectively It conducts electricity.

[0263] Note that precharging is not necessary. In this circuit, two inputs are made to the sense amplifier circuit. It is preferable to make the configurations of the circuits that generate the signals as similar as possible. For example, the reference cell It is preferable to use the same transistor configuration for the 225 and the memory cell. It is preferable to use the same configuration for the bias circuit 223 and the switches.

[0264] The timing chart for the write operation is the same as in Figure 25(A). The timing chart for the read operation An example of a tracking chart is shown in Figure 28. The chart shows the data "10b" being transferred from the memory cell. This is the timing chart for reading. Signals RE0, RE1, and RE2 are asserted. During this period, the output of the multiplexer (MUX2), MUX2_OUT, will be set to Vref0 Vref1 and Vref2 are input. In the first half of each period, signal ΦA is asserted, and reference A predetermined potential is applied to node B of the transistor in cell 225. The latter half of each period corresponds to the signal Φ. A is deasserted, and a predetermined potential is maintained at node B of the transistor of reference cell 225. In addition, the drain electrode of transistor 218 in reference cell 225 is in the bias circuit It is connected to 223. Then, the comparison result in the sense amplifier circuit is the flip-flop circuit. It is stored in FF0, FF1, and FF2 respectively. If the memory cell data is "10b" In this case, the values ​​of the flip-flop circuits FF0, FF1, and FF2 are "1", "1", and "0". The first signal line S1 and the second signal line S2 are 0[V].

[0265] Next, we will describe a readout circuit and readout method that differ from the configuration shown in Figure 20. .

[0266] Figure 29 shows an example of the readout circuit 231. The readout circuit 231 is a sense amplifier circuit , multiple reference cells (reference cell 225a, reference cell 225b, reference cell 225c), logical loop It includes a path 229, flip-flop circuits FF0, FF1, FF2, bias circuit 223, etc. do.

[0267] The multiple reference cells are transistor 216, transistor 217, and transistor 2 It has 18. Transistors 216, 217, and 218 are transistors that the memory cell 200 has These correspond to ZISTAS 201, 202, and 203 respectively, and have the same circuit configuration as memory cell 200. Transistors 216 and 218 use materials other than oxide semiconductors. It is formed, and it is preferable that the transistor 217 is formed using an oxide semiconductor. Furthermore, if the memory cell has a capacitive element 205, the reference cell also has a capacitive element. It is preferable to do so. The two output terminals of the bias circuit 223 are each connected via a switch. The bit line BL is connected to the drain electrode of transistor 218, which has multiple reference cells. Furthermore, the output terminal of the bias circuit 223 is connected to the input terminal of the sense amplifier circuit. The output terminals of the sense amplifier circuit are connected to the flip-flop circuits FF0, FF1, and FF2. The output terminals of the flip-flop circuits FF0, FF1, and FF2 are connected to the logic circuit 229. It is connected to the input terminal. Also, the bit line BL and the transistors of multiple reference cells The drain electrode of 218 is connected to wiring Vpc via a switch. Note that the above switch It is controlled by the read enable signal (RE signal).

[0268] The read circuit 231 reads the potential output from the memory cell and the potential output from the reference cell 225. This configuration compares the conductance of a memory cell and multiple reference cells by comparing their potentials. This configuration has one sense amplifier circuit and performs three comparisons to read out the four states. Let's assume that the conductance of the memory cell and the three reference cells are compared. The three comparisons are controlled by signals RE0, RE1, and RE2. The three reference cells are... The gate electrode of transistor 216 is connected to transistor 217 via Vref0 and Vref1 Vref2 is input to each of these. Before reading, assert signal ΦA, Turn on all transistors 217 and write to the reference cell. Writing to the cell only needs to be done once before reading. Of course, for several read operations... You can do it once or every time. Also, flip-flop circuits FF0, FF1, F F2 is controlled by signals RE0, RE1, and RE2 respectively, and is the output of the sense amplifier. Stores the value of the signal SA_OUT.

[0269] The reference potential is V00 <Vref0<V01<Vref1<V10<Vref2<V11と Determine the values ​​accordingly. By doing this, you can read out four states as a result of three comparisons. It is possible. In the case of data "00b", the values ​​of FF0, FF1, and FF2 are "0". If the data is "0", "0", then the values ​​of FF0, FF1, and FF2 are "1", If the data is 0", "0", then the values ​​of FF0, FF1, and FF2 are "1", "1 If the values ​​are ", "0", and the data is "11b", then the values ​​of FF0, FF1, and FF2 are "1", "1". This results in "1". In this way, the state of the memory cell is read out as a 3-bit digital signal. This can be done. Then, using the logic circuit 229 represented by the logic value table shown in Table 2, 2B The data DO is generated and output from the readout circuit.

[0270] In the readout circuit shown in Figure 29, when the RE signal is deasserted, the bit line BL The reference cell is then connected to the Vpc and precharged. When the RE signal is asserted, the bit The T-wire BL and the bias circuit 223, and the reference cell and the bias circuit 223 are both conductive.

[0271] Note that precharging is not necessary. In this circuit, two inputs are made to the sense amplifier circuit. It is preferable to make the configurations of the circuits that generate the signals as similar as possible. For example, the reference cell It is preferable to use the same configuration for the corresponding transistors in the memory cell. It is preferable to use the same configuration for circuit 223 and switches.

[0272] The timing chart for the write operation is the same as in Figure 25(A). The timing chart for the read operation An example of a tracking chart is shown in Figure 30. The chart shows the data "10b" being transferred from the memory cell. This is a timing chart for reading data. It shows the timing when RE0, RE1, and RE2 are asserted. Between them, reference cell 225a, reference cell 225b, and reference cell 225c are selected, respectively. It is connected to bias circuit 223. Then, the comparison result in the sense amplifier circuit is flipped. The data is stored in the flop circuits FF0, FF1, and FF2 respectively. In the case of "0b", the values ​​of the flip-flop circuits FF0, FF1, and FF2 are "1", "1". , becomes "0". Note that the first signal line S1 and the second signal line S2 are 0[V].

[0273] Here is an example of a specific operating potential (voltage). For example, the threshold voltage of transistor 201 is Approximately 0.3V, with power supply potential VDD=2V, V11=1.6V, V10=1.2V, V0 1=0.8V, V00=0V, and Vref0=0.6V, Vref1=1.0V, Vr ef2 can be set to 1.4V. The potential Vpc can be set to, for example, 0V.

[0274] Furthermore, in this embodiment, the first signal line S1 is arranged in the direction of the bit line BL (column direction), and the second The signal line S2 is positioned in the direction of the word line WL (row direction), but this configuration is not necessarily limited to this. It is not that it can be done. For example, if the first signal line S1 is placed in the direction of the word line WL (row direction), The two signal lines S2 may be arranged in the direction of the bit line BL (column direction). In that case, the The drive circuit to which the first signal line S1 is connected and the drive circuit to which the second signal line S2 is connected are as appropriate. Just place them.

[0275] In this embodiment, a quad-value memory cell operates, that is, one memory cell contains four different We have explained how to write and read either state, but the circuit configuration can be changed as needed. By doing so, the operation of an n-value memory cell, that is, any one of n different states (n It is possible to write and read integers (2 or greater).

[0276] For example, an 8-level memory cell has three times the memory capacity compared to a 2-level memory cell. In this approach, eight different write potentials are prepared to determine the potential of node A, thereby generating eight different states. For reading, seven different reference potentials are prepared, which are capable of distinguishing between eight states. In the heading, one sense amplifier is installed, and it is possible to read the data after performing seven comparisons. Furthermore, by providing feedback on the comparison results, it is possible to reduce the number of comparisons to three. In the readout method that drives the source line SL, seven sense amplifiers are provided, It is also possible to read the results after multiple comparisons. Furthermore, multiple sense amplifiers can be used to perform multiple comparisons. It is also possible to configure it in this way.

[0277] Generally, 2 k In memory cells with a value (where k is an integer greater than or equal to 1), compared to the case of a binary value, The capacity will be k times greater. For writing, the write potential that determines the potential of node A is set to 2 k Prepare different types And, 2 k It generates a number of states. In reading, 2 k Two states that can distinguish between individual states k-It is good to prepare one type of reference potential. 2. Provide one sense amplifier. k -1 comparison It is possible to go and read the data. Also, by providing feedback on the comparison results, the comparison process can be repeated. It is also possible to reduce the number to k times. In the readout method that drives the source line SL, sense Two amplifiers k - You can also set up one and read it in a single comparison. Also, multiple senses are possible. It is also possible to configure the system to include an amplifier and perform multiple comparisons.

[0278] The semiconductor device according to this embodiment is extremely efficient due to the low off-current characteristics of the transistor 202. It is possible to retain information for a long period of time. In other words, it is required for DRAM, etc. Refresh operations are unnecessary, and power consumption can be reduced. Furthermore, it is virtually non-volatile. It can be used as a memory device.

[0279] Furthermore, information is written through the switching operation of transistor 202, It does not require high voltage and there are no issues with component degradation. Furthermore, the on / off switching of the transistor... Therefore, because information is written to and erased, high-speed operation can be easily achieved. Also, By controlling the potential input to a transistor, it is possible to directly rewrite the information. This eliminates the need for erasure operations required in flash memory and other devices. This can suppress the decrease in operating speed caused by the operation.

[0280] Furthermore, transistors using materials other than oxide semiconductors are capable of sufficiently high-speed operation, By using this method, it is possible to read the contents of memory at high speed.

[0281] Furthermore, since the semiconductor device according to this embodiment is a multi-level type, the memory capacity per unit area can be increased. This makes it possible to miniaturize and highly integrate semiconductor devices. In the loading operation, the potential of floating nodes can be directly controlled. Therefore, it is possible to easily perform high-precision threshold voltage control of semiconductor devices required for multi-level memory. This allows for the elimination of the post-write state check required for multi-value memory. It is also possible to do so, in which case the time required for writing can be shortened.

[0282] (Embodiment 4) This embodiment provides an example of a semiconductor device circuit configuration and operation different from those in Embodiments 2 and 3. I will explain this.

[0283] Figure 31 shows an example of a circuit diagram of a memory cell in a semiconductor device. The memory cell shown in Figure 31. 240 consists of source line SL, bit line BL, first signal line S1, second signal line S2, and It consists of a wire WL, transistor 201, transistor 202, and capacitive element 204. Transistor 201 is formed using materials other than oxide semiconductors. Transistor 202 is formed using an oxide semiconductor.

[0284] Here, the gate electrode of transistor 201 and the source electrode or dot of transistor 202 One electrode of the rain electrode and one electrode of the capacitive element 204 are electrically connected. The source line SL and the source electrode of transistor 201 are electrically connected, and the bit line BL and the drain electrode of transistor 201 are electrically connected, and the first signal line S1 and The source electrode or the other of the drain electrode of transistor 202 is electrically connected. The second signal line S2 and the gate electrode of transistor 202 are electrically connected, and the word line WL and the other electrode of the capacitive element 204 are electrically connected.

[0285] Next, we will explain the operation of the memory cell 240 shown in Figure 31. Here, we will describe the case of a quaternary type. This explains the four states of memory cell 240, with data "00b", "01b", and "10b". Let's call it "11b", and the potentials of node A at that time be V00, V01, V10, V11( V00 <V01<V10<V11)とする。

[0286] When writing to memory cell 240, set source line SL to 0[V] and word line WL to 0[V] Let V[V], bit line BL be 0[V], and second signal line S2 be VDD. Write the data "00b". When writing, set the first signal line S1 to V00[V]. In this case, the first signal line S1 is set to V01[V]. When writing data "10b", Let the first signal line S1 be V10[V]. When writing data "11b", the first signal Let line S1 be V11[V]. At this time, transistor 201 is in the off state, transistor 202 will be in the ON state. Note that when writing is complete, the potential of the first signal line S1 will change. Before proceeding, set the second signal line S2 to 0[V] and turn off transistor 202.

[0287] As a result, after writing data "00b", "01b", "10b", and "11b" (Word (Assume the line WL potential is 0[V]) The node connected to the gate electrode of transistor 201 The potentials at (Node A below) are approximately V00[V], V01[V], and V10[V], respectively. ], which is approximately V11[V]. At node A, a charge corresponding to the potential of the first signal line S1 is accumulated. However, the off-current of transistor 202 is extremely small, or practically zero. The potential of the gate electrode of transistor 201 is maintained for a long period of time.

[0288] When reading from memory cell 240, set source line SL to 0[V] and second signal line S2 to A readout circuit connected to bit line BL, with the first signal line S1 set to 0[V] and the voltage 0[V]. This is the operating state. At this time, transistor 202 is in the off state.

[0289] Then, let the word line WL be V_WL[V]. The potential of node A of memory cell 240 is It depends on the potential of the word line WL; the higher the potential of the word line WL, the higher the noise of memory cell 240. The potential of A also increases. For example, for memory cells in four different states, the potential of the word line WL increases. When the potential is changed from low to high, the transistor of the memory cell containing data "11b" 201 is the first to turn on, followed by the data "10b", "01b", and "00b". The memory cells are turned on sequentially. This is achieved by appropriately selecting the word line potential WL. This means that the state of the memory cell (i.e., the data in the memory cell) is identifiable. When the potential of the lead wire WL is appropriately selected, the memory cell with transistor 201 turned ON is low Since it enters a resistive state and transistor 201 is off, the memory cell enters a high-resistance state. By distinguishing this resistance state using a reading circuit, the data "00b", "01b", It can read "10b" and "11b".

[0290] Figure 32 shows a block of a semiconductor device according to one embodiment of the present invention having an m × n bit memory capacity. Here is another example of a circuit diagram.

[0291] The semiconductor device shown in Figure 32 has m word lines WL and a second signal line S2, and n bit lines BL and the first signal line S1, and multiple memory cells 240(1,1) to 240(m,n) are arranged vertically. Memory cells arranged in a matrix of m rows x n columns (where m and n are natural numbers) Ray 210, readout circuit 231, first signal line drive circuit 212, second signal line and It is composed of peripheral circuits such as the drive circuit 223 for the cord wires and the potential generation circuit 214. Other peripheral circuits, such as a refresh circuit, may be provided.

[0292] Consider each memory cell, for example, memory cell 240(i, j). Here, i is between 1 and m. An integer (where j is an integer between 1 and n). Memory cell 240(i, j) is connected to the bit line BL(j ), first signal line S1(j), word line WL(i) and second signal line S2(i), source wiring Each is connected to SL. The source wiring SL has a source line potential Vs (for example, 0[V]). ]) is applied. Also, bit lines BL(1) to BL(n) are connected to the readout circuit 231. Signal lines S1(1) to S1(n) are connected to the first signal line drive circuit 212, and word line WL(1) to WL(m) and the second signal lines S2(1) to S2(m) are connected to the second signal line S2 and the word line WL. They are each connected to the drive circuit 223.

[0293] The configurations of the first signal line drive circuit 212 and the potential generation circuit 214 are shown in Figure 19 and, respectively. The configuration shown in Figure 21 should be applied.

[0294] Figure 33 shows an example of a readout circuit. The readout circuit consists of a sense amplifier circuit and a flip-flow resistor. It has a top circuit, a bias circuit 224, etc. The bias circuit 224 is via a switch It is connected to the bit line BL. Also, the bias circuit 224 is connected to the input terminal of the sense amplifier circuit. It is connected to the other input terminal of the sense amplifier circuit. The reference potential Vr is input to the other input terminal. Furthermore, the output terminal of the sense amplifier circuit is connected to the input terminals of the flip-flop circuits FF0 and FF1. It is connected. Note that the above switch is controlled by the read enable signal (RE signal). The read circuit is connected to the bit line BL, and the specified memory cell is bit Data can be read by reading the potential output to line BL. Bit line B The potential of L changes in accordance with the conductance. Note that the conductance of the memory cell is read. "To read" means to read the on or off state of transistor 201 that constitutes the memory cell. It means to release or put out.

[0295] The readout circuit shown in Figure 33 has one sense amplifier circuit and identifies four different states. To achieve this, two comparisons will be performed. The two comparisons will be controlled by signals RE0 and RE1. The flip-flop circuits FF0 and FF1 are controlled by signals RE0 and RE1, respectively. The value of the output signal of the sense amplifier circuit is stored. The force is represented as DO[1], and the output of the flip-flop circuit FF1 is represented as DO[0], and the reading is It is output from the circuit.

[0296] In the illustrated readout circuit, when the RE signal is deasserted, the bit line BL is wired. Connect to Vpc and precharge. When the RE signal is asserted, the bit line BL and bi The ass circuit 224 becomes conductive. Note that precharging is not necessary.

[0297] Figure 34 shows another example of the drive circuit 223 for the second signal line S2 and the word line WL.

[0298] The drive circuit 223 for the second signal line and word line shown in Figure 34 receives the address signal ADR. Then, the row with the specified address (selected row) is asserted, and the other rows (unselected rows) are not asserted. Asserted. The second signal line S2 is connected to the decoder output when the WE signal is asserted. When the WE signal is deasserted, it is connected to GND. The word line WL of the selected row is maru The output V_WL of the chipplexer (MUX3) is connected, and the word line WL of the unselected row is connected to GND. The connection is established. The multiplexer (MUX3) responds according to the values ​​of signals RE0, RE1, and DO0. , one of three reference potentials Vref0, Vref1, Vref2, or GND Select. The behavior of the multiplexer (MUX3) is shown in Table 4.

[0299] [Table 4]

[0300] Three types of reference potentials Vref0, Vref1, Vref2 (Vref0 <Verf1<Vr Let's explain ef2). Vref0 was selected as the potential of the word line WL. In this case, the transistor 201 of the memory cell containing data "00b" is turned off, and the data Select the potential that turns on transistor 201 of memory cell 01b. Also, V ref1 is selected as the potential of the word line WL, and the data "01b" Turn off transistor 201 of the Morissel, and turn off the memory cell transistor for data "10b". Select the potential that will turn on ZISTA201. Also, Vref2 is the word line W. When selected as potential L, transistor 201 of memory cell containing data "10b" This is turned off, and transistor 201 of the memory cell for data "11b" is turned on. Select the potential.

[0301] This readout circuit performs readout by making two comparisons. The first comparison uses Vref1. Then perform the comparison. For the second time, if the comparison result FF0 using Vref1 is "0", then Vref If the comparison is performed using 2, then if it's "1", then the comparison is performed using Vref0. This is how it's done. This makes it possible to read the four states through two comparisons.

[0302] The timing chart for the write operation is the same as in Figure 25(A). The timing chart for the read operation is also shown. An example of a timing chart is shown in Figure 35. The figure shows the data "1" from the memory cell. This is a timing chart for reading "0b". RE0 and RE1 are asserted during this period. In between, Vref1 and Vref2 are entered into the selected word line WL, and sense The comparison results from the amplifier circuit are stored in the flip-flop circuits FF0 and FF1, respectively. If the data of the memory cell is "10b", the flip-flop circuits FF0 and FF1 The values ​​will be "1" and "0". Note that the first signal line S1 and the second signal line S2 are 0[V].

[0303] An example of a specific operating potential (voltage) is shown. For example, the threshold voltage V of transistor 201. Assume th = 2.2V. The potential at node A is determined by the capacitance C1 between the word line WL and node A, and the traction This depends on the gate capacitance C2 of transistor 202, but here, as an example, transistor 2 Assume that when O2 is off, C1 / C2 >> 1, and when it is on, C1 / C2 = 1. See Figure 36. This shows the relationship between the potential at node A and the potential at word line WL when the source line SL is 0[V]. From Figure 36, for example, the potential of node A of data "00b" during writing is 0V, and the data The node A potential for "01b" is 0.8V, and the node A potential for data "10b" is 1.2V. If the potential of node A of "11b" is 1.6V, then the reference potential is Vref0 = 0.6V. It can be seen that setting Vref1=1.0V and Vref2=1.4V is a good approach.

[0304] Note that the voltage of node A of transistor 201 after writing (word line WL potential is 0[V]) The voltage level is preferably set to be below the threshold voltage of transistor 201.

[0305] Furthermore, in this embodiment, the first signal line S1 is arranged in the direction of the bit line BL (column direction), and the second The signal line S2 is positioned in the direction of the word line WL (row direction), but this configuration is not necessarily limited to this. It is not that it can be done. For example, if the first signal line S1 is placed in the direction of the word line WL (row direction), The two signal lines S2 may be arranged in the direction of the bit line BL (column direction). In that case, the The drive circuit to which the first signal line S1 is connected and the drive circuit to which the second signal line S2 is connected are as appropriate. Just place them.

[0306] In this embodiment, a quad-value memory cell operates, that is, one memory cell contains four different We have explained how to write and read either state, but the circuit configuration can be changed as needed. By doing so, the operation of an n-value memory cell, that is, any one of n different states (n It is possible to write and read integers (2 or greater).

[0307] For example, an 8-level memory cell has three times the memory capacity compared to a 2-level memory cell. In this approach, eight different write potentials are prepared to determine the potential of node A, thereby generating eight different states. For reading, seven different reference potentials are prepared, which are capable of distinguishing between eight states. In the heading, one sense amplifier is installed, and it is possible to read the data after performing seven comparisons. Furthermore, by providing feedback on the comparison results, it is possible to reduce the number of comparisons to three. .

[0308] Generally, 2 k In memory cells with a value (where k is an integer greater than or equal to 1), compared to the case of a binary value, The capacity will be k times greater. For writing, the write potential that determines the potential of node A is set to 2 k Prepare different types And, 2 k It generates a number of states. In reading, 2 k Two states that can distinguish between individual states k -It is good to prepare one type of reference potential. 2. Provide one sense amplifier. k -1 comparison It is possible to go and read the data. Also, by providing feedback on the comparison results, the comparison process can be repeated. It is also possible to reduce the number to k times. In the readout method that drives the source line SL, sense Two amplifiers k - You can also set up one and read it in a single comparison. Also, multiple senses are possible. It is also possible to configure the system to include an amplifier and perform multiple comparisons.

[0309] The semiconductor device according to this embodiment is extremely efficient due to the low off-current characteristics of the transistor 202. It is possible to retain information for a long period of time. In other words, it is required for DRAM, etc. Refresh operations are unnecessary, and power consumption can be reduced. Furthermore, it is virtually non-volatile. It can be used as a memory device.

[0310] Furthermore, information is written through the switching operation of transistor 202, It does not require high voltage and there are no issues with component degradation. Furthermore, the on / off switching of the transistor... Therefore, because information is written to and erased, high-speed operation can be easily achieved. Also, By controlling the potential input to a transistor, it is possible to directly rewrite the information. This eliminates the need for erasure operations required in flash memory and other devices. This can suppress the decrease in operating speed caused by the operation.

[0311] Furthermore, transistors using materials other than oxide semiconductors are capable of sufficiently high-speed operation, By using this method, it is possible to read the contents of memory at high speed.

[0312] Furthermore, since the semiconductor device according to this embodiment is a multi-level type, the memory capacity per unit area can be increased. This makes it possible to miniaturize and highly integrate semiconductor devices. In the loading operation, the potential of floating nodes can be directly controlled. Therefore, it is possible to easily perform high-precision threshold voltage control of semiconductor devices required for multi-level memory. This allows for the elimination of the post-write state check required for multi-value memory. It is also possible to do so, in which case the time required for writing can be shortened.

[0313] (Embodiment 5) In this embodiment, an example of an electronic device equipped with the semiconductor device obtained in the previous embodiment is described below. This will be explained using Figure 37. The semiconductor device obtained in the previous embodiment does not have a power supply. Even in such cases, it is possible to retain information. Furthermore, no degradation occurs due to writing and erasing. Furthermore, its operation is also high-speed. For this reason, a new configuration of electric device can be created using this semiconductor device. It is possible to provide sub-devices. Furthermore, the semiconductor device according to the above embodiment is integrated These components are then mounted on circuit boards and installed inside various electronic devices.

[0314] Figure 37(A) shows a notebook-type personal computer including a semiconductor device according to the above embodiment. It is a data system consisting of the main unit 301, the casing 302, the display unit 303, the keyboard 304, etc. This has been done. A semiconductor device according to one aspect of the present invention is used in a notebook-type personal computer. By applying this technology, it becomes possible to retain information even when there is no power supply. Also, There is no degradation associated with writing and erasing. Furthermore, the operation is also fast. For this reason, It is preferable to apply a semiconductor device according to one embodiment of the invention to a notebook-type personal computer. That is the case.

[0315] Figure 37(B) shows a personal digital assistant (PDA) including a semiconductor device according to the previous embodiment. The main unit 311 includes a display unit 313, an external interface 315, and operation buttons 314, etc. A stylus 312 is provided as an accessory for operation. By applying the semiconductor device mentioned above to a PDA, information can be retained even when there is no power supply. It is possible to do so. Furthermore, no degradation occurs due to writing and erasing. Moreover, its operation is It is high-speed. For this reason, it is preferable to apply a semiconductor device according to one aspect of the present invention to a PDA. That is the case.

[0316] Figure 37(C) shows an example of an electronic paper including a semiconductor device according to the above embodiment, This shows the e-book 320. The e-book 320 is housed in two enclosures, enclosure 321 and enclosure 323. It is constructed such that the housing 321 and housing 323 are integrated by the shaft portion 337. The shaft portion 337 can be used as an axis for opening and closing operations. With this configuration, ebooks 320 can be used like a paper book. Semiconductor device according to one aspect of the present invention By applying this to electronic paper, it is possible to retain information even when there is no power supply. It is capable of handling data. Furthermore, there is no degradation associated with writing or erasing data. Moreover, its operation is high-speed. Therefore, it is preferable to apply a semiconductor device according to one aspect of the present invention to electronic paper. ru.

[0317] The display unit 325 is incorporated into the housing 321, and the display unit 327 is incorporated into the housing 323. The display units 325 and 327 may be configured to display a continuation screen, or differently. It is also possible to configure the system to display a different screen. By configuring the system to display different screens, for example, Text is displayed on the right-hand display unit (display unit 325 in Figure 37(C)), and on the left-hand display unit (Figure 37 (C) allows an image to be displayed on the display unit 327).

[0318] Furthermore, Figure 37(C) shows an example in which the housing 321 is equipped with an operating section, etc. The body 321 is equipped with a power supply 331, operation keys 333, speaker 335, etc. Pages can be turned using -333. Note that the keyboard and port are located on the same surface as the display unit. The configuration may also include input devices, etc. Connection terminals (earphone jack, USB terminal, or AC adapter and USB cable, etc.) The configuration may also include terminals that can be connected to various cables, a recording medium insertion section, and so on. Furthermore, eBook 320 may be configured to also function as an electronic dictionary.

[0319] Furthermore, the e-book 320 may be configured to transmit and receive information wirelessly. It is also possible to configure the system to allow users to purchase and download desired book data from a sub-book server. It is possible.

[0320] Furthermore, electronic paper can be applied to any field that displays information. For example, in addition to ebooks, there are posters, advertisements on trains and other vehicles, and credit cards. This can be applied to displays on various types of cards, such as TCG cards.

[0321] Figure 37(D) shows a mobile phone including a semiconductor device according to the previous embodiment. The telephone consists of two housings, housing 340 and housing 341. Housing 341 is front Display panel 342, speaker 343, microphone 344, pointing device 3 It is equipped with 46, a camera lens 347, an external connection terminal 348, etc. Also, housing 341 This includes a solar cell 349 for charging the mobile phone, an external memory slot 350, etc. It is equipped with. Furthermore, the antenna is built into the housing 341. This is according to one aspect of the present invention. By applying semiconductor devices to mobile phones, information can be retained even when there is no power supply. This is possible. Furthermore, no degradation occurs during writing and erasing. Moreover, its operation is also high-performance. It is fast. For this reason, applying a semiconductor device according to one aspect of the present invention to a mobile phone is preferable. It is suitable.

[0322] The display panel 342 has a touch panel function, and the image displayed in Figure 37(D) is Multiple operation keys 345 are shown with dotted lines. Note that the mobile phone has a solar cell 34 A boost circuit is implemented to increase the voltage output from 9 to the voltage required for each circuit. Furthermore, in addition to the above configuration, the configuration will include a contactless IC chip, a small recording device, etc. It's also possible.

[0323] The display panel 342 changes its orientation as appropriate depending on the usage mode. Since the camera lens 347 is located on the same plane as 42, video calls are possible. Speaker 343 and microphone 344 are not limited to voice calls, but also video calls, recording, and playback. Raw materials can be used. Furthermore, the housing 340 and housing 341 slide together, as shown in Figure 37(D). It can be transformed from an unfolded state to an overlapping state, and can be made smaller for portability. It is Noh.

[0324] External connection terminal 348 can be connected to various cables such as AC adapters and USB cables. It also enables charging and data communication. In addition, the external memory slot 350 can be used for recording media. By inserting this, it can handle the storage and movement of larger amounts of data. In addition to the above functions, It may also be equipped with infrared communication capabilities, television reception capabilities, etc.

[0325] Figure 37(E) shows a digital camera including a semiconductor device according to the previous embodiment. The digital camera consists of the main unit 361, the display unit (A) 367, the eyepiece 363, and the operation switch 364. It consists of a display unit (B) 365, a battery 366, and the like. One aspect of the present invention By applying the semiconductor device to a digital camera, information can be transmitted even when there is no power supply. It is possible to retain it. Furthermore, no degradation occurs due to writing or erasing. Its operation is also fast. For this reason, a semiconductor device according to one aspect of the present invention is suitable for a digital camera. It is preferable to use it.

[0326] Figure 37(F) shows a television apparatus including a semiconductor device according to the previous embodiment. In the vision device 370, the display unit 373 is incorporated into the housing 371. This makes it possible to display video. Note that here, the enclosure is connected by stand 375. This shows the configuration that supported 371.

[0327] The television device 370 can be operated using the control switches on the housing 371 or a separate remote control. This can be done using the control unit 380. The operation keys 379 on the remote control unit 380 This allows you to control the channel and volume, and manipulate the image displayed on the display unit 373. It is possible to output from the remote control unit 380 to the remote control unit 380. A configuration may also be provided that includes a display unit 377 for displaying the information. Semiconductor according to one aspect of the present invention By applying this device to a television system, information can be retained even when there is no power supply. It is possible to do so. Furthermore, no degradation occurs due to writing and erasing. Moreover, its operation is It is high-speed. For this reason, a semiconductor device according to one aspect of the present invention is applied to a television apparatus. This is preferable.

[0328] Furthermore, it is preferable that the television equipment 370 be configured to include a receiver, modem, etc. The receiver can receive regular television broadcasts. It can also receive broadcasts via a modem. By connecting to a wired or wireless communication network, one-way communication (from sender to receiver) is possible. (Sender) or two-way information communication (between sender and receiver, or between receivers, etc.) This is possible.

[0329] The configurations and methods shown in this embodiment may be combined with the configurations and methods shown in other embodiments as appropriate. They can be used together. [Explanation of Symbols]

[0330] 100 circuit boards 102 Protective layer 104 Semiconductor field 106 element isolation insulating layer 108a Gate Insulation Layer 110a Shuttle bus 112 Insulating layer 114 Impurity region 116 Channel formation region 118 Sidewall insulation layer 120 High concentration impurity region 122 Metal layer 124 Metal compound area 126 Interlayer insulating layer 128 Interlayer insulating layer 130a Source electrode or drain electrode 130b Source electrode or drain electrode 130c electrode 132 Insulating layer 134 Conductive layer 136a electrode 136b Electrode 136c electrode 136d Gate 138 Gate Insulation Layer 140 Oxide semiconductor layer 142a Source electrode or drain electrode 142b Source electrode or drain electrode 144 Protective insulating layer 146 Interlayer insulating layer 148 Conductive layer 150a electrode 150b electrode 150c electrode 150d electrode 150e electrode 152 Insulating layer 154a electrode 154b electrode 154c electrode 154d electrode 160 transistors 162 transistors 200 memory cells 201 Transistors 202 transistors 203 Transistors 204 Capacitive element 205 Capacitive element 210 memory cell array 211 Readout Circuit 212 Signal Line Drive Circuit 213 Drive Circuit 214 Potential generation circuit 215 Decoder 216 transistors 217 transistors 218 transistors 219 Boost Circuit 220 Analog Buffer 221 Readout Circuit 223 Drive Circuit 224 Bias Circuit 225 Reference Cell 225a Reference cell 225b Reference cell 225c Reference cell 229 Logic Circuits 231 Readout Circuit 240 memory cells 301 Main Unit 302 enclosures 303 Display section 304 Keyboard 311 Main Unit 312 Stylus 313 Display section 314 Operation Buttons 315 External Interface 320 eBooks 321 cabinet 323 enclosures 325 Display section 327 Display section 331 Power supply 333 Operation Keys 335 speakers 337 Shaft 340 cabinets 341 cabinets 342 Display Panel 343 speakers 344 Microphone 345 Operation Keys 346 Pointing devices 347 Camera Lenses 348 External connection terminals 349 solar cells 350 external memory slots 361 Main Unit 363 Eyepiece 364 Operation Switches 365 Display section (B) 366 Battery 367 Display section (A) 370 Television equipment 371 cabinets 373 Display section 375 Stand 377 Display section 379 Operation Keys 380 Remote Control Unit 402 diode 404 diode 406 diode 408 diode 410 diode 412 Capacitive elements 414 Capacitive elements 416 Capacitive elements 418 Capacitive elements 420 Capacitive elements

Claims

1. The device comprises a first transistor having silicon in its first channel formation region, a second transistor having an oxide semiconductor in its second channel formation region, a third transistor having silicon in its third channel formation region, and a capacitive element. The source or drain of the first transistor is electrically connected to the source or drain of the third transistor. The source or drain of the second transistor is electrically connected to the gate of the first transistor and to one electrode of the capacitive element. The gate of the second transistor is electrically connected to the first signal line. The gate of the third transistor is electrically connected to the second signal line. A semiconductor device wherein a predetermined potential is supplied to the other electrode of the capacitive element, A first conductive layer having a region positioned above the first channel forming region and functioning as the gate of the first transistor, A first insulating layer having a region positioned above the first conductive layer, A second conductive layer having a region positioned above the first insulating layer and functioning as the gate of the second transistor, A second insulating layer having a region positioned above the second conductive layer and functioning as a gate insulating layer for the second transistor, An oxide semiconductor layer having a region positioned above the second insulating layer and having the second channel-forming region, A third insulating layer having a region disposed above the oxide semiconductor layer, In a plan view, the first conductive layer does not have a region that overlaps with the second channel-forming region. Semiconductor equipment.

2. The device comprises a first transistor having silicon in its first channel formation region, a second transistor having an oxide semiconductor in its second channel formation region, a third transistor having silicon in its third channel formation region, and a capacitive element. The source or drain of the first transistor is electrically connected to the source or drain of the third transistor. The source or drain of the second transistor is electrically connected to the gate of the first transistor and to one electrode of the capacitive element. The gate of the second transistor is electrically connected to the first signal line. The gate of the third transistor is electrically connected to the second signal line. A predetermined potential is supplied to the other electrode of the capacitive element. The charge held at the gate of the first transistor corresponds to three or more potentials in a semiconductor device, A first conductive layer having a region positioned above the first channel forming region and functioning as the gate of the first transistor, A first insulating layer having a region positioned above the first conductive layer, A second conductive layer having a region positioned above the first insulating layer and functioning as the gate of the second transistor, A second insulating layer having a region positioned above the second conductive layer and functioning as a gate insulating layer for the second transistor, An oxide semiconductor layer having a region positioned above the second insulating layer and having the second channel-forming region, A third insulating layer having a region disposed above the oxide semiconductor layer, In a plan view, the first conductive layer does not have a region that overlaps with the second channel-forming region. Semiconductor equipment.

3. The device comprises a first transistor having silicon in its first channel formation region, a second transistor having an oxide semiconductor in its second channel formation region, a third transistor having silicon in its third channel formation region, and a capacitive element. The source or drain of the first transistor is electrically connected to the source or drain of the third transistor. The source or drain of the second transistor is electrically connected to the gate of the first transistor and to one electrode of the capacitive element. The gate of the second transistor is electrically connected to the first signal line. The gate of the third transistor is electrically connected to the second signal line. A semiconductor device wherein a predetermined potential is supplied to the other electrode of the capacitive element, A first conductive layer having a region positioned above the first channel forming region and functioning as the gate of the first transistor, A first insulating layer having a region positioned above the first conductive layer, A second conductive layer having a region positioned above the first insulating layer and functioning as the gate of the second transistor, A second insulating layer having a region positioned above the second conductive layer and functioning as a gate insulating layer for the second transistor, An oxide semiconductor layer having a region positioned above the second insulating layer and having the second channel-forming region, A third insulating layer having a region disposed above the oxide semiconductor layer, In a plan view, the first conductive layer does not have an area that overlaps with the second channel-forming region. The second insulating layer has a region in contact with the oxide semiconductor layer and contains oxygen and silicon. The third insulating layer has a region in contact with the oxide semiconductor layer and contains oxygen and silicon. Semiconductor equipment.

4. The device comprises a first transistor having silicon in its first channel formation region, a second transistor having an oxide semiconductor in its second channel formation region, a third transistor having silicon in its third channel formation region, and a capacitive element. The source or drain of the first transistor is electrically connected to the source or drain of the third transistor. The source or drain of the second transistor is electrically connected to the gate of the first transistor and to one electrode of the capacitive element. The gate of the second transistor is electrically connected to the first signal line. The gate of the third transistor is electrically connected to the second signal line. A predetermined potential is supplied to the other electrode of the capacitive element. The charge held at the gate of the first transistor corresponds to three or more potentials in a semiconductor device, A first conductive layer having a region positioned above the first channel forming region and functioning as the gate of the first transistor, A first insulating layer having a region positioned above the first conductive layer, A second conductive layer having a region positioned above the first insulating layer and functioning as the gate of the second transistor, A second insulating layer having a region positioned above the second conductive layer and functioning as a gate insulating layer for the second transistor, An oxide semiconductor layer having a region positioned above the second insulating layer and having the second channel-forming region, A third insulating layer having a region disposed above the oxide semiconductor layer, In a plan view, the first conductive layer does not have an area that overlaps with the second channel-forming region. The second insulating layer has a region in contact with the oxide semiconductor layer and contains oxygen and silicon. The third insulating layer has a region in contact with the oxide semiconductor layer and contains oxygen and silicon. Semiconductor equipment.

5. The device comprises a first transistor having silicon in its first channel formation region, a second transistor having an oxide semiconductor in its second channel formation region, a third transistor having silicon in its third channel formation region, and a capacitive element. The source or drain of the first transistor is electrically connected to the source or drain of the third transistor. The source or drain of the second transistor is electrically connected to the gate of the first transistor and to one electrode of the capacitive element. The gate of the second transistor is electrically connected to the first signal line. The gate of the third transistor is electrically connected to the second signal line. A semiconductor device wherein a predetermined potential is supplied to the other electrode of the capacitive element, A first conductive layer having a region positioned above the first channel forming region and functioning as the gate of the first transistor, A first insulating layer having a region positioned above the first conductive layer, A second conductive layer having a region positioned above the first insulating layer and functioning as the gate of the second transistor, A second insulating layer having a region positioned above the second conductive layer and functioning as a gate insulating layer for the second transistor, An oxide semiconductor layer having a region positioned above the second insulating layer and having the second channel-forming region, A third insulating layer having a region disposed above the oxide semiconductor layer, A third conductive layer having a region positioned above the third insulating layer, The first conductive layer is electrically connected to the oxide semiconductor layer via the third conductive layer. In a plan view, the first conductive layer does not have an area that overlaps with the second channel-forming region. In a plan view, the maximum length of the oxide semiconductor layer in the channel length direction of the second transistor is greater than the maximum length of the oxide semiconductor layer in the channel width direction of the second transistor. In a plan view, the maximum length of the third conductive layer in the channel length direction of the second transistor is greater than the maximum length of the third conductive layer in the channel width direction of the second transistor. In a plan view, the maximum length of the first conductive layer in the channel width direction of the second transistor is greater than the maximum length of the region in the channel width direction of the second transistor where the third conductive layer overlaps with the first conductive layer. In a plan view, the maximum length of the first conductive layer in the channel width direction of the second transistor is greater than the maximum length of the oxide semiconductor layer in the channel width direction of the second transistor. Semiconductor equipment.

6. The device comprises a first transistor having silicon in its first channel formation region, a second transistor having an oxide semiconductor in its second channel formation region, a third transistor having silicon in its third channel formation region, and a capacitive element. The source or drain of the first transistor is electrically connected to the source or drain of the third transistor. The source or drain of the second transistor is electrically connected to the gate of the first transistor and to one electrode of the capacitive element. The gate of the second transistor is electrically connected to the first signal line. The gate of the third transistor is electrically connected to the second signal line. A predetermined potential is supplied to the other electrode of the capacitive element. The charge held at the gate of the first transistor corresponds to three or more potentials in a semiconductor device, A first conductive layer having a region positioned above the first channel forming region and functioning as the gate of the first transistor, A first insulating layer having a region positioned above the first conductive layer, A second conductive layer having a region positioned above the first insulating layer and functioning as the gate of the second transistor, A second insulating layer having a region positioned above the second conductive layer and functioning as a gate insulating layer for the second transistor, An oxide semiconductor layer having a region positioned above the second insulating layer and having the second channel-forming region, A third insulating layer having a region disposed above the oxide semiconductor layer, A third conductive layer having a region positioned above the third insulating layer, The first conductive layer is electrically connected to the oxide semiconductor layer via the third conductive layer. In a plan view, the first conductive layer does not have an area that overlaps with the second channel-forming region. In a plan view, the maximum length of the oxide semiconductor layer in the channel length direction of the second transistor is greater than the maximum length of the oxide semiconductor layer in the channel width direction of the second transistor. In a plan view, the maximum length of the third conductive layer in the channel length direction of the second transistor is greater than the maximum length of the third conductive layer in the channel width direction of the second transistor. In a plan view, the maximum length of the first conductive layer in the channel width direction of the second transistor is greater than the maximum length of the region in the channel width direction of the second transistor where the third conductive layer overlaps with the first conductive layer. In a plan view, the maximum length of the first conductive layer in the channel width direction of the second transistor is greater than the maximum length of the oxide semiconductor layer in the channel width direction of the second transistor. Semiconductor equipment.

7. In claim 5 or 6, The second insulating layer has a region in contact with the oxide semiconductor layer and contains oxygen and silicon. The third insulating layer has a region in contact with the oxide semiconductor layer and contains oxygen and silicon. Semiconductor equipment.

8. In any one of claims 1 to 7, In a plan view, the channel formation region of the first transistor has a region in which current flows in a direction intersecting the channel length direction of the second transistor. Semiconductor equipment.

9. In any one of claims 1 to 8, The first insulating layer comprises nitrogen and silicon, Semiconductor equipment.

10. In any one of claims 1 to 9, A signal is input to the gate of the first transistor via the second transistor. Semiconductor equipment.

11. In any one of claims 1 to 10, The second transistor has an off-current of 1 × 10⁻⁶ －１３ It is less than or equal to A. Semiconductor equipment.

12. In any one of claims 1 to 11, The oxide semiconductor layer comprises In, Ga, and Zn. Semiconductor equipment.

13. In any one of claims 1 to 12, The oxide semiconductor layer has a crystalline portion, Semiconductor equipment.

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