Integrated waveguide

Abstract

To provide a substrate-integrated waveguide that can reduce the waveguide width while maintaining transmission characteristics. [Solution] The substrate integrated waveguide 1 comprises a dielectric portion 10, a lower conductive layer 21 disposed on the lower surface of the dielectric portion 10, an upper conductive layer 22 disposed on the upper surface of the dielectric portion 10, a post row PC1 in which a plurality of conductive posts 41 are arranged along the longitudinal direction of the dielectric portion 10, a post row PC2 in which a plurality of conductive posts 42 are arranged along the longitudinal direction and provided parallel to the post row PC1, and an internal conductive layer 31 disposed inside the dielectric portion 10, electrically connected to the lower conductive layer 21 and the upper conductive layer 22 via the post rows PC1 and PC2, extending along the longitudinal direction and including a gap G1 provided on the post row PC1 side.

Description

Technical Field

[0001] The present invention relates to a substrate integrated waveguide.

Background Art

[0002] As one type of waveguide, a substrate integrated waveguide (SIW) is known. This substrate integrated waveguide has a waveguide structure surrounded by an upper conductive layer and a lower conductive layer sandwiching a dielectric layer, and two post arrays composed of a plurality of vias electrically connecting the upper conductive layer and the lower conductive layer and arranged in the longitudinal direction of the dielectric layer. In the substrate integrated waveguide, a signal propagates as an electromagnetic wave in the dielectric layer surrounded by the upper conductive layer, the lower conductive layer, and the two post arrays. The electromagnetic wave is reflected by the post arrays to form an electromagnetic field pattern in the waveguide. When only the basic TE10 mode is used as the transmission mode, frequencies from about twice the cut-off frequency are used.

Prior Art Documents

Patent Documents

[0007] In a substrate-integrated waveguide, the waveguide width x is the internal dimension of the longer side of the dielectric layer's cross-section (the distance between two post rows). As can be seen from equation (1), the waveguide width (x) increases as the cutoff frequency decreases. Therefore, the waveguide width for transmitting relatively low-frequency signals must be large. However, when applying substrate-integrated waveguides to electronic devices with limited internal space, such as portable information terminals, a smaller waveguide width is desirable.

[0008] The problem that the present invention aims to solve is to provide a substrate-integrated waveguide that can reduce the waveguide width while maintaining transmission characteristics. However, the present invention is not limited to this problem, and problems corresponding to the effects of the configurations of each embodiment described later may also be considered problems of the present invention. [Means for solving the problem]

[0009] The substrate integrated waveguide according to the present invention is Dielectric part, A first conductive layer disposed on the lower surface of the dielectric portion, A second conductive layer disposed on the upper surface of the dielectric portion, A first post row is formed in which a plurality of conductive posts electrically connecting the first conductive layer and the second conductive layer are arranged along the longitudinal direction of the dielectric portion, A plurality of conductive posts are arranged along the longitudinal direction, electrically connecting the first conductive layer and the second conductive layer, and a second row of posts is provided parallel to the first row of posts, The device comprises an internal conductive layer disposed within the dielectric portion, electrically connected to the first conductive layer and the second conductive layer via the first and second post rows, extending along the longitudinal direction and including a gap provided on the first post row side.

[0010] Furthermore, in the substrate integrated waveguide, The dielectric portion is A first dielectric layer provided on the first conductive layer, The material may also include a second dielectric layer provided on the internal conductive layer and connected to the first dielectric layer via the gap.

[0011] Furthermore, in the substrate integrated waveguide, The gap may be provided in close proximity to the first row of posts.

[0012] Furthermore, in the substrate integrated waveguide, The thicknesses of the first dielectric layer and the second dielectric layer may be equal to each other, and the width of the gap may be equal to the thickness of the first dielectric layer.

[0013] Furthermore, in the substrate integrated waveguide, The dielectric portion further comprises a second internal conductive layer, which extends along the longitudinal direction and includes a second gap provided on the second post row side, and is disposed above the internal conductive layer within the dielectric portion. The dielectric portion is A first dielectric layer provided on the first conductive layer, A second dielectric layer is provided on the internal conductive layer and connected to the first dielectric layer via the gap, The material may also include a third dielectric layer provided on the second internal conductive layer and connected to the second dielectric layer via the second gap.

[0014] Furthermore, in the substrate integrated waveguide, A second internal conductive layer is provided within the dielectric portion and is located above the internal conductive layer, and includes a second gap extending along the longitudinal direction and provided on the second post row side. The dielectric portion further comprises a third internal conductive layer, which extends along the longitudinal direction and includes a third gap provided on the first post row side, and is disposed above the second internal conductive layer within the dielectric portion, The dielectric portion is A first dielectric layer provided on the first conductive layer, A second dielectric layer provided on the inner conductive layer and connected to the first dielectric layer through the gap; A third dielectric layer provided on the second inner conductive layer and connected to the second dielectric layer through the second gap; A fourth dielectric layer provided on the third inner conductive layer and connected to the third dielectric layer through the third gap may be included.

[0015] Also, in the substrate integrated waveguide, The inner conductive layer may be provided with a first signal port for inputting a signal from a stripline or a microstrip line, and a second signal port for outputting a signal input from the first signal port and propagated as an electromagnetic wave between the first post row and the second post row to a stripline or a microstrip line.

[0016] Also, in the substrate integrated waveguide, The first signal port and / or the second signal port May be defined by a first port defining gap having a first portion extending in a width direction orthogonal to the longitudinal direction, and a second portion connected to the first portion and extending in a direction obliquely intersecting the longitudinal direction and connected to the gap. And a second port defining gap having a third portion extending substantially parallel to the first portion, and a fourth portion connected to the third portion and extending in a direction obliquely intersecting the longitudinal direction and away from the second portion.

[0017] Also, in the substrate integrated waveguide, The second port defining gap may include an extension extending deeper than the gap along the fourth portion.

[0018] Also, in the substrate integrated waveguide, The first signal port and / or the second signal port may have a tapered base end portion. [Effects of the Invention]

[0019] According to the present invention, it is possible to provide a substrate-integrated waveguide that can reduce the waveguide width while maintaining transmission characteristics. [Brief explanation of the drawing]

[0020] [Figure 1] This is a perspective view of a substrate integrated waveguide according to the first embodiment. [Figure 2] This is an exploded perspective view of a substrate-integrated waveguide according to the first embodiment. [Figure 3] This is a plan view of the internal conductive layer of a substrate-integrated waveguide according to the first embodiment. [Figure 4] This is a cross-sectional view of a substrate-integrated waveguide according to the first embodiment. [Figure 5] This graph shows an example of the analysis results of the transmission characteristics of a substrate-integrated waveguide according to the first embodiment. [Figure 6] This is a cross-sectional view of a substrate-integrated waveguide according to the second embodiment. [Figure 7] This is a cross-sectional view of a substrate-integrated waveguide according to a modified example of the third embodiment. [Figure 8] This is a perspective view of a substrate-integrated waveguide according to the fourth embodiment. [Figure 9] This is a plan view of the internal conductive layer of a substrate-integrated waveguide according to the fourth embodiment. [Figure 10] This is a cross-sectional view of a substrate-integrated waveguide along line II in Figure 9. [Figure 11] This is a perspective view of a substrate integrated waveguide according to the fifth embodiment. [Figure 12] This is a plan view of the internal conductive layer of a substrate-integrated waveguide according to the fifth embodiment. [Figure 13] This graph shows an example of the analysis results of the transmission characteristics of a substrate-integrated waveguide according to the fifth embodiment. [Modes for carrying out the invention]

[0021] Embodiments of the present invention will be described below with reference to the drawings. In each figure, components having equivalent functions are denoted by the same reference numerals. The drawings are schematic and mainly show characteristic parts of each embodiment, and the relationship between thickness and planar dimensions, the ratio of the thickness of each layer, etc., may differ from reality.

[0022] In this specification, terms such as "parallel," "orthogonal," and "equal," as well as dimensions and values ​​of physical properties used to specify shapes, geometric conditions, physical properties, and their degrees, shall not be strictly interpreted, but shall be interpreted to include a range that allows for the expectation of similar functionality.

[0023] (First Embodiment) The substrate integrated waveguide according to the first embodiment will be described with reference to Figures 1 to 4. Figure 1 is a perspective view of the substrate integrated waveguide 1 according to this embodiment, Figure 2 is an exploded perspective view of the substrate integrated waveguide 1, Figure 3 is a plan view of the internal conductive layer 31 of the substrate integrated waveguide 1, and Figure 4 is a cross-sectional view of the substrate integrated waveguide 1.

[0024] The substrate integrated waveguide 1 comprises a dielectric portion 10, a lower conductive layer 21 (first conductive layer) disposed on the lower surface of the dielectric portion 10, an upper conductive layer 22 (second conductive layer) disposed on the upper surface of the dielectric portion 10, a post row PC1 (first post row), a post row PC2 (second post row), and an internal conductive layer 31 disposed inside the dielectric portion 10.

[0025] The dielectric portion 10 includes a dielectric layer 11 (first dielectric layer) provided on the lower conductive layer 21 and a dielectric layer 12 (second dielectric layer) provided on the internal conductive layer 31. The dielectric layer 12 is connected to the dielectric layer 11 via a gap G1. The thicknesses of the dielectric layer 11 and the dielectric layer 12 are equal. The thicknesses of the dielectric layer 11 and the dielectric layer 12 may be different.

[0026] The materials of dielectric layers 11 and 12 are not particularly limited and may be flexible materials such as liquid crystal polymer (LCP), polyimide (PI), modified polyimide (MPI), polyethylene naphthalate (PEN), polyether ether ketone (PEEK), fluororesin (PFA, PTFE, etc.), or rigid materials such as ceramic or glass epoxy.

[0027] Furthermore, the dielectric layer 11 and / or dielectric layer 12 may include an adhesive layer (not shown) at the boundary between dielectric layer 11 and dielectric layer 12. For example, dielectric layer 12 includes an adhesive layer between itself and the internal conductive layer 31. Preferably, the adhesive layer has a dielectric constant close to that of dielectric layers 11 and 12.

[0028] The lower conductive layer 21 and the upper conductive layer 22 constitute the ground plane of the substrate integrated waveguide 1. The lower conductive layer 21 is provided on the lower surface of the dielectric layer 11, and the upper conductive layer 22 is provided on the upper surface of the dielectric layer 12, with the lower conductive layer 21 and the upper conductive layer 22 sandwiching the dielectric portion 10. The lower conductive layer 21 and the upper conductive layer 22 are made of conductive materials such as copper foil and electrolytic copper.

[0029] The internal conductive layer 31 faces the lower conductive layer 21 and the upper conductive layer 22, and is electrically connected to the lower conductive layer 21 and the upper conductive layer 22 via post rows PC1 and PC2.

[0030] A gap G1 is provided in the internal conductive layer 31. This gap G1 extends along the longitudinal direction of the dielectric portion 10 and is located on the post row PC1 side. In this way, the internal conductive layer 31 is divided into two parts in the waveguide direction (longitudinal direction) via the gap G1. Note that the gap G1 may also be located on the post row PC2 side.

[0031] In this embodiment, as shown in Figure 4, the gap G1 is positioned in contact with the land of the via 41a in the internal conductive layer 31. By providing the gap G1 in close proximity to the post row PC1 in this way, the width of the substrate integrated waveguide can be effectively reduced. In order to reduce the width of the substrate integrated waveguide, the gap G1 may be provided as close as possible to the post row PC1 (multiple conductive posts 41), or it may be provided so as to be in contact with multiple conductive posts 41.

[0032] In this embodiment, the thicknesses of dielectric layer 11 and dielectric layer 12 are equal to each other, and the width of the gap G1 is equal to the thickness of dielectric layer 11 (dielectric layer 12). This makes it possible to obtain good transmission characteristics.

[0033] Post rows PC1 and PC2 are arranged parallel to each other along the longitudinal direction of the substrate integrated waveguide 1. Post row PC1 consists of a plurality of conductive posts 41 arranged along the longitudinal direction of the substrate integrated waveguide 1. Each conductive post 41 penetrates the dielectric portion 10 in the thickness direction and electrically connects the lower conductive layer 21 and the upper conductive layer 22. Post row PC2 consists of a plurality of conductive posts 42 arranged along the longitudinal direction of the substrate integrated waveguide 1. Each conductive post 42 penetrates the dielectric portion 10 in the thickness direction and electrically connects the lower conductive layer 21 and the upper conductive layer 22.

[0034] Conductive post 41 has a via 41a connecting the lower conductive layer 21 and the inner conductive layer 31, and a via 41b connecting the inner conductive layer 31 and the upper conductive layer 22. Conductive post 42 has a via 42a connecting the lower conductive layer 21 and the inner conductive layer 31, and a via 42b connecting the inner conductive layer 31 and the upper conductive layer 22.

[0035] In this embodiment, as shown in Figure 4, via 41b is provided directly above via 41a, and via 42b is provided directly above via 42a. However, it is not limited to this, and via 41b may be provided at a position away from via 41a when viewed in the thickness direction of the dielectric portion 10. Similarly, via 42b may be provided at a position away from via 42a.

[0036] Furthermore, in this embodiment, each via constituting the conductive posts 41 and 42 is a filled via in which a through-hole in the dielectric layer is filled with a conductive material. However, it is not limited to this, and each via may be a through-hole or other form of interlayer connection path.

[0037] The substrate integrated waveguide 1 of this embodiment has a structure in which two transmission paths are folded. This will be explained in detail with reference to Figure 4. In Figure 4, length L1 is the length from post row PC2 (vias 42a, 42b) to gap G1 plus the width of gap G1 (L3). Length L2 is the length from post row PC2 to gap G1. Length L3 is the width of gap G1. Length L4 is the length of the protruding portion of the land of via 41a in the internal conductive layer 31. Thickness d is the thickness of the internal conductive layer 31.

[0038] The substrate integrated waveguide 1 has a structure in which a waveguide with a width of L1 + L2 is folded into a U-shape with a gap G1. In such a structure, the sum of the lengths L1, L2 and thickness d (L1 + L2 + d) corresponds to the waveguide width x in equation (1). Therefore, according to this embodiment, the cutoff frequency f c If the same properties are maintained, the width of the substrate-integrated waveguide can be reduced.

[0039] As described above, the substrate integrated waveguide 1 according to this embodiment includes an internal conductive layer 31 within the dielectric portion 10. The internal conductive layer 31 has a gap G1 that extends along the longitudinal direction of the dielectric portion 10 and is provided on the post row PC1 (or post row PC2) side, and the dielectric layer 12 is connected to the dielectric layer 11 via the gap G1. In such a substrate integrated waveguide 1, the dielectric layer 11 and the dielectric layer 12 as a whole form a waveguide for electromagnetic waves to propagate in a single transmission mode. For example, electromagnetic waves propagate through the waveguide in the TE10 mode transmission mode, where the electric field strength is strongest at the gap G1 of the internal conductive layer 31.

[0040] According to the first embodiment, electromagnetic waves propagate through the substrate integrated waveguide 1 in a U-shaped folded state at the gap G1. Therefore, if the cutoff frequency is the same, the width dimension of the substrate integrated waveguide can be reduced by approximately half.

[0041] <Examples> Next, we will explain the results of the electromagnetic field simulation analysis of the transmission characteristics of the substrate integrated waveguide 1. Ansys HFSS was used as the simulation software. The dielectric constant of the dielectric layers 11 and 12 was set to 3.3, and the dielectric loss tangent was set to 0.002. The dimensions of each part of the substrate integrated waveguide 1 were set to the values ​​shown below, and the cutoff frequency was set to 30 GHz.

[0042] Thickness of the lower conductive layer 21: 0.03 mm Thickness of the upper conductive layer 22: 0.03 mm Thickness (d) of the internal conductive layer 31: 0.01 mm Diameter of conductive post 41: 0.2 mm Diameter of conductive post 42: 0.2 mm Thickness of dielectric layer 11: 0.2 mm Thickness of dielectric layer 12: 0.2 mm Length L1: 1.45mm Length L2: 1.25mm Length L3: 0.2mm Length L4: 0.05mm Waveguide length: 10mm

[0043] Figure 5 is an example of a graph showing the analysis results of the transmission characteristics of the substrate integrated waveguide 1 according to the first embodiment. From the analysis results, it was confirmed that the substrate integrated waveguide 1 can obtain transmission characteristics similar to those of a normal substrate integrated waveguide.

[0044] <Manufacturing method for substrate-integrated waveguide 1> The above-described substrate integrated waveguide 1 can be easily manufactured using known techniques for manufacturing flexible printed circuit boards. An example of the manufacturing method is as follows.

[0045] 1. Prepare a double-sided copper-clad laminate and form an internal conductive layer 31 with a gap G1 by etching one of the copper foils. Also, form a confort mask for vias by etching the copper foil.

[0046] 2. By irradiating the conformal mask with laser light, multiple bottomed via holes are formed, penetrating the dielectric layer (corresponding to dielectric layer 11) and exposing the copper foil on the other side of the double-sided copper-clad laminate (corresponding to the lower conductive layer 21) at the bottom. Then, conductive paste is filled into each bottomed via hole. The filled conductive paste becomes vias 41a and 42a.

[0047] 3. Prepare a single-sided copper-clad laminate and bond an adhesive protective film (a protective film with an adhesive layer formed on top) to the dielectric layer. By irradiating with laser light, multiple bottomed via holes are formed, penetrating the adhesive protective film and dielectric layer, exposing the copper foil at the bottom. Then, conductive paste is filled into each bottomed via hole. The filled conductive paste becomes vias 41b and 42b.

[0048] 4. Peel the protective film from the adhesive protective film, allowing the tip of the conductive paste to protrude from the adhesive layer.

[0049] 5. After bonding the two copper-clad laminates together via an adhesive layer, they are subjected to heating and pressurizing to integrate them. This results in a substrate-integrated waveguide 1.

[0050] (Second embodiment) Next, with reference to Figure 6, a substrate integrated waveguide 1A according to the second embodiment will be described. Figure 6 is a cross-sectional view of the substrate integrated waveguide 1A according to this embodiment. One of the differences between the second embodiment and the first embodiment is the number of internal conductive layers. In the second embodiment, two internal conductive layers are provided.

[0051] The second embodiment will now be described, focusing on the differences from the first embodiment.

[0052] In this embodiment, the dielectric portion 10 includes a dielectric layer 11, a dielectric layer 12, and a dielectric layer 13. An internal conductive layer 31 with a gap G1 is disposed between dielectric layer 11 and dielectric layer 12. An internal conductive layer 32 with a gap G2 is disposed between dielectric layer 12 and dielectric layer 13. The gap G2 extends along the longitudinal direction of the dielectric portion 10 and is provided on the post row PC2 side.

[0053] As shown in Figure 6, the gap G2 is positioned in contact with the land of the via 42b in the internal conductive layer 32. By providing the gap G2 in close proximity to the post row PC2 in this way, the width of the substrate integrated waveguide can be effectively reduced. In order to reduce the width of the substrate integrated waveguide, the gap G2 may be provided as close as possible to the post row PC2 (multiple conductive posts 42), or it may be provided so as to be in contact with multiple conductive posts 42.

[0054] The dielectric layer 13 is connected to the dielectric layer 12 via a gap G2. The dielectric layer 13 is an example of a third dielectric layer in the claims. The material of the dielectric layer 13 is not particularly limited, and the same material as that used for dielectric layers 11 and 12 can be applied.

[0055] In this embodiment, the thicknesses of dielectric layers 11, 12, and 13 are equal to each other. Also, the widths of gaps G1 and G2 are equal to each other. Furthermore, the thickness of dielectric layers 11, 12, and 13 is equal to the width of gap G1 (gap G2). This improves the transmission characteristics of the substrate integrated waveguide 1A.

[0056] In this embodiment, the conductive post 41 includes vias 41a, 41b, and 41c. Via 41a connects the lower conductive layer 21 to the inner conductive layer 31. Via 41b connects the inner conductive layer 31 to the inner conductive layer 32. Via 41c connects the inner conductive layer 32 to the upper conductive layer 22. Similarly, the conductive post 42 includes vias 42a, 42b, and 42c. Via 42a connects the lower conductive layer 21 to the inner conductive layer 31. Via 42b connects the inner conductive layer 31 to the inner conductive layer 32. Via 42c connects the inner conductive layer 32 to the upper conductive layer 22.

[0057] As described above, the substrate integrated waveguide 1A according to the second embodiment further comprises an internal conductive layer 32 located above the internal conductive layer 31 within the dielectric portion 10, compared to the substrate integrated waveguide 1 of the first embodiment. This internal conductive layer 32 extends along the longitudinal direction of the dielectric portion 10 and includes a gap G2 provided on the post row PC2 side. The dielectric layer 12 is connected to the dielectric layer 11 via the gap G1, and the dielectric layer 13 is connected to the dielectric layer 12 via the gap G2. Thus, in the substrate integrated waveguide 1A, the dielectric layer 11, dielectric layer 12, and dielectric layer 13 as a whole form a waveguide for electromagnetic waves to propagate in a single transmission mode.

[0058] Therefore, according to the second embodiment, electromagnetic waves propagate through the substrate integrated waveguide 1A in an S-shaped folded state at gaps G1 and G2. Consequently, if the cutoff frequency is the same, the width dimension of the substrate integrated waveguide can be further reduced compared to the first embodiment.

[0059] (Third embodiment) Next, with reference to Figure 7, a substrate integrated waveguide 1B according to the third embodiment will be described. Figure 7 is a cross-sectional view of the substrate integrated waveguide 1B according to this embodiment. One of the differences between the third embodiment and the first and second embodiments is the number of internal conductive layers. In the third embodiment, three internal conductive layers are provided.

[0060] The third embodiment will now be described, focusing on the differences from the second embodiment.

[0061] In this embodiment, the dielectric portion 10 includes a dielectric layer 11, a dielectric layer 12, a dielectric layer 13, and a dielectric layer 14. An internal conductive layer 31 with a gap G1 is disposed between dielectric layer 11 and dielectric layer 12. An internal conductive layer 32 with a gap G2 is disposed between dielectric layer 12 and dielectric layer 13. An internal conductive layer 33 with a gap G3 is disposed between dielectric layer 13 and dielectric layer 14. The gap G3 extends along the longitudinal direction of the dielectric portion 10 and is provided on the post row PC1 side.

[0062] As shown in Figure 7, the gap G3 is positioned in contact with the land of the via 41c in the internal conductive layer 33. By providing the gap G3 in close proximity to the post row PC3 in this way, the width of the substrate integrated waveguide can be effectively reduced. In order to reduce the width of the substrate integrated waveguide, the gap G3 may be provided as close as possible to the post row PC1 (multiple conductive posts 41), or it may be provided so as to be in contact with multiple conductive posts 41.

[0063] The dielectric layer 14 is connected to the dielectric layer 13 via a gap G3. The dielectric layer 14 is an example of the fourth dielectric layer in the claims. The material of the dielectric layer 14 is not particularly limited, and the same materials as those used for dielectric layers 11, 12, and 13 can be applied.

[0064] In this embodiment, the thicknesses of dielectric layers 11, 12, 13, and 14 are equal to each other. The widths of gaps G1, G2, and G3 are equal to each other. The thickness of dielectric layers 11, 12, 13, and 14 is equal to the width of gap G1 (gap G2, G3). This improves the transmission characteristics of the substrate integrated waveguide 1B.

[0065] In this embodiment, the conductive post 41 includes vias 41a, 41b, 41c, and 41d. Via 41c connects the internal conductive layer 32 to the internal conductive layer 33. Via 41d connects the internal conductive layer 33 to the upper conductive layer 22. Similarly, the conductive post 42 includes vias 42a, 42b, 42c, and 42d. Via 42c connects the internal conductive layer 32 to the internal conductive layer 33. Via 42d connects the internal conductive layer 33 to the upper conductive layer 22.

[0066] As described above, the substrate integrated waveguide 1B according to the third embodiment further comprises an internal conductive layer 33 located above the internal conductive layer 32 within the dielectric portion 10, compared to the substrate integrated waveguide 1A of the second embodiment. This internal conductive layer 33 extends along the longitudinal direction of the dielectric portion 10 and includes a gap G3 provided on the post row PC1 side. Dielectric layer 12 is connected to dielectric layer 11 via gap G1, dielectric layer 13 is connected to dielectric layer 12 via gap G2, and dielectric layer 14 is connected to dielectric layer 13 via gap G3. Thus, in the substrate integrated waveguide 1B, dielectric layers 11, 12, 13, and 14 together form a waveguide for electromagnetic waves to propagate in a single transmission mode.

[0067] Therefore, according to the third embodiment, electromagnetic waves propagate within the substrate integrated waveguide 1B in a bellows-like folded state through gaps G1, G2, and G3. Consequently, if the cutoff frequency is the same, the width dimension of the substrate integrated waveguide can be further reduced compared to the second embodiment.

[0068] As described in the first to third embodiments above, the substrate integrated waveguides 1, 1A, and 1B comprise a plurality of dielectric layers connected via gaps in the internal conductive layers. The electromagnetic waves of the signal propagate by forming a single electromagnetic field pattern across the plurality of dielectric layers. As a result, according to each of the above embodiments, the width dimension of the substrate integrated waveguide can be reduced. It is also possible to have five or more dielectric layers (four or more internal conductive layers).

[0069] (Fourth embodiment) Next, with reference to Figures 8 to 10, the substrate integrated waveguide 1C according to the fourth embodiment will be described. Figure 8 is a perspective view of the substrate integrated waveguide 1C, Figure 9 is a plan view of the internal conductive layer 31A of the substrate integrated waveguide 1C, and Figure 10 is a cross-sectional view of the substrate integrated waveguide 1C along line II in Figure 9.

[0070] One of the differences between the first and fourth embodiments is that in the fourth embodiment, the substrate integrated waveguide 1C is integrally connected to the stripline. The fourth embodiment will now be described, focusing on the differences from the first embodiment.

[0071] As shown in Figure 8, the substrate integrated waveguide 1C includes, in addition to the configuration of the substrate integrated waveguide 1 according to the first embodiment, a signal port Sp1 for inputting signals from the stripline and a signal port Sp2 for outputting signals to the stripline. Conductive posts 43 are provided at both ends of the substrate integrated waveguide 1C to suppress electromagnetic wave leakage.

[0072] Signal port Sp1 is connected to the signal lines of the stripline, receiving signals from the stripline and outputting them to the integrated waveguide. More specifically, the signal transmitted along the stripline is mode-converted at signal port Sp1 and propagates as an electromagnetic wave within the integrated waveguide. Signal port Sp2 receives signals from signal port Sp1 and outputs the signal, which has propagated as an electromagnetic wave between post rows PC1 and PC2, to the stripline. More specifically, when the electromagnetic wave reaches signal port Sp2, it is mode-converted again and transmitted through the stripline.

[0073] As shown in Figures 8 and 9, the signal ports Sp1 and Sp2 are defined by port definition gaps Ga and Gb. That is, the internal conductive layer 31A of the substrate integrated waveguide 1C is provided with a port definition gap Ga and a gap Gb connected to gap G1 for each signal port. The port definition gaps Ga and Gb function as mode conversion slits.

[0074] The port delimiting gap Ga has a first portion Ga1 and a second portion Ga2. The first portion Ga1 extends in a direction perpendicular to the longitudinal direction (width direction) of the dielectric portion 10. The second portion Ga2 connects to the first portion Ga1 and extends in a direction oblique to the longitudinal direction to connect to gap G1. The port delimiting gap Gb has a third portion Gb1 and a fourth portion Gb2. The third portion Gb1 extends substantially parallel to the first portion Ga1. The fourth portion Gb2 connects to the third portion Gb1 and extends in a direction oblique to the longitudinal direction and away from the second portion Ga2.

[0075] The signal ports Sp1 and Sp2 have a base portion Spe defined by a second portion Ga2 and a fourth portion Gb2. The base portion Spe is tapered, narrowing in width towards the stripline side. This reduces impedance mismatch between the stripline and the SIW. As a result, signal reflections in the signal ports are suppressed, and the voltage standing wave ratio (VSWR) can be improved.

[0076] As described above, according to the fourth embodiment, the substrate integrated waveguide 1C can be configured integrally with the stripline.

[0077] In addition, striplines may be connected to the substrate integrated waveguide 1A described in the second embodiment or the substrate integrated waveguide 1B described in the third embodiment. In that case, signal ports Sp1 and Sp2 should be provided in one of the multiple internal conductive layers.

[0078] Furthermore, signal ports Sp1 and / or Sp2 do not necessarily have tapered base ends Spe.

[0079] Additionally, signal port Sp1 and / or signal port Sp2 may be connected to a microstrip line.

[0080] (Fifth embodiment) Next, with reference to Figures 11 and 12, a substrate integrated waveguide 1D according to a fifth embodiment will be described. Figure 11 is a perspective view of the substrate integrated waveguide 1D, and Figure 12 is a plan view of the internal conductive layer 31B of the substrate integrated waveguide 1D.

[0081] One of the differences between the fourth and fifth embodiments is that the substrate integrated waveguide 1D according to the fifth embodiment has an extension Ge in the port delimiting gap Gb. The fifth embodiment will now be described, focusing on the differences from the fourth embodiment.

[0082] Similar to the fourth embodiment, the internal conductive layer 31B of the substrate integrated waveguide 1D is provided with a port definition gap Ga and a Gb connected to gap G1 for each of the signal ports Sp1 and Sp2.

[0083] As shown in Figures 11 and 12, the port definition gap Gb has an extension Ge. This extension Ge extends further into the gap G1 along the fourth portion Gb2. This further reduces impedance mismatch between the stripline and the SIW and further suppresses signal reflection.

[0084] Figure 13 shows an example of the results of an electromagnetic field analysis performed from signal port Sp1 to signal port Sp2 in the substrate integrated waveguide 1D according to this embodiment. The dimensions, dielectric constant, cutoff frequency, and other values ​​of each part of the substrate integrated waveguide 1D were set to the same values ​​as those used in the simulation of the substrate integrated waveguide 1 described with reference to Figure 5. However, the waveguide length was set to 100 mm.

[0085] As shown in the graph in Figure 13, good transmission characteristics were confirmed at frequencies above the set cutoff frequency (30 GHz). It can be seen that ripple is suppressed because impedance mismatch is reduced by providing the extension Ge. It was also confirmed that signal mode conversion from stripline structure to SIW and from SIW to stripline structure is possible.

[0086] As described above, according to the fifth embodiment, by providing an extension Ge in the port definition gap Gb, impedance mismatch between the stripline and the SIW can be further reduced, and signal reflection can be further suppressed.

[0087] Based on the above description, those skilled in the art may conceive of additional effects and various modifications of the present invention, but the embodiments of the present invention are not limited to the individual embodiments described above. Components from different embodiments may be combined as appropriate. Various additions, modifications, and partial deletions are possible without departing from the conceptual idea and spirit of the present invention derived from the claims and their equivalents. [Explanation of Symbols]

[0088] 1,1A,1B,1C,1D Integrated waveguide 10 Dielectric part 11, 12, 13 Dielectric layer 21 Lower conductive layer 22 Upper conductive layer 31,31A,31B,32,33 Internal conductive layer 41, 42, 43 Conductive posts 41a, 41b, 42a, 42b Via G1, G2, G3 gap Ga, Gb Port Definition Gap Re extension PC1, PC2 Post Queue Sp1, Sp2 signal ports Spe (signal port) base

Claims

1. Dielectric part, A first conductive layer disposed on the lower surface of the dielectric portion, A second conductive layer disposed on the upper surface of the dielectric portion, A first row of posts is arranged along the longitudinal direction of the dielectric portion, wherein a plurality of conductive posts electrically connecting the first conductive layer and the second conductive layer are arranged along the longitudinal direction of the dielectric portion. A plurality of conductive posts electrically connecting the first conductive layer and the second conductive layer are arranged along the longitudinal direction, and a second row of posts is provided parallel to the first row of posts, An internal conductive layer is disposed inside the dielectric portion and electrically connected to the first conductive layer and the second conductive layer via the first and second post rows, extending along the longitudinal direction and including a gap provided on the first post row side, A substrate-integrated waveguide equipped with a waveguide.

2. The dielectric portion is A first dielectric layer provided on the first conductive layer, A second dielectric layer is provided on the internal conductive layer and connected to the first dielectric layer via the gap, A substrate integrated waveguide according to claim 1, including the above.

3. The substrate integrated waveguide according to claim 2, wherein the gap is provided in close proximity to the first row of posts.

4. The substrate integrated waveguide according to claim 2, wherein the thicknesses of the first dielectric layer and the second dielectric layer are equal to each other, and the width of the gap is equal to the thickness of the first dielectric layer.

5. The dielectric portion further comprises a second internal conductive layer, which extends along the longitudinal direction and includes a second gap provided on the second post row side, and is disposed above the internal conductive layer within the dielectric portion. The dielectric portion is A first dielectric layer provided on the first conductive layer, A second dielectric layer is provided on the internal conductive layer and connected to the first dielectric layer via the gap, A substrate integrated waveguide according to claim 1, comprising: a third dielectric layer provided on the second internal conductive layer and connected to the second dielectric layer via the second gap.

6. A second internal conductive layer is disposed above the internal conductive layer within the dielectric portion, including a second gap that extends along the longitudinal direction and is provided on the second post row side, The dielectric portion further comprises a third internal conductive layer, which extends along the longitudinal direction and includes a third gap provided on the first post row side, and is disposed above the second internal conductive layer within the dielectric portion, The dielectric portion is A first dielectric layer provided on the first conductive layer, A second dielectric layer is provided on the internal conductive layer and connected to the first dielectric layer via the gap, A third dielectric layer is provided on the second internal conductive layer and connected to the second dielectric layer via the second gap, A substrate integrated waveguide according to claim 1, comprising: a fourth dielectric layer provided on the third internal conductive layer and connected to the third dielectric layer via the third gap.

7. The substrate integrated waveguide according to claim 1, wherein the internal conductive layer is provided with a first signal port for receiving a signal from a stripline or microstrip line, and a second signal port for outputting a signal received from the first signal port and propagated as an electromagnetic wave between the first post row and the second post row to the stripline or microstrip line.

8. The first signal port and / or the second signal port are A first port delimiting gap having a first portion extending in a width direction perpendicular to the longitudinal direction, and a second portion connected to the first portion and extending in a direction oblique to the longitudinal direction and connected to the gap, The substrate integrated waveguide according to claim 7, defined by a second port defining gap having a third portion extending substantially parallel to the first portion and a fourth portion connected to the third portion, oblique to the longitudinal direction, and extending away from the second portion.

9. The substrate integrated waveguide according to claim 8, wherein the second port defining gap includes an extension that extends along the fourth portion beyond the gap.

10. The substrate integrated waveguide according to claim 7, wherein the first signal port and / or the second signal port have tapered base ends.

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