Flash memory device and its programming method

Abstract

The present invention provides a flash memory device and a programming method thereof that can reduce the time required for programming operations. [Solution] The programming method includes the steps of: selecting a target memory area from multiple memory areas to perform a programming operation on, the target memory area being divided into multiple memory cell groups; performing programming verification on the target memory area; and, if the target memory area does not pass the programming verification, setting one programming time segment of the memory cell group to overlap with another programming time segment of the memory cell group, thereby programming the memory cell group.

Description

Technical Field

[0001] The present invention relates to control technology of memory devices, and particularly to flash memory devices and their programming methods.

Background Art

[0002] Flash memory devices are mainly divided into two types: NOR type and NAND type. Compared with NAND type flash memory devices, the programming operation of NOR type flash memory devices takes a longer time to execute. However, NOR type flash memory devices can provide a complete address bus and data bus, and can access any memory cell of the device. Therefore, how to shorten the programming time of NOR type flash memory devices has become one of the important issues in this technical field.

Summary of the Invention

Problems to be Solved by the Invention

[0003] The present invention provides a flash memory device and its programming method that can shorten the time required for programming operations.

[0022]

Means for Solving the Problems

[0004] The programming method of the flash memory device of the present invention includes: selecting a target memory area for programming operations from a plurality of memory areas, where the target memory area is divided into a plurality of memory cell groups; executing programming verification on the target memory area; when the target memory area fails the programming verification, setting one programming time segment of the memory cell groups to overlap with another programming time segment of the memory cell groups, so that the memory cell groups are programmed in sequence.

[0005] The flash memory device of the present invention includes a memory array and a memory control circuit. The memory array has a plurality of memory regions. The memory control circuit is connected to the memory array and configured to select a target memory region from the plurality of memory regions for which a programming operation is to be performed. The target memory region is divided into a plurality of memory cell groups. The memory control circuit performs a programming verification on the target memory region. If the target memory region fails the programming verification, the memory control circuit sets one programming time segment of one of the memory cell groups to overlap with another programming time segment of the memory cell group, thereby programming the memory cell groups sequentially. [Effects of the Invention]

[0006] As described above, the flash memory device and its programming method of the present invention allow the programming time segments of multiple memory cell groups to overlap. This reduces the time required for programming operations.

[0007] To make the above-mentioned features and advantages of the present invention clearer and easier to understand, embodiments will be described in detail below with reference to the accompanying drawings. [Brief explanation of the drawing]

[0008] [Figure 1] This is a block diagram of a flash memory device according to one embodiment of the present invention. [Figure 2] This is a step-by-step flowchart of a programming method for a flash memory device according to some embodiments of the present invention. [Figure 3A] This is an example of a programming method for a flash memory device according to some embodiments of the present invention. [Figure 3B] This is an example of a programming method for a flash memory device according to some embodiments of the present invention. [Figure 3C]This is an example of a programming method for a flash memory device according to some embodiments of the present invention. [Figure 3D] This is an example of a programming method for a flash memory device according to some embodiments of the present invention. [Figure 4] This is a step-by-step flowchart of a programming method for a flash memory device according to some embodiments of the present invention. [Figure 5] This is an example of a programming method for a flash memory device according to some embodiments of the present invention. [Modes for carrying out the invention]

[0009] Referring to Figure 1, the flash memory device 100 according to one embodiment of the present invention is a NOR type, for example, including a memory array 110 and a memory control circuit 120. The memory array 110 has a plurality of memory areas 112. Each memory area 112 is composed of a plurality of memory cells. The memory cells according to this embodiment are, for example, ETOX structured. Note that the present invention does not limit the number of memory areas 112 or the number of memory cells constituting one memory area 112.

[0010] The memory control circuit 120 is connected to the memory array 110. The memory control circuit 120 can select a target memory area 112T from among multiple memory areas 112 of the memory array 110 in response to a received selection command CMD. In this embodiment, the target memory area 112T may be divided into eight memory cell groups MG1 to MG8. For example, each memory cell group MG1 to MG8 can correspond to 16 bits. Memory cell group MG1 includes 16 memory cells corresponding to the upper 16 bits of the target memory area 112T, memory cell group MG2 includes 16 memory cells corresponding to the 16 bits immediately following the bits of memory cell group MG1 in the target memory area 112T, and so on. However, the present invention does not limit the size or the number of bits corresponding to each memory cell group MG1 to MG8, and those skilled in the art can adjust them as appropriate according to their actual needs.

[0011] The memory control circuit 120 is designed, for example, by a state machine, central processing unit, or other programmable general-purpose or dedicated microprocessor, digital signal processor, programmable controller, application-specific integrated circuit, programmable logic device, or other similar device, or a combination of these devices, in addition to a hardware description language or any other conventional digital circuit design method, such as a field-programmable logic gate array or a complex programmable logic device. The hardware circuit may be implemented by the method described above. In Figure 1, the memory control circuit 120 is located on the flash memory device 100, but the memory control circuit 120 may be a device independent of the flash memory device 100.

[0012] In flash memory device programming operations, in addition to programming time, the programming current flowing from the drain to the source of the memory cell is also an important parameter that can be used to save power, and is therefore crucial for green semiconductor technology. When programming a specific number of memory cells, a regulator with a charge pump circuit can be used to supply a stable drain voltage (e.g., 4 volts) to the memory cells to generate the programming current, ensuring that programming is performed successfully.

[0013] However, the programming current generated by all memory cells during programming decreases over time, sometimes to half of its original value, which can impair the efficiency of the charge pump circuit. Therefore, in this invention, taking advantage of the above characteristics and assuming that the peak value of the programming current does not exceed the load of the charge pump circuit, the programming time segments of multiple memory cell groups are made to overlap, thereby shortening the time required for the programming operation.

[0014] Referring to Figures 1 and 2, the programming method for the flash memory device according to this embodiment is applied to the flash memory device 100 shown in Figure 1. Hereinafter, each step of the programming method according to the embodiment of the present invention will be described by combining the various components of the flash memory device 100.

[0015] First, in step S200, the memory control circuit 120 selects a target memory area 112T from among the multiple memory areas 112 of the memory array 110 in response to the received selection command CMD. The target memory area 112T is divided into eight memory cell groups MG1 to MG8.

[0016] Next, in step S202, the memory control circuit 120 performs programming verification on the target memory area 112T. Specifically, the memory control circuit 120 compares the bit data (e.g., 16 bits) formed by each memory cell group MG1 to MG8 of the target memory area 112T with the corresponding data pattern (e.g., 16 bits) and determines whether the memory cell groups MG1 to MG8 of the target memory area 112T have passed the programming verification. More specifically, in the example of programming verification, the memory control circuit 120 can determine whether the threshold voltage (Vth) of each memory cell in each memory cell group MG1 to MG8 satisfies the specified range for each bit value of the corresponding data pattern. If the bit value of the data pattern is "0", the corresponding threshold voltage must be greater than the preset programming verification reference voltage, and if the bit value of the data pattern is "1", the corresponding threshold voltage must be less than the preset programming verification reference voltage.

[0017] If the threshold voltages of all memory cells in memory cell groups MG1 to MG8 match the specified range of bit values ​​for the corresponding data patterns, it means that there are no defective memory cells in memory cell groups MG1 to MG8, that is, all have passed the programming verification. In this case, the memory control circuit 120 determines that the target memory area 112T has passed the programming verification. If the threshold voltages of the memory cells in memory cell groups MG1 to MG8 do not match the specified range of bit values ​​for the corresponding data patterns, it means that there are defective memory cells in memory cell groups MG1 to MG8, that is, not all have passed the programming verification. In this case, the memory control circuit 120 determines that the target memory area 112T has not passed the programming verification. A so-called "defective memory cell" refers to a memory cell that did not pass the programming verification.

[0018] Finally, in step S204, when the target memory area 112T fails the programming verification, the memory control circuit 120 sets one programming time segment of the memory cell groups MG1 to MG8 to overlap with another programming time segment of the memory cell groups MG1 to MG8, and thereby programs the memory cell groups MG1 to MG8 in order.

[0019] For example, referring to FIGS. 3A to 3C, in the examples of FIGS. 3A to 3C, the horizontal axis is time t, and the programming time segments PT1 to PT8 are the programming time segments corresponding to the memory cell groups MG1 to MG8, respectively. The time lengths of each of the programming time segments PT1 to PT8 are the same and are represented by tPGM. The memory control circuit 120 can set the programming time segments PT1 to PT8 of each memory cell group MG1 to MG8 to overlap with the programming time segment of the previous memory cell group by a predetermined time length TL. The programming time segment PT2 of the memory cell group MG2 is set to overlap with the programming time segment PT1 of the memory cell group MG1 by a predetermined time length TL, the programming time segment PT3 of the memory cell group MG3 is set to overlap with the programming time segment PT2 of the memory cell group MG2 by a predetermined time length TL, and the same applies to the others. In the present embodiment, the predetermined time length TL is half of the time length tPGM.

[0020] Assume that there are defective memory cells in each memory cell group MG1 to MG8 (that is, all of the memory cell groups MG1 to MG8 fail the programming verification). As shown in FIG. 3A, the memory control circuit 120 can program the memory cell groups MG1 to MG8 that did not pass the programming verification in the programming time segments PT1 to PT8 in order. Specifically, the memory control circuit 120 applies a programming voltage Vprg to the defective memory cells included in the memory cell group MG1 of the target memory area 112T in the programming time segment PT1, and the memory control circuit 120 applies a programming voltage Vprg to the defective memory cells included in the memory cell group MG2 of the target memory area 112T in the programming time segment PT2, and the same applies to the others.

[0021] As an application, the memory cell groups MG1 to MG8 can each correspond to eight masks Mask[0] to Mask[7]. As shown in FIG. 3B, when Mask[0] is first turned on, the memory control circuit 120 programs only the memory cell group MG1. After a predetermined time length TL (half of the time length tPGM) has elapsed since Mask[0] was turned on, Mask[1] is turned on, whereby the memory control circuit 120 programs the memory cell groups MG1 and MG2 simultaneously. After a time twice the predetermined time length TL (equal to the time length tPGM) has elapsed since Mask[0] was turned on, Mask[0] is turned off and Mask[2] is turned on, whereby the memory control circuit 120 programs the memory cell groups MG2 and MG3 simultaneously, and the same applies to the others. In this way, the programming of the memory cell groups MG1 to MG8 is gradually completed.

[0022] The programming voltage Vprg includes the voltages applied to the gate node, drain node, source node, and well area of ​​a faulty memory cell, and in particular refers to the voltage applied to the drain node. For example, the voltage applied to the gate node may be 9 volts, the voltage applied to the drain node may be 4 volts, and the voltages applied to the source node and well area may be 0 volts, but the present invention is not limited thereto.

[0023] Since the programming time segments PT1 to PT8 of each memory cell group MG1 to MG8 are set to overlap with the programming time segment of the previous memory cell group, one programming operation on the target memory area 112T can be completed in only 4.5 times the time length tPGM, thereby reducing the time required for programming operations.

[0024] If, for example, only some memory cell groups MG1 to MG8 have faulty memory cells (for instance, only memory cell groups MG1, MG3, MG6, MG7, and MG8 fail the programming verification), then, as shown in Figure 3C, the memory control circuit 120 can sequentially program the memory cell groups MG1, MG3, MG6, MG7, and MG8 that failed the programming verification in programming time segments PT1, PT3, PT6, PT7, and PT8. Specifically, the memory control circuit 120 applies the programming voltage Vprg to the faulty memory cells in memory cell groups MG1, MG3, MG6, MG7, and MG8 of the target memory area 112T in programming time segments PT1, PT3, PT6, PT7, and PT8, respectively, but does not apply the programming voltage Vprg to memory cell groups MG2, MG4, and MG5 of the target memory area 112T in programming time segments PT2, PT4, and PT5 (shown as dotted lines in Figure 3C).

[0025] Furthermore, the predetermined time length TL is not limited to half of the time length tPGM, and those skilled in the art can adjust the length of the predetermined time length TL according to their actual needs. In one embodiment, as shown in Figure 3D, the predetermined time length TL that overlaps with the programming time segment of the previous memory cell group is two-thirds of the time length tPGM.

[0026] The following describes the programming method of the present disclosure using a different embodiment. Referring to Figures 1 and 4, the programming method of the flash memory device according to this embodiment is applied to the flash memory device 100 of Figure 1, and the following describes each step of the programming method according to the embodiment of the present invention by combining each component of the flash memory device 100. In this embodiment, parts that are the same or similar as those described in Figure 2 will not be described again.

[0027] First, in step S400, the memory control circuit 120 selects a target memory area 112T from among multiple memory areas 112 of the memory array 110 in response to the received selection command CMD. The target memory area 112T is divided into eight memory cell groups MG1 to MG8.

[0028] Next, in step S402, the memory control circuit 120 determines whether all of the memory cell groups MG1 to MG8 of the target memory area 112T have passed the programming verification. Specifically, the memory control circuit 120 can compare the bit data (e.g., 16 bits) formed by each memory cell group MG1 to MG8 of the target memory area 112T with the corresponding data pattern (e.g., 16 bits).

[0029] If the threshold voltages of all memory cells in memory cell groups MG1 to MG8 match the specified range of bit values ​​for the corresponding data patterns, it means that there are no defective memory cells in memory cell groups MG1 to MG8, i.e., that all have passed the programming verification. At this time, the memory control circuit 120 determines that the target memory area 112T has passed the programming verification, and the programming operation of the target memory area 112T is completed in step S404.

[0030] If the threshold voltage of the memory cells in memory cell groups MG1 to MG8 does not match the specified range of bit values ​​for the corresponding data patterns, it means that there are defective memory cells in memory cell groups MG1 to MG8, that is, not all of them passed the programming verification. At this time, the memory control circuit 120 determines that the target memory area 112T did not pass the programming verification and proceeds to step S406.

[0031] In step S406, the memory control circuit 120 adds memory cell groups that failed the programming verification of the target memory area 112T to the defective group set. For example, if only memory cell groups MG1, MG3, MG6, MG7, and MG8 of the target memory area 112T have defective memory cells and failed the programming verification, the memory control circuit 120 adds memory cell groups MG1, MG3, MG6, MG7, and MG8 to the defective group set.

[0032] In step S408, the memory control circuit 120 sets the programming time segments (e.g., programming time segments PT1, PT3, PT6, PT7, PT8) of each memory cell group in the faulty group set (e.g., each memory cell group MG1, MG3, MG6, MG7, MG8) to overlap with the programming time segment of the previous memory cell group in the faulty group set by a predetermined time length TL. Referring to Figure 5, in this example, the horizontal axis is time t, and the time lengths of each programming time segment PT1, PT3, PT6, PT7, PT8 are the same and are represented as tPGM. The programming time segment PT3 of memory cell group MG3 is set to overlap with the programming time segment PT1 of memory cell group MG1 for a predetermined time length TL, the programming time segment PT6 of memory cell group MG6 is set to overlap with the programming time segment PT3 of memory cell group MG3 for a predetermined time length TL, the programming time segment PT7 of memory cell group MG7 is set to overlap with the programming time segment PT6 of memory cell group MG6 for a predetermined time length TL, and the programming time segment PT8 of memory cell group MG8 is set to overlap with the programming time segment PT7 of memory cell group MG7 for a predetermined time length TL.

[0033] As a result, in step S410, the memory control circuit 120 sequentially programs the memory cell groups MG1, MG3, MG6, MG7, and MG8 of the faulty group set to the programming time segments PT1, PT3, PT6, PT7, and PT8, which are set as shown in Figure 5. Specifically, the memory control circuit 120 applies a programming voltage Vprg to the faulty memory cell in the memory cell group MG1 of the target memory area 112T in programming time segment PT1, and applies a programming voltage Vprg to the faulty memory cell in the memory cell group MG3 of the target memory area 112T in programming time segment PT3, and so on.

[0034] Subsequently, the memory control circuit 120 can clear the defective group set and return to step S402, continuing the programming verification until all memory cell groups in the target memory area 112T pass the programming verification.

[0035] Thus, since only the programming time segment of the memory cell group is considered each time it is added to the bad group set, a single programming operation on the target memory area 112T can be completed in a shorter time, thereby reducing the time required for the programming operation.

[0036] In summary, the flash memory device and its programming method of the present invention overlap the programming time segments of multiple memory cell groups, assuming that the peak value of the programming current does not exceed the load of the charge pump circuit. This not only shortens the time required for programming operations but also fully utilizes the efficiency of the charge pump circuit. Therefore, the present invention is beneficial for applications in energy-saving products and belongs to green semiconductor technology. [Industrial applicability]

[0037] The flash memory device and its programming method according to the present invention can be applied to the execution of memory programming operations. [Explanation of Symbols]

[0038] 100: Flash memory devices 110: Memory Array 112: Memory area 112T: Target memory area 120: Memory control circuit CMD: Select Command Mask[0]~Mask[7]: Mask MG1~MG8: Memory cell group t: time TL: Scheduled time length tPGM: Time length PT1~PT8: Programming time segments Vprg: Programming Voltage S200~S204, S400~S410: Step

Claims

1. A programming method for a flash memory device including a memory array having multiple memory regions, The steps include selecting a target memory area from the aforementioned multiple memory areas to perform a programming operation on, and the target memory area being divided into multiple memory cell groups, The steps include: performing programming verification on the aforementioned target memory area; If the target memory area fails the programming verification, the programming time segment of one of the multiple memory cell groups is set to overlap with the programming time segment of another of the multiple memory cell groups, thereby programming the multiple memory cell groups in sequence. A method for programming flash memory devices, including those mentioned above.

2. Each of the aforementioned multiple memory cell groups corresponds to a plurality of masks, and in the step of performing the programming verification on the target memory area, The steps include: when the first of the plurality of masks is turned on, programming only the first of the plurality of memory cell groups; The programming method according to claim 1, which includes the step of turning on the second of the plurality of masks after a predetermined time has elapsed since the first of the plurality of masks was turned on, thereby simultaneously programming the first and second of the plurality of memory cell groups.

3. The step of setting one programming time segment of the plurality of memory cell groups to overlap with another programming time segment of the plurality of memory cell groups includes: The programming method according to claim 1, further comprising the step of setting the programming time segment of each of the plurality of memory cell groups to overlap with the programming time segment of the previous memory cell group for a predetermined time length.

4. The programming method according to claim 3, wherein the predetermined time length is 1 / 2 or 2 / 3 of the length of the programming time segment of the memory cell group.

5. The programming method according to claim 1, further comprising the step of adding the plurality of memory cell groups that did not pass the programming verification of the target memory area to a set of defective groups.

6. The step of setting one programming time segment of the plurality of memory cell groups to overlap with another programming time segment of the plurality of memory cell groups includes: The programming method according to claim 5, further comprising the step of setting the programming time section of each of the plurality of memory cell groups of the faulty group set to overlap with the programming time segment of the memory cell group immediately preceding the faulty group set for a predetermined time length.

7. A memory array having multiple memory regions, A memory control circuit connected to the memory array and configured to select a target memory region from the plurality of memory regions for programming operations, wherein the target memory region is divided into a plurality of memory cell groups, A flash memory device including, The memory control circuit performs programming verification on the target memory area. If the target memory area fails the programming verification, the memory control circuit sets one programming time segment of the plurality of memory cell groups to overlap with another programming time segment of the plurality of memory cell groups, thereby programming the plurality of memory cell groups sequentially, in a flash memory device.

8. Each of the plurality of memory cell groups corresponds to a plurality of masks, and when the first of the plurality of masks is on, the memory control circuit programs only the first of the plurality of memory cell groups. The flash memory device according to claim 7, wherein after the first of the plurality of masks has been turned on for a predetermined period of time, the second of the plurality of masks is turned on, thereby the memory control circuit programs the first and second of the plurality of memory cell groups.

9. The flash memory device according to claim 7, wherein the memory control circuit is configured to overlap the programming time segment of each of the plurality of memory cell groups with the programming time segment of the previous memory cell group for a predetermined period of time.

10. The flash memory device according to claim 9, wherein the memory control circuit sequentially programs the plurality of memory cell groups that did not pass the programming verification in the corresponding programming time segment.

11. The flash memory device according to claim 9, wherein the predetermined time length is 1 / 2 or 2 / 3 of the length of the programming time segment of the memory cell group.

12. The flash memory device according to claim 7, wherein the memory control circuit adds the plurality of memory cell groups that did not pass the programming verification of the target memory area to a defective group set.

13. The flash memory device according to claim 12, wherein the memory control circuit is configured to overlap the programming time segment of each of the plurality of memory cell groups of the faulty group set with the programming time segment of the memory cell group immediately preceding the faulty group set for a predetermined time period.

14. The flash memory device according to claim 13, wherein the memory control circuit sequentially programs the plurality of memory cell groups of the faulty group set in the corresponding programming time segment.

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