Semiconductor memory device and method for manufacturing a semiconductor memory device

Abstract

Ensure the channel layer is sufficiently crystallized. [Solution] The semiconductor memory device of the embodiment comprises a laminate in which a plurality of conductive layers and a plurality of first insulating layers are alternately stacked one layer at a time; a plate-like portion extending within the laminate in a first direction intersecting the stacking direction and the stacking direction, and dividing the laminate in a second direction intersecting the first direction and the stacking direction; a pillar arranged adjacent to the plate-like portion in the second direction and including a semiconductor layer extending within the laminate in the stacking direction; a first layer arranged above the laminate and mainly composed of semiconductors; and a second layer arranged above the first layer and mainly composed of semiconductors. The plate-like portion has a protruding portion that penetrates the first layer and extends upward, and the protruding portion is arranged between the first and second layers and covered by a third layer mainly composed of semiconductors.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor memory device and a method for manufacturing a semiconductor memory device.

Background Art

[0002] In a semiconductor memory device such as a three-dimensional non-volatile memory, a pillar penetrating a stacked body in which a plurality of conductive layers and a plurality of insulating layers are alternately stacked is formed. At that time, in order to crystallize the channel layer of the pillar and activate impurities in the channel layer, laser light or the like may be irradiated from above the semiconductor memory device. However, crystallization of the channel may not be sufficient around the pillar adjacent to other members or the like.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0004] One embodiment aims to provide a semiconductor memory device and a method for manufacturing a semiconductor memory device that can sufficiently crystallize a channel layer.

Means for Solving the Problems

[0005] The semiconductor memory device of the embodiment comprises a laminate in which a plurality of conductive layers and a plurality of first insulating layers are alternately stacked one layer at a time; a plate-like portion extending within the laminate in a first direction intersecting the stacking direction and the stacking direction, and dividing the laminate in a second direction intersecting the first direction and the stacking direction; a pillar disposed adjacent to the plate-like portion in the second direction and including a semiconductor layer extending within the laminate in the stacking direction; a first layer disposed above the laminate and mainly composed of semiconductors; and a second layer disposed above the first layer and mainly composed of semiconductors, wherein the plate-like portion has a projection extending upward through the first layer, and the projection is disposed between the first and second layers and covered by a third layer mainly composed of semiconductors. [Brief explanation of the drawing]

[0006] [Figure 1] A diagram showing a schematic configuration example of a semiconductor memory device according to an embodiment. [Figure 2] A cross-sectional view showing an example of the configuration of a semiconductor memory device according to the embodiment. [Figure 3] A diagram illustrating, in order, some of the steps of a semiconductor memory manufacturing method according to an embodiment. [Figure 4] A diagram illustrating, in order, some of the steps of a semiconductor memory manufacturing method according to an embodiment. [Figure 5] A diagram illustrating, in order, some of the steps of a semiconductor memory manufacturing method according to an embodiment. [Figure 6] A diagram illustrating, in order, some of the steps of a semiconductor memory manufacturing method according to an embodiment. [Figure 7] A diagram illustrating, in order, some of the steps of a semiconductor memory manufacturing method according to an embodiment. [Figure 8] A diagram illustrating, in order, some of the steps of a semiconductor memory manufacturing method according to an embodiment. [Figure 9] A diagram illustrating, in order, some of the steps of a semiconductor memory manufacturing method according to an embodiment. [Figure 10] A diagram illustrating, in order, some of the steps of a semiconductor memory manufacturing method according to an embodiment. [Figure 11] A diagram illustrating, in order, some of the steps of a semiconductor memory manufacturing method according to an embodiment. [Figure 12] A diagram illustrating, in order, some of the steps of a semiconductor memory manufacturing method according to an embodiment. [Figure 13] A diagram illustrating a method for doping the channel layer of a semiconductor memory device with impurities, as shown in the comparative example. [Figure 14] A diagram illustrating a method for doping the channel layer of a semiconductor memory device with impurities, as shown in the comparative example. [Modes for carrying out the invention]

[0007] Embodiments of the present invention will be described in detail below with reference to the drawings. However, the present invention is not limited to the embodiments described below. Furthermore, the components in the embodiments described below include those that are easily conceivable by those skilled in the art or that are substantially identical.

[0008] (Example of semiconductor memory device configuration) Figure 1 is a diagram showing a schematic configuration example of a semiconductor memory device 1 according to an embodiment. More specifically, Figure 1(a) is a cross-sectional view of the semiconductor memory device 1 along the X direction, and Figure 1(b) is a schematic plan view showing the layout of the semiconductor memory device 1.

[0009] However, in Figure 1(a), hatching is omitted for the sake of readability. Also, in Figure 1(a), components that do not necessarily exist in the same cross-section are shown, and some upper-level wiring, etc., are omitted.

[0010] Furthermore, in this specification, both the X and Y directions are directions along the orientation of the surface of the word line WL, and the X and Y directions are orthogonal to each other. The electrical extraction direction of the word line WL may be referred to as the first direction, and this first direction is along the X direction. The direction intersecting the first direction may be referred to as the second direction, and this second direction is along the Y direction. However, since the semiconductor memory device 1 may contain manufacturing tolerances, the first direction and the second direction are not necessarily orthogonal.

[0011] As shown in FIG. 1(a), the semiconductor memory device 1 includes, in order from the lower side of the paper surface, a semiconductor substrate SB, a peripheral circuit CBA, one or more selection gate lines SGD, a plurality of word lines WL, one or more selection gate lines SGS, a source line SL, and an electrode film EL, etc.

[0012] The semiconductor substrate SB is, for example, a silicon substrate or the like. A peripheral circuit CBA including transistors TR, wirings, etc. is disposed on the surface of the semiconductor substrate SB, and the whole is covered by an insulating layer 40. Above the semiconductor substrate SB on which the peripheral circuit CBA etc. is disposed, a plurality of word lines WL and selection gate lines SGD, SGS covered entirely by an insulating layer 50 are disposed.

[0013] As shown in FIGS. 1(a) and (b), a memory region MR is disposed at the central portion in the X direction of a plurality of word lines WL etc., and staircase regions SR are respectively disposed at both ends in the X direction of the plurality of word lines WL etc. These memory regions MR and staircase regions SR are divided into a plurality of regions by a plurality of plate-like contacts LI that penetrate the plurality of word lines WL etc. and extend in the direction along the X direction.

[0014] Note that a region disposed between plate-like contacts LI adjacent in the Y direction and including the memory region MR and the staircase region SR is called a block region BLK. As will be described later, a plurality of memory cells that hold data non-volatilely are included in the memory region MR, and the above block region BLK is an erasure unit of these data.

[0015] Also, a plurality of separation layers SHE that penetrate the selection gate line SGD and extend in the direction along the X direction are disposed between plate-like contacts LI adjacent in the Y direction. The plurality of separation layers SHE extend in the direction along the X direction over the entire memory region MR and reach a part of the staircase regions SR at both ends in the X direction.

[0016] Multiple pillars PL are arranged in the memory area MR. The multiple pillars PL penetrate multiple word lines WL and selection gate lines SGD, SGS, with one end protruding into the source line SL.

[0017] An electrode film EL is positioned above the metal layer TS via an insulating layer 60. The electrode film EL is entirely covered by an insulating layer 70, except for a pad region PD located in the peripheral region PR, which is located outside the X direction, such as the word line WL. The insulating layer 70 has a structure in which layers such as a silicon oxide layer, a silicon nitride layer, and a polyimide layer are stacked from the bottom.

[0018] The electrode film EL is connected to the source wire SL and the through-contact C3 by a plug PG or the like that penetrates the insulating layer 60. The through-contact C3 is provided in the peripheral region PR and penetrates the insulating layer 50 that covers the word WL and the like, and the insulating layer 40 that covers the peripheral circuit CBA, and is connected to the semiconductor substrate SB on which the peripheral circuit CBA is located.

[0019] From outside the semiconductor memory device 1, the semiconductor substrate SB is controlled to a predetermined potential via the pad area PD and through-contact C3. Furthermore, power and signals from the outside are supplied to the semiconductor memory device 1 via the pad area PD.

[0020] Multiple memory cells are formed at the intersection of the pillar PL and the word line WL. As a result, the semiconductor memory device 1 is configured as a three-dimensional non-volatile memory in which memory cells are arranged three-dimensionally in the memory region MR, for example.

[0021] In the stepped region SR, there is a stepped section SP where multiple word lines WL and selection gate lines SGD and SGS are processed in a stepped manner and terminated. The aforementioned isolation layer SHE extends from the memory region MR to the portion of the stepped region SR where the selection gate line SGD is processed in a stepped manner. As a result, within a single block region BLK, the selection gate line SGD is separated into multiple regions. In other words, the isolation layer SHE penetrates the portion below the multiple word lines WL, thereby dividing these portions into multiple patterns of selection gate line SGD.

[0022] Each terrace section, composed of multiple word lines WL and select gate lines SGD and SGS, has a contact CC that extends upward through the insulating layer 50 and connects to the word lines WL and select gate lines SGD and SGS of each layer.

[0023] In this specification, the direction in which the terrace surfaces of the multiple word lines WL and the selected gate lines SGD and SGS face is defined as the lower side of the semiconductor memory device 1.

[0024] In word lines WL and select gate lines SGS, one contact CC is connected per layer. In select gate lines SGD, one contact CC is connected per layer for each section separated by the isolation layer SHE.

[0025] Here, within a single block region BLK, multiple contacts CC are positioned on one side of the staircase region SR on both sides in the X direction. Also, looking at one side in the X direction, for example, multiple contacts CC are positioned every two block regions BLK.

[0026] In other words, in the example shown in Figure 1(b), in the block region BLK at the very top of the page, multiple contact CCs are located in the stair region SR on the left side of the page, among the stair regions SR at both ends in the X direction. Furthermore, in the block region BLK one level below and two levels below the above block region BLK, multiple contact CCs are located in the stair region SR on the right side of the page, among the stair regions SR at both ends in the X direction. Moreover, in the block region BLK at the very bottom of the page, multiple contact CCs are again located in the stair region SR on the left side of the page.

[0027] Therefore, as shown in Figure 1(a), the respective contact CCs of the stair region SR at both ends in the X direction belong to different block regions BLK and are not actually located in the same cross-section.

[0028] These contact CCs allow individual stacked word lines WLs to be drawn out. More specifically, these contact CCs apply write voltages and read voltages to memory cells included in the memory region MR at the center of multiple word lines WLs, via word lines WLs located at the same height as the memory cells.

[0029] In this embodiment, the semiconductor memory device 1 is constructed by bonding together an insulating layer 40 covering the peripheral circuit CBA and an insulating layer 50 covering the word lines WL, etc. Thus, the insulating layers 40 and 50 function as bonding layers. Furthermore, by bonding the insulating layers 40 and 50, the electrode pads placed on the surfaces of these insulating layers 40 and 50 are connected to each other, thereby electrically connecting the peripheral circuit CBA, the contact CC, the multiple word lines WL and the selection gate lines SGS, SGD, and the pillar PL.

[0030] The application of a predetermined voltage from contact CC to the memory cell is controlled by the peripheral circuit CBA, which is electrically connected to these components. In this way, the peripheral circuit CBA controls the electrical operation of the memory cell.

[0031] Next, a detailed example of the configuration of the semiconductor memory device 1 will be described using Figure 2. Figure 2 is a cross-sectional view showing an example of the configuration of the semiconductor memory device 1 according to the embodiment.

[0032] More specifically, Figure 2(a) is a cross-sectional view along the Y direction in the memory region MR of the semiconductor memory device 1. In Figure 2(a), the structure above the insulating layer 60 and below the insulating layer 52, which will be described later, are omitted.

[0033] Figure 2(b) is an enlarged cross-sectional view of pillar PL at the height of word line WL. Figure 2(c) is an enlarged cross-sectional view of pillar PL at the height of selected gate lines SGD and SGS.

[0034] As shown in Figure 2(a), below the insulating layer 60, in order from the side of the insulating layer 60, are the metal layer TS, the barrier metal layer BM, and the source wire SL.

[0035] The insulating layer 60 is, for example, a silicon oxide layer. The metal layer TS is, for example, a tungsten layer, and functions as the source wire metal of the semiconductor memory device 1 in addition to the source wire SL below. The barrier metal layer BM is, for example, at least one of a titanium layer, a titanium nitride layer, a tantalum layer, or a tantalum nitride layer, and suppresses the diffusion of tungsten atoms from the metal layer TS to the neighboring components.

[0036] The source line SL has a multilayer structure in which, for example, the auxiliary source line ASL and the main source line DSLb are arranged in this order from the barrier metal layer BM side downwards. The auxiliary source line ASL is, for example, an undoped amorphous layer, an undoped polysilicon layer, or an undoped semiconductor layer in which amorphous and polysilicon layers are mixed. The main source line DSLb is, for example, a polycrystalline semiconductor layer such as an undoped polysilicon layer, or an amorphous semiconductor layer such as an undoped amorphous silicon layer. However, at least one of the auxiliary source line ASL and the main source line DSLb may contain an impurity that makes it N-type conductive, such as phosphorus or arsenic.

[0037] The source line SL may also include a stopper layer DSLa, which will be described later. The stopper layer DSLa is a polycrystalline semiconductor layer, such as a polysilicon layer containing N-type impurities such as phosphorus or arsenic.

[0038] Below the source wire SL, a laminate LM is arranged, in which multiple word wires WL and multiple insulating layers OL are alternately stacked one layer at a time. The laminate LM consists of a laminate LMa located below the source wire SL and a laminate LMb located further below the laminate LMa.

[0039] The LMa laminate has selection gate lines SGS1 and SGS0 above the uppermost word line WL, starting from the source line SL side. These selection gate lines SGS1 and SGS0 are the selection gate lines on the source side.

[0040] The laminate LMb has selection gate lines SGD1 and SGD0 located below the bottommost word line WL, starting from the bottommost word line WL side. These selection gate lines SGD1 and SGD0 are the drain-side selection gate lines.

[0041] However, the number of word line WL and selective gate line SGS,SGD layers included in the laminate LM is arbitrary. Therefore, the laminate LM may have one or more selective gate lines SGS,SGD each, or three or more each. The multiple word line WL and selective gate lines SGS,SGD may be, for example, tungsten layers or molybdenum layers, and the multiple insulating layers OL may be, for example, silicon oxide layers.

[0042] Below the laminate LM, insulating layers 52 and 53 are arranged in order from the LM side. These insulating layers 52 and 53 constitute a part of the insulating layer 50 (see Figure 1(a)) described above.

[0043] As described above, the multiple plate-like contacts LI extend in directions along the lamination direction and the X direction of the laminate LM. More specifically, the plate-like contacts LI penetrate the laminate LM and the main source line DSLb and protrude into the stopper layer DSLa interposed between the main source line DSLb and the auxiliary source line ASL.

[0044] The stopper layer DSLa is unevenly distributed near the plate-shaped contact LI, positioned on the main source line DSLb via an intermediate insulating layer OSL, and covering the upper end of the plate-shaped contact LI. The plate-shaped contact LI also penetrates this intermediate insulating layer OSL. The intermediate insulating layer OSL is, for example, a silicon oxide layer.

[0045] Each of these plate-shaped contacts LI has a conductive layer 24, such as a tungsten layer, and an insulating layer 54 that covers the side walls of the conductive layer 24. The insulating layer 54 also covers the upper end of the conductive layer 24 that protrudes into the stopper layer DSLa.

[0046] However, as mentioned above, these main source line DSLb, stopper layer DSLa, and auxiliary source line ASL are all semiconductor layers such as silicon layers. Therefore, in an actual semiconductor memory device 1, it may not be possible to distinguish the interfaces between these main source line DSLb, stopper layer DSLa, and auxiliary source line ASL, and these layers may not be able to be identified individually.

[0047] Even in such cases, it is possible to distinguish that among the various semiconductor layers mentioned above, the semiconductor layer located on the upper end of the pillar PL is a thin auxiliary source wire ASL, while the upper end of the plate-shaped contact LI has relatively thick semiconductor layers: a stopper layer DSLa and an auxiliary source wire ASL. Furthermore, since the intermediate insulating layer OSL is a layer of different materials from the main source wire DSLb and the stopper layer DSLa, it can be determined that it is interposed between them, thereby allowing for differentiation between the main source wire DSLb and the stopper layer DSLa. Moreover, while the main source wire DSLb and auxiliary source wire ASL are undoped semiconductor layers, the stopper layer DSLa covering the upper end of the plate-shaped contact LI contains N-type impurities. Even if the main source wire DSLb and auxiliary source wire ASL contain N-type impurities, they can be distinguished from the stopper layer DSLa due to differences in crystallinity depending on how heat is applied during the manufacturing process, or differences in the type or concentration of impurities.

[0048] From the above, it can be determined that the upper end of the pillar PL is not covered by the stopper layer DSLa, while the upper end of the plate-shaped contact LI is covered by the stopper layer DSLa.

[0049] Furthermore, the plate-shaped contact LI may have a tapered shape in which its width in the Y direction increases from the upper end to the lower end, for example. Alternatively, the plate-shaped contact LI may have a bowing shape in which its width in the Y direction is maximum at a predetermined position between the upper end and the lower end.

[0050] Among the multiple plate-shaped contacts LI, one or more isolation layers SHE extend along the X-direction to the lower part of the laminate LM between adjacent plate-shaped contacts LI in the Y-direction. In the example shown in Figure 2(a), the isolation layer SHE penetrates the aforementioned selection gate lines SGD0 and SGD1 and reaches the insulating layer OL adjacent to the selection gate line SGD1 in the lamination direction. As a result, the selection gate lines SGD0 and SGD1 are divided into multiple sections.

[0051] Furthermore, between adjacent plate-shaped contacts LI in the Y direction, multiple pillars PL extend through the laminate LM in the stacking direction of the laminate LM. More specifically, these pillars PL extend from the bottom insulating layer OL of the laminate LM through the laminate LM in the stacking direction of the laminate LM and penetrate the laminate LM and the main source line DSLb.

[0052] Multiple pillars PL are arranged, for example, in a staggered pattern when viewed from the stacking direction of the laminate LM. Each pillar PL has a cross-sectional shape in the direction along the layering direction of the laminate LM, i.e., along the XY plane, such as a circular, elliptical, or oval shape.

[0053] Furthermore, the pillar PL has a tapered shape in the portion that penetrates the laminate LMa and the portion that penetrates the laminate LMb, where the diameter and cross-sectional area increase from the upper layer side to the lower layer side. Alternatively, the pillar PL has a bowing shape in the portion that penetrates the laminate LMa and the portion that penetrates the laminate LMb, where the diameter and cross-sectional area are maximized at a predetermined position between the upper layer side and the lower layer side.

[0054] Furthermore, the pillar PL comprises a core layer CR which serves as the core material, a channel layer CN which covers the sidewalls of the core layer CR, a memory layer ME which covers the sidewalls of the channel layer CN, and a cap layer CP which is positioned at the lower end of the pillar PL.

[0055] Of these core layer CR, channel layer CN, and memory layer ME, the memory layer ME penetrates the laminate LM and the main source line DSLb, reaching the auxiliary source line ASL. Furthermore, the core layer CR and channel layer CN penetrate the laminate LM and the main source line DSLb, with their upper ends protruding into the metal layer TS. The lower end of the channel layer CN within the metal layer TS is covered in that order by the auxiliary source line ASL and the barrier metal layer BM.

[0056] In other words, the portion of the channel layer CN that protrudes into the metal layer TS is not covered by the memory layer ME, and the channel layer CN is in direct contact with the auxiliary source line ASL. As a result, the channel layer CN is electrically connected to the main source line DSLb via the auxiliary source line ASL. From the upper end connected to the auxiliary source line ASL, etc., to the depth position of the aforementioned selected gate lines SGS0, SGS1, the channel layer CN contains N-type impurities such as phosphorus or arsenic.

[0057] Furthermore, the aforementioned stopper layer DSLa and intermediate insulating layer OSL are unevenly distributed near the plate-shaped contact LI and are not located near the pillar PL.

[0058] The cap layer CP, located at the lower end of pillar PL, connects the channel layer CN to the plug CH, which extends through the bottom insulating layer OL of the laminate LM and the insulating layer 52 below it. The plug CH connects the bit wire BL, located in the insulating layer 53, to pillar PL, located in the laminate LM. The bit wire BL extends downward along the Y direction so as to intersect with the drawing direction of the word wire WL.

[0059] As shown in Figures 2(b) and 2(c), the memory layer ME has a stacked structure including a block insulating layer BK, a charge storage layer CT, and a tunnel insulating layer TN, in that order from the outer periphery of the pillar PL. The charge storage layer CT of the memory layer ME is, for example, a silicon nitride layer. The block insulating layer BK, the tunnel insulating layer TN, and the core layer CR of the memory layer ME are, for example, silicon oxide layers. The channel layer CN and the cap layer CP are, for example, polycrystalline semiconductor layers such as polysilicon layers.

[0060] As shown in Figure 2(b), with the above configuration, memory cells MC are formed in the portions of the pillar PL side surface that face each word line WL. Data is written to and read from the memory cells MC by applying a predetermined voltage from the word line WL.

[0061] As shown in Figure 2(c), selection gate STD is formed on the side of pillar PL where it faces selection gate lines SGD0 and SGD1. Additionally, selection gate STS is formed on the side of pillar PL where it faces selection gate lines SGS0 and SGS1, which are lower than the word line WL.

[0062] By applying predetermined voltages to the selection gate lines SGD and SGS, respectively, the selection gates STD and STS can be turned on or off, thereby selecting or deselecting the memory cell MC of the pillar PL to which the selection gates STD and STS belong. As described above, by including impurities such as phosphorus or arsenic in the channel layer CN at the depth position of the selection gate lines SGD and SGS, the threshold voltage of the selection gate STS can be adjusted to a desired value.

[0063] (Method of manufacturing semiconductor memory devices) Next, the manufacturing method of the semiconductor memory device 1 according to the embodiment will be described using Figures 3 to 12. Figures 3 to 12 are diagrams illustrating, in order, some of the steps of the manufacturing method of the semiconductor memory device 1 according to the embodiment. More specifically, Figures 3 to 12 show a cross-section along the Y direction of the region that will later become the memory region MR.

[0064] In the following explanation, the direction in which the side of the support substrate SS or semiconductor substrate SB, which will be described later, that undergoes various processing will be oriented will be considered the upper side of the semiconductor memory device 1 during manufacturing. In other words, the upper side of the drawing below is the upper side of the semiconductor memory device 1 during manufacturing, and the lower side of the drawing below is the lower side of the semiconductor memory device 1 during manufacturing.

[0065] As shown in Figure 3(a), a support substrate SS is prepared. As the support substrate SS, a semiconductor substrate such as a silicon substrate, an insulating substrate such as a ceramic substrate, or a conductive substrate can be used.

[0066] Subsequently, the components that will later become the source wire SL, the laminate LM, and the pillar PL are formed on the upper surface of the support substrate SS. These formation processes are carried out in a state where the vertical direction is reversed compared to the examples in Figures 1 and 2 described above.

[0067] First, a stopper layer DSLa, an intermediate insulating layer OSL, and a main source line DSLb are formed on the support substrate SS in this order. The stopper layer DSLa and the main source line DSLb are polycrystalline semiconductor layers such as undoped polysilicon layers. In this case, the stopper layer DSLa and the main source line DSLb may be formed as amorphous silicon layers. The intermediate insulating layer OSL is a silicon oxide layer or the like.

[0068] Furthermore, a laminate LMsa is formed on the main source line DSLb, in which multiple insulating layers NL and multiple insulating layers OL are alternately stacked one layer at a time. The insulating layer NL is, for example, a silicon nitride layer, and functions as a sacrificial layer that will later be replaced by a conductive material to become the word line WL or the selected gate line SGS.

[0069] Although not shown in the diagram, in a portion of the laminated LMsa, the insulating layer NL and insulating layer OL are processed in a stepped manner. This processing can be achieved by repeatedly slimming the mask pattern of the photoresist layer, etc., and etching the insulating layer NL and insulating layer OL of the laminated LMsa.

[0070] Specifically, a mask pattern is formed on the upper surface of the laminated LMsa, and the insulating layer NL and insulating layer OL in the exposed areas are etched away one layer at a time. Then, the edges of the mask pattern are receded by treatment with oxygen plasma or the like, exposing the upper surface of the laminated LMsa, and the insulating layer NL and insulating layer OL are etched away one layer at a time again. By repeating this process multiple times, a laminated LMsa with a stepped shape at both ends in the X direction is formed.

[0071] Subsequently, the stepped shape at both ends in the X direction is covered with a portion of the insulating layer 50 (see Figure 1(a)) described above.

[0072] As shown in Figure 3(b), the laminate LMsa forms multiple memory holes MHa extending in the stacking direction. These multiple memory holes MHa penetrate the laminate LMsa, the main source line DSLb, and the intermediate insulating layer OSL, reaching a predetermined depth in the stopper layer DSLa. These memory holes MHa are the portions that later penetrate the laminate LMa of the pillar PL.

[0073] As shown in Figure 3(c), these memory holes MHa are filled with a sacrificial layer 26 such as a CVD-carbon layer. This forms a pillar PLc in which multiple memory holes MHa are filled with the sacrificial layer 26.

[0074] As shown in Figure 4(a), the laminate LMsa is covered, and a laminate LMsb is formed by alternately stacking multiple insulating layers NL and multiple insulating layers OL one layer at a time. The insulating layers NL of the laminate LMsb function as sacrificial layers that are later replaced by conductive layers to become word lines WL or selected gate lines SGD.

[0075] Although not shown in the diagram, a portion of the laminate LMsb is processed in a stepwise manner, altering the insulating layer NL and insulating layer OL. This processing can be achieved by repeatedly performing the same steps as the processing for the laminate LMsa described above: slimming the mask pattern of the photoresist layer, etc., and etching the insulating layer NL and insulating layer OL of the laminate LMsb.

[0076] At this time, the uppermost step of the stair section formed on the laminated LMsa and the lowermost step of the stair section formed on the laminated LMsb are brought into close proximity to form a stair shape that extends continuously from the lower layer of the laminated LMsa to the upper layer of the laminated LMsb. As a result, the laminated LMsa and LMsb are formed with a stair region SR having a stair shape extending from the laminated LMsa to the laminated LMsb, with the stair region SR formed at both ends in the X direction.

[0077] Subsequently, the stepped shape at both ends in the X direction is further covered with a portion of the insulating layer 50 (see Figure 1(a)) described above.

[0078] As shown in Figure 4(b), multiple memory holes MHb are formed that penetrate the laminate LMsb and connect to multiple pillars PLc that have already been formed within the laminate LMsa. The memory holes MHb are the parts of pillar PL that will later penetrate the laminate LMb.

[0079] As shown in Figure 5(a), the sacrificial layer 26 is removed from the pillar PLc at the bottom of the memory hole MHb. As a result, multiple memory holes MHa open at the bottom of multiple memory holes MHb, and multiple memory holes MH are formed that penetrate the laminate LMsb, LMsa, the main source line DSLb, and the intermediate insulating layer OSL, reaching a predetermined depth in the stopper layer DSLa.

[0080] Furthermore, if the sacrificial layer 26 filled inside the pillar PLc is a CVD-carbon layer or the like, the sacrificial layer 26 can be removed from these pillar PLc all at once when the mask pattern used to form the memory holes MHb in Figure 4(b) above is removed by ashing using oxygen plasma or the like.

[0081] As shown in Figure 5(b), a memory layer ME is formed on the sidewall and bottom surface of the memory hole MH, in the order of block insulating layer BK, charge storage layer CT, and tunnel insulating layer TN (see Figures 2(b) and 2(c)), starting from the sidewall side of the memory hole MH. The memory layer ME is also formed on the top surface of the laminate LMsb.

[0082] Furthermore, the channel layer CN and core layer CR are formed in this order within the memory hole MH via the memory layer ME. As a result, the channel layer CN is formed on the memory layer ME that covers the sides and bottom of the memory hole MH, and the core layer CR fills the center of the memory hole MH. The channel layer CN and core layer CR are also formed in this order on the upper surface of the laminate LMsb via the memory layer ME.

[0083] Furthermore, the channel layer CN at this point is not doped with impurities and may be in an amorphous state, such as an amorphous silicon layer.

[0084] As shown in Figure 6(a), the core layer CR, channel layer CN, and memory layer ME formed on the upper surface of the laminate LMsb are removed by etch-back along with a portion of the insulating layer OL of the uppermost layer of the laminate LMsb, and the core layer CR is recessed to a predetermined depth of the memory hole MH to form a depression DN at the upper end of the memory hole MH.

[0085] As shown in Figure 6(b), a cap layer CP is formed in the recess DN at the upper end of the memory hole MH. At this point, the cap layer CP may be in an amorphous state, such as an amorphous silicon layer.

[0086] As shown in Figure 7(a), the etch-back of the core layer CR, channel layer CN, and memory layer ME formed on the upper surface of the laminated LMsb increases the thickness of the insulating layer OL on the top layer of the laminated LMsb. This forms a pillar PL whose upper end is embedded in the insulating layer OL on the top layer of the laminated LMsb. However, at this point, the memory layer ME covers the channel layer CN at the lower end of the pillar PL.

[0087] As shown in Figure 7(b), a slit ST is formed that penetrates the laminates LMsb, LMsa, the main source wire DSLb, and the intermediate insulating layer OSL, reaching a predetermined depth in the stopper layer DSLa. The slit ST also extends within the laminates LMsa, LMsb in a direction along the X direction.

[0088] As shown in Figure 8(a), a solvent for removing the insulating layer NL, such as thermal phosphoric acid, is introduced into the laminates LMsa and LMsb through the slit ST to remove the insulating layer NL of the laminates LMsa and LMsb. This forms laminates LMga and LMgb having multiple gap layers GP from which the insulating layer NL between insulating layers OL has been removed.

[0089] Laminates LMga and LMgb, which contain multiple gap layers GP, have a fragile structure. Multiple pillars PL support these fragile laminates LMga and LMgb. This prevents the insulating layer OL remaining in the laminate from bending, and prevents the laminate LMga and LMgb from deforming or collapsing.

[0090] As shown in Figure 8(b), a conductive material raw material gas, such as tungsten or molybdenum, is injected into the interior of the laminates LMga and LMgb through the slit ST, and the gap layer GP of the laminates LMga and LMgb is filled with the conductive material to form multiple word lines WL, etc. This forms a laminate LM containing laminates LMa and LMb, in which multiple word lines WL, etc. and multiple insulating layers OL are alternately stacked one layer at a time.

[0091] As described above, the process of forming the word line WL from the insulating layer NL is also called the replacement process.

[0092] As shown in Figure 9(a), a conductive layer 24 is filled into the slit ST via an insulating layer 54 to form a plate-shaped contact LI.

[0093] As shown in Figure 9(b), grooves GR are formed that penetrate one or more conductive layers, including the uppermost conductive layer of the laminate LMb.

[0094] As shown in Figure 10(a), an insulating layer 56 is filled into the groove GR, forming a separation layer SHE that divides the conductive layer on the upper side of the laminate LM into the pattern of the selected gate line SGD.

[0095] Although not shown in the diagram, multiple contact points CC are formed from the upper side of the staircase area SR, reaching the word lines WL and selection gate lines SGD and SGS that constitute each step of the staircase structure of the staircase area SR.

[0096] As shown in Figure 10(b), after forming an insulating layer 52 covering the laminate LM, plugs CH are formed that penetrate the uppermost insulating layer OL of the laminate LM and the insulating layer 52, and are connected to the cap layer CP at the upper end of the pillar PL. In addition, an insulating layer 53 is formed to cover the insulating layer 52, and bit wires BL are formed in the insulating layer 53 to which the individual plugs CH are connected.

[0097] Furthermore, the plug CH and bit wire BL may be formed collectively, for example, by using a dual damascene method.

[0098] Although not shown in the diagram, a peripheral circuit CBA is formed on a semiconductor substrate SB, which is separate from the support substrate SS on which the laminate LM is formed, and is covered with an insulating layer 40. Contacts, vias, wiring, etc. are formed in the insulating layer 40 to bring the peripheral circuit CBA to the surface of the insulating layer 40 and connect to electrode pads etc. formed on the upper surface of the insulating layer 40.

[0099] Furthermore, the support substrate SS and the semiconductor substrate SB are bonded together using their respective insulating layers 50 and 40, and the electrode pads within the insulating layers 50 and 40 are connected. These insulating layers 50 and 40 can be bonded together by activating them beforehand, for example, through plasma treatment. Additionally, after bonding the insulating layers 54 and 40, annealing treatment can be performed to connect the electrode pads within the insulating layers 50 and 40 by Cu-Cu bonding or the like.

[0100] As shown in Figure 11(a), from this point onward, various processes are performed on the support substrate SS, which is bonded to the semiconductor substrate SB in an inverted state. Therefore, in the following drawings, the portions of the pillar PL and plate-shaped contact LI that protrude into the stopper layer DSLa are considered as the upper ends, and the various processes are shown from the upper end side of these pillar PL and plate-shaped contact LI.

[0101] Note that in the drawings from Figure 11(a) onward, only the upper ends of the pillar PL and plate-shaped contact LI are shown.

[0102] As shown in Figure 11(b), the support substrate SS is removed by cracking the interface between the stopper layer DSLa and the support substrate SS. In the memory region MR where pillars PL etc. are formed, the intermediate insulating layer OSL is used as a stopper layer and the stopper layer DSLa is removed. At this time, a photomask layer etc. (not shown) is formed on the stopper layer DSLa at a position overlapping with the upper end of the plate-shaped contact LI, and the stopper layer DSLa covering the upper end of the plate-shaped contact LI is left in place without being removed.

[0103] As a result, in the memory region MR, the upper end of the pillar PL protrudes above the intermediate insulating layer OSL. On the other hand, the upper end of the plate-shaped contact LI remains covered by the stopper layer DSLa.

[0104] As shown in Figure 11(c), the upper end of the pillar PL, which protrudes upward from the intermediate insulating layer OSL, is subjected to an implantation treatment with, for example, phosphorus or arsenic, thereby doping the semiconductor layer CN of the pillar PL with an N-type impurity via the memory layer ME. As a result of doping with these impurities, at least the upper end of the channel layer CN becomes an amorphous semiconductor layer, such as an amorphous silicon layer.

[0105] On the other hand, the intermediate insulating layer OSL suppresses the doping of these impurities into the main source wire DSLb. However, the above treatment may result in impurities doping the stopper layer DSLa covering the upper end of the plate-shaped contact LI, and the stopper layer DSLa may change from a polysilicon layer to an amorphous silicon layer. If impurities are doped into the stopper layer DSLa, the main source wire DSLb may also be doped with impurities via the intermediate insulating layer OSL. In this case, the impurity concentration of the stopper layer DSLa may be higher than that of the main source wire DSLb. Also, if impurities are not doped into the stopper layer DSLa, the impurity concentration of the stopper layer DSLa may be lower than that of the main source wire DSLb. If impurities are not doped into the stopper layer DSLa and impurities are not doped into the main source wire DSLb, both the stopper layer DSLa and the main source wire DSLb are maintained as undoped polysilicon layers or amorphous silicon layers.

[0106] As shown in Figure 11(d), the memory layer ME is removed from the upper end of the pillar PL that protrudes above the intermediate insulating layer OSL. Simultaneously, the intermediate insulating layer OSL is removed. This exposes the upper end of the channel layer CN of the pillar PL above the main source line DSLb. At this time, the insulating layer 54 of the plate-shaped contact LI remains because it is covered by the stopper layer DSLa. The intermediate insulating layer OSL, which is interposed between the stopper layer DSLa and the main source line DSLb and through which the plate-shaped contact LI penetrates, also remains.

[0107] As shown in Figure 12(a), an auxiliary source wire ASL is formed to cover the main source wire DSLb that has been exposed after the intermediate insulating layer OSL has been removed. At this time, the auxiliary source wire ASL is formed to cover the upper end of the pillar PL that protrudes above the main source wire DSLb and the stopper layer DSLa that covers the upper end of the plate-shaped contact LI.

[0108] The auxiliary source wire ASL is deposited as an undoped amorphous silicon layer. The auxiliary source wire ASL is used as a heat source that absorbs laser light during laser annealing. Subsequently, to reduce the contact resistance with the metal laminated on top of the auxiliary source wire ASL, ion implantation (implantation) of impurities such as phosphorus or arsenic that make the auxiliary source wire ASL N-type conductive may be performed on its surface. Further annealing or other processes may be performed after ion implantation to improve the conductivity of the auxiliary source wire ASL.

[0109] As shown in Figure 12(b), the channel layer CN of the pillar PL covered with the auxiliary source line ASL is irradiated with laser light, and the channel layer CN is annealed by the heat of the laser light. At this time, a laser light having a wavelength of 540 nm, such as a green laser, can be used. When a laser light with a wavelength of 540 nm is used, the channel layer CN can be heated to, for example, about 1100°C.

[0110] As described above, when laser light is applied, the auxiliary source line ASL absorbs the laser light and functions as a heat source. As a result, the auxiliary source line ASL is heated by the laser light, and the heat from the auxiliary source line ASL is further transferred to the upper end of the channel layer CN of the pillar PL, causing the channel layer CN to undergo annealing.

[0111] Thus, by performing annealing using laser light, the channel layer CN, which has become amorphous due to impurity doping, can be crystallized, and the N-type impurities doped in the channel layer CN can be activated. Furthermore, through such annealing, part or all of the auxiliary source line ASL, which was originally an amorphous silicon layer, may become a polysilicon layer, and part or all of the stopper layer DSLa, which was an amorphous silicon layer due to impurity doping, may become a polysilicon layer.

[0112] At this time, the laser light is also irradiated onto the formation region of the plate-shaped contact LI. The plate-shaped contact LI has a relatively large volume conductive layer 24, such as a tungsten layer, that extends in the X direction and the stacking direction of the laminate LM. However, the conductive layer 24 of the plate-shaped contact LI is covered with an insulating layer 54, such as a silicon oxide layer, which has a lower thermal conductivity than the conductive layer 24. Therefore, heating of the conductive layer 24 by the laser light is suppressed.

[0113] As shown in Figure 12(c), a barrier metal BM is formed on the auxiliary source wire ASL, which covers the main source wire DSLb including the protruding portions of the pillar PL and plate-shaped contact LI.

[0114] As shown in Figure 12(d), a metal layer TS is further formed to cover the barrier metal BM.

[0115] Subsequently, an insulating layer 60 is formed on the metal layer TS, and a plug PG is formed that penetrates the insulating layer 60. An electrode film EL is also formed in the insulating layer 60 and connected to the plug PG, and an insulating layer 70 is formed to cover the electrode film EL. Furthermore, an opening is made in the insulating layer 70 to expose a part of the electrode film EL, forming a pad region PD.

[0116] The semiconductor memory device 1 of the embodiment is manufactured as described above.

[0117] (Overview) Semiconductor memory devices such as three-dimensional non-volatile memory may be manufactured by forming peripheral circuits including transistors and other components, and laminates including word lines and pillar PLs, on separate substrates, and then bonding these substrates together.

[0118] Furthermore, after bonding the substrates together, various treatments may be performed on the back side of the support substrate that supports the laminate. These treatments on the back side may include, for example, doping the channel layer of the pillar with N-type impurities and activating it by annealing using laser light. Figures 13 and 14 show the process at this time.

[0119] Figures 13 and 14 show a method for doping the channel layer CNx of a semiconductor memory device with impurities according to a comparative example.

[0120] As shown in Figure 13(a), the upper surface of the semiconductor substrate to which the peripheral circuit and the laminate are bonded has a pillar PLx having a channel layer CNx with its upper end protruding into the stopper layer DSLa, and a plate-shaped contact LIx having an insulating layer 54x covering a conductive layer 24 with its upper end protruding into the stopper layer DSLa. Thus, the state of the semiconductor memory device of the comparative example in Figure 13(a) corresponds to the state in Figure 11(a) of the embodiment described above.

[0121] As shown in Figure 13(b), the support substrate SS and the stopper layer DSLa are removed. In this comparative example, the entire stopper layer DSLa is removed. As a result, not only the upper end of the pillar PLx but also the upper end of the plate-shaped contact LIx is exposed above the intermediate insulating layer OSL.

[0122] As shown in Figure 13(c), N-type impurities are doped into the protruding portion of the channel layer CNx of the pillar PL via the memory layer ME. As a result, the upper end of the channel layer CNx becomes an amorphous semiconductor layer, such as an amorphous silicon layer.

[0123] As shown in Figure 13(d), the memory layer ME is removed from the upper end of the protruding pillar PLx, and the intermediate insulating layer OSL covering the main source line DSLb is also removed. At this time, the insulating layer 54x covering the conductive layer 24 of the plate-shaped contact LIx is exposed at the upper end of the plate-shaped contact LIx. Therefore, along with the memory layer ME and intermediate insulating layer OSL of the pillar PLx, the insulating layer 54x of the plate-shaped contact LIx is also partially removed, resulting in a thinner layer.

[0124] As shown in Figure 14(a), an auxiliary source line ASL is formed that covers the entire main source line DSLb, etc.

[0125] As shown in Figure 14(b), the channel layer CN of the pillar PL covered with the auxiliary source line ASL is irradiated with laser light to crystallize the channel layer CNx and activate impurities in the channel layer CNx.

[0126] However, in the comparative example semiconductor memory device, variations may occur in the threshold voltage of the source-side selection gate formed on multiple pillars PLx. More specifically, in pillars PLx adjacent to plate-shaped contacts LIx, the threshold voltage of the selection gate line may shift to a higher voltage than the desired value.

[0127] The inventors conducted intensive research to solve the above problems and discovered that heat from the laser beam is dissipated to the relatively large volume conductive layer 24 of the plate-shaped contact LIx. This revealed that the pillar PLx adjacent to the plate-shaped contact LIx is not sufficiently heated by the laser beam.

[0128] As shown in Figure 14(c), the heat from the laser beam is dissipated into the conductive layer 24 of the plate-shaped contact LIx, resulting in insufficient crystallization of the channel layer CNx in the pillar PLx adjacent to the plate-shaped contact LIx, and it is thought that the impurities in the channel layer CNx are not sufficiently activated. This is presumed to cause a shift in the threshold voltage of the selected gate line.

[0129] The inventors conducted further research and discovered that the degree of heat dissipation by laser light changes depending on the thickness of the insulating layer 54x of the plate-shaped contact LIx.

[0130] According to the semiconductor memory device 1 of the embodiment, the plate-shaped contact LI has a projection that extends upward through the main source line DSLb, and the projection is positioned between the main source line DSLb and the auxiliary source line ASL and is covered with a stopper layer DSLa which is mainly composed of semiconductor material.

[0131] In this way, by leaving the stopper layer DSLa covering the upper end of the plate-shaped contact LI, it is possible to suppress the thinning of the insulating layer 54 of the plate-shaped contact LI when removing the memory layer ME etc. at the upper end of the pillar PL. By maintaining the insulating layer 54 at a sufficient thickness, the dissipation of heat from the conductive layer 24 of the plate-shaped contact LI due to the laser light is suppressed. Therefore, by irradiating with laser light, the crystallization of the channel layer CN can be sufficiently achieved and impurities in the channel layer CN can be sufficiently activated, and variations in the threshold voltage of the selected gate STD formed on the pillar PL can be suppressed.

[0132] According to the semiconductor memory device 1 of this embodiment, the plate-shaped contact LI has an insulating layer 54 disposed on the upper surface and side wall of the plate-shaped contact LI, and a conductive layer 24 which is a core material with a higher thermal conductivity than the insulating layer 54. In this way, the conductive layer 24, which has a relatively large volume, is insulated by the insulating layer 54 which has sufficient thickness, so that the heat from the laser light is not transferred to the conductive layer 24 and dissipated.

[0133] According to the semiconductor memory device 1 of this embodiment, the semiconductor layer covering the upper end of the plate-shaped contact LI includes a stopper layer DSLa in addition to the auxiliary source line ASL, and is thicker than the auxiliary source line ASL, which is a semiconductor layer covering the upper end of the pillar PL and does not include the stopper layer DSLa. As a result, impurities in the channel layer CN can be sufficiently activated by laser irradiation, and variations in the threshold voltage of the selection gate STD formed on the pillar PL can be suppressed.

[0134] According to the manufacturing method of the semiconductor memory device 1 of the embodiment, before impurities are injected into the channel layer CN of the pillar PL, a portion of the stopper layer DSLa is removed while leaving a portion covering one end of the plate-shaped contact LI, thereby exposing one end of the pillar PL. This allows the channel layer CN to be sufficiently crystallized by laser irradiation, and variations in the threshold voltage of the selection gate STD formed on the pillar PL can be suppressed.

[0135] In the manufacturing method of the semiconductor memory device 1 of this embodiment, the main source line DSLb and the auxiliary source line ASL are stacked with an intermediate insulating layer OSL in between. This allows the intermediate insulating layer OSL to be used as a stopper layer when removing the stopper layer DSLa in order to expose the upper end of the pillar PL.

[0136] According to the manufacturing method of the semiconductor memory device 1 of this embodiment, after impurities are injected into the channel layer CN of the pillar PL, the intermediate insulating layer OSL is removed together with the memory layer ME. At this time, as described above, the upper end of the plate-shaped contact LI is protected by the stopper layer DSLa, so that the insulating layer 54 of the plate-shaped contact LI does not become thin.

[0137] According to the manufacturing method of the semiconductor memory device 1 of this embodiment, the irradiation of laser light includes irradiating one end of the plate-shaped contact LI covered with the stopper layer DSLa, along with the channel layer CN of the pillar PL. In this way, even when the entire surface is irradiated with laser light, the above configuration suppresses the transfer and dissipation of heat from the laser light to the conductive layer 24.

[0138] According to the manufacturing method of the semiconductor memory device 1 of the embodiment, the irradiation with laser light includes crystallizing the channel layer CN of the pillar PL, which has become amorphous due to impurity doping. As described above, the heat from the laser light is suppressed from being transmitted to and dissipated by the conductive layer 24 of the plate-shaped contact LI, so that the channel layer CN can be sufficiently crystallized and the impurities can be activated.

[0139] In the above embodiment, the semiconductor memory device 1 is provided with a stacked LM having a 2-tier structure in which two stacked layers LMa and LMb are stacked vertically. However, the configuration of the stacked layer is not limited to 2 tiers; it may be 1 tier or 3 tiers or more.

[0140] Furthermore, in the above-described embodiment, the stair region SR is positioned at both ends of the laminate LM in the X direction. However, the stair region may be positioned in the center of the laminate in the X direction, and the memory region MR may be positioned at both ends in the X direction.

[0141] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of symbols]

[0142] 1... Semiconductor memory device, 40, 50... Insulating layer, ASL... Auxiliary source line, BM... Barrier metal layer, CN... Channel layer, CR... Core layer, DSLa... Stopper layer, DSLb... Main source line, LM, LMa, LMb, LMga, LMgb, LMsa, LMsb... Stack, MC... Memory cell, ME... Memory layer, MR... Memory area, NL, OL... Insulating layer, OSL... Intermediate insulating layer, PL... Pillar, SGD, SGS... Select gate line, SL... Source line, STD, STS... Select gate, TS... Metal layer, WL... Word line.

Claims

1. A laminate in which multiple conductive layers and multiple first insulating layers are alternately stacked one layer at a time, A plate-like portion extending within the laminate in a first direction intersecting the lamination direction and the lamination direction, and dividing the laminate in a second direction intersecting the first direction and the lamination direction, A pillar is arranged adjacent to the plate-like portion in the second direction and includes a semiconductor layer extending within the laminate in the lamination direction, A first layer, mainly composed of semiconductors, is placed above the aforementioned laminate, The first layer is positioned above the second layer, and the second layer is mainly composed of a semiconductor, The plate-like portion is It has a projection that penetrates the first layer and extends upward, The aforementioned protrusion is Displaced between the first and second layers, and covered by a third layer mainly composed of semiconductors, Semiconductor memory device.

2. The third layer is, Of the plate-like portion and the pillar, the plate-like portion is selectively positioned to overlap with the pillar in the stacking direction. The semiconductor memory device according to claim 1.

3. The present invention further comprises a second insulating layer interposed between the first layer and the third layer. The semiconductor memory device according to claim 2.

4. The plate-like portion is A third insulating layer is disposed on the upper surface and side wall of the plate-like portion, The device has a core material with a higher thermal conductivity than the third insulating layer, The semiconductor memory device according to claim 1.

5. The first to third layers include at least one of a polysilicon layer or an amorphous silicon layer. Of the first to third layers, at least the third layer contains an impurity of the first conductivity type. The semiconductor memory device according to claim 1.

6. A laminate in which multiple conductive layers and multiple first insulating layers are alternately stacked one layer at a time, A plate-like portion extending within the laminate in a first direction intersecting the lamination direction and the lamination direction, and dividing the laminate in a second direction intersecting the first direction and the lamination direction, A pillar is arranged adjacent to the plate-like portion in the second direction and includes a semiconductor layer extending within the laminate in the lamination direction, The laminate comprises a first layer, which is positioned above the aforementioned laminate and is mainly composed of a semiconductor, The upper end of the plate-like portion and the upper end of the pillar are, It extends upward through the laminate and is covered by the first layer, The first layer covering the upper end of the plate-like portion is A layer thicker than the first layer covering the upper end of the pillar, Semiconductor memory device.

7. The first layer covering the upper end of the plate-like portion is Including a second insulating layer interposed at a predetermined position in the thickness direction of the layer, The semiconductor memory device according to claim 6.

8. A laminate is formed in which a plurality of conductive layers and a plurality of first insulating layers are alternately stacked one by one on a first layer mainly composed of a semiconductor; a plate-like portion penetrates the laminate and the first layer, extends in a first direction intersecting the stacking direction of the laminate, and divides the laminate in a second direction intersecting the first direction and the stacking direction; and a pillar is arranged adjacent to the plate-like portion in the second direction, penetrates the laminate and the first layer, and includes a semiconductor layer covered by a memory layer. A first conductivity type impurity is injected into the semiconductor layer that protrudes from the first layer and is covered by the memory layer, the portion of the memory layer that protrudes from the first layer is removed, the semiconductor layer protruding from the first layer is covered with a second layer mainly composed of semiconductor material, and the semiconductor layer is irradiated with laser light using the second layer. The plate-like portion and the pillar are The laminate is formed to penetrate the first layer and reach a third layer mainly composed of semiconductor material. Before implanting the impurities into the semiconductor layer, While leaving a portion that covers one end of the plate-like part, a part of the third layer is removed to expose one end of the pillar. A method for manufacturing semiconductor memory devices.

9. The first layer and the second layer are laminated with a second insulating layer in between. After impurities are injected into the semiconductor layer, the second insulating layer is removed together with the memory layer. The method for manufacturing a semiconductor memory device according to claim 8.

10. The formation of the plate-like portion is A third insulating layer is formed to cover one end of the plate-like portion and the side wall, This includes forming a core material with a higher thermal conductivity than the third insulating layer, The method for manufacturing a semiconductor memory device according to claim 8.

11. The irradiation of the aforementioned laser light This includes crystallizing the semiconductor layer that has become amorphous due to the doping of the aforementioned impurities. The method for manufacturing a semiconductor memory device according to claim 8.

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