Printed circuit board

Abstract

One of several objectives of the present invention is to provide a printed circuit board that can cut a multilayer substrate including a glass layer in a relatively simple process. [Solution] The present invention relates to a printed circuit board comprising a glass layer, an insulating body disposed on the glass layer, a plurality of wiring layers disposed within the insulating body, and a plurality of via layers disposed within the insulating body and connected to one or more of the plurality of wiring layers, wherein at least one side surface of the insulating body has a plurality of recesses and a plurality of protrusions arranged alternately with respect to each other in the stacking direction in cross-section.

Description

Technical Field

[0001] The present invention relates to a printed circuit board.

Background Art

[0002] In order to meet the high-performance and miniaturization strategies of semiconductors, the levels of miniaturization and high density required for printed circuit boards are increasing. For example, in order to manufacture high-end products such as server boards, high-multi-layer and large-sized boards are required. However, as the number of wiring layers increases and the size of the main body becomes larger, the board may be more vulnerable to warpage. In order to solve such problems, it is considered to use a glass core. However, glass may be more likely to crack compared to general epoxy-based substrates. For example, initial cracks may occur during cutting, and the glass may crack.

Summary of the Invention

Problems to be Solved by the Invention

[0003] One of several objects of the present invention is to provide a printed circuit board capable of cutting a multi-layer board including a glass layer in a relatively simple process.

[0004] Another one of several objects of the present invention is to provide a printed circuit board capable of preventing initial cracks in the glass layer during the cutting process.

[0005] Still another one of several objects of the present invention is to provide a printed circuit board capable of minimizing the stress in the glass layer by increasing the surface area of the insulating material during the cutting process.

Means for Solving the Problems

[0006] One of several solutions of the present invention involves forming a stacked via structure by plating on the cutting lines between units when manufacturing a multilayer substrate including a glass layer, and then removing the stacked via structure formed on the cutting lines by etching during the cutting process, and cutting away the resin, glass residue, etc., using a blade.

[0007] For example, a printed circuit board according to one example includes a glass layer, an insulating body disposed on the glass layer, a plurality of wiring layers disposed within the insulating body, and a plurality of via layers disposed within the insulating body and connected to one or more of the plurality of wiring layers, wherein at least one side of the insulating body may have a plurality of recesses and a plurality of protrusions arranged alternately with respect to each other in the stacking direction in cross-section.

[0008] For example, a printed circuit board according to one example includes a glass layer, a plurality of insulating layers disposed on the glass layer, a plurality of wiring layers disposed within each of the plurality of insulating layers, and a plurality of via layers disposed within each of the plurality of insulating layers and connected to one or more of the plurality of wiring layers, wherein any two insulating layers adjacent to each other in the stacking direction may have a step difference in cross-section. [Effects of the Invention]

[0009] One of the various effects of the present invention is the ability to provide a printed circuit board that can cut a multilayer substrate including a glass layer in a relatively simple process.

[0010] Another effect of the present invention is to provide a printed circuit board that can prevent initial cracking of the glass layer during the cutting process.

[0011] Another effect of the present invention is that it can provide a printed circuit board that minimizes stress within the glass layer by increasing the surface area of ​​the insulating material during the cutting process. [Brief explanation of the drawing]

[0012] [Figure 1] This is a block diagram illustrating an example of an electronic equipment system. [Figure 2] This is a schematic cross-sectional view showing an example of a printed circuit board. [Figure 3a] Figure 2 is a schematic cross-sectional view showing an example of the cutting process in the manufacturing process of a printed circuit board. [Figure 3b] Figure 2 is a schematic cross-sectional view showing an example of the cutting process in the manufacturing process of a printed circuit board. [Figure 3c] Figure 2 is a schematic cross-sectional view showing an example of the cutting process in the manufacturing process of a printed circuit board. [Modes for carrying out the invention]

[0013] The present invention will be described below with reference to the attached drawings. The shapes and sizes of the elements in the drawings may be exaggerated or reduced for clearer explanation.

[0014] Figure 1 is a block diagram illustrating an example of an electronic equipment system.

[0015] Referring to the drawing, the electronic device 1000 houses the main board 1010. The main board 1010 is physically and / or electrically connected to chip-related components 1020, network-related components 1030, and other components 1040, etc. These are also coupled with other electronic components, which will be described later, to form various signal lines 1090.

[0016] The chip-related components 1020 include, but are not limited to, memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), and flash memory; application processor chips such as central processors (e.g., CPUs), graphics processors (e.g., GPUs), digital signal processors, cryptographic processors, microprocessors, and microcontrollers; and logic chips such as analog-to-digital converters and ASICs (application-specific ICs). It goes without saying that other different forms of chip-related electronic components may also be included. Furthermore, these chip-related components 1020 may be combined with each other. The chip-related components 1020 may also be in the form of a package that includes the chips and electronic components mentioned above.

[0017] Network-related component 1030 includes, but is not limited to, any other wireless and wired protocols designated as Wi-Fi (IEEE 802.11 family, etc.), WiMAX (IEEE 802.16 family, etc.), IEEE 802.20, LTE (long term evolution), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPS, GPRS, CDMA, TDMA, DECT, Bluetooth, 3G, 4G, 5G, and later. It also includes any other diverse wireless or wired standards and protocols. Furthermore, it goes without saying that network-related component 1030 may be combined with chip-related component 1020.

[0018] Other components 1040 include high-frequency inductors, ferrite inductors, power inductors, ferrite beads, LTCCs (low-temperature co-firing ceramics), EMI (electromagnetic interference) filters, MLCCs (multi-layer ceramic condensers), etc. However, they are not limited to these, and may also include other passive elements in chip component form used for various other applications. It goes without saying that other components 1040 may be combined with chip-related components 1020 and / or network-related components 1030.

[0019] Depending on the type of electronic device 1000, the electronic device 1000 may include other electronic components that are physically and / or electrically connected to the main board 1010 or not. Examples of other electronic components include, but are not limited to, audio codecs, video codecs, power amplifiers, compasses, accelerometers, gyroscopes, speakers, mass storage devices (e.g., hard disk drives), CDs (compact disks), DVDs (digital versatile disks), etc. Needless to say, other electronic components used for various purposes may also be included depending on the type of electronic device 1000.

[0020] The electronic device 1000 may be, for example, a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automotive device, a server, or the like. However, it is not limited thereto, and needless to say, it may be any other electronic device that processes data other than these.

[0021] FIG. 2 is a cross-sectional view schematically showing an example of a printed circuit board.

[0022] Referring to the drawings, an example of a printed circuit board 100 may include a glass layer 110, a first insulating body 111 disposed on the upper surface of the glass layer 110, a plurality of first wiring layers 121 disposed within the first insulating body 111, a plurality of first via layers 131 disposed within the first insulating body 111, a second insulating body 112 disposed on the lower surface of the glass layer 110, a plurality of second wiring layers 122 disposed within the second insulating body 112, a plurality of second via layers 132 disposed within the second insulating body 112, and metal vias 130 penetrating at least a portion between the upper and lower surfaces of the glass layer 110. The first insulating body 111 may include a plurality of first insulating layers, in which case the uppermost first insulating layer among the plurality of first insulating layers may include a first passivation layer 111b, and the remaining first insulating layers may constitute a first insulating section 111a for build-up. The second insulating body 112 may include a plurality of second insulating layers, in which case the lowest second insulating layer may include a second passivation layer 112b, and the remaining second insulating layers may constitute a build-up second insulating portion 112a. If necessary, the build-up layer may be formed only on the upper or lower side of the glass layer 110. For example, the first insulating body 111, the plurality of first wiring layers 121, and the plurality of first via layers 131 may be omitted, or the second insulating body 112, the plurality of second wiring layers 122, and the plurality of second via layers 132 may be omitted.

[0023] On the one hand, after building up an insulating material on a glass layer and then cutting it in unit form, there may be a limit to cutting the insulating material and the glass layer at once. For example, a nanosecond ultraviolet laser may be required to cut the insulating material, and a picosecond infrared laser may be required to cut the glass layer. However, initial cracks may occur in the glass layer during such a laser cutting process, and the glass layer may crack. Therefore, in the process of forming metal vias in the glass layer and the build-up process on the glass layer, a stacked via structure is formed by plating on the cutting line between units, and then the stacked via structure formed on the cutting line is removed by etching in the subsequent cutting process, and the resin and glass residues are considered to be cut using a blade. In this case, the above-mentioned problems can be solved. For example, a multilayer substrate including a glass layer can be cut in a relatively simple process, initial cracks in the glass layer can be prevented during the cutting process, and the stress in the glass layer can be minimized by increasing the surface area of the insulating material.

[0024] From such a perspective, the printed circuit board 100 that can be manufactured in the above-mentioned unit cutting process can have a plurality of recesses R1 and a plurality of protrusions P1, at least one side surface of the first insulating body 111 being alternately arranged with each other in the stacking direction in the cross section. Also, at least one side surface of the second insulating body 112 can have a plurality of recesses R2 and a plurality of protrusions P2 alternately arranged with each other in the stacking direction in the cross section. Also, at least one side surface of the glass layer 110 may be substantially flat. At this time, the above-mentioned at least one side surface of each of the first and second insulating bodies 111 and 112 and the above-mentioned at least one side surface of the glass layer 110 may be arranged in the same direction as each other. For example, the above-mentioned at least one side surface of each of the first and second insulating bodies 111 and 112 may be connected to each other through the above-mentioned at least one side surface of the glass layer 110 in the stacking direction. Here, the at least one side surface may be any one side surface, but is not limited thereto, and may include each of a plurality of side surfaces.

[0025] Furthermore, from this viewpoint, each of the plurality of recesses R1 located on at least one side of the first insulating body 111 may be located at substantially the same level as each of the plurality of first wiring layers 121, and each of the plurality of protrusions P1 located on at least one side of the first insulating body 111 may be located at substantially the same level as each of the plurality of first via layers 131. In this case, each side of the plurality of recesses R1 located on at least one side of the first insulating body 111 may be recessed inward from at least one side of the glass layer 110, and each side of the plurality of protrusions P1 located on at least one side of the first insulating body 111 may be substantially coplane with at least one side of the glass layer 110. Also, each of the plurality of recesses R2 located on at least one side of the second insulating body 112 may be located at substantially the same level as each of the plurality of second wiring layers 122, and each of the plurality of protrusions P2 located on at least one side of the second insulating body 112 may be located at substantially the same level as each of the plurality of second via layers 132. In this case, each of the multiple recesses R2 located on at least one side of the second insulating body 112 can be recessed inward from at least one side of the glass layer 110, and each of the multiple protrusions P2 located on at least one side of the second insulating body 112 can be substantially coplane with at least one side of the glass layer 110.

[0026] On the other hand, the shapes of the multiple recesses R1 and R2 are not particularly limited, and the corners may be recessed so as to be substantially right angles, or they may be recessed so as to be substantially curved. Also, the sides of the multiple recesses R1 and R2 may be substantially vertical, but are not limited to this, and may be substantially curved. Also, the shapes of the multiple protrusions P1 and P2 are not particularly limited, and they may protrude so as to be substantially right angles, or they may protrude so as to be substantially curved. Also, the sides of the multiple protrusions P1 and P2 may be substantially vertical, but are not limited to this, and may be substantially curved.

[0027] From a similar viewpoint, in the printed circuit board 100 that can be manufactured by the unit cutting process described above, any two adjacent first insulating layers in the first insulating body 111 that are connected to each other may have a step difference in cross-section. Similarly, any two adjacent second insulating layers in the second insulating body 112 that are connected to each other may have a step difference in cross-section. Also, any one side surface of the glass layer 110 may be substantially flat. In this case, any two adjacent first and second insulating layers in the first and second insulating bodies 111 and 112, respectively, that are connected to each other may be arranged in the same direction as the one side surface of the glass layer 110. For example, any one side surface of any two adjacent first insulating layers in the first insulating body 111 and any one side surface of any two second insulating layers in the second insulating body 112 may be connected to each other in the stacking direction via the one side surface of the glass layer 110. On the other hand, if necessary, such structural features can be applied substantially similarly to other aspects of the multiple first and second insulating layers and glass layer 110 contained in each of the first and second insulating bodies 111 and 112, not just one aspect.

[0028] Furthermore, from a similar viewpoint, one side of any two adjacent first insulating layers included in the first insulating body 111 may be recessed inward more than the other side. Also, one side of any two adjacent first insulating layers included in the first insulating body 111 may be recessed inward more than the other side of the glass layer 110, and the other side may be substantially coplane with the other side of the glass layer 110. Furthermore, one side of any two adjacent second insulating layers included in the second insulating body 112 may be recessed inward more than the other side. Also, one side of any two adjacent second insulating layers included in the second insulating body 112 may be recessed inward more than the other side of the glass layer 110, and the other side may be substantially coplane with the other side of the glass layer 110.

[0029] On the other hand, the printed circuit board 100 in this example configuration may be, but is not limited to, a high-multilayer and large-area board suitable for use in high-capacity servers, etc. It may also be, but is not limited to, a package board and / or an interposer board.

[0030] In the following section, the components of an example printed circuit board 100 will be described in more detail with reference to the drawings.

[0031] The glass layer 110 may include glass, which is an amorphous solid. The glass may include, for example, pure silicon dioxide (about 100% SiO2), soda-lime glass, borosilicate glass, aluminosilicate glass, etc. However, it is not limited to these, and alternative glass materials such as fluorine glass, phosphoric acid glass, and chalcogen glass can also be used. Furthermore, other additives may be included to form glass with specific physical properties. Such additives may include not only calcium carbonate (e.g., lime) and sodium carbonate (e.g., soda), but also magnesium, calcium, manganese, aluminum, lead, boron, iron, chromium, potassium, sulfur, and antimony, as well as carbonates and / or oxides of these elements and other elements. On the other hand, the glass layer 110 can be distinguished from organic insulating materials containing glass fibers (glass fiber, glass cloth, glass fabric), such as CCL (copper clad laminate) and PPG (prepreg). The glass layer 110 may be in the form of, for example, a glass plate. The through-holes in which the metal vias 130 are placed can penetrate between the upper and lower surfaces of the glass layer 110. The glass layer 110 may, but is not limited to, have a substantially rectangular shape on a plane.

[0032] The metal via 130 may contain metals such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. For example, the metal via 130 may contain a titanium layer and a copper layer formed by sputtering, i.e., sputtered titanium and sputtered copper, as seed layers, and electroplated copper formed by electroplating based on these, as a plating layer. If necessary, the seed layers may further include a titanium layer formed by sputtering and chemical copper formed by electroless plating on the copper layer. The metal via 130 can perform various functions depending on the design. For example, the metal via 130 may include through-holes for signal transmission, through-holes for power transmission, through-holes for ground transmission, etc. The metal via 130 may include filled vias in which at least a portion of the through-hole is filled with metal. The metal via 130 may have a substantially hourglass shape, or it may have a substantially cylindrical shape. The upper and lower surfaces of the metal via 130 can be recessed inward from the upper and lower surfaces of the glass layer 110, respectively, so the upper and lower surfaces of the metal via 130 can have a step difference from the upper and lower surfaces of the glass layer 110, respectively, but are not limited to this. There may be multiple metal vias 130.

[0033] The first and second insulating bodies 111 and 112 may each contain insulating material. The insulating material may be a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or may contain inorganic fillers, organic fillers and / or glass fibers (glass fiber, glass cloth, glass fabric) together with the resin. Examples of insulating materials include, but are not limited to, PPG (Prepreg), ABF (Ajinomoto Build-up Film), PID (Photo Imageable Dielectric), and SR (Solder Resist). The first insulating body 111 may contain a plurality of first insulating layers. Each of the plurality of first insulating layers may contain the insulating material described above. The uppermost first insulating layer among the plurality of first insulating layers may contain a first passivation layer 111b, and the remaining first insulating layers may constitute a first insulating section 111a for build-up. The first insulating section 111a and the first passivation layer 111b may contain different insulating materials, but are not limited to this. The remaining first insulating layers constituting the first insulating portion 111a may have boundaries separated from each other, or they may be integrated to the extent that their boundaries cannot be separated. The second insulating body 112 may include a plurality of second insulating layers. Each of the plurality of second insulating layers may contain the insulating material described above. The second insulating layer located at the bottom of the plurality of second insulating layers may include a second passivation layer 112b, and the remaining second insulating layers may constitute a second insulating portion 112a for build-up. The second insulating portion 112a and the second passivation layer 112b may contain different insulating materials, but are not limited to this. The remaining first insulating layers constituting the second insulating portion 112a may have boundaries separated from each other, or they may be integrated to the extent that their boundaries cannot be separated. The first passivation layer 111b may have a plurality of first openings that expose at least a portion of the first wiring layer located at the top of the plurality of first wiring layers 121. The second passivation layer 112b may have a plurality of second openings that expose at least a portion of the second wiring layer located at the bottom of the plurality of second wiring layers 122.The patterns exposed through the first and second openings may, but are not limited to, SMD (Solder Mask Defined) and / or NSMD (Non Solder Mask Defined) types.

[0034] Each of the multiple first and second wiring layers 121, 122 may contain a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. For example, each of the multiple first and second wiring layers 121, 122 may contain chemical copper formed by electroless plating as a seed layer, and electroplated copper formed by electroplating based on this as a plating layer. Each of the multiple first and second wiring layers 121, 122 can perform various functions depending on the design. For example, each of the multiple first and second wiring layers 121, 122 may contain signal patterns, power patterns, ground patterns, etc. These patterns may have various forms such as lines, traces, planes, lands, and pads. The lowest of the multiple first wiring layers 121 may be connected to the upper side of the metal via 130. The uppermost of the multiple second wiring layers 122 may be connected to the underside of the metal via 130. If necessary, the lowest first wiring layer and the uppermost second wiring layer may not be directly connected to the metal via 130, but may be connected via a connecting via. In this case, the metal via 130 may have a structure without pads or lands.

[0035] Each of the multiple first and second via layers 131 and 132 can contain a metal. The metals can include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. For example, each of the multiple first and second via layers 131 and 132 can contain chemical copper formed by electroless plating as a seed layer, and electroplated copper formed by electroplating based on this as a plating layer. Each of the multiple first and second via layers 131 and 132 can perform various functions depending on the design. For example, each of the multiple first and second via layers 131 and 132 can contain signal transmission connection vias, power transmission connection vias, ground transmission connection vias, and so on. The multiple first and second via layers 131, 132 may each include filled vias in which at least a portion of the via hole is filled with metal, but may also include conformal vias in which metal is arranged along the wall surface of the via hole. The multiple first and second via layers 131, 132 may each include multiple connecting vias. For example, the multiple first via layers 131 may include one or more substantially tapered first connecting vias such that the width of the upper end is greater than the width of the lower end in cross-section. Similarly, the multiple second via layers 132 may include one or more substantially tapered second connecting vias such that the width of the lower end is greater than the width of the upper end in cross-section.

[0036] Figures 3a to 3c are schematic cross-sectional views illustrating an example of the cutting process in the manufacturing process of the printed circuit board shown in Figure 2.

[0037] Referring to Figure 3a, a panel-level multilayer substrate can be prepared having multiple units and a cutting region CL between the multiple units. Each of the multiple units may include a structure in which first and second insulating bodies 111, 112, multiple first and second wiring layers 121, 122, and multiple first and second via layers 131, 132 are arranged on both sides of a glass layer 110 on which metal vias 130 are formed. A stacked via structure 150 formed by plating may be formed in the cutting region CL. The stacked via structure 150 can be formed together at substantially the same level in each layer when forming the metal vias 130, multiple first and second wiring layers 121, 122, and multiple first and second via layers 131, 132 in each of the multiple units. For example, the stacked via structure 150 may include a via layer penetrating the glass layer 110, and multiple pattern layers and multiple via layers arranged on the first and second insulating bodies 111, respectively. The first and second passivation layers 111b and 112b of the first and second insulating bodies 111 and 112, respectively, may have openings formed so as to expose the upper and lower surfaces of such a stacked via structure 150.

[0038] Referring to Figure 3b, the stacked via structure 150 formed in the cutting region CL can be removed. For example, the stacked via structure 150 can be removed by performing a metal etching process through the aforementioned openings formed in the first and second passivation layers 111b and 112b, respectively. In this case, even without two types of laser equipment for cutting the glass layer and the insulating material, multiple through-holes H that distinguish the units can be formed in the cutting region CL. Therefore, the process can be made relatively simple, and the process cost can be reduced. In addition, it is possible to prevent the occurrence of initial cracks in the glass layer 110. Furthermore, it is possible to minimize the stress generated in the glass layer 110 due to the increase in the surface area of ​​the insulating material.

[0039] Referring to Figure 3c, residual resin and glass residue in the cutting region CL can be removed. For example, a portion of the penetration H can be cut using a blade. In this case, multiple recesses R1, R2 and multiple protrusions P1, P2 can be formed on the sides of the first and second insulating bodies 111 and 112 of each unit that are located in the cutting region CL, as described above. In addition, the sides of the glass layer 110 located in the cutting region CL can be made substantially flat. Thus, the cutting process according to this example can be made relatively simple as described above, process costs can be reduced, and initial cracks can be prevented from occurring in the glass layer 110 during the cutting process. Furthermore, the stress generated in the glass layer 110 due to the increase in the surface area of ​​the insulating material can be minimized.

[0040] Through a series of processes, the printed circuit board 100 according to the example described above can be manufactured, and other details may be substantially the same as those described above.

[0041] In this invention, the expression "cover" can include not only covering the entire object but also covering at least a part of it, and can include not only directly covering the object but also indirectly covering it. Furthermore, the expression "fill" can include not only completely filling the object but also filling at least a part of it, and can also include nearly filling the object. For example, it can include cases where there are some gaps or voids. Also, the expression "enclose" can include not only completely enclosing the object but also partially enclosing it and generally enclosing it. Furthermore, "expose" can include not only completely exposing the object but also partially exposing it, and "exposure" can mean that the component is exposed from what it is embedded in.

[0042] In this invention, "placed within a through hole or via hole" can include not only cases where the object is completely placed within a through hole or via hole, but also cases where it partially protrudes upward or downward on a cross-section. For example, if the object is placed within a through hole or via hole on a plane, it can be interpreted in a broader sense.

[0043] In this invention, the determination can be made including process errors, positional deviations, and measurement errors that substantially occur during the manufacturing process. For example, "substantially the same direction" can include not only exactly the same direction but also approximately the same direction. Also, "substantially coplanar" can include not only cases where the surfaces are completely coplanar but also cases where they are approximately coplanar. Furthermore, "substantially having a specific shape" can include not only cases where the surfaces are exactly that shape but also cases where they are approximately that shape. In addition, "substantially flat" can include cases where the surfaces are approximately flat but also cases where they are completely flat. Moreover, "substantially the same insulating material" can mean not only cases where the insulating material is completely identical but also cases where the insulating material is of the same type.Therefore, even if the composition of the insulating material is substantially the same, their specific composition ratios may differ slightly.

[0044] In this invention, "on a cross-section" can mean the cross-sectional shape when the object is cut vertically, or the cross-sectional shape when the object is viewed from the side. "On a plane" can mean the planar shape when the object is cut horizontally, or the planar shape when the object is viewed from the top or bottom.

[0045] In this invention, terms such as "lower side," "lower part," and "bottom surface" are used for convenience to mean the downward direction relative to the cross-section in the drawing, while terms such as "upper side," "upper part," and "top surface" are used to mean the opposite direction. However, this is merely a definition of direction for explanatory purposes, and it goes without saying that the scope of rights in the patent claims is not particularly limited by such descriptions of direction, and the concepts of up / down can be changed at any time.

[0046] In this invention, "connected" is a concept that includes not only direct connection but also indirect connection via an adhesive layer or the like. Furthermore, "electrically connected" is a concept that includes both cases where they are physically connected and cases where they are not connected. In addition, expressions such as "first," "second," etc., are used to distinguish one component from another and do not limit the order and / or importance of the components. In some cases, within the scope of the rights, the first component may be named the second component, and similarly, the second component may be named the first component.

[0047] In this invention, "thickness, width, length, depth, line width, spacing, pitch, separation distance, surface roughness," etc., can be measured using a scanning microscope or optical microscope based on a cross-section obtained by polishing or cutting the printed circuit board. The cut cross-section can be a vertical or horizontal cross-section, and each value can be measured based on the required cut cross-section. For example, the width of the upper and / or lower ends of a via can be measured on a cross-section cut along the central axis of the via. In this case, if the values ​​are not constant, the values ​​can be determined by the average value of the values ​​measured at any five points.

[0048] The expression "example" as used in this invention does not mean that each embodiment is the same as another, but is provided to highlight and illustrate the unique and distinct features of each. However, the examples presented above do not preclude their realization in combination with features of other examples. For example, even if a matter described in a particular example is not described in another example, it can be understood as a description related to that other example, unless there is a description in the other example that contradicts or is contrary to that description.

[0049] The terms used in this invention are for illustrative purposes only and are not intended to limit the invention. In this context, singular expressions include plural expressions unless the context clearly indicates a different meaning. [Explanation of symbols]

[0050] 1000:Electronic equipment 1010: Mainboard 1020: Chip-related components 1030: Network-related components 1040: Other parts 1050: Camera 1060: Antenna 1070: Display 1080: Battery 1090: Signal line 100: Printed circuit board 110: Glass layer 111, 112: Insulating body 111a, 112a: Insulation part 111b, 112b: Passivation layer 121, 122: Wiring layer 130: Metal Via 131, 132: Beer layer 150: Stacked via structure H: Penetration part P1, P2: Protrusion R1, R2: Recessed section CL: Cutting area

Claims

1. A glass layer, An insulating body disposed on the glass layer, Multiple wiring layers are arranged within the aforementioned insulating body, It includes a plurality of via layers, each disposed within the insulating body and connected to one or more of the plurality of wiring layers, A printed circuit board wherein at least one side surface of the insulating body has a plurality of recesses and a plurality of protrusions arranged alternately with respect to each other in the stacking direction in cross-section.

2. Each of the plurality of recesses is positioned at the same level as each of the plurality of wiring layers. The printed circuit board according to claim 1, wherein each of the plurality of protrusions is positioned at the same level as each of the plurality of via layers.

3. The printed circuit board according to claim 1, wherein at least one side of the glass layer, which is arranged in the same direction as at least one side of the insulating body, is flat.

4. The printed circuit board according to claim 3, wherein each of the sides of the plurality of recesses is recessed inward from at least one side of the glass layer.

5. The printed circuit board according to claim 3, wherein each of the sides of the plurality of protrusions is coplane with at least one side of the glass layer.

6. The insulating body includes a first insulating body disposed on the upper surface of the glass layer and a second insulating body disposed on the lower surface of the glass layer. The plurality of wiring layers include a plurality of first wiring layers each arranged within the first insulating body and a plurality of second wiring layers each arranged within the second insulating body. The plurality of via layers include a plurality of first via layers, each disposed within the first insulating body and connected to one or more of the plurality of first wiring layers, and a plurality of second via layers, each disposed within the second insulating body and connected to one or more of the plurality of second wiring layers. The printed circuit board according to claim 1, wherein each of the first and second insulating bodies has at least one side surface that is arranged in the same direction from each other, and each of the plurality of recesses and the plurality of protrusions.

7. The invention further includes a metal via that penetrates at least a portion of the space between the upper and lower surfaces of the glass layer, The printed circuit board according to claim 6, wherein the lowest of the plurality of first wiring layers and the uppermost of the plurality of second wiring layers are each connected to the metal via.

8. Each of the plurality of first via layers includes one or more tapered first connecting vias in cross-section, the width of which is greater at the upper end than at the lower end. The printed circuit board according to claim 6, wherein each of the plurality of second via layers includes one or more tapered second connecting vias, the width of which is greater at the lower end than at the upper end in cross-section.

9. A glass layer, Multiple insulating layers arranged on the glass layer, A plurality of wiring layers are arranged within each of the plurality of insulating layers, It includes a plurality of via layers, each disposed within the plurality of insulating layers and each connected to one or more of the plurality of wiring layers, A printed circuit board in which any two of the aforementioned insulating layers that are adjacent to each other in the stacking direction have a step difference in cross-section.

10. The printed circuit board according to claim 9, wherein one side of any two adjacent insulating layers is recessed inward more than the other side.

11. The printed circuit board according to claim 9, wherein one side of the glass layer, which is arranged in the same direction as one connected side of any two adjacent insulating layers, is flat.

12. One side of any two adjacent insulating layers is recessed inward more than one side of the glass layer. The printed circuit board according to claim 11, wherein one side surface of any two adjacent insulating layers is coplane with one side surface of the glass layer.

13. The plurality of insulating layers include a plurality of first insulating layers disposed on the upper surface of the glass layer and a plurality of second insulating layers disposed on the lower surface of the glass layer. The plurality of wiring layers include a plurality of first wiring layers each disposed within the plurality of first insulating layers, and a plurality of second wiring layers each disposed within the plurality of second insulating layers. The plurality of via layers include a plurality of first via layers, each disposed within the plurality of first insulating layers and connected to one or more of the plurality of first wiring layers, and a plurality of second via layers, each disposed within the plurality of second insulating layers and connected to one or more of the plurality of second wiring layers. Of the plurality of first insulating layers, any two first insulating layers adjacent to each other in the stacking direction have a step difference between them in cross-section. Of the plurality of second insulating layers, any two second insulating layers adjacent to each other in the stacking direction have a step difference between them in cross-section. The printed circuit board according to claim 9, wherein one connected side surface of any two adjacent first insulating layers and one connected side surface of any two adjacent second insulating layers are arranged in the same direction.

14. The invention further includes a metal via that penetrates at least a portion of the space between the upper and lower surfaces of the glass layer, The printed circuit board according to claim 13, wherein the lowest of the plurality of first wiring layers and the uppermost of the plurality of second wiring layers are each connected to the metal via.

15. Each of the plurality of first via layers includes one or more tapered first connecting vias, the width of which is greater at the upper end than at the lower end in cross-section. The printed circuit board according to claim 13, wherein each of the plurality of second via layers includes one or more tapered second connecting vias, the width of which is greater at the lower end than at the upper end in cross-section.

16. The uppermost of the plurality of first insulating layers includes a first passivation layer having a plurality of first openings that expose at least a portion of the uppermost of the plurality of first wiring layers, The printed circuit board according to claim 13, wherein the lowest of the plurality of second insulating layers includes a second passivation layer having a plurality of second openings that expose at least a portion of the second wiring layer, which is located at the bottom of the plurality of second wiring layers.

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