Electronic circuits, drive circuits, and control systems

Abstract

The present invention provides an electronic circuit capable of generating a pulse train containing multiple pulses in response to an input pulse signal. [Solution] The electronic circuit of this embodiment includes a reference circuit that generates a reference pulse signal synchronized with a clock signal based on an input pulse signal, a delay circuit that generates a delayed pulse signal by delaying the reference pulse signal, and an output circuit that outputs a pulse train including a plurality of pulses synchronized with a clock signal based on the reference pulse signal, the delayed pulse signal, and the clock signal.

Claims

1. A first amplification circuit generates an amplified input pulse signal by expanding the pulse width of the input pulse signal in synchronization with the first edge of the input pulse signal, A first reference circuit that generates a reference pulse signal synchronized with a clock signal, having a rising edge corresponding to the rising edge of the augmented input pulse signal and a falling edge corresponding to the falling edge of the augmented input pulse signal, A delay circuit that delays the aforementioned reference pulse signal to generate a delayed pulse signal, An output circuit that outputs a pulse train including a plurality of pulses synchronized with the clock signal, based on the reference pulse signal, the delay pulse signal, and the clock signal. An electronic circuit equipped with the following features.

2. A reference circuit that generates a reference pulse signal synchronized with a clock signal, having a rising edge corresponding to the rising edge of the input pulse signal and a falling edge corresponding to the falling edge of the input pulse signal, A delay circuit that delays the aforementioned reference pulse signal to generate a delayed pulse signal, A combining circuit that generates a combined pulse signal that is on in intervals where only the reference pulse signal is on and intervals where only the delayed pulse signal is on, based on the reference pulse signal and the delayed pulse signal, An output circuit that outputs a pulse train including a plurality of pulses synchronized with the clock signal based on the combined pulse signal and the clock signal, An electronic circuit equipped with the following features.

3. The electronic circuit according to claim 1 or 2, wherein the delay time of the delay circuit is set in the range Tc*(M-1) < Td ≤ Tc*M, where Td is the delay time, Tc is the period of the clock signal, and M is the number of pulses included in the pulse train.

4. The output circuit includes a synthesis circuit that generates a composite pulse signal having a pulse width corresponding to the delay time of the delay circuit based on the reference pulse signal and the delayed pulse signal, A generation circuit that generates a pulse train including a plurality of pulses synchronized with the clock signal based on the combined pulse signal and the clock signal. The electronic circuit according to claim 1, including the following:

5. The system further comprises an inverting circuit that logically inverts the input pulse signal, The electronic circuit according to claim 1, wherein the first amplification circuit uses the logically inverted input pulse signal as the input pulse signal.

6. An inverting circuit that logically inverts the input pulse signal, A second amplification circuit generates an amplified inverted input pulse signal by expanding the pulse width of the logically inverted input pulse signal in synchronization with the first edge of the logically inverted input pulse signal, A second reference circuit that generates a reference pulse signal synchronized with a clock signal, having a rising edge corresponding to the rising edge of the expanded inverted input pulse signal and a falling edge corresponding to the falling edge of the expanded inverted input pulse signal, Furthermore, The delay circuit delays the reference pulse signal generated by the first reference circuit or the second reference circuit. The electronic circuit according to claim 1.

7. A reference circuit that generates a reference pulse signal synchronized with a clock signal, having a rising edge corresponding to the rising edge of the input pulse signal and a falling edge corresponding to the falling edge of the input pulse signal, A delay circuit that delays the aforementioned reference pulse signal to generate a delayed pulse signal, An output circuit that outputs a pulse train including a plurality of pulses synchronized with the clock signal, based on the reference pulse signal, the delayed pulse signal, and the clock signal, A storage circuit receives the pulse train generated by the output circuit and sequentially outputs waveform data in synchronization with each pulse included in the pulse train. A signal generation circuit generates a drive signal for a switching element based on the waveform data. A drive circuit equipped with the following features.

8. Multiple memory circuits, A first selection circuit that, based on a selection signal, selects and inputs the pulse train generated by the output circuit to one of the plurality of memory circuits, A second selection circuit inputs waveform data output from one of the plurality of memory circuits to the signal generation circuit based on the selection signal. The drive circuit according to claim 7, further comprising:

9. A reference circuit that generates a reference pulse signal synchronized with a clock signal, having a rising edge corresponding to the rising edge of the input pulse signal and a falling edge corresponding to the falling edge of the input pulse signal, A delay circuit that delays the aforementioned reference pulse signal to generate a delayed pulse signal, An output circuit that outputs a pulse train including a plurality of pulses synchronized with the clock signal, based on the reference pulse signal, the delayed pulse signal, and the clock signal, A plurality of storage circuits receive the pulse train generated by the output circuit and sequentially output waveform data in synchronization with each pulse included in the pulse train, A signal generation circuit that generates a drive signal for a switching element based on the waveform data, A first selection circuit that, based on a selection signal, selects and inputs the pulse train generated by the output circuit to one of the plurality of storage circuits, A second selection circuit inputs waveform data output from one of the plurality of memory circuits to the signal generation circuit based on the selection signal, A detection circuit for detecting the operating state of the switching element, A control circuit that generates the input pulse signal and the selection signal based on the operating state, A control system equipped with the following features.

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