Semiconductor device, display device, and method for manufacturing a semiconductor device.

Abstract

The present invention provides a semiconductor device, a method for manufacturing the same, and a display device, which maintain good contact between the semiconductor part and the second conductive part. [Solution] The semiconductor device 21 comprises a semiconductor portion 30D, a first insulating film F3, a first conductive portion 32 disposed so as not to overlap with the semiconductor portion, a second insulating film F8, second conductive portions 30B and 30C disposed in overlap with the semiconductor portion, and a third conductive portion 33 disposed in overlap with the first conductive portion 32. The first insulating film and the second insulating film are provided with first contact holes CH1 and CH2 disposed in overlap with both the semiconductor portion and the second conductive portion, and the second insulating film is provided with a second contact hole CH3 disposed in overlap with both the first and third conductive portions. The first conductive portion includes at least a first conductive layer 32B disposed on the first insulating film, a second conductive layer 32C disposed on the first conductive film, and a sacrificial layer 32D disposed on the second conductive film. The sacrificial layer is made of a semiconductor material or a conductive material and has a communication hole 32D1 that communicates with the second contact hole.

Description

【Technical Field】 【0001】 The technology disclosed in this specification relates to a semiconductor device, a display device, and a method for manufacturing a semiconductor device in which a good contact state between a semiconductor portion and a second conductive portion is maintained. 【Background Art】 【0002】 Conventionally, as an example of a semiconductor device, a display panel described in Patent Document 1 below is known. In the display panel described in Patent Document 1, by etching a certain amount of a protective layer in a first contact region and a second contact region of an active layer, a first via hole and a second via hole expose the surface of the active layer, and a source / drain metal layer is connected to the active layer through the first via hole and the second via hole. Since a hydrofluoric acid cleaning machine is not used for rinsing the protective layer, etching of the first capacitor electrode and the second capacitor electrode by hydrofluoric acid is effectively prevented. 【Prior Art Documents】 【Patent Documents】 【0003】 【Patent Document 1】 U.S. Patent Application Publication No. 2021 / 0335938 【Summary of the Invention】 【Problems to be Solved by the Invention】 【0004】 In the display panel described in Patent Document 1 mentioned above, the interiors of the first and second via holes are pre-cleaned using a pre-cleaning device that includes an ultraviolet exposure device and various cleaning units, and hydrofluoric acid cleaning using a hydrofluoric acid cleaning machine is not performed. In this case, of the first and second contact regions of the active layer, the portions exposed through the first and second via holes naturally form an oxide film over time, but the aforementioned pre-cleaning device cannot remove this oxide film. Therefore, there was a risk that the contact condition between the first and second contact regions and the source / drain metal layer would deteriorate due to the oxide film. 【0005】 The technology described herein was developed based on the circumstances described above, and aims to maintain good contact between the semiconductor part and the second conductive part. [Means for solving the problem] 【0006】 (1) A semiconductor device relating to the technology described herein comprises a semiconductor portion consisting of a part of a semiconductor film, a first insulating film disposed on the upper side of the semiconductor film, a first conductive portion disposed on the upper side of the first insulating film and disposed so as not to overlap with the semiconductor portion, a second insulating film disposed on the upper side of the first insulating film and the first conductive portion, a second conductive portion disposed on the upper side of the second insulating film and disposed in overlap with the semiconductor portion, and a third conductive portion disposed on the upper side of the second insulating film and disposed in overlap with the first conductive portion, wherein the first insulating film and the second insulating film contain the semiconductor portion and the second conductive portion A first contact hole is provided which is superimposed on both the electrical portion and the second insulating film. A second contact hole is provided which is superimposed on both the first conductive portion and the third conductive portion. The first conductive portion includes at least a first conductive layer which is a part of the first conductive film disposed on the upper side of the first insulating film, a second conductive layer which is a part of the second conductive film disposed on the upper side of the first conductive film, and a sacrificial layer which is a part of the sacrificial film disposed on the upper side of the second conductive film. The sacrificial layer is made of a semiconductor material or a conductive material and has a communication hole which communicates with the second contact hole. 【0007】 (2) In addition to (1) above, the semiconductor device may also have a sacrificial layer made of an oxide semiconductor material which is the semiconductor material. 【0008】 (3) In addition to (1) or (2) above, the semiconductor device may also have a sacrificial layer made of the transparent electrode material which is the conductive material. 【0009】 (4) In addition to any of (1) to (3) above, the semiconductor device may also have the first conductive layer containing aluminum and the second conductive layer containing molybdenum. 【0010】 (5) In addition to any of (1) to (4) above, the semiconductor device may have a sacrificial layer with a film thickness of 40 nm or less. 【0011】 (6) A display device relating to the technology described herein comprises a semiconductor device described in any of (1) to (5) above, and a counter substrate disposed opposite to the semiconductor device. 【0012】 (7) A method for manufacturing a semiconductor device relating to the technology described herein involves: forming a semiconductor film; patterning the formed semiconductor film to form a semiconductor portion; forming a first insulating film on the upper side of the semiconductor film; sequentially forming at least a first conductive film, a second conductive film, and a sacrificial film made of a semiconductor material or a conductive material on the upper side of the first insulating film; patterning the first conductive film, the second conductive film, and the sacrificial film to form a first conductive portion in a position that does not overlap with the semiconductor portion, starting from the lower layer, including at least a first conductive layer made of a part of the first conductive film, a second conductive layer made of a part of the second conductive film, and a sacrificial layer made of a part of the sacrificial film; forming a second insulating film on the upper side of the first insulating film and the first conductive portion; and patterning the second insulating film to form a part of a first contact hole and a first conductive film in a position that overlaps with the semiconductor portion. A second contact hole is provided at a position overlapping with the semiconductor portion, the remaining portion of the first contact hole is provided by patterning the first insulating film following the second insulating film, the portion of the semiconductor portion facing the first contact hole is cleaned by supplying a cleaning agent containing hydrofluoric acid to the inside of the first and second contact holes, a communication hole communicating with the second contact hole is provided in the sacrificial layer of the first conductive portion, a second conductive portion is provided on the upper side of the second insulating film at a position overlapping with the semiconductor portion, the second conductive portion is connected to the semiconductor portion through the first contact hole, a third conductive portion is provided on the upper side of the second insulating film at a position overlapping with the first conductive portion, and the third conductive portion is connected to the second conductive layer of the first conductive portion through the second contact hole and the communication hole. 【0013】 (8) In addition to (7) above, the method for manufacturing the semiconductor device may also involve forming the sacrificial film made of the oxide semiconductor material, which is the semiconductor material, and then performing an annealing treatment after providing the first conductive portion. [Effects of the Invention] 【0014】 According to the technology described herein, it is possible to maintain good contact between the semiconductor part and the second conductive part. [Brief explanation of the drawing] 【0015】 [Figure 1] Plan view of a liquid crystal panel, a driver, and a flexible substrate according to Embodiment 1 [Figure 2] Cross-sectional view of a liquid crystal panel, a driver, and a flexible substrate according to Embodiment 1 [Figure 3] Plan view showing the pixel arrangement of the liquid crystal panel according to Embodiment 1 [Figure 4] Plan view showing a part of the gate circuit section provided on the array substrate according to Embodiment 1 [Figure 5] Cross-sectional view taken along line v-v of FIG. 4 in the array substrate according to Embodiment 1 [Figure 6] Cross-sectional view similar to FIG. 5 showing the state where a base coat film is formed in the first step and a semiconductor film is formed in the second step included in the method for manufacturing an array substrate according to Embodiment 1 [Figure 7] Cross-sectional view similar to FIG. 5 showing the state where a first photoresist pattern is formed in the second step included in the method for manufacturing an array substrate according to Embodiment 1 [Figure 8] Cross-sectional view similar to FIG. 5 showing the state where a gate insulating film is formed in the third step and a gate formation film is formed in the fourth step included in the method for manufacturing an array substrate according to Embodiment 1 [Figure 9] Cross-sectional view similar to FIG. 5 showing the state where a second photoresist pattern is formed in the fourth step included in the method for manufacturing an array substrate according to Embodiment 1 [Figure 10] Cross-sectional view similar to FIG. 5 showing the state where the gate formation film is etched using the second photoresist pattern as a mask in the fourth step included in the method for manufacturing an array substrate according to Embodiment 1 [Figure 11] Cross-sectional view similar to FIG. 5 showing the state where an interlayer insulating film is formed in the sixth step after passing through the fifth step included in the method for manufacturing an array substrate according to Embodiment 1 [Figure 12] Cross-sectional view similar to FIG. 5 showing the state where a third photoresist pattern is formed in the sixth step included in the method for manufacturing an array substrate according to Embodiment Ⅰ [Figure 13]A cross-sectional view similar to FIG. 5 showing the state where an interlayer insulating film and a gate constituent film are etched using a third photoresist pattern as a mask in the sixth step included in the method for manufacturing an array substrate according to Embodiment 1 [Figure 14] A cross-sectional view similar to FIG. 5 showing the state where a cleaning liquid is supplied onto the interlayer insulating film and a communication hole is formed in the sacrificial layer in the seventh step included in the method for manufacturing an array substrate according to Embodiment 1 [Figure 15] A cross-sectional view similar to FIG. 5 showing the state where a fourth metal film is formed in the eighth step included in the method for manufacturing an array substrate according to Embodiment 1 [Figure 16] A cross-sectional view similar to FIG. 5 showing the state where a fourth photoresist pattern is formed in the eighth step included in the method for manufacturing an array substrate according to Embodiment 1 【Best Mode for Carrying Out the Invention】 【0016】 <Embodiment 1> Embodiment 1 will be described with reference to FIGS. 1 to 16. In this embodiment, a liquid crystal display device 10 will be exemplified. Note that the X-axis, Y-axis, and Z-axis are shown in part of each drawing, and the directions of the respective axes are drawn so as to be the directions shown in each drawing. Also, the upper side of FIGS. 2 and 5 to 16 is defined as the front side, and the lower side of the same figure is defined as the back side. 【0017】 As shown in FIG. 1, the liquid crystal display device 10 includes at least a horizontally long rectangular liquid crystal panel (display device, display panel) 11 capable of displaying an image, and a backlight device (lighting device) that irradiates the liquid crystal panel 11 with light for display. The backlight device is disposed on the back side (rear side) of the liquid crystal panel 11, and includes a light source (for example, an LED or the like) that emits white light, and an optical member that converts the light from the light source into planar light by imparting an optical action to the light. The central portion on the main surface of the liquid crystal panel 11 is a display region AA where an image is displayed. On the other hand, the frame-shaped outer peripheral portion surrounding the display region AA on the main surface of the liquid crystal panel 11 is a non-display region NAA where an image is not displayed. 【0018】 As shown in Figure 1, a gate circuit section 14 is provided in the non-display area NAA of the liquid crystal panel 11. A pair of gate circuit sections 14 are arranged so as to sandwich the display area AA from both sides in the X-axis direction. The gate circuit section 14 is provided in a strip-shaped area extending along the Y-axis direction. The gate circuit section 14 is for supplying scanning signals to the gate wiring 26, which will be described later, and is monolithically provided on the array substrate 21, which will be described later. The gate circuit section 14 is a GDM (Gate Driver Monolithic) circuit. The gate circuit section 14 includes a shift register circuit that outputs scanning signals at predetermined timings, a buffer circuit for amplifying scanning signals, and the like. 【0019】 The liquid crystal panel 11 will be described with reference to Figure 2 in addition to Figure 1. As shown in Figures 1 and 2, the liquid crystal panel 11 is formed by bonding a pair of substrates 20 and 21 together. Of the pair of substrates 20 and 21, the front side is the opposing substrate 20, and the back side is the array substrate (semiconductor device) 21. Both the opposing substrate 20 and the array substrate 21 are formed by laminating various films on the inner surface of a glass substrate. A liquid crystal layer 22 containing liquid crystal molecules, which are substances whose optical properties change when an electric field is applied, is interposed between the pair of substrates 20 and 21. A sealing portion 23 is provided between the outer edges of the pair of substrates 20 and 21 to seal the liquid crystal layer 22. The sealing portion 23 is formed in the shape of a rectangular frame surrounding the liquid crystal layer 22. Polarizing plates 15 are attached to the outer surfaces of both substrates 20 and 21. 【0020】 As shown in Figures 1 and 2, the opposing substrate 20 has a shorter short side dimension than the array substrate 21. The opposing substrate 20 is bonded to the array substrate 21 such that one end in the short side direction (Y-axis direction) is aligned with it. Therefore, the other end of the array substrate 21 in the short side direction is an exposed portion 21A that protrudes laterally from the opposing substrate 20. This exposed portion 21A is entirely a non-display area (NAA), and the driver 12 and flexible substrate 13 for supplying various signals are mounted on it. 【0021】 The driver 12 consists of an LSI chip with an internal drive circuit. The driver 12 is mounted on the exposed portion 21A of the array substrate 21 using COG (Chip On Glass) mounting. The driver 12 processes various signals transmitted by the flexible substrate 13. As shown in Figures 1 and 2, the driver 12 is positioned adjacent to one side of the display area AA in the Y-axis direction, sandwiched between the flexible substrate 13 and the display area AA. The driver 12 has a horizontally elongated rectangular shape in its planar form. The driver 12 can supply various signals to source wiring 27 and the like provided on the array substrate 21. The flexible substrate 13 is constructed by forming a large number of wiring patterns on a substrate made of a synthetic resin material (e.g., polyimide resin) that has insulating and flexible properties. One end of the flexible substrate 13 is connected to the exposed portion 21A of the array substrate 21, and the other end is connected to an external circuit board (control board, etc.). 【0022】 Next, the configuration of the display area AA on the array substrate 21 will be explained using Figure 3. On the inner surface of the display area AA on the array substrate 21, at least pixel TFTs (pixel transistors, pixel switching elements) 24 and pixel electrodes 25 are provided, as shown in Figure 3. Multiple pixel TFTs 24 and pixel electrodes 25 are arranged in a matrix (arrangement) with spacing along the X-axis and Y-axis directions. Around these pixel TFTs 24 and pixel electrodes 25, gate wiring (scanning wiring) 26 and source wiring (image wiring, signal wiring) 27 are arranged orthogonally (intersecting) with each other. Multiple gate wirings 26 extend along the X-axis direction, with spacing along the Y-axis direction. Multiple source wirings 27 extend along the Y-axis direction, with spacing along the X-axis direction. 【0023】 As shown in Figure 3, the pixel TFT 24 includes a pixel gate electrode 24A connected to the gate wiring 26, a pixel source electrode 24B connected to the source wiring 27, a pixel drain electrode 24C connected to the pixel electrode 25, and a pixel semiconductor section 24D made of semiconductor material connected to the source electrode 24B and the drain electrode 24C. The pixel TFT 24 is driven based on a scanning signal supplied to the pixel gate electrode 24A by the gate wiring 26. This scanning signal includes a potential higher than the threshold voltage of the pixel TFT 24. As a result, a channel region is created in the pixel semiconductor section 24D, allowing charge to move between the pixel source electrode 24B and the pixel drain electrode 24C through the channel region. Therefore, the potential related to the image signal (data signal) supplied to the pixel source electrode 24B by the source wiring 27 is supplied to the pixel drain electrode 24C via the pixel semiconductor section 24D. Consequently, the pixel electrode 25 is charged with the potential related to the image signal. The pixel electrode 25 is made of a transparent electrode material and has a planar shape, for example, a vertically elongated, approximately rectangular shape. The pixel electrode 25 is located in a region enclosed by two adjacent gate wirings 26 spaced apart in the Y-axis direction and two adjacent source wirings 27 spaced apart in the X-axis direction. 【0024】 Furthermore, in the display area AA of the opposing substrate 20, multiple color filters are provided at positions opposite to each pixel electrode 25 on the array substrate 21. The color filters consist of three colors, R (red), G (green), and B (blue), arranged repeatedly in a predetermined order, and together with the pixel electrodes 25, they constitute pixels of each color (red pixels, green pixels, and blue pixels). The three pixels of red, green, and blue constitute a display pixel capable of displaying a predetermined gradation of color. In the display area AA of the opposing substrate 20, a light-shielding portion (black matrix) is formed between each color filter to prevent color mixing. In addition, either the opposing substrate 20 or the array substrate 21 is provided with a common electrode made of the same transparent electrode material as the pixel electrodes 25, which is superimposed on the pixel electrodes 25 at a distance from them. In the liquid crystal panel 11, a predetermined electric field is applied to the liquid crystal layer 22 based on the potential difference generated between this common electrode and each pixel electrode 25, thereby enabling each pixel to display a predetermined gradation. Furthermore, on the innermost surface (uppermost layer) of both substrates 20 and 21 that is in contact with the liquid crystal layer 22, an alignment film (not shown) is formed to orient the liquid crystal molecules contained in the liquid crystal layer 22. 【0025】 Next, the configuration of the non-display area NAA in the array substrate 21 will be explained using Figures 4 and 5. The gate circuit section 14 provided in the non-display area NAA of the array substrate 21 is equipped with various circuit elements, including at least a non-pixel TFT (non-pixel transistor, non-pixel switching element) 30. Furthermore, the circuit elements of the gate circuit section 14 include at least a drive wiring (third conductive part) 33 for transmitting a drive signal to drive the non-pixel TFT 30, and a connection wiring 31 and a connection electrode (first conductive part) 32 for connecting the non-pixel TFT 30 and the drive wiring 33. 【0026】 The non-pixel TFT 30 is a so-called top-gate type. The pixel TFT 24 is also a top-gate type, similar to the non-pixel TFT 30. As shown in Figure 4, the non-pixel TFT 30 has a non-pixel gate electrode 30A, a non-pixel source electrode (second conductive part) 30B, a non-pixel drain electrode (second conductive part) 30C, and a non-pixel semiconductor part (semiconductor part) 30D. The non-pixel gate electrode 30A of the non-pixel TFT 30 extends along the Y-axis direction, and one end (lower side in Figure 4) is arranged superimposed on the non-pixel semiconductor part 30D. The other end (upper side in Figure 4) of the non-pixel gate electrode 30A is connected to a connection wiring 31, which will be described later. As will be described in detail later, a drive signal is supplied to the non-pixel gate electrode 30A from the drive wiring 33 via the connection wiring 31 and the connection electrode 32. The non-pixel source electrode 30B on the non-pixel TFT 30 is positioned at a distance from the non-pixel gate electrode 30A on one side in the X-axis direction (left side in Figure 4). The non-pixel source electrode 30B extends along the Y-axis direction, with one end (upper side in Figure 4) overlapping the non-pixel semiconductor portion 30D. The other end (lower side in Figure 4) of the non-pixel source electrode 30B is led out to the outside of the non-pixel semiconductor portion 30D and connected to wiring (not shown) provided in the gate circuit portion 14, and a predetermined signal is supplied from this wiring. 【0027】 As shown in Figure 4, the non-pixel drain electrode 30C on the non-pixel TFT 30 is positioned at a distance from the non-pixel gate electrode 30A in the X-axis direction, on the other side (right side in Figure 4). The non-pixel drain electrode 30C extends along the Y-axis direction, with one end (upper side in Figure 4) overlapping the non-pixel semiconductor portion 30D. The other end (lower side in Figure 4) of the non-pixel drain electrode 30C is led out to the outside of the non-pixel semiconductor portion 30D and connected to wiring (not shown) provided in the gate circuit portion 14, enabling the output of a signal from the non-pixel source electrode 30B to this wiring. The non-pixel semiconductor portion 30D constituting the non-pixel TFT 30 has a horizontally elongated rectangular shape when viewed in plan. The non-pixel gate electrode 30A is superimposed on the central part of the non-pixel semiconductor portion 30D in the X-axis direction. A non-pixel source electrode 30B is superimposed on one end portion of the non-pixel semiconductor portion 30D in the X-axis direction (left side in Figure 4). A non-pixel drain electrode 30C is superimposed on the other end portion of the non-pixel semiconductor portion 30D in the X-axis direction (right side in Figure 4). 【0028】 In the non-pixel TFT 30 with the above configuration, when a voltage above the threshold voltage is applied to the non-pixel gate electrode 30A, a channel region is created in the portion of the non-pixel semiconductor part 30D that overlaps with the non-pixel gate electrode 30A (the non-low-resistance region described later). This makes it possible for charge to move between the non-pixel source electrode 30B and the non-pixel drain electrode 30C through the channel region of the non-pixel semiconductor part 30D. As a result, the signal supplied to the non-pixel source electrode 30B can be transmitted to the non-pixel drain electrode 30C. 【0029】 Next, using Figure 5, the various films laminated on the glass substrate (substrate) 21GS of the array substrate 21 will be explained in detail. As shown in Figure 5, the glass substrate 21GS of the array substrate 21 has at least the following films laminated on it, in order from the bottom layer (glass substrate 21GS side): base coat film F1, semiconductor film F2, gate insulating film (first insulating film) F3, first metal film F4, second metal film (first conductive film) F5, third metal film (second conductive film) F6, sacrificial film F7, interlayer insulating film (second insulating film) F8, and fourth metal film F9. Of these, the semiconductor film F2 is shown in Figure 6, the first metal film F4, second metal film F5, third metal film F6, and sacrificial film F7 (gate constituent film FG, which will be described later) are shown in Figure 8, and the fourth metal film F9 is shown in Figure 15. In addition to the films described above, the glass substrate 21GS of the array substrate 21 also has transparent electrode films that constitute the pixel electrodes 25 and alignment films for aligning liquid crystal molecules formed on it. 【0030】 Each structure in the display area AA and non-display area NAA of the array substrate 21 is composed of one of these films F1 to F9 (including transparent electrode films and alignment films, etc.). Specifically, of the above-mentioned films F1 to F9, the first metal film F4, the second metal film F5, the third metal film F6, and the sacrificial film F7 constitute the gate wiring 26 and pixel gate electrodes 24A, etc., in the display area AA (see Figure 3). Hereinafter, the four-layer laminated film consisting of the first metal film F4, the second metal film F5, the third metal film F6, and the sacrificial film F7 will be referred to as the "gate constituent film" and its designation will be "FG". As shown in Figure 5, the gate constituent film FG constitutes the non-pixel gate electrode 30A, connection wiring 31, and connection electrode 32, etc., in the non-display area NAA. The first metal film F4 is a single-layer film made of one type of metal material, such as Mo (molybdenum). The thickness of the first metal film F4 is, for example, about 20 nm. By placing the first metal film F4, which is made of Mo, on the lower side of the second metal film F5, the adhesion of the gate constituent film FG to the gate insulating film F3, which is the substrate for the gate constituent film FG, is improved. 【0031】 The second metal film F5 is a single layer film made of one type of metal material, such as Al (aluminum). In this embodiment, since the material of the second metal film F5 is Al, the wiring resistance of the gate wiring 26 can be reduced compared to when Ta (tantalum) or W (tungsten) is used. The thickness of the second metal film F5 is greater than that of the first metal film F4, for example, 300 nm or more. This further reduces the wiring resistance of the gate wiring 26. The third metal film F6 is a single layer film made of one type of metal material, such as Mo. The third metal film F6 made of Mo has higher resistance to hydrofluoric acid than the second metal film F5 made of Al. The thickness of the third metal film F6 is smaller than that of the second metal film F5, for example, about 20 nm. The sacrificial film F7 is a single layer made of a semiconductor material or transparent electrode material, and is made of one of the following: an oxide semiconductor material such as an In-Ga-Zn-O system semiconductor material (e.g., indium gallium zinc oxide), an In-Sn-Zn-O system semiconductor material (e.g., indium tin zinc oxide), an In-Ga-O system semiconductor material (e.g., indium gallium oxide), or a transparent electrode material such as IZO (Indium Zinc Oxide). The sacrificial film F7 made of a semiconductor material or transparent electrode material has higher resistance to etching (especially dry etching) compared to the third metal film F6 made of Mo. On the other hand, the sacrificial film F7 made of a semiconductor material or transparent electrode material has lower resistance to hydrofluoric acid compared to the third metal film F6 made of Mo. The thickness of the sacrificial film F7 is, for example, 10 nm or more and 40 nm or less. 【0032】 In the display area AA, the fourth metal film F9 constitutes the source wiring 27, the pixel source electrode 24B, and the pixel drain electrode 24C, etc. (see Figure 3). Hereafter, the fourth metal film F9 will be referred to as the "source constituent film". As shown in Figure 5, in the non-display area NAA, the source constituent film (fourth metal film F9) constitutes the non-pixel source electrode 30B, the non-pixel drain electrode 30C, and the drive wiring 33, etc. 【0033】 The semiconductor film F2 constitutes the pixel semiconductor portion 24D, etc., in the display area AA (see Figure 3). As shown in Figure 5, the semiconductor film F2 constitutes the non-pixel semiconductor portion 30D, etc., in the non-display area NAA. The semiconductor film F2 is made of a crystalline polysilicon semiconductor material (semiconductor material) created by known methods such as laser crystallization. The thickness of the semiconductor film F2 is, for example, about 50 nm. The polysilicon semiconductor material of the semiconductor film F2 has higher electron mobility compared to amorphous silicon semiconductor materials and oxide semiconductor materials. The pixel semiconductor portion 24D and the non-pixel semiconductor portion 30D, which are composed of parts of the semiconductor film F2, are subjected to a low-resistance treatment (conductor treatment) during the manufacturing process of the array substrate 21, using the pixel gate electrode 24A and the non-pixel gate electrode 30A as masks, respectively. Through this low-resistance treatment, the portions of the pixel semiconductor portion 24D and the non-pixel semiconductor portion 30D that do not overlap with the pixel gate electrode 24A and the non-pixel gate electrode 30A are made low-resistance (conductive). The low-resistance treatment includes, for example, doping treatment using ionic species such as B (boron) and P (phosphorus), and annealing treatment. The non-pixel source electrode 30B and the non-pixel drain electrode 30C are connected to the low-resistance portion (low-resistance region) of the non-pixel semiconductor portion 30D. The pixel source electrode 24B and the pixel drain electrode 24C are connected to the low-resistance portion (low-resistance region) of the pixel semiconductor portion 24D (see Figure 3). The portion of the non-pixel semiconductor portion 30D that overlaps with the non-pixel gate electrode 30A (non-low-resistance region) is not made low-resistance, and charge movement is possible only under specific conditions (when a drive signal is supplied to the non-pixel gate electrode 30A). Similarly, the portion of the pixel semiconductor 24D that overlaps with the pixel gate electrode 24A (non-low-resistance region) is not made low-resistance, and charge movement is only possible under specific conditions (when a drive signal is supplied to the pixel gate electrode 24A). 【0034】 The base coat film F1, gate insulating film F3, and interlayer insulating film F8 are all types of inorganic materials (inorganic resin materials), such as SiO2 (silicon oxide, silicon oxide) and SiN xThe semiconductor film is a single-layer or multilayer film made of silicon nitride or the like. The base coat film F1 is the underlay for the semiconductor film F2 and can prevent impurities from the glass substrate 21GS constituting the array substrate 21 from diffusing into the semiconductor film F2. The gate insulating film F3 is interposed between the semiconductor film F2 and the gate constituent film FG (the bottommost first metal film F4) and keeps them in an insulating state. Specifically, as shown in Figure 5, the gate insulating film F3 keeps the non-pixel semiconductor portion 30D and the non-pixel gate electrode 30A in an insulating state in the non-display area NAA. The gate insulating film F3 keeps the pixel semiconductor portion 24D and the pixel gate electrode 24A in an insulating state in the display area AA (see Figure 3). The interlayer insulating film F8 is interposed between the gate constituent film (the topmost sacrificial film F7) FG and the source constituent film (the fourth metal film F9) and keeps them in an insulating state. Specifically, the interlayer insulating film F8 keeps the non-pixel gate electrode 30A in an insulated state from the non-pixel source electrode 30B and the non-pixel drain electrode 30C in the non-display region NAA. In the display region AA, the interlayer insulating film F8 keeps the pixel gate electrode 24A in an insulated state from the pixel source electrode 24B and the pixel drain electrode 24C (see Figure 3). 【0035】 In the non-display area NAA of the array substrate 21, non-pixel source contact holes (first contact holes) CH1 are provided in communication with the gate insulating film F3 and interlayer insulating film F8 at positions where they overlap with both the non-pixel source electrode 30B and the non-pixel semiconductor portion 30D, as shown in Figures 4 and 5. The non-pixel source electrode 30B is connected to one end portion (low-resistance region) of the non-pixel semiconductor portion 30D through the non-pixel source contact holes CH1 of the gate insulating film F3 and interlayer insulating film F8. Similarly, in the non-display area NAA of the array substrate 21, non-pixel drain contact holes (first contact holes) CH2 are provided in communication with the gate insulating film F3 and interlayer insulating film F8 at positions where they overlap with both the non-pixel drain electrode 30C and the non-pixel semiconductor portion 30D. The non-pixel drain electrode 30C is connected to the other end portion (low-resistance region) of the non-pixel semiconductor portion 30D through the non-pixel drain contact holes CH2 of the gate insulating film F3 and interlayer insulating film F8. In the display area AA of the array substrate 21, pixel source contact holes and pixel drain contact holes are provided in communication with each other at positions where the gate insulating film F3 and interlayer insulating film F8 overlap with both the pixel source electrode 24B and the pixel semiconductor portion 24D, and at positions where the pixel drain electrode 24C and the pixel semiconductor portion 24D overlap (see Figure 3). The pixel source electrode 24B is connected to one low-resistance region of the pixel semiconductor portion 24D through the pixel source contact holes of the gate insulating film F3 and interlayer insulating film F8, and the pixel drain electrode 24C is connected to the other low-resistance region of the pixel semiconductor portion 24D through the pixel drain contact holes of the gate insulating film F3 and interlayer insulating film F8. 【0036】 Next, the detailed configurations of the connection wiring 31, connection electrode 32, and drive wiring 33 will be described. As shown in Figure 4, the connection wiring 31 extends along the X-axis direction, and one end (the left side in Figure 4) is connected to the non-pixel gate electrode 30A. Similar to the non-pixel gate electrode 30A, the connection wiring 31 is made up of a part of the gate constituent film FG, and is connected to the gate constituent film FG by being directly connected to it. The other end (the right side in Figure 4) of the connection wiring 31 is connected to the connection electrode 32. The connection electrode 32 extends from the other end of the connection wiring 31 along the Y-axis direction toward the same side as the non-pixel gate electrode 30A (the lower side in Figure 4), and has a vertically elongated rectangular shape when viewed in plane. Similar to the connection wiring 31, the connection electrode 32 is made up of a part of the gate constituent film FG, and is connected to the connection wiring 31 by being directly connected to it. 【0037】 As shown in Figure 4, the drive wiring 33 extends along the X-axis direction, with one end (the left side in Figure 4) overlapping the connection electrode 32. The drive wiring 33 transmits a drive signal for driving the non-pixel TFT 30. The drive signal includes a potential higher than the threshold voltage of the non-pixel TFT 30. The drive wiring 33 is made up of a part of the fourth metal film F9 (source constituent film). Therefore, an interlayer insulating film F8 is interposed between the drive wiring 33 and the overlapping connection electrode 32. As shown in Figure 5, a drive wiring contact hole (second contact hole) CH3 is provided through the interlayer insulating film F8 interposed between the overlapping connection electrode 32 and the drive wiring 33 at a position that overlaps with both the connection electrode 32 and the drive wiring 33. One end of the drive wiring 33 is connected to the connection electrode 32 through the drive wiring contact hole CH3 of the interlayer insulating film F8. As a result, the drive wiring 33 is electrically connected to the non-pixel gate electrode 30A via the connection wiring 31 and the connection electrode 32, and is also capable of supplying a drive signal. 【0038】 As shown in Figure 5, the connecting electrode 32 is made up of a part of the gate constituent film FG and has a four-layer structure. Specifically, the connecting electrode 32 includes, in order from the bottom layer, a first metal layer 32A made up of a part of the first metal film F4, a second metal layer (first conductive layer) 32B made up of a part of the second metal film F5, a third metal layer (second conductive layer) 32C made up of a part of the third metal film F6, and a sacrificial layer 32D made up of a part of the sacrificial film F7. The sacrificial layer 32D, which is the uppermost layer of the connecting electrode 32, has a communication hole 32D1 that communicates with the drive wiring contact hole CH3 of the interlayer insulating film F8. Therefore, the drive wiring 33 is in contact with the third metal layer 32C of the connecting electrode 32 through the drive wiring contact hole CH3 of the interlayer insulating film F8 and the communication hole 32D1 of the sacrificial layer 32D. 【0039】 Thus, as shown in Figure 5, the connecting electrode 32 includes at least a first metal layer 32A, a second metal layer 32B, a third metal layer 32C, and a sacrificial layer 32D, in order from the bottom layer, of which the sacrificial layer 32D is made of a semiconductor material or a conductive material. The sacrificial layer 32D, made of a semiconductor material or a conductive material, is considered to have higher resistance to etching than the third metal layer 32C, which is made of Mo. Therefore, in the manufacturing process of the array substrate 21, when etching the gate insulating film F3 and the interlayer insulating film F8 to provide non-pixel source contact holes CH1 and non-pixel drain contact holes CH2, and etching the interlayer insulating film F8 to provide drive wiring contact holes CH3, the sacrificial layer 32D, which is located in the uppermost layer of the connecting electrode 32, is sacrificed, and the etching effect does not easily extend to the third metal layer 32C. In other words, it is possible to make it less likely for the first metal layer 32A, the second metal layer 32B, and the third metal layer 32C (especially the third metal layer 32C), which are located below the sacrificial layer 32D, to be over-etched. 【0040】 Incidentally, during the manufacturing process of the array substrate 21, if a cleaning agent containing, for example, hydrofluoric acid is supplied to the non-pixel source contact hole CH1 and non-pixel drain contact hole CH2 provided in the gate insulating film F3 and the interlayer insulating film F8, the surface of the non-pixel semiconductor portion 30D exposed through the non-pixel source contact hole CH1 and the non-pixel drain contact hole CH2 can be cleaned (see Figure 14). At this time, the cleaning agent is also supplied to the drive wiring contact hole CH3 provided in the interlayer insulating film F8. Here, the sacrificial layer 32D, which is made of a semiconductor material or a conductive material, has lower resistance to hydrofluoric acid than the third metal layer 32C made of Mo, so when the cleaning agent is supplied to the drive wiring contact hole CH3, the sacrificial layer 32D exposed through the drive wiring contact hole CH3 is more easily dissolved by the cleaning agent. Accordingly, the sacrificial layer 32D is provided with a high degree of certainty to communicate with the drive wiring contact hole CH3 through a communication hole 32D1. On the other hand, the third metal layer 32C, made of Mo, has higher resistance to hydrofluoric acid than the sacrificial layer 32D, making it less susceptible to erosion by cleaning agents and more likely to remain intact. As a result, the second metal layer 32B, made of Al, which has lower resistance to hydrofluoric acid than the third metal layer 32C, can be protected from the hydrofluoric acid contained in the cleaning agent by the third metal layer 32C, making the second metal layer 32B less susceptible to erosion by hydrofluoric acid. 【0041】 After non-pixel source contact holes CH1 and non-pixel drain contact holes CH2 are provided in the gate insulating film F3 and interlayer insulating film F8, and then non-pixel source electrodes 30B and non-pixel drain electrodes 30C are provided, as shown in Figure 5, the non-pixel source electrodes 30B and non-pixel drain electrodes 30C are connected to the portion of the non-pixel semiconductor portion 30D that is exposed through the non-pixel source contact holes CH1 and non-pixel drain contact holes CH2 and has been cleaned in advance. This ensures that good contact is maintained between the non-pixel semiconductor portion 30D and the second conductive portion, which consists of the non-pixel source electrodes 30B and non-pixel drain electrodes 30C. After drive wiring contact holes CH3 are provided in the interlayer insulating film F8, and then drive wiring 33 is provided, the drive wiring 33 is connected to the third metal layer 32C that is exposed through the drive wiring contact holes CH3 and communication holes 32D1 of the connecting electrodes 32. The second metal layer 32B included in the connecting electrode 32 is resistant to over-etching, and the third metal layer 32C included in the connecting electrode 32 is resistant to erosion by hydrofluoric acid, so that good contact between the connecting electrode 32 and the drive wiring 33 can be maintained. In this way, good contact between the non-pixel semiconductor portion 30D and the non-pixel source electrode 30B and non-pixel drain electrode 30C is maintained, and good contact between the connecting electrode 32 and the drive wiring 33 is maintained, resulting in good product reliability and yield in the liquid crystal panel 11. 【0042】 In this embodiment, the second metal layer 32B of the connecting electrode 32 is made of Al, which is suitable for increasing the conductivity of the connecting electrode 32. On the other hand, Al, which makes up the second metal layer 32B, has lower resistance to hydrofluoric acid contained in cleaning agents compared to Mo, and is easily dissolved by hydrofluoric acid. For this reason, when the drive wiring contact holes CH3 are provided in the interlayer insulating film F8 during the manufacturing process of the array substrate 21, if the third metal layer 32C is over-etched and the second metal layer 32B is exposed, the second metal layer 32B may be subsequently exposed to the cleaning agent and dissolved, potentially damaging the second metal layer 32B. However, when the drive wiring contact holes CH3 are provided in the interlayer insulating film F8 during the manufacturing process of the array substrate 21, the sacrificial layer 32D is sacrificed, making it difficult for the third metal layer 32C to be over-etched, thus avoiding exposure of the second metal layer 32B to cleaning agents containing hydrofluoric acid. Furthermore, Mo, which forms the third metal layer 32C, has higher resistance to hydrofluoric acid contained in the cleaning agent compared to Al, and is less likely to dissolve in hydrofluoric acid. Therefore, even if exposed to the cleaning agent through the communication holes 32D1 of the sacrificial layer 32D, the third metal layer 32C is less likely to be eroded. As a result, the conductivity of the connecting electrode 32 can be increased while maintaining good contact between the connecting electrode 32 and the drive wiring 33. 【0043】 In this embodiment, the sacrificial layer 32D has a thickness of 40 nm or less. If the thickness of the sacrificial layer 32D exceeds 40 nm, when a communication hole 32D1 is formed in the sacrificial layer 32D by the cleaning solution, the surface area of ​​the communication hole 32D1 becomes too large, causing excessive erosion of the sacrificial layer 32D by the cleaning solution, and making it easier for the communication hole 32D1 to form over a wider area than the drive wiring contact hole CH3. In this respect, by setting the thickness of the sacrificial layer 32D to 40 nm or less, the surface area of ​​the communication hole 32D1 becomes sufficiently small, making it difficult for the sacrificial layer 32D to be excessively eroded by the cleaning solution, and making it less likely for the communication hole 32D1 to become wider than the drive wiring contact hole CH3. As a result, the contact state between the drive wiring 33 connected through the drive wiring contact hole CH3 and the communication hole 32D1 and the third metal layer 32C can be maintained more favorably. 【0044】 Furthermore, as shown in Figure 5, the non-pixel gate electrode 30A, like the connecting electrode 32 described above, is made of a part of the gate constituent film FG and has a four-layer structure. Specifically, the non-pixel gate electrode 30A includes, in order from the bottom layer, a first layer 30A1 made of a part of the first metal film F4, a second layer 30A2 made of a part of the second metal film F5, a third layer 30A3 made of a part of the third metal film F6, and a fourth layer 30A4 made of a part of the sacrificial film F7. The fourth layer 30A4 differs from the sacrificial layer 32D in that it does not have a communication hole 32D1. 【0045】 The liquid crystal panel 11 according to this embodiment has the structure described above, and its manufacturing method will now be explained. The manufacturing method for the liquid crystal panel 11 includes a counter substrate manufacturing process for manufacturing the counter substrate 20, an array substrate manufacturing process (semiconductor device manufacturing process) for manufacturing the array substrate 21, and a bonding process for bonding the manufactured counter substrate 20 and the array substrate 21 together. The array substrate manufacturing process will be described below. 【0046】 The array substrate manufacturing process includes at least the following steps: a first step (base coat film deposition step) for depositing a base coat film F1; a second step (semiconductor film patterning step) for depositing a semiconductor film F2, performing laser crystallization treatment, and then patterning it; a third step (gate insulating film deposition step) for depositing a gate insulating film F3; a fourth step (gate constituent film patterning step) for depositing and patterning a gate constituent film FG; a fifth step (resistance reduction step, annealing step) for selectively reducing the resistance of the semiconductor film F2 structure; a sixth step (insulating film patterning step) for depositing an interlayer insulating film F8 and patterning the gate insulating film F3 and the interlayer insulating film F8; a seventh step (cleaning step) for cleaning the semiconductor film F2 structure with a cleaning solution; and an eighth step (second metal film patterning step) for depositing and patterning a fourth metal film F9. 【0047】 The term "patterning" used above refers to the processing of a film based on a general photolithography method. Specifically, a photoresist film is deposited on the film to be processed, the photoresist film is exposed using an exposure device through a photomask having a predetermined aperture pattern, the photoresist film is developed, and etching is performed through the developed photoresist film to process the film, i.e., pattern the film. 【0048】 In the first step, a base coat film F1 is deposited on the glass substrate 21GS of the array substrate 21, as shown in Figure 6. In the next second step, a semiconductor film F2 is deposited on the upper layer side of the base coat film F1. The deposited semiconductor film F2 is subjected to laser crystallization treatment, causing the semiconductor film F2 to become polycrystalline. Subsequently, a first photoresist film is deposited on the upper layer side of the semiconductor film F2, and the first photoresist film is exposed using an exposure apparatus and a first photomask (not shown, along with the exposure apparatus) having a predetermined aperture pattern, and then developed. As a result, as shown in Figure 7, a first photoresist pattern PR1, which is a transfer of the aperture pattern of the first photomask, remains on the semiconductor film F2. The semiconductor film F2 is etched (dry etching or wet etching) using the remaining first photoresist pattern PR1 as a mask. As a result, in the non-pixel area NAA, a non-pixel semiconductor area 30D is provided that is located in the area overlapping with the first photoresist pattern PR1 (see Figure 8). In the display area AA, a pixel semiconductor section 24D is provided (see Figure 3). After etching of the semiconductor film F2 is complete, the first photoresist pattern PR1 is removed with a stripping solution. 【0049】 In the third step, as shown in Figure 8, a gate insulating film F3 is deposited on the upper side of the semiconductor film F2. In the next fourth step, a gate constituent film FG is deposited on the upper side of the gate insulating film F3. Specifically, a first metal film F4, a second metal film F5, a third metal film F6, and a sacrificial film F7 are deposited on the upper side of the gate insulating film F3 in that order. Subsequently, a second photoresist film is deposited on the upper side of the sacrificial film F7, and the second photoresist film is exposed using an exposure apparatus and a second photomask (not shown along with the exposure apparatus) having a predetermined aperture pattern, and then developed. As a result, as shown in Figure 9, a second photoresist pattern PR2, which is a transfer of the aperture pattern of the second photomask, remains on the sacrificial film F7. The gate constituent film FG is wet-etched using the remaining second photoresist pattern PR2 as a mask. Then, in the non-display area NAA, as shown in Figure 10, a non-pixel gate electrode 30A, connecting wiring 31 (see Figure 4), and connecting electrode 32 are provided in the area overlapping with the second photoresist pattern PR2. The connecting electrode 32 includes, in order from the bottom layer, a first metal layer 32A made of a part of the first metal film F4, a second metal layer 32B made of a part of the second metal film F5, a third metal layer 32C made of a part of the third metal film F6, and a sacrificial layer 32D made of a part of the sacrificial film F7. In the display area AA, a pixel gate electrode 24A is provided (see Figure 3). After the wet etching of the gate constituent film FG is completed, the second photoresist pattern PR2 is removed with a stripping solution. 【0050】 In the fifth step, a structure made of a gate constituent film FG is used as a mask to selectively reduce the resistance of a structure made of a semiconductor film F2. The resistance reduction treatment includes, for example, doping treatment using ionic species such as B and P, and annealing treatment. Specifically, in the non-display region NAA, the portion of the non-pixel semiconductor part 30D that does not overlap with the non-pixel gate electrode 30A is selectively reduced in resistance. In the display region AA, the portion of the pixel semiconductor part 24D that does not overlap with the pixel gate electrode 24A is selectively reduced in resistance (see Figure 3). At this time, if a semiconductor material is used as the material for the sacrificial film F7, both the sacrificial layer 32D included in the connecting electrode 32 and the fourth layer 30A4 included in the non-pixel gate electrode 30A are reduced in resistance over their entire areas. 【0051】 In the sixth step, as shown in Figure 11, an interlayer insulating film F8 is deposited on the upper side of the gate constituent film FG. Subsequently, a third photoresist film is deposited on the upper side of the interlayer insulating film F8, and the third photoresist film is exposed using an exposure apparatus and a third photomask (not shown, along with the exposure apparatus) having a predetermined aperture pattern, and then developed. As a result, as shown in Figure 12, a third photoresist pattern PR3, which is a transfer of the aperture pattern of the third photomask, remains on the interlayer insulating film F8. The interlayer insulating film F8 is dry-etched using the remaining third photoresist pattern PR3 as a mask. As a result, in the non-display area NAA, as shown in Figure 13, a part of the non-pixel source contact hole CH1, a part of the non-pixel drain contact hole CH2, and a drive wiring contact hole CH3 are provided in the interlayer insulating film F8 in the area that overlaps with the aperture portion of the third photoresist pattern PR3. As dry etching continues, in the non-display area NAA, the remaining portion of the non-pixel source contact hole CH1 and the remaining portion of the non-pixel drain contact hole CH2 are formed in the gate insulating film F3 in the area overlapping with the opening of the third photoresist pattern PR3. While this gate insulating film F3 is dry-etched, the connecting electrode 32 exposed through the drive wiring contact hole CH3 of the interlayer insulating film F8 is also dry-etched. However, the uppermost layer of the connecting electrode 32 has a sacrificial layer 32D with excellent resistance to dry etching, so even if the sacrificial layer 32D is slightly reduced by dry etching, it is unlikely to burn out. In particular, in this embodiment, the thickness of the sacrificial layer 32D is set to 10 nm or more, so it is even less likely that the sacrificial layer 32D will burn out due to dry etching. In this way, the sacrificial layer 32D is sacrificed, making it less likely that the third metal layer 32C and the second metal layer 32B, which have low resistance to dry etching, will be over-etched. In the display area AA, at least pixel source contact holes and pixel drain contact holes are provided. After the dry etching of the interlayer insulating film F8 and the gate insulating film F3 is completed, the third photoresist pattern PR3 is removed with a stripping solution. 【0052】 In the seventh step, a cleaning device supplies a cleaning agent containing hydrofluoric acid onto the interlayer insulating film F8. The cleaning agent then penetrates into the non-pixel source contact hole CH1, the non-pixel drain contact hole CH2, and the drive wiring contact hole CH3, respectively. Inside the non-pixel source contact hole CH1 and the non-pixel drain contact hole CH2, the portion of the non-pixel semiconductor part 30D facing the non-pixel source contact hole CH1 and the non-pixel drain contact hole CH2 is cleaned by the cleaning agent, improving its surface condition. Inside the drive wiring contact hole CH3, the portion of the sacrificial layer 32D of the connecting electrode 32 facing the drive wiring contact hole CH3 is exposed to the hydrofluoric acid contained in the cleaning agent and dissolves. As a result, a communication hole 32D1 communicating with the drive wiring contact hole CH3 is provided in the sacrificial layer 32D. At this time, the third metal layer 32C, made of Mo which has high resistance to hydrofluoric acid, remains on the lower side of the sacrificial layer 32D without being over-etched in the sixth step. Therefore, even if exposed to hydrofluoric acid through the communication hole 32D1, it is unlikely that the third metal layer 32C will be eroded. Consequently, the second metal layer 32B, which is located on the lower side of the third metal layer 32C and is made of Al which has low resistance to hydrofluoric acid, can be protected from the hydrofluoric acid contained in the cleaning agent. This prevents the second metal layer 32B from being exposed to hydrofluoric acid and makes it unlikely that the second metal layer 32B will be eroded by hydrofluoric acid. 【0053】 In particular, in this embodiment, the thickness of the sacrificial film F7 is set to 40 nm or less. If the thickness of the sacrificial layer 32D exceeds 40 nm, when a communication hole 32D1 is formed in the sacrificial layer 32D by hydrofluoric acid contained in the cleaning solution, the surface area of ​​the communication hole 32D1 becomes too large. As a result, the erosion of the sacrificial layer 32D by the hydrofluoric acid contained in the cleaning solution progresses excessively, and the communication hole 32D1 is more likely to be formed over a wider area than the drive wiring contact hole CH3. In this respect, by setting the thickness of the sacrificial layer 32D to 40 nm or less, the surface area of ​​the communication hole 32D1 becomes sufficiently small, so the erosion of the sacrificial layer 32D by hydrofluoric acid contained in the cleaning solution becomes less likely to occur excessively, and the situation in which the communication hole 32D1 becomes wider than the drive wiring contact hole CH3 becomes less likely. 【0054】 In the eighth step, as shown in Figure 15, a fourth metal film F9 is deposited on the upper side of the interlayer insulating film F8. Subsequently, a fourth photoresist film is deposited on the upper side of the fourth metal film F9, and the fourth photoresist film is exposed using an exposure apparatus and a fourth photomask (not shown, along with the exposure apparatus) having a predetermined aperture pattern, and then developed. As a result, as shown in Figure 16, a fourth photoresist pattern PR4, which is a transfer of the aperture pattern of the fourth photomask, remains on the fourth metal film F9. The fourth metal film F9 is etched (dry etching or wet etching) using the remaining fourth photoresist pattern PR4 as a mask. As a result, in the non-display area NAA, a non-pixel source electrode 30B, a non-pixel drain electrode 30C, and a drive wiring 33 are provided in the area overlapping with the fourth photoresist pattern PR4 (see Figure 5). In the display area AA, a pixel source electrode 24B and a pixel drain electrode 24C are provided (see Figure 3). After etching of the fourth metal film F9 is complete, the fourth photoresist pattern PR4 is removed with a stripping solution. 【0055】 The non-pixel source electrode 30B and non-pixel drain electrode 30C, provided in step 8, are connected to the non-pixel semiconductor portion 30D through the non-pixel source contact hole CH1 and non-pixel drain contact hole CH2 of the interlayer insulating film F8. The portion of the non-pixel semiconductor portion 30D that contacts the non-pixel source electrode 30B and non-pixel drain electrode 30C has its surface condition improved by being pre-cleaned with a cleaning solution in step 7, resulting in good contact with the non-pixel source electrode 30B and non-pixel drain electrode 30C. The drive wiring 33, provided in step 8, is connected to the third metal layer 32C of the connecting electrode 32 through the drive wiring contact hole CH3 of the interlayer insulating film F8 and the communication hole 32D1 of the sacrificial layer 32D of the connecting electrode 32. The third metal layer 32C in the connecting electrode 32, which is in direct contact with the drive wiring 33, is protected by the sacrificial layer 32D in the sixth step, making it less susceptible to over-etching, and is also less susceptible to erosion by hydrofluoric acid contained in the cleaning agent in the seventh step, thus ensuring good contact with the drive wiring 33. The second metal layer 32B, located below the third metal layer 32C in the connecting electrode 32, is protected by the sacrificial layer 32D in the sixth step, making it less susceptible to over-etching, and is also prevented from being directly exposed to hydrofluoric acid contained in the cleaning agent in the seventh step, thus reducing the likelihood of erosion by hydrofluoric acid. As a result, good contact between the connecting electrode 32 and the drive wiring 33 can be maintained. 【0056】 Furthermore, by setting the thickness of the sacrificial film F7 to 40 nm or less, excessive erosion of the sacrificial layer 32D by hydrofluoric acid contained in the cleaning solution in the seventh step is less likely to occur, and the situation in which the communication hole 32D1 becomes wider than the drive wiring contact hole CH3 is less likely to occur. As a result, the contact state between the drive wiring 33, which is connected through the drive wiring contact hole CH3 and the communication hole 32D1, and the third metal layer 32C can be maintained more favorably. 【0057】 Furthermore, in this embodiment, since the sacrificial layer 32D included in the connecting electrode 32 is made conductive by the low-resistance treatment in the fifth step, even if the communication hole 32D1 is provided in a way that does not penetrate the sacrificial layer 32D when cleaning with a cleaning agent is performed in the seventh step, the drive wiring 33 can be made electrically connected to the third metal layer 32C via the conductive sacrificial layer 32D. This improves the reliability of the connection between the connecting electrode 32 and the drive wiring 33. 【0058】 As described above, the array substrate (semiconductor device) 21 of this embodiment comprises a non-pixel semiconductor portion (semiconductor portion) 30D made up of a part of the semiconductor film F2, a gate insulating film (first insulating film) F3 disposed on the upper side of the semiconductor film F2, a connecting electrode (first conductive portion) 32 disposed on the upper side of the gate insulating film F3 and disposed so as not to overlap with the non-pixel semiconductor portion 30D, an interlayer insulating film (second insulating film) F8 disposed on the upper side of the gate insulating film F3 and the connecting electrode 32, a second conductive portion consisting of a non-pixel source electrode 30B and a non-pixel drain electrode 30C disposed on the upper side of the interlayer insulating film F8 and superimposed on the non-pixel semiconductor portion 30D, and a drive wiring (third conductive portion) 33 disposed on the upper side of the interlayer insulating film F8 and superimposed on the connecting electrode 32. The gate insulating film F3 and the interlayer insulating film F8 comprise the non-pixel semiconductor portion 30D and the second conductive portion consisting of the non-pixel source electrode 30B and the non-pixel The first contact holes, non-pixel source contact hole CH1 and non-pixel drain contact hole CH2, are provided superimposed on both of the primary drain electrodes 30C. The interlayer insulating film F8 is provided with a drive wiring contact hole (second contact hole) CH3 superimposed on both the connecting electrode 32 and the drive wiring 33. The connecting electrode 32 includes at least a second metal layer (first conductive layer) 32B made up of a part of a second metal film (first conductive film) F5 disposed on the upper side of the gate insulating film F3, a third metal layer (second conductive layer) 32C made up of a part of a third metal film (second conductive film) F6 disposed on the upper side of the second metal film F5, and a sacrificial layer 32D made up of a part of a sacrificial film F7 disposed on the upper side of the third metal film F6. The sacrificial layer 32D is made of a semiconductor material or a conductive material and has a communication hole 32D1 that communicates with the drive wiring contact hole CH3. 【0059】 The non-pixel semiconductor portion 30D is connected to the second conductive portion, the non-pixel source electrode 30B and the non-pixel drain electrode 30C, through the first contact holes, the non-pixel source contact hole CH1 and the non-pixel drain contact hole CH2, which are provided in the gate insulating film F3 and the interlayer insulating film F8, respectively. The connecting electrode 32 is connected to the driving wiring 33 through the driving wiring contact hole CH3 provided in the interlayer insulating film F8. Here, the connecting electrode 32 includes at least a second metal layer 32B, a third metal layer 32C and a sacrificial layer 32D in order from the bottom layer, of which the sacrificial layer 32D is made of a semiconductor material or a conductive material. Therefore, when etching the gate insulating film F3 and the interlayer insulating film F8 during the manufacturing process to create the first contact holes, namely the non-pixel source contact hole CH1 and the non-pixel drain contact hole CH2, and etching the interlayer insulating film F8 to create the drive wiring contact hole CH3, the sacrificial layer 32D, which is the uppermost layer of the connecting electrode 32, is sacrificed, making it less likely that the second metal layer 32B and the third metal layer 32C will be over-etched. 【0060】 Incidentally, if a cleaning agent containing, for example, hydrofluoric acid is supplied to the first contact holes, non-pixel source contact hole CH1 and non-pixel drain contact hole CH2, which are provided in the gate insulating film F3 and interlayer insulating film F8 during the manufacturing process, the surface of the non-pixel semiconductor portion 30D exposed through the first contact holes, non-pixel source contact hole CH1 and non-pixel drain contact hole CH2, can be cleaned. At this time, if the cleaning agent is supplied to the drive wiring contact hole CH3 provided in the interlayer insulating film F8, the sacrificial layer 32D exposed through the drive wiring contact hole CH3 dissolves into the cleaning agent, and a communication hole 32D1 communicating with the drive wiring contact hole CH3 is provided in the sacrificial layer 32D. Since the third metal layer 32C remains on the lower side of the sacrificial layer 32D, the second metal layer 32B can be protected from the hydrofluoric acid contained in the cleaning agent, and the second metal layer 32B becomes less susceptible to erosion by hydrofluoric acid. After the gate insulating film F3 and the interlayer insulating film F8 are provided with first contact holes, namely the non-pixel source contact hole CH1 and the non-pixel drain contact hole CH2, and then the second conductive parts, namely the non-pixel source electrode 30B and the non-pixel drain electrode 30C, are provided, the second conductive parts, namely the non-pixel source electrode 30B and the non-pixel drain electrode 30C, are connected to the portion of the non-pixel semiconductor part 30D that is exposed through the first contact holes, namely the non-pixel source contact hole CH1 and the non-pixel drain contact hole CH2 and has been cleaned in advance. This ensures that good contact is maintained between the non-pixel semiconductor part 30D and the second conductive parts, namely the non-pixel source electrode 30B and the non-pixel drain electrode 30C. After the interlayer insulating film F8 is provided with the drive wiring contact hole CH3 and then the drive wiring 33 is provided, the drive wiring 33 is connected to the third metal layer 32C that is exposed through the drive wiring contact hole CH3 and the communication hole 32D1 of the connecting electrode 32. The second metal layer 32B contained in the connecting electrode 32 is less susceptible to over-etching, and the third metal layer 32C contained in the connecting electrode 32 is less susceptible to erosion by hydrofluoric acid, thereby maintaining good contact between the connecting electrode 32 and the drive wiring 33. 【0061】 Furthermore, the sacrificial layer 32D is made of an oxide semiconductor material, which is a semiconductor material. During the manufacturing process, when the interlayer insulating film F8 is etched to create the drive wiring contact holes CH3, the sacrificial layer 32D made of oxide semiconductor material is difficult to etch, thus making it less likely for the second metal layer 32B and the third metal layer 32C to be over-etched. On the other hand, when a cleaning agent containing hydrofluoric acid is supplied to the drive wiring contact holes CH3 provided in the interlayer insulating film F8, the sacrificial layer 32D made of oxide semiconductor material is easily dissolved by the hydrofluoric acid, so it is easier to provide a communication hole 32D1 in the sacrificial layer 32D that communicates with the drive wiring contact holes CH3. This increases the certainty that the third metal layer 32C is exposed through the communication hole 32D1 in the sacrificial layer 32D. 【0062】 Furthermore, the sacrificial layer 32D is made of a transparent electrode material, which is a conductive material. During the manufacturing process, when the interlayer insulating film F8 is etched to create the drive wiring contact hole CH3, the sacrificial layer 32D, which is made of the transparent electrode material, is difficult to etch, thus making it less likely for the second metal layer 32B and the third metal layer 32C to be over-etched. On the other hand, when a cleaning agent containing hydrofluoric acid is supplied to the drive wiring contact hole CH3 provided in the interlayer insulating film F8, the sacrificial layer 32D, which is made of the transparent electrode material, is easily dissolved by the hydrofluoric acid, so it is easier to provide a communication hole 32D1 in the sacrificial layer 32D that communicates with the drive wiring contact hole CH3. This increases the certainty that the third metal layer 32C is exposed through the communication hole 32D1 in the sacrificial layer 32D. 【0063】 Furthermore, the second metal layer 32B contains aluminum, and the third metal layer 32C contains molybdenum. Aluminum has lower sheet resistance compared to tantalum and tungsten. Therefore, having the second metal layer 32B of the connecting electrode 32 made of aluminum is preferable for increasing the conductivity of the connecting electrode 32. On the other hand, aluminum has lower resistance to hydrofluoric acid contained in cleaning agents compared to molybdenum and is more easily dissolved by hydrofluoric acid. For this reason, when the drive wiring contact hole CH3 is provided in the interlayer insulating film F8 during the manufacturing process, if the third metal layer 32C is over-etched and the second metal layer 32B is exposed, the second metal layer 32B may be damaged by subsequent exposure to the cleaning agent and dissolution. In this respect, when the drive wiring contact holes CH3 are provided in the interlayer insulating film F8 during the manufacturing process, the sacrificial layer 32D is sacrificed, making it difficult for the third metal layer 32C to be over-etched, thus avoiding exposure of the second metal layer 32B to cleaning agents containing hydrofluoric acid. Furthermore, molybdenum, which makes up the third metal layer 32C, has higher resistance to hydrofluoric acid contained in cleaning agents compared to aluminum, and is less likely to dissolve in hydrofluoric acid. Therefore, even if exposed to cleaning agents through the communication holes 32D1 of the sacrificial layer 32D, it is less likely that the third metal layer 32C will be eroded. As a result, the conductivity of the connecting electrode 32 can be increased while maintaining good contact between the connecting electrode 32 and the drive wiring 33. 【0064】 Furthermore, the sacrificial layer 32D has a film thickness of 40 nm or less. If the film thickness of the sacrificial layer 32D exceeds 40 nm, when a communication hole 32D1 is formed in the sacrificial layer 32D by the cleaning solution, the surface area of ​​the communication hole 32D1 becomes too large, causing excessive erosion of the sacrificial layer 32D by the cleaning solution, and making it easier for the communication hole 32D1 to form over a wider area than the drive wiring contact hole CH3. In this respect, by setting the film thickness of the sacrificial layer 32D to 40 nm or less, the surface area of ​​the communication hole 32D1 becomes sufficiently small, making it difficult for excessive erosion of the sacrificial layer 32D by the cleaning solution to occur, and making it less likely for the communication hole 32D1 to become wider than the drive wiring contact hole CH3. As a result, the contact state between the drive wiring 33, which is connected through the drive wiring contact hole CH3 and the communication hole 32D1, and the third metal layer 32C can be maintained in a better condition. 【0065】 The liquid crystal panel (display device) 11 according to this embodiment comprises the array substrate 21 and a counter substrate 20 arranged opposite the array substrate 21. With such a liquid crystal panel 11, good contact is maintained between the non-pixel semiconductor portion 30D and the second conductive portion, which is the non-pixel source electrode 30B and the non-pixel drain electrode 30C, and good contact is maintained between the connecting electrode 32 and the drive wiring 33, resulting in good product reliability and yield. 【0066】 The manufacturing method of the array substrate 21 according to this embodiment involves forming a semiconductor film F2, patterning the formed semiconductor film F2 to provide a non-pixel semiconductor portion 30D, forming a gate insulating film F3 on the upper side of the semiconductor film F2, sequentially forming at least a second metal film F5, a third metal film F6, and a sacrificial film F7 made of a semiconductor material or conductive material on the upper side of the gate insulating film F3, and patterning the second metal film F5, the third metal film F6, and the sacrificial film F7 so that a second metal layer 32B, which is a part of the second metal film F5, and a third metal film F7 are formed in order from the lower side at a position that does not overlap with the non-pixel semiconductor portion 30D. A connecting electrode 32 is provided, which includes at least a third metal layer 32C consisting of a part of the base film F6 and a sacrificial layer 32D consisting of a part of the sacrificial film F7. An interlayer insulating film F8 is deposited on the upper side of the gate insulating film F3 and the connecting electrode 32, and the interlayer insulating film F8 is patterned to provide a first contact hole, which is a non-pixel source contact hole CH1 and a part of the non-pixel drain contact hole CH2, at a position overlapping with the non-pixel semiconductor portion 30D, and a drive wiring contact hole CH3 at a position overlapping with the connecting electrode 32. Following the interlayer insulating film F8, the gate insulating film F3 is patterned. By doing so, the remaining portions of the first contact holes, which are the non-pixel source contact hole CH1 and the non-pixel drain contact hole CH2, are provided, and a cleaning agent containing hydrofluoric acid is supplied to the inside of the first contact holes, which are the non-pixel source contact hole CH1 and the non-pixel drain contact hole CH2 and the drive wiring contact hole CH3, thereby cleaning the portion of the non-pixel semiconductor section 30D that faces the first contact holes, which are the non-pixel source contact hole CH1 and the non-pixel drain contact hole CH2, and also the connecting electrode 32 A communication hole 32D1 is provided in the sacrificial layer 32D that communicates with the drive wiring contact hole CH3, a second conductive part, a non-pixel source electrode 30B and a non-pixel drain electrode 30C, is provided on the upper side of the interlayer insulating film F8 at a position overlapping with the non-pixel semiconductor part 30D, the second conductive part, the non-pixel source electrode 30B and the non-pixel drain electrode 30C are connected to the non-pixel semiconductor part 30D through the first contact hole, the non-pixel source contact hole CH1 and the non-pixel drain contact hole CH2, and a drive wiring 33 is provided on the upper side of the interlayer insulating film F8 at a position overlapping with the connecting electrode 32.The drive wiring 33 is connected to the third metal layer 32C of the connecting electrode 32 through the drive wiring contact hole CH3 and the communication hole 32D1. 【0067】 When etching the interlayer insulating film F8 to form the first contact holes, which are a portion of the non-pixel source contact hole CH1 and the non-pixel drain contact hole CH2, and the drive wiring contact hole CH3, and etching the gate insulating film F3 to form the remaining portions of the first contact holes, which are the non-pixel source contact hole CH1 and the non-pixel drain contact hole CH2, the sacrificial layer 32D, which is located in the uppermost layer of the connecting electrode 32, is sacrificed, making it less likely that the second metal layer 32B and the third metal layer 32C will be over-etched. When a cleaning agent containing hydrofluoric acid is supplied to the first contact holes of the gate insulating film F3 and the interlayer insulating film F8, namely the non-pixel source contact hole CH1 and the non-pixel drain contact hole CH2, and to the drive wiring contact hole CH3 of the interlayer insulating film F8, the surface of the non-pixel semiconductor portion 30D exposed through the first contact holes, namely the non-pixel source contact hole CH1 and the non-pixel drain contact hole CH2, is cleaned, and the sacrificial layer 32D exposed through the drive wiring contact hole CH3 dissolves into the cleaning agent, creating a communication hole 32D1 in the sacrificial layer 32D that communicates with the drive wiring contact hole CH3. At this time, since the third metal layer 32C remains on the lower side of the sacrificial layer 32D, the second metal layer 32B can be protected from the hydrofluoric acid contained in the cleaning agent, making it difficult for the second metal layer 32B to be eroded by hydrofluoric acid. When the second conductive part, the non-pixel source electrode 30B and the non-pixel drain electrode 30C, are provided, the second conductive part, the non-pixel source electrode 30B and the non-pixel drain electrode 30C, are connected to the portion of the non-pixel semiconductor part 30D that is exposed and pre-cleaned through the first contact holes, the non-pixel source contact hole CH1 and the non-pixel drain contact hole CH2. This ensures good contact between the non-pixel semiconductor part 30D and the second conductive part, the non-pixel source electrode 30B and the non-pixel drain electrode 30C. When the drive wiring 33 is provided, the drive wiring 33 is connected to the third metal layer 32C that is exposed through the drive wiring contact hole CH3 and the communication hole 32D1 of the connecting electrode 32.The second metal layer 32B contained in the connecting electrode 32 is less susceptible to over-etching, and the third metal layer 32C contained in the connecting electrode 32 is less susceptible to erosion by hydrofluoric acid, thereby maintaining good contact between the connecting electrode 32 and the drive wiring 33. 【0068】 Furthermore, a sacrificial film F7 made of an oxide semiconductor material is formed, and after the connecting electrode 32 is provided, an annealing treatment is performed. The sacrificial layer 32D included in the connecting electrode 32 is made of an oxide semiconductor material and becomes conductive as the annealing treatment is performed. Therefore, even if the communication hole 32D1 is provided in a way that does not penetrate the sacrificial layer 32D when cleaning with a cleaning agent is performed, the drive wiring 33 can be electrically connected to the third metal layer 32C via the conductive sacrificial layer 32D. This improves the reliability of the connection between the connecting electrode 32 and the drive wiring 33. 【0069】 <Other Embodiments> The technology disclosed herein is not limited to the embodiments described above in the description and drawings, but also includes, for example, the following embodiments. 【0070】 (1) The sacrificial film F7 may be a multilayer film of a semiconductor material and a transparent electrode material. It may also be a multilayer film of multiple semiconductor materials or a multilayer film of multiple transparent electrode materials. 【0071】 (2) The specific material used for the sacrificial film F7 can be changed as appropriate in addition to the above. Specifically, as the material for the sacrificial film F7, oxide semiconductor materials such as In-W-Zn-O semiconductor materials, In-W-Sn-Zn-O semiconductor materials, In-Al-Zn-O semiconductor materials, In-Al-Sn-Zn-O semiconductor materials, Zn-O semiconductor materials, Zn-Ti-O semiconductor materials, Cd-Ge-O semiconductor materials, Cd-Pb-O semiconductor materials, CdO (cadmium oxide), Mg-Zn-O semiconductor materials, In-Ga-Sn-O semiconductor materials, Zr-In-Zn-O semiconductor materials, Hf-In-Zn-O semiconductor materials, Al-Ga-Zn-O semiconductor materials, Ga-Zn-O semiconductor materials, and In-Ga-Zn-Sn-O semiconductor materials can be used. In addition to oxide semiconductor materials, amorphous silicon materials may also be used for the sacrificial film F7. Furthermore, the sacrificial layer 32D may be made of a metallic material in addition to a semiconductor material. 【0072】 (3) The specific numerical value of the thickness of the sacrificial film F7 can be changed as appropriate, even outside the range described above. 【0073】 (4) The specific materials of the first metal film F4 and the third metal film F6 can be changed as appropriate in addition to those mentioned above, for example, they may be made of Ti (titanium). Furthermore, the first metal film F4 and the third metal film F6 are not limited to being made of a single material, but may be alloys made of multiple materials, for example. 【0074】 (5) The specific material of the second metal film F5 can be changed as appropriate in addition to the above, for example, it may be Cu (copper) or Au (gold). 【0075】 (6) The specific numerical values ​​of the film thickness of the first metal film F4, the second metal film F5, and the third metal film F6 can be changed as appropriate, in addition to those stated above. 【0076】 (7) The connecting electrode 32 may have a three-layer structure consisting of a second metal layer 32B, a third metal layer 32C, and a sacrificial layer 32D, with the first metal layer 32A omitted. Alternatively, the connecting electrode 32 may have a laminated structure of five or more layers, in which case the additional metal layer may be placed below the first metal layer 32A or interposed between the first metal layer 32A and the second metal layer 32B. 【0077】 (8) The specific planar shapes (planar patterns) of the non-pixel gate electrode 30A, non-pixel source electrode 30B, non-pixel drain electrode 30C, non-pixel semiconductor portion 30D, connecting wiring 31, connecting electrode 32, and drive wiring 33 can be changed as appropriate, in addition to those shown. For example, the non-pixel gate electrode 30A, non-pixel source electrode 30B, non-pixel drain electrode 30C, and connecting electrode 32 may have a horizontally elongated shape when viewed in a plane. Also, the non-pixel semiconductor portion 30D, connecting wiring 31, and drive wiring 33 may have a planar shape that extends along the Y-axis, or along an oblique direction inclined with respect to both the X-axis and Y-axis. 【0078】 (9) In the method for manufacturing the array substrate 21, the fifth step (resistance reduction step, annealing step) may be performed after the sixth step. 【0079】 (10) The gate wiring 26 is led out to the non-display area AA (non-display area NAA) and connected to the gate circuit section 14. The led portion of the gate wiring 26 that is located in the non-display area NAA may be made of a part of the fourth metal film F9. In that case, the main body portion of the gate wiring 26, which is made of a part of the gate constituent film FG, and the led portion, which is made of a part of the fourth metal film F9, are partially superimposed, and the main body portion and the led portion can be connected by providing a contact hole in the interlayer insulating film F8 interposed between the superimposed portions. In this configuration, the overlapping portion of the main body with the drawer portion becomes the "first conductive portion," the overlapping portion of the drawer portion with the main body becomes the "third conductive portion," the contact hole connecting the main body and the drawer portion becomes the "second contact hole," the pixel source electrode 24B and pixel drain electrode 24C provided on the pixel TFT 24 each become the "second conductive portion," the pixel semiconductor portion 24D becomes the "semiconductor portion," and the pixel source contact hole and pixel drain contact hole become the "first contact hole." 【0080】 (11) If the array substrate 21 is provided with a switch circuit (SSD (Source Shared Driving) circuit) that distributes the image signal supplied from the driver 12 to a plurality of source lines 27, the non-pixel TFT 30 may be included in the switch circuit. In addition, the non-pixel TFT 30 may be provided in a circuit on the array substrate 21 that is included in a circuit other than the gate circuit section 14 or the switch circuit. 【0081】 (12) The pixel TFT 24 and non-pixel TFT 30 may be of a double-gate type or the like, in addition to the top-gate type. In that case, for example, a metal film may be formed on the lower side of the base coat film F1, and the pixel bottom gate electrode superimposed on the pixel semiconductor part 24D and the non-pixel bottom gate electrode superimposed on the non-pixel semiconductor part 30D may be provided using this metal film. 【0082】 (13) The driver 12 may also be mounted on the flexible substrate 13 which is mounted on the array substrate 21 using the FOG (Film On Glass) method, or it may be mounted using the COF (Chip On Film) method. 【0083】 (14) The planar shape of the liquid crystal panel 11 may be a vertically elongated rectangle, square, circle, semicircle, vertically elongated oval, ellipse, trapezoid, etc. 【0084】 (15) The display mode of the liquid crystal panel 11 may be any of the following: FFS (Fringe Field Switching) mode, TN (Twisted Nematic) mode, VA (Vertical Alignment) mode, IPS (In Plane Switching) mode, etc. 【0085】 (16) The display device may be something other than the liquid crystal panel 11 (such as an organic EL (Electro Luminescence) display panel) or an EPD (microcapsule electrophoretic display panel). [Explanation of symbols] 【0086】 11…Liquid crystal panel (display device), 20…Opposite substrate, 21…Array substrate (semiconductor device), 30B…Non-pixel source electrode (second conductive part), 30C…Non-pixel drain electrode (second conductive part), 30D…Non-pixel semiconductor part (semiconductor part), 32…Connecting electrode (first conductive part), 32B…Second metal layer (first conductive layer), 32C…Third metal layer (second conductive layer), 32D…Sacrificial layer, 32D1…Communication hole, 33…Drive wiring (third conductive part), CH1…Non-pixel source contact hole (first contact hole), CH2…Non-pixel drain contact hole (first contact hole), CH3…Drive wiring contact hole (second contact hole), F2…Semiconductor film, F3…Gate insulating film (first insulating film), F5…Second metal film (first conductive film), F6…Third metal film (second conductive film), F7…Sacrificial film, F8…Interlayer insulating film (second insulating film)

Claims

[Claim 1] A semiconductor portion consisting of a part of a semiconductor film, A first insulating film is disposed on the upper layer side of the semiconductor film, A first conductive portion is disposed on the upper layer side of the first insulating film and is arranged so as not to overlap with the semiconductor portion, The first insulating film and the second insulating film disposed on the upper side of the first conductive portion, A second conductive portion is disposed on the upper layer side of the second insulating film and superimposed on the semiconductor portion, The device comprises a third conductive portion disposed on the upper side of the second insulating film and superimposed on the first conductive portion, The first insulating film and the second insulating film are provided with a first contact hole that is arranged superimposed on both the semiconductor portion and the second conductive portion. The second insulating film is provided with a second contact hole that is arranged superimposed on both the first conductive portion and the third conductive portion. The first conductive portion includes at least a first conductive layer consisting of a part of the first conductive film disposed on the upper side of the first insulating film, a second conductive layer consisting of a part of the second conductive film disposed on the upper side of the first conductive film, and a sacrificial layer consisting of a part of the sacrificial film disposed on the upper side of the second conductive film. The sacrificial layer is made of a semiconductor material or a conductive material and has a communication hole that communicates with the second contact hole. [Claim 2] The semiconductor device according to claim 1, wherein the sacrificial layer is made of an oxide semiconductor material which is the semiconductor material. [Claim 3] The semiconductor device according to claim 1 or claim 2, wherein the sacrificial layer is made of the transparent electrode material which is the conductive material. [Claim 4] The semiconductor device according to claim 1 or claim 2, wherein the first conductive layer comprises aluminum and the second conductive layer comprises molybdenum. [Claim 5] The semiconductor device according to claim 1 or claim 2, wherein the sacrificial layer has a film thickness of 40 nm or less. [Claim 6] A semiconductor device according to claim 1 or claim 2, A display device comprising a counter substrate arranged opposite to the semiconductor device. [Claim 7] A semiconductor film is formed, and the formed semiconductor film is patterned to create a semiconductor portion. A first insulating film is formed on the upper layer side of the semiconductor film. At least a first conductive film, a second conductive film, and a sacrificial film made of a semiconductor material or a conductive material are sequentially deposited on the upper side of the first insulating film, and the first conductive film, the second conductive film, and the sacrificial film are patterned to form a first conductive portion at a position that does not overlap with the semiconductor portion, starting from the lower layer side, and including at least a first conductive layer made of a part of the first conductive film, a second conductive layer made of a part of the second conductive film, and a sacrificial layer made of a part of the sacrificial film. A second insulating film is formed on the upper side of the first insulating film and the first conductive portion. By patterning the second insulating film, a portion of the first contact hole is provided at a position overlapping with the semiconductor portion, and a second contact hole is provided at a position overlapping with the first conductive portion. The remaining portion of the first contact hole is provided by patterning the first insulating film after the second insulating film. By supplying a cleaning agent containing hydrofluoric acid to the interior of the first contact hole and the second contact hole, the portion of the semiconductor part facing the first contact hole is cleaned, and a communication hole communicating with the second contact hole is provided in the sacrificial layer of the first conductive part. A second conductive portion is provided on the upper layer side of the second insulating film at a position overlapping with the semiconductor portion, and the second conductive portion is connected to the semiconductor portion through the first contact hole. A method for manufacturing a semiconductor device, comprising providing a third conductive portion on the upper layer side of the second insulating film at a position overlapping with the first conductive portion, and connecting the third conductive portion to the second conductive layer of the first conductive portion through a second contact hole and a communication hole. [Claim 8] The sacrificial film, which is made of the aforementioned semiconductor material, an oxide semiconductor material, is formed. The method for manufacturing a semiconductor device according to claim 7, wherein an annealing treatment is performed after providing the first conductive portion.

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