2T0C-based memory cell and its operating method

Abstract

The present invention provides a 2T0C-based memory cell, a method for operating it, a computer program stored on a computer read medium, a computer read medium on which the computer program is stored, and an apparatus (system). [Solution] The present invention relates to a 2T0C-based memory cell. The 2T0C-based memory cell includes a first transistor and a second transistor connected through a storage node, a first word line connected to the first transistor and controlling the on / off state of the first transistor through the operation of applying a voltage, a second word line connected to the second transistor and controlling the on / off state of the second transistor so that data stored in the memory cell can be read, and a single bit line connected to the first transistor and the second transistor and configured so that the storage node can be charged or discharged in response to the applied voltage.

Description

[Technical Field] 【0001】 The present invention relates to a 2T0C-based memory cell and a method for operating the same, and more specifically, to a 2T0C-based memory cell and a method for operating the same for improving the integration density of memory cells. 【0002】 This invention is derived from research conducted as part of the National Semiconductor Research Laboratory (NSL) Core Technology Development project of the Ministry of Science and ICT (Project ID: 1711197801, Project ID: 00256917, Research Project Title: Development of IGZO V-Tr-based High-Integration / High-Performance Capacitorless DRAM Technology for Next-Generation Neuromorphic Computing Systems, Project Management Agency: Korea Research Foundation, Project Execution Agency: Yonsei University Industry-Academia Cooperation Group, Research Period: 2023.05.01~2024.01.31). On the other hand, there is no property interest of the Korean government in any aspect of this invention. [Background technology] 【0003】 Unlike existing memory cells that contain one transistor and one capacitor, 2T0C-based memory cells represent memory cells that contain two transistors without a capacitor. For example, 2T0C-based memory cells can store data by utilizing the parasitic capacitance formed by the two transistors. 【0004】 Meanwhile, with the development of technologies such as on-device AI, various studies are underway to miniaturize semiconductor chips and improve the integration density of memory cells. However, existing 2T0C-based memory cells are configured to include two bit lines and two word lines, which presents a problem in reducing the feature size, which represents the area of ​​the memory cell. [Overview of the project] [Problems that the invention aims to solve] 【0005】 The present invention provides a 2T0C-based memory cell, a method for operating it, a computer program stored on a computer read medium, a computer read medium storing the computer program, and an apparatus (system) to solve the aforementioned problems. [Means for solving the problem] 【0006】 The present invention can be embodied in various ways, including methods, apparatus (systems), computer programs stored on computer read media, or computer read media containing computer programs. 【0007】 A 2T0C-based memory cell according to one embodiment of the present invention may include a first transistor and a second transistor connected through a storage node; a first word line connected to the first transistor and controlling the on / off state of the first transistor through the operation of applying a voltage; a second word line connected to the second transistor and controlling the on / off state of the second transistor so that data stored in the memory cell can be read; and a single bit line connected to the first transistor and the second transistor and configured so that the storage node can be charged or discharged in response to the applied voltage. 【0008】 Furthermore, when the first word line controls the first transistor to be in an on state and a first voltage is provided through the single bit line, the storage node is charged, thereby allowing the first data to be stored. 【0009】 Also, when the first transistor is controlled to be in an off state by the first word line, the first data stored on the storage node can be retained. 【0010】 Also, when a second voltage is provided through the single-bit line and the second voltage is provided through the second word line, the second transistor operates and the single-bit line senses the voltage value of the second transistor to read out the first data. 【0011】 Also, when the first transistor is controlled to be in an on state by the first word line and a second voltage is provided through the single-bit line, a second data can be stored by discharging the charge on the storage node. 【0012】 Also, when the first transistor is controlled to be in an off state by the first word line and a first voltage is applied to the second word line, the second data stored on the storage node can be retained. 【0013】 Also, when a second voltage is provided through the single-bit line and the second voltage is provided through the second word line, while the second transistor operates, the voltage value of the single-bit line can be sensed to read out the second data. 【0014】 Also, the memory cell can have a smaller feature size than a memory cell using two bit lines using one of the single-bit lines. 【0015】 Also, the memory cell can have a feature size of 12F per bit using one of the single-bit lines. 2 【0016】 Also, the memory cell can be stacked in multiple layers within the range of the feature size. 【0017】 Also, the memory cell can be stacked in two layers within the range of a feature size of 12F per bit 2 and the 2T0C-based memory cell can have a feature size of 6F per bit. 2 【0018】 Also, the memory cell can be stacked in three layers within the range of a feature size of 12F per bit 2 and the 2T0C-based memory cell can have a feature size of 4F per bit. 2 【0019】 Also, the first transistor or the second transistor can have a channel composed of at least one of an oxide and an organic semiconductor. 【0020】 Also, the first transistor or the second transistor can have an insulator composed of at least a part of AIO X , HfO X , SiO X and HfZrO. X 【0021】 A method for operating a 2T0C memory cell, performed by at least one processor according to an embodiment of the present invention, may include the steps of: controlling a first transistor to be turned on based on a first word line; charging a storage node by applying a first voltage to a single bit line and storing first data; controlling the first transistor to be turned off based on the first word line to maintain the charge state of the storage node; and applying a second voltage to the single bit line, and after applying the second voltage to the second word line, sensing the voltage value of the single bit line by the operation of a second transistor connected to the storage node and reading the first data. 【0022】 Furthermore, the step of reading the first data may include a step of sensing the voltage value of the single bit line based on the operation of the second transistor while the storage node is charged, and reading the first data. 【0023】 Furthermore, if the charge state of the storage node is maintained, the process may further include the steps of: controlling the first transistor to be turned ON based on the first word line; discharging charge onto the storage node by applying a second voltage to the single bit line and storing the second data; maintaining the discharge state of the storage node by controlling the first transistor to be turned OFF based on the first word line; and applying a second voltage to the single bit line, and after applying the second voltage to the second word line, the second transistor connected to the storage node operates to sense the voltage value of the single bit line and read out the second data. 【0024】 A computer program stored on a computer-readable non-temporary recording medium is provided for performing the method described above according to one embodiment of the present invention on a computer. [Effects of the Invention] 【0025】 In various embodiments of the present invention, the memory cell can efficiently control the charging and discharging state of the storage node or precisely form a potential difference with the second word line, even while utilizing a single bit line. 【0026】 In various embodiments of the present invention, the 2T0C-based memory cell has a smaller feature size than existing memory cells. Therefore, when it is used by stacking it in multiple layers, the overall memory integration density can be significantly improved. [Brief explanation of the drawing] 【0027】 Embodiments of the present invention will be described below with reference to the accompanying drawings, where similar reference numerals indicate similar elements, but are not limited thereto. [Figure 1] This is an illustrative diagram showing the circuit structure of a 2T0C-based memory cell according to one embodiment of the present invention. [Figure 2] This is an exemplary diagram illustrating the operation of a memory cell during the process of writing or reading first data according to one embodiment of the present invention. [Figure 3] This is an exemplary diagram illustrating the operation of a memory cell during the process of writing or reading second data according to one embodiment of the present invention. [Figure 4] This is an illustrative drawing showing a top-view image of a 2T0C-based memory cell according to one embodiment of the present invention. [Figure 5] This is an illustrative drawing of a 2T0C-based memory cell in a stacked configuration of two layers according to one embodiment of the present invention. [Figure 6] This is an illustrative drawing of a 2T0C-based memory cell in a stacked configuration of three layers according to one embodiment of the present invention. [Figure 7] This table shows the effect on the feature size and number of layers of a 2T0C-based memory cell stacked in multiple layers according to one embodiment of the present invention. [Figure 8]This flowchart illustrates an example of how a 2T0C memory cell operates according to one embodiment of the present invention. [Figure 9] This is a block diagram showing the internal configuration of a computing device according to one embodiment of the present invention. [Modes for carrying out the invention] 【0028】 The specific details for implementing the present invention will be described below with reference to the attached drawings. However, in the following description, if there is a risk of unnecessarily obscuring the gist of the present invention, specific descriptions of widely known functions and configurations will be omitted. 【0029】 In the attached drawings, identical or corresponding components are assigned the same reference numerals. Furthermore, in the following description of embodiments, identical or corresponding components may be omitted from the description. However, the omission of technical details regarding a component does not mean that such a component is not included in the given embodiment. 【0030】 The advantages and features of the disclosed embodiments, and how to achieve them, will become clear by referring to the embodiments described below in detail with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below and can be embodied in a variety of different forms, and these embodiments are merely provided to complete the invention and to fully inform the ordinary art of the scope of the invention. 【0031】 This specification provides a brief explanation of the terms used herein and a detailed explanation of the disclosed embodiments. The terms used herein have been selected from currently widely used general terms, taking into account the function of the present invention, but these may change depending on the intent of the articulate person or precedent, the emergence of new technologies, etc. In some cases, the applicant has arbitrarily selected terms, in which case their meaning will be described in detail in the relevant section of the invention description. Therefore, the terms used in this invention are not simply nouns, but must be defined based on the meaning of the term and the overall content of the present invention. 【0032】 In this specification, singular expressions include plural expressions unless explicitly specified in the context to be singular. Similarly, plural expressions include singular expressions unless explicitly specified in the context to be plural. Throughout the specification, when a given part is said to contain a given component, this does not mean that other components are excluded, but rather that other components may be included, unless otherwise stated. 【0033】 In this disclosure, terms such as “includes” and “contains” indicate the presence of features, stages, actions, elements, and / or components, but such terms do not preclude the addition of one or more other features, stages, actions, elements, components, and / or combinations thereof. 【0034】 Where this disclosure refers to a particular component being “combined,” “associated,” “connected,” or “reacting” with any other component, the particular component may, but is not limited to, be directly combined, associated, and / or connected to or react with the other component. For example, there may be one or more intermediate components between the particular component and the other component. Also, in this invention, “and / or” may include each of the one or more enumerated items or a combination of at least some of the one or more items. 【0035】 In this disclosure, terms such as “first,” “second,” etc., are used to distinguish certain components from other components, and such terms do not limit the components described above. For example, a “first” component may be identical to or similar in form to a “second” component. 【0036】 In this disclosure, “2T0C-based memory cell” can refer to a memory cell that includes two transistors without a capacitor, unlike existing memory cells that include one transistor and one capacitor. For example, a 2T0C-based memory cell can store data by utilizing the parasitic capacitance formed by the two transistors. 【0037】 In this disclosure, “transistor” can refer to an element that regulates and amplifies current or voltage flow, or acts as a switch, and may include, for example, a MOSFET (metal oxide semiconductor field effect transistor). 【0038】 In this disclosure, “storage node” may refer to a parasitic capacitor formed between two transistors, which can be used to store data through charging or discharging. 【0039】 Figure 1 is an exemplary diagram showing the circuit structure of a 2T0C-based memory cell 100 according to one embodiment of the present invention. According to one embodiment, the 2T0C-based memory cell 100 can refer to a memory cell that operates using two transistors without a capacitor. For example, the 2T0C-based memory cell 100 can write or read data using a parasitic capacitor generated by the two transistors as a storage node. 【0040】 As shown in the diagram, the memory cell 100 may include a first transistor 110 and a second transistor 120 connected through the storage node 160. The memory cell 100 may also include a first word line 130 connected to the first transistor 110 and a second word line 140 connected to the second transistor 120. In this case, unlike a typical memory cell having two bit lines, the memory cell 100 may include a single bit line 150 for storing data. 【0041】 According to one embodiment, the first word line 130 can be used to control the on / off state of the first transistor 110. For example, when a bias voltage is applied through the first word line 130, the state of the first transistor 110 can be converted to an on state and a channel can be formed. Conversely, when no voltage is applied through the first word line 130, the state of the first transistor 110 can be converted to an off state and the channel can be blocked. In other words, the first word line 130 can either form or block a path for charge to move through the first transistor 110. 【0042】 According to one embodiment, the second word line 140 can be used to read data stored in a single bit line 150 through the operation of the second transistor 120 by changing the source / drain voltage of the second transistor 120. Specifically, the second word line 140 contributes to reading data stored in the memory cell 100 based on whether the storage node 160 is charged or discharged. For example, if the storage node 160 is charged, the second word line 140 can contribute to operating the second transistor to read that data '1' has been stored, and if the storage node 160 is discharged, it can contribute to reading that data '0' has been stored. 【0043】 According to one embodiment, a single bit line 150 can be connected to a first transistor 110 and a second transistor 120. By adjusting the voltage applied to the single bit line 150, the direction of charge passing through the first transistor 120 can be changed, and the storage node 160 can be charged or discharged accordingly. Furthermore, by adjusting the voltage applied to the single bit line 150, the potential difference between the single bit line 150 connected around the second transistor 120 and the second word line 140 can be changed, and the second transistor, which operates accordingly, may or may not sense the voltage value of the single bit line 150. 【0044】 Figure 1 illustrates that one memory cell 100 is connected through a first word line 130, a second word line 140, and a single bit line 150, but is not limited to this. For example, the memory cell 100 may share the first word line 130, the second word line 140, and the single bit line 150 with other adjacent memory cells. With such a configuration, the memory cell 100 can utilize the single bit line 150 while regulating the charge and discharge state of the storage node 160, or precisely forming a potential difference with the second word line 140 to perform efficient control. 【0045】 Figure 2 is an exemplary diagram showing the operation of a memory cell 100 during the process of writing or reading first data according to one embodiment of the present invention. In the illustrated example, graph 200 shows the time-dependent voltage changes of the first word line 130, the second word line 140, and the single bit line 150. 【0046】 According to one embodiment, an operation can be performed in which first data (e.g., data '1') is written to the memory cell 100 during a time interval between t1 and t2. Referring to Graph 200, a voltage of 1V can be applied to the first word line 130. In this case, the first transistor 110 can be converted to an ON state to form a charge transfer path. Alternatively, a voltage of 1V (e.g., first voltage) can be applied to a single bit line 150. In this case, the charge on the single bit line 150 can be transferred to the storage node 160 through the first transistor 110 and stored. In this way, by charging the storage node 160, the first data can be stored in the memory cell 100. 【0047】 According to one embodiment, the first data stored in the memory cell 100 can be held for a time interval between t2 and t3. Referring to graph 200, the voltage applied to the first word line 130 can be converted from 1V to -2V. In this case, the first transistor 110 can be converted to an off state, thereby blocking the charge transfer path. 【0048】 Furthermore, the voltage applied to the second word line 140 can be converted from 1V to 0V. In this case, the second transistor 120 cannot maintain the potential difference between source and drain, and therefore can block the charge transfer path. 【0049】 In this way, when the charge transfer path is blocked, the storage node 160 remains charged, and consequently, the state in which the first data is stored in the memory cell 100 can be maintained. 【0050】 According to one embodiment, an operation to read the first data stored in the memory cell 100 can be performed in a time interval after t3. Referring to Graph 200, the voltage applied to the single bit line 150 can be converted from 1V to 0V. Also, the voltage applied to the second word line 140 can be converted from 0V to 1V. By applying a 0V voltage (e.g., second voltage) to the single bit line 150 and a 1V voltage to the second word line 140 in this way, a potential difference can be generated on the second transistor 120. At this time, the second transistor 120 operates due to the potential difference generated between the second word line 140 and the single bit line 150, and can sense the voltage value of the single bit line 150 and read the first data. 【0051】 According to one embodiment, the storage node 160 has a positive charge when it is charged, but since no potential difference is generated between the second word line 140 and the single bit line 150, the charge transfer path of the second transistor can be blocked. In Figure 2, for the sake of simplicity, the process of holding the first data and the process of reading the first data are explained separately, but by converting the voltage applied to the first word line 130 and the single bit line 150 in the time interval after t2, the process of holding the first data and the process of reading the first data can be performed simultaneously. Also, although Figure 2 describes that a voltage of -2V or 1V is applied to the first word line 130, it is not limited to this. For example, the first word line 130 can have any voltage value for controlling the on / off state of the first transistor 110. 【0052】 Figure 3 is an exemplary diagram showing the operation of the memory cell 100 during the process of writing or reading second data according to one embodiment of the present invention. In the illustrated example, graph 300 shows the time-dependent voltage changes of the first word line 130, the second word line 140, and the single bit line 150. 【0053】 According to one embodiment, an operation can be performed in which second data (e.g., data '0') is written to the memory cell 100 during a time interval between t1 and t2. Referring to Graph 300, a voltage of 1V can be applied to the first word line 130. In this case, the first transistor 110 can be turned on to form a charge transfer path. Alternatively, a voltage of 0V can be applied to the single bit line 150. In this case, the charge present on the storage node 160 can escape through the first transistor 110, and the storage node 160 can be discharged. By discharging the charge on the storage node 160 in this way, the second data can be stored in the memory cell 100. 【0054】 According to one embodiment, the second data stored in the memory cell 100 can be retained during the time interval between t2 and t3. Referring to graph 300, the voltage applied to the first word line 130 can be converted from 1V to -2V. Also, the voltage applied to the second word line 140 can be converted from 1V to 0V. In this case, the second transistor 120 can not maintain the potential difference between source and drain, and therefore the charge transfer path can be blocked. When the charge transfer path is blocked in this way, the storage node 160 is held in a discharged state, and consequently, the state in which the second data is stored in the memory cell 100 can be retained. 【0055】 According to one embodiment, the operation of reading the second data stored in the memory cell 100 can be performed in the time interval after t3. Referring to Graph 300, a voltage of 0V is applied to the single bit line 150, and the voltage applied to the second word line 140 may be in a state where it can be converted from 0V to 1V. By applying a voltage of 0V to the single bit line 150 and a voltage of 1V to the second word line 140 in this way, a potential difference can be generated on the second transistor 120. At this time, the second word line 140 can sense the voltage value of the single bit line 150 by operating the second transistor 120 due to the generated potential difference and read the second data. 【0056】 In Figure 3, for the sake of simplicity, the processes of holding the second data and reading the second data are explained separately. However, by changing the voltage applied to the first word line 130 in the time interval after t2, the processes of holding the second data and reading the second data can be performed simultaneously. Also, although Figure 3 describes that a voltage of -2V or 1V is applied to the first word line 130, it is not limited to this. For example, the first word line 130 can have any voltage value for controlling the on / off state of the first transistor 110. 【0057】 Figure 4 is an illustrative drawing showing a top-view image of a 2T0C-based memory cell according to one embodiment of the present invention. As shown in (a), the 2T0C-based memory cell can be configured by linking a first word line 130, a second word line 140, a single bit line 150, and a storage node 160 on two transistors made up of a source (S), gate (G), and drain (D). Here, the transistor on the left may be the first transistor 110 described above, and the transistor on the right may be the second transistor 120. 【0058】 According to one embodiment, a first word line 130, a second word line 140, a single bit line 150, and a storage node 160 can be connected to transistors through via holes. Here, via holes are used to electrically connect metal layers and can be formed by drilling holes in the metal layers and filling the holes with a conductive material. In the example shown in (a), the single bit line 150 can be connected to the sources of the first transistor 110 and the second transistor 120, and the first word line 130 can be connected to the gate of the first transistor 110. The second word line 140 can be connected to the drain of the second transistor 120, and the storage node 160 can be connected to the drain of the first transistor 110 and the gate of the second transistor 120. 【0059】 According to one embodiment, the first transistor 110 and / or the second transistor 120 may have a channel composed of at least one of oxide, silicon, and organic semiconductors. Here, the channel may be formed by connecting the source and drain of a memory cell so that charge flow is possible. For example, the substrate of the first transistor 110 and / or the second transistor 120 may be composed of at least one of oxide semiconductors and organic semiconductors, and a source, gate, and drain may be formed on such a semiconductor substrate. Alternatively, the source and drain may be connected and a channel formed by applying a threshold voltage to the gate. 【0060】 According to one embodiment, the first transistor 110 and / or the second transistor 120 are AIO X , HfO X SiO X and HfZrO X It can have an insulator composed of at least a portion of the above. Here, the insulator refers to the film located between the substrate and the gate so that current does not flow to the gate of the transistor, and x can be a natural number with a range limited according to each molecular structure. That is, AIO X , HfO XSiO X and HfZrO X By including an insulator composed of at least a portion of the above, the dielectric constant can be improved while appropriately reducing leakage current. 【0061】 Feature size is a term used in semiconductors and electronic circuits to refer to the size of memory cells. Feature size is primarily used in semiconductor manufacturing processes and can indicate the size of individual circuit components such as transistors and memory cells. It can also refer to the size of the smallest structure used in semiconductor manufacturing processes. 【0062】 According to one embodiment, since a 2T0C-based memory cell uses one single bit line, it can have a smaller feature size than a memory cell that uses two bit lines. (b) When using one single bit line 150 as shown in the drawing, the memory cell is 12F, consisting of a vertical length of 2F and a horizontal length of 6F. 2 It can have a feature size of 18F. That is, the memory cell is 18F 2 Compared to conventional memory cells with 6F 2 This can have a reduced feature size. This means the feature size per bit corresponding to one bit is 12F. 2 It is possible that this is the case. 【0063】 Figure 4 shows a 12F memory cell based on 2T0C, composed of 2F and 6F cells. 2 Although illustrated as having a feature size of , this is illustrative, and 2T0C-based memory cells may have a smaller feature size than memory cells using two bit lines. With such a configuration, 2T0C-based memory cells have a smaller feature size than existing memory cells, and when used stacked in multiple layers, the overall memory integration density can be significantly improved. 【0064】 On the other hand, a memory device according to one embodiment may include memory cells 100. In this case, the memory device may consist only of a plurality of memory cells 100, but it may also include a plurality of memory cells 100 and an auxiliary memory cell that uses two bit lines. That is, the auxiliary memory cell may be a general memory cell having two bit lines. 【0065】 The signal application device can be connected to the first word line 130, the second word line 140, the two bit lines, and the single bit line 150 included in the memory device, and can be configured to determine the size of the voltage applied to each line and to apply the voltage. 【0066】 The memory device is electrically detachable from the signal application device. The voltage applied to the bit line of the memory device can be determined by the signal application device to which it is connected. In this case, if the signal application device is a type that applies voltage to two bit lines and not a type that determines the voltage applied to a single bit line 150, the memory device containing only the memory cell 100 may not function properly. 【0067】 The memory device's processor can determine, based on the signals transmitted from the connected signaling device, whether the connected signaling device applies voltage to two bit lines or determines the voltage applied to a single bit line 150. 【0068】 If the memory device determines that the connected signaling device applies voltage to two bit lines, it can apply voltage to the two pairs of bit lines of the auxiliary memory cell in such a way that two bit line signals are transmitted to the auxiliary memory cell that uses two bit lines. 【0069】 If the memory device determines that the connected signal application device applies voltage to a single bit line 150, it can apply voltage to the single bit line 150 of the memory cell 100 in such a way that two bit line signals are transmitted to the memory cell 100. 【0070】 Thus, the memory device of this embodiment does not simply utilize a memory cell 100 through which a bit line signal is transmitted via a single bit line, but can also utilize an auxiliary memory cell through which two bit line signals are transmitted depending on the situation. Therefore, its operation is not limited by whether the received signal is a single bit line signal or a two-bit line signal, and it can operate in any case. 【0071】 According to one embodiment, a 2T0C-based memory cell may be in a form that can be stacked in multiple layers. That is, a 2T0C-based memory cell may be 12F 2 Multiple layers can be stacked within the feature size range. When multiple memory cells are stacked as multiple layers in this way, the same feature size as when using a single memory cell is used, so the overall integration density of the memory can be increased. For example, when two layers are stacked, logically one memory cell is 6F 2 Since it occupies only the area of ​​the memory, the more layers are stacked, the higher the memory integration density can be. 【0072】 A single layer of memory cells uses one single bit line, with 12F per bit. 2 It can have a feature size of [specify feature size]. 【0073】 That is, a fixed area (12F 2When memory cells are stacked in multiple layers, the memory cells are stacked vertically, so the area they occupy remains the same, but the number of bits that can be processed increases, and as a result the feature size required per bit of a 2T0C-based memory cell composed of multiple layers can be reduced. 【0074】 In other words, if the number of layers is n, the required feature size per bit for a 2T0C-based memory cell composed of multiple layers is 12F. 2 It could be / n 【0075】 Figure 5 is an illustrative diagram of a 2T0C-based memory cell in a stacked configuration of two layers according to one embodiment of the present invention. 【0076】 Referring to Figure 5, the memory cell is 12F per bit. 2 It is possible to stack two layers within the range of feature size. 【0077】 At this time, the 2T0C-based memory cells as a whole had 6F per bit. 2 It can have a feature size of 6F. That is, the required feature size per bit is 6F. 2 It is possible. 【0078】 Figure 6 is an illustrative diagram of a 2T0C-based memory cell in a three-layer stacked configuration according to one embodiment of the present invention. 【0079】 Referring to Figure 6, the memory cell is 12F per bit. 2 It is possible to stack three layers within the range of the feature size. 【0080】 At this time, the 2T0C-based memory cells as a whole had 4F per bit. 2 It can have a feature size of 4F. That is, the required feature size per bit is 4F. 2It is possible. 【0081】 Figure 7 is a table showing the effect on the feature size and number of layers of a 2T0C-based memory cell stacked in multiple layers according to one embodiment of the present invention. 【0082】 Referring to Figure 7, it can be seen that in one embodiment of a 2T0C-based memory cell (Single bit line-based 2T0C DRAM), when multiple memory cells are stacked, the area required to process any one unit of bit is reduced compared to a conventional memory cell (Conventional 2T0C DRAM), and accordingly, the number of stacked layers required can also be reduced. 【0083】 For example, 6F per bit 2 If you need a 2T0C-based memory cell with the performance of that feature size, a conventional memory cell (Conventional 2T0C DRAM) would have 18F per bit per layer. 2 Because it has the performance of a feature size, three layers were deemed necessary. 【0084】 However, one embodiment of a 2T0C-based memory cell (Single bit line-based 2T0C DRAM) has 12F per bit per layer. 2 Because it has the performance of a feature size, even if only two layers are stacked, it is 6F per bit. 2 It can achieve performance with a feature size of [specify feature size]. 【0085】 Therefore, a 2T0C-based memory cell according to one embodiment can achieve the same performance even when stacking fewer memory cell layers compared to conventional memory cells. 【0086】 Figure 8 is a flowchart illustrating an example of a 2T0C memory cell operation method 500 according to one embodiment of the present invention. The 2T0C memory cell operation method 500 can be performed by a processor (e.g., at least one processor of a computing device). The 2T0C memory cell operation method 500 can be initiated by the processor controlling a first transistor to an ON state based on a first word line (S510). 【0087】 According to one embodiment, the processor can charge a storage node by applying a first voltage to a single bit line and store first data (S520). For example, when a voltage of 1V is applied to a single bit line, the charge on the single bit line can move through a first transistor to the storage node and be stored. In this way, the first data can be stored in the memory cell by charging the storage node. 【0088】 The processor can maintain the charge state of the storage node by controlling the first transistor to the off state based on the first word line (S530). Alternatively, after applying a second voltage to a single bit line, the processor can operate a second transistor connected to the storage node through the second word line to sense the voltage value of the single bit line and read out the first data (S540). For example, the processor can operate the second transistor while the storage node is charged, sense the change in the voltage value of the changed single bit line, and read out the first data. 【0089】 According to one embodiment, the processor can control the first transistor to the ON state based on the first word line when the charge state of the storage node is maintained. Furthermore, the processor can discharge the charge on the storage node by applying a second voltage to a single bit line, thereby storing second data. That is, the second data can be stored in the memory cell by the discharge of charge on the storage node. 【0090】 The processor can maintain the discharge state of the storage node by controlling the first transistor to the off state based on the first word line. Alternatively, after applying a second voltage to a single bit line, the processor can operate a second transistor connected to the storage node through the second word line to sense the voltage value of the single bit line and read out the second data. For example, the processor can sense the voltage value of the second transistor in a discharged state on the storage node based on the leakage current generated by the second transistor and read out the second data. 【0091】 Figure 9 is a block diagram showing the internal configuration of a computing device 600 according to one embodiment of the present invention. According to one embodiment, the computing device 600 can refer to any device for controlling a storage device including the 2T0C-based memory cell and / or a plurality of 2T0C-based memory cells described above. The computing device 600 may include a memory 610, a processor 620, a communication module 630, and an input / output interface 640, and as shown in Figure 9, the computing device 600 may be configured to communicate information and / or data over a network using the communication module 630. 【0092】 The memory 610 may include any non-temporary computer-readable recording medium. According to one embodiment, the memory 610 may include a permanent mass storage device such as RAM (random access memory), ROM (read-only memory), a disk drive, an SSD (solid-state drive), or flash memory. As another example, a permanent mass storage device such as ROM, an SSD, flash memory, or a disk drive may be included in the computing device 600 as a separate permanent storage device distinct from the memory. The memory 610 may also store an operating system and at least one program code. 【0093】 Such software components can be loaded from a computer-readable storage medium separate from memory 610. Such a computer-readable storage medium may include a storage medium that can be directly connected to such computing device 600, and may include computer-readable storage media such as floppy drives, disks, tapes, DVD / CD-ROM drives, and memory cards. As another example, software components may be loaded into memory 610 through a communication module 630 that is not a computer-readable storage medium. For example, at least one program may be loaded into memory 610 based on a computer program installed by a file provided through the communication module 630 by a developer or a file distribution system that distributes application installation files. 【0094】 The processor 620 can be configured to process computer program instructions by performing basic arithmetic, logic, and input / output operations. Instructions can be provided to other user terminals (not shown) or other external systems via memory 610 or a communication module 630. 【0095】 The communication module 630 can provide a configuration or function for a user terminal (not shown) and a computing device 600 to communicate with each other via a network, and can also provide a configuration or function for the computing device 600 to communicate with an external system (for example, another cloud system). For example, control signals, instructions, data, etc., provided in response to the control of the processor 620 of the computing device 600 can be transmitted to the user terminal and / or the external system via the communication module of the user terminal and / or the external system through the communication module of the user terminal and / or the external system via the communication module of the user terminal and / or the external system via the network. 【0096】 Furthermore, the input / output interface 640 of the computing device 600 may be a means for connecting to the computing device 600 or for interface with an input or output device (not shown) that the computing device 600 may include. In Figure 9, the input / output interface 640 is shown as an element configured separately from the processor 620, but is not limited to this, and the input / output interface 640 can be configured to be included in the processor 620. The computing device 600 may include even more components than those shown in Figure 9. However, it is not necessary to explicitly illustrate most of the components of the prior art. 【0097】 The processor 620 of the computing device 600 can be configured to manage, process, and / or store information and / or data received from multiple user terminals and / or multiple external systems. 【0098】 The methods and / or various embodiments described above can be implemented in digital electronic circuits, computer hardware, firmware, software, and / or combinations thereof. Various embodiments of the present invention can be executed by data processing devices, such as one or more programmable processors and / or one or more computing devices, or embodied in computer-readable recording media and / or computer programs stored on computer-readable recording media. The computer programs described above can be written in any form of programming language, including compiled or interpreted languages, and can be distributed in any form, such as standalone programs, modules, subroutines, etc. Computer programs can be distributed through one computing device, multiple computing devices connected through the same network and / or multiple computing devices distributed to be connected through multiple different networks. 【0099】 The methods and / or various embodiments described above can be carried out by one or more processors configured to execute one or more computer programs that process, store, and / or manage arbitrary functions, functions, etc., by operating on input data or generating output data. For example, the methods and / or various embodiments of the present invention can be carried out by special-purpose logic circuits such as FPGAs (Field Programmable Gate Arrays) or ASICs (Application Specific Integrated Circuits), and the apparatus and / or systems for carrying out the methods and / or embodiments of the present invention can be embodied as special-purpose logic circuits such as FPGAs or ASICs. 【0100】 One or more processors that execute a computer program may include one or more processors in a general-purpose or special-purpose microprocessor and / or any type of digital computing device. A processor may receive instructions and / or data from read-only memory and random-access memory, or it may receive instructions and / or data from both read-only memory and random-access memory. In the present invention, components of a computing device that carries out the method and / or embodiments may include one or more processors for executing instruction words and one or more memory devices for storing instruction words and / or data. 【0101】 According to one embodiment, a computing device can exchange data with one or more mass storage devices for storing data. For example, a computing device can receive data from and / or an optical disc, and / or transmit data to a magnetic disc or optical disc. A computer-readable storage medium suitable for storing instruction words and / or data associated with a computer program may include, but is not limited to, any form of non-volatile memory, such as semiconductor memory devices including EPROM (Erasable Programmable Read-Only Memory), EEPROM (Electrically Erasable PROM), and flash memory devices, as a memory device in which a plurality of memory cells 100 and a plurality of auxiliary memory cells are arranged. For example, the computer-readable storage medium may include magnetic disks such as internal hard disks or portable disks, magneto-optical disks, CD-ROMs, and DVD-ROM disks. 【0102】 To provide interaction with the user, a computing device may include, but is not limited to, a display device (e.g., a CRT (Cathode Ray Tube), an LCD (Liquid Crystal Display), etc.) for providing or displaying information to the user, and a pointing device (e.g., a keyboard, mouse, trackball, etc.) on which the user can provide input and / or commands to the computing device. In other words, a computing device may further include any other type of device for providing interaction with the user. For example, a computing device may provide the user with any form of sensory feedback, including visual feedback, auditory feedback, and / or tactile feedback, etc., for interaction with the user. In response, the user may provide input to the computing device through various gestures such as sight, sound, and movement. 【0103】 In the present invention, various embodiments can be embodied in a computing system including backend components (e.g., data servers), middleware components (e.g., application servers), and / or frontend components. In this case, the components can be interconnected by any form or medium of digital data communication, such as a communication network. For example, the communication network may include a LAN (Local Area Network), a WAN (Wide Area Network), etc. 【0104】 A computing device based on the exemplary embodiments described herein may be embodied using hardware and / or software configured to interact with a user, including a user device, a user interface UI device, a user terminal, or a client device. For example, a computing device may include a portable computing device such as a laptop computer. Additionally or alternatively, a computing device may include, but is not limited to, PDAs (Personal Digital Assistants), tablet PCs, game consoles, wearable devices, IoT (Internet of Things) devices, VR (virtual reality) devices, AR (augmented reality) devices, etc. A computing device may further include other types of devices configured to interact with a user. A computing device may also include portable communication devices suitable for wireless communication over a network such as a mobile communication network (e.g., mobile phones, smartphones, wireless cellular phones, etc.). Computing devices can be configured to communicate wirelessly with network servers using wireless communication technologies and / or protocols such as radio frequency (RF), microwave frequency (MWF), and / or infrared ray frequency (IRF). 【0105】 The various embodiments of the present invention, including specific structural and functional details, are illustrative. Therefore, embodiments of the present invention are not limited to those described above and can be embodied in various other forms. Furthermore, the terminology used in the present invention is for the purpose of describing some embodiments and is not intended to limit the embodiments. For example, singular words and above may be interpreted to include plural forms unless otherwise clearly indicated in the context. 【0106】 In this invention, unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as they are generally understood by a person of ordinary skill in the art to which such concepts belong. Furthermore, commonly used terms, such as those defined in dictionaries, must be analyzed to have a meaning consistent with their meaning in the context of the relevant art. 【0107】 Although the present invention has been described in relation to some embodiments, various modifications and alterations can be made without departing from the scope of the invention as understandable to a person ordinary in the art to which the invention pertains. Such modifications and alterations should be construed as falling within the scope of the claims appended herein. [Explanation of symbols] 【0108】 110 First Transistor 120 Second Transistor 130 First Wordline 140 Second Wordline 150 Single-bit Line 160 storage nodes

Claims

[Claim 1] A 2T0C-based memory cell, A first transistor and a second transistor connected through a storage node, A first word line connected to the first transistor controls the on / off state of the first transistor by applying a voltage, A second word line is connected to the second transistor and controls the on / off state of the second transistor so that data stored in the memory cell can be read, A single bit line connected to the first transistor and the second transistor, configured such that the storage node can be charged or discharged in accordance with the applied voltage, A 2T0C-based memory cell including this. [Claim 2] The 2T0C-based memory cell according to claim 1, wherein the first word line controls the first transistor to be on state and a first voltage is provided through the single bit line, thereby charging the storage node and storing first data. [Claim 3] The 2T0C-based memory cell according to claim 2, wherein the first transistor is controlled to an off state by the first word line, thereby holding the first data stored on the storage node. [Claim 4] A 2T0C-based memory cell according to claim 3, wherein when a second voltage is provided through the single bit line and the second voltage is provided through the second word line, the second transistor operates so that the single bit line senses the voltage value of the second transistor and reads out the first data. [Claim 5] The 2T0C-based memory cell according to claim 1, wherein the first word line controls the first transistor to be turned on, and when a second voltage is provided through the single bit line, a second data is stored by discharging a charge onto the storage node. [Claim 6] The 2T0C-based memory cell according to claim 5, wherein the first word line controls the first transistor to an off state, and the second data stored on the storage node is held by applying a first voltage to the second word line. [Claim 7] A 2T0C-based memory cell according to claim 6, wherein when a second voltage is provided through the single bit line and the second voltage is provided through the second word line, the second transistor operates and senses the voltage value of the single bit line to read out the second data. [Claim 8] The memory cell uses one of the single bit lines to obtain 12F per bit. ２ A 2T0C-based memory cell according to claim 1, having a feature size of . [Claim 9] The 2T0C-based memory cell according to claim 8, wherein the memory cell can be stacked in multiple layers within the range of the feature size. [Claim 10] The memory cell has 12F per bit. ２ It is possible to stack two layers within the feature size range, The aforementioned 2T0C-based memory cell is 6F per bit ２ A 2T0C-based memory cell according to claim 9, having a feature size of . [Claim 11] The memory cell has 12F per bit. ２ It is possible to stack three layers within the feature size range, The aforementioned 2T0C-based memory cell is 4F per bit ２ A 2T0C-based memory cell according to claim 9, having a feature size of . [Claim 12] The 2T0C-based memory cell according to claim 1, wherein the first transistor or the second transistor has a channel composed of at least one of oxide and organic semiconductor materials. [Claim 13] The first transistor or the second transistor is an AIO Ｘ , HfO Ｘ , SiO Ｘ and having an insulator composed of at least a part of HfZrO Ｘ , the 2T0C-based memory cell according to claim 1. [Claim 14] A method for operating a 2T0C memory cell, performed by at least one processor, A step of controlling the first transistor to the ON state based on the first word line, The process involves applying a first voltage to a single bit line to charge the storage node and store the first data, A step of controlling the first transistor to an off state based on the first word line to maintain the charge state of the storage node, The first step involves applying a second voltage to the single bit line, applying the second voltage to the second word line, and then having a second transistor connected to the storage node operate to sense the voltage value of the single bit line and read out the first data. A method for operating a 2T0C-based memory cell, including the following: [Claim 15] The step of reading the first data is, The steps include: reading the first data by sensing the voltage value of the single bit line based on the operation of the second transistor while the storage node is charged; A method for operating a 2T0C-based memory cell according to claim 14, including the following: [Claim 16] If the charge state of the storage node is maintained, the first transistor is controlled to be turned on based on the first word line. The steps include: discharging charge on the storage node by applying a second voltage to the single bit line and storing the second data; A step of controlling the first transistor to an off state based on the first word line to maintain the discharge state of the storage node, The steps include: applying a second voltage to the single bit line, applying the second voltage to the second word line, and then the second transistor connected to the storage node operates to sense the voltage value of the single bit line and read the second data; A method for operating a 2T0C-based memory cell according to claim 14, further comprising: [Claim 17] A non-temporary recording medium storing a computer-readable computer program for executing the operation method of a 2T0C-based memory cell according to any one of claims 14 to 16.

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