Wiring board and method for manufacturing a wiring board

Abstract

The objective is to provide a wiring board and a method for manufacturing a wiring board that can reliably mount fine wiring members 50 within a cavity 35 in close proximity to its side wall. [Solution] A wiring board 20 on which at least one semiconductor element 40 is mounted, wherein the wiring board has a core layer 60, and wiring layers (21, 22) are arranged on the first and second surfaces of the core layer, and the core layer is provided with at least one through-electrode 30 that penetrates from the first surface to the second surface. Furthermore, at least one bottomed cavity 35 is formed on the surface on which the semiconductor elements of the core layer are mounted. The inclination angle of the side wall of the cavity is such that, with respect to the depth D1 of the cavity, the inclination angle θ1 of the side wall from the bottom of the cavity up to 40% of the height is in the range of 25 to 60 degrees. The inclination angle θ2 of the side walls, which are more than 40% in height from the bottom of the cavity, is in the range of 1.5 degrees to 5.0 degrees.

Description

Technical Field

[0001] Wiring board and method for manufacturing the same

Background Art

[0002] In recent years, due to the innovations in semiconductor technology, semiconductor packaging technology, manufacturing process technology, and software technology, the high performance of electronic products has been rapidly progressing. Semiconductor technology has achieved line widths in nano units below micrometers, realized more than tens of millions of highly integrated cells per chip, and has also achieved various developments such as high-speed operation and heat treatment. However, in response to the advancement of these semiconductor elements, the packaging technology may not be fully established, and the performance of the final semiconductor product may be restricted by the packaging technology and its electrical connection technology.

[0003] As the material of the packaging substrate, ceramics or resins are often used. In the case of a ceramic substrate, although it has a high resistance value and excellent insulation against direct current, its dielectric constant is high, and the energy loss in an alternating current field becomes large, so it is not necessarily suitable for mounting high-performance high-frequency semiconductor elements. In the case of a resin substrate, high-frequency semiconductor elements can be mounted, but there is a limit to the pitch of the wiring that can be formed on the substrate, and warping may occur due to the influence of the heat history, so it is difficult to mount highly improved semiconductor elements.

[0004] On the other hand, in recent years, attention has been focused on the technology of applying silicon or glass to high-end packaging substrates. By forming through holes in a silicon or glass substrate and attaching a conductive substance to these through holes to form an intermediate substrate used between a semiconductor element and a motherboard, the length of the wiring between the semiconductor element and the motherboard can be shortened, and an intermediate substrate with excellent electrical characteristics can be obtained.

[0005] For example, in Patent Document 1, for the purpose of providing a packaging substrate having a cavity structure and applicable to a high-speed circuit and a semiconductor device including the same, the following disclosure is made. "The semiconductor device 100 includes a semiconductor element section 30 containing semiconductor elements 32, 34, and 36, and a packaging substrate 20 electrically connected to the semiconductor element section. By applying a glass substrate as a core to the packaging substrate 20, the semiconductor elements and the motherboard are connected more closely, and electrical signals are transmitted over the shortest possible distance. This greatly improves electrical characteristics such as signal transmission speed and simplifies the insulating film processing process by substantially preventing the generation of parasitic elements." [Prior art documents] [Patent Documents]

[0006] [Patent Document 1] Japanese Patent Publication No. 2023-52130 [Overview of the Initiative] [Problems that the invention aims to solve]

[0007] In Patent Document 1, in order to fix a component (cavity element) within the cavity, an arc-shaped support portion is provided, protruding into the internal space of the cavity, connecting one end and the other end of the side surface of the cavity portion. The position of the cavity element is then fixed by this support portion. However, because glass substrates are brittle materials, using a support part with an arc shape connecting one end to the other may cause cracking or chipping during component fixation. Furthermore, using an arc shape connecting one end to the other makes it difficult to shorten the distance between the cavity and the through-electrode of the element.

[0008] Furthermore, in the process of mounting components inside the cavity, DAF material (Die Attach Film) formed on the components by applying temperature and load is used to embed the components. While DAF material with a thickness of 15-20 μm is generally used, defects have been observed where the DAF material creeps up the sides and then onto the surface of the mounted components due to the heat and load during component mounting. In addition, because DAF material has a different coefficient of thermal expansion (CET) and elastic modulus than the insulating resin used in wiring boards, the stress applied to the mounted components when the structure is formed as a wiring board differs, resulting in damage to mounted components and delamination at the interface with the mounted components, raising concerns about the reliability of the package substrate. Furthermore, after embedding components inside the cavity, the surface of the wiring board is filled with insulating resin. However, if the insulating resin contains solid substances such as fillers, and the gap between the inner wall of the cavity and the mounted components differs significantly in the vertical direction, the fillers can get trapped between the inner wall and the mounted components, preventing the insulating resin from penetrating the cavity sufficiently.

[0009] Therefore, the present invention aims to provide a wiring board and a method for manufacturing a wiring board that can reliably mount fine wiring members within a cavity in close proximity to its side walls. [Means for solving the problem]

[0010] To solve the above problems, one representative multilayer wiring board of the present invention is a wiring board on which at least one semiconductor element is mounted, The aforementioned wiring board has a core layer, A wiring layer is arranged on the first and second surfaces of the core layer. The core layer is provided with at least one through-electrode that penetrates from the first surface to the second surface. Furthermore, at least one bottomed cavity is formed on the surface on which the semiconductor elements of the core layer are mounted. A fine wiring component is placed in the cavity. The inclination angle of the side wall of the cavity is, With respect to the cavity depth D1, the inclination angle θ1 of the side wall from the bottom of the cavity up to 40% of its height is in the range of 25 to 60 degrees. The inclination angle θ2 of the side walls, which are more than 40% in height from the bottom of the cavity, is in the range of 1.5 degrees to 5.0 degrees.

[0011] Furthermore, one of the typical methods for manufacturing the wiring board of the present invention is: A process of irradiating the core layer of the wiring board with a laser to the areas where through electrodes and cavities are to be formed, and performing an etching process to form cavities with roughness of Sa of 500 nm or more at the bottom of the through holes and cavities, A step of arranging a fine wiring member in the cavity, It has. [Effects of the Invention]

[0012] According to the present invention, it is possible to provide a wiring board and a method for manufacturing a wiring board that enable reliable mounting of fine wiring members within a cavity, with the fine wiring members positioned close to the side walls of the cavity and without the gap between the inner wall of the cavity and the fine wiring members varying significantly in the vertical direction. Other issues, configurations, and effects not mentioned above will be clarified by the description of the embodiments for carrying out the invention below. [Brief explanation of the drawing]

[0013] [Figure 1] Figure 1 is a cross-sectional view of a semiconductor package substrate. [Figure 2A] Figure 2A is a plan view of a semiconductor package substrate on which one wiring board is mounted. [Figure 2B] Figure 2B is a plan view of a semiconductor package substrate on which multiple wiring boards are mounted. [Figure 3] Figure 3 is a cross-sectional view showing an example of a semiconductor package substrate. [Figure 4] Figure 4 is a cross-sectional view showing the structure of the core layer. [Figure 5A] Figure 5A is a diagram illustrating the shape of the bottom of the cavity. [Figure 5B]FIG. 5B is a diagram for explaining the shape of the bottom of the cavity. [Figure 6] FIG. 6 is a diagram for explaining the shape of the side wall of the cavity. [Figure 7] FIG. 7 is a diagram for explaining the inclination angle of the side wall of the cavity. [Figure 8] FIG. 8 is a diagram for explaining the positional relationship between the cavity and the through hole. [Figure 9] FIG. 9 is a cross-sectional view for explaining the through electrodes and wirings formed in the core layer. [Figure 10] FIG. 10 is a cross-sectional view of a semiconductor package substrate according to the second embodiment. [Figure 11] FIG. 11 is a cross-sectional view for explaining the third embodiment in which a plurality of types of cavities are mixed. [Figure 12] FIG. 12 is a diagram showing the process of eluting the core layer. [Figure 13] FIG. 13 is a diagram showing the process of performing laser processing that serves as the starting point of the through hole and the cavity in the core layer. [Figure 14] FIG. 14 is a diagram for explaining the overlap of the modified portions by laser modification and etching. [Figure 15] FIG. 15 is a diagram for explaining the process of forming the through hole and the cavity of the core material by etching. [Figure 16] FIG. 16 is a diagram for explaining the shape of the through hole formed in the core layer. [Figure 17] FIG. 17 is a diagram for explaining the process of forming a conductor layer in the through hole formed in the core layer. [Figure 18] FIG. 18 is a diagram for explaining the process of mounting the fine wiring member in the cavity portion. [Figure 19] FIG. 19 is a diagram for explaining the process of forming insulating resin layers on the front and back surfaces of the core material and the fine wiring member. [Figure 20] FIG. 20 is a diagram for explaining the process of forming wirings on the insulating resin layers formed on the front and back surfaces of the core material. [Figure 21] FIG. 21 is a diagram for explaining the process of forming the wiring layer and the connection terminals. [Figure 22] Figure 22 illustrates the connection process between a semiconductor element and a wiring board. [Figure 23] Figure 23 illustrates the underfill filling process at the connection point between the semiconductor element and the wiring substrate. [Figure 24] Figure 24 illustrates the formation of the protective resin for semiconductor devices. [Figure 25] Figure 25 is a diagram illustrating the laser processing process according to the second embodiment. [Figure 26] Figure 26 is a diagram illustrating the etching process according to the second embodiment. [Figure 27] Figure 27 illustrates a modified structure of a semiconductor package substrate according to an embodiment of the present invention, illustrating the laser processing process that serves as the starting point for through-holes in the cavity. [Figure 28] Figure 28 illustrates an etching process for forming through holes in a cavity portion using a modified structure of a semiconductor package substrate according to an embodiment of the present invention. [Modes for carrying out the invention]

[0014] The embodiments of the present invention will be described below with reference to the drawings. The embodiments and examples shown below are merely examples of embodiments of the present invention, and the present invention is not limited to these embodiments and examples. In the drawings referenced in embodiments of the present invention, the same parts are denoted by the same or similar reference numerals (simply numbers followed by A, B, etc.), and repeated explanations may be omitted. Furthermore, the dimensions and proportions described in the drawings may differ from actual proportions or be omitted from the configuration for the sake of explanation and notation.

[0015] The positions, sizes, shapes, and ranges of each component shown in the drawings may not represent their actual positions, sizes, shapes, or ranges in order to facilitate understanding of the invention. Therefore, the present invention is not necessarily limited to the positions, sizes, shapes, and ranges disclosed in the drawings.

[0016] In this disclosure, "surface" may refer not only to the surface of the plate-like member, but also to the interface of a layer contained within the plate-like member that is substantially parallel to the surface of the plate-like member. Furthermore, "upper surface" and "lower surface" refer to the surfaces shown above or below the plate-like member or the layers contained within the plate-like member in the drawing. In addition, "upper surface" and "lower surface" may also be referred to as "first surface" and "second surface."

[0017] Furthermore, "side surface" refers to the surface or thickness of a layer within a plate-like member or a layer contained within a plate-like member. In addition, a part of the surface and the side surface together are sometimes referred to as the "end." Furthermore, "side of the through hole" refers to the interface on the object that forms the through hole in the object. Furthermore, "upward" refers to the vertically upward direction when a plate-like member or layer is placed horizontally. In addition, "upward" and its opposite, "downward," may be referred to as the "positive Z-axis direction" and the "negative Z-axis direction," respectively, while the horizontal direction may be referred to as the "X-axis direction" and the "Y-axis direction."

[0018] Furthermore, the distance along the Z-axis is referred to as "height," and the distance on the XY plane defined by the X-axis and Y-axis is referred to as "width." In addition, when referring to the height of a layered object, it is also referred to as "thickness." Furthermore, "through-electrode" refers to a conductive path provided to electrically connect the first and second surfaces of a glass substrate when the glass substrate is used as part of a multilayer wiring board, and it is not necessarily required that the glass substrate be completely penetrated by a single conductive material. If the conductive path from the first surface and the conductive path from the second surface are connected, it is included as a through-electrode. Moreover, the form of the through-electrode may be a filled structure in which the through-hole is filled with conductive material, or a conformal structure in which only the side walls of the through-hole are covered with conductive material.

[0019] Furthermore, "planar shape" and "planar view" refer to the shape of a surface or layer as viewed from above. In addition, "cross-sectional shape" and "cross-sectional view" refer to the shape of a plate-like member or layer as viewed from the horizontal when it is cut in a specific direction. Furthermore, "center" refers to the central part of a surface or layer, not its periphery. And "center direction" refers to the direction from the periphery of a surface or layer toward the center of the planar shape of the surface or layer.

[0020] Furthermore, when a numerical range is indicated as, for example, "3-10 ppm / °C," it refers to a range between 3 ppm / °C and 10 ppm / °C. The same applies to other numerical ranges.

[0021] Furthermore, surface roughness Sa represents the average of the absolute differences in height between each point relative to the average surface level, and is defined by the following formula.

number

[0022] Furthermore, the PV value represents the difference in height between the highest point (peak) and the lowest point (valley) on the surface. The depth of the recess is defined by the following formula.

number

[0023] <First Embodiment> (Semiconductor package substrate) First, the structure of the semiconductor package substrate in the first embodiment will be described with reference to Figure 1. Figure 1 is a cross-sectional view of the semiconductor package substrate mounted on the motherboard 1. The semiconductor package substrate 100 according to the embodiment of the present invention consists of an FC-BGA substrate 10, a wiring board 20, and semiconductor elements 40. The wiring board 20 is a wiring board for connecting the FC-BGA substrate 10 and the semiconductor elements 40, and fine wiring members 50 are mounted on the wiring board 20. As shown in Figure 1, the semiconductor package substrate 100 is mounted on the motherboard 1 and transmits external electrical signals from the motherboard 1 to the semiconductor elements 40. Furthermore, the fine wiring members 50 mounted on the wiring board 20 can electrically connect multiple semiconductor elements mounted on the wiring board 20 to each other. As for the semiconductor elements 40, a CPU such as HBM (High Bandwidth Memory) can be mounted.

[0024] (Planar shape of semiconductor package substrate) Next, with reference to Figures 2A and 2B, the planar shape of the semiconductor package substrate 100 on which the semiconductor element 40 and the wiring board 20 are mounted will be described when viewed from above. Figure 2A is a plan view of the semiconductor package substrate 100 on which one wiring board is mounted, and Figure 2B is a plan view of the semiconductor package substrate 100 on which multiple wiring boards are mounted. As shown in Figures 2A and 2B, at least one semiconductor element 40 is mounted on top of the wiring board 20 in the semiconductor package substrate 100, and the semiconductor elements are electrically connected to each other via the wiring board 20. Furthermore, the semiconductor element 40 is connected to the motherboard 1 via the FC-BGA substrate 10, enabling the transmission and reception of electrical signals to and from the outside.

[0025] (Cross-section of a semiconductor package substrate) Next, the cross-sectional structure of the semiconductor package substrate 100 will be described with reference to Figure 3. Figure 3 is a cross-sectional view of the semiconductor package substrate. In Figure 3, the wiring substrate 20 is constructed with a first wiring layer 21 formed on the first surface, which is the upper surface of the core layer 60, and a second wiring layer 22 formed on the second surface of the core layer 60. A semiconductor element 40 is mounted above the first wiring layer 21 via an underfill 86. A cavity 35 is also formed in the core layer 60, and a fine wiring member 50 is placed inside the cavity 35 via a DAF (Die Attach Film) 51. Furthermore, a through electrode 30 is formed that penetrates from the first surface to the second surface of the core layer. The through-electrode 30 penetrates the first and second surfaces of the core layer 60 to make an electrical connection, and the fine wiring member 50 is a wiring member for electrically connecting the semiconductor element 40 and is embedded in the cavity 35.

[0026] As a result, multiple semiconductor elements 40 can be electrically connected via the fine wiring members 50 of the wiring substrate 20 and the first wiring layer 21 of the core layer 60. The fine wiring members 50 are fixed by the insulating resin 85 of the first wiring layer 21 of the core layer 60, in conjunction with the uneven shape of the bottom of the cavity 35, which will be described later.

[0027] (Cross-section of the core layer) Next, the structure of the core layer 60 will be described with reference to Figure 4. Figure 4 is a cross-sectional view of the core layer in the portion where the cavities 35 and through holes 70 are formed. Multiple cavities 35 and through holes 70 are formed in the core layer 60 by laser irradiation and etching, which will be described later. The core layer 60 is a composite material containing at least one of the following: quartz, alkali-free glass, alkali glass, Al2O3, SiO2, CaO, MgO, SrO, BaO, ZrO2, etc. The main physical properties of the core layer 60 are that the coefficient of thermal expansion is in the range of 3 to 10 ppm / °C, and the modulus of elasticity is 40 GPa or higher, preferably around 60 GPa. The composition ratio can be set appropriately. The thickness T1 of the core layer 60 is in the range of 100 to 1,800 μm, preferably in the range of 200 to 1,000 μm. However, the thickness T1 of the core layer 60 is not limited to the above range, and can be set appropriately.

[0028] The depth D1 of the bottomed cavity 35 formed in the core layer 60 is greater than or equal to the thickness T2 of the fine wiring member 50, and at least the relationship between D1 and T2 is D1 > T2 + 5 μm. Also, the relationship between D1 and the thickness T1 of the core layer 60 is T1 > D1. The depth D1 of the cavity 35 can be set appropriately as long as D1 > T2 + 5 μm or greater.

[0029] The relationship between the width W1 and depth W2 of the bottomed cavity 35 formed in the core layer 60 and the w1 and w2 of the fine wiring member 50 is w1+20μm>W1>w1+3μm and w2+20μm>W2>w2+3μm. The width W1 and depth W2 of the cavity 35 can be set appropriately as long as the above conditions are met. If W1>w1+20μm and W2>w2+20μm, a depression will occur in the insulating resin 85 when the first wiring layer 21 is formed on the core layer 60, reducing the reliability of wiring formation and potentially significantly decreasing the yield of the wiring substrate 20.

[0030] (Unevenness at the bottom of the cavity) Next, the irregularities formed at the bottom of the cavity 35 will be described with reference to Figures 5A and 5B. Figure 5A is a diagram illustrating the irregularities at the bottom of the cavity. As shown in Figures 5A and 5B, the bottom of the cavity 35, which has a closed-bottom structure formed in the core layer 60, has minute irregularities, and the roughness is preferably Sa: 500 to 1500 nm. The minute irregularities have a periodic structure, and their period is in the range of 5.0 to 25 μm. The above minute irregularities have the effect of improving adhesion with the Die Attach Film (DAF) used when the fine wiring member 50 is mounted. Below Sa: 500 nm, it becomes difficult to obtain an anchoring effect to improve adhesion. Furthermore, if Sa:1500nm or greater, the unevenness of the bottom surface becomes large, affecting the parallelism when the fine wiring member 50 is mounted. For this reason, the roughness should be Sa:500~1000nm, more preferably in the range of 500~800nm. The roughness can be set appropriately as long as it maintains adhesion and the mountability of the fine wiring member 50. The same applies to the period of the minute unevenness; it can be set appropriately within the range of 5.0~25μm.

[0031] Furthermore, as shown in Figure 5B, the uneven shape at the bottom of the cavity can also be described as a shape with points of height ranging from 0.25 to 10 μm arranged at a period of 5.0 to 25 μm. The bottom of the cavity only needs to satisfy the above-mentioned conditions such as Sa and the shape of the pointed tip.

[0032] (Cavity sidewall) Next, the irregularities formed on the side walls of the cavity 35 will be described with reference to Figure 6. Figure 6(a) is a diagram illustrating the shape of the side walls of the cavity. On the side walls of the bottomed cavity 35 formed in the core layer 60, as shown in Figure 6(a), ridges are formed in the vertical and horizontal directions, with a PV value of 1.2 μm or more and 3.6 μm or less for the ridges, and the depth of the recesses is in the range of 0.5 μm or more and 4.1 μm or less. These multiple longitudinal and transverse ridges form multiple roughly rectangular recesses that can be observed with an optical microscope at a magnification of 50x or more. The spacing between the longitudinal ridges is in the range of 5 μm to 20 μm, and the spacing between the transverse ridges is in the range of 2 μm to 25 μm. Figure 6(b) is an optical microscope image showing the upper part of the side wall of cavity 35 observed from the top surface of cavity 35. The ridges of the side walls of the cavity 35 with the bottom structure described above, and the multiple substantially rectangular recesses, have the effect of fixing the fine wiring member 50 and improving the adhesion between the insulating resin 85 used for the first wiring layer 21 formed on the core layer 60 and the core layer 60.

[0033] Generally, chemical adhesion treatment is used to ensure adhesion between the core layer 60 and the insulating resin 85. However, defects such as delamination at the interface due to stress caused by the difference in the coefficients of thermal expansion of the materials used have been observed. By forming irregularities within the above numerical range on the side walls of the bottomed cavity 35, it becomes possible to create an anchoring effect, thereby ensuring adhesion between the core layer 60 and the insulating resin 85, and thus ensuring the reliability of the wiring board. Figure 6(b) is an optical microscope image of the side wall of cavity 35 viewed from above the z-axis, where fine irregularities can be seen.

[0034] (Angle of the cavity side wall) Next, the inclination angle of the cavity sidewall will be explained with reference to Figure 7. Figure 7 is a cross-sectional view illustrating the inclination angle of the cavity sidewall. In the wiring board 20 according to an embodiment of the present invention, as shown in Figure 7, the inclination angle of the side wall of the bottomed cavity 35 formed in the core board 60 is such that the inclination angle of the side wall from the bottom of the cavity to 40% of the height is in the range of 25 to 60 degrees with respect to the depth D1 of the cavity, and the inclination angle of the side wall above 40% of the height from the bottom of the cavity can be set to the range of 1.5 to 5.0 degrees. The inclination angle of the side wall of the cavity 35 can be derived from the relationship between the depth D1 of the cavity and the opening S1 between the top and bottom of the cavity, as shown in Figure 7. By changing the inclination angle of the side wall of the cavity 35 at the 40% height of the depth D1, it is possible to suppress the creeping up of the DAF when the fine wiring member 50 is mounted. By setting the inclination angle θ1 up to 40% of the cavity depth D1 to a range of 25 degrees or more and 60 degrees or less, it is possible to suppress the upward movement of the DAF when mounting the fine wiring components 50. Furthermore, by setting the inclination angle from a position 40% or more of the cavity depth D1 to a range of 1.5 to 20 degrees, it becomes possible to set the distance to the through-electrode 30 formed on the core substrate 60 to 40 μm or more and 150 μm or less, as shown in Figure 8. If the inclination angle from 40% or more of the cavity depth D1 height of the cavity 35 is set to 20° or more, the distance between the cavity 35 and the through-electrode 30 becomes 150 μm or more, increasing the wiring length on the wiring substrate 20, increasing the overall wiring length of the semiconductor element 40, FC-BGA substrate 10, motherboard 1 and semiconductor package substrate 100, and degrading the transmission characteristics. Therefore, the inclination angle of the cavity sidewalls is such that, with respect to the cavity depth D1, the inclination angle of the sidewalls from the bottom of the cavity up to 40% of the height is in the range of 25 to 60 degrees, and the inclination angle of the sidewalls above 40% of the height from the bottom of the cavity is in the range of 1.5 to 5.0 degrees. Within the above range and while maintaining the relationship θ1 > θ2, the inclination angle of the sidewalls of cavity 35 may be set as appropriate.

[0035] The depth D1 of the bottomed cavity 35 and the inclination angle of the side wall of the cavity were measured by cutting the base material substrate 10A with a scribe to obtain the cross-section (cut surface) of the through hole 70, and then analyzing the SEM (Scanning Electron Microscope) image using image analysis software. Regarding the measurement method of the inclination angle of the side wall of the cavity 35, the distance to the bottom surface of the cavity 35 was defined as D1, the distance to the first surface of the core material was divided into 10 parts, the rising part of the cavity side wall was used as the reference point, and the inclination angle θ was measured at each position from 10% to 100%.

[0036] Next, with reference to Figure 8, the through-holes 70 around the cavity 35 will be described. Figure 8 is a diagram illustrating the positional relationship between the cavity 35 and the through-holes 70, and is a plan view of the core layer as seen from above. As shown in Figure 8, if the inclination angle of the side wall of the cavity 35 is excessive, a wasted area will be generated on the core layer, and the distance from the fine wiring member 50 to the through-electrode 30 formed in the through-hole 70 will increase.

[0037] (Organic resin layer) Next, with reference to Figure 9, the through-electrodes and wiring formed on the surface of the core layer will be described. Figure 9 is a cross-sectional view illustrating the through-electrode 30, the first wiring layer 21, and the second wiring layer 22 formed on the core layer material. In the wiring substrate 20 according to this embodiment, as shown in Figure 9, an organic resin layer 80 is formed at the interface between the core substrate 60 and the first wiring layer 21, the second wiring layer 22, and the through-electrode 30, with a thickness of 100 nm to 10,000 nm. The organic resin layer 80 is formed to cover the microcracks occurring in the core layer 60, and has the effect of inhibiting fracture of the core layer 60 and the propagation of microcracks. Furthermore, it has the effect of ensuring adhesion between the core layer 60 and the conductor layer. The organic resin layer 80 is a resin obtained by mixing at least one of the following: epoxy resin, urethane resin, silicone resin, polyester resin, oxetane resin, and polyamide resin, and is formed by spin coating or immersion treatment. If the thickness of the organic resin layer 80 is 100 nm or less, the effect of covering the microcracks generated in the core layer 60 and suppressing the propagation of microcracks is small. On the other hand, if the thickness is 10,000 nm or more, the generation of stress due to the increased thickness becomes a problem. For this reason, the thickness of the organic resin layer 80 is preferably in the range of 100 nm or more and 10,000 nm or less, and more preferably in the range of 200 nm or more and 800 nm or less. Within the above range, the thickness of the organic resin layer 80 may be set as appropriate.

[0038] Furthermore, the conductor layers used in the core layer 60, the first wiring layer 21, the second wiring layer 22, and the through-electrode 30 can be made of materials such as Cu, Ni, Al, Ti, Cr, Mo, W, Ta, Au, Ir, Ru, Pd, and Pt, but preferably Cu. The thickness of the wiring can be set as desired. For the seed layer for forming the conductor layer, any material that can be formed in the organic resin layer 80 can be selected from materials such as Cu, Ni, Al, Ti, Cr, Mo, W, Ta, Au, Ir, Ru, Pd, and Pt. However, Cu is preferred, and the formation method can be a suitable method from sputtering, electroless plating, CVD treatment, etc.

[0039] The insulating resin 85 formed on the upper surfaces of the first wiring layer 21 and the second wiring layer 22, which are formed on the front and back surfaces of the core layer 60, is preferably a material in which silica, titanium oxide, aluminum oxide, magnesium oxide, or zinc oxide is added as a filler to at least one of the following resins: epoxy resin, urethane resin, silicone resin, polyester resin, oxetane resin, and polyamide resin. It is preferably a thermosetting resin with an elastic modulus in the range of 6 to 15 GPa and a coefficient of thermal expansion in the range of 11 to 30 ppm / Deg.C. Methods for forming the insulating resin layer include spin coating, vacuum pressure pressing, hot pressing, compression molding, and transfer molding. The method for forming the insulating resin layer can be set as appropriate, as long as it allows for the embedding of the fine wiring member 50 mounted in the bottomed cavity 35 of the core layer 60. Preferably, the method is vacuum pressure pressing, and it is desirable to select a processing method that applies heat and pressure simultaneously under vacuum. The processing method is not limited to one, and multiple methods other than those mentioned above may be combined.

[0040] As shown in Figure 3, the semiconductor element connection terminals that electrically connect the semiconductor element 40 and the wiring board 20 have a pillar structure, and the structure can be SnAg / Ni, SnAgCu / Ni, SnCu / Ni, SnAg / Cu / Ni, Au / Pd / Ni, Au / Ni, IT, OPS, etc. The pillars are in the range of Φ10μm to 30μm, and the period is 20 to 50μm. The pillar diameter and pitch can be appropriately set according to the structure of the semiconductor element 40 and the connection terminals.

[0041] Furthermore, the core layer 60 used in the wiring board 20 is made of glass, and the SiO2 ratio of the glass is in the range of 55% by mass or more and 85.0% by mass or less. If the glass composition has an SiO2 ratio of 55% by mass or less, it becomes difficult to form the cavity structure. Also, if the SiO2 ratio is 85.0% by mass or more, the difference in the coefficient of linear expansion between the core layer 60 and the first wiring layer 21 and the second wiring layer 22 becomes large, causing stress, which leads to warping of the wiring board 20, or delamination at the interface between the first wiring layer 21 and the second wiring layer 22 and the core layer 60, and at the interface between the core layer 60 and the fine wiring member 50. Therefore, the SiO2 ratio of the core layer 60 is preferably in the range of 55% by mass or more and 85% by mass or less, and more preferably in the range of 75% by mass or more and 85% by mass or less. Within the above range, the SiO2 ratio of the core layer 60 may be set as appropriate.

[0042] <Second Embodiment> Next, a second embodiment will be described with reference to Figure 10. The second embodiment differs from the first embodiment in that through electrodes are also formed in the region below where the cavity 35 is formed. In the following description, components identical or equivalent to those in the first embodiment described above will be denoted by the same reference numerals, and their descriptions will be simplified or omitted. In the wiring board according to the second embodiment shown in Figure 10, the diameters of the through-electrodes 30 formed in the core layer 60 and the cavity through-electrodes 31 formed below the cavity with a bottomed structure are different. If the processing diameter of the through-electrode 30 that penetrates from the first surface to the second surface of the core layer 60 is Φ1, and the processing diameter of the cavity through-electrode 31 formed in the cavity with a bottomed structure is Φ2, then Φ1 > Φ2. By having the diameter of the through-electrodes Φ1 > Φ2, it becomes possible to miniaturize the connection terminals used when electrically connecting the fine wiring member 50 placed in the cavity 35 to the outside. As a result of the above, in addition to the fine wiring member 50, functional members such as semiconductor elements and capacitors can be mounted in the cavity with a bottomed structure 35, thereby enabling the multi-functionalization of the wiring board 20, i.e., the semiconductor package substrate 100.

[0043] <Third Embodiment> Next, a third embodiment will be described with reference to Figure 11. Figure 11 is a cross-sectional view of a wiring board having cavities and through electrodes of various depths on the same substrate. The cavities and through electrodes described in the first and second embodiments can be formed on the same substrate by changing the length and width dimensions and depth of the cavities, as well as the shape of the through electrodes. The wiring board shown in Figure 3 has a panel size of 510 mm × 515 mm and is a glass panel with a thickness of 0.44 mm, on which cavities with depths of 70 μm and 200 μm are formed simultaneously. Figure 12(a) shows the structure in which a through electrode is formed at the bottom of the cavity as described in the second embodiment, specifically the portion where the cavity depth is 200 μm. Furthermore, Figure 11(b) shows the cavity structure described in the first embodiment, specifically the portion where the cavity depth is formed to 200 μm. Furthermore, Figure 11(c) shows the cavity structure described in the first embodiment, specifically the portion where the cavity depth is 70 μm. The depth of these cavities can be modified locally to control the etching conditions, allowing for the creation of various dimensions and shapes beyond those shown in Figure 11.

[0044] The through-electrode shown in Figure 11(d) is an X-shaped through-electrode with an aperture diameter of 60 μm, and can be formed by etching from both sides of the glass substrate. A characteristic of this shape of through-hole is that the aperture diameter is smallest near the center of the glass panel's thickness. Furthermore, the through-electrode in Figure 11(e) and the bottomed hole in Figure 11(f) are referred to as V-shapes, and the cross-section of the through-hole is V-shaped. Such shapes can be created by masking one side of the glass panel and etching from only that side. When masking one side of the glass panel and etching, it is desirable to divide the glass panel into sections of approximately 100 mm x 100 mm before processing.

[0045] <Method for manufacturing a wiring board in an embodiment of the present invention> A method for manufacturing the wiring board 20 in an embodiment of the present invention will be described below with reference to Figures 12 to 22.

[0046] (Creating the core layer) Figure 12 shows the etching process of the base material substrate 61, which will serve as the base material for the core layer. When the core material is glass, hydrogen fluoride-based or alkali-based etching is performed to adjust the glass thickness. The thickness T1A of the base material substrate 61, which will form the core layer 60, can be appropriately set according to the application, taking into account the reduction in thickness due to the etching process for forming through holes. For example, T1A is in the range of 200 to 1,900 μm, and the reduction in thickness of the base material substrate due to through hole formation T1 can be in the range of 100 to 1,800 μm.

[0047] (Construction of cavities with through holes and bottomed structures) Figure 13 shows the process of forming through holes and laser-modified sections that serve as the starting points for cavities in the core layer 60. Figure 14 shows the structure of the laser-modified section that serves as the starting point for the bottomed cavity 35, and Figure 15 shows the process of removing the through holes 70 and the bottomed cavity 35 by etching to form through holes and cavities. Figure 16 is a diagram illustrating the cross-sectional shape of the through holes 70 formed by etching and the inclination angle of the vias.

[0048] (Laser modification) To form the through-hole 70 and the bottomed cavity 35, one method involves forming a laser-modified section 75 (the starting point for the through-hole 70 and cavity 35, and the planned formation of the through-electrode and cavity) on the base material substrate 61 shown in Figure 12, for example, by laser processing as shown in Figure 13, and then expanding it by etching. For laser processing, if a femtosecond laser or picosecond laser is used, it is preferable to use one of the following wavelengths: 1064 nm, 532 nm, or 355 nm. Alternatively, it is also possible to form the starting point for the through-hole 70 and the bottomed cavity 35 by processing using a CO2 laser or electrical discharge machining. Unlike the through-hole 70, the bottomed cavity 35 is processed by adjusting the height of the laser-modified section 75. To create a two-stage angle on the wall surface of the cavity 35, this can be achieved by processing the laser shots near the outer periphery of the cavity 35 more shallowly than those in the center. For the core layer 60 after laser processing, the core layer 60 is immersed in hydrogen fluoride or a high-concentration alkaline etching solution (e.g., aqueous sodium hydroxide solution, aqueous potassium hydroxide solution) to etch the core layer 60 along the starting point of the through hole 11, thereby forming the through hole 11 and the bottomed cavity 35. Generally, etching proceeds isotropically in the xy plane, and the degree of etching progresses according to the thickness direction (z-axis direction) of the base material substrate 61. Therefore, the cylindrical space formed by the core layer 60 after etching becomes the through hole 70.

[0049] In forming the bottomed cavity 35 described above, when forming the laser-modified portion that serves as the starting point of the cavity by laser processing, the laser-modified portion 75 is formed so that the through-holes 70 after etching overlap, as shown in Figure 14. The high overlap rate indicates that the proportion of the through-holes 11 that overlap with adjacent through-holes is high. Figure 14(a) shows the case where there are two laser-modified portions, and Figure 14(b) shows the case where multiple laser-modified portions are formed to form a bottomed cavity. When forming the bottomed cavity 35, it is desirable to process the laser-modified portion 75 with a period of 5 μm or more and 25 μm or less, and more preferably in the range of 5 μm or more and 10 μm or less. By processing with the above period, the bottom of the bottomed cavity has a Sa: 500 to 3000 nm range, and the minute irregularities are periodic with a pitch of 5 to 25 μm. In the side walls of cavity 35, ridges are formed in the vertical and horizontal directions, with a PV value of 1.8 μm or more and 3.6 μm or less, and a recess depth of 0.5 μm or more and 4.1 μm or less, and the spacing between vertical ridges is in the range of 5 μm to 15.5 μm, and the spacing between horizontal ridges is in the range of 2 μm to 25 μm. The inclination angle of the side walls of cavity 35 is in the range of 25 to 60 degrees for the side walls from the bottom of the cavity up to 40% of the height, relative to the depth D1 of the cavity, and the inclination angle of the side walls above 40% of the height from the bottom of the cavity can be formed in the range of 1.5 to 5.0 degrees.

[0050] (Cross-sectional shape of the through hole) Figure 16 is a magnified cross-sectional view of a through-hole 70 formed in the core layer 60. Figure 16(a) shows a cross-sectional view of the through-hole 70, and Figure 16(b) shows the inclination angle of the through-hole 70. The method for measuring the inclination angle will be described later. The cross-section of the through-hole 70 shown in Figure 16 was obtained by scribing (cutting) the base material substrate 10A in the thickness direction to obtain the cross-section (cut surface) of the through-hole 70, and then analyzing the SEM image observed by an SEM (Scanning Electron Microscope) using image analysis software. As shown in Figure 16, it has an hourglass shape, and the angle of the side of the through-hole 70 is inverted vertically with respect to the 50% position, which is the central part. The shape of the through-hole 70 is not limited to the above shape, and the shape can be appropriately set as long as it penetrates the first surface 60a and the second surface 60b of the core layer 60. The shape of the through-hole 70 is an example of a through-hole that can be obtained by laser processing and etching, and this disclosure is not limited to the above shape.

[0051] The shape of the through-hole 70 shown in Figure 16(a) has a structure that is almost vertically symmetrical at the 50% mark. Regarding the method of measuring the inclination angle of the side surface of the through-hole 70, for the section from 5% to 50% of the distance from the first surface 60a, a center line TC is drawn perpendicular to the first surface 60a at the center of the opening on the first surface 60a side of the core layer 60, as shown in Figure 16(b). Next, as shown by arrow A1, the center line TC is moved parallel to both sides of the through-hole 11 until it contacts the point where the diameter of the through-hole 11 takes its minimum value, and this contact point is taken as the reference point RP. Then, from the reference point RP, tangent lines ss are drawn to the side surfaces corresponding to the positions from 5% to 50% of the mark, and the inclination angle θ of the tangent lines ss is measured, and this inclination angle θ is taken as the inclination angle at each cross-sectional position from 5% to 50%. The inclination angle θ is considered positive in the direction in which the diameter of the through-hole 11 widens upward. Furthermore, for the section from 50% to 95% of the distance from the first surface 10a, the center line TC is moved parallel to the reference point RP, and tangent lines ss are drawn on the sides corresponding to each position from 50% to 95% of the scale. Then, the inclination angle θ of the tangent line ss is measured, and this inclination angle θ is taken as the inclination angle at each cross-sectional position from 50% to 95%. The inclination angle θ is considered negative in the direction in which the diameter of the through hole 11 widens downwards. As shown in Figure 16(b), the tilt angle θ changes in sign at the 50% position, and the absolute value of the tilt angle θ is approximately between 14 and 15 degrees.

[0052] (Formation of through-electrodes) Next, using Figure 17, the process of forming a conductive layer in the through-hole 70 formed in the core layer 60 to form a through-electrode 30 will be explained. To form the through-electrode 30, an organic resin layer 80 is formed on the surface of the core layer 60. The organic resin layer 80 is a resin mixed with at least one of the following: epoxy resin, urethane resin, silicone resin, polyester resin, oxetane resin, and polyamide resin, and is formed by spin coating or immersion treatment. If the thickness of the organic resin layer 80 is 100 nm or less, the effect of following the microcracks generated in the core layer 60 is small, and it becomes difficult to suppress the propagation of microcracks. Also, if the thickness is 10,000 nm or more, the stress due to the increase in thickness becomes large. Therefore, a range of 100 nm or more and 10,000 nm or less is good, and more preferably a range of 200 nm or more and 800 nm. Within the above range, the thickness of the organic resin layer 80 may be set appropriately.

[0053] After forming an organic resin layer 80 on the core layer 60, a seed layer is formed. Examples of materials for the formed metal seed layer include Cu, Ni, Al, Ti, Cr, Mo, W, Ta, Au, Ir, Ru, Pd, and Pt, but Cu is preferred. Examples of the formation method include electroless plating, and the solution composition includes, for example, copper salts such as copper sulfate and copper chloride, Rossel's salt to retain copper ions, EDTA (ethylenediaminetetraacetic acid), and formalin. The solution composition can be appropriately adjusted according to the chemical resistance of the insulating resin used. It is desirable that the thickness of the metal seed layer formed by the electroless plating method be at least 0.3 μm inside the sub-through hole 12. If it is less than 0.3 μm, the coverage of the metal seed layer formed by electroless plating is insufficient, and the conductive layer formed by the electroplating film becomes discontinuous. If the thickness of the metal seed layer formed by electroless plating is 0.3 μm or more, the thickness of the metal seed layer can be appropriately set. Other methods for forming a seed layer besides electroless plating include sputtering. Examples of materials used for seed layer formation by sputtering include Ti and Cu, and the seed layer may consist of at least one metal layer made of these materials. The method for forming the seed layer can be appropriately selected from the above methods.

[0054] (Wiring formation) The core layer 60 on which the seed layer is formed is subjected to photolithography to form a resist pattern, followed by electroplating to form the through-electrode 30, the first wiring layer 21, and the second wiring layer 22. In the resist pattern formation process using photolithography, for example, a dry film resist is laminated, the pattern is drawn by exposure, and then developed. The resist pattern formation process using photolithography is generally carried out using materials used in the wiring formation process of FC-BGA. The resist pattern is peeled off after the electroplating process, and any excess seed layer is removed by etching. In the resist pattern formation process using photolithography, the bottom of the cavity 35, which has a bottomed structure, is protected with the resist pattern as needed. In the electroplating method for the through-hole 70, the through-electrode 30 and wiring formed are made of metals such as Cu, Ni, Al, Ti, Cr, Mo, W, Ta, Au, Ir, Ru, Pd, and Pt, but preferably Cu. The solution composition mainly consists of copper sulfide pentahydrate, sulfuric acid, and chloride ions. To ensure uniformity of the plating film, the through-electrode 30, first wiring 21a1, and second wiring 22b1 are formed using a plating solution with a solution composition containing at least one additive. It is desirable that the thickness of the through-electrode 30, first wiring 21a1, and second wiring 22b1 be at least 2 μm.

[0055] (Mounting of fine wiring components) Next, referring to Figure 18, the process of mounting the fine wiring member 50 into the cavity 35, which has a bottomed structure formed in the core layer 60, will be described. The fine wiring member 50 uses Die Attach Film (DAF) material and is mounted into the cavity from the bottomed structure using Face UP mounting. The thickness of the DAF material used is at least 5 μm and within the range of 30 μm or less. If the thickness of the DAF material is 5 μm or less, it becomes difficult to follow the irregularities at the bottom of the cavity 35, which has a bottomed structure. Also, if the thickness of the DAF material is 30 μm or more, the heat and pressure during mounting will cause the DAF material to creep up onto the sides and top surface of the fine wiring member 50. Therefore, the thickness of the DAF material can be set appropriately within the range of 5 μm or more and 30 μm or less. Furthermore, when mounting the fine wiring components 50, the wiring pattern formed on the core layer 60 can be used as alignment marks to ensure accurate mounting. The alignment marks on the wiring pattern can be arbitrarily shaped. When mounting the fine wiring components 50, it is desirable to use a mounting machine that can set the stage temperature to 80°C or higher, the load to 10N or higher, and the mounting accuracy (average +4σ) ±5μm or less.

[0056] (Formation of an insulating resin layer) Next, the formation of the insulating resin layer will be explained with reference to Figure 19. After mounting the fine wiring member 50 in the cavity 35, which has a bottomed structure of the core layer 60, insulating resin 85 is formed on the front and back surfaces of the core layer 60, as shown in Figure 19. The insulating resin 85 is made by adding silica, titanium oxide, aluminum oxide, magnesium oxide, or zinc oxide as a filler to at least one of the following resins: epoxy resin, urethane resin, silicone resin, polyester resin, oxetane resin, and polyamide resin. The insulating resin 85 is a material with an elastic modulus in the range of 6 to 15 GPa and a coefficient of linear expansion in the range of 11 to 30 ppm / Deg.C, and it is desirable that it be a thermosetting resin.

[0057] Methods for forming the insulating resin layer include spin coating, vacuum press, hot press, compression molding, and transfer molding. The formation method can be set as appropriate, as long as it is possible to embed the fine wiring member 50 mounted in the bottomed cavity 35 of the core layer 60. Preferably, the vacuum press method is used, and it is desirable to select a processing method that applies heat and pressure simultaneously under vacuum. The processing method is not limited to one, and multiple methods other than those mentioned above may be combined. By forming insulating resin 85 on the front and back surfaces of the core layer 60, the fine wiring member 50 is sealed into the cavity 35, which has a bottomed structure.

[0058] (Formation of conductive vias) Next, the formation of conductive vias will be explained with reference to Figure 20. By forming insulating resin 85 on the front and back surfaces of the core layer 60, conductive vias are formed in the insulating resin 85 in order to electrically connect it to the fine wiring member 50 sealed in the cavity 35, which has a bottomed structure. Conductive vias may be formed, for example, by laser via processing using a UV laser or a CO2 laser. If a photosensitive insulating resin material is used for the insulating resin 85, photovias may be formed by photolithography. Any means or method may be selected as appropriate for vias used to electrically connect to the fine wiring component 50. Vias formed in the insulating resin 85 are subjected to a seed layer formation, followed by a pattern formation by photolithography, and then wiring formation. For the seed layer, for example, Cu, Ni, Al, Ti, Cr, Mo, W, Ta, Au, Ir, Ru, Pd, Pt, etc. are formed by electroless plating or sputtering. Similarly, the wiring layer is also formed from Cu, Ni, Al, Ti, Cr, Mo, W, Ta, Au, Ir, Ru, Pd, Pt, etc. The metal material for the seed layer and wiring layer is preferably Cu, and is formed from at least one metal containing Cu.

[0059] (Formation of wiring layers and connection terminals) Next, the formation of the wiring layer and connection terminals will be described with reference to Figure 21. After forming insulating resin 85 and wiring including vias on the front and back surfaces of the core layer 60, wiring is formed multiple times as shown in Figure 21 to form the first wiring layer 21 and the second wiring layer 22. At least one layer of the first wiring layer 21 and the second wiring layer 22 are formed, and the required number of layers are formed. In addition, semiconductor element connection terminals 23 for electrically connecting to the semiconductor element 40 are formed in the first wiring layer 21. The semiconductor element connection terminals 23 have a pillar structure, and the structure can be SnAg / Ni, SnAgCu / Ni, SnCu / Ni, SnAg / Cu / Ni, Au / Pd / Ni, Au / Ni, IT, OPS, etc. The pillar is in the range of Φ10μm to 30μm, and the period is 20 to 50μm. The pillar diameter and pitch may be designed as appropriate according to the structure of the semiconductor element 40 and the connection terminal.

[0060] (Electrical connection with semiconductor elements) Next, the formation of the wiring layer will be explained with reference to Figure 22. After the first wiring layer 21 and the second wiring layer 22 are formed on the front and back surfaces of the core layer 60, an electrical bond is made with the semiconductor element 40 as shown in Figure 22. Examples of bonding methods for the semiconductor element 40 to the wiring substrate 20 include the mount reflow method, in which soldering is performed after heat treatment following mounting of the semiconductor element, and Thermal Compression Bonding (TCB), in which heat and load are applied simultaneously to solder the wiring substrate 20. The bonding method for the semiconductor element 40 and the wiring substrate 20 can be appropriately selected depending on the diameter of the connection terminals and the pitch of the connection terminals of the semiconductor element 40 and the wiring substrate 20. However, if the pitch of the connection terminals is 30 μm or less, it is possible to reduce connection failures between the semiconductor element 40 and the wiring substrate 20 by using Thermal Compression Bonding (TCB).

[0061] (Underfill) Next, we will explain underfill filling with reference to Figure 23. After connecting the semiconductor element 40 and the wiring board 20, as shown in Figure 23, underfill 86 is filled to protect the connection between the semiconductor element 40 and the wiring board 20. For the underfill 86, for example, at least one resin from epoxy resin, urethane resin, silicone resin, polyester resin, oxetane resin, and polyamide resin is used, with silica, titanium dioxide, aluminum oxide, magnesium oxide, or zinc oxide added as a filler, and the underfill is filled into the joint between the semiconductor element 40 and the wiring board 20 by capillary action. There are two methods for filling the underfill 86: filling by capillary action and filling by pre-applying during Thermal Compression Bonding (TCB). When pre-applying during Thermal Compression Bonding (TCB), Non-Conductive Paste (NCP) and Non-Conductive Film (NCF) are used. Both NCP and NCF are intended to protect the joint between the semiconductor element 40 and the wiring board 20, and the composition of the resin material used is the same. Regarding the underfill 86, the materials and methods used may be appropriately determined depending on the method of joining the semiconductor element 40 and the wiring board 20.

[0062] (Resin mold) Next, as shown in Figure 24, the outer periphery of the semiconductor element 40 is protected with a molding resin 87. For the molding resin, for example, at least one of the following resins is used: epoxy resin, urethane resin, silicone resin, polyester resin, oxetane resin, and polyamide resin, to which silica, titanium oxide, aluminum oxide, magnesium oxide, or zinc oxide as a filler is added, and it is formed by a method such as compression molding or transfer molding. After the molding resin 87 is formed, grinding may be performed to reduce the height of the wiring board 20, and it may be ground down to a desired thickness. The amount of grinding may be set appropriately according to the thickness of the wiring board 20.

[0063] (Manufacturing method 1 of the second embodiment) Next, with reference to Figures 25 and 26, a manufacturing method 1 of a second embodiment of the present invention will be described. Figures 25 and 26 illustrate the process of forming a cavity through-hole 71 in a cavity 35 having a bottomed structure. Figure 25 illustrates the process of forming through holes 70 and laser-modified sections 75 that serve as the starting points for cavities 35 in the core layer 60. When forming the modified sections 75 using a femtosecond or picosecond laser, the Z-axis of the laser is controlled to control the depth of the laser-modified sections 75, and simultaneously the through holes 70 and the laser-modified sections 75 that serve as the starting points for cavities 35 are formed. In the second embodiment as well, in order to create a two-stage angle on the wall surface of the cavity 35, the laser shots on the outermost periphery of the cavity 35 are processed more shallowly compared to those on the center. Subsequently, as shown in Figure 26, etching is performed to form cavity through-holes 71 within the cavity 35, which consists of the core layer 60 and the closed-bottom structure. Because the laser-modified portion 75 is exposed to the etching solution for different amounts of time, the opening diameters of the cavity through-holes 70 and the cavity through-holes 71 formed within the cavity 35, which consists of the core layer 60 and the closed-bottom structure, are greater for through-holes 70 than for cavity through-holes 71.

[0064] (Manufacturing method 2 of the second embodiment) Next, with reference to Figures 27 and 28, the manufacturing method 2 of the second embodiment will be described. Figure 27 is a diagram illustrating the process of forming through holes 70 and a cavity 35 with a bottom structure in the core layer 60 by laser processing and etching, and then forming a laser-modified portion 75 in the cavity 35 with a bottom structure by laser processing. Figure 28 is a diagram illustrating the process of etching the laser-modified portion 75 formed in the cavity 35 with a bottom structure in Figure 27 to form a cavity through hole 71.

[0065] <Effects and Actions> The manufacturing methods 1 and 2 according to the second embodiment described above describe the step of forming a cavity through-hole 71 in a cavity 35 having a bottomed structure, and the steps before and after are the same as those of the manufacturing method according to the first embodiment.

[0066] The following describes the details of the examples and comparative examples in the embodiments, using the examples and comparative examples provided below. Note that the examples shown below are merely examples of embodiments of the present invention, and the present invention is not limited to these examples.

[0067] <Examples and Comparative Examples of the Invention> For the examples and comparative examples, a cavity 35 with a closed bottom structure was formed in the core material of the wiring board 20, various processes were carried out, and temperature cycle tests were performed. Table 1 shows the manufacturing conditions and the shape of the cavity 35 with a closed bottom structure for the examples and comparative examples. In Examples 1 to 5, the processing pitch of the laser-modified section was varied, and processing was carried out so that the roughness of the bottom and sides of the cavity 35 with a closed bottom structure formed by etching was changed. In Comparative Example 1, the laser processing pitch was set to a larger value compared to Examples 1 to 5, and a cavity with a closed bottom structure was formed by etching. In Comparative Example 2, a resist pattern was formed on the core material by photolithography, and a cavity 35 with a closed bottom structure was formed by etching. The Sa, PV, and unevenness period of the cavity bottom were measured in the range of 174 × 174 μm using a white light interferometer (Zygo NeX View NX2). As shown in Table 1, the results indicate that as the laser processing pitch increases, the Sa, PV, and unevenness period of the bottom surface of cavity 35, as well as the PV and edge spacing of the sides, increase. Regarding the mountability of the fine wiring component 50, while the thickness of the DAF material used for the component is 15 μm, in Comparative Example 1 the average PV at the bottom of the cavity is 15,000 nm or more, which can be judged as reducing the mountability. Similarly, in the reliability evaluation in the temperature cycle test, the average PV at the bottom is 15,000 nm or more, making it difficult for the DAF to maintain bonding, and thus reducing reliability. In Comparative Example 2, where a resist pattern was formed on the core material by photolithography and etched, the bottom and sides are smooth, but the distance between adjacent through holes is set wide, and in the reliability evaluation in the temperature cycle test, delamination of the component was confirmed, resulting in a failure. [Table 1]

[0068] Next, Table 2 shows the results of changing the inclination angle of the side wall of the cavity 35 by changing the etching rate of the etching solution. Table 2 shows the results of evaluating the transmission characteristics with the fine wiring member 50 mounted on the cavity 35 after performing each mounting process. Examples 6 to 11 are processed in such a way that the etching rate is changed, the inclination angle of the side wall of the cavity 35 is changed, and the distance between the cavity 35 and the through electrode 30 is changed. Comparative Example 3 shows the same processing conditions as Example 6, but with a higher inclination angle of the cavity side wall, θ1 ≈ θ2. Comparative Example 4 shows the same processing as Comparative Example 2 described above. Regarding the transmission characteristics shown in Table 2, the fine wiring components and the through-electrode 30 are connected by forming fine wiring with Line & Space = 5 / 5 μm using the Semi Additive Process (SAP) method. As shown in Table 2, the mounting of the fine wiring member 50 is good in Examples 6 to 11, but as shown in Comparative Example 3, when the cavity tilt angle is θ1 ≈ θ2, DAF creep is observed, and the mounting of the member having the fine wiring layer is unacceptable. To measure transmission characteristics, the S-parameter (S21), which indicates the frequency dependence of the degree of propagation relative to the input wave, is used. S21 is expressed as the logarithm of the power ratio (transmitted wave power / input wave power), and a smaller absolute value indicates lower transmission loss. A network analyzer was used to measure the S-parameter (S21). Note that for transmission characteristic evaluation, S21 values ​​below -3.0 dB are considered unsuitable. As shown in Table 2, in Examples 6 to 11, the distance between the cavity 35 and the through-electrode 30 can be set within the range of 20 to 150 μm, and the transmission characteristic S21 is -3.0 dB or less. In Comparative Example 1, it is difficult to have the cavity 35 and the through-electrode 30 adjacent, and the transmission characteristic S21 is -3.0 dB or more. [Table 2]

[0069] Next, Table 3 shows the results of evaluating the adhesion between the core material, through-electrode, and metal wiring layer with and without an organic resin layer. In Examples 12 to 15, the thickness of the organic resin layer was varied, a seed layer was formed using electroless plating and a sputter seed layer, followed by electroplating, and the adhesion was evaluated by a peel test. Comparative Example 5 shows the evaluation without the formation of an organic resin layer. A peel strength of 0.3 kN / m or higher was considered acceptable. As shown in Table 3, in each example where an organic resin layer was formed, it was confirmed that both electroless plating and sputter seeding layers obtained high peel strength. Furthermore, from the results of the comparative example, it was confirmed that without the organic resin layer, the peel strength was 0.3 kN / m or less. [Table 3]

[0070] Table 4 shows the yield of component mounting, substrate warpage, and reliability evaluation results in temperature cycling tests for Example 16, which is an embodiment of the present invention, and for Comparative Examples 6 and 7. In the evaluations shown in Table 4, a 100 × 100 mm substrate was fabricated and evaluated with the structure shown in Figure 2(a). In Comparative Example 6, a resist pattern was formed on the core material by photolithography, similar to Comparative Example 1 shown in Table 2, and a cavity 35 consisting of a bottomed structure was formed. In Comparative Example 7, the substrate was fabricated and evaluated with the same specifications as in Prior Art 1: Patent No. 6665375. <Temperature Cycle Test> The test conditions involve a change from -55°C to RT (room temperature) and then to 125°C, with each temperature being held for 30 minutes, and this process is repeated up to 1000 times. Observation method: Resistance measurement (Judgment criteria: Resistance change rate of 10% or less compared to the initial value) Observation of blistering on the substrate (If blistering occurs, the blistered area is evaluated using a cross-sectional view and ultrasonic flaw detection device). As shown in Table 4, using glass as the core material makes it possible to suppress warping of the substrate compared to Comparative Example 7. In reliability evaluation by temperature cycling test, Comparative Example 6 failed at 700 cycles, while Example 16, which is an embodiment of the present invention, was confirmed to be problem-free up to 1000 cycles in the temperature cycling test. [Table 4]

[0071] <Effects and Actions> By adjusting the roughness of the bottom and sides of the cavity 35, which has a bottomed structure, on the core layer 60, it is possible to improve the adhesion with the components mounted in the cavity 35. Furthermore, by adjusting the inclination angle of the sides, it is possible to ensure transmission characteristics by making the distance to the through-electrode 30 adjacent. In addition, adhesion can be obtained by forming an organic resin layer at the interface between the core layer 60, the through-electrode 30, and the metal wiring. Thus, according to the embodiment of the present invention, the semiconductor package substrate 100 using the wiring substrate 20 can be made highly reliable. According to embodiments of the present invention, as well as the manufacturing method and examples of the embodiments of the present invention, it is possible to provide a wiring board and a method for manufacturing a wiring board that can suppress warping and have high reliability.

[0072] Although embodiments of the present invention have been described above, the present invention is not limited to the embodiments described above, and various modifications are possible without departing from the spirit of the present invention. This disclosure includes the following aspects:

[0073] <Other Embodiments> This disclosure also includes the following aspects: (Aspect 1) A wiring board on which at least one semiconductor element is mounted, The aforementioned wiring board has a core layer, A wiring layer is arranged on the first and second surfaces of the core layer. The core layer is provided with at least one through-electrode that penetrates from the first surface to the second surface, At least one bottomed cavity is formed on the surface on which the semiconductor elements of the core layer are mounted. The cavity is equipped with a fine wiring component. The inclination angle of the side wall of the cavity is, With respect to the depth D1 of the cavity, the inclination angle θ1 of the side wall from the bottom of the cavity up to 40% of its height is in the range of 25 to 60 degrees. The inclination angle θ2 of the side walls, which are more than 40% in height from the bottom of the cavity, is in the range of 1.5 degrees to 5.0 degrees. A wiring board characterized by the following features.

[0074] (Aspect 2) At the bottom of the cavity, irregularities with a roughness of Sa: 500 to 1,500 nm are periodically formed at a pitch of 5.0 to 15.5 μm. A wiring board according to embodiment 1, characterized by the features described herein.

[0075] (Aspect 3) At the bottom of the cavity, there are irregularities formed by pointed surfaces with a height of 0.25 to 10 μm and a periodicity of 5.0 to 25 μm in the horizontal direction. A wiring board according to embodiment 1 or 2, characterized by the features described herein.

[0076] (Aspect 4) The side walls of the cavity have ridges formed in the longitudinal and transverse directions, with a ridge PV value of 1.2 μm or more and 3.6 μm or less, and the depth of the recess is 0.5 μm or more and 4.1 μm or less. A wiring board according to any one of embodiments 1 to 3, characterized in that way.

[0077] (Appendix 5) Multiple substantially rectangular recesses are formed on the side walls of the cavity by multiple vertical and horizontal ridges. The spacing between longitudinal ridges is 5 μm to 15.5 μm, and the spacing between transverse ridges is 2 μm to 25 μm. A wiring board according to any one of embodiments 1 to 4, characterized in that it is a wiring board.

[0078] (Aspect 6) The distance between the cavity and the nearest through-electrode is between 20 μm and 150 μm. A wiring board according to any one of embodiments 1 to 5, characterized in that it is a wiring board.

[0079] (Aspect 7) An organic resin layer of at least 100 nm to 5,000 nm is formed at the interface between the core layer and the wiring layer, and at the interface between the core layer and the through electrode. A wiring board according to any one of embodiments 1 to 6, characterized by the features described herein.

[0080] (Pattern 8) The material of the core layer is The glass has an SiO2 ratio of 55% by mass or more and 85% by mass or less. A wiring board according to any one of embodiments 1 to 7, characterized by the features described herein.

[0081] (Aspect 9) The core layer has cavities of varying depths. A wiring board according to any one of embodiments 1 to 8, characterized in that it is a wiring board.

[0082] (Aspect 10) A method for manufacturing a wiring substrate, comprising a wiring substrate on which at least one semiconductor element is mounted, wherein the wiring substrate has a first surface and a second surface, and is provided with at least one through-electrode penetrating from the first surface to the second surface, and the first surface, which is the surface on which the semiconductor element is mounted, has at least one bottomed cavity structure in the core material of the wiring substrate, and a member on which a fine wiring layer is formed is embedded in the core material of the wiring substrate, The process involves irradiating the core material of a wiring board with a laser near the outer edge of the cavity, shallower than the center, onto the areas where through-electrodes are to be formed and areas where a bottomed cavity is to be formed, thereby etching the laser-irradiated areas and forming through-holes and bottomed cavities. The process involves forming a seed layer in a core material having through holes and a bottomed cavity, forming a resist pattern, and then forming a wiring layer by electroplating. A process of placing a component with a fine wiring layer formed in a bottomed cavity, A process of forming insulating resin layers on the first and second surfaces of a core material and a component having a fine wiring layer arranged in a bottomed cavity, The first and second surfaces involve the process of forming at least two or more wiring layers, and the process of separating the wiring board into individual pieces. A method for manufacturing a multilayer wiring board having the following characteristics.

[0083] (Aspect 11) In the process of irradiating the core material of the aforementioned wiring board with a laser in the area where through electrodes are to be formed and the area where a bottomed cavity is to be formed, In the area where through-electrode formation is planned, laser irradiation is performed perpendicular to the core material to modify the entire core material in the thickness direction. A method for manufacturing a wiring board according to embodiment 10, characterized in that, in the area where a bottomed cavity is to be formed, laser irradiation is performed perpendicular to the core material to partially modify the core material in the thickness direction. (Aspect 12) In the process of placing a member having a fine wiring layer formed in the bottomed cavity, The method for manufacturing a wiring board according to embodiment 10 or embodiment 11, characterized in that the member is mounted in the bottomed cavity using DAF material. (Aspect 13) A method for manufacturing a wiring board according to any one of embodiments 10 to 12, characterized in that the thickness of the DAF material is in the range of 5 μm or more and 30 μm or less. [Explanation of symbols]

[0084] 1: Motherboard 10: FC-BGA 20: Wiring board 21: First wiring layer 22:Second wiring layer 23: Terminals for connecting semiconductor devices 30:Through electrode 31: Through-cavity electrode 35: Cavity 40: Semiconductor devices 50: Fine wiring components 51:DAF 60: Core Layer 60a: Front page 60b:Second side 61: Base material substrate 70: Through hole 71: Cavity through-hole 75: Laser modification section 80: Organic resin layer (primer layer) 85: Insulating resin 86: Underfill 87: Molding resin 100: Semiconductor package substrate T1: Core board thickness T2: Thickness of the component having a fine wiring layer D1: Cavity depth W1: Cavity width W2: Cavity depth w1: Fine width with fine wiring layer w2: Depth of the component having a fine wiring layer S1: Difference in opening between the top and bottom of the cavity θ: Cavity angle CB: Cavity bottom TC: TGV centerline SS: TGV tangent

Claims

1. A wiring board on which at least one semiconductor element is mounted, The aforementioned wiring board has a core layer, A wiring layer is arranged on the first and second surfaces of the core layer. The core layer is provided with at least one through-electrode that penetrates from the first surface to the second surface, At least one bottomed cavity is formed on the surface on which the semiconductor elements of the core layer are mounted. The cavity is equipped with a fine wiring component. The inclination angle of the side wall of the cavity is, With respect to the depth D1 of the cavity, the inclination angle θ1 of the side wall from the bottom of the cavity up to 40% of its height is in the range of 25 to 60 degrees. The inclination angle θ2 of the side walls, which are more than 40% in height from the bottom of the cavity, is in the range of 1.5 degrees to 5.0 degrees. A wiring board characterized by the following features.

2. At the bottom of the cavity, irregularities with a roughness of Sa greater than 500 nm and less than 1,500 nm are periodically formed at a pitch of 5.0 to 15.5 μm. The wiring board according to feature 1.

3. At the bottom of the cavity, there are irregularities formed by pointed surfaces with a height of 0.25 to 10 μm and a period of 5.0 to 25 μm in the horizontal direction. The wiring board according to feature 1.

4. The side walls of the cavity have ridges formed in the longitudinal and transverse directions, with a ridge PV value of 1.2 μm or more and 3.6 μm or less, and the depth of the recess is 0.5 μm or more and 4.1 μm or less. A wiring board according to any one of claims 1 to 3, characterized in that...

5. Multiple substantially rectangular recesses are formed on the side walls of the cavity by multiple vertical and horizontal ridges. The spacing between longitudinal ridges is 5 μm to 15.5 μm, and the spacing between transverse ridges is 2 μm to 25 μm. A wiring board according to any one of claims 1 to 3.

6. The distance between the cavity and the nearest through-electrode is in the range of 20 μm or more and less than 150 μm. A wiring board according to any one of claims 1 to 3.

7. At least an organic resin layer greater than 100 nm and less than or equal to 5,000 nm is formed at the interface between the core layer and the wiring layer, and at the interface between the core layer and the through electrode. A wiring board according to any one of claims 1 to 3.

8. The material of the core layer is SiO ２ This glass has a ratio greater than 55% by mass and less than 85% by mass. A wiring board according to any one of claims 1 to 3, characterized in that it is a wiring board.

9. The core layer has cavities of varying depths. A wiring board according to any one of claims 1 to 3.

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