Photoelectric conversion circuit and optical line sensor

Abstract

In a photoelectric conversion circuit, the linearity of the output voltage with respect to the amount of incident light is improved. [Solution] The photoelectric conversion circuit is The device includes a photoelectric conversion element, an output transistor connected to the photoelectric conversion element and outputting a voltage corresponding to the amount of light incident on the photoelectric conversion element, a current control transistor that controls the current flowing through the output transistor, a capacitor connected between the gate and drain of the output transistor, a first switch connected in parallel with the capacitor, a bias circuit that outputs a bias voltage, and a second switch provided between the output terminal of the bias circuit and the gate of the output transistor.

Description

[Technical Field]

[0001] The disclosed technology relates to a photoelectric conversion circuit and an optical line sensor. [Background technology]

[0002] The following technologies are known as technologies related to photoelectric conversion circuits. For example, Patent Document 1 describes a photoelectric conversion circuit equipped with a photodetector, an output transistor, a capacitor, a reset switch element, a constant current element, a constant potential difference element, and an output terminal. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2019-198026 [Overview of the project] [Problems that the invention aims to solve]

[0004] A photoelectric conversion circuit has the function of converting the photocurrent generated when light is incident on a photoelectric conversion element such as a photodiode into a voltage and outputting it. Preferably, the output voltage of the photoelectric conversion circuit is linear with respect to the amount of light incident on the photoelectric conversion element, that is, the output voltage is precisely proportional to the amount of incident light.

[0005] The disclosed technology aims to improve the linearity of the output voltage with respect to the amount of incident light in a photoelectric conversion circuit. [Means for solving the problem]

[0006] The photoelectric conversion circuit according to the disclosed technology includes a photoelectric conversion element, an output transistor connected to the photoelectric conversion element and outputting a voltage corresponding to the amount of light incident on the photoelectric conversion element, a current control transistor for controlling the current flowing through the output transistor, a capacitor connected between the gate and drain of the output transistor, a first switch connected in parallel with the capacitor, a bias circuit for outputting a bias voltage, and a second switch provided between the output end of the bias circuit and the gate of the output transistor.

[0007] Before light is incident on the photoelectric conversion element and after the first switch transitions from the on state to the off state, the second switch may transition from the off state to the on state.

[0008] The output transistor may be an n-channel type MOSFET. The current control transistor may be a p-channel type MOSFET provided on the higher potential side than the output transistor. The photoelectric conversion element may be a photodiode. The cathode of the photodiode may be connected to the gate of the output transistor.

[0009] The output transistor may be a p-channel type MOSFET. The current control transistor may be an n-channel type MOSFET provided on the lower potential side than the output transistor. The photoelectric conversion element may be a photodiode. The anode of the photodiode may be connected to the gate of the output transistor.

[0010] The optical line sensor according to the disclosed technology includes a plurality of the above photoelectric conversion circuits connected in parallel between a high potential side power line and a low potential side power line.

Advantages of the Invention

[0011] According to the disclosed technology, in the photoelectric conversion circuit, it is possible to improve the linearity of the output voltage with respect to the incident light amount.

Brief Description of the Drawings

[0012] [Figure 1] This is a circuit diagram showing an example of the configuration of a photoelectric conversion circuit according to an embodiment of the disclosed technology. [Figure 2] This is a circuit diagram showing an example of the configuration of a bias circuit according to an embodiment of the disclosed technology. [Figure 3] This is a timing chart showing an example of the time progression of the state of the first and second switches and the potential of the output voltage according to an embodiment of the disclosed technology. [Figure 4] This graph shows an example of the relationship between the amount of light incident on a photoelectric conversion element according to an embodiment of the disclosed technology and the output voltage. [Figure 5] Figure 4 shows a graph illustrating an example of the relationship between incident light intensity and output voltage for each of the three ranges indicated. [Figure 6] Figure 4 shows a graph illustrating an example of the deviation rate from the approximate straight line for the relationship between incident light intensity and output voltage for each of the three ranges shown. [Figure 7] This graph shows an example of the relationship between incident light intensity and output voltage, obtained with and without bias voltage application. [Figure 8] This graph shows an example of the deviation rate from an approximate straight line between the relationship between incident light quantity and output voltage, both when a bias voltage is applied and when it is not. [Figure 9] This is a circuit diagram showing an example of the configuration of a photoelectric conversion circuit according to another embodiment of the disclosed technology. [Figure 10] This is a circuit block diagram showing an example of the configuration of an optical line sensor according to an embodiment of the disclosed technology. [Figure 11] This is a circuit block diagram showing an example of the configuration of an optical line sensor according to another embodiment of the disclosed technology. [Modes for carrying out the invention]

[0013] The embodiments of the disclosed technology will be described below with reference to the drawings. In each drawing, substantially identical or equivalent components or parts are given the same reference numerals.

[0014] [First Embodiment] Figure 1 is a circuit diagram showing an example of the configuration of a photoelectric conversion circuit 1 according to an embodiment of the disclosed technology. The photoelectric conversion circuit 1 includes a photoelectric conversion element 10, an output transistor 20, a capacitor 30, a first switch 40, a current control transistor 50, a second switch 70, and a bias circuit 80.

[0015] The photoelectric conversion element 10 is an element that generates a photocurrent in proportion to the amount of incident light. The photoelectric conversion element 10 may be, for example, a photodiode. In the photodiode that constitutes the photoelectric conversion element 10, the anode is connected to the low-potential power line VSS, and the cathode is connected to the gate of the output transistor 20.

[0016] The output transistor 20 is an n-channel MOSFET (Metal Oxide Semiconductor Field-Effect Transistor). The gate of the output transistor 20 is connected to the cathode of the photodiode constituting the photoelectric conversion element 10, the source is connected to the low-potential power supply line VSS, and the drain is connected to the output terminal 60 of the photoelectric conversion circuit 1. The node of the drain of the output transistor 20 is denoted as node n1, and the node of the gate of the output transistor 20 is denoted as node n2.

[0017] Capacitor 30 has one end connected to node n1 and the other end connected to node n2. That is, capacitor 30 is connected between the gate and drain of output transistor 20. When the first switch 40 is turned on, it discharges the charge stored in capacitor 30. This resets the state of photoelectric conversion circuit 1. The first switch 40 is, for example, an n-channel MOSFET, with its drain connected to node n1 and its source connected to node n2, and a control signal that controls the on / off state of the first switch 40 is input to its gate.

[0018] The current control transistor 50 controls the current flowing through the output transistor 20. The current control transistor 50 is a p-channel type MOSFET located at a higher potential than the output transistor 20, with its source connected to the high-potential power line VDD and its drain connected to node n1. The gate of the current control transistor 50 is connected to a bias voltage V bias1 A current is input. A current control transistor 50 supplies a current of a constant magnitude to the output transistor 20. The current control transistor 50 may also constitute a current mirror circuit.

[0019] The bias circuit 80 provides a constant level of bias voltage V baias2 It outputs. Figure 2 is a circuit diagram showing an example of the configuration of the bias circuit 80. The bias circuit 80 may be composed of a resistive voltage divider circuit including resistive elements 81 and 82, which is provided between the high-potential power line VDD and the low-potential power line VSS. The resistive element 82 may be a variable resistor. Bias voltage V baias2 The level is set to a level slightly lower (for example, about 1mV lower) than the potential at node n2 when the second switch 70 is in the OFF state and the first switch 40 is in the ON state.

[0020] The second switch 70 has one end connected to the output terminal of the bias circuit 80 and the other end connected to the gate (node ​​n2) of the output transistor 20. When the second switch 70 is turned ON, the bias voltage V is output from the bias circuit 80. baias2 This is applied to the gate (node ​​n2) of the output transistor 20. The on / off switching of the first switch 40 and the second switch 70 is controlled by a control circuit (not shown).

[0021] The basic photoelectric conversion operation of the photoelectric conversion circuit 1 is described below. Before light enters the photoelectric conversion element 10, the first switch 40 is controlled to the ON state. This discharges the charge stored in the capacitor 30, resetting the state of the photoelectric conversion circuit 1. Subsequently, the first switch 40 is controlled to the OFF state. At this time, the potential of the drain (node ​​n1) of the output transistor 20 is set to a potential that naturally balances.

[0022] Subsequently, when light is incident on the photoelectric conversion element 10, the photoelectric conversion element 10 generates a photocurrent. This photocurrent causes the potential of the gate (node ​​n2) of the output transistor 20 to decrease. As a result, the impedance of the output transistor 20 increases. In other words, the output transistor 20 behaves like a variable resistor whose resistance changes in response to the photocurrent. When the impedance of the output transistor 20 increases, the output voltage V is output from the output terminal 60 connected to the drain (node ​​n1) of the output transistor 20. OUT The output voltage V will increase. OUT This value changes depending on the amount of light incident on the photoelectric conversion element 10.

[0023] Figure 3 shows the state of the first switch 40 and the second switch 70 and the output voltage V OUT This is a timing chart showing an example of the time evolution of the potential at node n2. In Figure 3, the case where the second switch 70 is not turned on (i.e., the bias voltage V to node n2) baias2 The area where no application is present is indicated by a dotted line.

[0024] The first switch 40 is turned on for a certain period before light is incident on the photoelectric conversion element 10. As a result, the charges accumulated in the capacitor 30 are discharged, and the state of the photoelectric conversion circuit 1 is reset. The second switch 70 is turned on before light is incident on the photoelectric conversion element 10 and after the first switch 40 transitions from the on state to the off state. When the second switch 70 is turned on, the bias voltage V baias2 output from the bias circuit 80 is applied to the gate (node n2) of the output transistor 20. As a result, the level of the output voltage V OUT (node n1) rises. After the second switch 70 transitions to the off state, light is incident on the photoelectric conversion element 10. The potential of the output voltage V OUT (node n1) rises as the amount of incident light increases starting from the level that rose with the application of the bias voltage V baias2 .

[0025] FIG. 4 is a graph showing an example of the relationship between the amount of light E (hereinafter referred to as the incident light amount E) incident on the photoelectric conversion element 10 and the output voltage V OUT . FIG. 5 is a graph showing an example of the relationship between the incident light amount E and the output voltage V OUT for each of the three ranges R1, R2, and R3 shown in FIG. 4. FIG. 6 is a graph showing an example of the deviation rate of the relationship between the incident light amount E and the output voltage V OUT for each of the three ranges R1, R2, and R3 shown in FIG. 4 with respect to an approximate straight line. In FIG. 6, the smaller the absolute value of the deviation rate, the higher the linearity of the output voltage V OUT with respect to the incident light amount E.

[0026] As shown in FIGS. 4 to 6, the linearity of the output voltage V OUT with respect to the incident light amount E is highest in the range R3, second highest in the range R2, and lowest in the range R1. Thus, the linearity of the output voltage V OUT with respect to the incident light amount E changes according to the range of the output voltage V OUT . This means that the output voltage V OUTThe linearity of the output voltage with respect to the incident light intensity E means that it changes depending on the setting of the operating point of the output transistor 20. For example, by operating the output transistor 20 in the region of range R3, the output voltage V OUT It is possible to improve the linearity with respect to the incident light intensity E.

[0027] The operating point of the output transistor 20 can be set by setting the potential of the drain (node ​​n1) of the output transistor 20 after reset (after the capacitor 30 has discharged and the amount of incident light is zero). The potential of the drain (node ​​n1) of the output transistor 20 after reset is the potential that balances when the first switch 40 is turned ON to discharge the charge stored in the capacitor 30, and then the first switch 40 is turned OFF.

[0028] Before light is incident on the photoelectric conversion element 10, and after the first switch 40 has transitioned from the ON state to the OFF state, the second switch 70 can be switched from the OFF state to the ON state, thereby increasing the potential of the drain (node ​​n1) of the output transistor 20 after the reset. This increases the output voltage V OUT This makes it possible to operate the output transistor 20 in a region where the linearity with respect to the incident light intensity E is relatively high.

[0029] Figure 7 shows the bias voltage V to node n2. baias2 The incident light quantity E and output voltage V were obtained for both the case with and without the application of the light (comparative example). OUT This graph shows an example of the relationship between the two.

[0030] Figure 8 shows the bias voltage V to node n2. baias2 The incident light quantity E and output voltage V for the case where the light was applied and the case where it was not applied (comparative example). OUT This graph shows an example of the deviation rate from the approximate straight line in relation to the given value. As shown in Figures 7 and 8, the bias voltage V to node n2 baias2 When the bias voltage V to node n2 is applied, baias2Compared to the case where no voltage is applied, the output voltage V OUT It was confirmed that the linearity with respect to the incident light intensity E is high.

[0031] Bias voltage V applied to node n2 baias2 The lower the level of the output transistor, the higher the potential of the drain (node ​​n1) of the output transistor 20 after reset, and the operating point of the output transistor 20 can be raised to the output voltage V. OUT It is possible to include the region where the linearity with respect to the incident light intensity E is relatively high (for example, the range R3 shown in Figure 4). Bias voltage V baias2 If the level is set too low, the output of output transistor 20 may saturate. Therefore, the bias voltage V baias2 It is preferable to set the level to a level slightly lower (for example, about 1 mV lower) than the potential of node n2 when the second switch 70 is in the off state and the first switch 40 is in the on state.

[0032] As described above, the photoelectric conversion circuit 1 according to the embodiment of the disclosed technology makes it possible to improve the linearity of the output voltage with respect to the amount of light incident on the photoelectric conversion element 10.

[0033] [Second Embodiment] Figure 9 is a circuit diagram showing an example of the configuration of a photoelectric conversion circuit 1A according to a second embodiment of the disclosed technology. In contrast to the photoelectric conversion circuit 1 according to the first embodiment described above, the output transistor 20 is configured with an n-channel type MOSFET located on the low-potential side, whereas the photoelectric conversion circuit 1A according to the second embodiment is configured with a p-channel type MOSFET located on the high-potential side.

[0034] The output transistor 20, which is composed of a p-channel MOSFET, has its gate connected to the anode of the photodiode constituting the photoelectric conversion element 10, its source connected to the high-potential power supply line VDD, and its drain connected to the output terminal 60 of the photoelectric conversion circuit 1A. The node of the drain of the output transistor 20 is denoted as node n1, and the node of the gate of the output transistor 20 is denoted as node n2. The photodiode constituting the photoelectric conversion element 10 has its cathode connected to the high-potential power supply line VDD, and its anode connected to the gate of the output transistor 20.

[0035] Capacitor 30 has one end connected to node n1 and the other end connected to node n2. That is, capacitor 30 is connected between the gate and drain of output transistor 20. When the first switch 40 is turned on, it discharges the charge stored in capacitor 30. This resets the state of photoelectric conversion circuit 1A. The first switch 40 is, for example, a p-channel type MOSFET, with its drain connected to node n1 and its source connected to node n2, and a control signal that controls the on / off state of the first switch 40 is input to its gate.

[0036] The current control transistor 50 controls the current flowing through the output transistor 20. The current control transistor 50 is an n-channel MOSFET located at a lower potential than the output transistor 20, with its source connected to the low-potential power line VSS and its drain connected to node n1. The gate of the current control transistor 50 is connected to a bias voltage V bias1 A current is input. A current control transistor 50 supplies a current of a constant magnitude to the output transistor 20. The current control transistor 50 may also constitute a current mirror circuit.

[0037] The bias circuit 80 provides a constant level of bias voltage V baias2The bias circuit 80 may be composed of a resistive voltage divider circuit including resistive elements 81 and 82 as illustrated in Figure 2. The resistive element 82 may be a variable resistor. Bias voltage V baias2 It is preferable to set the level to a level slightly higher (for example, about 1 mV higher) than the potential of node n2 when the second switch 70 is in the OFF state and the first switch 40 is in the ON state.

[0038] The second switch 70 has one end connected to the output terminal of the bias circuit 80 and the other end connected to the gate (node ​​n2) of the output transistor 20. When the second switch 70 is turned ON, the bias voltage V is output from the bias circuit 80. baias2 This is applied to the gate (node ​​n2) of the output transistor 20. The on / off switching of the first switch 40 and the second switch 70 is controlled by a control circuit (not shown).

[0039] In the photoelectric conversion circuit 1A, the photocurrent generated by the photoelectric conversion element 10 causes the potential of the gate (node ​​n2) of the output transistor 20 to increase. This increases the impedance of the output transistor 20. In other words, the output transistor 20 behaves like a variable resistor whose resistance changes according to the photocurrent. When the impedance of the output transistor 20 increases, the output voltage V is output from the output terminal 60 connected to the drain (node ​​n1) of the output transistor 20. OUT The output voltage V becomes lower. OUT This value changes depending on the amount of light incident on the photoelectric conversion element 10.

[0040] The first switch 40 is kept ON for a certain period before light is incident on the photoelectric conversion element 10. This discharges the charge stored in the capacitor 30 and resets the state of the photoelectric conversion circuit 1. The second switch 70 is switched ON from the OFF state before light is incident on the photoelectric conversion element 10 and after the first switch 40 has switched from the ON state to the OFF state. When the second switch 70 is ON, the bias voltage V output from the bias circuit 80 is activated. baias2This is applied to the gate (node ​​n2) of the output transistor 20. As a result, the output voltage V OUT The level of (node ​​n1) decreases. After the second switch 70 is switched to the off state, light is incident on the photoelectric conversion element 10. Output voltage V OUT The potential of (node ​​n1) is the bias voltage V baias2 Starting from the level that drops upon application, the level decreases in accordance with the increase in the amount of incident light.

[0041] Before light is incident on the photoelectric conversion element 10, and after the first switch 40 has transitioned from the ON state to the OFF state, the second switch 70 can be switched from the OFF state to the ON state, thereby lowering the potential of the drain (node ​​n1) of the output transistor 20 after the reset. This reduces the output voltage V OUT This makes it possible to operate the output transistor 20 in a region where the linearity with respect to the incident light intensity E is relatively high.

[0042] As described above, according to the photoelectric conversion circuit 1A of the second embodiment of the disclosed technology, it is possible to improve the linearity of the output voltage with respect to the amount of light incident on the photoelectric conversion element 10.

[0043] [Third Embodiment] Figure 10 is a circuit block diagram showing an example of the configuration of an optical line sensor 100 according to a third embodiment of the disclosed technology. The optical line sensor 100 has a plurality of photoelectric conversion circuits 1 connected in parallel between a high-potential power line VDD and a low-potential power line VSS. Each of the plurality of photoelectric conversion circuits 1 is a photoelectric conversion circuit 1 according to the first embodiment described above. The optical line sensor 100 has a plurality of offset compensation circuits 110, a plurality of sample-and-hold circuits 111, a plurality of switches 112, a readout control circuit 113, and an output circuit 114.

[0044] Multiple offset compensation circuits 110, multiple sample-and-hold circuits 111, and multiple switches 112 are each provided in accordance with multiple photoelectric conversion circuits 1. The offset compensation circuit 110 adjusts the output voltage V of the corresponding photoelectric conversion circuit 1. OUTThe DC component contained in is set to a reference level. The sample-and-hold circuit 111 uses the offset-compensated output voltage V OUT The sampling value is stored. The readout control circuit 113 sequentially controls the multiple switches 112 to be turned on, thereby controlling the output voltage V of each of the multiple photoelectric conversion circuits 1. OUT The sampling values ​​are sequentially supplied to the output circuit 114. The output circuit 114 outputs voltage V OUT The sampled values ​​are subjected to a predetermined process and output.

[0045] The optical line sensor 100 according to this embodiment makes it possible to improve the linearity of the output voltage with respect to the amount of incident light. As shown in Figure 11, the optical line sensor 100 may have a plurality of photoelectric conversion circuits 1A connected in parallel between the high-potential power supply line VDD and the low-potential power supply line VSS. Each of the plurality of photoelectric conversion circuits 1A is a photoelectric conversion circuit 1A according to the second embodiment described above.

[0046] With regard to the first to third embodiments described above, the following additional information is disclosed. (Note 1) Photoelectric conversion element, An output transistor connected to the photoelectric conversion element, which outputs a voltage corresponding to the amount of light incident on the photoelectric conversion element, A current control transistor that controls the current flowing through the output transistor, A capacitor connected between the gate and drain of the output transistor, A first switch connected in parallel to the capacitor, A bias circuit that outputs a bias voltage, Includes a second switch provided between the output terminal of the bias circuit and the gate of the output transistor. Photoelectric conversion circuit.

[0047] (Note 2) Before light is incident on the photoelectric conversion element, and after the first switch has transitioned from the ON state to the OFF state, the second switch transitions from the OFF state to the ON state. The photoelectric conversion circuit described in Appendix 1.

[0048] (Note 3) The output transistor is an n-channel type MOSFET. The current control transistor is a p-channel type MOSFET located at a higher potential than the output transistor. The aforementioned photoelectric conversion element is a photodiode, The cathode of the photodiode is connected to the gate of the output transistor. The photoelectric conversion circuit described in Appendix 1 or Appendix 2.

[0049] (Note 4) The output transistor is a p-channel type MOSFET. The current control transistor is an n-channel type MOSFET located at a lower potential than the output transistor. The aforementioned photoelectric conversion element is a photodiode, The anode of the photodiode is connected to the gate of the output transistor. The photoelectric conversion circuit described in Appendix 1 or Appendix 2.

[0050] (Note 5) Includes multiple photoelectric conversion circuits, as described in any one of Appendix 1 to 4, connected in parallel between the high-potential power line and the low-potential power line. Optical line sensor. [Explanation of Symbols]

[0051] 1. 1A Photoelectric Conversion Circuit 10 Photoelectric conversion element 20 Output transistors 30 Capacitors 40 First switch 50 Current-Controlled Transistors 60 output terminals 70 Second switch 80 Bias Circuit 100 Optical Line Sensor 110 Offset Compensation Circuit 111 Sample-and-Hold Circuit 112 switches 113 Readout control circuit 114 Output Circuit

Claims

1. Photoelectric conversion element, An output transistor connected to the photoelectric conversion element, which outputs a voltage corresponding to the amount of light incident on the photoelectric conversion element, A current control transistor that controls the current flowing through the output transistor, A capacitor connected between the gate and drain of the output transistor, A first switch connected in parallel to the capacitor, A bias circuit that outputs a bias voltage, A second switch is provided between the output terminal of the bias circuit and the gate of the output transistor, A photoelectric conversion circuit including this.

2. Before light is incident on the photoelectric conversion element, and after the first switch has transitioned from the ON state to the OFF state, the second switch transitions from the OFF state to the ON state. The photoelectric conversion circuit according to claim 1.

3. The output transistor is an n-channel MOSFET. The current control transistor is a p-channel type MOSFET located at a higher potential than the output transistor. The aforementioned photoelectric conversion element is a photodiode, The cathode of the photodiode is connected to the gate of the output transistor. The photoelectric conversion circuit according to claim 1.

4. The output transistor is a p-channel type MOSFET. The current control transistor is an n-channel type MOSFET located at a lower potential than the output transistor. The aforementioned photoelectric conversion element is a photodiode, The anode of the photodiode is connected to the gate of the output transistor. The photoelectric conversion circuit according to claim 1.

5. Includes a plurality of photoelectric conversion circuits according to any one of claims 1 to 4, connected in parallel between a high-potential power supply line and a low-potential power supply line. Optical line sensor.

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