Local stress reduction in glass through vias

Abstract

The present invention provides an apparatus, device, and method for reducing the amount of local stress at the points where the upper and lower surfaces of a glass through-via (TGV) metal region are in contact with the glass layer during the TGV formation process. [Solution] A method for forming a TGV includes forming a structure by forming through holes in a glass layer, forming adhesion-promoting layers on the side walls of the through holes, the upper surface of the glass layer, and the lower surface of the glass layer, forming a dielectric layer on the upper surface of the glass layer, forming holes in the dielectric layer, and forming a seed layer in the adhesion-promoting layer within the through holes, and leaving a portion of the dielectric layer within the through holes by etching and planarizing the structure.

Description

Background Art

[0001] Glass substrates are promising alternatives to conventional organic substrates (e.g., printed circuit boards) due to their low flatness, which enables higher interconnect density on the substrate, and better thermal and mechanical stability. Glass vias provide electrical connection between a component located on one side of the glass substrate and another component located on the opposite side of the glass substrate.

Brief Description of the Drawings

[0002] [Figure 1-1] FIGS. 1A, 1B, 1C, 1D, 1E, and 1F are cross-sectional views of a first exemplary structure including a glass layer at various stages of manufacture. [Figure 1-2] FIGS. 1G and 1H are cross-sectional views of a first exemplary structure including a glass layer at various stages of manufacture.

[0003] [Figure 2-1] FIGS. 2A, 2B, 2C, 2D, and 2E are cross-sectional views of a second exemplary structure including a glass layer at various stages of manufacture. [Figure 2-2] FIGS. 2F, 2G, 2H, 2I, 2J, and 2K are cross-sectional views of a second exemplary structure including a glass layer at various stages of manufacture.

[0004] [Figure 3-1] FIGS. 3A, 3B, 3C, 3D, 3E, and 3F are cross-sectional views of a third exemplary structure including a glass layer at various stages of manufacture. [Figure 3-2] FIGS. 3G, 3H, 3I, 3J, and 3K are cross-sectional views of a third exemplary structure including a glass layer at various stages of manufacture.

[0005] [Figure 4-1]Figures 4A, 4B, 4C, 4D, 4E, and 4F are cross-sectional views of a fourth exemplary structure containing a glass layer at various stages of the formation of through-glass vias (TGVs) within the structure. [Figure 4-2] Figures 4G and 4H are cross-sectional views of a fourth exemplary structure containing a glass layer at various stages of the formation of through-glass vias (TGVs) within the structure.

[0006] [Figure 5] This is a plan view of a fifth exemplary structure having a layer of glass including glass through vias formed by any of the embodiments disclosed herein.

[0007] [Figure 6] This is a first exemplary method for forming glass through vias.

[0008] [Figure 7] This is a second exemplary method for forming glass through vias.

[0009] [Figure 8] This is a third exemplary method for forming glass through vias.

[0010] [Figure 9] This is a third exemplary method for forming glass through vias.

[0011] [Figure 10] This is a top view of a wafer and die that may be included in a microelectronic assembly according to any embodiment disclosed herein.

[0012] [Figure 11] This is a side cross-sectional view of an integrated circuit device that may be included in a microelectronic assembly according to any embodiment disclosed herein.

[0013] [Figure 12] A side cross-sectional view of an integrated circuit device assembly that may include a microelectronic assembly according to any of the embodiments disclosed herein.

[0014] [Figure 13] A block diagram of an exemplary electrical device that may include a microelectronic assembly according to any of the embodiments disclosed herein.

Mode for Carrying Out the Invention

[0015] In some existing glass through-via (TGV) formation processes, by etching and polishing the TGV metal after TGV metal plating, a TGV region having upper and lower surfaces recessed from the upper and lower surfaces of the glass layer in which the TGV is formed may remain. These recesses create a triple point where the TGV metal, glass, and air contact. Due to the difference in the coefficient of thermal expansion between the TGV metal (typically copper) and the glass layer, downstream heat treatment (e.g., annealing) causes the expansion of the TGV metal along the surface of the glass layer, generating shear stress at the TGV glass interface. This may cause cracks or other damage to the glass layer. The susceptibility of damage to the glass layer starting from these triple points may increase at a fine TGV pitch.

[0016] This specification discloses a technique for reducing the amount of local stress at the points where the upper and lower surfaces of a TGV metal region contact the glass layer by filling in recesses on the upper and lower surfaces of the TGV metal region that may be created after etching and polishing the TGV metal following TGV plating. The recesses are filled with a conductive paste or metal-plated by an electroless process. The conductive paste may have tin or tin doped with one or more metals. The electroless copper may have a particle size of less than 1 micron, and the particle size of the bulk TGV region may be in the range of 1 to 10 microns. Alternatively, a “lip” containing a low-modulus dielectric material is formed where the TGV-glass-air triple point would normally be formed. By filling the recesses with a conductive paste that is doped tin, or by forming a low-modulus “lip” instead of the metal-glass-air triple point, local TGV stress can be reduced, and crack formation in the glass layer can be mitigated. This increases the yield of glass substrates (or cores) containing TGV, thereby reducing the overall cost of manufacturing these components.

[0017] The following description provides specific details, but embodiments of the technology described herein can be implemented without these details. Known circuits, structures, and technologies are not described in detail to avoid obscuring the understanding of this specification. Phrases such as “one embodiment,” “various embodiments,” and “several embodiments” may include features, structures, or characteristics, but not all embodiments necessarily include a particular feature, structure, or characteristic.

[0018] Some embodiments may have some or all of the features of other embodiments and may not have any of these features. "First", "Second", "Third", etc. describe common objects and indicate that different examples of similar objects are being referred to. Such adjectives do not indicate that the objects so described need to be in a given order, rank, or any other manner, either temporally or spatially. "Connected" may indicate that elements are in direct physical or electrical contact with each other, and "coupled" may indicate that elements cooperate or interact with each other, although they may or may not be in direct physical or electrical contact with each other. Further, terms such as "comprise", "include", "have", etc. are synonymous when used with respect to embodiments of the present disclosure.

[0019] Terms modified by the term "substantially" include arrangements, orientations, intervals, or positions that vary slightly from the meaning of the unmodified term. For example, a hole described as substantially filled may include voids, and an end described as substantially coinciding with a surface includes an end that is not exactly in the same plane as that surface but coincides within a few microns of that surface, and a cross-section described as substantially a particular shape (e.g., four semi-circles) includes a cross-section that is different from the complete version of that particular shape but still has the overall same shape as the described shape.

[0020] Reference is made to the drawings below, which are not necessarily drawn to scale and like or identical reference numerals may be used to designate like or identical parts in different figures. The use of like or identical reference numerals in different figures does not mean that all figures including those reference numerals constitute a single or the same embodiment. Similar numerals with different letter suffixes may represent different instances of similar components. The drawings generally, by way of example and not limitation, illustrate the various embodiments discussed in this document.

[0021] In the following description, numerical details are provided for illustrative purposes to facilitate understanding. However, it will be apparent that these novel embodiments can be practiced without these specific details. In other examples, known structures and devices are shown in the form of block diagrams to facilitate their description. The present invention covers all variations, equivalents, and substitutions within the scope of the claims.

[0022] As used herein, the term “located” in the context of a first layer or component located on a second layer or component means that the first layer or component is physically directly attached to the second layer or component (without any layers or components between the first and second layers or components), or that one or more layers or components interpose to the second layer or component. For example, referring to Figure 3F, layer 311 is located on the side wall 309 of the glass layer 304 with an intervening layer 301.

[0023] As used herein, the term “adjacent” refers to layers or components that are in physical contact with each other. In other words, there are no layers or components between the indicated adjacent layers or components. For example, layer X adjacent to layer Y refers to a layer that is in physical contact with layer Y.

[0024] As used herein, the term “integrated circuit component” refers to a packaged or unpackaged integrated circuit product. A packaged integrated circuit component comprises one or more integrated circuit dies mounted on a package substrate, and the integrated circuit dies and package substrate are enclosed in a casing material such as metal, plastic, glass, or ceramic. In one example, a packaged integrated circuit component includes one or more processor units mounted on a substrate, the outer surface of which includes a solder ball grid array (BGA). In one example of an unpackaged integrated circuit component, a single monolithic integrated circuit die comprises solder bumps attached to contacts on the die. The solder bumps enable the die to be directly mounted to a printed circuit board. An integrated circuit component may include one or more of any computing system components described or referred to herein, or any other computing system components, such as processor units (e.g., system-on-a-chip (SoC), processor cores, graphics processor units (GPUs), accelerators, chipset processors), I / O controllers, memory, or network interface controllers.

[0025] As used herein, the phrase "electrically coupled" means that there is one or more conductive paths between the components described as electrically coupled.

[0026] Certain technical terms may be used herein for reference purposes only and are therefore not intended to be limiting. For example, terms such as “upper,” “lower,” “top,” “bottom,” “underside,” and “upper part” refer to directions in the referenced figures. Terms such as “front,” “back,” “rear,” and “side” describe the orientation and / or location of layers, components, parts of components, etc., within any reference frame, which will be identified by referring to the strings and associated figures describing those layers, components, parts of components, etc., under consideration. Such technical terms may include the terms specifically mentioned above, their derivatives, and terms with similar meanings.

[0027] Figures 1A to 1H are cross-sectional views of a first exemplary structure including a glass layer (which may also be called a glass core or glass substrate) at various stages of manufacturing. Figure 1A shows a solid layer of glass 104 (glass layer) as the starting point for structure 100.

[0028] In any of the embodiments described herein, the glass layer 104 may be an amorphous solid glass layer. In some embodiments, the glass layer may comprise silica (containing silicon dioxide (SiO2)), fused silica, aluminosilicate (containing aluminum oxide (Al2O3) and silicon dioxide), borosilicate (containing silicon dioxide and boron trioxide (B2O3)), or aluminoborosilicate (containing aluminum oxide, silicon dioxide, and boron trioxide). In some embodiments, the glass layer may contain one or more of the following additives: aluminum oxide, boron trioxide, magnesium oxide (MgO), calcium oxide (CaO), strontium oxide (SrO), barium oxide (BaO), tin(IV) oxide (SnO2), nitrous oxide (Na2O), potassium oxide (K2O), phosphorus trioxide (P2O3), zirconium dioxide (ZrO2), lithium oxide (Li2O), titanium, and zinc. In some embodiments, the glass layer may contain silicon and oxygen, as well as one or more of aluminum, boron, magnesium, calcium, barium, tin, potassium, sodium, strontium, phosphorus, zirconium, lithium, titanium, and zinc. In some embodiments, the glass layer contains at least 23 weight percent silicon, at least 26 weight percent oxygen, and at least 5 weight percent aluminum. In some embodiments, the glass layer does not contain organic adhesives or organic materials. For example, it is not a substrate or board containing glass fibers and epoxy binders, such as a printed circuit board (PCB) having multiple metal (or interconnect) layers separated from each other by layers of dielectric material (e.g., FR-4 or other glass fiber reinforced epoxy laminate) and interconnected by conductive vias.

[0029] In some embodiments, the glass layer has a thickness ranging from about 50 microns to about 1.4 millimeters. In some embodiments, the glass layer is a multilayer glass substrate (coreless substrate) or a part thereof. Individual glass layers within the multilayer glass substrate may have a thickness ranging from about 25 microns to about 50 microns. In some embodiments, the glass layer may have a length ranging from about 10 millimeters to about 250 millimeters on each side (for example, it may have an area ranging from about 10 mm × 10 mm to about 250 mm to 250 mm). In some embodiments, the glass layer comprises a rectangular prism volume from which sections or parts (e.g., glass through vias) have been removed and filled with other metals (e.g., metal).

[0030] Various suitable techniques may be used during the processing of structure 100 (and any other structure comprising a glass layer having glass through vias as described or referenced herein). For example, film deposition, such as depositing layers, filling portions of layers (e.g., removed portions), and filling via openings, may be carried out using any suitable deposition technique, including, for example, chemical vapor deposition (CVD), metalorganic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), atomic layer deposition (ALD), sputtering, and / or physical vapor deposition (PVD). Furthermore, patterning and removal, such as interconnect patterning, via opening formation, and shaping, may be carried out using any suitable technique, such as lithography-based patterning / masking, etching, and / or chemical-mechanical planarization (CMP).

[0031] Figure 1B shows the structure 100 after a through hole 108 has been formed in the glass layer 104. The through hole 108 (or hole) extends from the upper surface 110 to the lower surface 114 of the glass layer 104. Any hole disclosed herein as being formed in the glass layer may be formed by laser-induced deep etching (LIDE) of the glass layer or by another preferred process. When the hole 108 (or any other hole described herein) is formed by the LIDE process, the cross-sectional profile of the hole 108 is shown as an idealized hole in that the side walls 109 of the hole are vertical. In practice, the side walls 109 of the hole produced by LIDE may be tapered, and the width of the hole 108 may narrow from the upper and lower surfaces 110 and 114 of the glass layer 104 toward the center of the glass layer 104, creating an hourglass-shaped hole.

[0032] Figure 1C shows the structure 100 after layer 112 has been formed on the upper and lower surfaces 110 and 114 of the glass layer 104 and on the surface of the side wall 109 of the hole 108. Layer 112 can act as an adhesion promoter to facilitate the adhesion of glass through-via (TGV) metal to the seed layer, the glass layer 104, allowing the hole 108 to be filled with the TGV metal (e.g., by electroplating), and as a diffusion barrier to prevent the TGV metal from diffusing into the glass layer 104. Similar seed / diffusion / adhesion layers may be formed on the side walls of any through-hole disclosed herein before filling the through-hole with the TGV metal. In some embodiments, layer 112 includes a first layer located on the side wall 109 of the glass layer 104, and a second layer located on the first layer. The first layer may include titanium or another suitable material capable of promoting the adhesion of the metal to the glass layer 104, and the second layer may include copper, silver, gold, or another suitable conductive material capable of acting as a seed layer for the TGV metal. For convenience, a layer formed on the sidewall of a hole in the glass layer (e.g., 112) may be referred to herein as a “seed layer” even if, in addition to acting as a seed layer while the through-hole is filled by plating, layer 112 can also perform adhesion-promoting and diffusion barrier functions.

[0033] Figure 1D shows structure 100 after plating with glass through via metal 116. The TGV metal fills the through hole 108 by filling plating (i.e., filling the through hole 108 with the TGV metal, which is formed on the seed layer 112 on the side wall 109 of the through hole, and filling the through hole outward from there). The TGV metal 116 substantially fills the hole 108 and covers the upper and lower surfaces 110 and 114 of the glass layer 104. The TGV metal 116, and any other TGV metals disclosed or referenced herein (e.g., 216, 316), may include copper, nickel, tungsten, molybdenum, platinum, gold, silver, aluminum, another suitable metal, or a suitable alloy.

[0034] Figure 1E shows structure 100 after etching and planarizing the upper and lower surfaces of structure 100 shown in Figure 1D. Etching and planarizing remove the TGV metal 116 from the upper and lower surfaces 110 and 114 of the glass layer 104, leaving a region of TGV metal 117 (TGV metal region 117) within the hole 108. Figure 1E shows the upper recess 120 remaining after the planarization process due to the upper surface 122 of the TGV metal region 117 being within the distance of the upper surface 110, and the lower recess 124 remaining after the planarization process due to the lower surface 126 of the TGV metal region 117 being within the distance of the lower surface 114 of the glass layer 104. In some embodiments, the heights of the recesses 120 and 124 (e.g., heights 125 and 127, respectively) are in the range of about 4 microns to about 10 microns. As a result of etching and planarizing the TGV metal 116, the seed layer 112 is removed from the upper and lower surfaces 110 and 114 of the glass layer 104, and from the portion of the side wall 109 adjacent to the recesses 120 and 124. Consequently, the upper end 130 and lower end 134 of the seed layer 112 substantially coincide with the upper surface 122 and lower surface 126, respectively, of the TGV metal region 117. The structure 100 includes a triple point 123 (in contact with the glass layer 104, the TGV metal region 117, and air).

[0035] Figure 1F shows structure 100 after recesses 120 and 124 have been substantially filled with layer 138 to reduce local stress at the triple point 123 during downstream heat treatment of structure 100. In some embodiments, layer 138 may contain a tin-based paste. In some embodiments, the tin-based paste may be doped with silver, copper, nickel, antimony, indium, palladium, or bismuth. In embodiments in which layer 138 contains a tin-based paste, the paste contains a binder. In embodiments in which layer 138 contains a tin-based paste, the paste may further contain one or more additives.

[0036] In other embodiments, layer 138 may be formed by electroless plating. In such embodiments, the grain structure of layer 138 may have a different grain structure from that of the TGV metal region 117 (or bulk TGV region). For example, in some embodiments, the particle size of layer 138 may be smaller than the particle size of the particles in the TGV metal region 117. In other embodiments, a substantial portion (more than 90%) of the particles in layer 138 have a size within a first particle size range, and a substantial portion (more than 90%) of the particles in the TGV metal region 117 have a size within a second particle size range. In some embodiments, the first particle size range does not have to overlap with the second particle size range; that is, the upper limit of the first particle size range is smaller than the lower limit of the second particle size range. In some embodiments, there may be overlap between the first and second particle size ranges (for example, the upper limit of the first particle size range is 25% or less larger than the lower limit of the second particle size range). In some embodiments, the particle size within layer 138 may be less than about 1 micron, and the particle size within the TGV metal region may be in the range of about 1 micron to about 10 microns. In embodiments in which layer 138 is formed by electroless plating, layer 138 may contain copper, nickel, palladium, gold, silver, or other suitable metals.

[0037] In both cases, the TGV metal region 117 and the layers 138 adjacent to the upper and lower surfaces 122 and 126 of the TGV metal region 117 provide a conductive path through the glass layer 104 from the upper surface 110 to the lower surface 114 of the glass 104, thereby forming glass through vias 119.

[0038] Figure 1G shows structure 100 after dielectric layers 142, vias 146, and pads 154 are formed on the upper and lower surfaces of structure 100 shown in Figure 1F. The dielectric layer 142 may include an oxide, nitride, or another suitable dielectric. For example, the dielectric layer 142 may be silicon and oxygen (e.g., SiO2). x SiO2), silicon and nitrogen (e.g., Si x N y The dielectric layer may include silicon nitride (Si3N4), or Ajinomoto Build-up Film (ABF). ABF may be characterized as a material mainly containing carbon, or a material mainly containing carbon and nitrogen. Layer 142 may act as a buffer layer between the glass layer 104 and the layer formed on the glass layer during downstream processing. A layer 150 of material is positioned between the dielectric layer 142 and the upper and lower surfaces 110 and 114 of the glass layer 104. Layer 150 may act as an adhesive layer to promote adhesion of the dielectric layer 142 to the glass layer 104. In some embodiments, layer 150 contains silicon nitride (e.g., SiN). The dielectric layer 142 and layer 150 are located above or below the TGV 119 and include openings that are substantially filled by vias 146. The vias 146 provide a conductive connection between the pad 154 and the TGV 119. The vias 146 and pads 154 may include copper, nickel, tungsten, molybdenum, platinum, gold, silver, aluminum, another suitable metal, or a suitable alloy. The material used for any of the TGV metal area 117, recess 120 or 124, via 146, or pad 154 may be the same as or different from the material used for the other of the TGV metal area 117, recess 120 or 124, via 146, or pad 154.

[0039] Pad 154 may be part of a first redistribution layer (RDL), which is part of a stack of RDLs connecting integrated circuit components to TGV 119. Pad 154 is optional. In some embodiments, integrated circuit components may be attached to the structure without using pad 154. For example, conductive contacts (e.g., microbumps) of integrated circuit components may be attached directly to via 146. Figure 1H is a detailed view of a part of Figure 1G.

[0040] Figures 2A to 2K are cross-sectional views of a second exemplary structure including glass layers at various stages of manufacturing. The above descriptions of elements and features in Figures 1A to 1H apply to element features with similar reference numerals in Figures 2A to 2K. For example, glass layer 204, layer 212, TGV metal region 217, and via 246 are described by the descriptions provided above for glass layer 104, layer 112, TGV metal region 117, and via 146, respectively.

[0041] Figures 2A to 2C show the structure 200 in a processing stage similar to that shown in Figures 1A to 1C. Figure 2A shows the solid glass layer 204 as the starting point of the structure 200. Figure 2B shows the structure 200 after through holes 208 have been formed in the glass layer 204. The through holes 208 extend from the upper surface 210 to the lower surface 214 of the glass layer 204. Figure 2C shows the structure 200 after one or more seed layers 212 have been formed on the upper surface 210, the lower surface 214, and the side walls 209 of the glass layer 204. The layers 212 act as seed layers for the TGV metal.

[0042] Figure 2D shows the structure 200 after lamination, where layers 207 of dielectric material are placed on the upper and lower surfaces 210 and 214 of the glass layer 204. In some embodiments, layer 207 may be placed on and bonded to the glass layer 204 by a dynamic lamination assembly (DLA) process. In other embodiments, layer 207 may be placed or formed on the upper and lower surfaces 210 and 214 of the glass layer 204 by another preferred method. Layer 207 covers the hole 208 and forms a “tent” feature 205 that extends into the hole 208. The tent feature 205 is shown as having a rounded shape, but can have other shapes. Layer 207 may include any low-modulus dielectric material having a Young's modulus of about 5 gigapascals (GPa) or less, such as a low-modulus Ajinomoto build-up film or encapsulation molding material. In some embodiments, the encapsulation mold material may include a polymer of carbon and oxygen, along with a filler material such as silicon dioxide (silica) and / or other inorganic materials. The tent feature of layer 207 prevents the formation of an air-glass-via triple point within the structure 200, and the low coefficient of the material forming layer 207 allows layer 207 to absorb stresses within the structure 200 during downstream heat treatment of the structure 200, helping to prevent cracks or other damage in the glass layer 204. In embodiments where ABF is used as layer 207, layer 207 may be laminated only over the opening of the hole 208, rather than being a continuous layer as shown in Figure 2D.

[0043] Figure 2E shows the structure 200 after an opening 203 has been formed in layer 207. The opening 203 may be formed by a photolithography process, laser drilling, or another preferred process in embodiments in which layer 207 contains a photoimaging dielectric. The opening 203 exposes the hole 208 and leaves a protrusion 221 of the dielectric layer 207 that extends beyond the side wall 209 of the glass layer 204 and over the through hole 208. The protrusion 221 includes a portion 223 (protruding portion) that extends into the hole 208. The protruding portion 223 may be called a “lip”. The protrusion 221 and the protruding portion 223 will be discussed in more detail below.

[0044] Figure 2F shows structure 200 after it has been filled and plated with glass-penetrating via metal. The TGV metal substantially fills the holes 208 in the glass layer 204 and substantially fills the openings 203, creating TGV metal regions 217.

[0045] Figure 2G shows structure 200 after etching and planarizing the upper and lower surfaces of structure 200 shown in Figure 2F. The etching and planarization process removes layer 207 from the upper and lower surfaces 210 and 214 of the glass layer 204, leaving the TGV metal region 217 that substantially fills the hole 208. As a result of the etching and planarization process, the lip 223 of the dielectric extension 221 remains as part of structure 200. Referring to Figures 2H and 2I, respectively, a detailed plan view and a detailed cross-sectional view of a portion B of structure 200 shown in Figure 2G, the surface 264 of the lip 223 located on the upper part of structure 200 is located between the periphery 268 of the TGV metal region 217 on the upper surface 272 of the TGV metal region 217 and the upper periphery 276 of the TGV sidewall 209. Referring to Figure 2J, a cross-sectional view of a portion C of the structure 200 shown in Figure 2G, the lower surface 265 of the lip 223 located at the bottom of the structure 200 is situated between the peripheral portion 269 of the TGV metal region 217 on the lower surface 273 of the TGV metal region 217 and the lower peripheral portion 277 of the TGV side wall 209.

[0046] The lip 223 shown in Figures 2G to 2K has an annular shape in the plan view. In other embodiments, the lip 223 may have a rounded rectangular shape in the plan view. The lip 223 may have a quarter-circular cross-sectional shape, as shown in Figures 2G and 2I to 2K. In other embodiments, the lip 223 may have other cross-sectional shapes, such as substantially triangular or substantially quarter-circular. In some embodiments, such as those shown in Figures 2G and 2I to 2K, the lip 223 may have a first thickness (e.g., 282) in the inner periphery 270 of the lip 223 that is greater than a second thickness (e.g., 280) in the outer periphery 271 of the lip 223. In some embodiments, the maximum thickness (e.g., distance 282) of the lip 223 extending into the TGV metal region 217 is less than about 30%, less than about 25%, less than about 20%, or less than about 10% of the height of the glass layer (e.g., 284). In some embodiments, the maximum thickness of the lip 223 extends about 200 microns or less within the TGV metal region 217. The maximum thickness of the lip 223 may extend by different distances within the TGV metal region 217 depending on the height of the glass layer. In some embodiments, the maximum thickness of the lip 223 may extend about 30 microns, about 50 microns, and about 100 microns for heights of about 100, about 200, or about 400 microns, or greater, of the TGV metal region 217. In some embodiments, the minimum thickness of the lip 223 (e.g., distance 280) extends only about 0.5 microns within the TGV metal region 217. In some embodiments, the width 284 of the lip may be less than about 10 microns, less than about 7 microns, or less than about 5 microns, or smaller.

[0047] Figure 2K shows structure 200 after dielectric layers 242, vias 246, and pads 254 have been formed on the upper and lower surfaces of structure 200 shown in Figure 2F. A layer of material 250 is positioned between the upper and lower surfaces 210 and 214 of the dielectric layer 242 and glass layer 204. The dielectric layer 242 and layer 250 include openings located above or below the TGV metal region 217 and substantially filled by vias 246. The vias 246 provide a conductive connection between the pads 254 and the TGV metal region 217.

[0048] Figures 3A–3K are cross-sectional views of a third exemplary structure including a glass layer at various stages of manufacturing. One difference between the process shown in Figures 3A–3K and that shown in Figures 2A–2K is that the dielectric layer (e.g., 207) used to create the tent-shaped feature remains as part of the structure, providing local stress relief, and also acts as a buffer layer between the glass layer and the layers formed above and below the glass layer in downstream processes. By retaining the dielectric layer 207 for use as a buffer layer, the number of processing steps required to form the TGV can be reduced.

[0049] The above descriptions of the elements and features in Figures 1A to 1H and Figures 2A to 2K apply to the element features with similar reference numerals in Figures 3A to 3K. For example, layer 301, glass layer 304, TGV metal region 317, dielectric layer 307, and overhang portion 323 are described by the descriptions provided above for layer 212, glass layer 104, TGV metal region 117, dielectric layer 207, and lip 223, respectively.

[0050] Figures 3A to 3C show the same processing steps as those shown in Figures 2A to 2C. Figure 3A shows the solid glass layer 304 as the starting point of structure 300. Figure 3B shows structure 300 after through holes 308 have been formed in the glass layer 304. The through holes 308 extend from the upper surface 310 to the lower surface 314 of the glass layer 304. Figure 3C shows structure 300 after layers 301 have been formed on the upper surface 310, the lower surface 314, and the side walls 309 of the glass layer 304. Layer 301 acts as an adhesion promoter layer for forming the dielectric layer 307.

[0051] Figure 3D shows the structure 300 after lamination has been performed to place a layer 307 containing dielectric material on the upper and lower surfaces 310 and 314 of the glass layer 304. Layer 307 covers the through hole 308 and includes a low-factor "tent" feature 305 that extends into the through hole 308 and prevents the formation of an air-glass-metal triple point in the structure 300. Figure 3E shows the structure 300 after a via opening 303 has been formed in layer 307. The opening 303 exposes the hole 308 and leaves an overhang 321 of the dielectric layer 307 that extends past the side wall 309 and out over the hole 308. The overhang 321 includes a lip 323 that extends into the hole 308.

[0052] Figure 3F shows the structure 300 after the formation of layer 311 (the light gray line in Figure 3F). In some embodiments, layer 311 includes a first layer located in layer 301, which is located in the side wall 309, and a second layer located in the first layer. That is, the first layer of layer 311 is located between layer 301 and the second layer of layer 311. The first layer may contain titanium or another suitable material capable of promoting adhesion of glass-penetrating via metal to layer 301, and the second layer may contain copper, silver, gold, or another suitable conductive material capable of acting as a seed layer for the TGV metal. In some embodiments, layer 311 includes a single layer containing copper or another suitable conductive material capable of acting as a seed layer for the TGV metal.

[0053] Figure 3G shows the structure 300 after it has been plated with TGV metal. The TGV metal substantially fills the holes 308 in the glass layer 304 and the openings 303 in the layer 307, forming the TGV metal region 317. Referring to Figures 3H and 3I, respectively, detailed plan and cross-sectional views of portion D of the structure 300 shown in Figure 3G, the overhang portion 323 located above the TGV metal region 317 extends downward by a first distance 382 into the TGV metal region 317 at the opening 303 in the layer 307, at the inner peripheral portion 390 of the layer 307. The first distance 382 is greater than the second distance 380 into the TGV metal region 317 to which the overhang portion 323 extends downward at the outer peripheral portion 392 of the overhang portion 323. Referring to Figure 3J, a detailed cross-sectional view of part E of structure 300 shown in Figure 3G, the overhang 321 located below the TGV metal region 317 extends upward by a first distance within the TGV metal region 317, and the first distance at the inner peripheral portion 390 of layer 307 at the opening 303 of layer 307 is greater than the second distance at the outer peripheral portion 392 of the overhang 323 into the TGV metal region 317 to which the overhang 323 extends upward. The overhang 323 may have the shape and characteristics as discussed above with respect to the lip 223. Figure 3K shows structure 300 after pads 354 have been formed on the upper and lower surfaces of structure 300 shown in Figure 3G.

[0054] Figures 4A–4H are cross-sectional views of a fourth exemplary structure including a glass layer at various stages of manufacturing. Structure 400 formed by the process shown in Figures 4A–4H is similar to structure 300 formed by the process shown in Figures 3A–3K, except that the process shown in Figures 4A–4H utilizes bottom-up plating (rather than fill plating) to fill through holes 408 with TGV metal by using a temporary carrier. The above descriptions of elements and features in Figures 1A–1H and 2A–2K apply to element features with similar reference numerals in Figures 4A–4H. For example, layer 401, glass layer 404, TGV metal region 417, dielectric layer 407, and lip 423 are described by the descriptions provided above for layer 212, glass layer 104, TGV metal region 117, dielectric layer 207, and lip 223, respectively.

[0055] Figures 4A to 4E show the same processing steps as those shown in Figures 3A to 3E. Figure 4A shows the solid glass layer 404 as the starting point of structure 400. Figure 4B shows structure 400 after through holes 408 have been formed in the glass layer 404. The through holes 408 extend from the upper surface 410 to the lower surface 414 of the glass layer 404. Figure 4C shows structure 400 after layers 401 have been formed on the upper surface 410, the lower surface 414, and the side walls 409 of the glass layer 404. Layer 401 acts as an adhesion promoting layer for forming the dielectric layer 407. Figure 4D shows structure 400 after layers 407 containing dielectric material have been placed on the upper and lower surfaces 410 and 414 of the glass layer 404 by lamination. Layer 407 includes a low-factor “tent” feature 405 that covers the hole 408 and extends into the hole 408, preventing the formation of an air-glass-metal triple point in the structure 400. Figure 4E shows the structure 400 after a via opening 403 is formed in layer 407. The opening 403 exposes the hole 408 and leaves an overhang 421 of the dielectric layer 407 that extends past the side wall 409 and out over the hole 408. The overhang 421 includes a lip 423 that extends into the hole 408.

[0056] Figure 4F shows structure 400 after a carrier 498 has been attached to the underside of structure 400 shown in Figure 4E. The carrier 498 can act as a seed layer for the TGV metal plating to fill the hole 408. The carrier 498 may include copper, aluminum, or another suitable material. By using the carrier 498 as a seed in TGV plating, the need to form a seed layer on the side wall 409 of the through hole 408 is eliminated.

[0057] Figure 4G shows structure 400 after bottom-up plating of structure 400 with glass-through via metal. Because there is a carrier 498 acting as a seed layer for the TGV metal, the TGV metal substantially fills the holes 408 in a bottom-up manner to form the TGV metal region 417. After bottom-up plating of the TGV metal, the TGV metal may extend past the top surface of layer 407. A planarization process may be performed to planarize the top of structure 400. Figure 4G shows structure 400 after TGV metal plating and subsequent planarization. Figure 4H shows structure 400 after the carrier 498 has been removed and pads 454 have been formed on the top and bottom surfaces of structure 400 as shown in Figure 4G.

[0058] Figures 4A to 4H show the process by which bottom-up plating is used to form a TGV within structure 400, but bottom-up plating can also be used for TGV formation in other structures disclosed herein, such as structure 100.

[0059] Figure 5 is a plan view of a fifth exemplary structure having a layer of glass including glass through vias formed by any of the embodiments disclosed herein. The structure 500 includes a layer of glass 504 having a rectangular shape in the plan view, with a plurality of TGVs 512 formed in the glass layer 504. The TGVs 512 provide electrical connections of an integrated circuit component 508 (its contour is shown by a dashed line) to other components that will be attached to the glass layer 504, or to other components located elsewhere in the computing system in which the structure 500 will be situated.

[0060] Figure 6 shows a second exemplary method for forming a glass through via. In method 600, in step 610, a structure is formed. Forming the structure may include: In step 620, a through hole is formed in a glass layer, where the glass layer is solid and has a rectangular shape in plan view, and the through hole extends from the upper surface of the glass layer to the lower surface of the glass layer. In step 630, adhesion-promoting layers are formed on the side walls of the through hole, the upper surface of the glass layer, and the lower surface of the glass layer. In step 640, a dielectric layer is formed on the upper surface of the glass layer, with a portion of the dielectric layer extending into the through hole. In step 650, a hole is formed in the dielectric layer, which is positioned above the through hole. In step 660, a seed layer is formed in the adhesion-promoting layer within the through hole. In step 670, the seed layer is plated with metal, so that the through hole is substantially filled with metal as a result of the plating. After the formation of the structure, in 680, the structure is etched and planarized, where etching and planarization leave a metallic region substantially filling the through-hole and a portion of the dielectric layer remaining within the through-hole, where the upper surface of the metallic region has a first peripheral portion, the through-hole has a second peripheral portion on the upper surface of the glass layer, the portion of the dielectric layer within the through-hole has an upper surface located between the first and second peripheral portions, and the portion of the dielectric layer within the through-hole extends within the through-hole for a maximum distance of less than 10% of the height of the glass layer.

[0061] Figure 7 shows a third exemplary method for forming a glass through via. In method 700, in step 710, a through hole is formed in a glass layer, where the glass layer is solid and has a rectangular shape in plan view, and the through hole extends from the upper surface to the lower surface of the glass layer. In step 720, adhesion-promoting layers are formed on the sidewall of the through hole, the upper surface of the glass layer, and the lower surface of the glass layer. In step 730, a dielectric layer is formed on the upper surface of the glass layer, with a portion of the dielectric layer extending into the through hole, and the dielectric layer contains a dielectric material. In step 740, an opening is formed in the dielectric layer, the opening is positioned above the through hole, and as a result of forming the opening in the dielectric layer, the dielectric layer includes a projection that extends past the sidewall of the through hole, where the projection includes a projection portion that extends into the through hole. In step 750, a seed layer is formed on the adhesion-promoting layer in the through hole. In step 760, the seed layer is plated with metal, where the through hole is substantially filled with metal as a result of the plating.

[0062] Figure 8 shows a first exemplary method for forming a glass through via. In method 800, in step 810, a structure is formed. Forming the structure may include: In step 820, a through hole is formed in a glass layer, where the glass layer is solid and has a rectangular shape in plan view, and the through hole extends from the upper surface of the glass layer to the lower surface of the glass layer. In step 830, a seed layer is formed on the sidewall of the through hole, the upper surface of the glass layer, and the lower surface of the glass layer. In step 840, the seed layer is plated with a first metal, where the through hole is substantially filled with the first metal as a result of the plating, and substantial portions of the particles of the first metal have a size within a first range of size. After the formation of the structure, in step 850, the structure is etched and planarized, where etching and planarization leave a first region of the first metal substantially filling the through hole, a first recess of the through hole on the upper surface of the first region, and a second recess of the through hole on the lower surface of the first region. In 860, the first recess is substantially filled with a first layer containing tin. In 870, the second recess is substantially filled with a second layer containing tin.

[0063] Figure 9 shows a first exemplary method for forming a glass through via. In method 900, in step 910, a structure is formed. Forming the structure may include: In step 920, a through hole is formed in a glass layer, where the glass layer is solid and has a rectangular shape in plan view, and the through hole extends from the upper surface of the glass layer to the lower surface of the glass layer. In step 930, a seed layer is formed on the sidewall of the through hole, the upper surface of the glass layer, and the lower surface of the glass layer. In step 940, the seed layer is plated with a first metal, where the through hole is substantially filled with the first metal as a result of the plating, and substantial portions of the particles of the first metal have a size within a first range of sizes. After the formation of the structure, in step 950, the structure is etched and planarized, where etching and planarization leave a first region of the first metal substantially filling the through hole, a first recess of the through hole on the upper surface of the first region, and a second recess of the through hole on the lower surface of the first region. In 960, the first recess is substantially filled with a first layer containing tin by electroless plating. In 970, the second recess is substantially filled with a second layer containing tin by electroless plating.

[0064] Methods 600, 700, 800, and 900 may have more or fewer actions than those shown. In some embodiments, multiple actions in these methods may be combined, or individual actions may be divided into multiple actions.

[0065] The glass layer described herein may have any processor unit or integrated circuit component described or referred to herein, either directly attached thereto or attached by one or more interposed routing layers such as a redistribution layer (RDL). Any structure including a glass layer having a TGV to which one or more integrated circuit components are attached (e.g., 100, 200, 300, 400) may be called a microelectronic assembly. The glass layer can also be attached to a printed circuit board. In some embodiments, one or more additional integrated circuit components or other components, such as a battery or an antenna, may be attached to the printed circuit board to which the glass layer is attached. In some embodiments, the printed circuit board and integrated circuit components may be located within a computing device including a housing surrounding the printed circuit board and the glass layer.

[0066] It should be understood that drawings represent an idealized version of a structural cross-section. In actual cross-sections, lines, layers, and other elements shown in drawings may have different shapes. For example, a surface shown as flat may have undulations, bumps, or bowl-shaped features; sidewalls may have tapers to these; 90-degree angles may be rounded; and lines, layers, and features may overlap more or less than shown.

[0067] Figure 10 is a top view of a wafer 1000 and a die 1002 that may be included in any microelectronic assembly including glass layers (e.g., 100, 200, 300, 400) disclosed herein. The wafer 1000 may be constructed of semiconductor material and may include one or more dies 1002 having integrated circuit structures formed on the surface of the wafer 1000. Each die 1002 may be an iterative unit of an integrated circuit product containing any suitable integrated circuit. After the fabrication of the semiconductor product is complete, the wafer 1000 may undergo a fragmentation process in which the dies 1002 are separated from each other to provide separate “chips” of the integrated circuit product. The die 1002 may include one or more transistors (e.g., part of transistor 1140 in Figure 11, discussed below), support circuits for routing electrical signals to the transistors, passive components (e.g., signal traces, resistors, capacitors, or inductors), and / or any other integrated circuit components. In some embodiments, the wafer 1000 or die 1002 may include memory devices (e.g., random access memory (RAM) devices, such as static RAM (SRAM) devices, magnetic RAM (MRAM) devices, resistive RAM (RRAM®) devices, conductive-bridging RAM (CBRAM) devices, etc.), logic devices (e.g., AND, OR, NAND, or NOR gates), or any other suitable circuit elements. Multiple of these devices may be combined on a single die 1002. For example, a memory array formed by multiple memory devices may be formed on the same die 1002 as a processor unit (e.g., processor unit 1302 in Figure 13) or other logic configured to store information in the memory devices or execute instructions stored in the memory array. Various microelectronic assemblies among those disclosed herein may be manufactured using die-to-wafer assembly technology, in which some dies are mounted onto a wafer 1000 containing other dies, and the wafer 1000 is then pulverized.

[0068] Figure 11 is a side cross-sectional view of an integrated circuit device 1100 that may be included in any of the microelectronic assemblies disclosed herein, such as a die included in a packaged integrated circuit component mounted on a glass layer having a TGV. One or more of the integrated circuit devices 1100 may be included in one or more dies 1002 (Figure 10). The integrated circuit device 1100 may be formed on a die substrate 1102 (e.g., wafer 1000 in Figure 10) and may be included in a die (e.g., die 1002 in Figure 10). The die substrate 1102 may be a semiconductor substrate constructed of a semiconductor material system including, for example, a system (or a combination of both) of n-type or p-type material. The die substrate 1102 may include, for example, a crystalline substrate formed using bulk silicon or a silicon-on-insulator (SOI) substructure. In some embodiments, the die substrate 1102 may be formed using alternative materials, which may or may not be combined with silicon, including, but are not limited to, germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Further materials classified as Groups II-VI, III-V, or IV may also be used to form the die substrate 1102. Only a few examples of materials from which the die substrate 1102 may be formed are described here, but any material that can function as the basis for the integrated circuit device 1100 may be used. The die substrate 1102 may be part of a plucked die (e.g., die 1002 in Figure 10) or a wafer (e.g., wafer 1000 in Figure 10).

[0069] The integrated circuit device 1100 may include one or more device layers 1104 disposed on the die substrate 1102. The device layer 1104 may include features of one or more transistors 1140 (e.g., metal oxide semiconductor field-effect transistors: MOSFETs) formed on the die substrate 1102. The transistor 1140 may include, for example, one or more source and / or drain (S / D) regions 1120, a gate 1122 that controls the current between the S / D regions 1120, and one or more S / D contacts 1124 that route electrical signals to and from the S / D regions 1120. The transistor 1140 may include additional features not depicted for clarity, such as device isolation regions, gate contacts, etc. The transistor 1140 is not limited to the type and configuration depicted in Figure 11 and may include a variety of other types and configurations, such as planar transistors, non-planar transistors, or a combination of both. Non-planar transistors may include FinFET transistors such as double-gate transistors or tri-gate transistors, and wrap-around or all-around gate transistors, such as nanoribbons, nanosheets, or nanowire transistors.

[0070] The transistor 1140 may include a gate 1122 formed from at least two layers, a gate dielectric, and a gate electrode. The gate dielectric layer may include one layer or a stack of multiple layers. One or more layers may include silicon oxide, silicon dioxide, silicon carbide, and / or a high-k dielectric material.

[0071] High-k dielectric materials may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that can be used in the gate dielectric layer include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantalate, and zinc lead niobate. In some embodiments, when high-k materials are used, an annealing process may be performed on the gate dielectric layer to improve its quality.

[0072] The gate electrode may be formed on a gate dielectric and may include at least one p-type work function metal or n-type work function metal, depending on whether the transistor 1140 is a p-type metal-oxide-semiconductor (PMOS) or n-type metal-oxide-semiconductor (NMOS) transistor. In some implementations, the gate electrode layer may consist of a stack of two or more metal layers, one or more of which are work function metal layers, and at least one of which is a filler metal layer. Furthermore, metal layers may be included for other purposes, such as barrier layers.

[0073] For PMOS transistors, the metals that can be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and any of the metals discussed below with reference to NMOS transistors (e.g., for work function tuning). For NMOS transistors, the metals that can be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any of the metals discussed above with reference to PMOS transistors (e.g., for work function tuning).

[0074] In some embodiments, when viewed as a cross-section of the transistor 1140 along the source-channel-drain direction, the gate electrode may consist of a U-shaped structure including a lower portion substantially parallel to the surface of the die substrate 1102 and two sidewall portions substantially perpendicular to the top surface of the die substrate 1102. In other embodiments, at least one of the metal layers forming the gate electrode may simply be a planar layer substantially parallel to the top surface of the die substrate 1102 and not including sidewall portions substantially perpendicular to the top surface of the die substrate 1102. In other embodiments, the gate electrode may consist of a combination of U-shaped and non-U-shaped planar structures. For example, the gate electrode may consist of one or more U-shaped metal layers formed on the top surface of one or more planar non-U-shaped layers.

[0075] In some embodiments, pairs of sidewall spacers may be formed on opposing faces of a gate stack so as to surround the gate stack. These sidewall spacers may be formed from materials such as silicon nitride, silicon oxide, silicon carbide, carbon-doped silicon nitride, and silicon oxynitride. Multiple processes for forming sidewall spacers are well known in the art and generally include deposition and etching steps. In some embodiments, multiple spacer pairs may be used; for example, two, three, or four pairs of sidewall spacers may be formed on opposing sides of a gate stack.

[0076] The S / D region 1120 may be formed within the die substrate 1102 adjacent to the gate 1122 of an individual transistor 1140. The S / D region 1120 may be formed using, for example, an implantation / diffusion process or an etching / deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorus, or arsenic may be ion-implanted into the die substrate 1102 to form the S / D region 1120. An annealing process to activate the dopants and further diffuse them into the die substrate 1102 may follow the ion implantation process. In the latter process, the die substrate 1102 may first be etched to form a recess at the location of the S / D region 1120. Next, an epitaxial growth process may be performed to fill the recess with the material used to manufacture the S / D region 1120. In some implementations, the S / D region 1120 may be manufactured using a silicon alloy such as silicon germanium or silicon carbide. In some embodiments, the epitaxially deposited silicon alloy may be in situ doped with dopants such as boron, arsenic, or phosphorus. In some embodiments, the S / D region 1120 is formed using one or more alternating semiconductor materials, such as germanium or materials or alloys of groups III to V. In further embodiments, one or more layers of metals and / or metal alloys may be used to form the S / D region 1120.

[0077] Electrical signals, such as power and / or input / output (I / O) signals, can be routed to and from the device on the device layer 1104 (e.g., transistor 1140) through one or more interconnect layers (shown as interconnect layers 1106-1110 in Figure 11) located on the device layer 1104. For example, the conductive properties of the device layer 1104 (e.g., gate 1122 and S / D contact 1124) can be electrically coupled to the interconnect structure 1128 of the interconnect layers 1106-1110. One or more interconnect layers 1106-1110 can form a metallization stack (also called an "ILD stack") 1119 of the integrated circuit device 1100.

[0078] The interconnect structure 1128 may be arranged within interconnect layers 1106-1110 to route electrical signals according to a variety of designs, and in particular, the arrangement is not limited to the specific configuration of the interconnect structure 1128 depicted in Figure 11. Although a specific number of interconnect layers 1106-1110 are depicted in Figure 11, embodiments of the present disclosure include integrated circuit devices having more or fewer interconnect layers than those depicted.

[0079] In some embodiments, the interconnect structure 1128 may include lines 1128a and / or vias 1128b filled with a conductive material such as metal. Lines 1128a may be arranged to route electrical signals in a plane substantially parallel to the surface of the die substrate 1102 on which the device layer 1104 is formed. For example, lines 1128a may route electrical signals in the direction entering and exiting the plane of the paper and / or across the plane of the paper in the perspective view of Figure 12. Vias 1128b may be arranged to route electrical signals in a plane substantially perpendicular to the surface of the die substrate 1102 on which the device layer 1104 is formed. In some embodiments, vias 1128b may electrically couple lines 1128a of different interconnect layers 1106-1110 together.

[0080] As shown in Figure 11, interconnect layers 1106-1110 may include dielectric material 1126 disposed between interconnect structures 1128. In some embodiments, the dielectric material 1126 disposed between interconnect structures 1128 in different interconnect layers 1106-1110 may have different compositions; in other embodiments, the composition of the dielectric material 1126 between different interconnect layers 1106-1110 may be the same. Device layer 1104 may include dielectric material 1126 disposed between the transistor 1140 and the lower layers of the metallization stack. The dielectric material 1126 contained in device layer 1104 may have a different composition from the dielectric material 1126 contained in interconnect layers 1106-1110; in other embodiments, the composition of the dielectric material 1126 in device layer 1104 may be the same as the dielectric material 1126 contained in any one of interconnect layers 1106-1110.

[0081] A first interconnect layer 1106 (referred to as metal 1 or "M1") may be formed directly on the device layer 1104. As shown, in some embodiments, the first interconnect layer 1106 may include lines 1128a and / or vias 1128b. Lines 1128a of the first interconnect layer 1106 may be coupled to contacts of the device layer 1104 (e.g., S / D contacts 1124). Vias 1128b of the first interconnect layer 1106 may be coupled to lines 1128a of the second interconnect layer 1108.

[0082] A second interconnect layer 1108 (referred to as metal 2 or "M2") may be formed directly above the first interconnect layer 1106. In some embodiments, the second interconnect layer 1108 may include vias 1128b for connecting line 1128 of the second interconnect layer 1108 to line 1128a of the third interconnect layer 1110. Although line 1128a and via 1128b are structurally depicted using lines within the individual interconnect layers for clarity, line 1128a and via 1128b may be structurally and / or materially continuous in some embodiments (e.g., filled simultaneously during a dual damascene process).

[0083] A third interconnect layer 1110 (referred to as metal 3 or "M3") (and additional interconnect layers as desired) may be formed in succession on the second interconnect layer 1108 according to similar techniques and configurations described in relation to the second interconnect layer 1108 or the first interconnect layer 1106. In some embodiments, interconnect layers that are "higher" (i.e., further away from the device layer 1104) in the metallization stack 1119 within the integrated circuit device 1100 may be thicker than interconnect layers that are lower in the metallization stack 1119, and lines 1128a and vias 1128b in the higher interconnect layers are thicker than those in the lower interconnect layers.

[0084] The integrated circuit device 1100 may include a solder resist material 1134 (e.g., polyimide or a similar material) and one or more conductive contacts 1136 formed on interconnect layers 1106-1110. In Figure 11, the conductive contacts 1136 are shown to take the form of bonding pads. The conductive contacts 1136 may be electrically coupled to an interconnect structure 1128 and configured to route electrical signals from transistors 1140 to an external device. For example, solder bonding may be formed on one or more conductive contacts 1136 to mechanically and / or electrically couple an integrated circuit die containing the integrated circuit device 1100 to another component (e.g., a printed circuit board). The integrated circuit device 1100 may include additional or alternating structures for routing electrical signals from interconnect layers 1106-1110; for example, the conductive contacts 1136 may include other similar features (e.g., posts) for routing electrical signals to an external component. The conductive contact 1136 can, as appropriate, function as a pad (154, 254, 354, 454).

[0085] In some embodiments where the integrated circuit device 1100 is a double-sided die, the integrated circuit device 1100 may include another metallization stack (not shown) on the opposite side of the device layer 1104. This metallization stack may include multiple interconnect layers to provide conductive paths (including, for example, conductive lines and vias) between the device layer 1104 and the additional conductive contacts (not shown) on the opposite side of the integrated circuit device 1100 from the conductive contact 1136, as discussed above with reference to interconnect layers 1106-1110. These additional conductive contacts may also function as pads (154, 254, 354, 454) as appropriate.

[0086] In other embodiments where the integrated circuit device 1100 is a double-sided die, the integrated circuit device 1100 may include one or more through-silicon vias (TSVs) through the die substrate 1102. These TSVs may contact the device layer 1104 and provide a conductive path between the device layer 1104 and additional conductive contacts (not shown) on the opposite side of the conductive contact 1136 of the integrated circuit device 1100. These additional conductive contacts may, as appropriate, function as pads (154, 254, 354, 454). In some embodiments, TSVs extending through the substrate may be used to route power and ground signals from the conductive contacts on the opposite side of the conductive contact 1136 of the integrated circuit device 1100 to the transistor 1140 and any other components integrated into the die 1100, and the metallization stack 1119 may be used to route I / O signals from the conductive contact 1136 to the transistor 1140 and any other components integrated into the die 1100.

[0087] In individual stacked devices, multiple integrated circuit devices 1100 may be stacked using one or more TSVs that provide connections between one of the devices and any of the other devices in the stack. For example, one or more high-bandwidth memory (HBM) integrated circuit dies may be stacked on top of a base integrated circuit die, and TSVs in the HBM die may provide connections between the individual HBM and base integrated circuit dies. Conductive contacts may provide additional connections between adjacent integrated circuit dies in the stack. In some embodiments, the conductive contacts may have fine-pitched solder bumps (microbumps).

[0088] Figure 12 is a side cross-sectional view of an integrated circuit device assembly 1200, which may include any of the microelectronic assemblies disclosed herein, including a glass layer having glass through vias. The integrated circuit device assembly 1200 includes several components arranged on a circuit board 1202 (which may be a motherboard, system board, mainboard, etc.). The integrated circuit device assembly 1200 includes components arranged on a first surface 1240 of the circuit board 1202 and a second opposite surface 1242 of the circuit board 1202; generally, components may be arranged on one or both surfaces 1240 and 1242. Any of the integrated circuit components considered below with reference to the integrated circuit device assembly 1200 may take the form of any preferred integrated circuit component among the integrated circuit components disclosed herein.

[0089] In some embodiments, the circuit board 1202 may be a printed circuit board (PCB) comprising a plurality of metal (or interconnect) layers separated from each other by layers of dielectric material and interconnected by conductive vias. Each individual metal layer is provided with conductive traces. One or more of the metal layers may be formed with a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between components coupled to the circuit board 1202. In other embodiments, the circuit board 1202 may be a non-PCB substrate. In other embodiments, the circuit board 1302 may comprise any of the glass layers comprising TGV disclosed herein.

[0090] The integrated circuit device assembly 1200 shown in Figure 12 includes a package-on-interposer structure 1236 coupled to a first surface 1240 of a circuit board 1202 by a coupling component 1216. The coupling component 1216 may electrically and mechanically couple the package-on-interposer structure 1236 to the circuit board 1202 and may include solder balls (as shown in Figure 12), pins (e.g., as part of a pin grid array (PGA)), contacts (e.g., as part of a land grid array (LGA)), male and female sockets, adhesives, underfill materials, and / or any other suitable electrical and / or mechanical coupling structures. The coupling component 1216 may, as appropriate, function as a coupling component illustrated or described for any of the substrate assemblies or substrate assembly components described herein.

[0091] The package-on-interposer structure 1236 may include an integrated circuit component 1220 coupled to the interposer 1204 by a coupling component 1218. The coupling component 1218 can take any preferred form for the application, such as the form considered above with reference to the coupling component 1216. Although a single integrated circuit component 1220 is shown in Figure 12, multiple integrated circuit components may be coupled to the interposer 1204; in fact, additional interposers may be coupled to the interposer 1204.

[0092] The integrated circuit component 1220 may be a packaged or unpackaged integrated circuit product comprising one or more integrated circuit dies (e.g., die 1002 in Figure 10, integrated circuit device 1100 in Figure 11) and / or one or more other suitable components. The packaged integrated circuit component comprises one or more integrated circuit dies mounted on a package substrate, and the integrated circuit dies and package substrate are enclosed in a casing material such as metal, plastic, glass, or ceramic. In an example of an unpackaged integrated circuit component 1220, a single monolithic integrated circuit die comprises solder bumps attached to contacts on the die. The solder bumps allow the die to be mounted directly to the interposer 1204. The integrated circuit component 1220 may comprise one or more computing system components, such as one or more processor units (e.g., a system-on-a-chip (SoC), a processor core, a graphics processor unit (GPU), an accelerator, a chipset processor, an I / O controller, memory, or a network interface controller). In some embodiments, the integrated circuit component 1220 may comprise one or more additional active or passive devices, such as capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices.

[0093] In embodiments where the integrated circuit component 1220 comprises multiple integrated circuit dies, the dies may be of the same type (homogeneous multi-die integrated circuit component) or two or more different types (heterogeneous multi-die integrated circuit component). The multi-die integrated circuit component may be called a multi-chip package (MCP) or a multi-chip module (MCM).

[0094] In addition to comprising one or more processor units, the integrated circuit component 1220 may comprise additional components, such as embedded DRAM, stacked high-bandwidth memory (HBM), shared cache memory, input / output (I / O) controllers, or memory controllers. Any of these additional components may reside on the same integrated circuit die as the processor units, or on one or more integrated circuit dies separate from the integrated circuit die comprising the processor units. These separate integrated circuit dies may be referred to as “chiplets.” In embodiments in which the integrated circuit component comprises multiple integrated circuit dies, the interconnects between the dies may be provided by a package substrate, one or more silicon interposers, one or more silicon bridges embedded in the package substrate (e.g., Intel® embedded multi-die interconnect bridge (EMIB)), or a combination thereof.

[0095] Generally, the interposer 1204 may spread connections to a wider pitch or reroute connections to different connections. For example, the interposer 1204 may couple an integrated circuit component 1220 to a set of ball grid array (BGA) conductive contacts of coupling component 1216 for coupling to a circuit board 1202. In the embodiment shown in Figure 12, the integrated circuit component 1220 and the circuit board 1202 are mounted on opposite sides of the interposer 1204; in other embodiments, the integrated circuit component 1220 and the circuit board 1202 may be mounted on the same side of the interposer 1204. In some embodiments, three or more components may be interconnected by the interposer 1204.

[0096] In some embodiments, the interposer 1204 may be formed as a PCB comprising a plurality of metal layers separated from each other by layers of dielectric material and interconnected by conductive vias. In some embodiments, the interposer 1204 may be formed of an epoxy resin, a glass fiber reinforced epoxy resin, an epoxy resin containing an inorganic filler, a ceramic material, or a polymer material such as polyimide. In some embodiments, the interposer 1204 may be formed of alternating rigid or flexible materials, which may include the same materials described above for use in semiconductor substrates, such as silicon, germanium, and other Group III-V and Group IV materials. The interposer 1204 may include metal interconnects 1208 and vias 1210, including but not limited to through-hole vias 1210-1 (extending from a first surface 1250 of the interposer 1204 to a second surface 1254 of the interposer 1204), blind vias 1210-2 (extending from the first or second surface 1250 or 1254 of the interposer 1204 to an internal metal layer), and embedded vias 1210-3 (connecting internal metal layers to each other).

[0097] In some embodiments, the interposer 1204 may comprise a silicon interposer. Through-silicon vias (TSVs) extending through the silicon interposer may connect connections from a first face of the silicon interposer to a second face opposite the silicon interposer. In some embodiments, the interposer 1304 may have a glass layer including through-glass vias. In some embodiments, the interposer 1204 having a silicon interposer or a glass layer may further have one or more routing layers, such as redistribution layers (RDLs), for routing connections on the first face of the interposer 1204 to a second face opposite the interposer 1204. These routing layers may be located on either of the two faces of the interposer 1304.

[0098] The interposer 1204 may further include embedded devices 1214, which include both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. Multiple more complex devices, such as radio frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and micro-electromechanical systems (MEMS) devices, may also be formed on the interposer 1204. The package-on-interposer structure 1236 may take any form of package-on-interposer structure known in the art. In embodiments where the interposer is a printed circuit board,

[0099] The integrated circuit device assembly 1200 may include an integrated circuit component 1224 coupled to a first surface 1240 of a circuit board 1202 by a coupling component 1222. The coupling component 1222 may take any form of the embodiments discussed above with reference to coupling component 1216, and the integrated circuit component 1224 may take any form of the embodiments discussed above with reference to integrated circuit component 1220.

[0100] The integrated circuit device assembly 1200 shown in Figure 12 includes a package-on-package structure 1234 coupled to a second surface 1242 of a circuit board 1202 by a coupling component 1228. The package-on-package structure 1234 may include integrated circuit components 1226 and 1232, coupled together by a coupling component 1230 such that integrated circuit component 1226 is positioned between the circuit board 1202 and integrated circuit component 1232. The coupling components 1228 and 1230 may take any form of the embodiment of the coupling component 1216 discussed above, and the integrated circuit components 1226 and 1232 may take any form of the embodiment of the integrated circuit component 1220 discussed above. The package-on-package structure 1234 may be configured according to any package-on-package structure known in the art.

[0101] Figure 13 is a block diagram of an exemplary electrical device 1300, which may include one or more of the microelectronic assemblies disclosed herein. For example, any preferred component of the electrical device 1300 may include one or more of the integrated circuit device assembly 1200, integrated circuit component 1220, integrated circuit device 1100, or integrated circuit die 1002 disclosed herein, and may be arranged in any of the microelectronic assemblies disclosed herein. Although numerous components are shown in Figure 13 as being included in the electrical device 1300, one or more of these components may be omitted or duplicated if appropriate for the application. In some embodiments, some or all of the components included in the electrical device 1300 may be mounted on one or more motherboard mainboards or system boards. In some embodiments, one or more of these components are manufactured on a single system-on-chip (SoC) die.

[0102] Additionally, in various embodiments, the electrical device 1300 does not have to include one or more of the components shown in Figure 13, but it may include interface circuits for coupling one or more components. For example, the electrical device 1300 does not have to include the display device 1306, but it may include a display device interface circuit (e.g., a connector and driver circuit) to which the display device 1306 can be coupled. In another set of examples, the electrical device 1300 does not have to include the audio input device 1318 or the audio output device 1308, but it may include an audio input or output device interface circuit (e.g., a connector and support circuit) to which the audio input device 1318 or the audio output device 1308 can be coupled.

[0103] The electrical device 1300 may include one or more processor units 1302 (e.g., one or more processor units). As used herein, the terms “processor unit,” “processing unit,” or “processor” may refer to any device or part of a device that processes electronic data from registers and / or memory and converts that electronic data into other electronic data that can be stored in registers and / or memory. The processor unit 1302 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), general-purpose GPUs (GPGPUs), accelerated processing units (APUs), field-programmable gate arrays (FPGAs), neural network processing units (NPUs), data processor units (DPUs), accelerators (e.g., graphics accelerators, compression accelerators, artificial intelligence accelerators), controller cryptographic processors (dedicated processors that execute cryptographic algorithms in hardware), server processors, controllers, or any other suitable type of processor unit. Therefore, the processor unit may be referred to as XPU (or XPU).

[0104] The electrical device 1300 may include a memory 1304 which itself may include one or more memory devices such as volatile memory (e.g., dynamic random access memory (DRAM), static random-access memory (SRAM)), non-volatile memory (e.g., read-only memory (ROM), flash memory, chalcogenide-based phase-change non-voltage memory), solid-state memory, and / or hard drives). In some embodiments, the memory 1304 may include a memory located on the same integrated circuit die as the processor unit 1302. This memory may be used as a cache memory (e.g., Level 1 (L1), Level 2 (L2), Level 3 (L3), Level 4 (L4), Last Level Cache (LLC)) and may include embedded dynamic random-access memory (eDRAM) or spin-transfer torque magnetic random-access memory (STT-MRAM).

[0105] In some embodiments, the electrical device 1300 may comprise one or more processor units 1302 that are heterogeneous or asymmetrical to other processor units 1302 in the electrical device 1300. There may be a variety of differences between the processing units 1302 in the system in terms of a spectrum of advantages metrics, including architecture, microarchitecture, thermal characteristics, and power consumption characteristics. These differences may effectively manifest themselves as asymmetrical and heterogeneous among the processor units 1302 in the electrical device 1300.

[0106] In some embodiments, the electrical device 1300 may include a communication component 1312 (e.g., one or more communication components). For example, the communication component 1312 may manage wireless communication for data transfer to and from the electrical device 1300. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., that can communicate data by the use of modulated electromagnetic radiation over a non-solid medium. The term “wireless” does not imply that the associated device does not include any wires, although in some embodiments this may not be the case.

[0107] The communication component 1312 may implement any of several wireless standards or protocols, including, but are not limited to, Wi-Fi® (IEEE 802.11 family), IEEE standards including the IEEE 802.16 standard (e.g., IEEE 802.16-2005 amendment), and Long-Term Evolution (LTE) projects including any modifications, updates, and / or revisions (e.g., the Advanced LTE project, the Ultra Mobile Broadband (UMB) project (also known as "3GPP®2")). Broadband radio access (BWA) networks compatible with IEEE 802.16 are commonly referred to as WiMAX® networks. This acronym stands for Worldwide Interoperability for Microwave Access, and it is a certification mark for products that have passed compliance and interoperability tests for the IEEE 802.16 standard. The communication component 1312 may operate in accordance with the Global System for Mobile Communications (GSM®), General-Purpose Packet Radio Service (GPRS), Universal Mobile Communications System (UMTS), High-Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication component 1312 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication component 1312 may operate in accordance with Code Division Multiplexing (CDMA), Time Division Multiplexing (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO) and their derivatives, as well as any other radio protocol designated as 3G, 4G, 5G and beyond. In other embodiments, the communication component 1312 may operate in accordance with a plurality of other radio protocols.The electrical device 1300 may include an antenna for facilitating wireless communication and / or for receiving other wireless communications (e.g., AM or FM radio transmissions).

[0108] In some embodiments, the communication component 1312 may manage wired communications such as electrical, optical, or any other suitable communication protocol (e.g., the IEEE 802.3 Ethernet® standard). As noted above, the communication component 1312 may include multiple communication components. For example, a first communication component 1312 may be dedicated to shorter-range wireless communications such as Wi-Fi® or Bluetooth®, and a second communication component 1312 may be dedicated to longer-range wireless communications such as Global Positioning System (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, the first communication component 1312 may be dedicated to wireless communications, and the second communication component 1312 may be dedicated to wired communications.

[0109] The electrical device 1300 may include a battery / power supply circuit 1314. The battery / power supply circuit 1314 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuits for coupling components of the electrical device 1300 to an energy source separate from the electrical device 1300 (e.g., AC line power).

[0110] The electrical device 1300 may include a display device 1306 (or the corresponding interface circuit discussed above). The display device 1306 may include one or more embedded or wired or wirelessly connected external visual indicators, such as a head-up display, computer monitor, projector, touchscreen display, liquid crystal display (LCD), light-emitting diode display, or flat panel display.

[0111] The electrical device 1300 may include an audio output device 1308 (or the corresponding interface circuit discussed above). The audio output device 1308 may include any embedded or wired or wirelessly connected external device that generates an audible indicator, such as a speaker, headset, or earphone.

[0112] The electrical device 1300 may include an audio input device 1318 (or a corresponding interface circuit as discussed above). The audio input device 1318 may include any embedded, wired, or wirelessly connected device that generates a signal representing sound, such as a microphone, a microphone array, or a digital device (e.g., a device with a MIDI (musical instrument digital interface) output). The electrical device 1300 may include a Global Navigation Satellite System (GNSS) device 1316 (or a corresponding interface circuit as discussed above), such as a Global Positioning System (GPS) device. The GNSS device 1316 may communicate with a satellite-based system and determine the geographic location of the electrical device 1300 based on information received from one or more GNSS satellites, as is known in the art.

[0113] The electrical device 1300 may include other output devices 1310 (or the corresponding interface circuits discussed above). Examples of other output devices 1310 may include audio codecs, video codecs, printers, wired or wireless transmitters for providing information to other devices, or additional storage devices.

[0114] The electrical device 1300 may include other input devices 1320 (or corresponding interface circuits discussed above). Examples of other input devices 1320 may include accelerometers, gyroscopes, compasses, image capture devices (e.g., planar or stereoscopic cameras), cursor control devices such as trackballs, trackpads, touchpads, keyboards, and mice, styluses, touchscreens, proximity sensors, microphones, barcode readers, quick response (QR) code readers, electrocardiogram (ECG) sensors, PPG (photoelectric fingertip plethysmography) sensors, electrocutaneous reaction sensors, any other sensors, or radio frequency identification (RFID) readers.

[0115] The electrical device 1300 may have any desired form factor, such as handheld or mobile electrical devices (e.g., mobile phones, smartphones, mobile internet devices, music players, tablet computers, laptop computers, 2-in-1 convertible computers, portable all-in-one computers, netbooks, ultrabooks, personal digital assistants (PDAs®), ultramobile personal computers, portable gaming consoles, etc.), desktop electrical devices, servers, rack-level computing solutions (e.g., blade, tray, or thread computing systems), workstations or other networked computing components, printers, scanners, monitors, set-top boxes, entertainment control units, stationary gaming consoles, smart TVs, vehicle control units, digital cameras, digital video recorders, wearable electrical devices, or embedded computing systems (e.g., vehicles, smart home appliances, home electronics products or equipment, computing systems that are part of manufacturing equipment). In some embodiments, the electrical device 1300 may be any other electronic device that processes data. In some embodiments, the electrical device 1300 may comprise a plurality of separate physical components. Given the range of devices that the electrical device 1300 can present as in various embodiments, in some embodiments the electrical device 1300 may be referred to as a computing device or computing system.

[0116] When used in this specification and in the claims, an enumeration of items joined by the term "and / or" may mean any combination of the enumerated items. For example, the phrase "A, B, and / or C" may mean A;B;C;A and B;A and C;B and C; or A, B, and C. When used in this specification and in the claims, an enumeration of items joined by the term "at least one of" may mean any combination of the enumerated terms. For example, the phrase "at least one of A, B, or C" may mean A;B;C;A and B;A and C;B and C; or A, B, and C. Furthermore, when used in this specification and in the claims, an enumeration of items joined by the term "one or more of" may mean any combination of the enumerated terms. For example, the phrase "one or more of A, B, and C" may mean A;B;C;A and B;A and C;B and C; or A, B, and C.

[0117] When used in this specification and in the claims, the phrases “each of” or “each of” following an enumeration of items described or referred to as having features, etc., mean that all items in the enumeration have the features, etc., referred to or described. For example, the phrases “each of A, B, or C includes a sidewall” or “each of A, B, or C includes a sidewall” mean that A includes a sidewall, B includes a sidewall, and C includes a sidewall.

[0118] The disclosed methods, apparatus, and systems are not to be considered limited in any way. Rather, this disclosure covers all novel and non-obvious features and aspects of the various disclosed embodiments, both individually and in various combinations and subcombinations of each other. The disclosed methods, apparatus, and systems are not limited to any particular aspect or feature or combination thereof, and the disclosed embodiments do not require any particular effect or problem to be solved or any particular effect to be present or any particular problem to be solved.

[0119] Any theory, scientific principle, or other theoretical explanation of operation presented herein with reference to the apparatus or method of this disclosure is provided for the purpose of better understanding and is not intended to be a limitation of scope. The apparatus and method of the appended claims are not limited to those apparatus and method that operate in the manner described by such operational logic.

[0120] Some operations of the disclosed method are described in a specific order for convenience of presentation; however, unless a specific order is required by certain wording herein, this description should be understood to include rearrangement. For example, operations described in order may, in some cases, be rearranged or performed simultaneously. Furthermore, for the sake of brevity, the accompanying diagrams may not show the various ways in which the disclosed method may be used in conjunction with other methods.

[0121] The following examples relate to additional embodiments of the technology disclosed herein.

[0122] Example A1 is an apparatus comprising a layer of glass; and a through hole extending from the upper surface of the glass layer to the lower surface of the glass layer, wherein a first metal substantially fills a first region of the through hole up to a first distance from the upper surface of the glass layer and up to a second distance from the lower surface of the glass layer; a second metal substantially fills a second region of the through hole located between the upper surface of the first region and the upper surface of the glass layer; and the second metal substantially fills a third region of the through hole located between the lower surface of the first region and the lower surface of the glass layer.

[0123] Example A2 includes the apparatus described in Example A1, wherein the second metal is tin.

[0124] Example A3 includes the apparatus described in Example A1, wherein the second and third regions further contain silver, copper, nickel, antimony, indium, palladium, or bismuth.

[0125] Example A4 includes the apparatus described in Example A1, wherein the second and third regions contain a paste containing the second metal.

[0126] Example A5 includes the apparatus described in any one of Examples A1 to A4, wherein the glass layer comprises silicon; oxygen; and one or more of aluminum, boron, magnesium, calcium, barium, tin, sodium, potassium, strontium, phosphorus, zirconium, lithium, titanium, and zinc.

[0127] Example A6 includes the apparatus described in any one of Examples A1 to A4, wherein the glass layer comprises aluminosilicate glass, borosilicate glass, aluminoborosilicate glass, silica, or fused silica.

[0128] Example A7 includes the apparatus according to any one of Examples A1 to A4, wherein the glass layer contains at least 23 weight percent silicon, at least 26 weight percent oxygen, and at least 5 weight percent aluminum.

[0129] Example A8 includes the apparatus described in any one of Examples A1 to A4, wherein the glass layer does not contain an organic adhesive or organic material.

[0130] Example A9 includes the apparatus described in any one of Examples A1 to A4, wherein the glass layer is amorphous.

[0131] Example A9.1 includes the apparatus described in any one of Examples A1 to A4, wherein the glass layer is solid and has a rectangular shape in a plan view.

[0132] Example A10 includes an apparatus comprising a layer of glass; and a through-hole extending from the upper surface of the layer of glass to the lower surface of the layer of glass, wherein a first metal substantially fills a first region of the through-hole up to a first distance from the upper surface of the layer of glass and up to a second distance from the lower surface of the layer of glass, and a substantial portion of the particles in the first region are of a size within a first range of particle sizes; a second metal substantially fills a second region of the through-hole located between the upper surface of the first metal and the upper surface of the layer of glass, and the second metal substantially fills a third region of the through-hole located between the lower surface of the first metal and the lower surface of the layer of glass, and a substantial portion of the particles in the second and third regions are within a second range of particle sizes, with the lower end of the first range of particle sizes being greater than the upper end of the second range of particle sizes.

[0133] Example A11 includes the apparatus described in Example A10, wherein the first range of particle size is approximately 1 micron to 10 microns, and the second range of particle size is less than approximately 1 micron.

[0134] Example A12 includes the apparatus described in Example A10 or 11, wherein the second metal is copper.

[0135] Example A13 includes the apparatus described in Example A10 or 11, wherein the second metal is nickel, palladium, gold, or silver.

[0136] Example A14 includes the apparatus according to any one of Examples A10 to A13, wherein the glass layer contains at least 23 weight percent silicon, at least 26 weight percent oxygen, and further at least 5 weight percent aluminum.

[0137] Example A15 includes the apparatus described in any one of Examples A10 to A13, wherein the glass layer does not contain an organic adhesive or organic material.

[0138] Example A16 includes the apparatus described in any one of Examples A10 to A15, wherein the glass layer is amorphous.

[0139] Example A17 includes the apparatus described in any one of Examples A10 to A16, wherein the glass layer is a solid glass layer and has a rectangular shape in the plan view.

[0140] Example A17.1 includes the apparatus described in any one of Examples A10 to A16, wherein the glass layer comprises silicon, oxygen, and aluminum.

[0141] Example A18 includes the apparatus described in any one of Examples A1 to A17, wherein the first metal is copper.

[0142] Example A19 includes the apparatus described in any one of Examples A1 to A17, wherein the first metal is nickel, tungsten, molybdenum, platinum, gold, silver, or aluminum.

[0143] Example A20 further includes the apparatus according to any one of Examples A1 to A19, comprising: a first layer having a third metal, the first layer being located on the side wall of the through hole, the upper end of the first layer substantially coinciding with the upper surface of the first region, and the lower end of the first layer substantially coinciding with the lower surface of the first region; and a second layer having a fourth metal, the second layer being located on the first layer, between the first layer and the first region, the upper end of the second layer substantially coinciding with the upper surface of the first region, and the lower end of the second layer substantially coinciding with the lower surface of the first region.

[0144] Example A21 includes the apparatus described in Example A20, wherein the first layer contains titanium and the second layer contains copper.

[0145] Example A22 includes the apparatus described in Example A20, wherein the first layer contains titanium and the second layer contains silver or gold.

[0146] Example A23 further includes the apparatus according to any one of Examples A1 to A20, comprising: a first layer containing silicon and nitrogen located on the upper surface of the glass layer, the first layer having a first opening above the first region; and a second layer containing a dielectric material located on the first layer, the second layer having a second opening above the first region.

[0147] Example A24 includes the apparatus described in Example A23, wherein the dielectric material includes carbon and nitrogen.

[0148] Example A25 includes the apparatus described in Example A23, wherein the dielectric material includes Ajinomoto build-up film.

[0149] Example A26 includes the apparatus described in any one of Examples A23 to A25, wherein the dielectric material comprises a polymer containing carbon and oxygen.

[0150] Example A27 includes the apparatus described in Example A26, wherein the dielectric material further includes silicon.

[0151] Example A28 further comprises the apparatus according to any one of Examples A23 to A25, wherein the third layer comprises a third metal, the third layer substantially filling the first opening and the second opening.

[0152] Example A29 includes the apparatus described in any one of Examples A28, wherein the third metal is copper.

[0153] Example A30 includes the apparatus described in any one of Example A28, wherein the third metal is silver, gold, nickel, tungsten, cobalt, or aluminum.

[0154] Example A31 is a device comprising: a layer of glass; a through-hole extending from the upper surface of the glass layer to the lower surface of the glass layer, wherein a first metal substantially fills a first region of the through-hole up to a first distance from the upper surface of the glass layer and up to a second distance from the lower surface of the glass layer; a second metal substantially fills a second region of the through-hole located between the upper surface of the first region and the upper surface of the glass layer; and a third region of the through-hole located between the lower surface of the first region and the lower surface of the glass layer; and an integrated circuit component located on the upper surface of the glass layer, the conductive contacts of the integrated circuit component being electrically coupled to the first region.

[0155] Example A32 includes the device described in Example A31, wherein the second metal is tin.

[0156] Example A33 includes the device described in Example A31, wherein the second and third regions further contain silver, copper, nickel, antimony, indium, palladium, or bismuth.

[0157] Example A34 includes the device described in Example A31, wherein the second region and the third region contain a paste containing the second metal.

[0158] Example A35 includes the device described in any one of Examples A31 to A34, wherein the glass layer does not contain an organic adhesive or organic material.

[0159] Example A36 includes the device described in any one of Examples A31 to A35, wherein the glass layer is amorphous.

[0160] Example A37 includes a device according to any one of Examples A31 to A36, wherein the glass layer is a solid glass layer and has a rectangular shape in a plan view.

[0161] Example A38 is a device comprising a glass layer containing silicon, oxygen, and aluminum; and a through-hole extending from the upper surface to the lower surface of the glass layer, wherein a first metal substantially fills a first region of the through-hole up to a first distance from the upper surface of the glass layer and up to a second distance from the lower surface of the glass layer, with a substantial portion of the particles in the first region having a size within a first range of particle sizes; and a second metal fills a second region of the through-hole located between the upper surface of the first metal and the upper surface of the glass layer. The device comprises: a second metal substantially filling a third region of the through hole located between the lower surface of the first metal and the lower surface of the glass layer, wherein substantial portions of the particles in the second and third regions are within a second range of particle size, with the lower end of the first range of particle size being greater than the upper end of the second range of particle size; and an integrated circuit component located on the upper surface of the glass layer, the conductive contacts of the integrated circuit component being electrically coupled to the first region.

[0162] Example A39 includes the device described in Example A38, wherein the first range of particle size is approximately 1 micron to 10 microns, and the second range of particle size is less than approximately 1 micron.

[0163] Example A40 includes the device described in Example A38 or A39, wherein the second metal is copper, nickel, palladium, or gold.

[0164] Example A41 includes the device described in any one of Examples A38 to A40, wherein the glass layer comprises silicon; oxygen; and one or more of aluminum, boron, magnesium, calcium, barium, tin, sodium, potassium, strontium, phosphorus, zirconium, lithium, titanium, and zinc.

[0165] Example A42 includes a device according to any one of Examples A38 to A40, wherein the glass layer comprises aluminosilicate glass, borosilicate glass, aluminoborosilicate glass, silica, or fused silica.

[0166] Example A43 includes the device according to any one of Examples A38 to A40, wherein the glass layer contains at least 23 weight percent silicon, at least 26 weight percent oxygen, and further at least 5 weight percent aluminum.

[0167] Example A44 includes the device described in any one of Examples A38 to A43, wherein the glass layer is amorphous.

[0168] Example A45 includes a device according to any one of Examples A38 to A44, wherein the glass layer is a solid glass layer and has a rectangular shape in a plan view.

[0169] Example A45 includes the device described in any one of Examples A38 to A44, wherein the glass layer comprises silicon, oxygen, and aluminum.

[0170] Example A46 includes the device according to any one of Examples A38 to A45, wherein the integrated circuit component is a first integrated circuit component, and the device further comprises a second integrated circuit component located on the lower surface of the glass layer, the second integrated circuit component being electrically coupled to the first region.

[0171] Example A47 further comprises a printed circuit board, wherein the glass layer is located on the printed circuit board, and conductive contacts of the printed circuit board are electrically coupled to the first region, the device according to any one of Examples A38 to A46.

[0172] Example A48 includes the device described in Example A47, wherein the device further comprises a battery and / or antenna located on the printed circuit board.

[0173] Example A49 is a method comprising the steps of forming a structure, the steps of forming through holes in a layer of glass, the through holes extending from the upper surface to the lower surface of the layer of glass; forming seed layers on the side walls of the through holes, the upper surface of the layer of glass, and the lower surface of the layer of glass; and plating the seed layers with a first metal, the through holes being substantially filled with the first metal as a result of the plating, the substantial portion of the particles of the first metal having a size within a first range of sizes; etching and planarizing the structure, the etching and planarizing leaving a first region of the first metal substantially filling the through holes, a first recess of the through holes on the upper surface of the first region, and a second recess of the through holes on the lower surface of the first region; substantially filling the first recess with a first layer containing tin; and substantially filling the second recess with a second layer containing tin.

[0174] Example A50 includes the method according to Example A49, wherein the first and second layers further comprise silver, copper, nickel, antimony, indium, palladium, or bismuth.

[0175] Example A51 includes the method according to Example A49, wherein the first layer and the second layer contain a tin-based paste.

[0176] Example A52 includes the method according to any one of Examples A49 to A51, wherein the glass layer comprises silicon, oxygen, and one or more of aluminum, boron, magnesium, calcium, barium, tin, sodium, potassium, strontium, phosphorus, zirconium, lithium, titanium, and zinc.

[0177] Example A53 includes the method according to any one of Examples A49 to A51, wherein the glass layer comprises aluminosilicate glass, borosilicate glass, aluminoborosilicate glass, silica, or fused silica.

[0178] Example A54 includes the method according to any one of Examples A49 to A51, wherein the glass layer comprises at least 23 weight percent silicon, at least 26 weight percent oxygen, and further at least 5 weight percent aluminum.

[0179] Example A55 includes the method according to any one of Examples A49 to A51, wherein the glass layer does not contain an organic adhesive or organic material.

[0180] Example A56 includes the method according to any one of Examples A49 to A55, wherein the glass layer is amorphous.

[0181] Example A56.1 includes the method according to any one of Examples A49 to A55, wherein the glass layer is solid and has a rectangular shape in a plan view.

[0182] Example A57 is a method for forming a structure, comprising the steps of: forming through holes in a layer of glass comprising silicon, oxygen, and aluminum, wherein the through holes extend from the upper surface to the lower surface of the glass layer; forming seed layers on the side walls of the through holes, the upper surface of the glass layer, and the lower surface of the glass layer; and plating the seed layers with a first metal, wherein the through holes are substantially filled with the first metal as a result of the plating, and substantial portions of the particles of the first metal have a size within a first range of particle sizes. A method comprising: a step of etching and planarizing the structure, wherein etching and planarizing leaves a first region of the first metal substantially filling the through hole, a first recess of the through hole on the upper surface of the first region, and a second recess of the through hole on the lower surface of the first region, wherein substantial portions of the particles in the first and second recesses have a size within a second range of particle sizes; a step of substantially filling the first recess with the second metal by electroless plating; and a step of substantially filling the second recess with the second metal by electroless plating.

[0183] Example A58 includes the method of Example A57, wherein, as a result of etching and planarization, the upper end of the seed layer substantially coincides with the upper surface of the first region, and the lower end of the seed layer substantially coincides with the lower surface of the first region.

[0184] Example A59 includes the method according to any one of Examples A57 to A58, wherein the first range of particle size is about 1 micron to 10 microns, and the second range of particle size is less than about 1 micron.

[0185] Example A60 includes the method described in Examples A57 to A59, wherein the second metal is copper.

[0186] Example A61 includes the methods of Examples A57 to A59, wherein the second metal is nickel, palladium, gold, or silver.

[0187] Example A62 includes the method according to any one of Examples A57 to A59, wherein the glass layer comprises at least 23 weight percent silicon, at least 26 weight percent oxygen, and further at least 5 weight percent aluminum.

[0188] Example A63 includes the method according to any one of Examples A57 to A62, wherein the glass layer does not contain an organic adhesive or organic material.

[0189] Example A64 includes the method according to any one of Examples A57 to A63, wherein the glass layer is amorphous.

[0190] Example A64 includes the method according to any one of Examples A57 to A63, wherein the glass layer comprises silicon, oxygen, and aluminum.

[0191] Example A65 includes the method according to any one of Examples A49 to A64, wherein the first metal is copper.

[0192] Example A66 includes the method according to any one of Examples A49 to A64, wherein the first metal is nickel, tungsten, molybdenum, platinum, gold, silver, or aluminum.

[0193] Example A67 includes a method according to any one of Examples A49 to A66, wherein the step of forming the seed layer is to form a third layer having a third metal, the third layer being located on the side wall of the through hole, the upper end of the third layer substantially coinciding with the upper surface of the first region, and the lower end of the third layer substantially coinciding with the lower surface of the first region; and the step of forming a fourth layer having a fourth metal, the fourth layer being located on the third layer, between the third layer and the first region, the upper end of the fourth layer substantially coinciding with the upper surface of the first region, and the lower end of the fourth layer substantially coinciding with the lower surface of the first region.

[0194] Example A68 includes the method of Example A67, wherein the fourth layer contains titanium and the third layer contains copper.

[0195] Example A69 includes the method of Example A67, wherein the fourth layer contains titanium and the third layer contains silver or gold.

[0196] Example A70 is an apparatus comprising: a layer of glass; a through hole extending from the upper surface of the layer of glass to the lower surface of the layer of glass; wherein a first metal substantially fills a first region of the through hole up to a first distance from the upper surface of the layer of glass; and a first stress relief means for reducing stress in the layer of glass at the point where the layer of glass contacts the upper surface of the first region.

[0197] Example A71 includes the apparatus described in Example A70, wherein the glass layer comprises aluminosilicate glass, borosilicate glass, aluminoborosilicate glass, silica, or fused silica.

[0198] Example A72 includes the apparatus described in Example A70, wherein the glass layer contains at least 23 weight percent silicon, at least 26 weight percent oxygen, and further at least 5 weight percent aluminum.

[0199] Example A73 includes the apparatus described in Example A70, wherein the glass layer does not contain an organic adhesive or organic material.

[0200] Example A74 includes the apparatus described in any one of Examples A70 to A73, wherein the glass layer is amorphous.

[0201] Example A75 includes the apparatus described in Examples A70 to A74, wherein the glass layer is solid and has a rectangular shape in a plan view.

[0202] Example A76 includes the apparatus or device according to any one of Examples A1 to A48, wherein the glass layer has a thickness in the range of about 50 microns to about 1.4 millimeters, a first length in the range of about 10 millimeters to about 250 millimeters, and a second length in the range of about 10 millimeters to about 250 millimeters, the first length being perpendicular to the second length.

[0203] Example A77 includes the apparatus or device described in any one of Examples A1 to A48, wherein the glass layer has a rectangular prism volume.

[0204] Example A78 includes the apparatus or device according to any one of Examples A1 to A48, wherein the layer of glass has a rectangular prism volume having a first side and a second side perpendicular to the first side, the first side having a length in the range of 10 mm to about 250 mm, and the second side having a length in the range of about 10 mm to about 250 mm.

[0205] Example B1 is an apparatus comprising: a layer of glass; and a through hole extending from the upper surface of the layer of glass to the lower surface of the layer of glass; wherein a first metal substantially fills a first region of the through hole; and a second region of the through hole having a dielectric material, wherein the upper surface of the first region of the through hole has a first peripheral portion, the through hole has a second peripheral portion on the upper surface of the layer of glass, and the second region of the through hole has an upper surface located between the first peripheral portion of the first region of the through hole and the second region of the through hole The apparatus comprises a region extending within the through-hole for a maximum distance of less than 10% of the height of the glass layer; a third region of the through-hole containing the dielectric material, the lower surface of the first region of the through-hole having a third peripheral portion, the through-hole having a fourth peripheral portion on the lower surface of the glass layer, the third region of the through-hole having a lower surface located between the third and fourth peripheral portions of the first region of the through-hole, and the third region extending within the through-hole for a maximum distance of less than 10% of the height of the glass layer.

[0206] Example B2 includes the apparatus described in Example B1, wherein the second region of the through hole and the third region of the through hole have an annular or rounded rectangular shape in a plan view.

[0207] Example B3 includes the apparatus according to Example B1 or B2, wherein the first thickness of the second region of the through hole in the inner peripheral portion of the second region of the through hole is greater than the second thickness of the second region of the through hole in the outer peripheral portion of the second region of the through hole.

[0208] Example B4 includes the apparatus according to any one of Examples B1 to B3, wherein the second region of the through hole and the third region of the through hole have a substantially triangular cross-sectional shape.

[0209] Example B5 includes the apparatus according to any one of Examples B1 to B3, wherein the second region of the through hole and the third region of the through hole have substantially a quarter-circular cross-sectional shape.

[0210] Example B6 includes the apparatus described in any one of Examples B1 to B5, wherein the glass layer comprises silicon; oxygen; and one or more of aluminum, boron, magnesium, calcium, barium, tin, sodium, potassium, strontium, phosphorus, zirconium, lithium, titanium, and zinc.

[0211] Example B7 includes the apparatus described in any one of Examples B1 to B5, wherein the glass layer comprises aluminosilicate glass, borosilicate glass, aluminoborosilicate glass, silica, or fused silica.

[0212] Example B8 includes the apparatus according to any one of Examples B1 to B5, wherein the glass layer contains at least 23 weight percent silicon, at least 26 weight percent oxygen, and further at least 5 weight percent aluminum.

[0213] Example B9 includes the apparatus described in any one of Examples B1 to B8, wherein the glass layer does not contain an organic adhesive or organic material.

[0214] Example B10 includes the apparatus described in any one of Examples B1 to B9, wherein the glass layer is amorphous.

[0215] Example B11 includes the apparatus according to any one of Examples B1 to B10, wherein the dielectric material is a first dielectric material, and the apparatus further comprises a first layer comprising silicon and nitrogen, the first layer being located on the upper surface of the glass layer, and the first layer having a first opening above the first region; and a second layer comprising a second dielectric material, the second layer being located on the first layer, and the second layer having a second opening above the first region.

[0216] Example B12 includes the apparatus described in Example B11, wherein the second dielectric material comprises carbon and nitrogen.

[0217] Example B13 includes the apparatus described in Example B11, wherein the second dielectric material comprises a polymer containing carbon and oxygen.

[0218] Example B14 includes the apparatus described in Example B13, wherein the second dielectric material further comprises silicon.

[0219] Example B15 further comprises the apparatus according to any one of Examples B11 to B14, wherein the third layer comprises a second metal, the third layer substantially filling the first opening and the second opening.

[0220] Example B16 includes the apparatus according to any one of Examples B1 to B10, further comprising a first layer located on the side wall of the through hole, the first layer comprising a second metal; and a second layer comprising a third metal, wherein the first layer is located between the side wall and the second layer, and the second layer is located between the first layer and the first region.

[0221] Example B16.1 includes the apparatus described in any one of Examples B1 to B10, wherein the glass layer is solid and has a rectangular shape in a plan view.

[0222] Example B17 is an apparatus comprising: a layer of glass; a through hole extending from the upper surface of the glass layer to the lower surface of the glass layer; wherein a first region of the through hole has a first metal, and the first region of the through hole substantially fills the through hole; and a first layer comprising a dielectric material, wherein the first layer is located on the upper surface of the glass layer, and the first layer includes a first opening through which the first region of the through hole extends; The apparatus comprises: a first overhang extending beyond the side wall of the through hole, the first overhang including a first overhang portion extending into the through hole; and a second layer comprising the dielectric material, wherein the second layer is located on the lower surface of the glass layer, the second layer includes a second opening through which the first region of the through hole extends, the second layer includes a second overhang extending beyond the side wall of the through hole, the second overhang including a second overhang portion extending into the through hole.

[0223] Example B18 includes the apparatus described in Example B17, wherein the first and second overhangs have substantially triangular cross-sectional shapes.

[0224] Example B19 includes the apparatus described in Example B17, wherein the first and second overhangs have substantially quarter-circular cross-sectional shapes.

[0225] Example B20 includes the apparatus described in any one of Examples B17 to B19, wherein the first protruding portion extends downward by a first distance within the through hole at the inner peripheral portion of the first protruding portion, and the first protruding portion extends downward by a second distance within the through hole at the outer peripheral portion of the first protruding portion, and the first distance is greater than the second distance.

[0226] Example B21 includes the apparatus described in any one of Examples B17 to B20, wherein the dielectric material comprises a polymer containing carbon and oxygen.

[0227] Example B22 includes the apparatus according to any one of Example B21, wherein the dielectric material further comprises silicon.

[0228] Example B23 includes the apparatus described in any one of Examples B17 to B21, wherein the dielectric material includes carbon and nitrogen.

[0229] Example B24 includes the apparatus according to any one of Examples B17 to B23, wherein the glass layer contains at least 23 weight percent silicon, at least 26 weight percent oxygen, and further at least 5 weight percent aluminum.

[0230] Example B25 includes the apparatus described in any one of Examples B17 to B24, wherein the glass layer does not contain an organic adhesive or organic material.

[0231] Example B26 includes the apparatus described in any one of Examples B17 to B25, wherein the glass layer is amorphous.

[0232] Example B27 includes the apparatus described in any one of Examples B17 to B26, wherein the glass layer is a solid glass layer and has a rectangular shape in the plan view.

[0233] Example B27.1 includes the apparatus described in any one of Examples B17 to B26, wherein the glass layer comprises silicon, oxygen, and aluminum.

[0234] Example B28 includes the apparatus according to any one of Examples B17 to B27, further comprising: a third layer containing silicon and nitrogen located between the first layer and the upper surface of the glass layer; and a fourth layer containing silicon and nitrogen located between the second layer and the lower surface of the glass layer.

[0235] Example B29 further comprises a fifth layer containing a second metal, wherein the third layer substantially fills the first opening, as described in Example B28.

[0236] Example B30 includes the apparatus described in Example B16 or B29, wherein the second metal is copper.

[0237] Example B31 includes the apparatus described in Example B16 or B29, wherein the second metal is silver, gold, nickel, tungsten, cobalt, or aluminum.

[0238] Example B32 includes the apparatus described in any one of Examples B1 to B31, wherein the first metal includes copper.

[0239] Example B33 includes the apparatus described in any one of Examples B1 to B32, wherein the first metal includes nickel, tungsten, molybdenum, platinum, gold, silver, or aluminum.

[0240] Example B34 includes the apparatus according to any one of Examples B17 to B33, further comprising a first layer located on the side wall of the through hole, the first layer comprising a second metal; and a second layer comprising a third metal, wherein the first layer is located between the side wall and the second layer, and the second layer is located between the first layer and the first region.

[0241] Example B35 includes the apparatus described in Example B16 or B34, wherein the first layer contains titanium and the second layer contains copper.

[0242] Example B36 includes the apparatus described in Example B34, wherein the upper portion of the first layer is positioned between the first overhang and the glass layer, and the lower portion of the first layer is positioned between the second overhang and the glass layer.

[0243] Example B37 includes the apparatus described in Example B16 or B34, wherein the second layer contains titanium and the third layer contains silver.

[0244] Example B38 includes the apparatus described in Example B16 or B34, wherein the second layer contains titanium and the third layer contains gold.

[0245] Example B39. A device comprising a layer of glass; and a through hole extending from the upper surface of the glass layer to the lower surface of the glass layer; wherein a first metal substantially fills a first region of the through hole; a second region of the through hole having a dielectric material, the upper surface of the first region of the through hole having a first peripheral portion, the through hole having a second peripheral portion on the upper surface of the glass layer, the second region of the through hole having an upper surface located between the first peripheral portion of the first region of the through hole and the first peripheral portion of the through hole, the second region of the through hole extending into the through hole for a maximum distance of less than 30% of the height of the glass layer; the through hole A device comprising: a third region comprising the dielectric material, the lower surface of the first region of the through-hole having a third peripheral portion, the through-hole having a fourth peripheral portion on the lower surface of the glass layer, the third region of the through-hole having a lower surface located between the third and fourth peripheral portions of the first region of the through-hole, the third region extending into the through-hole for a maximum distance of less than 30% of the height of the glass layer; and an integrated circuit component located on the upper surface of the glass layer, the conductive contacts of the integrated circuit component being electrically coupled to the first region.

[0246] Example B40 includes the device described in Example B39, wherein the second region of the through hole and the third region of the through hole have an annular or rounded rectangular shape in a plan view.

[0247] Example B41 includes the device described in Example B39 or B40, wherein the first thickness of the second region of the through hole in the inner peripheral portion of the second region of the through hole is greater than the second thickness of the second region of the through hole in the outer peripheral portion of the second region of the through hole.

[0248] Example B42 includes the device described in any one of Examples B39 to B41, wherein the second region and the third region have substantially triangular cross-sectional shapes.

[0249] Example B43 includes the device described in any one of Examples B39 to B41, wherein the second region and the third region have substantially quarter-circular cross-sectional shapes.

[0250] Example B44 includes the device described in any one of Examples B39 to B43, wherein the glass layer comprises silicon; oxygen; and one or more of aluminum, boron, magnesium, calcium, barium, tin, sodium, potassium, strontium, phosphorus, zirconium, lithium, titanium, and zinc.

[0251] Example B45 includes a device according to any one of Examples B39 to B43, wherein the glass layer comprises aluminosilicate glass, borosilicate glass, aluminoborosilicate glass, silica, or fused silica.

[0252] Example B46 includes the device according to any one of Examples B39 to B43, wherein the glass layer contains at least 23 weight percent silicon, at least 26 weight percent oxygen, and further at least 5 weight percent aluminum.

[0253] Example B47 includes the device described in any one of Examples B39 to B46, wherein the glass layer does not contain an organic adhesive or organic material.

[0254] Example B48 includes the device described in any one of Examples B39 to B47, wherein the glass layer is amorphous.

[0255] Example B49 includes a device according to any one of Examples B39 to B48, wherein the glass layer is a solid glass layer and has a rectangular shape in a plan view.

[0256] Example B49.1 includes the device according to any one of Examples B39 to B48, wherein the glass layer contains at least 23 weight percent silicon, at least 26 weight percent oxygen, and further at least 5 weight percent aluminum.

[0257] Example B50 includes a device according to any one of Examples B39 to B49, wherein the dielectric material is a first dielectric material, and the device further comprises a first layer comprising silicon and nitrogen, the first layer located on the upper surface of the glass layer, and the first layer having a first opening above the first region; and a second layer comprising a second dielectric material, the second layer located on the first layer, and the second layer having a second opening above the first region.

[0258] Example B51 includes the device described in Example B50, wherein the second dielectric material comprises carbon and nitrogen.

[0259] Example B52 includes the device described in Example B50, wherein the second dielectric material comprises a polymer containing carbon and oxygen.

[0260] Example B53 includes the device described in Example B52, wherein the second dielectric material further comprises silicon.

[0261] Example B54 further comprises a device according to any one of Examples B50 to B53, the third layer comprising a second metal, the third layer substantially filling the first opening and the second opening.

[0262] Example B55 includes a device according to any one of Examples B39 to B54, further comprising a first layer located on the side wall of the through hole, the first layer comprising a second metal; and a second layer comprising a third metal, wherein the first layer is located between the side wall and the second layer, and the second layer is located between the first layer and the first region.

[0263] Example B56. A device comprising: a layer of glass; a through hole extending from the upper surface of the layer of glass to the lower surface of the layer of glass; wherein a first region of the through hole comprises a first metal, the first region of the through hole substantially filling the through hole, the first metal substantially filling the first region of the through hole; a first layer comprising a dielectric material, wherein the first layer is located on the upper surface of the layer of glass, the first layer includes a first opening through which the first region of the through hole extends, the first layer includes a first overhang extending beyond the side wall of the through hole, the first overhang is A device comprising: a first protruding portion extending into the through hole; a second layer comprising a dielectric material, wherein the second layer is located on the lower surface of the glass layer, the second layer includes a second opening through which the first region of the through hole extends, the second layer includes a second protrusion extending beyond the side wall of the through hole, the second protrusion includes a second protruding portion extending into the through hole; and an integrated circuit component located on the upper surface of the glass layer, the conductive contacts of the integrated circuit component being electrically coupled to the first region.

[0264] Example B57 includes the device described in Example B56, wherein the first and second overhangs have substantially triangular cross-sectional shapes.

[0265] Example B58 includes the device described in Example B56, wherein the first and second protruding portions have substantially quarter-circular cross-sectional shapes.

[0266] Example B59 includes a device according to any one of Examples B56 to B58, wherein the first protruding portion extends downward by a first distance within the through hole at the inner peripheral portion of the first protruding portion, and the first protruding portion extends downward by a second distance within the through hole at the outer peripheral portion of the first protruding portion, and the first distance is greater than the second distance.

[0267] Example B60 includes a device according to any one of Examples B56 to B59, wherein the dielectric material comprises a polymer containing carbon and oxygen.

[0268] Example B61 includes the device according to any one of Example B60, wherein the dielectric material further comprises silicon.

[0269] Example B62 includes a device according to any one of Examples B56 to B60, wherein the dielectric material comprises carbon and nitrogen.

[0270] Example B63 includes the device according to any one of Examples B56 to B62, wherein the glass layer contains at least 23 weight percent silicon, at least 26 weight percent oxygen, and further at least 5 weight percent aluminum.

[0271] Example B64 includes the device described in any one of Examples B56 to B63, wherein the glass layer does not contain an organic adhesive or organic material.

[0272] Example B65 includes the device described in any one of Examples B56 to B64, wherein the glass layer is amorphous.

[0273] Example B66.1 includes the device described in any one of Examples B56 to B65, wherein the glass layer comprises silicon, oxygen, and aluminum.

[0274] Example B66 includes a device according to any one of Examples B56 to B65, wherein the glass layer is a solid glass layer and has a rectangular shape in a plan view.

[0275] Example B67 includes the device according to any one of Examples B56 to B66, further comprising: a third layer containing silicon and nitrogen located between the first layer and the upper surface of the glass layer; and a fourth layer containing silicon and nitrogen located between the second layer and the lower surface of the glass layer.

[0276] Example B68 further comprises the device according to Example B67, wherein the third layer substantially fills the first opening, and a fifth layer comprising a second metal is further included.

[0277] Example B69 includes the device described in Example B54 or B68, wherein the second metal is copper.

[0278] Example B70 includes the device described in Example B54 or B68, wherein the second metal is silver, gold, nickel, tungsten, cobalt, or aluminum.

[0279] Example B71 includes the device described in any one of Examples B39 to B70, wherein the first metal includes copper.

[0280] Example B72 includes the device described in any one of Examples B39 to B70, wherein the first metal includes nickel, tungsten, molybdenum, platinum, gold, silver, or aluminum.

[0281] Example B73 includes a device according to any one of Examples B56 to B72, further comprising a first layer located on the side wall of the through hole, the first layer comprising a second metal; and a second layer comprising a third metal, wherein the first layer is located between the side wall and the second layer, and the second layer is located between the first layer and the first region.

[0282] Example B74 includes the device described in Example B55 or B73, wherein the first layer comprises titanium and the second layer comprises copper.

[0283] Example B75 includes the device described in Example B73, wherein the upper portion of the first layer is positioned between the first overhang and the glass layer, and the lower portion of the first layer is positioned between the second overhang and the glass layer.

[0284] Example B76 includes the device described in Example B55 or B73, wherein the second layer comprises titanium and the third layer comprises silver.

[0285] Example B77 includes the device according to Example B55 or B73, wherein the second layer contains titanium and the third layer contains gold.

[0286] Example B78. A method comprising forming a structure, the steps of forming through holes in a glass layer, where the through holes extend from the upper surface of the glass layer to the lower surface of the glass layer; forming an adhesion promoting layer on the sidewalls of the through holes, the upper surface of the glass layer, and the lower surface of the glass layer; forming a dielectric layer on the upper surface of the glass layer, a portion of the dielectric layer extending into the through holes; forming holes in the dielectric layer, the holes being positioned above the through holes; forming a seed layer on the adhesion promoting seed layer within the through holes; and plating the seed layer with a metal, where the through holes are substantially filled with the metal as a result of the plating, to form a structure; and etching and planarizing the structure, where etching and planarizing leave a region of the metal substantially filling the through holes, a portion of the dielectric layer within the through holes, the upper surface of the region of the metal having a first peripheral portion, the through holes having a second peripheral portion on the upper surface of the glass layer, the portion of the dielectric layer within the through holes having an upper surface positioned between the first peripheral portion and the second peripheral portion, and the portion of the dielectric layer within the through holes extending within the through holes a maximum distance less than 10% of the height of the glass layer.

[0287] Example B79 includes the method according to Example B78, wherein the portion of the dielectric layer within the through holes has an annular or rounded rectangular shape in a plan view.

[0288] Example B80 includes the method according to Example B78 or B79, wherein a first thickness of the portion of the dielectric layer within the through holes at an inner peripheral portion of the portion of the dielectric layer within the through holes is greater than a second thickness of the portion of the dielectric layer within the through holes at an outer peripheral portion of the portion of the dielectric layer within the through holes.

[0289] Example B81 includes the method according to any one of Examples B78 to B80, wherein the portion of the dielectric layer within the through hole has a substantially quarter-circular cross-sectional shape.

[0290] Example B82. A method comprising the steps of: forming a through hole in a glass layer, the through hole extending from the upper surface to the lower surface of the glass layer; forming an adhesion-promoting layer on the sidewall of the through hole, the upper surface of the glass layer, and the lower surface of the glass layer; forming a dielectric layer on the upper surface of the glass layer, the portion of which of the dielectric layer extends into the through hole, and the dielectric layer comprises a dielectric material; forming an opening in the dielectric layer, the opening positioned above the through hole, and the dielectric layer including a projection extending beyond the sidewall of the through hole as a result of the formation of the opening in the dielectric layer, the projection including a projection portion extending into the through hole; forming a seed layer in the adhesion-promoting layer within the through hole; and plating the seed layer with a metal, the through hole being substantially filled with the metal as a result of the plating.

[0291] Example B83 includes the method of Example B82, wherein the protruding portion has a substantially triangular cross-sectional shape.

[0292] Example B84 includes the method of Example B82, wherein the protruding portion has a substantially quarter-circular cross-sectional shape.

[0293] Example B85 includes the method according to any one of Examples B82 to B84, wherein the protruding portion extends downward by a first distance within the through hole at the inner peripheral portion of the protruding portion, and the protruding portion extends downward by a second distance within the through hole at the outer peripheral portion of the protruding portion, and the first distance is greater than the second distance.

[0294] Example B86 includes a method according to any one of Examples B82 to B85, wherein the dielectric material comprises a polymer containing carbon and oxygen.

[0295] Example B87 includes the method of any one of Example B86, wherein the dielectric material further comprises silicon.

[0296] Example B88 includes a method according to any one of Examples B82 to B87, wherein the dielectric material comprises carbon and nitrogen.

[0297] Example B89 includes the method according to any one of Examples B78 to B88, wherein the glass layer comprises silicon; oxygen; and one or more of aluminum, boron, magnesium, calcium, barium, tin, sodium, potassium, strontium, phosphorus, zirconium, lithium, titanium, and zinc.

[0298] Example B90 includes the method according to any one of Examples B78 to B88, wherein the glass layer comprises aluminosilicate glass, borosilicate glass, aluminoborosilicate glass, silica, or fused silica.

[0299] Example B91 includes the method according to any one of Examples B78 to B88, wherein the glass layer comprises at least 23 weight percent silicon, at least 26 weight percent oxygen, and further at least 5 weight percent aluminum.

[0300] Example B92 includes a method according to any one of Examples B78 to B91, wherein the glass layer does not contain an organic adhesive or organic material.

[0301] Example B93 includes a method according to any one of Examples B78 to B92, wherein the glass layer is amorphous.

[0302] Example B93.1 includes the method according to any one of Examples B78 to B92, wherein the glass layer is solid and has a rectangular shape in a plan view.

[0303] Example B94 includes a method according to any one of Examples B78 to B93, further comprising the step of attaching an integrated circuit component to the structure.

[0304] Example B95 includes the apparatus or device according to any one of Examples B1 to B77, wherein the glass layer has a thickness in the range of about 50 microns to about 1.4 millimeters, a first length in the range of about 10 millimeters to about 250 millimeters, and a second length in the range of about 10 millimeters to about 250 millimeters, and the first length is perpendicular to the second length.

[0305] Example B96 includes the apparatus or device according to any one of Examples B1 to B77, wherein the glass layer has a rectangular prism volume.

[0306] Example B97 includes the apparatus or device according to any one of Examples B1 to B77, wherein the glass layer has a rectangular prism volume having a first side and a second side perpendicular to the first side, the first side having a length in the range of 10 millimeters to about 250 millimeters, and the second side having a length in the range of about 10 millimeters to about 250 millimeters. (Other possible items) (Item 1) A glass layer; and A through hole extending from the upper surface of the glass layer to the lower surface of the glass layer An apparatus comprising: a first metal substantially filling a first region of the through hole within a first distance from the upper surface of the glass layer and within a second distance from the lower surface of the glass layer; a second metal substantially filling a second region of the through hole located between the upper surface of the first region and the upper surface of the glass layer; and the second metal substantially filling a third region of the through hole located between the lower surface of the first region and the lower surface of the glass layer. (Item 2) The apparatus according to Item 1, wherein the second metal is tin. (Item 3) The apparatus according to Item 1, wherein the second region and the third region further contain silver, copper, nickel, antimony, indium, palladium, or bismuth. (Item 4) The apparatus according to item 1, wherein the second region and the third region contain a paste containing the second metal. (Item 5) The apparatus according to item 1, wherein the first metal is copper, nickel, tungsten, molybdenum, platinum, gold, silver, or aluminum. (Item 6) A first layer having a third metal, the first layer being located on the side wall of the through hole, the upper end of the first layer substantially coinciding with the upper surface of the first region, and the lower end of the first layer substantially coinciding with the lower surface of the first region; and A second layer having a fourth metal, the second layer being located on the first layer between the first layer and the first region, the upper end of the second layer substantially coinciding with the upper surface of the first region, and the lower end of the second layer substantially coinciding with the lower surface of the first region. The apparatus described in item 1, further comprising the above. (Item 7) The apparatus according to item 6, wherein the first layer contains titanium and the second layer contains copper, silver, or gold. (Item 8) A layer of glass containing silicon, oxygen, and aluminum; and A through hole extending from the upper surface to the lower surface of the glass layer. Apparatus comprising, wherein a first metal substantially fills a first region of the through-hole up to a first distance from the upper surface of the glass layer and up to a second distance from the lower surface of the glass layer, and substantial portions of the particles in the first region are of a size within a first range of particle sizes; a second metal substantially fills a second region of the through-hole located between the upper surface of the first metal and the upper surface of the glass layer, and the second metal substantially fills a third region of the through-hole located between the lower surface of the first metal and the lower surface of the glass layer, and substantial portions of the particles in the second and third regions are within a second range of particle sizes, and the lower end of the first range of particle sizes is greater than the upper end of the second range of particle sizes. (Item 9) The apparatus according to item 8, wherein the first range of particle size is approximately 1 micron to 10 microns, and the second range of particle size is less than approximately 1 micron. (Item 10) The apparatus according to item 8, wherein the second metal is copper. (Item 11) The apparatus according to item 8, wherein the second metal is nickel, palladium, gold, or silver. (Item 12) The apparatus according to item 8, wherein the first metal is copper, nickel, tungsten, molybdenum, platinum, gold, silver, or aluminum. (Item 13) A first layer having a third metal, the first layer being located on the side wall of the through hole, the upper end of the first layer substantially coinciding with the upper surface of the first region, and the lower end of the first layer substantially coinciding with the lower surface of the first region; and A second layer having a fourth metal, the second layer being located on the first layer between the first layer and the first region, the upper end of the second layer substantially coinciding with the upper surface of the first region, and the lower end of the second layer substantially coinciding with the lower surface of the first region. The apparatus described in item 8, further comprising the above. (Item 14) The apparatus according to item 13, wherein the first layer has titanium and the second layer has copper, silver, or gold. (Item 15) A layer of glass; A through-hole extending from the upper surface to the lower surface of the glass layer, wherein a first metal substantially fills a first region of the through-hole up to a first distance from the upper surface of the glass layer and up to a second distance from the lower surface of the glass layer; a second metal substantially fills a second region of the through-hole located between the upper surface of the first region and the upper surface of the glass layer; and a third region of the through-hole located between the lower surface of the first region and the lower surface of the glass layer; and An integrated circuit component located on the upper surface of the glass layer, and a conductive contact of the integrated circuit component, are electrically coupled to the first region. A device equipped with the following features. (Item 16) The device described in item 15, wherein the second metal is tin. (Item 17) The device according to item 15, wherein the second and third regions further include silver, copper, nickel, antimony, indium, palladium, or bismuth. (Item 18) The device according to item 15, wherein the integrated circuit component is a first integrated circuit component, and the device further comprises a second integrated circuit component located on the lower surface of the glass layer, the second integrated circuit component being electrically coupled to the first region. (Item 19) The device according to item 15, further comprising a printed circuit board, wherein the glass layer is located on the printed circuit board, and conductive contacts of the printed circuit board are electrically coupled to the first region. (Item 20) The device according to item 19, wherein the device further comprises a battery and / or antenna located on the printed circuit board.

Claims

1. A layer of glass; and A through hole extending from the upper surface to the lower surface of the glass layer. The apparatus comprises, wherein the first metal substantially fills a first region of the through-hole up to a first distance from the upper surface of the glass layer and up to a second distance from the lower surface of the glass layer; the second metal substantially fills a second region of the through-hole located between the upper surface of the first region and the upper surface of the glass layer; and the second metal substantially fills a third region of the through-hole located between the lower surface of the first region and the lower surface of the glass layer.

2. The apparatus according to claim 1, wherein the second metal is tin.

3. The apparatus according to claim 1, wherein the second region and the third region further include silver, copper, nickel, antimony, indium, palladium, or bismuth.

4. The apparatus according to claim 1, wherein the second region and the third region contain a paste containing the second metal.

5. The apparatus according to claim 1, wherein the first metal is copper, nickel, tungsten, molybdenum, platinum, gold, silver, or aluminum.

6. A layer of glass; and A through hole extending from the upper surface to the lower surface of the glass layer. Apparatus comprising, wherein a first metal substantially fills a first region of the through-hole up to a first distance from the upper surface of the glass layer and up to a second distance from the lower surface of the glass layer, and a substantial portion of the particles in the first region are of a size within a first range of particle sizes; a second metal substantially fills a second region of the through-hole located between the upper surface of the first metal and the upper surface of the glass layer, and the second metal substantially fills a third region of the through-hole located between the lower surface of the first metal and the lower surface of the glass layer, and a substantial portion of the particles in the second and third regions are within a second range of particle sizes, and the lower end of the first range of particle sizes is greater than the upper end of the second range of particle sizes.

7. The apparatus according to claim 6, wherein the first range of particle size is about 1 micron to 10 microns, and the second range of particle size is less than about 1 micron.

8. The apparatus according to claim 6, wherein the second metal is copper.

9. The apparatus according to claim 6, wherein the second metal is nickel, palladium, gold, or silver.

10. A first layer having a third metal, the first layer being located on the side wall of the through hole, the upper end of the first layer substantially coinciding with the upper surface of the first region, and the lower end of the first layer substantially coinciding with the lower surface of the first region; and A second layer having a fourth metal, the second layer being located on the first layer between the first layer and the first region, the upper end of the second layer substantially coinciding with the upper surface of the first region, and the lower end of the second layer substantially coinciding with the lower surface of the first region. The apparatus according to claim 1, further comprising:

11. The apparatus according to claim 10, wherein the first layer has titanium and the second layer has copper.

12. The apparatus according to claim 10, wherein the first layer has titanium and the second layer has copper, silver, or gold.

13. The apparatus according to claim 1, wherein the first metal is copper.

14. The apparatus according to claim 1, wherein the first metal is nickel, tungsten, molybdenum, platinum, gold, silver, or aluminum.

15. The aforementioned glass layer, silicon; oxygen; and One or more of the following: aluminum, boron, magnesium, calcium, barium, tin, sodium, potassium, strontium, phosphorus, zirconium, lithium, titanium, and zinc. The apparatus according to claim 1, having the following features.

16. A first layer having silicon and nitrogen located on the upper surface of the glass layer, the first layer having a first opening above the first region; and A second layer having a dielectric material located in the first layer, wherein the second layer has a second opening above the first region. The apparatus according to claim 1, further comprising:

17. The apparatus according to claim 16, wherein the dielectric material comprises carbon and nitrogen.

18. The apparatus according to claim 16, wherein the dielectric material comprises a polymer containing carbon and oxygen.

19. A third layer comprising a third metal, the third layer substantially filling the first opening and the second opening. The apparatus according to claim 16, further comprising:

20. The apparatus according to claim 19, wherein the third metal is copper.

21. The apparatus according to claim 19, wherein the third metal is silver, gold, nickel, tungsten, cobalt, or aluminum.

22. A device comprising the apparatus according to any one of claims 1 to 21, and an integrated circuit component located on the upper surface of the glass layer, wherein the conductive contacts of the integrated circuit component are electrically coupled to the first region.

23. The device according to claim 22, wherein the integrated circuit component is a first integrated circuit component, and the device further comprises a second integrated circuit component located on the lower surface of the glass layer, the second integrated circuit component being electrically coupled to the first region.

24. The device according to claim 22, further comprising a printed circuit board, wherein the glass layer is located on the printed circuit board, and conductive contacts of the printed circuit board are electrically coupled to the first region.

25. The device according to claim 24, wherein the device further comprises a battery and / or an antenna located on the printed circuit board.

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