Test equipment, test method, and test system
The use of a machine learning model to predict trim values for functional circuits on wafers reduces testing time and costs, addressing the redundancy and cost issues in existing test processes.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- NUVOTON
- Filing Date
- 2025-11-12
- Publication Date
- 2026-06-22
AI Technical Summary
The existing test process for unpackaged dies on a wafer is redundant and costly due to the need for extensive testing to obtain trim values for each die, which increases testing time and costs.
A test apparatus and method utilizing a machine learning model to predict trim values by training on sample wafers and applying the learned model to test wafers, converting process parameters to trim values for functional circuits.
This approach significantly reduces testing time and costs while improving product quality by accurately predicting trim values for functional circuits, thereby enhancing yield and efficiency.
Smart Images
Figure 2026101613000001_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a test apparatus, and more particularly to a test apparatus that predicts a trim value of a wafer using a machine learning model.
Background Art
[0002] On a completed wafer, dies in an unpackaged state are regularly arranged. In order to operate the functional circuits of each die normally, in the test process, first, each die needs to be actually tested to obtain the trim value of each die. Therefore, the test process is extremely redundant and requires a large amount of test costs.
Summary of the Invention
Problems to be Solved by the Invention
[0003] An object of the present invention is to provide a test apparatus having a memory circuit and a processing circuit.
Means for Solving the Problems
[0004] The test apparatus of the present invention comprises a memory circuit and a processing circuit. The memory circuit stores a machine learning model. The processing circuit accesses the memory circuit. In training mode, the processing circuit is electrically connected to a sample wafer. The sample wafer has multiple sample dies. The processing circuit loads the machine learning model and trains the machine learning model to predict the process parameters of each sample die by inputting wafer acceptance test sample data of the sample wafer into the machine learning model. In test mode, the processing circuit is electrically connected to the wafer under test. The wafer under test has multiple test dies. The processing circuit inputs wafer acceptance test data of the wafer under test into the machine learning model to predict the process parameters of each test die on the wafer under test. The processing circuit converts the process parameters of each test die to generate trim values and provides the trim values to the first functional circuit of the corresponding test die.
[0005] The present invention further provides a test method. The test method comprises the steps of: electrically connecting to a sample wafer having a plurality of sample dies in training mode; inputting wafer acceptance test sample data of the sample wafer into a machine learning model to train the machine learning model to predict the process parameters of each sample die; electrically connecting to a wafer under test having a plurality of dies under test in test mode; inputting wafer acceptance test data of the wafer under test into a machine learning model so that the machine learning model predicts the process parameters of each die under test; converting the process parameters of each die under test to generate trim values; and providing the trim values to the functional circuits of the corresponding dies under test.
[0006] The test method of the present invention can be carried out by the test apparatus and test system of the present invention. These may be hardware or firmware capable of performing specific functions, or they may be stored on a recording medium in the form of program code and implemented in combination with specific hardware. When the program code is loaded into and executed by an electronic device, processor, computer, or machine, the electronic device, processor, computer, or machine will execute the test apparatus and test system of the present invention. [Effects of the Invention]
[0007] This invention makes it possible to shorten testing time, reduce testing costs, and improve product quality. [Brief explanation of the drawing]
[0008] [Figure 1A] This is a flowchart of the test method of the present invention. [Figure 1B] This figure shows another test method of the present invention. [Figure 2] This is a diagram showing a wafer map. [Figure 3] This is a schematic diagram of the test system of the present invention. [Modes for carrying out the invention]
[0009] To make the object, features, and advantages of the present invention clearer and easier to understand, embodiments are described below in detail with reference to the accompanying drawings. The specification of the present invention provides different embodiments to illustrate various embodiments of the present invention, and the arrangement of components in each embodiment is for illustrative purposes only and does not limit the present invention. Furthermore, some reference numerals in the drawings are duplicated in the embodiments for the purpose of simplifying the explanation and do not imply any relationship between different embodiments.
[0010] Figure 1A is a flowchart of the test method of the present invention. The test method of the present invention may exist as program code. When the program code is loaded into the device and executed, the device becomes a test apparatus and test system for carrying out the test method of the present invention. First, in training mode, a training operation is performed on a sample wafer (step S110). The sample wafer has a plurality of sample dies.
[0011] Sample wafer acceptance test (WAT) data from the sample wafer is input into a machine learning model (step S111). The machine learning model inferences the process parameters of each sample die based on the WAT sample data of the sample wafer. In one embodiment, the manufacturer of the sample wafer sets up at least one test point on the sample wafer to test the process yield of the sample wafer and performs initial electrical measurements, such as capacitance, current, voltage, and resistance, on the test point. The manufacturer uses these measurement results as WAT sample data. In this example, the machine learning model calculates the WAT sample data of the sample wafer and predicts the process parameters of each sample die. In some embodiments, the process parameters may be the drain current (Idsat) of a MOS transistor in the saturation region, the threshold voltage (Vth) of a MOS transistor, or the leakage current (Ioff) when the MOS transistor is off, the capacitance value of a metal-oxide-metal (MOM) capacitor, or the resistance value of a non-silicide resistor.
[0012] In other embodiments, step S111 further inputs a wafer map of the sample wafer into the machine learning model. Figure 2 shows an example of a wafer map. The wafer map 200 shows the positions of all sample die SDs on the sample wafer, and the test point TA ~This shows the location of TI. In this example, the WAT sample data is the test point TA. ~ TI's process parameters are being recorded.
[0013] A machine learning model can predict the process parameters of each sample die based on the wafer map 200 and WAT sample data. In one embodiment, the machine learning model calculates the relative distance between each sample die SD and at least one test point. The machine learning model constructs at least one correction between the relative distance between each sample die and at least one test point and the process parameters of the corresponding test point. In this example, the machine learning model predicts the process parameters of each sample die based on these corrections.
[0014] Let's take sample die SD_S as an example. Suppose a machine learning model calculates the relative distances DSA, DSB, DSF, DSH, and DSI between sample die SD_S and test points TA, TB, TF, TH, and TI. The machine learning model constructs a first correlation between relative distance DSA and the process parameter of the corresponding test point TA, a second correlation between relative distance DSB and the process parameter of the corresponding test point TB, a third correlation between relative distance DSF and the process parameter of the corresponding test point TF, a fourth correlation between relative distance DSH and the process parameter of the corresponding test point TH, and a fifth correlation between relative distance DSI and the process parameter of the corresponding test point TI. Based on the first to fifth correlations, the machine learning model predicts the process parameter of sample die SD_S.
[0015] In other embodiments, the machine learning model may calculate the relative distance between the sample die SD_S and more or fewer test points. The present invention does not limit how the machine learning model constructs a correlation between the sample die SD_S and at least one test point. In some embodiments, the process parameters of the sample die SD_S may approximate the process parameters of the test point TA because the relative distance DSA is smaller than the relative distances DSB, DSF, DSH, and DSI. Therefore, the machine learning model may predict the process parameters of the sample die SD_S based on the relative distance DSA and the process parameters of the test point TA.
[0016] Next, in test mode, a test operation is performed on the wafer under test (step S120). The wafer under test has multiple dies under test. In one embodiment, the wafer under test has the same specifications as the sample wafer. First, the WAT data of the wafer under test is input to a trained machine learning model to predict at least one process parameter for each die under test (step S121). In one embodiment, step S121 further inputs the wafer map of the wafer under test to the machine learning model. In this example, since the wafer under test and the sample wafer have the same specifications, the wafer map of the wafer under test is the same as the wafer map of the sample wafer. In some embodiments, step S121 writes the process parameters of each die under test to the corresponding die under test.
[0017] Next, the process parameters of each die under test are converted to generate trim values, and each trim value is provided to the corresponding die under test (step S122). In one embodiment, in step S122, each trim value is stored in the corresponding die under test. In this example, at least one functional circuit in the die under test operates based on the corresponding trim value.
[0018] Subsequently, it is determined whether the output of a predetermined functional circuit (also referred to as the first functional circuit) in each die under test conforms to the test standard (step S123). In one embodiment, each die under test has a plurality of functional circuits. The present invention does not limit the type and quantity of the functional circuits provided in the die under test. Any electronic circuit can be provided in the die under test.
[0019] If the outputs of the predetermined functional circuits in all the dies under test conform to the test standard, the test operation S120 is terminated. However, if the output of a predetermined functional circuit in a die under test does not conform to the test standard, the trim value of the predetermined functional circuit in the die under test is adjusted (step S124). Thereafter, it is determined again whether the output of the predetermined functional circuit in the die under test after adjustment conforms to the test standard (step S123).
[0020] According to the trim value predicted by the trained machine learning model, the outputs of most of the predetermined functional circuits should conform to the test standard. Even if the outputs of a small number of predetermined functional circuits do not conform to the test standard, only the trim values of the small number of predetermined functional circuits need to be corrected. Therefore, the test time can be shortened, the test cost can be reduced, and the product quality can be improved.
[0021] FIG. 1B is a diagram showing another test method of the present invention. FIG. 1B is similar to FIG. 1A, but the difference is that the training operation S110 in FIG. 1B further includes steps S112 to S114. After predicting the process parameters of the sample die, the machine learning model converts the process parameters of each sample die to generate at least one trim value and provides each trim value to the corresponding sample die (step S112). In one embodiment, step S112 writes each trim value to the corresponding sample die.
[0022] In some embodiments, the functional circuit (also referred to as the second functional circuit) within each sample die generates an output signal based on a trim value. The present invention does not limit the type of the second functional circuit. In one embodiment, the second functional circuit is a resistor-capacitor oscillator (RC oscillator). In this case, each sample die has a resistor-capacitor oscillator. The resistor-capacitor oscillator of each sample die generates a clock signal based on the trim value generated in step S112.
[0023] Next, it is determined whether the yield of the sample die exceeds a target value (step S113). In one embodiment, step S113 is a step of determining whether the frequency of the output signal of the second functional circuit conforms to a predetermined value. When the frequency of the output signal of the second functional circuit of the sample die conforms to the predetermined value, it indicates that the sample die is a good product. However, when the frequency of the output signal of the second functional circuit of the sample die does not conform to the predetermined value, it indicates that the sample die is a defective product. When the quantity of defective products is less than the threshold value, it means that the yield of the sample die exceeds the target value. Thereby, the test operation S120 is started for the test wafer. When the quantity of defective products exceeds the threshold value, it means that the yield of the sample die does not exceed the target value. Therefore, the parameters of the machine learning model are adjusted until the yield of the sample die exceeds the target value (step S114).
[0024] FIG. 3 is a schematic diagram of the test system of the present invention. As shown in the figure, the test system 300 has a test device 310 and a test platform 320. The test platform 320 is used to mount the wafer WF. During the training period, a test operator (or a robotic arm) places the sample wafer 331 on the test platform 320. During the test period, the test wafer 332 is placed on the test platform 320.
[0025] The test apparatus 310 is electrically connected to the wafer WF via the test platform 320. During the training period, the test apparatus 310 performs training operations on the machine learning model ML using the sample wafer 331. During the test period, the test apparatus 310 performs test operations on the wafer under test 332 using the trained machine learning model ML. In this embodiment, the test apparatus 310 includes a memory circuit 311 and a processing circuit 312.
[0026] The memory circuit 311 stores the machine learning model ML. In some embodiments, the memory circuit 311 further stores the WAT sample data WS and wafer map MS of the sample wafer 331, and the WAT data WT and wafer map MT of the wafer under test 332. In one embodiment, if the sample wafer 331 and the wafer under test 332 have the same specifications, the wafer map MS is the same as the wafer map MT.
[0027] In other embodiments, the test apparatus 310 further includes an input / output interface 313. The input / output interface 313 receives external data and writes the external data to the memory circuit 311. In one embodiment, the external data includes at least one of a machine learning model ML, WAT sample data WS, wafer map MS, WAT data WT, and wafer map MT. In some embodiments, the input / output interface 313 further outputs the test results of the wafer under test 332.
[0028] In training mode, a sample wafer 331 is placed on the test platform 320. The sample wafer 331 has multiple sample dies. The processing circuit 312 uses the sample wafer 331 to perform training operations on the machine learning model ML. In this mode, the processing circuit 312 accesses the memory circuit 311 to load the machine learning model ML. The processing circuit 312 inputs the WAT sample data WS into the machine learning model ML and trains the machine learning model ML to predict the process parameters of each sample die.
[0029] In another embodiment, the processing circuit 312 inputs the WAT sample data WS and the wafer map MS to the machine learning model ML. In this example, the machine learning model ML calculates the WAT sample data WS and the wafer map MS to predict the process parameters of all sample dies on the sample wafer 331.
[0030] The present invention does not limit how the machine learning model ML calculates the WAT sample data WS and the wafer map MS. In one embodiment, the machine learning model ML determines the relative distance between each sample die of the sample wafer 331 and at least one test point based on the wafer map MS and the WAT sample data WS, and constructs multiple correlations between the distance between each sample die and the test point and the process parameters of the test point. In this example, the machine learning model ML predicts the process parameters of each sample die based on these correlations.
[0031] After completing the training operation, the processing circuit 312 writes the trained machine learning model ML to the memory circuit 311 and switches to test mode. In test mode, the wafer under test 332 is placed on the test platform 320. The wafer under test 332 has multiple dies under test. The processing circuit 312 performs test operations on the wafer under test 332 using the trained machine learning model ML. In this mode, the processing circuit 312 accesses the memory circuit 311 to load the trained machine learning model ML and further inputs WAT data WT to the machine learning model ML in order to predict at least one process parameter of each die under test on the wafer under test 332.
[0032] In one embodiment, the processing circuit 312 further inputs the wafer map MT to a machine learning model ML. The machine learning model ML calculates the WAT data WT and the wafer map MT to predict at least one process parameter for each die under test. In some embodiments, the processing circuit 312 writes each process parameter to the corresponding die under test. In this example, each die under test has non-volatile memory (NVM) for storing the process parameters.
[0033] In test mode, the processing circuit 312 converts the process parameters of each die under test to generate at least one trim value and provides the trim value to the corresponding functional circuit (or first functional circuit) of the die under test. In one embodiment, the processing circuit 312 writes each trim value to the non-volatile memory of the die under test.
[0034] Each die under test operates based on its corresponding trim value. In test mode, the processing circuit 312 determines whether the output of each first functional circuit conforms to the test standard. If the output of a particular circuit among the first functional circuits does not conform to the test standard, the processing circuit 312 adjusts the trim value of that particular circuit.
[0035] In other embodiments, in training mode, the processing circuit 312 converts the process parameters of each sample die to generate at least one trim value and writes each trim value to the corresponding sample die. In this example, the functional circuit (or second functional circuit) of each sample die generates an output signal based on the corresponding trim value. Based on the output signal of each sample die, the processing circuit 312 determines whether the yield of the sample die exceeds a target value. The present invention does not limit the type of second functional circuit. In one embodiment, the second functional circuit is a resistive-capacitive oscillator circuit, which generates a clock signal based on the corresponding trim value.
[0036] The present invention does not limit how the processing circuit 312 determines whether the yield of sample dies exceeds a target value. In one embodiment, the processing circuit 312 determines whether the output signal of each sample die conforms to a predetermined value. If the output signal of a sample die conforms to the predetermined value, the sample die is considered good. If the output signal of a sample die does not conform to the predetermined value, the sample die is considered defective. In this example, the processing circuit 312 determines whether the number of defective products is less than a threshold value. If the number of defective products is less than the threshold value, it means that the yield of sample dies exceeds the target value. Therefore, the processing circuit 312 switches to test mode. If the number of defective products exceeds the threshold value, it means that the yield of sample dies does not exceed the target value. Therefore, the processing circuit 312 adjusts the parameters of the machine learning model ML until the yield of sample dies exceeds the target value.
[0037] Using the machine learning model ML trained by the processing circuit 312, the process parameters of each die on the wafer 332 under test are predicted. These process parameters are then converted into trim values for the functional circuits of each die, and testing is initiated for each die. Most functional circuits pass the test, but some die functional circuits do not. The processing circuit 312 fine-tunes the corresponding trim values so that the functional circuits of some dies also pass the test. Therefore, the testing time for the wafer under test can be significantly reduced, testing costs can be lowered, and product quality can be improved.
[0038] The test method of the present invention, or a particular embodiment thereof, or a part thereof, may exist in the form of program code. The program code can be stored on a physical medium such as a floppy disk, optical disk, hard disk, or other machine-readable (e.g., computer-readable) storage medium. It may also exist as a computer program product, not limited to its external form. In this case, when the program code is read and executed by a machine such as a computer, that machine becomes a test apparatus and test system of the present invention. The program code can be transmitted by wires, cables, optical fibers, or any other transmission method. In this case, when the program code is received, read, and executed by a machine such as a computer, that machine becomes a test apparatus and test system for carrying out the test method of the present invention. When implemented in a general-purpose processor unit, the program code is combined with the processor unit to provide operation similar to that of a dedicated device using an ASIC.
[0039] Unless otherwise specified, all terms in this specification (including technical and scientific terms) should be interpreted in accordance with the general understanding of a person ordinary in the art. Furthermore, unless explicitly stated, definitions of terms should be interpreted in accordance with the definitions in general dictionaries and in accordance with their meanings in the relevant art literature, and not in an idealistic or overly formal manner. Terms such as "first," "second," etc., may be used to describe various components, but these components are not limited by these terms. These terms are used simply to distinguish one component from another. In the claims, terms such as "first," "second," etc., are used merely as symbols and are not intended to impose a numerical limitation on the subject matter.
[0040] Although the present invention has been disclosed with preferred embodiments as described above, this does not limit the invention. Those with ordinary skill in the art can make some modifications and alterations without departing from the spirit and scope of the invention. For example, the systems, apparatus, or methods described in the embodiments of the present invention can be implemented as specific embodiments of hardware, software, or a combination of hardware and software. Therefore, the scope of protection of the present invention is defined by the claims described below. [Explanation of symbols]
[0041] S110 training operation S120 Test Operation S111~S113, S121~S124 Step 200 wafer map SD Sample Die TA~TI Test Point DSA, DSB, DSF, DSH, DSI relative distance 300 Test Systems 310 Test equipment 320 Test Platforms WF wafer 331 Sample wafers 332 Test wafer 311 Memory circuit 312 Processing Circuit 313 Input / Output Interfaces ML Machine Learning Models WS, WT WAT data MS, MT wafer map
Claims
1. A test apparatus, A memory circuit for storing machine learning models, and The system includes a processing circuit that accesses the memory circuit, In training mode, The processing circuit is electrically connected to a sample wafer, and the sample wafer has a plurality of sample dies. The processing circuit loads the machine learning model and inputs wafer acceptance test sample data of the sample wafer into the machine learning model to train the machine learning model to predict the process parameters of each sample die of the sample wafer. In test mode, The processing circuit is electrically connected to the wafer under test, and the wafer under test has a plurality of dies under test. The processing circuit inputs wafer acceptance test data of the wafer under test into the machine learning model in order to predict the process parameters of each die under test. The processing circuit converts the process parameters of each die under test to generate trim values, and provides the trim values to the first functional circuit of the corresponding die under test. A test apparatus characterized by the following features.
2. A test method, In training mode, A process of electrically connecting a sample wafer having multiple sample dies, The process involves inputting wafer acceptance test sample data of the sample wafer into a machine learning model and training the machine learning model to predict the process parameters of each sample die. In test mode, A process of electrically connecting a wafer having multiple dies to be tested, The process involves inputting wafer acceptance test data of the wafer under test into the machine learning model so that the machine learning model predicts the process parameters of each die under test. A process of converting the process parameters of each die under test to generate trim values, The process of providing the trim value to the first functional circuit of the die under test, A test method characterized by having the following features.
3. It is a testing system, A test platform on which to place a sample wafer or wafer under test. A memory circuit for storing machine learning models, and The system includes a processing circuit that accesses the memory circuit, In training mode, The test platform is used to place the sample wafer, The processing circuit is electrically connected to the sample wafer, and the sample wafer has a plurality of sample dies. The processing circuit loads the machine learning model and inputs the wafer acceptance test sample data of the sample wafer into the machine learning model to train the machine learning model to predict the process parameters of each sample die. In test mode, The test platform is used to place the wafer under test, The processing circuit is electrically connected to the wafer under test, and the wafer under test has a plurality of dies under test. The processing circuit inputs wafer acceptance test data of the wafer under test into the machine learning model in order to predict the process parameters of each die under test. The processing circuit converts the process parameters of each die under test to generate trim values, and provides the trim values to the first functional circuit of the corresponding die under test. A testing system characterized by the following features.