Semiconductor device and method for manufacturing the same

Abstract

This provides a novel technology for forming metal patterns on a substrate. [Solution] The semiconductor device comprises an interlayer insulating film containing a cured product of a curable composition disposed on a semiconductor substrate, grooves provided in the cured product, and a metal pattern filled in the grooves.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same.

Background Art

[0002] As a method for forming a metal pattern on a substrate, the damascene method is known. In the damascene method, a wiring groove is formed in an interlayer insulating film, a metal film is formed on the interlayer insulating film so that the wiring groove is filled with metal, and then the metal film other than in the wiring groove is removed by a CMP method. In such a method, for example, there are problems such as that dishing may occur on the surface of the interlayer insulating film, or a limitation that a vacuum process is required for the formation and processing of the interlayer insulating film, or a limitation that the choice of materials is limited.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] An object of the present invention is to provide a novel technique for forming a metal pattern on a substrate.

Means for Solving the Problems

[0005] A first aspect of the present invention relates to a semiconductor device, the semiconductor device including an interlayer insulating film including a cured product of a curable composition disposed on a semiconductor substrate, a groove provided in the cured product, and a metal pattern filled in the groove.

[0006] A second aspect of the present invention relates to a method for manufacturing a semiconductor device, the manufacturing method comprising: a recess formation step of forming recesses in an interlayer insulating film disposed on a semiconductor substrate; a planarization step of forming a planarization film made of a first cured product of a first curable composition on the interlayer insulating film so as to fill the recesses; a pattern formation step of forming a pattern on the planarization film made of a second cured product of a second curable composition and having openings above the recesses; an etching step of etching the planarization film using the pattern so as to form grooves in the first cured product within the recesses; a metal film formation step of forming a metal film on the interlayer insulating film so as to fill the grooves with metal; and a polishing step of polishing the metal film by CMP so as to leave metal patterns in the grooves.

[0007] A third aspect of the present invention relates to a method for manufacturing a semiconductor device, the manufacturing method comprising: a recess formation step of forming recesses in an interlayer insulating film disposed on a semiconductor substrate; a pattern formation step of forming a pattern on the interlayer insulating film that is made of a curable composition and has openings above the recesses, so as to fill the recesses; an etching step of etching the entire pattern so as to form grooves in the curable composition within the recesses; a metal film formation step of forming a metal film on the pattern so as to fill the grooves with metal; and a polishing step of polishing the metal film by CMP so as to leave a metal pattern in the grooves.

[0008] A fourth aspect of the present invention relates to a method for manufacturing a semiconductor device, the manufacturing method comprising: an insulating film forming step of forming an insulating film having grooves made of a curable composition on a semiconductor substrate; a metal film forming step of forming a metal film on the insulating film such that metal fills the grooves; and a polishing step of polishing the metal film by CMP so that a metal pattern remains in the grooves. [Effects of the Invention]

[0009] The present invention provides a novel technique for forming a metal pattern on a substrate. [Brief explanation of the drawing]

[0010] [Figure 1] A schematic diagram showing the configuration of a planarization device. [Figure 2] A schematic diagram showing the configuration of an imprinting device. [Figure 3] A schematic diagram showing the cross-sectional configuration of the semiconductor device of the first embodiment. [Figure 4] A schematic diagram showing the cross-sectional configuration of the semiconductor device of the first embodiment. [Figure 5] A figure showing a first example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 6] A figure showing a first example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 7] A figure showing a first example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 8] A figure showing a second example of the method for manufacturing a semiconductor device according to the first embodiment. [Figure 9] A figure showing a second example of the method for manufacturing a semiconductor device according to the first embodiment. [Figure 10] A figure showing a second example of the method for manufacturing a semiconductor device according to the first embodiment. [Figure 11] A figure showing a third example of the method for manufacturing a semiconductor device according to the first embodiment. [Figure 12] A figure showing a third example of the method for manufacturing a semiconductor device according to the first embodiment. [Figure 13] A figure showing a fourth example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 14] A figure showing a fourth example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 15] A schematic diagram showing the cross-sectional configuration of the semiconductor device of the second embodiment. [Figure 16] A figure showing a first example of a method for manufacturing a semiconductor device according to a second embodiment. [Figure 17] A figure showing a first example of a method for manufacturing a semiconductor device according to a second embodiment. [Figure 18] A figure showing a second example of a method for manufacturing a semiconductor device according to the second embodiment. [Modes for carrying out the invention]

[0011] Hereinafter, preferred embodiments of the present invention will be described in detail based on the accompanying drawings. Note that the following embodiments do not limit the invention according to the claims. Although a plurality of features are described in the embodiments, not all of these plurality of features are essential to the invention, and the plurality of features may be arbitrarily combined. Further, in the accompanying drawings, the same or similar configurations are denoted by the same reference numerals, and redundant descriptions are omitted.

[0012] First, before describing the manufacturing method of the semiconductor device of the present embodiment, a planarization device and an imprint device that can be used in the manufacturing method will be exemplarily described. The planarization device and the imprint device are devices that form a film made of a cured product of a curable composition portion by applying curing energy to the curable composition disposed on a substrate. The curable composition is a composition that cures when curing energy is applied. As the curing energy, electromagnetic waves, heat, etc. can be used. The electromagnetic wave can be, for example, light selected from the range of its wavelength being 10 nm or more and 1 mm or less, for example, infrared rays, visible light rays, ultraviolet rays, etc. The curable composition may be understood as a composition that cures by light irradiation or by heating. Among these, the photocurable composition that cures by light irradiation contains at least a polymerizable compound and a photoinitiator, and may further contain a non-polymerizable compound or a solvent as necessary. The non-polymerizable compound is at least one selected from the group consisting of a sensitizer, a hydrogen donor, an internal mold release agent, a surfactant, an antioxidant, a polymer component, etc. The curable composition can be disposed on the substrate in a droplet shape, or in an island shape or a film shape formed by connecting a plurality of droplets. Further, the curable composition may be supplied onto the substrate in a film shape by a spin coater or a slit coater. The viscosity of the imprint material (viscosity at 25°C) can be, for example, 1 mPa·s or more and 100 mPa·s or less.

[0013] FIG. 1 schematically shows the configuration of the planarization apparatus 1. The planarization apparatus 1 may include a substrate holding unit SH1 that holds the substrate S, and a substrate driving mechanism SD1 that drives the substrate S by driving the substrate holding unit SH1. The substrate driving mechanism SD1 may be configured to drive the substrate S about a plurality of axes (for example, three axes of an X axis, a Y axis, and a θZ axis, preferably, six axes of an X axis, a Y axis, a Z axis, a θX axis, a θY axis, and a θZ axis). The planarization apparatus 1 may also include a mold holding unit MH1 that holds the super straight SS as a mold having a surface for planarization, and a mold driving mechanism MD1 that drives the super straight SS by driving the mold holding unit MH1. The mold driving mechanism MD1 may be configured to drive the super straight SS about a plurality of axes (for example, three axes of a Z axis, a θX axis, and a θY axis, preferably, six axes of an X axis, a Y axis, a Z axis, a θX axis, a θY axis, and a θZ axis).

[0014] The planarization apparatus 1 may also include a shape control unit MD1 that controls the shape of the super straight SS with respect to the Z axis held by the mold holding unit MH1. The shape control unit MD1 may control the shape of the super straight SS with respect to the Z axis, for example, by adjusting the pressure on the back surface of the super straight SS held by the mold holding unit MH1 (the surface opposite to the surface having the pattern region in contact with the curable composition). Usually, when the pattern region of the super straight SS is brought into contact with the curable composition on the substrate S, the shape of the super straight SS may be controlled by the shape control unit CC1 so as to have a convex shape downward.

[0015] The planarization apparatus 1 may also include a curing unit CU1 that cures a curable composition by irradiating curing energy onto the curable composition filled in the space between multiple shot areas of the substrate S and the superstraight SS. The planarization apparatus 1 may also include a dispenser DU1 that places the curable composition on the multiple shot areas of the substrate S. However, the planarization apparatus 1 may be fed or supplied with a substrate S on which the curable composition has been placed on the multiple shot areas of the substrate S, in which case the dispenser DU1 is not necessary. The planarization apparatus 1 may also include an alignment scope AS1. The alignment scope AS1 may be used to detect the position of alignment marks provided on the substrate S.

[0016] The planarization apparatus 1 may also include a control unit CNT1 that controls the substrate holding unit SH1, substrate driving mechanism SD1, mold holding unit MH1, mold driving mechanism MD1, curing unit CU1, dispenser DU1, alignment scope AS1, shape control unit CC1, etc. The control unit CNT1 may be composed of, for example, a PLD (Programmable Logic Device) such as an FPGA (Field Programmable Gate Array), or an ASIC (Application Specific Integrated Circuit), or a general-purpose or dedicated computer with a program installed, or a combination of all or part of these.

[0017] Figure 2 schematically shows the configuration of the imprint apparatus 2. The imprint apparatus 2 may include a substrate holding unit SH2 that holds a substrate S, and a substrate driving mechanism SD2 that drives the substrate S by driving the substrate holding unit SH2. The substrate driving mechanism SD2 may be configured to drive the substrate S along multiple axes (for example, three axes: X axis, Y axis, and θZ axis; preferably, six axes: X axis, Y axis, Z axis, θX axis, θY axis, and θZ axis).

[0018] The imprint apparatus 2 may also include a mold holding unit MH2 for holding a mold M having a transfer surface for a three-dimensional structure to be transferred to a curable composition, and a mold driving mechanism MD2 for driving the mold M by driving the mold holding unit MH2. The mold driving mechanism MD2 may be configured to drive the mold M along a plurality of axes (for example, three axes: Z-axis, θX-axis, and θY-axis; preferably six axes: X-axis, Y-axis, Z-axis, θX-axis, θY-axis, and θZ-axis). The imprint apparatus 2 may also include a shape control unit CC2 for controlling the shape of the mold M with respect to the Z-axis held by the mold holding unit MH2. The shape control unit CC2 may control the shape of the mold M with respect to the Z-axis, for example, by adjusting the pressure on the back surface of the mold M held by the mold holding unit MH2 (the surface opposite to the surface having a pattern area that contacts the curable composition). Normally, when the transfer surface of the mold M is brought into contact with the curable composition on the substrate S, the shape of the mold M can be controlled by the shape control unit CC2 so that it has a convex shape directed downwards.

[0019] The imprint apparatus 2 may also include a curing unit CU2 that cures the curable composition by irradiating curing energy onto the curable composition filled in the space between the shot area of ​​the substrate S and the mold M. The imprint apparatus 2 may also include a dispenser DU2 that places the curable composition onto the shot area of ​​the substrate S. However, the imprint apparatus 2 may be fed or supplied with a substrate S on which the curable composition is placed on multiple shot areas of the substrate S, in which case the dispenser DU2 is not required. The imprint apparatus 2 may also include an alignment scope AS2. The alignment scope AS2 may be used to detect the position of alignment marks provided on the substrate S.

[0020] The imprint apparatus 2 may also include a control unit CNT2 that controls the substrate holding unit SH2, substrate driving mechanism SD2, mold holding unit MH2, mold driving mechanism MD2, curing unit CU2, dispenser DU2, alignment scope AS2, shape control unit CC2, etc. The control unit CNT2 may be composed of, for example, a PLD (Programmable Logic Device) such as an FPGA (Field Programmable Gate Array), or an ASIC (Application Specific Integrated Circuit), or a general-purpose or dedicated computer with a program installed, or a combination of all or part of these.

[0021] Figure 3 schematically shows a cross-sectional configuration of the semiconductor device 100 according to the first embodiment. The semiconductor device 100 may include an interlayer insulating film 124 containing a cured product 125 of a curable composition disposed on a semiconductor substrate 110, grooves TR provided in the cured product 125, and a metal pattern 126 filled in the grooves TR. The cured product 125 may be formed using a planarizing apparatus 1 and an imprinting apparatus 2. Alternatively, the cured product 125 may be formed using the imprinting apparatus 2. The curable composition may be a photocurable composition. The interlayer insulating film 124 may further include an inorganic insulating film having a recess, and the cured product 125 may be disposed in the recess. The inorganic insulating film may include, for example, at least one of a PSG (Phospho Silicate Glass) film, a BPSG (Boron Phospho Silicate Glass) film, and an SOG (Spin On Glass) film. Alternatively, the inorganic material film may include at least one of a SiN film, an SiO2 film, and a SiON film.

[0022] Although not shown in Figure 3, the entire interlayer insulating film 124 may be composed of a cured product 125. The semiconductor device 100 may further include via plugs 127 connected to a metal pattern 126. The via plugs 127 may be located in the interlayer insulating film 123, which is placed between the interlayer insulating film 124 and the semiconductor substrate 110. The metal pattern 126 and the via plugs 127 may be formed separately, for example, by a single damascene method, or they may be formed together, for example, by a dual damascene method. A barrier metal (not shown) may be placed between the groove TR and the metal pattern 126. The barrier metal may be formed of, for example, Ta, TaN, or TiN. The metal pattern 126 may be formed of, for example, copper, or an alloy mainly composed of copper.

[0023] In one aspect, the semiconductor device 100 may include a substrate SB1 comprising a semiconductor substrate 110 and a wiring structure 120. The wiring structure 120 may include an interlayer insulating film 124. Alternatively, the wiring structure 120 may include interlayer insulating films 124 and 123. Alternatively, the wiring structure 120 may include at least one interlayer insulating film 122 in addition to the interlayer insulating films 124 and 123. The interlayer insulating film 122 may be placed between the interlayer insulating film 123 and the semiconductor substrate 110. Multiple transistors tr may be placed on the semiconductor substrate 110.

[0024] The interlayer insulating films 122 and 123 may be composed of, for example, inorganic material films. These inorganic material films may include, for example, at least one of PSG films, BPSG films, SOG films, SiN films, SiO2 films, and SiON films. Alternatively, the interlayer insulating films 122 and 123 may be composed of organic material films.

[0025] In other aspects, the semiconductor device 100 may include a laminated structure including a substrate SB1 as a first substrate including a semiconductor substrate 110 and a wiring structure 120, and a substrate SB2 as a second substrate including a semiconductor substrate 130 and a wiring structure 140. In yet other aspects, the semiconductor device 100 is a semiconductor device having a substrate SB1 as a first substrate and a substrate SB2 as a second substrate. The semiconductor device 100 may further include one or more other substrates. The substrate SB1 has a metal pattern 126 as a first metal pattern, the substrate SB2 has a metal pattern 146 as a second metal pattern, and the semiconductor device 100 may have a structure in which the metal pattern 126 and the metal pattern 146 are joined together.

[0026] The substrate SB2 may comprise an interlayer insulating film 144 containing a cured product 145 of a curable composition disposed on a semiconductor substrate 130, grooves TR2 provided in the cured product 145, and a metal pattern 146 filled in the grooves TR2. The cured product 145 may be formed using a planarizing apparatus 1 and an imprinting apparatus 2. Alternatively, the cured product 145 may be formed using the imprinting apparatus 2. The curable composition may be a photocurable composition. The interlayer insulating film 144 may further include an inorganic insulating film having a recess, and the cured product 145 may be disposed in the recess. The inorganic material film may include, for example, at least one of a PSG film, a BPSG film, an SOG film, a SiN film, an SiO2 film, and an SiON film.

[0027] Although not shown in Figure 3, the entire interlayer insulating film 144 may be composed of a cured product 145. In other examples, the entire interlayer insulating film 144 may be composed of an inorganic insulating film. The substrate SB2 may further include via plugs 147 connected to the metal pattern 146. The via plugs 147 may be located in the interlayer insulating film 143, which is positioned between the interlayer insulating film 144 and the semiconductor substrate 130. The metal pattern 146 and the via plugs 147 may be formed separately, for example, by a single damascene method, or integrally, for example, by a dual damascene method. A barrier metal (not shown) may be placed between the groove TR2 and the metal pattern 146. The barrier metal may be formed of, for example, Ta, TaN, or TiN. The metal pattern 146 may be formed of, for example, copper, or an alloy mainly composed of copper.

[0028] When metal pattern 126 is placed on the outermost surface of substrate SB1 and metal pattern 146 is placed on the outermost surface of substrate SB2, metal pattern 126 and metal pattern 146 can be joined together. In this case, metal pattern 126 and metal pattern 146 may be joined directly without the use of other materials, or they may be joined via a conductive material.

[0029] The semiconductor substrates 110 and 130 may be, for example, silicon substrates, SiC substrates, or GaN substrates, but are not limited thereto.

[0030] Figure 4 shows a cross-sectional view of a portion of the semiconductor device 100 shown in Figure 3. The semiconductor device 100 may include a semiconductor substrate 110 and a wiring structure 120 disposed on the semiconductor substrate 110. The wiring structure 120 may include an interlayer insulating film 124 containing a cured product 125 of a curable composition disposed on the semiconductor substrate 110. The wiring structure 120 may also include an interlayer insulating film 123 disposed between the semiconductor substrate 110 and the interlayer insulating film 124. The wiring structure 120 may also include one or more interlayer insulating films disposed between the semiconductor substrate 110 and the interlayer insulating film 123.

[0031] The wiring structure 120 may comprise a groove TR provided in the cured material 125 and a metal pattern 126 filled in the groove TR. The cured material 125 may be formed using a planarizing apparatus 1 and an imprinting apparatus 2. Alternatively, the cured material 125 may be formed using the imprinting apparatus 2. The curable composition may be a photocurable composition. The interlayer insulating film 124 may further comprise an inorganic insulating film having a recess, and the cured material 125 may be placed in the recess. The semiconductor device 100 may further comprise via plugs 127 connected to the metal pattern 126. The via plugs 127 may be placed in the interlayer insulating film 123. The metal pattern 126 and the via plugs 127 may be formed separately, for example, by a single damascene method, or integrally, for example, by a dual damascene method. A barrier metal (not shown) may be placed between the groove TR and the metal pattern 126. The barrier metal may be formed of, for example, Ta, TaN, or TiN.

[0032] Hereinafter, with reference to Figures 5, 6, and 7, a first example of a method for manufacturing the semiconductor device 100 of the first embodiment described in Figures 3 and 4 will be explained illustratively. In this example, an example in which the dual damascene method is applied will be described. In step S1, via holes VH may be formed in the interlayer insulating film 123, which is composed of, for example, an inorganic insulating film, by a lithography process. The lithography process may include, for example, a photolithography process using a projection exposure apparatus, or an imprint process using an imprint apparatus. The same applies to the lithography process in the following description. Next, if necessary, a filler material may be filled into the via holes VH to form a dummy plug 151. Next, an interlayer insulating film 124 may be formed on the interlayer insulating film 123. At this stage, each of the interlayer insulating films 123 and 124 may include, for example, at least one of a PSG film, a BPSG film, an SOG film, a SiN film, an SiO2 film, or an SiON film. Next, a recess R may be formed in the interlayer insulating film 124 by a lithography process (recess formation step). In other words, step S1 may include a recess formation step in which a recess R is formed in the interlayer insulating film 124 placed on the semiconductor substrate 110. The interlayer insulating film 124 in which the recess R is formed will also be referred to as the interlayer insulating film 124'. In subsequent steps, the interlayer insulating film 124 becomes an interlayer insulating film that includes a cured product 125 in addition to the interlayer insulating film 124'.

[0033] Next, in step S2, a planarization step may be performed to form a planarization film PF1 consisting of a first cured product of the first curable composition CM1 on the interlayer insulating film 124 so as to fill the recesses R. The planarization step may be performed using a planarization apparatus 1. That is, in the planarization step, the first curable composition CM1 is placed on the interlayer insulating film 124, the super straight SS is brought into contact with the first curable composition CM1, and the planarization film PF1 is formed by curing the first curable composition CM1. Alternatively, instead of filling the via holes VH with filler material in step S1, the dummy plugs 151 may be formed as part of the planarization film PF1 by filling the via holes VH with the curable composition CM1 and curing it in the planarization step.

[0034] Next, in step S3, a pattern forming step may be performed to form a pattern PF2 on the planarization film PF1, which is made of a second cured product of the second curable composition CM2 and has openings OP on recesses R. The pattern forming step may be performed using an imprinting apparatus 2. In other words, in the pattern forming step, the second curable composition CM2 is placed on the planarization film PF1, a mold M is brought into contact with the second curable composition CM2, and the pattern PF2 is formed by curing the second curable composition CM2. The composition of the second curable composition CM2 may be the same as or different from the composition of the first curable composition CM1.

[0035] Next, in step S4, an etching step may be performed in which the planarization film PF1 is etched using pattern PF2 so that grooves TR are formed in the first cured material (part of the planarization film PF) within the recess R. In this etching step, the planarization film PF1 is etched according to the shape of pattern PF2 having openings OP, and the first cured material (part of the planarization film PF) may remain as cured material 125 having grooves TR. At this point, the interlayer insulating film 124 is composed of the interlayer insulating film 124' and the cured material 125. Furthermore, the dummy plug 151 may be removed by etching.

[0036] Next, in step S5, a metal film formation step may be performed to form a metal film MF on the interlayer insulating film 124 so that the via holes VH and grooves TR are filled with metal. Here, although not shown, a barrier metal may be formed before the metal film formation step to cover the bottom and sides of the via holes VH, the bottom and sides of the grooves TR, and the top surface of the interlayer insulating film 124. The barrier metal may be formed of, for example, Ta, TaN, or TiN. The barrier metal may be formed by, for example, sputtering or CVD. After the barrier metal is formed, the metal film MF may be formed by plating. The metal film MF may be formed of, for example, copper or an alloy mainly composed of copper.

[0037] Next, in step S6, a polishing step may be performed in which the metal film MF is polished by the CMP (Chemical Mechanical Polishing) method so that the metal pattern 126 remains in the via holes VH and grooves TR. In other words, in step S6, a polishing step may be performed in which the metal film MF is polished by the CMP method so that the metal pattern 126 arranged in the via holes VH and grooves TR is formed. The slurry may be prepared so that the polishing rate of the cured product 125 (first cured product) in the polishing step is smaller than the polishing rate of the interlayer insulating film 124' in the polishing step. A semiconductor substrate 130 or semiconductor device 100 is obtained after the polishing step.

[0038] In step S7, the second substrate SB2 may be bonded to the first substrate SB1. Subsequently, one or more other substrates may be bonded to substrate SB1 or substrate SB2.

[0039] In one respect, the method for manufacturing the semiconductor device 100 may include a first preparation step (S1 to S6) of preparing a substrate SB1 as a first substrate having a metal pattern 126 as a first metal pattern. The method for manufacturing the semiconductor device 100 may also include a second preparation step of preparing a substrate SB2 as a second substrate having a metal pattern 146 as a second metal pattern. The second preparation step may be the same as the first preparation step, but may also be a different step from the first preparation step. The method for manufacturing the semiconductor device 100 may also include a bonding step (S7) of bonding the metal pattern 126 and the metal pattern 146 to obtain the semiconductor device 100 including the substrates SB1 and SB2.

[0040] In other examples, the semiconductor device 100 may be completed without bonding substrate SB2 to substrate SB1.

[0041] The above is an example of applying the dual damascene method, but instead of forming the dummy plug 151, a conductive plug may be formed and used as a via plug without being removed in step S4. This method is called the single damascene method.

[0042] In the first example, the presence of a cured material 125 surrounding the metal pattern 126 in the interlayer insulating film 124 can reduce dishing in the CMP process compared to the case where the cured material 125 is not present. As a result, an interlayer insulating film 124 with a flat surface may remain after the CMP process. An interlayer insulating film 124 with a flat surface is advantageous for bonding the substrate SB2 to the interlayer insulating film 124.

[0043] Hereinafter, a second example of the manufacturing method for the semiconductor device 100 described in Figures 3 and 4 will be explained with reference to Figures 8, 9 and 10. In this example, the dual damascene method will be applied. In step S11, via holes VH may be formed in the interlayer insulating film 123, which is composed of, for example, an inorganic insulating film, by a lithography process. Then, if necessary, filler material may be filled into the via holes VH to form dummy plugs 151. Next, an interlayer insulating film 124 may be formed on the interlayer insulating film 123. At this stage, each of the interlayer insulating films 123 and 124 may include, for example, at least one of PSG film, BPSG film, SOG film, SiN film, SiO2 film, or SiON film. Next, a recess R may be formed in the interlayer insulating film 124 by a lithography process (recess formation step). That is, step S1 may include a recess formation step in which a recess R is formed in the interlayer insulating film 124 placed on the semiconductor substrate 110. The interlayer insulating film 124 on which the recess R is formed will also be referred to as the interlayer insulating film 124'. In subsequent processes, the interlayer insulating film 124 becomes an interlayer insulating film that includes a cured material 125 in addition to the interlayer insulating film 124'.

[0044] Next, in step S12, a planarization step may be performed to form a planarization film PF1 made of a first cured product of the first curable composition CM1 on the interlayer insulating film 124 so as to fill the recesses R. The planarization step may be performed using a planarization apparatus 1. That is, in the planarization step, the first curable composition CM1 is placed on the interlayer insulating film 124, the super straight SS is brought into contact with the first curable composition CM1, and the planarization film PF1 is formed by curing the first curable composition CM1. Alternatively, instead of filling the via holes VH with filler material in step S11, the dummy plug 151 may be formed as part of the planarization film PF1 by filling the via holes VH with the curable composition CM1 and curing it in the planarization step.

[0045] Next, in step S13, a pattern forming step may be performed to form a pattern PF2 on the planarization film PF1, which is made of a second cured product of the second curable composition CM2 and has an opening OP on a recess R. The pattern forming step may be performed using an imprinting apparatus 2. That is, in the pattern forming step, the second curable composition CM2 is placed on the planarization film PF1, the mold M is brought into contact with the second curable composition CM2, and the pattern PF2 is formed by curing the second curable composition CM2. The composition of the second curable composition CM2 may be the same as or different from the composition of the first curable composition CM1. In the second example, in the pattern forming step, the pattern PF2 may be formed having a first region RA having a first height and a second region RB having a second height higher than the first height and positioned between the first region RA and the opening OP.

[0046] Next, in step S14, an etching step may be performed in which the planarization film PF1 is etched using pattern PF2 so that grooves TR are formed in the first cured material (part of the planarization film PF) within the recesses R. In this etching step, the planarization film PF1 is etched according to the shape of pattern PF2 having openings OP, and the first cured material (part of the planarization film PF) may remain as cured material 125 having grooves TR. At this point, the interlayer insulating film 124 is composed of the interlayer insulating film 124' and the cured material 125. Furthermore, the dummy plug 151 may be removed by etching. In the second example, the upper surface of the cured material 125 is higher than the upper surface of the interlayer insulating film 124'. This is a result of the reflection of a first region RA having a first height and a second region RB having a second height that is higher than the first height.

[0047] Next, in step S15, a metal film formation step may be performed to form a metal film MF on the interlayer insulating film 124 so that the via holes VH and grooves TR are filled with metal. Here, although not shown, a barrier metal may be formed before the metal film formation step to cover the bottom and sides of the via holes VH, the bottom and sides of the grooves TR, and the top surface of the interlayer insulating film 124. The barrier metal may be formed of, for example, Ta, TaN, or TiN. The barrier metal may be formed by, for example, sputtering or CVD. After the barrier metal is formed, the metal film MF may be formed by plating. The metal film MF may be formed of, for example, copper or an alloy mainly composed of copper.

[0048] Next, in step S16, a polishing step may be performed in which the metal film MF is polished by the CMP method so that the metal pattern 126 remains in the via holes VH and grooves TR. In other words, in step S16, a polishing step may be performed in which the metal film MF is polished by the CMP method so that the metal pattern 126 placed in the via holes VH and grooves TR is formed. The slurry may be prepared so that the polishing rate of the cured product 125 (first cured product) in the polishing step is smaller than the polishing rate of the interlayer insulating film 124' in the polishing step. A semiconductor substrate 130 or semiconductor device 100 is obtained after the polishing step.

[0049] In step S17, a second substrate, substrate SB2, may be bonded to a first substrate, substrate SB1. Subsequently, one or more other substrates may be bonded to substrate SB1 or substrate SB2.

[0050] In one respect, the method for manufacturing the semiconductor device 100 may include a first preparation step (S11-S16) for preparing a substrate SB1 as a first substrate having a metal pattern 126 as a first metal pattern. The method for manufacturing the semiconductor device 100 may also include a second preparation step for preparing a substrate SB2 as a second substrate having a metal pattern 146 as a second metal pattern. The second preparation step may be the same as the first preparation step, but may also be different from the first preparation step. The method for manufacturing the semiconductor device 100 may also include a bonding step (S17) for obtaining the semiconductor device 100 including substrates SB1 and SB2 by bonding the metal pattern 126 and the metal pattern 146.

[0051] In other examples, the semiconductor device 100 may be completed without bonding substrate SB2 to substrate SB1.

[0052] The above is an example of applying the dual damascene method, but instead of forming the dummy plug 151, a conductive plug may be formed and used as a via plug without being removed in step S14. This method is called the single damascene method.

[0053] In the second example, since the upper surface of the cured product 125 is higher than the upper surface of the interlayer insulating film 124' before the CMP process, dishing in the CMP process can be reduced compared to the first example. As a result, an interlayer insulating film 124 with a flatter surface may remain after the CMP process. An interlayer insulating film 124 with a flatter surface is advantageous for bonding the substrate SB2 to the interlayer insulating film 124.

[0054] Hereinafter, a third example of the manufacturing method of the semiconductor device 100 described in Figures 3 and 4 will be explained illustratively with reference to Figures 11 and 12. In this example, the dual damascene method will be applied. In step S21, via holes VH may be formed in the interlayer insulating film 123, which is composed of, for example, an inorganic insulating film, by a lithography process. Then, if necessary, filler material may be filled into the via holes VH to form dummy plugs 151. Next, an interlayer insulating film 124 may be formed on the interlayer insulating film 123. At this stage, each of the interlayer insulating films 123 and 124 may include, for example, at least one of PSG film, BPSG film, SOG film, SiN film, SiO2 film, or SiON film. Next, a recess R may be formed in the interlayer insulating film 124 by a lithography process (recess formation step). That is, step S21 may include a recess formation step in which a recess R is formed in the interlayer insulating film 124 placed on the semiconductor substrate 110. The interlayer insulating film 124 on which the recess R is formed will also be referred to as the interlayer insulating film 124'. In subsequent processes, the interlayer insulating film 124 becomes an interlayer insulating film that includes a cured material 125 in addition to the interlayer insulating film 124'.

[0055] Next, in step S22, a pattern forming step may be performed in which a pattern PF having an opening OP is formed on the interlayer insulating film 124, consisting of a cured product of the curable composition CM so as to fill the recess R. The pattern forming step may be performed using an imprint apparatus 2. In other words, in the pattern forming step, the pattern PF can be formed by placing the curable composition CM on the interlayer insulating film 124, bringing the mold M into contact with the curable composition CM, and curing the curable composition CM. Alternatively, instead of filling the via holes VH with filler material in step S21, the dummy plugs 151 may be formed as part of the pattern PF by filling the via holes VH with the curable composition CM and curing it in the pattern forming step.

[0056] Next, in step S23, an etching step may be performed to etch the entire pattern PF so that grooves TR are formed in the cured material (part of the pattern PF) within the recesses R. In this etching step, the thickness of the pattern PF is reduced, and the cured material (part of the planarized film PF) within the recesses R may remain as cured material 125 having grooves TR. At this point, the interlayer insulating film 124 is composed of the interlayer insulating film 124' and the cured material 125. Furthermore, the dummy plug 151 may be removed by etching.

[0057] Next, in step S24, a metal film formation step may be performed to form a metal film MF on the interlayer insulating film 124 so that the via holes VH and grooves TR are filled with metal. Here, although not shown, a barrier metal may be formed before the metal film formation step to cover the bottom and sides of the via holes VH, the bottom and sides of the grooves TR, and the top surface of the interlayer insulating film 124. The barrier metal may be formed of, for example, Ta, TaN, or TiN. The barrier metal may be formed by, for example, sputtering or CVD. After the barrier metal is formed, the metal film MF may be formed by plating. The metal film MF may be formed of, for example, copper or an alloy mainly composed of copper.

[0058] Next, in step S25, a polishing step may be performed in which the metal film MF is polished by the CMP method so that the metal pattern 126 remains in the via holes VH and grooves TR. In other words, in step S25, a polishing step may be performed in which the metal film MF is polished by the CMP method so that the metal pattern 126 arranged in the via holes VH and grooves TR is formed. The slurry may be prepared so that the polishing rate of the hardened product 125 in the polishing step is smaller than the polishing rate of the interlayer insulating film 124' in the polishing step. A semiconductor substrate 130 or semiconductor device 100 is obtained after the polishing step.

[0059] In step S26, a second substrate, SB2, may be bonded to a first substrate, SB1. Subsequently, one or more other substrates may be bonded to substrate SB1 or substrate SB2.

[0060] In one respect, the method for manufacturing the semiconductor device 100 may include a first preparation step (S21-S25) of preparing a substrate SB1 as a first substrate having a metal pattern 126 as a first metal pattern. The method for manufacturing the semiconductor device 100 may also include a second preparation step of preparing a substrate SB2 as a second substrate having a metal pattern 146 as a second metal pattern. The second preparation step may be the same as the first preparation step, but may also be a different step from the first preparation step. The method for manufacturing the semiconductor device 100 may also include a bonding step (S26) of bonding the metal pattern 126 and the metal pattern 146 to obtain the semiconductor device 100 including the substrates SB1 and SB2.

[0061] In other examples, the semiconductor device 100 may be completed without bonding substrate SB2 to substrate SB1.

[0062] The above is an example of applying the dual damascene method, but instead of forming the dummy plug 151, a conductive plug may be formed and used as a via plug without being removed in step S4. This method is called the single damascene method.

[0063] In the third example, the presence of a cured material 125 surrounding the metal pattern 126 in the interlayer insulating film 124 can reduce dishing in the CMP process compared to the case where the cured material 125 is not present. As a result, an interlayer insulating film 124 with a flat surface may remain after the CMP process. An interlayer insulating film 124 with a flat surface is advantageous for bonding the substrate SB2 to the interlayer insulating film 124. Furthermore, in the third example, the process of forming the cured material 125 in the recess R is simplified compared to the first example.

[0064] Hereinafter, a fourth example of the manufacturing method of the semiconductor device 100 described in Figures 3 and 4 will be explained illustratively with reference to Figures 13 and 14. In this example, the dual damascene method will be applied. In step S31, via holes VH may be formed in the interlayer insulating film 123, which is composed of, for example, an inorganic insulating film, by a lithography process. Then, if necessary, filler material may be filled into the via holes VH to form a dummy plug 151. Next, an interlayer insulating film 124 may be formed on the interlayer insulating film 123. At this stage, each of the interlayer insulating films 123 and 124 may include, for example, at least one of PSG film, BPSG film, SOG film, SiN film, SiO2 film, or SiON film. Next, a recess R may be formed in the interlayer insulating film 124 by a lithography process (recess formation step). That is, step S31 may include a recess formation step in which a recess R is formed in the interlayer insulating film 124 placed on the semiconductor substrate 110. The interlayer insulating film 124 on which the recess R is formed will also be referred to as the interlayer insulating film 124'. In subsequent processes, the interlayer insulating film 124 becomes an interlayer insulating film that includes a cured material 125 in addition to the interlayer insulating film 124'.

[0065] Next, in step S32, a pattern forming step may be performed in which a pattern PF having an opening OP and consisting of a cured product of a curable composition CM so as to fill a recess R is formed on the interlayer insulating film 124. The pattern forming step may be performed using an imprint apparatus 2. In other words, in the pattern forming step, the pattern PF can be formed by placing the curable composition CM on the interlayer insulating film 124, bringing the mold M into contact with the curable composition CM, and curing the curable composition CM. Alternatively, instead of filling the via holes VH with filler material in step S31, a dummy plug 151 may be formed as part of the pattern PF by filling the via holes VH with the curable composition CM and curing it in the pattern forming step. In the fourth example, in the pattern forming step, the pattern PF can be formed having a first region RA having a first height and a second region RB having a second height higher than the first height and positioned between the first region RA and the opening OP.

[0066] Next, in step S33, an etching step may be performed to etch the entire pattern PF so that grooves TR are formed in the cured material (part of the pattern PF) within the recesses R. In this etching step, the thickness of the pattern PF is reduced, and the cured material (part of the planarized film PF) within the recesses R may remain as cured material 125 having grooves TR. At this point, the interlayer insulating film 124 is composed of the interlayer insulating film 124' and the cured material 125. Furthermore, the dummy plug 151 may be removed by etching.

[0067] Next, in step S34, a metal film formation step may be performed to form a metal film MF on the interlayer insulating film 124 so that the via holes VH and grooves TR are filled with metal. Here, although not shown, a barrier metal may be formed before the metal film formation step to cover the bottom and sides of the via holes VH, the bottom and sides of the grooves TR, and the top surface of the interlayer insulating film 124. The barrier metal may be formed of, for example, Ta, TaN, or TiN. The barrier metal may be formed by, for example, sputtering or CVD. After the barrier metal is formed, the metal film MF may be formed by plating. The metal film MF may be formed of, for example, copper or an alloy mainly composed of copper.

[0068] Next, in step S35, a polishing step may be performed in which the metal film MF is polished by the CMP method so that the metal pattern 126 remains in the via holes VH and grooves TR. In other words, in step S35, a polishing step may be performed in which the metal film MF is polished by the CMP method so that the metal pattern 126 arranged in the via holes VH and grooves TR is formed. The slurry may be prepared so that the polishing rate of the hardened product 125 in the polishing step is smaller than the polishing rate of the interlayer insulating film 124' in the polishing step. A semiconductor substrate 130 or semiconductor device 100 is obtained after the polishing step.

[0069] In step S36, a second substrate, SB2, may be bonded to a first substrate, SB1. Subsequently, one or more other substrates may be bonded to substrate SB1 or substrate SB2.

[0070] In one respect, the method for manufacturing the semiconductor device 100 may include a first preparation step (S31-S35) of preparing a substrate SB1 as a first substrate having a metal pattern 126 as a first metal pattern. The method for manufacturing the semiconductor device 100 may also include a second preparation step of preparing a substrate SB2 as a second substrate having a metal pattern 146 as a second metal pattern. The second preparation step may be the same as the first preparation step, but may also be a different step from the first preparation step. The method for manufacturing the semiconductor device 100 may also include a bonding step (S36) of bonding the metal pattern 126 and the metal pattern 146 to obtain the semiconductor device 100 including the substrates SB1 and SB2.

[0071] In other examples, the semiconductor device 100 may be completed without bonding substrate SB2 to substrate SB1.

[0072] The above is an example of applying the dual damascene method, but instead of forming the dummy plug 151, a conductive plug may be formed and used as a via plug without being removed in step S4. This method is called the single damascene method.

[0073] In the fourth example, since the upper surface of the cured product 125 is higher than the upper surface of the interlayer insulating film 124' before the CMP process, dishing in the CMP process can be reduced compared to the first example. As a result, an interlayer insulating film 124 with a flatter surface may remain after the CMP process. An interlayer insulating film 124 with a flatter surface is advantageous for bonding the substrate SB2 to the interlayer insulating film 124. Furthermore, in the fourth example, the process of forming the cured product 125 in the recess R is simplified compared to the second example.

[0074] The semiconductor device 100 of the second embodiment will now be described. Matters not mentioned in the description of the second embodiment may follow the description of the first embodiment, but the second embodiment may be implemented independently of the first embodiment. Figure 15 schematically shows the cross-sectional configuration of the semiconductor device 100 of the second embodiment.

[0075] The semiconductor device 100 of the second embodiment may include an interlayer insulating film 122b containing a cured product of a curable composition disposed on a semiconductor substrate 110, a groove TR3 provided in the interlayer insulating film 122b, and a metal pattern 128 filled in the groove TR3. The cured product constituting the interlayer insulating film 122b may be formed using a planarizing apparatus 1 and an imprinting apparatus 2. Alternatively, the cured product 125 may be formed using the imprinting apparatus 2. The curable composition may be a photocurable composition. The interlayer insulating film 124 may further include an inorganic insulating film having a recess, and the cured product 125 may be disposed in the recess. The inorganic insulating film may include, for example, at least one of a PSG film, a BPSG film, an SOG film, a SiN film, an SiO2 film, and an SiON film.

[0076] The interlayer insulating film 122b may be composed entirely of a cured product of a curable composition. The semiconductor device 100 may further include via plugs 129 connected to a metal pattern 128. The via plugs 129 may be located in the interlayer insulating film 122a, which is positioned between the interlayer insulating film 122b and the semiconductor substrate 110. The metal pattern 128 and the via plugs 129 may be formed separately, for example, by a single damascene method, or integrally, for example, by a dual damascene method. A barrier metal (not shown) may be placed between the groove TR3 and the metal pattern 128. The barrier metal may be formed of, for example, Ta, TaN, or TiN. The metal pattern 126 may be formed of, for example, copper, or an alloy mainly composed of copper.

[0077] In one aspect, the semiconductor device 100 may include a substrate SB1 comprising a semiconductor substrate 110 and a wiring structure 120. The wiring structure 120 may include an interlayer insulating film 122b. Alternatively, the wiring structure 120 may include interlayer insulating films 122b and 122a. Alternatively, the wiring structure 120 may include at least one interlayer insulating film in addition to the interlayer insulating films 122b and 122a, for example, interlayer insulating layers 122, 123, and 124. The interlayer insulating film 122 may be placed between the interlayer insulating film 122a and the semiconductor substrate 110. The interlayer insulating layers 123 and 124 may be placed on the interlayer insulating film 122b. Multiple transistors tr may be placed on the semiconductor substrate 110.

[0078] In other aspects, the semiconductor device 100 may include a laminated structure including a substrate SB1 as a first substrate including a semiconductor substrate 110 and a wiring structure 120, and a substrate SB2 as a second substrate including a semiconductor substrate 130 and a wiring structure 140. In yet other aspects, the semiconductor device 100 is a semiconductor device having substrate SB1 as a first substrate and substrate SB2 as a second substrate. The semiconductor device 100 may further include one or more other substrates. Substrate SB1 has a metal pattern 126 as a first metal pattern, and substrate SB2 has a metal pattern 146 as a second metal pattern, and the semiconductor device 100 may have a structure in which the metal patterns 126 and 146 are joined. At least one of the interlayer insulating films 122, 123, 124 may be composed of, for example, an inorganic material film. The inorganic material film may include, for example, at least one of a PSG film, a BPSG film, an SOG film, a SiN film, an SiO2 film, and an SiON film. Alternatively, the interlayer insulating films 122 and 123 may be composed of organic material films.

[0079] Hereinafter, with reference to Figures 16 and 17, a first example of a method for manufacturing the semiconductor device 100 of the second embodiment shown in Figure 15 will be described illustratively. In this example, an example in which the dual damascene method is applied will be described. In step S41, a first insulating layer formation step may be performed in which a first interlayer insulating film 122a, which is a first insulating film made of a first cured product of the first curable composition CM1, is formed on the semiconductor substrate 110. The first insulating layer formation step may be performed using a planarization apparatus 1. That is, in the first insulating layer formation step, the first curable composition CM1 is placed on the semiconductor substrate 110, the first curable composition CM1 is brought into contact with the first curable composition CM1, and the first insulating layer can be formed by curing the first curable composition CM1.

[0080] Furthermore, in step S41, via holes VH3 may be formed in the first interlayer insulating film 122a by a lithography process. Subsequently, if necessary, filler material may be filled into the via holes VH3 to form dummy plugs 153.

[0081] Next, in step S42, a second insulating film formation step may be performed to form a second insulating film 122b, which is made of a second cured product of the second curable composition CM2 and has grooves TR3, on top of the first insulating film 122a. The second insulating film formation step may be performed using the imprint apparatus 2. That is, in the second insulating film formation step, the second curable composition CM2 is placed on top of the first insulating film 122a, the mold M is brought into contact with the second curable composition CM2, and the second insulating film 122b is formed by curing the second curable composition CM2. The composition of the second curable composition CM2 may be the same as or different from the composition of the first curable composition CM1. The first curable composition CM1 and the second curable composition CM2 may be photocurable compositions. Next, the dummy plug 151 may be removed by etching.

[0082] Next, in step S43, a metal film formation step may be performed to form a metal film MF2 on the second interlayer insulating film 122b so that the via holes VH3 and grooves TR3 are filled with metal. Here, although not shown, a barrier metal may be formed before the metal film formation step to cover the bottom and sides of the via holes VH3, the bottom and sides of the grooves TR3, and the top surface of the second interlayer insulating film 122b. The barrier metal may be formed of, for example, Ta, TaN, or TiN. The barrier metal may be formed by, for example, sputtering or CVD. After the barrier metal is formed, the metal film MF may be formed by plating. The metal film MF2 may be formed of, for example, copper or an alloy mainly composed of copper.

[0083] Next, in step S44, a polishing step may be performed in which the metal film MF is polished by the CMP method so that the metal pattern 126 remains in the via hole VH and groove TR. In other words, in step S44, a polishing step may be performed in which the metal film MF2 is polished by the CMP method so that the metal pattern 128 is formed in the via hole VH3 and groove TR3.

[0084] Furthermore, the substrate SB1 and substrate SB2 having the metal pattern 126 formed as described above may be joined together, in which case the metal pattern 126 of substrate SB1 and the metal pattern exposed on the surface of substrate SB2 may be joined together.

[0085] The above is an example of applying the dual damascene method, but instead of forming the dummy plug 153, a conductive plug may be formed and used as a via plug without being removed in step S42. This method is called the single damascene method.

[0086] According to the above method, the formation and processing of interlayer insulating films 122a and 122b to which the damascene method is applied can be carried out without using a vacuum process. Furthermore, forming 122a and 122b with a curable composition can contribute to expanding the range of material options.

[0087] Hereinafter, a second example of the manufacturing method for the semiconductor device 100 of the second embodiment described in Figure 15 will be explained illustratively with reference to Figure 18. In this example, an example in which the dual damascene method is applied will be described. In step S51, an insulating film formation step may be performed in which an insulating film or interlayer insulating film 122c having via holes VR4 and grooves TR4, consisting of a cured product of a curable composition CM, is formed on the semiconductor substrate 110. The interlayer insulating film 122c corresponds to the laminated film of the aforementioned interlayer insulating films 122a and 122b. The insulating film formation step may be performed using an imprint apparatus 2. That is, in the insulating film formation step, the curable composition CM is placed on the semiconductor substrate 110, a mold M is brought into contact with the curable composition CM, and the interlayer insulating film 122c can be formed by curing the curable composition CM.

[0088] Next, in step S52, a metal film formation step may be performed to form a metal film MF2 on the interlayer insulating film 122c so that the via holes VH4 and grooves TR4 are filled with metal. Here, although not shown, a barrier metal may be formed before the metal film formation step to cover the bottom and sides of the via holes VH4, the bottom and sides of the grooves TR4, and the top surface of the interlayer insulating film 122c. The barrier metal may be formed of, for example, Ta, TaN, or TiN. The barrier metal may be formed by, for example, sputtering or CVD. After the barrier metal is formed, the metal film MF may be formed by plating. The metal film MF2 may be formed of, for example, copper or an alloy mainly composed of copper.

[0089] Next, in step S53, a polishing step may be performed in which the metal film MF is polished by the CMP method so that the metal pattern 128 remains in the via hole VH4 and groove TR4. In other words, in step S53, a polishing step may be performed in which the metal film MF2 is polished by the CMP method so that the metal pattern 128 is formed in the via hole VH4 and groove TR4.

[0090] Furthermore, the substrate SB1 and substrate SB2 having the metal pattern 126 formed as described above may be joined together, in which case the metal pattern 126 of substrate SB1 and the metal pattern exposed on the surface of substrate SB2 may be joined together.

[0091] According to the above method, the formation and processing of the interlayer insulating film 122c to which the damascene method is applied can be carried out without using a vacuum process. Furthermore, forming 122c with a curable composition can contribute to expanding the range of material options.

[0092] This specification and accompanying drawings include the following disclosures: (Item 1) An interlayer insulating film containing a cured product of a curable composition disposed on a semiconductor substrate, Grooves provided in the hardened material, The metal pattern filled in the groove, A semiconductor device characterized by comprising the following features. (Item 2) The interlayer insulating film further comprises an inorganic insulating film having a recess, and the cured product is disposed in the recess. A semiconductor device as described in item 1, characterized by the features described herein. (Item 3) The metal pattern is further comprising a via plug connected to the aforementioned metal pattern. A semiconductor device as described in item 2, characterized by the features described herein. (Item 4) The entire interlayer insulating film is composed of the cured product. A semiconductor device as described in item 1, characterized by the features described herein. (Item 5) The metal pattern is further comprising a via plug connected to the aforementioned metal pattern. A semiconductor device as described in item 4, characterized by the features described herein. (Item 6) The curable composition is a photocurable composition. A semiconductor device according to any one of items 1 to 5, characterized by the features described herein. (Item 7) A recess formation step in which recesses are formed in the interlayer insulating film placed on a semiconductor substrate, A planarization step of forming a planar film made of a first cured product of the first curable composition on the interlayer insulating film so as to fill the recesses, A pattern forming step is to form a pattern on the planarized film, which consists of a second cured product of the second curable composition and has openings on the recesses, An etching step of etching the planarized film using the pattern such that grooves are formed in the first cured product within the recess, A metal film forming step of forming a metal film on the interlayer insulating film such that metal fills the grooves, A polishing step in which the metal film is polished by the CMP method so that a metal pattern remains in the groove, A method for manufacturing a semiconductor device, characterized by including [the necessary components]. (Item 8) In the pattern forming step, the pattern is formed such that it has a first region having a first height and a second region having a second height that is higher than the first height and is located between the first region and the opening. A method for manufacturing a semiconductor device as described in item 7, characterized by the features described therein. (Item 9) The polishing rate of the first cured product in the polishing step is smaller than the polishing rate of the interlayer insulating film in the polishing step. A method for manufacturing a semiconductor device as described in item 7 or 8, characterized by the features described therein. (Item 10) In the planarization step, the first curable composition is placed on the interlayer insulating film, SuperStraight is brought into contact with the first curable composition, and the first curable composition is cured to form the planarized film. In the pattern forming step, the pattern is formed by placing the second curable composition on the planarized film, bringing a mold into contact with the second curable composition, and curing the second curable composition. A method for manufacturing a semiconductor device as described in any one of items 7 to 9, characterized by the features described herein. (Item 11) The interlayer insulating film includes an inorganic insulating film. A method for manufacturing a semiconductor device according to any one of items 7 to 10, characterized by the features described herein. (Item 12) The first curable composition and the second curable composition are photocurable compositions. A method for manufacturing a semiconductor device according to any one of items 7 to 11, characterized by the features described herein. (Item 13) A recess formation step in which recesses are formed in the interlayer insulating film placed on a semiconductor substrate, A pattern forming step is to form a pattern on the interlayer insulating film, which is made of a cured product of a curable composition and has openings on the recesses, so as to fill the recesses. An etching step of etching the entire pattern so that grooves are formed in the hardened material within the recesses, A metal film forming step of forming a metal film on the pattern such that metal fills the grooves, A polishing step in which the metal film is polished by the CMP method so that a metal pattern remains in the groove, A method for manufacturing a semiconductor device, characterized by including [the necessary components]. (Item 14) In the pattern forming step, the pattern is formed such that it has a first region having a first height and a second region positioned between the first region and the recess and having a height higher than the first height. A method for manufacturing a semiconductor device as described in item 13, characterized by the features described therein. (Item 15) The polishing rate of the cured product in the polishing step is smaller than the polishing rate of the interlayer insulating film in the polishing step. A method for manufacturing a semiconductor device as described in item 13 or 14, characterized by the above. (Item 16) In the pattern forming step, the curable composition is placed on the interlayer insulating film, a mold is brought into contact with the curable composition, and the pattern is formed by curing the curable composition. A method for manufacturing a semiconductor device according to any one of items 13 to 15, characterized by the features described herein. (Item 17) The interlayer insulating film includes an inorganic insulating film. A method for manufacturing a semiconductor device according to any one of items 13 to 16, characterized by the features described above. (Item 18) The curable composition is a photocurable composition. A method for manufacturing a semiconductor device as described in any one of items 13 to 17, characterized by the features described herein. (Item 19) A first insulating film formation step in which a first insulating film consisting of a first cured product of a first curable composition is formed on a semiconductor substrate, A second insulating film forming step, in which a second insulating film having grooves and consisting of a second cured product of a second curable composition is formed on the first insulating film, A metal film forming step of forming a metal film on the second insulating film such that metal fills the grooves, A polishing step in which the metal film is polished by the CMP method so that a metal pattern remains in the groove, A method for manufacturing a semiconductor device, characterized by including [the necessary components]. (Item 20) In the first insulating film formation step, the first curable composition is placed on the semiconductor substrate, Superstraight is brought into contact with the first curable composition, and the first insulating film is formed by curing the first curable composition. In the second insulating film formation step, the second curable composition is placed on the first insulating film, a mold is brought into contact with the second curable composition, and the second insulating film is formed by curing the second curable composition. A method for manufacturing a semiconductor device as described in item 19, characterized by the present invention. (Item 21) The first curable composition and the second curable composition are photocurable compositions. A method for manufacturing a semiconductor device as described in item 19 or 20, characterized by the above. (Item 22) An insulating film formation step in which an insulating film having grooves is formed on a semiconductor substrate, which consists of a cured product of a curable composition, A metal film forming step of forming a metal film on the insulating film such that metal fills the grooves, A polishing step in which the metal film is polished by the CMP method so that a metal pattern remains in the groove, A method for manufacturing a semiconductor device, characterized by including [the necessary components]. (Item 23) In the insulating film formation step, the curable composition is placed on the semiconductor substrate, a mold is brought into contact with the curable composition, and the insulating film is formed by curing the curable composition. A method for manufacturing a semiconductor device as described in item 22, characterized by the following: (Item 24) The curable composition is a photocurable composition. A method for manufacturing a semiconductor device according to item 22 or 23, characterized by the features described above. (others) The invention is not limited to the embodiments described above, and various modifications and variations are possible without departing from the spirit and scope of the invention. Accordingly, claims are attached to disclose the scope of the invention. [Explanation of Symbols]

[0093] 100: Semiconductor device, 110: Semiconductor substrate, CM, CM1, CM2: Curable composition, 122, 123, 124: Interlayer insulating film, 125: Cured product, 126: Metal pattern, 127: Via plug, TR: Groove, R: Recess, OP: Opening

Claims

1. An interlayer insulating film containing a cured product of a curable composition disposed on a semiconductor substrate, Grooves provided in the hardened material, The metal pattern filled in the groove, A semiconductor device characterized by comprising the following features.

2. The interlayer insulating film further comprises an inorganic insulating film having a recess, and the cured product is disposed in the recess. The semiconductor device according to feature 1.

3. The metal pattern is further comprising a via plug connected to the aforementioned metal pattern. The semiconductor device according to claim 2.

4. The entire interlayer insulating film is composed of the cured product. The semiconductor device according to feature 1.

5. The metal pattern is further comprising a via plug connected to the aforementioned metal pattern. The semiconductor device according to feature 4.

6. The curable composition is a photocurable composition. The semiconductor device according to any one of claims 1 to 5.

7. A recess formation step in which recesses are formed in the interlayer insulating film placed on a semiconductor substrate, A planarization step of forming a planar film made of a first cured product of the first curable composition on the interlayer insulating film so as to fill the recesses, A pattern forming step is to form a pattern on the planarized film, which consists of a second cured product of the second curable composition and has openings on the recesses. An etching step of etching the planarized film using the pattern such that grooves are formed in the first cured product within the recess, A metal film forming step of forming a metal film on the interlayer insulating film such that metal fills the grooves, A polishing step in which the metal film is polished by the CMP method so that a metal pattern remains in the groove, A method for manufacturing a semiconductor device, characterized by including [the necessary components].

8. In the pattern forming step, the pattern is formed such that it has a first region having a first height and a second region having a second height that is higher than the first height and is located between the first region and the opening. The method for manufacturing a semiconductor device according to claim 7.

9. The polishing rate of the first cured product in the polishing step is smaller than the polishing rate of the interlayer insulating film in the polishing step. The method for manufacturing a semiconductor device according to claim 7.

10. In the planarization step, the first curable composition is placed on the interlayer insulating film, SuperStraight is brought into contact with the first curable composition, and the first curable composition is cured to form the planarized film. In the pattern forming step, the second curable composition is placed on the planarized film, a mold is brought into contact with the second curable composition, and the pattern is formed by curing the second curable composition. The method for manufacturing a semiconductor device according to claim 7.

11. The interlayer insulating film includes an inorganic insulating film. The method for manufacturing a semiconductor device according to claim 7.

12. The first curable composition and the second curable composition are photocurable compositions. A method for manufacturing a semiconductor device according to any one of claims 7 to 11.

13. A recess formation step in which recesses are formed in the interlayer insulating film placed on a semiconductor substrate, A pattern forming step is to form a pattern on the interlayer insulating film, which is made of a cured product of a curable composition and has openings on the recesses, so as to fill the recesses. An etching step of etching the entire pattern so that grooves are formed in the hardened material within the recesses, A metal film forming step of forming a metal film on the pattern such that metal fills the grooves, A polishing step in which the metal film is polished by the CMP method so that a metal pattern remains in the groove, A method for manufacturing a semiconductor device, characterized by including [the necessary components].

14. In the pattern forming step, the pattern is formed such that it has a first region having a first height and a second region positioned between the first region and the recess and having a height higher than the first height. A method for manufacturing a semiconductor device according to claim 13, characterized in that it is a semiconductor device.

15. The polishing rate of the cured product in the polishing step is smaller than the polishing rate of the interlayer insulating film in the polishing step. A method for manufacturing a semiconductor device according to claim 13, characterized in that it is a semiconductor device.

16. In the pattern forming step, the curable composition is placed on the interlayer insulating film, a mold is brought into contact with the curable composition, and the pattern is formed by curing the curable composition. A method for manufacturing a semiconductor device according to claim 13, characterized in that it is a semiconductor device.

17. The interlayer insulating film includes an inorganic insulating film. A method for manufacturing a semiconductor device according to claim 13, characterized in that it is a semiconductor device.

18. The curable composition is a photocurable composition. A method for manufacturing a semiconductor device according to any one of claims 13 to 17.

19. A first insulating film formation step in which a first insulating film made of a first cured product of a first curable composition is formed on a semiconductor substrate, A second insulating film forming step, in which a second insulating film having grooves and consisting of a second cured product of a second curable composition is formed on the first insulating film, A metal film forming step of forming a metal film on the second insulating film such that metal fills the grooves, A polishing step in which the metal film is polished by the CMP method so that a metal pattern remains in the groove, A method for manufacturing a semiconductor device, characterized by including [the necessary components].

20. In the first insulating film formation step, the first curable composition is placed on the semiconductor substrate, Superstraight is brought into contact with the first curable composition, and the first insulating film is formed by curing the first curable composition. In the second insulating film formation step, the second curable composition is placed on the first insulating film, a mold is brought into contact with the second curable composition, and the second insulating film is formed by curing the second curable composition. The method for manufacturing a semiconductor device according to claim 19.

21. The first curable composition and the second curable composition are photocurable compositions. A method for manufacturing a semiconductor device according to claim 19 or 20, characterized in that it is a semiconductor device manufacturing method.

22. An insulating film formation step in which an insulating film having grooves is formed on a semiconductor substrate, which consists of a cured product of a curable composition, A metal film forming step of forming a metal film on the insulating film such that metal fills the grooves, A polishing step in which the metal film is polished by the CMP method so that a metal pattern remains in the groove, A method for manufacturing a semiconductor device, characterized by including [the necessary components].

23. In the insulating film formation step, the curable composition is placed on the semiconductor substrate, a mold is brought into contact with the curable composition, and the insulating film is formed by curing the curable composition. A method for manufacturing a semiconductor device according to claim 22, characterized in that it is a semiconductor device.

24. The curable composition is a photocurable composition. A method for manufacturing a semiconductor device according to claim 22 or 23, characterized by the above.

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