Multistep quantum ground state shift using a fixed number of ancilla qubits

Abstract

This invention provides a method and quantum circuit used to perform multi-step quantum ground state shifts. [Solution] In a quantum circuit, 2 N + 1 For a state vector space of size q, the shift register has a total of N+1 qubits, with the final qubit q N + 1 is a superposition qubit, which defines a superposition of substates. A superposition qubit is used to determine whether to increment or decrement a substate, and the even substate to increment is the i+1th qubit q. i + The step qubit, which is 1, can be incremented by simply inverting it, and similarly, the odd substates to be decremented can be decremented by applying the same inversion step. The remaining steps of the quantum circuit are used to rearrange the even substates to be incremented, the even substates to be decremented, the odd substates to be incremented, and the odd substates to be decremented.

Description

[Technical Field]

[0001] The present disclosure (hereinafter referred to as "the Disclosure") relates to a method for performing a multistep quantum ground state shift using a fixed number of ancilla qubits. The Disclosure also relates to a quantum computer or quantum simulator configured to perform the aforementioned method. The Disclosure further relates to a quantum circuit for performing a multistep quantum ground state shift using a fixed number of ancilla qubits. Background

[0002] For quantum algorithms to outperform classical computations, the scale of computational operations relative to the size of the problem must be smaller compared to classical algorithms solving the same problem. A desirable property for state-shifting algorithms is that quantum operations (i.e., gates) exhibit logarithmic scaling with respect to the number of internal qubit states. However, the computational complexity of a quantum algorithm varies greatly depending on the problem being solved and the computational approach used. Generally, computational complexity is not necessarily related to the number of tensor product states, and speedups can arise from diverse algorithmic mechanisms spanning multiple different complexity classes.

[0003] Of note is the fact that the state-shifting process is used as a subroutine in multiple quantum algorithms. Currently known quantum shift procedures can be implemented in two configurations: (i) a first configuration using an additional (variable) ancilla register, and (ii) a second configuration that does not use any additional (variable) ancilla registers. In the first configuration, the introduction of a variable ancilla register provides logarithmic dependence. The first configuration is disclosed in U.S. Patent No. 11,694,107. On the other hand, in the second configuration, an ancilla-less approach (e.g., a shift based on the quantum Fourier transform (QFT)) results in an algorithm that scales quadratically with respect to the number of qubits. This makes the complexity poly-logarithmic with respect to the number of states. Shakeel has proposed a QFT-based shift ("Efficient and scalable quantum walk algorithms via the quantum Fourier transform", published in Quantum Information Processing 19 (2020)).

[0004] These two configurations have complementary advantages and disadvantages. When implementing state shifts using the second configuration, fewer qubits are needed in the workspace, but the quantum circuit becomes much deeper than in the first configuration. For example, in QFT-based shifts, the number of gates increases quadratically in proportion to the size of the state space. Also, QFT-based shifts rely on precise rotation gates and phase transition gates, which are very sensitive to noise.

[0005] On the other hand, the first configuration has low computational complexity, and the number of gates increases linearly with the size of the state space. Execution time is primarily device-dependent, but it is understandable that execution time will be shorter as lower computational complexity generally requires less computation. While the size of the first configuration increases or decreases linearly, the initial gate cost is high, which significantly impacts computational complexity in practical applications. Furthermore, the process of setting up quantum circuits is quite complex.

[0006] To mitigate the shortcomings of the state-shift algorithm and achieve further improvements, redesign and optimization of the state-shift algorithm are necessary. Abstract

[0007] The present disclosure (hereinafter referred to as "the Disclosure") aims to provide a method for performing a multistep quantum ground state shift using a fixed number of ancilla qubits. The Disclosure also aims to provide a quantum computer or quantum simulator configured to perform the aforementioned method. The Disclosure further aims to provide a quantum circuit for performing a multistep quantum ground state shift using a fixed number of ancilla qubits. The object of the Disclosure is achieved by the method, quantum computer or quantum simulator, and quantum circuit described in the attached independent claims. Advantageous features are described in the attached dependent claims.

[0008] Throughout this specification and in its claims, phrases such as “equipped with,” “include,” and “possess” do not mean that they include a certain element but not that they include only that element. They do not preclude the existence of other components, items, numbers, or steps that are not expressly disclosed. Furthermore, unless otherwise specified in the context, singular expressions also include plural forms. In particular, where an indefinite article is used in the original text, this specification assumes both singular and plural forms unless otherwise required in the context. [Brief explanation of the drawing]

[0009] [Figure 1]This is a schematic diagram illustrating a part of a method for performing a multistep quantum ground state shift using a fixed number of ancilla qubits according to embodiments of the present disclosure. [Figure 2A-2C] Detailed diagrams of quantum circuits for performing multi-step quantum ground state shifts using a fixed number of ancilla qubits, according to embodiments of this disclosure, are shown. [Figure 2D] A detailed diagram of an example of a quantum circuit for the case N=5, i=0, j=2 according to an embodiment of this disclosure is shown. [Figure 3] An example of a multi-step quantum ground state shift on a two-dimensional lattice according to an embodiment of this disclosure is shown. [Figure 4] A detailed diagram of a quantum circuit according to an embodiment of the present disclosure is shown. This quantum circuit uses two controlled swap blocks to perform two multistep quantum ground state shifts in two dimensions. [Figure 5] This shows how the number of CX gates in various bidirectional shifts with step size 1 changes with respect to the number of qubits (N) used to encode the one-dimensional lattice. Detailed description of the embodiment

[0010] The following detailed description illustrates embodiments of the Disclosure and the ways in which they may be carried out. While several forms for carrying out the Disclosure have been disclosed, those skilled in the art will recognize that other forms for carrying out the Disclosure are also possible.

[0011] According to the first aspect, embodiments of the present disclosure provide a method that is performed by a quantum computer or quantum simulator. This method is 2 N+1 Setting up a shift register and an ancilla register for a quantum circuit used to perform a multistep quantum ground state shift in a state vector space of size n, wherein the shift register has a total of N+1 qubits, and the first N qubits (q) of the shift register 1, q 2, ...q N) forms an array register, and the last qubit (q N+1 ) of the shift register is an entangled qubit, and the ancilla register includes at most - two ancilla qubits (a1,... a N-i-2 ), provided that the step index i is a non - negative integer less than N, said setting; 2 N+1 For an input state having array sub - states, regarding the array sub - states where the entangled qubit (q N+1 ) is 0 as the array sub - states to be incremented, and regarding the array sub - states where the entangled qubit (q N+1 ) is 1 as the array sub - states to be decremented, dividing the input state into a first subset that is a subset including the array sub - states to be incremented and a second subset that is a subset including the array sub - states to be decremented; In the multi - step quantum ground - state shift, for the case where the step size is 2 i , setting the quantum circuit when i < N - 2; including, said setting of the quantum circuit is Regarding the sub - states where the k - th (k = i + 1) qubit (q k ) is 0 as even sub - states, and regarding the sub - states where the k - th qubit (q k ) is 1 as odd sub - states, decomposing the first subset into even sub - states to be incremented and odd sub - states to be incremented, and decomposing the second subset into even sub - states to be decremented and odd sub - states to be decremented; Remapping the state amplitudes of the even sub - states to be decremented and the state amplitudes of the odd sub - states to be decremented; Regarding the sub - states where the k - th qubit (q k ) is 0 as even sub - states, and also regarding the k - th qubit (q kBy considering a substate where ) is 1 as an odd substate, the incrementing odd substate is decomposed into a further incrementing even substate and a further incrementing odd substate by a recursive process in which k increases by 1 until it reaches i+j, and the decrementing even substate is decomposed into a further decrementing even substate and a further decrementing odd substate, where j is the number of ancilla qubits in the ancilla register; In each recursion, the state amplitude of the even substate to be further decremented is remapped to the state amplitude of the odd substate to be further decremented; The kth qubit (q k Substates where ) is 0 are considered even substates, and the k-th qubit (q k By considering a substate where ) is 1 as an odd substate, the recursive process in which k is further incremented by 1 in each recursion until k reaches N-1 decomposes the odd substate to be further incremented into an even substate to be further incremented and an odd substate to be further incremented, and the even substate to be further decremented is recursively decomposed into an even substate to be further decremented and an odd substate to be further decremented; In each recursion, the state amplitude of the even substate to be further decremented is remapped to the state amplitude of the odd substate to be further decremented; The kth qubit (q k With respect to the adjacent decrement target even substates, the size 2 k The amplitude block is swapped, and the k-th qubit (q k Regarding ), between adjacent incrementable odd substates, the size is 2 k To swap the amplitude block, the k+1th qubit (q k+1 The inversion of ) where k starts from N-1 and is decremented by 1 in each recursion until it reaches i+j; In each recursion, the remapping of the state amplitudes of the even substates targeted for further decrement and the state amplitudes of the odd substates targeted for further decrement is reversed; The recursive decomposition of the aforementioned odd substates subject to further increment and the aforementioned even substates subject to further decrement is reversed, wherein in each recursion, the decomposition by the recursive process, the inversion, and the reversal of the decomposition by the recursive process are performed by corresponding multi-control gates; The kth qubit (q k With respect to the adjacent decrement target even substates, the size 2 k The amplitude block is swapped, and the k-th qubit (q k Regarding ), between adjacent incrementable odd substates, the size is 2 k To swap the amplitude block, the k+1th qubit (q k+1 The inversion of ) where k starts from i+j and is further decremented by 1 in each recursion until it reaches i+1; Reversing the remapping of the state amplitudes of the even substates targeted for further decrement and the state amplitudes of the odd substates targeted for further decrement; The recursive decomposition of the odd substates to be incremented and the even substates to be decremented is reversed, wherein the reversal and the remapping are repeated prior to the reversal of each recursion of the decomposition by the recursive process; The k-th (where k=i+1) qubit (q k With respect to the adjacent decrement target even substates, the size 2 k The amplitude block is swapped, and the k-th qubit (q k Regarding ), between adjacent incrementable odd substates, the size is 2 k To swap the amplitude block, the first ancilla qubit (a1) of the ancilla register is used as control to swap the k+1th qubit (q k+1 ) and reversing it; Reversing the remapping of the state amplitudes of the even substates to be decremented and the state amplitudes of the odd substates to be decremented; Reversing the decomposition of the array substates of the first subset and the array subsets of the second subset; The aforementioned multi-step quantum ground state shift with a step size of 2 i To complete the multistep quantum ground state shift of the state amplitude based on, the i+1th qubit (q i+1 ) and reversing it; It is done by [the specified method].

[0012] According to the second interpretation, one embodiment of the present disclosure provides a quantum computer or quantum simulator configured to perform the method according to the first interpretation described above.

[0013] This disclosure provides the aforementioned method and the aforementioned quantum computer or quantum simulator. The aforementioned method provides a step size of 2, which is a power of 2. i Multistep quantum ground state shifts can be performed using this method. Advantageously, multistep quantum ground state shifts can be performed simultaneously in multiple shift directions with the same computational complexity class as single-step ground state shifts. In this regard, as will be discussed later, certain preparatory steps are performed to ensure the correct superposition of "direction substates." This enables a significant increase in quantum speed. Furthermore, by combining multistep quantum ground state shifts performed using the aforementioned method, it is possible to create multistep quantum ground state shifts of any step size.

[0014] The aforementioned method can be considered a redesign of the first configuration described in the background section. This method significantly reduces the initial gate cost, thereby making parallel shifts competitive with QFT-based shifts even with a small number of qubits, despite having a much simpler conceptual design. In particular, this allows for easy extension to multi-stepping and higher-dimensional lattice shifts.

[0015] One of the key advantages of the aforementioned method is the natural parallelization that arises from the superposition of array substates. The number of qubits in the shift register depends on the size of the state vector space. Specifically, if the size of the state vector space is 2 N+1 In this case, the shift register consists of a total of N+1 qubits. Of these N+1 qubits, the last qubit (q) of the entire shift register N+1 ) is a superposition qubit. This superposition qubit allows us to define a superposition of two array substates that are orthogonal (with respect to increment and decrement). In this respect, in the step of partitioning the input state, the superposition qubit is used to determine which array substates are to be incremented (i.e., the first subset) and which array substates are to be decremented (i.e., the second subset). N+1 Array substates where ) is 0 are considered to be incrementable, and the superposition qubit (q N+1 Array substates where ) is 1 are considered to be subject to decrement. As a result, the number of array substates in the first subset and the number of array substates in the second subset are both 2 N The first subset and the second subset mentioned above are (the first N qubits (q) of the shift register. 1, q 2, ...q NAt each array point defined by the fundamental state of the array register (composed of ), there are linked state amplitudes that are shifted "up" and state amplitudes that are shifted "down". This means that there are two layers of state amplitudes on the position space defined by the array register (which can be interpreted as, for example, a regular polygonal grid). This means that the total amount of data in the state vector space is 2 N+1 This means the state amplitude, which is also called the size of the state vector space. Here, the superposition qubits are marked as 0. N The array substates are subject to increment, and the superposition qubit is marked as 1. N The array substates are subject to decrement. Therefore, the first subset of array substates that are subject to increment, and the second subset of array substates that are subject to decrement, refer to a superposition of two probability distributions on the same position space defined by the array register. The array substates of the first subset and the array substates of the second subset are the first N qubits (q) of the array register, i.e., the shift register. 1, q 2, ...q N It is defined using ).

[0016] What is noteworthy is (step size 2 i The even substates subject to incrementing are simply the i+1th qubit (q i+1 The key point is that it can be incremented simply by applying a step that inverts ). This qubit is also called a step qubit. Similarly, (step size 2 i The odd substates that are subject to decrement (in this case) are also the i+1th qubit (q i+1 The (i.e., step qubit) can be decremented by applying the same step of inverting it. The remaining steps in the quantum circuit are used to rearrange the even substates to be decremented and the odd substates to be incremented as follows: the (i+1)th qubit (q i+1The step of inverting the (i+1) substate is used to rearrange the decremented even substates and incremented odd substates so that a multi-step quantum ground state shift is performed in one step. Notably, since the inverting step essentially deals with the incremented even substates and decremented odd substates, no special rearrangement is required for them. Throughout this specification, the notation "i+1th" refers to the (i+1)th substate. In other words, the parentheses are omitted for convenience and to improve readability. The same notation is used for other similar terms.

[0017] Furthermore, the number of ancilla qubits in the ancilla register depends on both the step size of the multistep quantum ground state shift and the selected transition point between the following two sections: (i) Cascaded sections corresponding to the recursive decomposition of the odd substates to be incremented and the even substates to be decremented, the reversal of this decomposition, and other related steps such as remapping, inversion, and reversal of the remapping, (ii) A fused multi-controlled section corresponding to the recursive decomposition of the further incrementable odd substates and the further decrementable even substates, the inversion of the decomposition, and other related steps such as remapping, inversion, and inversion of the remapping, wherein in each recursion, the recursive decomposition, the inversion, and the inversion of the recursive decomposition are performed by corresponding multi-controlled gates.

[0018] The cascade section is described in U.S. Patent Application No. 18 / 980,430, "Multi-step Quantum Basis State Shift," and the fused multi-control section is described in U.S. Patent Application No. 19 / 254,223, "Multi-step Quantum Basis State Shift Using Reduced Number of Ancilla Qubits." The contents of both documents are incorporated herein by reference.

[0019] In particular, for a step index i that is a non-negative integer less than N, the step size is 2 i In this case, the maximum number of ancilla qubits is limited to Ni-2. The cascade section continues decomposition by recursion until the decomposition index k reaches i+j, where j is the number of ancilla qubits used. Beyond this point, the quantum circuit moves to a fused multi-control section, and no further ancilla qubits are needed. Therefore, increasing j allows the cascade section to be extended deeper before the fused multi-control section, reducing the number of multi-control gates, but requiring larger ancilla registers. Conversely, decreasing j shortens the cascade section, reducing the qubit footprint, but increasing the gate complexity of the fused multi-control section. Thus, the number of ancilla qubits is determined by the trade-off between the number of available hardware qubits, the acceptable noise level, and the optimization of circuit depth and gate count. In practice, ancilla allocation can be guided by the point at which extending the cascade section yields a decrease in return compared to moving to the fused multi-control section earlier.

[0020] In embodiments of this specification, the step size is 2 iIt is defined as follows: That is, the step index i is used. This index is a non-negative integer less than N. The number of steps in the method for performing a multi-step quantum ground state shift depends on the step size. In other words, the number of steps in the method depends on the value of the step index i. This will be discussed later.

[0021] For illustrative purposes, the following shows how the quantum circuit is configured in the method described above.

[0022] When i < N-2, the quantum circuit is set up by performing the following steps.

[0023] Decomposing step (#1): The array substates of the first subset (i.e., the array substates to be incremented) are decomposed into even substates and odd substates to be incremented. On the other hand, the array substates of the second subset (i.e., the array substates to be decremented) are decomposed into even substates and odd substates to be decremented. In this respect, the k-th qubit (q k Substates where ) is 0 are considered even substates, and the k-th qubit (q k Substates where ) is 1 are considered odd substates. In this decomposition step, k = i + 1. i + 1 is simply the initial value of k, and as will be described later, the value of k is incremented with each recursion in the subsequent recursive step. k ) is called a partitioned qubit, and k is called the partition index. In the decomposition step (#1), it will be understood that the array substates are partitioned into smaller substates. In each subsequent decomposition, the substates are partitioned into even smaller substates. At the finest level, the smallest substate consists of a single amplitude corresponding to the ground state.

[0024] Remapping step (#2): The state amplitude of the even substate to be decremented is remapped to the state amplitude of the odd substate to be decremented. This remapping is performed on the k-th qubit (q) of the array register. k This does not affect any qubits other than the one being decremented. This remapping can also be described as a step of swapping (flipping) the even substates to be decremented with the odd substates to be decremented. This swapping operation does not affect the data; that is, the data remains held in the state amplitude.

[0025] Recursive decomposition step in the cascade section (#3A): The odd substates targeted for incrementing are recursively decomposed into further even substates targeted for incrementing and further odd substates targeted for incrementing. Similarly, the even substates targeted for decrementing are further decomposed into further even substates targeted for decrementing and further odd substates targeted for decrementing through recursion. In this respect, the k-th qubit (q k Substates where ) is 0 are considered even substates, and the k-th qubit (q k Substates where ) is 1 are considered odd substates. In the recursive decomposition step (#3A), the value of k is incremented by 1 each time it recurs until it reaches i+j. Therefore, the number of recurs in the recursive decomposition step (#3A) depends on the value of j. Specifically, the number of recurs is until k reaches i+j from its initial value i+1. In particular, the recursion of step (#3A) is executed one or more times for various values ​​of k from i+2 to i+j.

[0026] Remapping step (#4A) in each recursion of the recursive decomposition process in the cascade section: After each recursion in the recursive decomposition step (#3A), the state amplitudes of the even substates targeted for further decrement and the state amplitudes of the odd substates targeted for further decrement are remapped. In each recursion, this remapping is performed on the k-th qubit (q) of the array register. kThis does not affect any other qubits. As mentioned above, the even substates and odd substates targeted for further decrement are simply swapped while retaining their state amplitude data.

[0027] Recursive decomposition step (#3B) in the fused multi-control section: Further incrementable odd substates are ultimately decomposed recursively into even further incrementable even substates and even further incrementable odd substates. Similarly, further decrementable even substates are ultimately decomposed recursively into even further decrementable even substates and even further decrementable odd substates. In this respect, the k-th qubit (q k Substates where ) is 0 are considered even substates, and the k-th qubit (q k Substates where ) is 1 are considered odd substates. In the recursive decomposition step (#3B), with each recursion, the value of k is further incremented by 1 until it reaches N-1. Therefore, the number of recurs in the recursive decomposition step (#3B) depends on the values ​​i, j, and N. That is, the number of recurs corresponds to k from i+j to N-1. In particular, the recursion of step (#3B) is executed one or more times for various values ​​of k from i+j+1 to N-1.

[0028] Remapping step (#4B) in each recursion of the recursive decomposition process in the fused multi-control section: The state amplitudes of the even substates targeted for further decrement are remapped to the state amplitudes of the odd substates targeted for further decrement. In each recursion, this remapping is performed on the k-th qubit (q) of the array register. k This does not affect any other qubits. As mentioned above, the even substates and odd substates targeted for further decrement are simply swapped while retaining their state amplitude data.

[0029] Inverting step (#5B) in the fused multi-control section: The (k+1)th qubit (q k+1 ) is inverted. As a result, the k-th qubit (q k Regarding ), between adjacent decrement target even substates, the size is 2 k The amplitude block is swapped, and the k-th qubit (q k Regarding ), between adjacent incrementable odd substates, the size is 2 k The amplitude block is exchanged. The inversion step (#5B) is performed using a value of k that is decremented by 1 after each recursion, starting from N-1 and reaching i+j. The aforementioned exchange does not shift the entire quantum state, but only exchanges specific substates at specific positions in the decomposition sequence. This specific position is the k-th qubit (q k This is defined by ), which will also be referred to as “substate shift” throughout this specification.

[0030] Reversing step (#6B) of remapping step (#4B) in the fused multi-control section: In this step, we reverse the remapping step (#4B) described above. In other words, we undo the swapping (flipping) performed in step (#4B).

[0031] In the fused multi-control section, the step of reversing the decomposition step by recursive processing (#3B) is performed (#7B): In this step, the recursive decomposition step (#3B) described above is reversed. The reversal step of the recursive decomposition step can also be called the recursively re-composing step.

[0032] In each recursion of the fused multi-control section, there is a decomposition step by recursive processing (#3B) and the k+1th qubit (q k+1The inversion step (#5B) and the step (#7B) that reverses the decomposition step (#3B) are performed using the corresponding multi-control gate. In other words, these steps are fused together into a single quantum gate. In these steps, the value of k starts at N-1 and is decremented by 1 after each recursion until it reaches i+j.

[0033] Reversal step in the cascade section (#5A): The (k+1)th qubit (q k+1 ) is inverted. As a result, the k-th qubit (q k Regarding ), between adjacent decrement target even substates, the size is 2 k The amplitude block is swapped, and the k-th qubit (q k Regarding ), between adjacent incrementable odd substates, the size is 2 k The amplitude block is swapped. Here, the size of the swap depends on the split index 'k'. This is because the quantum gate used for inversion (also called an inverter) is the k+1th qubit (q k+1 This is because it is based on ). The inversion step (#5A) is performed using the value of k, which is decremented by 1 after each recursion, starting from i+j and reaching i+1.

[0034] The aforementioned exchange does not shift the entire quantum state, but rather exchanges only specific substates at a particular position in the decomposition sequence. This particular position is the k-th qubit (q k This is defined by ), which will also be referred to as “substate shift” throughout this specification.

[0035] Step (#6A) that reverses the aforementioned remapping step (#4A) in the cascade section: In this step, we reverse the remapping step (#4A) described above. In other words, we undo the swapping (flipping) performed in step (#4A).

[0036] In the cascade section, the step (#7A) reverses the aforementioned decomposition step (#3A) by recursive processing: In this step, the aforementioned recursive decomposition step (#3A) is reversed by recursion. The reversal step of the recursive decomposition step can also be called the recursively re-composing step. The aforementioned inversion step (#5A) and the remapping inversion step (#6A) are repeated before each recursion of the recursive decomposition step (#7A). In other words, the inversion step (#5A) and the remapping inversion step (#6A) are executed before each recursion of the recursive decomposition step (#7A). In these steps, the value of k starts from i+j and is decremented by 1 after each recursion until it reaches i+1.

[0037] Reversal step (#8) before reversing the decomposition step (#1): When the value of k reaches i+1, the k+1th qubit (q k+1 )(that is, the i+2th qubit (q i+2 This inverts the kth qubit (q). k )(that is, the i+1th qubit (q i+1 Regarding ), between adjacent decrement target even substates, the size is 2 k (that is, 2 i+1 The amplitude block of ) is swapped, and the k-th qubit (q k Regarding ), between adjacent incrementable odd substates, the size is 2 k Replace the amplitude block.

[0038] Here, the size of the exchange (i.e., substate shift) depends on the partition index 'k'. This is because the quantum gate used for inversion (i.e., inverter) is the k+1th qubit (q). k+1 This is because it is based on the fact that when the value of k reaches i+1, the k+1th qubit (q k+1) will point to the (i + 2)-th qubit (q i+2 ) of the array register. As mentioned above, the exchange does not shift the entire quantum state, but only exchanges specific sub-states at specific positions in the decomposition sequence. This specific position is defined by the k-th qubit (q k ), that is, the (i + 1)-th qubit (q i+1 ).

[0039] Reversal step (#9) of the above-mentioned remapping step (#2): In this step, the above-mentioned remapping step (#2) is reversed. That is, the flipping performed in step (#2) is restored. This step is also executed before reversing the decomposition step (#1).

[0040] Reversal step (#10) of the above-mentioned decomposition step (#1): In this step, the decomposition step (#1) is reversed. The step of reversing the decomposition step can also be called the re-composing step.

[0041] Final reversal step (#11): Step size 2 i To complete the multi-step quantum basis state shift of the state amplitudes based on, the (i + 1)-th qubit (q i+1 )(i.e., the step qubit) is reversed. This final reversal step (#11) completes the multi-step quantum basis state shift for the entire state of the array register prepared by the previous shift sequence of sub-states (i.e., the previous reversal steps). The final reversal step (#11) exchanges amplitude blocks of size 2 between adjacent decrement-target even sub-states with respect to the i-th qubit (qi), and also exchanges amplitude blocks of size 2 between adjacent increment-target odd sub-states with respect to the i-th qubit (qi). i i

[0042] ​​FIG. 1 is a schematic diagram showing a part of the foregoing method according to an embodiment of the present disclosure. This part includes the following steps.

[0043] Step S1.0 shows the foregoing step of dividing an input state p (including 2 N+1 array sub-states) into a first subset p+ of array sub-states to be incremented and a second subset p- of array sub-states to be decremented. In FIG. 1, the double line indicates the sub-state to be incremented, and the single line indicates the sub-state to be decremented.

[0044] Step S1.1 shows the foregoing decomposition step (#1). In FIG. 1, this "decomposition" is indicated by the phrase "decompose". In FIG. 1, the even sub-states are marked with respect to the split quantum bit (i.e., the k-th quantum bit q k ). Therefore, e(k) indicates the even sub-state, and o(k) indicates the odd sub-state. The initial value of k is equal to i + 1. That is, the decomposition step (#1) starts from the split index k = i + 1. In FIG. 1, the dashed line is used to represent the odd sub-state, and the solid line is used to represent the even sub-state.

[0045] Step S1.2 shows the foregoing remapping (step #2). In FIG. 1, this remapping is indicated by the phrase "flip" (swap). In this specification, "remapping" and "swap" are used interchangeably. Up to this step, the value of k is i + 1.

[0046] Step S1.3 shows the first recursion of the decomposition step (#3A) by the foregoing recursive processing in the cascade section. The value of k increases by 1 for each recursion.

[0047] Step S1.4 shows the foregoing remapping step (#4A). This is executed after the first recursion of the decomposition step (#3A) by the recursive processing in the cascade section.

[0048] Step S1.5 represents the second recursion of the aforementioned recursive decomposition step (#3A) in the cascade section. The method then continues as described above. For example, step S1.5 is followed by the aforementioned remapping step (#4A). This is executed after the second recursion of the recursive decomposition step (#3A) in the cascade section. In the cascade section, the recursive decomposition step (#3A) and the remapping step (#4A) are executed until the partition index k reaches i+j.

[0049] When k reaches i+j, the first recursion of the recursive decomposition step (#3B) in the fused multi-control section is performed as described above. The method then continues as described above. Then, remapping is performed according to the mapping step (#4B) described above. The one or more recursions of the recursive decomposition step (#3B) and remapping step (#4B) in the fused multi-control section are repeated until the partition index k reaches N-1.

[0050] Subsequently, a controlled inversion is performed according to the aforementioned inversion step (#5B). The remapping inversion and recursive decomposition inversion in the fused multi-control section are also performed according to the aforementioned steps (#6B) and (#7B), respectively. As previously mentioned, the recursive decomposition step (#3B), inversion step (#5B), and recursive decomposition inversion step (#7B) are fused together into the corresponding multi-control gate. After each recursion of these steps in the fused multi-control section, the value of k is decremented. This continues until the value of k reaches i+j.

[0051] Subsequently, the inversion step (#5A) in the cascade section is recursively executed to shift the decomposed substates and reverse the cascade of the previous remapping and decomposition steps. In this recursive process, k is decremented by 1 after each recursion. This recursion is repeated until k reaches i+1. Note that in the above explanation, reversing the previous remapping step refers to the process that follows the remapping inversion step (#6A), and reversing the previous decomposition step refers to the process that follows the recursive decomposition inversion step (#7A). However, for simplification, method steps executed after step S1.5 are not shown in Figure 1. As shown in Figure 1, the cascade of ancilla qubits in an ancilla register implements pairs of even and odd substates as preparation for a multistep quantum ground state shift.

[0052] The method described above has so far explained the case where i < N-2. Different steps may be performed for other values ​​of step index 'i'. This will be discussed later.

[0053] In some embodiments, the method further comprises, in the case i = N-2, a quantum circuit, The (i+1)th qubit (q) i+1 Substates where is 0 are considered even substates, and the (i+1)th qubit (q i+1 By considering substates where ) is 1 as odd substates, the first subset is decomposed into even substates to be incremented and odd substates to be incremented, and the second subset is decomposed into even substates to be decremented and odd substates to be decremented; Remapping the state amplitude of the even substate to be decremented with the state amplitude of the odd substate to be decremented; The (i+1)th qubit (q) i+1 With respect to the adjacent decrement target even substates, the size 2 i+1 The amplitude block is swapped, and the i+1th qubit (q i+1Regarding ), between adjacent incrementable odd substates, the size is 2 i+1 To swap the amplitude block, the first ancilla qubit (a1) of the ancilla register is used as the control to swap the i+2th qubit (q i+2 ) and reversing it; Reversing the step of remapping the state amplitude of the even substate to be decremented with the state amplitude of the odd substate to be decremented; Reversing the aforementioned disassembly step; The i+1th qubit (q i+1 By reversing ), 2 i Completing a multi-step quantum ground state shift of state amplitude based on the step size; This includes setting by [the specified method].

[0054] In particular, when i = N-2, the method is performed as follows.

[0055] The aforementioned decomposition step (#1) is performed. No decomposition by recursion is performed because the initial value k (which is considered to be i+1) becomes N-1. In this step (#1), the array substates of the first subset (i.e., the array substates to be incremented) are decomposed into even substates to be incremented and odd substates to be incremented. On the other hand, the array substates of the second subset (i.e., the array substates to be decremented) are decomposed into even substates to be decremented and odd substates to be decremented. In this respect, the (i+1)th qubit (q i+1 ), that is, the k-th qubit (q k Substates where ) is 0 are considered even substates, and the i+1th qubit (q i+1 ), that is, the k-th qubit (q k A substate where ) is 1 is considered an odd substate.

[0056] Next, the aforementioned remapping step (#2) is performed. In this step, the state amplitudes of the even substates to be decremented and the state amplitudes of the odd substates to be decremented are remapped.

[0057] In particular, if i = N-2, the next step is skipped. In the cascade section, the decomposition step by recursion (#3A), In the recursive decomposition process in the cascade section, the remapping step (#4A) in each recursion, In the fused multi-control section, the decomposition step by recursive processing (#3B) In each recursion of the recursive decomposition process in the fused multi-control section, the remapping step (#4B) Inversion step in the fusion multi-control section (#5B), Reversal step of remapping in the fused multi-control section (#6B), Reverse step of recursive decomposition process in fused multi-control section (#7B) Reversal step in the cascade section (#5A), Reversal step of remapping step in cascade section (#6A), Reverse step of the recursive decomposition process in the cascade section (#7A).

[0058] The aforementioned inversion step (#8) is performed. Since the value of k is i+1, the first ancilla qubit (a1) of the ancilla register is used as control, and the i+2th qubit (q i+2 ), that is, the k+1th qubit (q k+1 ) is inverted. As a result, the i+1th qubit (q i+1 ), that is, the k-th qubit (q k Regarding ), between adjacent decrement target even substates, size 2 i+1 The amplitude blocks are swapped. Similarly, the i+1th qubit (q i+1 ), that is, the k-th qubit (q kRegarding ), between adjacent odd substates that are subject to increment, size 2 i+1 The amplitude blocks are swapped.

[0059] The aforementioned remapping step (#2) is reversed, and the aforementioned step (#9) is executed.

[0060] Subsequently, the aforementioned step (#10) is performed, which reverses the aforementioned decomposition step (#1).

[0061] Finally, the aforementioned final inversion step (#11) is performed. In this step, 2 i To complete the multistep quantum ground state shift of the state amplitude based on the step size, the i+1th qubit (q i+1 ) can be reversed.

[0062] Depending on the embodiment, the method further comprises, in the case i = N-1, the quantum circuit being the i+1th qubit (q i+1 By reversing ), 2 i This includes setting by completing a multi-step quantum ground state shift of the state amplitude based on the step size.

[0063] In particular, when i = N-1, only the final inversion step (#11) is performed, and 2 i To complete the multistep quantum ground state shift of the state amplitude based on the step size, the i+1th qubit (q i+1 ) is inverted. i = N-1 has a size of 2 N+1 This corresponds to the largest possible step size for the state vector space. This corresponds to a step size of 2. i The size of the array register (i.e., 2 N This is because it is exactly half of the original value, and flipping the most significant qubit of an array register corresponds to a two-way shift.

[0064] For illustrative purposes only, an example of a quantum circuit that can be configured for i < N-2 or i = N-2 is shown below. Depending on the embodiment, this quantum circuit comprises the following elements in order: A starting segment with two CX gates; Depending on the embodiment, an intermediate segment having a plurality of CX gates and a plurality of multi-control gates, each having two or more controls; A terminal segment having three CX gates and one X gate.

[0065] Note that intermediate segments may not be included. This is because, in the case of i = N-2, the quantum circuit does not include intermediate segments. These intermediate segments correspond to the next step. In the cascade section, the decomposition step by recursion (#3A), In the recursive decomposition process in the cascade section, the remapping step (#4A) in each recursion, In the fused multi-control section, the decomposition step by recursive processing (#3B) In each recursion of the recursive decomposition process in the fused multi-control section, the remapping step (#4B) Inversion step in the fusion multi-control section (#5B), Reversal step of remapping in the fused multi-control section (#6B), Reverse step of recursive decomposition process in fused multi-control section (#7B) Reversal step in the cascade section (#5A), Reversal step of remapping step in cascade section (#6A), Reverse step of the recursive decomposition process in the cascade section (#7A).

[0066] As mentioned earlier, these steps are skipped when i = N-2. That is, when i = N-2, the quantum circuit has the following elements in order: • A starting segment with two CX gates; • A terminal segment with three CX gates and three X gates.

[0067] Depending on the embodiment, the two CX gates of the starting segment are applied in the following order: • The (i+1)th qubit of the array register (q i+1 ) is used as the control corresponding to state |1>, and a CX gate targets the first ancilla qubit (a1) of the ancilla register; • Superposition qubit (q) of a shift register N+1 A CX gate is used, targeting the first ancilla qubit (a1) of an ancilla register, with the control corresponding to state |1>.

[0068] To perform the decomposition step (#1), the first of the two CX gates in the starting segment is applied. As mentioned above, in the decomposition step (#1), the array substates of the first subset (i.e., the array substates to be incremented) are decomposed into even substates to be incremented and odd substates to be incremented. On the other hand, the array substates of the second subset (i.e., the array substates to be decremented) are decomposed into even substates to be decremented and odd substates to be decremented. In this regard, the k-th qubit (q k Substates where ) is 0 are considered even substates, and the k-th qubit (q k Substates where ) is 1 are considered odd substates. In this decomposition step, the value of k is considered to be i+1. Thus, the first CX gate of the start segment is the (i+1)th qubit (q) of the array register. i+1 Use ) as the control.

[0069] To perform the remapping step (#2), the last of the two CX gates in the starting segment is applied. As mentioned above, in the remapping step (#2), the state amplitudes of the even substates to be decremented and the state amplitudes of the odd substates to be decremented are remapped. Therefore, the last CX gate in the starting segment is applied to the superposition qubit (q) of the entire shift register. N+1 Use ) as the control.

[0070] Furthermore, depending on the embodiment, the three CX gates of the terminal segment are applied in the following order: The first ancilla qubit (a1) of the ancilla register is used as the control corresponding to state |1>, and the i+2th qubit (q) of the array register is used. i+2 ) CX gate targeting; • Superposition qubit (q) of a shift register N+1 ) is used as the control corresponding to state |1>, and a CX gate targets the first ancilla qubit (a1) of the ancilla register; • The (i+1)th qubit of the array register (q i+1 ) is used as the control corresponding to state |1>, and a CX gate targets the first ancilla qubit (a1) of the ancilla register; Here, the (i+1)th qubit (q) of the array register i+1 An X-gate is applied to ).

[0071] To perform the inversion step (#8), which is executed before reversing the decomposition step (#1), the first of the three CX gates in the terminal segment is applied in order. As mentioned above, the value of k reaches i+1 again. Therefore, in the inversion step (#8), the first qubit (a1) of the ancilla register is used as control to control the k+1th qubit (q k+1 )(that is, the i+2th qubit (q i+2 )) is inverted. As a result, the i+1th qubit (q i+1 Regarding ), between adjacent decrement target even substates, the size is 2i+1 The amplitude block is swapped, and the (i+1)th qubit (q i+1 Regarding ), between adjacent incrementable odd substates, the size is 2 i+1 The amplitude block is replaced.

[0072] To perform the step (#9) that reverses the state amplitude remapping step (#2), the middle CX gate of the three CX gates in the terminal segment is applied in order. Thus, the middle CX gate of the terminal segment is the superposition qubit (q) of the shift register. N+1 ) is used as control. Notably, the same qubits applied to perform the aforementioned remapping step (#2), namely the superposition qubits of the shift register (q N+1 ) is used as control by the last CX gate of the starting segment.

[0073] To perform step #10 (i.e., the reconstruction step), which reverses the aforementioned decomposition step (#1), the last of the three CX gates in the terminal segment is applied in order. Thus, the last CX gate in the terminal segment is applied to the (i+1)th qubit (q) of the array register. i+1 ) is used as control. Notably, the same qubit that is applied to perform the aforementioned decomposition step (#1), namely the i+1th qubit (q) of the array register, is used. i+1 ) is used as control by the first CX gate of the starting segment.

[0074] The X gate in the terminal segment is applied to perform the final inversion step (#11) described above. As mentioned earlier, in the final inversion step (#11), step size 2 i To complete the multistep quantum ground state shift of the state amplitude according to the (i+1)th qubit (q i+1 ) is inverted. Therefore, the (i+1)th qubit (q) of the array register is inverted. i+1 An X-gate is applied to ).

[0075] In some embodiments, the intermediate segment has one or more sets of multiple CX gates and multiple multi-control gates. The multiple CX gates and multiple multi-control gates in the intermediate segment take the form of multiple sets of multiple CX gates and multiple multi-control gates. In this respect, the number of sets in the intermediate segment depends on the number of recursions of the decomposition step by recursion. This recursion includes one or more recursions of the recursive decomposition step (#3A) in the cascade section and one or more recursions of the recursive decomposition step (#3B) in the fused multi-control section. Note that the number of recursions of step (#3A) depends on the number of ancilla qubits j, because the recursion continues until k reaches i+j (from the initial value i+1). The number of recursions of step (#3B) depends on the number of ancilla qubits j, the step step i, and the number of working qubits in the array register. This is because the recursion continues until k reaches N-1 from its initial value i+j.

[0076] In this regard, the first level of recursion occurs until k reaches i+j from its initial value i+1. k is incremented by 1 with each recursion. The second level of recursion occurs until k reaches N-1 from its initial value i+j. k is further incremented by 1 with each recursion. The first level of recursion corresponds to a cascaded section, and the second level of recursion corresponds to a fused multi-control section.

[0077] In the first level of recursion, a given set corresponding to a given recursion includes, in order, the following elements: • Superposition qubit (q) of a shift register N+1 ) is used as the control corresponding to state |1>, and the k-th qubit (q) of the array register is used. k The first CX gate targets ); • The k-th qubit (q) of the array register k ) and the ki-1th ancila qubit of the ancila register (a k-i-1) is used as the control corresponding to state |1>, and the ki-th ancilla qubit (a k-i The first multi-control gate that uses ) as its target; • The ki-th ancila qubit of the ancila register (a k-i ) is used as the control corresponding to state |1>, and the k+1th qubit (q) of the array register is used. k+1 The second CX gate uses ) as its target; • The k-th qubit (q) of the array register k ) and the ki-1th ancila qubit of the ancila register (a k-i-1 ) is used as the control corresponding to state |1>, and the ki-th ancilla qubit (a k-i A second multi-control gate that uses ) as its target; • Superposition qubit (q) of a shift register N+1 ) is used as the control corresponding to state |1>, and the k-th qubit (q) of the array register is used. k The third CX gate, targeting ).

[0078] After each recursion of the recursive decomposition step (#3), the first CX gate is applied to a given set of intermediate segments to perform the remapping step (#4A). In the remapping step (#4A), the state amplitudes of the even substates to be further decremented are remapped to the state amplitudes of the odd substates to be further decremented. To perform the remapping step (#4A), the first CX gate is applied to the superposition qubit (q) of the shift register. N+1 ) is used as control, and the k-th qubit (q) of the array register is used. k It is applied using ) as the target. Note that the value of k also changes with each recursion, making it possible to perform a remapping step on smaller substates.

[0079] To perform the recursive decomposition step (#3A), the first multi-control gate of a given set of intermediate segments is applied. In the recursive decomposition step (#3A), the incrementing odd substate is recursively decomposed into a further incrementing even substate and a further incrementing odd substate, and the decrementing even substate is recursively decomposed into a further decrementing even substate and a further decrementing odd substate. In this respect, the k-th qubit (q k Substates where ) is 0 are considered even substates, and the k-th qubit (q k Substates where ) is 1 are considered odd substates. In each recursion of the recursive decomposition step (#3A), the value of k is incremented by 1 from the initial value i+1 until it reaches i+j. In other words, a given set (corresponding to a given recursion) has a unique k value because k is incremented in each recursion. Thus, in the recursive decomposition step (#3A) of the first level (i.e., the cascade section), the value of k takes the range from i+2 to i+j. To perform the recursive decomposition step (#3A), the first multi-control gate of a given set of intermediate segments is the k-th qubit (q) of the array register. k ) and the ki-1th ancila qubit of the ancila register (a k-i-1 ) is used as control, and the ki-th ancila qubit (a k-i It is applied using ) as the target.

[0080] The second CX gate in a given set of intermediate segments is applied to perform the inversion step (#5A). In the inversion step (#5A), the ki-th ancilla qubit (a) of the ancilla register is applied. k-i Using ) as a control, the k+1th qubit (q k+1 ) is inverted. As a result, the k-th qubit (q k Regarding ), between adjacent decrement target even substates, the size is 2 kThe amplitude blocks are swapped, and the k-th qubit (q k Regarding ), between adjacent incrementable odd substates, the size is 2 k The amplitude blocks are swapped. The second CX gate in a given set of intermediate segments performs the inversion step (#5A) by setting the ki-th ancila qubit (a) of the ancila register. k-i ) is used as control, and the k+1th qubit (q) of the array register is used. k+1 This is applied using ) as the target. This inversion step is performed using the corresponding value k for a given recursion. The value of k starts at i+j and is decremented by 1 after each recursion until it reaches i+1.

[0081] A second multi-control gate in a given set of intermediate segments is applied to perform the step (#7A) of reversing the decomposition step (#3A) by the recursive process described above. To perform the reconstruction step (#7A), a second two-control gate in a given set of intermediate segments is applied to the k-th qubit (q) of the array register. k ) and the ki-1th ancila qubit of the ancila register (a k-i-1 ) is used as control, and the ki-th ancila qubit (a k-i It is applied using ) as the target.

[0082] The third CX gate in a given set of intermediate segments is applied to perform the step (#6A) that reverses the aforementioned remapping step (#4A). In order to perform the step (#6A) that reverses the remapping step (#4A), the third CX gate in a given set of intermediate segments is applied to the superposition qubit (q) of the shift register. N+1 ) is used as control, and the k-th qubit (q) of the array register is used. k) is used as the target and applied. As mentioned above, the value of k is decremented by 1 after each recursion of step (#7A) until k reaches i+1. Thus, in the recursion of the first level (i.e., the cascade section), in the inversion step (#5A), the remapping inversion step (#6a), and the recursive decomposition inversion step (#7A), the value of k takes the range from i+j to i+2.

[0083] It should be noted that in the intermediate segment described above, one or more sets consisting of multiple CX gates and multiple multi-control gates are not arranged in order. These sets are arranged in a predetermined manner in order to properly execute recursion. For example, the (M+1)th set corresponding to the (M+1)th recursion is placed after the first multi-control gate of the corresponding (M)th set corresponding to the (M)th recursion in the first level of recursion. This will be explained in relation to Figure 2D below.

[0084] In the second level of recursion, another given set corresponding to another given recursion includes, in order, the following elements: • Superposition qubit (q) of a shift register N+1 ) is used as the control corresponding to state |1>, and the k-th qubit (q) of the array register is used. k The first CX gate targets ); • The k+1th qubit (q) of the array register k+1 ) is targeted, and the j-th ancilla qubit (a) of the ancilla register is targeted. j ), the i+j+1th qubit of the array register (q i+j+1 ), the k-th qubit of the array register (q k ), each l-th qubit (q) of the array register l A multi-control gate that uses control corresponding to the state |1> in ), where k > (i+j+1)+1 and l is an integer satisfying (i+j+1) < l < k; • Superposition qubit (q) of a shift register N+1) is used as the control corresponding to state |1>, and the k-th qubit (q) of the array register is used. k The second CX gate, targeting ).

[0085] The (P+1)th set corresponding to the (P+1)th recursion in the second level of recursion is added after the corresponding 1st CX gate of the Pth set corresponding to the Pth recursion.

[0086] Here, the first CX gate of the other given set of intermediate segments is applied to perform the remapping step (#4B) in the fused multi-control section. In the remapping step (#4B), the state amplitudes of the even substates to be further decremented and the state amplitudes of the odd substates to be further decremented are remapped. To perform the final remapping step (#4B), the first CX gate is applied to the superposition qubit (q) of the shift register. N+1 ) is used as control, and the k-th qubit (q) of the array register is used. k It is applied using ) as the target.

[0087] To perform the step (#6B) of reversing the aforementioned remapping step (#4B) in the fused multi-control section, the second CX gate of the other given set of intermediate segments is applied. To perform the step (#6B) of reversing the remapping step (#4B), the second CX gate of the other given set of intermediate segments is applied to the superposition qubit (q) of the shift register. N+1 ) is used as control, and the k-th qubit (q) of the array register is used. k It is applied using ) as the target.

[0088] In the fused multi-control section, the aforementioned recursive decomposition step (#3B), the aforementioned inversion step (#5B), and the aforementioned step for reversing the recursive decomposition process (#7B) are applied to the aforementioned set of multi-control gates in the intermediate segment. In other words, these steps are fused together and executed using the corresponding multi-control gates. In particular, in these steps in the recursion of the second level (i.e., the fused multi-control section), the value of k takes the range from i+j+1 to N-1.

[0089] Referring to Figure 2A-2C, a detailed diagram of a quantum circuit according to an embodiment of the present disclosure is shown. This quantum circuit is executed by a quantum computer or quantum simulator. This quantum circuit is 2 N+1 It includes a shift register and an ancilla register used to perform a multistep quantum ground state shift in a state vector space of size n. The shift register has N+1 qubits, and its first N qubits (q 1, q 2, ...q N ) forms an array register, and its last qubit (q N+1 ) are superposition qubits. An ancila register has j ancila qubits (a1, ... a j ) has . j is at most N-2. This quantum circuit comprises the following elements in order: • Start segment 202 has two CX gates 2021-2022; Depending on the embodiment, an intermediate segment 206 is provided, which has multiple CX gates 2061, 2063, 2065, 2066, 2068 and multiple multi-control gates 2062, 2064, 2067; • A terminal segment 204 having three CX gates 2041-2043 and one X gate 2044.

[0090] Step size 2 in multi-step quantum ground state shift i The quantum circuit is described below. Here, the step index i is a non-negative integer less than N.

[0091] In some embodiments, as shown in Figure 2A, when i < N-2 or i = N-2, the two CX gates 2021-2022 of the starting segment 202 are applied in the following order: • The (i+1)th qubit q of the array register i+1 Using the control corresponding to state |1>, the CX gate 2021 targets the first ancilla qubit a1 of the ancilla register; • Shift register superposition qubit q N+1 Using the control corresponding to state |1>, the CX gate 2022 targets the first ancilla qubit a1 of the ancilla register.

[0092] Depending on the embodiment, as shown in Figure 2A, when i < N-2 or i = N-2, the three CX gates 2041-2043 of the terminal segment 204 are applied in the following order: The first ancilla qubit a1 of the ancilla register is used as the control corresponding to state |1>, and the i+2th qubit q of the array register is used. i+2 CX gate 2041 targeting; • Shift register superposition qubit q N+1 Using the control corresponding to state |1>, CX gate 2042 targets the first ancilla qubit a1 of the ancilla register; • The (i+1)th qubit q of the array register i+1 Using the control corresponding to state |1>, CX gate 2043 targets the first ancilla qubit a1 of the ancilla register; Here, the (i+1)th qubit (q) of the array register i+1 X-gate 2044 is applied to ).

[0093] In some embodiments, when i < N-2, the intermediate segment 206 has one or more sets of multiple CX gates and multiple multi-control gates, where the number of sets in the intermediate segment 206 depends on the total number of recursions, including the recursions of the first level 206A corresponding to the cascade section and the recursions of the second level 206B corresponding to the fused multi-control section.

[0094] The first level 206A recursion continues until k reaches i+j from its initial value i+1. k is incremented by 1 with each recursion. The second level 206B recursion continues until k reaches N-1 from its initial value i+j. k is further incremented by 1 with each recursion.

[0095] Figure 2B shows, for illustrative purposes, a specific set corresponding to a particular recursion in the first level 206A. This particular set comprises the following elements in order: • Superposition qubit (q) of a shift register N+1 ) is used as the control corresponding to state |1>, and the k-th qubit (q) of the array register is used. k The first CX gate 2061 uses ) as its target; • The k-th qubit (q) of the array register k ) and the ki-1th ancila qubit of the ancila register (a k-i-1 ) is used as the control corresponding to state |1>, and the ki-th ancilla qubit (a k-i The first multi-control gate 2062 uses ) as its target; • The ki-th ancila qubit of the ancila register (a k-i ) is used as the control corresponding to state |1>, and the k+1th qubit (q) of the array register is used. k+1 The second CX gate 2063 uses ) as its target; • The k-th qubit (q) of the array register k ) and the ki-1th ancila qubit of the ancila register (a k-i-1) is used as the control corresponding to state |1>, and the ki-th ancilla qubit (a k-i The second multi-control gate 2064 uses ) as its target; • Superposition qubit (q) of a shift register N+1 ) is used as the control corresponding to state |1>, and the k-th qubit (q) of the array register is used. k The third CX gate, 2065, targets ).

[0096] As shown by the dashed line 208, in the intermediate segment 206, the (M+1)th set corresponding to the (M+1)th recursion is added after the first multi-control gate of the Mth set corresponding to the Mth recursion in the first level 206A recursion.

[0097] Figure 2C shows, for illustrative purposes, another specific set corresponding to another specific recursion in the second level 206B. The aforementioned other specific set comprises, in order, the following elements: • Superposition qubit (q) of a shift register N+1 ) is used as the control corresponding to state |1>, and the k-th qubit (q) of the array register is used. k The first CX gate 2066 targets ); • The k+1th qubit (q) of the array register k+1 ) is targeted, and the j-th ancilla qubit (a) of the ancilla register is targeted. j ), the i+j+1th qubit of the array register (q i+j+1 ), the k-th qubit of the array register (q k ), each l-th qubit (q) of the array register l A multi-control gate 2067 that uses control corresponding to the state |1> in ), where k > (i+j+1)+1 and l is an integer satisfying (i+j+1) < l < k; • Superposition qubit (q) of a shift register N+1 ) is used as the control corresponding to state |1>, and the k-th qubit (q) of the array register is used.k The second CX gate, 2068, targets ).

[0098] As shown by the dashed line 210, the (P+1)th set corresponding to the (P+1)th recursion in the second level 206B recursion is added after the corresponding 1st CX gate of the Pth set corresponding to the Pth recursion.

[0099] Figure 2D shows a detail diagram of an example quantum circuit according to an embodiment of the present disclosure for the case N = 5, i = 0, j = 2, for illustrative purposes only. This exemplary quantum circuit has a size of 2 N+1 = 2 6 = Used to perform multistep quantum ground state shifts in a state vector space of 64. The shift register has a total of 6 qubits, the first 5 qubits (q 1, q 2, q 3, q 4, q5) forms an array register, and its last qubit (q6) is a superposition qubit. The ancilla register has two ancilla qubits (a1, a2). The example quantum circuit comprises the following elements in order: • Start segment 202 has two CX gates; • Intermediate segment 206 having three sets, each containing multiple CX gates and multiple multi-control gates; • Termination segment 204 having three CX gates and one X gate.

[0100] As shown in Figure 2D, the two CX gates in the starting segment 202 are applied in the following order: A CX gate that uses the first qubit q1 of an array register as the control bit corresponding to the state |1> and the first anscira qubit a1 of an anscira register as the target; • A CX gate that uses the superposition qubit q6 of the shift register as a control corresponding to state |1> and targets the first anscira qubit a1 of the anscira register.

[0101] As shown in Figure 2D, the three CX gates of the terminal segment 204 are applied in the following order: • A CX gate that uses the first ancilla qubit a1 of the ancilla register as a control corresponding to state |1>, and targets the second qubit q2 of the array register; • A CX gate that uses the superposition qubit q6 of the shift register as the control corresponding to state |1> and targets the first ancilla qubit a1 of the ancilla register; A CX gate that uses the first qubit q1 of an array register as the control bit corresponding to the state |1> and the first anscira qubit a1 of an anscira register as the target.

[0102] Here, the X gate is applied to the first qubit q1 of the array register.

[0103] As shown in Figure 2D, the intermediate segment 206 has three sets, each containing multiple CX gates and multiple multi-control gates. As mentioned earlier, the total number of sets in the intermediate segment 206 depends on the total number of recursions. In the first level of recursion, the initial value of k is 1, and it is incremented by 1 with each recursion until it reaches 2. Therefore, in the intermediate segment 206, the first level of recursion occurs only once. In the second level of recursion, the value of k starts at 2 and is incremented by 1 with each recursion until it reaches 4. Therefore, in the intermediate segment 206, the second level of recursion occurs twice.

[0104] As shown in Figure 2D, one iteration set of the first level comprises the following elements in order: The first CX gate 2061 uses the superposition qubit q6 of the shift register as the control corresponding to state |1> and the second qubit q2 of the array register as the target; The first multi-control gate 2062 uses the second qubit q2 of the array register and the first ancilla qubit a1 of the ancilla register as control corresponding to state |1>, and the second ancilla qubit a2 of the ancilla register as the target; The second CX gate 2063 uses the second ancilla qubit a2 of the ancilla register as the control corresponding to state |1>, and the third qubit q3 of the array register as the target; The second multi-control gate 2064 uses the second qubit q2 of the array register and the first ancilla qubit a1 of the ancilla register as control corresponding to state |1>, and the second ancilla qubit a2 of the ancilla register as the target; • A third CX gate 2065 uses the superposition qubit q6 of the shift register as the control corresponding to state |1> and the second qubit q2 of the array register as the target.

[0105] In the intermediate segment 206, the first recursive set of the second level is appended after the first multi-control gate 2062 of the aforementioned iteration set of the first level. As shown in Figure 2D, the first recursive set of the second level comprises, in order: The first CX gate 2066a uses the superposition qubit q6 of the shift register as the control corresponding to state |1> and the third qubit q3 of the array register as the target; A multi-control gate 2067a that uses the third qubit q3 of the array register and the second ancilla qubit a2 of the ancilla register as control corresponding to state |1>, and the fourth qubit q4 of the array register as the target; A second CX gate 2068a uses the superposition qubit q6 of the shift register as the control corresponding to state |1> and the third qubit q3 of the array register as the target.

[0106] In the intermediate segment 206, a second recursive set of the second level is added after the first CX control gate 2066a of the first iteration set of the second level. As shown in Figure 2D, the second recursive set of the second level comprises the following elements in order: The first CX gate 2066b uses the superposition qubit q6 of the shift register as the control corresponding to state |1> and the fourth qubit q4 of the array register as the target; Multi-control gate 2067b uses the third qubit q3 of the array register, the fourth qubit q4 of the array register, and the second ancilla qubit a2 of the ancilla register as controls corresponding to state |1>, and uses the fifth qubit q5 of the array register as the target; • The second CX gate 2068b uses the superposition qubit q6 of the shift register as the control corresponding to state |1> and the fourth qubit q4 of the array register as the target.

[0107] In the example circuit in Figure 2D, the first step of controlled inverting (corresponding to the multi-controlled gate 2067b) is applied to the last qubit q5 of the array register. This is because this inverting step starts at k = N-1 = 4. Therefore, the step size of the first sub-state shift is 2 k = 2 4 = 16. Since the first step of controlled inversion is performed after all decomposition operations have been carried out, the first substate shift applies only to the last substate of the decomposition (i.e., the even and odd substates relating to the fourth qubit q4). Note that in the multi-controlled gate 2067b, i+j+1 = 3 and k = 4. Therefore, for an integer l satisfying (i+j+1) < l < k, the l-th qubit q l It does not exist.

[0108] Since the value of k becomes 3 after being decremented by one, the second step of the controlled inversion (which corresponds to the multi-controlled gate 2067a) is applied to the fourth qubit q4 of the array register. Thus, the step size of the second substate shift is 2 3 = 8. The second substate shift is applied only to the even and odd substates related to the third qubit q3. Note that in the multi-control gate 2067a, i+j+1 = 3 and k = 3. Therefore, the i+j+1th qubit q of the array register i+j+1 This is the k-th qubit q of the array register. k This is identical to the third qubit, q3.

[0109] The third step of the controlled inversion (corresponding to CX gate 2063) is applied to the third qubit q3. This is because the value of k is decremented by one more to 2. Thus, the step size of the third substate shift is 2. 2 = 4. The second substate shift applies only to the even and odd substates related to the second qubit q2.

[0110] Similarly, the fourth step of controlled inversion (corresponding to CX gate 2041) is applied to the second qubit q2, because the value of k is further decremented to 1. Thus, the step size of the fourth substate shift is 2 1 = 2. The fourth substate shift applies only to the even and odd substates related to the first qubit bit q1.

[0111] Finally, the last inversion step (corresponding to X gate 2044) is performed by applying an X gate to the first qubit, bit q1. This completes a multi-step quantum ground state shift of step size 1 for all states of the array register in this exemplary quantum circuit. In Figures 2A through 2D, each X gate applied to perform the inversion step is enclosed by a dashed line.

[0112] In Figure 2D, the step index i is set to 0 to illustrate multiple recursion using the simplest example of a quantum circuit where the entire shift register consists of only 6 qubits. Based on the generalized implementation of the quantum circuit shown in Figures 2A-2C, it is possible to construct larger and more complex quantum circuits.

[0113] Multistep quantum ground state shifts implemented using such quantum circuits can be used in a variety of quantum algorithms, including quantum random walks and other related quantum applications. Particularly advantageous is that multistep quantum ground state shifts can be implemented as a fundamental building block in discrete quantum random walks and can be adopted in multiple quantum algorithms. For example, multistep quantum ground state shifts are used to implement the propagation step in quantum algorithms such as the Quantum Lattice Boltzmann Method (QLBM) and Quantum Lattice Gas Automata (QLGA).

[0114] In this regard, the method may further include executing a quantum algorithm using a quantum circuit that performs multi-step quantum ground state shifts as a subroutine within the quantum algorithm. In the simplest implementation of the method, the quantum circuit is used to perform multi-step quantum ground state shifts in an orthogonal direction on a polygonal lattice. The quantum circuit can also be used to perform multi-step quantum ground state shifts in a non-orthogonal direction on a polygonal lattice. Such multi-step quantum ground state shifts on polygonal lattices are of interest in several quantum algorithms, such as lattice-based physics solvers used to simulate physical processes. QLBM and QLGA are examples of such lattice-based physics solvers. In particular, the simulation of physical processes frequently involves quantum random walks and related quantum applications. Therefore, the quantum circuit of this disclosure can be used to perform multi-step quantum ground state shifts as a subroutine within a quantum algorithm.

[0115] Quantum algorithms can be used in a variety of practical application fields, and quantum circuits offer a clear computational advantage in diverse application areas such as cryptography and cybersecurity, drug discovery and molecular modeling, materials science and engineering, financial modeling and risk analysis, machine learning and artificial intelligence, climate modeling and environmental analysis. In this regard, quantum algorithms are used to perform simulations of physical processes. Here, the method further includes providing the user with measurements obtained after the simulation of the physical process. The state variables measured depend on the quantum algorithm and the physical process being simulated. Multistep quantum ground state shifts achieve a significant quantum speedup because they can execute multiple shift directions simultaneously at a computational complexity class equivalent to that of single-step ground state shifts. This makes it possible to provide measurement results to the user very quickly. In particular, this allows for the execution of multiple simulations of physical processes with a high degree of parallelism. Due to parallelization, the overall depth of the quantum algorithm becomes shallower compared to quantum algorithms using single-step ground state shifts. Advantageously, such shallow quantum algorithms are simpler to operate and tend to accumulate less noise and error in measurements.

[0116] Next, we will explain how the multistep quantum ground state shift performed using the method described above compares to a quantum random walk and how it can be implemented as part of a quantum random walk. The multistep quantum ground state shift relates to a shift of all states in an array register, which can be called a full data array shift. A quantum random walk, on the other hand, is defined as a superposition of at least two full data array shifts, where the interpretation of the walk probability depends on how the superposition is achieved.

[0117] Figure 3 shows an example of a full data array shift, i.e., a combination of two multistep quantum ground state shifts, which can be interpreted as a positional pattern on a two-dimensional lattice. In this example, the combination of two multistep quantum ground state shifts all states of the array register two steps to the right and one step upward. All states of the array register cover the entire two-dimensional lattice, but for illustrative purposes, some of the ground states are marked as lattice points on the two-dimensional lattice. This can be interpreted as particles existing at those lattice points. A "combination of two multistep quantum ground state shifts" means moving all states on the two-dimensional lattice as shown in Figure 3. This can be interpreted as the movement of particles. Algorithmically, not only the non-trivial marked lattice points but the entire state vector space is moved within the lattice. In the context of performing this combination of two multistep quantum ground state shifts, this movement corresponds to a remapping of state amplitudes. For example, if the ground states are indexed, the increment operator moves the state amplitudes to the next ground state according to the index.

[0118] Multistep quantum ground state transitions can be extended to quantum random walks by defining a superposition of all data in the state vector space on a lattice (each representing a different probability). As an example, consider the case where two multistep quantum ground state transitions are combined with equal weights. This can be interpreted as a uniform probability of a particle moving in either direction. This is just a simple example, but superposition can become complex depending on the embodiment. For example, one particle might have a different probability of appearing anywhere on the lattice, and another particle might have a different probability of moving in exactly the correct direction.

[0119] For simplicity, this specification focuses only on uniform superpositions of various different motions in multistep quantum ground state shifts. The simplest example is uniform symmetric motion, in which case the superpositions are symmetrically paired. This can be interpreted as diffusive motion on a regular lattice. As mentioned earlier, quantum circuits of such uniform symmetric motion are highly efficient due to their inherent parallelizability. This parallelizable uniform symmetric motion is also called a "parallel symmetric shift".

[0120] Throughout this specification, the canonical basis state is assumed to be 0 and 1, and the corresponding tensor product basis state is the bit string q m q m-1 ...assuming q1. Here q j The qubits are ∈{0,1}, and the rightmost bit is the least significant bit. In quantum circuit diagrams, the least significant qubit is displayed at the top. A finite subset of N qubits is used for indexing. Here, it is assumed that the index starts from 1.

[0121] The ground state shift is a Fredholm operator on Hilbert space induced by the tensor product of qubits. In other words, the indexed set of ground states {e j} n j=1 In contrast, the increment operator can be expressed as follows: S+:e j →e j +1

[0122] Furthermore, the decrement operator can be expressed as follows: S-:e j →e j -1

[0123] In a multi-step quantum ground state shift, the sequence of state amplitudes, which are the coefficients of the ground state, is shifted. Therefore, a multi-step quantum ground state shift moves the state amplitudes forward or backward in the index sequence of the ground state.

[0124] TIFF2026104807000001.tif28170

[0125] Furthermore, we assume that the indexing of the ground states is isomorphic to the quotient group Z / nZ, where n is the dimension of the state vector space, and n = 2 N This makes the shift periodic, allowing it to be interpreted as amplitude propagation on a cyclic one-dimensional graph. Of particular note is that in a one-dimensional lattice, the parallel symmetric shift is performed as a bidirectional shift. This interpretation of the parallel symmetric shift can be easily extended to higher dimensions from the perspective of orthogonal lattices, as will be discussed later.

[0126] From this perspective, we consider interpretations of parallel symmetric shifts in r-dimensional lattices (i.e., r = 2 or 3). These interpretations are particularly important in the practical application of quantum circuits. As mentioned above, we assume that parallel symmetric shifts are periodic. However, such periodicity is assumed to be with respect to each spatial dimension, such that the indexing is isomorphic to (Z / nZ)r. Here, this product is the direct product of quotient groups. Also, n is the size of the state vector subspace corresponding to one of the spatial dimensions of the entire state vector space, i.e., the length of the lattice edges of the state vector subspace. For simplification, the interpretation is carried out assuming a square lattice (for r = 2) or a cubic lattice (for r = 3), and that n (i.e., the size of the state vector subspace) is a power of 2. Topologically, such lattices can be interpreted as discrete torus surfaces. Furthermore, the different directions along the different dimensions of these lattices are considered orthogonal simply to refer to the structure of these lattices. Note that the dimensions are irrelevant to the purposes of this specification, and rather the fact that the directions are somewhat independent of each other is important.

[0127] The parallel symmetric shift in the one-dimensional lattice described above can be applied to higher dimensions (i.e., two-dimensional or three-dimensional lattices) by additional arrangement of ground states. In this regard, depending on the embodiment, this method can be applied to at least one additional dimension with a size of 2 i This further includes performing at least one additional multistep quantum ground state shift having (i.e., a power of 2). In some embodiments, the multistep quantum ground state shift and at least one additional multistep quantum ground state shift are performed by sequentially stacking one-dimensional shifts for one dimension and at least one additional dimension, respectively. Such stacking of one-dimensional multistep quantum ground state shifts is performed by considering an array register (i.e., an indexed array of ground states) as corresponding to a stack of multiple one-dimensional data. This ensures the correct superposition of "direction substates". It will be seen that this step can be performed using the steps of the method for the multistep quantum ground state shift (i.e., parallel symmetric shifts for a one-dimensional lattice) described above. In the above, when r = 2, at least one additional dimension includes a single additional dimension, and at least one additional multistep quantum ground state shift includes a single additional multistep quantum ground state shift. Similarly, when r = 3, at least one additional dimension includes two additional dimensions, and at least one additional multistep quantum ground state shift includes two additional multistep quantum ground state shifts.

[0128] The technical advantage of this is that multi-step quantum ground state shifts and at least one additional multi-step quantum ground state shifts can be performed together in the same computational complexity class as a single-step ground state shift. This technical advantage stems from the parallelization of multiple shifts under a single operation. Parallelization makes the overall depth of the quantum circuit for multi-step quantum ground state shifts and at least one additional multi-step quantum ground state shift less than twice the overall depth of the quantum circuit for a single-step ground state shift. Furthermore, it allows for different step sizes at once for different array substates corresponding to different dimensions.

[0129] In an r-dimensional lattice (with dimension r), an array register has rN qubits. Furthermore, to consider simple orthogonal shifts in all dimensions, r superposition qubits are required. Therefore, a shift register must have r(N+1) qubits, with the first rN qubits forming the array register and the last r qubits being superposition qubits. The r superposition qubits enable superposition along all directions of the r-dimensional lattice.

[0130] In other embodiments, multistep quantum ground state shifts and at least one additional multistep quantum ground state shifts are performed by changing the qubit order of the corresponding substates in the multistep quantum ground state shift and at least one additional multistep quantum ground state shift using controlled swap blocks for one dimension and at least one additional dimension, respectively. In other words, only a single one-dimensional shift is performed in these controlled swap blocks. The technical advantage of using controlled swap blocks is that they not only guarantee the correct superposition of "direction substates" but are also efficient in larger lattices. Controlled swap gates increase the overall complexity of the quantum circuit compared to a single one-dimensional shift, but the overall complexity remains linear.

[0131] Figure 4 shows a detailed diagram of a quantum circuit that uses two controlled swap blocks to perform two multistep quantum ground state shifts in two dimensions, according to an embodiment of the present disclosure. The two multistep quantum ground state shifts enable a symmetrically equal shift in four directions on a two-dimensional regular lattice using two controlled swap blocks. Referring to Figure 4, the box labeled "Shift" represents the quantum circuit for performing the multistep quantum ground state shift (i.e., shown in Figures 2A-2C). The first of the two controlled swap blocks is applied before performing the multistep quantum ground state shift, and the second swap block is applied after the multistep quantum ground state shift has been performed.

[0132] Most importantly, the array register has 2N qubits (q 1, q 2, ...q 2N ) has. Here, the quantum circuit for multistep quantum ground state shift is the first half of the array register, i.e., the first N qubits (q) of the array register. 1, q 2, ...q N ) and is applied to the first superposition qubit (c1) of the superposition register. The superposition register has two superposition qubits (c1, c2). Here, the second superposition qubit (c2) is used to provide control over the two uncontrolled swap blocks. In such an implementation, the shift register is an array register (q 1, q 2, ...q 2N It consists of a single register and superposition registers (c1, c2).

[0133] As shown in Figure 4, the first controlled swap block and the second controlled swap block each contain N controlled swap gates. The N controlled swap gates of the first controlled swap block are arranged symmetrically with respect to the N controlled swap gates of the second controlled swap block. In the first controlled swap block, the N controlled swap gates comprise the following elements in order: • The first qubit q1 of the array register and the (N+1)th qubit q of the array register N+1 The first controlled swap gate is applied between the two states, using the second superposition qubit c2 of the superposition register as the control corresponding to state |1>; • The second qubit q2 of the array register and the (N+2)th qubit q of the array register N+2 The second controlled swap gate is applied between the two states, using the second superposition qubit c2 of the superposition register as the control corresponding to state |1>; The same applies to the following... • The Nth qubit q of the array register N and the 2Nth qubit q of the array register 2N The Nth uncontrolled swap gate is applied between the two states, using the second superposition qubit c2 of the superposition register as the control corresponding to state |1>.

[0134] In the second controlled swap block, the N controlled swap gates comprise the following elements in order: • The Nth qubit q of the array register N and the 2Nth qubit q of the array register 2N The first controlled swap gate is applied between the two states, using the second superposition qubit c2 of the superposition register as the control corresponding to state |1>; • The (N-1)th qubit N-1 of the array register and the 2N-1th qubit q of the array register 2N-1The second controlled swap gate is applied between the two states, using the second superposition qubit c2 of the superposition register as the control corresponding to state |1>; The same applies to the following... • The first qubit q1 of the array register and the (N+1)th qubit q of the array register N+1 The Nth uncontrolled swap gate is applied between the two states, using the second superposition qubit c2 of the superposition register as the control corresponding to state |1>. [Experimental Results]

[0135] In practical implementations of quantum circuits that perform multi-step quantum ground state shifts, it is important to understand the complexity of the quantum circuit in terms of the required gates and qubits. In this regard, gate complexity (i.e., the complexity of a quantum circuit based on the number of required gates) has been measured as the number of CX gates relative to the number of qubits. This is because CX gates (i.e., controlled 1-qubit X gates) are often considered fundamental gates and have the highest gate infidelity in today's actual quantum computers.

[0136] The quantum circuit disclosed herein has a step size of 2 i The number of gates is maximized when is 1, i.e., i = 0. To calculate the gate complexity of the quantum circuit, we consider several different implementations of the quantum circuit for N>1 and i = 0. Here, the size of the state vector space is i.e., 2 N As the number of elements increases, the size of the array registers also increases.

[0137] The number of ancilla qubits is at most Ni-2. However, various quantum circuits were compiled for various numbers of ancilla qubits. This was to identify the threshold at which the overall gate complexity of a multistep quantum ground state shift based on this disclosure (i.e., by a cascade + fusion approach) becomes lower than that of a quantum Fourier transform (QFT) based shift. This comparative analysis provided an objective criterion for the selection of the number of ancilla qubits by showing the point at which the number of CX gates shows a measurable decrease compared to a QFT-based shift by extending the cascade section.

[0138] Throughout this specification, QFT-based shift refers to the shift based on the quantum Fourier transform, as proposed by Shakeel in "Efficient and scalable quantum walk algorithms via the quantum fourier transform", Quantum Information Processing 19 (2020).

[0139] In the following table, "QFT" refers to a QFT-based shift, and "Parallel Variable Ancilla Register" refers to the multi-step quantum ground state shift of this disclosure.

[0140] The number of CX gates is calculated using ancilla decomposition and gate cancellation whenever possible. All-to-all connections between qubits are assumed.

[0141] The following table shows the bidirectional shift in a one-dimensional lattice, with the number of qubits (N) in the array register and the step size 2. i This indicates the gate complexity as measured by the number of CX gates. The number of qubits refers to the number of qubits used to encode the array register.

[0142] TIFF2026104807000002.tif58170

[0143] Figure 5 shows how the number of CX gates in various bidirectional shifts with step size 1 changes with respect to the number of qubits (N) used to encode the one-dimensional lattice. A shift based on a QFT (shown as QFT) is compared to two variations of the multi-step quantum ground state shift (shown as Parallel) of this disclosure. One of the two variations uses five ancilla qubits, and the other uses six ancilla qubits. This figure shows that adding just one ancilla qubit can make a difference long before reaching the full cascade limit.

Claims

1. A method performed by a quantum computer or quantum simulator, wherein the method is 2 N+1 Setting up a shift register and an ancilla register for a quantum circuit used to perform a multistep quantum ground state shift in a state vector space of size n, wherein the shift register has a total of N+1 qubits, and the first N qubits (q) of the shift register 1， q 2， ...q N ) forms an array register, and the last qubit (q) of the shift register N+1 ) is a superposition qubit, and the ancilla register can hold up to 2 ancilla qubits (a 1 , ...a N-i-2 ) including, however, step index i is a non-negative integer less than N, and the above setting is: 2 N+1 For an input state having N+1 sub-array states, the sub-array states in which the superposed qubit (q N+1 ) is 0 are regarded as the sub-array states to be incremented, and the sub-array states in which the superposed qubit (q N+1 ) is 1 are regarded as the sub-array states to be decremented, thereby dividing the input state into a first subset which is a subset including the sub-array states to be incremented and a second subset which is a subset including the sub-array states to be decremented; In the multi-step quantum ground state shift described above, the step size is 2 i In the case of i < N-2, the quantum circuit is set up accordingly; Setting up the quantum circuit, including, The k-th (k=i+1) qubit (q k Substates where ) is 0 are considered even substates, and the k-th qubit (q k By considering substates where ) is 1 as odd substates, the first subset is decomposed into even substates to be incremented and odd substates to be incremented, and the second subset is decomposed into even substates to be decremented and odd substates to be decremented; Remapping the state amplitude of the even substate to be decremented with the state amplitude of the odd substate to be decremented; The kth qubit (q k Substates where ) is 0 are considered even substates, and the k-th qubit (q k By considering a substate where ) is 1 as an odd substate, the incrementing odd substate is decomposed into a further incrementing even substate and a further incrementing odd substate by a recursive process in which k increases by 1 until it reaches i+j, and the decrementing even substate is decomposed into a further decrementing even substate and a further decrementing odd substate, where j is the number of ancilla qubits in the ancilla register; In each recursion, the state amplitude of the even substate to be further decremented is remapped to the state amplitude of the odd substate to be further decremented; The kth qubit (q k Substates where ) is 0 are considered even substates, and the k-th qubit (q k By considering a substate where ) is 1 as an odd substate, the recursive process in which k is further incremented by 1 in each recursion until k reaches N-1 decomposes the odd substate to be further incremented into an even substate to be further incremented and an odd substate to be further incremented, and the even substate to be further decremented into an even substate to be further decremented and an odd substate to be further decremented by the recursive process; In each recursion, the state amplitude of the even substate to be further decremented is remapped to the state amplitude of the odd substate to be further decremented; The kth qubit (q k With respect to the adjacent decrement target even substates, the size 2 k The amplitude block is swapped, and the k-th qubit (q k Regarding ), between adjacent incrementable odd substates, the size is 2 k To swap the amplitude block, the k+1th qubit (q k+1 The inversion of ) where k starts from N-1 and is decremented by 1 in each recursion until it reaches i+j; In each recursion, the remapping of the state amplitudes of the even substates targeted for further decrement and the state amplitudes of the odd substates targeted for further decrement is reversed; The recursive decomposition of the aforementioned odd substates subject to further increment and the aforementioned even substates subject to further decrement is reversed, wherein in each recursion, the decomposition by the recursive process, the inversion, and the reversal of the decomposition by the recursive process are performed by corresponding multi-control gates; The kth qubit (q k With respect to the adjacent decrement target even substates, the size 2 k The amplitude block is swapped, and the k-th qubit (q k Regarding ), between adjacent incrementable odd substates, the size is 2 k To swap the amplitude block, the k+1th qubit (q k+1 The inversion of ) where k starts from i+j and is further decremented by 1 in each recursion until it reaches i+1; Reversing the remapping of the state amplitudes of the even substates targeted for further decrement and the state amplitudes of the odd substates targeted for further decrement; The recursive decomposition of the odd substates to be incremented and the even substates to be decremented is reversed, wherein the reversal and the remapping are repeated prior to the reversal of each recursion of the decomposition by the recursive process; The k-th (where k=i+1) qubit (q k With respect to the adjacent decrement target even substates, the size 2 k The amplitude block is swapped, and the k-th qubit (q k Regarding ), between adjacent incrementable odd substates, the size is 2 k To swap the amplitude block, the first ancila qubit (a) of the ancila register 1 ) is used as a control to control the k+1th qubit (q k+1 ) and reversing it; Reversing the remapping of the state amplitudes of the even substates to be decremented and the state amplitudes of the odd substates to be decremented; Reversing the decomposition of the array substates of the first subset and the array subsets of the second subset; The aforementioned multi-step quantum ground state shift with a step size of 2 i To complete the multistep quantum ground state shift of the state amplitude based on, the i+1th qubit (q i+1 ) and reversing it; Tested by, method.

2. If i = N-1, the step size is 2 i To complete the multistep quantum ground state shift of the state amplitude based on, the i+1 qubit (q i+1 The method according to claim 1, comprising setting the quantum circuit by inverting ).

3. If i = N-2, The (i+1)th qubit (q) i+1 Substates where is 0 are considered even substates, and the (i+1)th qubit (q i+1 By considering substates where ) is 1 as odd substates, the first subset is decomposed into even substates to be incremented and odd substates to be incremented, and the second subset is decomposed into even substates to be decremented and odd substates to be decremented; Remapping the state amplitude of the even substate to be decremented with the state amplitude of the odd substate to be decremented; The (i+1)th qubit (q) i+1 With respect to the adjacent decrement target even substates, the size 2 i+1 The amplitude block is swapped, and the i+1th qubit (q i+1 Regarding ), between adjacent incrementable odd substates, the size is 2 i+1 To swap the amplitude block, the first ancila qubit (a) of the ancila register 1 ) is used as a control to control the i+2th qubit (q i+2 ) and reversing it; Reversing the step of remapping the state amplitude of the even substate to be decremented with the state amplitude of the odd substate to be decremented; Reversing the aforementioned disassembly step; The aforementioned step size 2 i To complete the multistep quantum ground state shift of the state amplitude based on, the i+1 qubit (q i+1 ) and reversing it; The method according to claim 1 or 2, comprising setting up the quantum circuit by means of the method.

4. The aforementioned quantum circuits, in order, A starting segment with two CX gates; Depending on the embodiment, an intermediate segment having a plurality of CX gates and a plurality of multi-control gates, each having two or more controls; A terminal segment having three CX gates and one X gate; The method according to claim 1 or 3, comprising:

5. The two CX gates of the aforementioned starting segment are - The i+1th qubit (q) of the array register i+1 ) is used as the control corresponding to state |1>, and the first ancilla qubit (a) of the ancilla register is used. 1 ) CX gate targeting; - The superposition qubit (q) of the shift register N+1 ) is used as the control corresponding to state |1>, and the first ancilla qubit (a) of the ancilla register is used. 1 ) CX gate targeting; The method according to claim 4, applied in the order of:

6. The three CX gates of the termination segment are - The first ancila qubit (a) of the ancila register 1 ) is used as the control corresponding to state |1>, and the i+2th qubit (q) of the array register is used. i+2 ) CX gate targeting; - The superposition qubit (q) of the shift register N+1 ) is used as the control corresponding to state |1>, and the first ancilla qubit (a) of the ancilla register is used. 1 ) CX gate targeting; - The i+1th qubit (q) of the array register i+1 ) is used as the control corresponding to state |1>, and the first ancilla qubit (a) of the ancilla register is used. 1 ) CX gate targeting; The order in which they are applied is such that the i+1th qubit (q) of the array register is applied. i+1 The method according to claim 5, wherein an X gate is applied to ).

7. The intermediate segment has one or more sets including multiple CX gates and multiple multi-control gates, and the number of sets of the intermediate segment depends on the number of recursions of the decomposition by the recursive process. The first level of recursion increments k by 1 with each recursion until k reaches i+j from its initial value i+1. The second level of recursion further increments k by 1 with each recursion until k reaches N-1 from its initial value i+j. In the first level of recursion, the given set corresponding to a given recursion is, in order, - The superposition qubit (q) of the shift register N+1 ) is used as the control corresponding to state |1>, and the k-th qubit (q) of the array register is used. k The first CX gate targets ); - The k-th qubit (q) of the array register k ) and the ki-1th ancilla qubit of the ancilla register (a k-i-1 ) is used as the control corresponding to state |1>, and the ki-th ancilla qubit (a k-i The first multi-control gate that uses ) as its target; - The ki-th ancila qubit (a k-i ) is used as the control corresponding to state |1>, and the k+1th qubit (q) of the array register is used. k+1 The second CX gate uses ) as its target; - The k-th qubit (q) of the array register k ) and the ki-1th ancilla qubit of the ancilla register (a k-i-1 ) is used as the control corresponding to state |1>, and the ki-th ancilla qubit (a k-i A second multi-control gate that uses ) as its target; - The superposition qubit (q) of the shift register N+1 ) is used as the control corresponding to state |1>, and the k-th qubit (q) of the array register is used. k The third CX gate targets ); The first level of recursion includes, where the M+1th set corresponding to the M+1th recursion is placed after the first multi-control gate of the Mth set corresponding to the Mth recursion, In the second level of recursion, the other given set corresponding to another given recursion is, in order, - The superposition qubit (q) of the shift register N+1 ) is used as the control corresponding to state |1>, and the k-th qubit (q) of the array register is used. k The first CX gate targets ); - The k+1th qubit (q) of the array register k+1 ) is targeted, and the j-th ancilla qubit (a) of the ancilla register is targeted. j ), the i+j+1th qubit (q) of the array register i+j+1 ), the k-th qubit (q) of the array register k ), each l-th qubit (q) of the array register l A multi-control gate that uses control corresponding to the state |1> in ), where k > (i+j+1)+1 and l is an integer satisfying (i+j+1) < l < k; - The superposition qubit (q) of the shift register N+1 ) is used as the control corresponding to state |1>, and the k-th qubit (q) of the array register is used. k The second CX gate targets ); The second level of recursion includes the following: the P+1-th set corresponding to the P+1-th recursion is added after the first CX gate of the P-th set corresponding to the P-th recursion. The method according to any one of claims 4 to 6.

8. Size 2 for at least one additional dimension i The method according to any one of claims 1 to 7, further comprising performing at least one additional multistep quantum ground state shift having

9. The method according to claim 8, wherein the multi-step quantum ground state shift and the at least one additional multi-step quantum ground state shift are performed by sequentially stacking one-dimensional shifts for one dimension and the at least one additional dimension, respectively.

10. The method according to claim 8, wherein the multi-step quantum ground state shift and the at least one additional multi-step quantum ground state shift are performed by changing the qubit order of the corresponding substates in the multi-step quantum ground state shift and the at least one additional multi-step quantum ground state shift using controlled swap blocks for each of the one dimension and the at least one additional dimension, respectively.

11. The method according to any one of claims 1 to 10, comprising executing the quantum algorithm using a quantum circuit that performs the multi-step quantum ground state shift as a subroutine within the quantum algorithm.

12. The method according to claim 11, wherein the quantum algorithm is performed to carry out a simulation of a physical process, and the method further comprises providing the user with measurements obtained after the simulation of the physical process.

13. A quantum computer or quantum simulator configured to perform the method described in any one of claims 1 to 12.

14. A quantum circuit executed by a quantum computer or quantum simulator, wherein the quantum circuit is 2 N+1 It includes a shift register and an ancilla register used to perform a multistep quantum ground state shift in a state vector space of size n, wherein the shift register contains N+1 qubits, and the first N qubits (q) of the shift register 1， q 2， ...q N ) forms an array register, and the last qubit (q) of the shift register N+1 ) is a superposition qubit, and the ancilla register has a maximum of Ni-2 ancilla qubits (a 1 , ...a N-i-2 ) including, however, the step index i is a non-negative integer less than N, and the quantum circuit is, in order, A starting segment with two CX gates; Depending on the embodiment, an intermediate segment having a plurality of CX gates and a plurality of multi-control gates, each having two or more controls; A terminal segment having three CX gates and one X gate; A quantum circuit equipped with these features.

15. In the multi-step quantum ground state shift described above, the step size is 2 i In the case of, If i < N-2 or i = N-2, the two CX gates of the starting segment are ・ Use the (i + 1)-th qubit (q i+1 ) of the array register as control corresponding to the state |1>, and a CX gate targeting the first ancilla qubit (a 1 ) of the ancilla register; - The superposition qubit (q) of the shift register N+1 ) is used as the control corresponding to state |1>, and the first ancilla qubit (a) of the ancilla register is used. 1 ) CX gate targeting; The quantum circuit according to claim 14, applied in the order of:

16. In the multi-step quantum ground state shift described above, the step size is 2 i In the case of, If i < N-2 or i = N-2, the three CX gates of the terminal segment are: - The first ancila qubit (a) of the ancila register 1 ) is used as the control corresponding to state |1>, and the i+2th qubit (q) of the array register is used. i+2 ) CX gate targeting; ・ Use the superposed quantum bit (q N+1 ) of the shift register as control corresponding to the state |1> and apply a CX gate targeting the first ancilla quantum bit (a 1 ) of the ancilla register; - The i+1th qubit (q) of the array register i+1 ) is used as the control corresponding to state |1>, and the first ancilla qubit (a) of the ancilla register is used. 1 ) CX gate targeting; The order in which they are applied is such that the i+1th qubit (q) of the array register is applied. i+1 The quantum circuit according to claim 14 or 15, wherein an X gate is applied to ).

17. In the multi-step quantum ground state shift described above, the step size is 2 i In the case of, When i < N-2, the intermediate segment has one or more sets consisting of multiple CX gates and multiple multi-control gates, and the number of sets of the intermediate segment depends on the number of recursions in the decomposition by the recursive process. The first level of recursion increments k by 1 with each recursion until k reaches i+j from its initial value i+1. The second level of recursion further increments k by 1 with each recursion until k reaches N-1 from its initial value i+j. In the first level of recursion, the given set corresponding to a given recursion is, in order, - The superposition qubit (q) of the shift register N+1 ) is used as the control corresponding to state |1>, and the k-th qubit (q) of the array register is used. k The first CX gate targets ); - The k-th qubit (q) of the array register k ) and the ki-1th ancilla qubit of the ancilla register (a k-i-1 ) is used as the control corresponding to state |1>, and the ki-th ancilla qubit (a k-i The first multi-control gate that uses ) as its target; - The ki-th ancila qubit (a k-i ) is used as the control corresponding to state |1>, and the k+1th qubit (q) of the array register is used. k+1 The second CX gate uses ) as its target; - The k-th qubit (q) of the array register k ) and the ki-1th ancilla qubit of the ancilla register (a k-i-1 ) is used as the control corresponding to state |1>, and the ki-th ancilla qubit (a k-i A second multi-control gate that uses ) as its target; - The superposition qubit (q) of the shift register N+1 ) is used as the control corresponding to state |1>, and the k-th qubit (q) of the array register is used. k The third CX gate targets ); The first level of recursion includes, where the M+1th set corresponding to the M+1th recursion is placed after the first multi-control gate of the Mth set corresponding to the Mth recursion, In the second level of recursion, the other given set corresponding to another given recursion is, in order, - The superposition qubit (q) of the shift register N+1 ) is used as the control corresponding to state |1>, and the k-th qubit (q) of the array register is used. k The first CX gate targets ); - The k+1th qubit (q) of the array register k+1 ) is targeted, and the j-th ancilla qubit (a) of the ancilla register is targeted. j ), the i+j+1th qubit (q) of the array register i+j+1 ), the k-th qubit (q) of the array register k ), each l-th qubit (q) of the array register l A multi-control gate that uses control corresponding to the state |1> in ), where k > (i+j+1)+1 and l is an integer satisfying (i+j+1) < l < k; - The superposition qubit (q) of the shift register N+1 ) is used as the control corresponding to state |1>, and the k-th qubit (q) of the array register is used. k The second CX gate targets ); The quantum circuit according to any one of claims 14 to 16, wherein in the second level of recursion, the (P+1)th set corresponding to the (P+1)th recursion is added after the first CX gate of the (P)th set corresponding to the (P)th recursion.

Images