Semiconductor equipment

Abstract

We propose a technique to improve the trade-off between on-resistance and voltage rating. [Solution] The semiconductor device 10 has a plurality of p-type deep layers 36, a plurality of n-type deep layers 37, an n-type drift layer 38, and an n-type high-concentration layer 39. The n-type high-concentration layer is in contact with at least a portion of the lower surface of the corresponding p-type deep layer among the plurality of p-type deep layers, and has a higher concentration of n-type impurities than the drift layer.

Description

Cross-reference to Related Applications

[0001] This application is a related application of Japanese Patent Application No. 2022-066834 filed on April 14, 2022, claims priority based on this Japanese patent application, and incorporates all the content described in this Japanese patent application as part of this specification.

Technical Field

[0002] The technology disclosed in this specification relates to a semiconductor device and a method for manufacturing the same.

[0003] Japanese Patent Application Laid-Open No. 2003-309261 and Japanese Patent Application Laid-Open No. 2017-152488 disclose a semiconductor device in which p-type layers and n-type layers are alternately and repeatedly arranged in the plane direction of a semiconductor substrate. When this semiconductor device is turned off, a plurality of p-type layers and a plurality of n-type layers are depleted, and the voltage between the source and the drain is held.

Summary of the Invention

[0004] In such a semiconductor device having a plurality of p-type layers and a plurality of n-type layers, there is a trade-off relationship between the on-resistance and the breakdown voltage. This specification proposes a technique for improving the trade-off existing between the on-resistance and the breakdown voltage.

[0005] A semiconductor device disclosed herein may include a semiconductor substrate having a trench on its upper surface, a gate insulating film covering the inner surface of the trench, and a gate electrode disposed within the trench and insulated from the semiconductor substrate by the gate insulating film. The semiconductor substrate may include an n-type source layer in contact with the gate insulating film on the side surface of the trench, a p-type body layer located below the source layer and in contact with the gate insulating film on the side surface of the trench, a plurality of p-type deep layers, each extending from the body layer to below the bottom surface of the trench, and when viewed from above, extending along a first direction and spaced apart from each other in a second direction perpendicular to the first direction, and a plurality of n-type deep layers, each adjacent to The material may include: a plurality of n-type deep layers, arranged at corresponding intervals among a plurality of intervals defined between the p-type deep layers, and in contact with the gate insulating film on the side surface of the trench located below the body layer; an n-type drift layer, arranged below the plurality of p-type deep layers and the plurality of n-type deep layers, and in contact with the plurality of n-type deep layers; and an n-type high-concentration layer, in contact with at least a portion of the lower surface of a corresponding p-type deep layer among the plurality of p-type deep layers, and having a higher concentration of n-type impurities than the drift layer.

[0006] In the above semiconductor device, the n-type high-density layer is provided so as to be in contact with at least a portion of the lower surface of the p-type deep layer, thereby suppressing the expansion of the depletion layer from the p-type deep layer toward the drift layer when the device is turned on. As a result, the current path is wide in the above semiconductor device, and it is possible to have the characteristic of low on-resistance. Furthermore, the n-type high-density layer is provided so as to be in contact with the lower surface of the p-type deep layer. As a result, the decrease in breakdown voltage is also suppressed in the above semiconductor device. The above semiconductor device can achieve both low on-resistance and high breakdown voltage.

[0007] A method for manufacturing a semiconductor device disclosed herein includes a deep layer formation step of forming a plurality of p-type deep layers and a plurality of n-type deep layers on an n-type epitaxial layer, wherein each of the plurality of p-type deep layers extends along a first direction when the epitaxial layer is viewed from above and is spaced apart from each other in a second direction perpendicular to the first direction, and each of the plurality of n-type deep layers is positioned at a corresponding interval among a plurality of intervals defined between adjacent p-type deep layers; and an n-type high-concentration layer formation step of forming an n-type high-concentration layer that is in contact with at least a portion of the lower surface of a corresponding p-type deep layer among the plurality of p-type deep layers and has a higher concentration of n-type impurities than the epitaxial layer. The chronological order of the deep layer formation step and the n-type high-concentration layer formation step is not particularly limited.

[0008] This semiconductor device manufacturing method makes it possible to manufacture semiconductor devices that achieve both low on-resistance and high voltage resistance. [Brief explanation of the drawing]

[0009] [Figure 1] A cross-sectional perspective view of the semiconductor device 10 (showing the xz cross-section excluding the p-type deep layer 36). [Figure 2] A cross-sectional perspective view of the semiconductor device 10 with the source electrode 22 and interlayer insulating film 20 omitted (showing the xz cross-section without the p-type deep layer 36). [Figure 3] An enlarged xy cross-section including a p-type trench lower layer 35, a p-type deep layer 36, and an n-type deep layer 37, showing the arrangement of the p-type trench lower layer 35, the p-type deep layer 36, and the n-type deep layer 37 when the semiconductor substrate 12 is viewed from above. [Figure 4] An enlarged xy cross-section including a trench 14, a p-type deep layer 36, and an n-type deep layer 37, showing the arrangement of the trench 14, the p-type deep layer 36, and the n-type deep layer 37 when the semiconductor substrate 12 is viewed from above. [Figure 5]A cross-sectional perspective view of the semiconductor device 10 (showing the xz cross-section including the p-type deep layer 36). [Figure 6] Enlarged yz cross-sectional view of a modified semiconductor device 10 including a p-type deep layer 36, an n-type deep layer 37, and an n-type high-density layer. [Figure 7] Enlarged yz cross-sectional view of a modified semiconductor device 10 including a p-type deep layer 36, an n-type deep layer 37, and an n-type high-density layer. [Figure 8] Enlarged yz cross-sectional view of a modified semiconductor device 10 including a p-type deep layer 36, an n-type deep layer 37, and an n-type high-density layer. [Figure 9] Diagram illustrating the manufacturing method of the semiconductor device 10. [Figure 10] Diagram illustrating the manufacturing method of the semiconductor device 10. [Figure 11] Diagram illustrating the manufacturing method of the semiconductor device 10. [Figure 12] Diagram illustrating the manufacturing method of the semiconductor device 10. [Figure 13] Diagram illustrating the manufacturing method of the semiconductor device 10. [Figure 14] Diagram illustrating the manufacturing method of the semiconductor device 10. [Figure 15] Diagram illustrating the manufacturing method of the semiconductor device 10. [Figure 16] Diagram illustrating the manufacturing method of the semiconductor device 10. [Modes for carrying out the invention]

[0010] The embodiments will be described below with reference to the drawings. For the purpose of clarity in the illustration, only some of the components that are repeatedly arranged are given reference numerals.

[0011] The semiconductor device 10 shown in Figures 1 to 5 is a type of power device called a MOSFET (metal-oxide-semiconductor field effect transistor) and has a semiconductor substrate 12. Hereinafter, the thickness direction of the semiconductor substrate 12 will be referred to as the z direction, one direction parallel to the upper surface 12a of the semiconductor substrate 12 (one direction perpendicular to the z direction) will be referred to as the x direction, and the direction perpendicular to both the x and z directions will be referred to as the y direction. The semiconductor substrate 12 is made of silicon carbide (SiC). However, the semiconductor substrate 12 may be made of other semiconductor materials such as silicon or gallium nitride. Multiple trenches 14 are provided on the upper surface 12a of the semiconductor substrate 12. As shown in Figure 2, the multiple trenches 14 extend long along the y direction on the upper surface 12a. The multiple trenches 14 are spaced apart in the x direction.

[0012] As shown in Figures 1, 2, and 5, the inner surface (i.e., the sides and bottom) of each trench 14 is covered with a gate insulating film 16. A gate electrode 18 is placed inside each trench 14. Each gate electrode 18 is insulated from the semiconductor substrate 12 by the gate insulating film 16. As shown in Figures 1 and 5, the upper surface of each gate electrode 18 is covered with an interlayer insulating film 20. A source electrode 22 is provided on the upper part of the semiconductor substrate 12. The source electrode 22 covers each interlayer insulating film 20. The source electrode 22 is insulated from the gate electrode 18 by the interlayer insulating film 20. The source electrode 22 is in contact with the upper surface 12a of the semiconductor substrate 12 where the interlayer insulating film 20 is not present. A drain electrode 24 is provided on the lower part of the semiconductor substrate 12. The drain electrode 24 is in contact with the entire lower surface 12b of the semiconductor substrate 12.

[0013] As shown in Figures 1, 2, and 5, the semiconductor substrate 12 has a plurality of source layers 30, a plurality of contact layers 32, a body layer 34, a plurality of p-type trench underlayers 35, a plurality of p-type deep layers 36, a plurality of n-type deep layers 37, a drift layer 38, a plurality of n-type high-concentration layers 39, and a drain layer 40.

[0014] Each source layer 30 is an n-type layer with a high concentration of n-type impurities. Each source layer 30 is disposed in a range that partially includes the upper surface 12a of the semiconductor substrate 12. Each source layer 30 makes an ohmic contact with the source electrode 22. Each source layer 30 contacts the gate insulating film 16 at the uppermost part of the side surface of the trench 14. Each source layer 30 faces the gate electrode 18 through the gate insulating film 16. Each source layer 30 extends long in the y direction along the side surface of the trench 14. That is, when looking at the semiconductor substrate 12 from above, each source layer 30 extends parallel to the longitudinal direction of the trench 14 and extends from one end to the other end in the longitudinal direction of the trench 14.

[0015] Each contact layer 32 is a p-type layer with a high concentration of p-type impurities. Each contact layer 32 is disposed in a range that partially includes the upper surface 12a of the semiconductor substrate 12. Each contact layer 32 is disposed between two corresponding source layers 30. Each contact layer 32 makes an ohmic contact with the source electrode 22. Each contact layer 32 extends long in the y direction. That is, when looking at the semiconductor substrate 12 from above, each contact layer 32 extends parallel to the longitudinal direction of the trench 14 and extends from one end to the other end in the longitudinal direction of the trench 14.

[0016] The body layer 34 is a p-type layer with a lower concentration of p-type impurities than the contact layer 32. The body layer 34 is disposed below the plurality of source layers 30 and the plurality of contact layers 32. The body layer 34 contacts the plurality of source layers 30 and the plurality of contact layers 32 from below. The body layer 34 contacts the gate insulating film 16 at the side surface of the trench 14 located below the source layer 30. The body layer 34 faces the gate electrode 18 through the gate insulating film 16.

[0017] Each p-type trench lower layer 35 is a p-type layer disposed below the corresponding trench 14. As will be described later, each p-type trench lower layer 35 may be formed in an ion implantation process common to the body layer 34. In this case, the depth-direction concentration profiles of the p-type impurities in each p-type trench lower layer 35 and the body layer 34 coincide, and the depth from the bottom surface of the corresponding trench 14 to the lower surface of each p-type trench lower layer 35 coincides with the depth from the upper surface 12a of the semiconductor substrate 12 to the lower surface of the body layer 34. In this example, each p-type trench lower layer 35 is in contact with the gate insulating film 16 covering the bottom surface of the corresponding trench 14. As shown in FIG. 3, when the semiconductor substrate 12 is viewed from above, each p-type trench lower layer 35 extends long along the longitudinal direction of the corresponding trench 14 (in the y direction in this example), and extends continuously from one end to the other end in the longitudinal direction of the trench 14.

[0018] Each p-type deep layer 36 is a p-type layer protruding downward from the lower surface of the body layer 34. The concentration of p-type impurities in each p-type deep layer 36 is higher than the concentration of p-type impurities in the body layer 34 and lower than the concentration of p-type impurities in the contact layer 32. As shown in FIG. 4, when the semiconductor substrate 12 is viewed from above, each p-type deep layer 36 extends long in the x direction and is orthogonal to the longitudinal direction of the trench 14 (in the y direction in this example). Each p-type deep layer 36 is arranged at intervals in the y direction. The p-type deep layer 36 has a shape that is long in the z direction in the yz cross section. That is, the dimension of the p-type deep layer 36 in the z direction (i.e., the height of the p-type deep layer 36) is larger than the dimension of the p-type deep layer 36 in the y direction (i.e., the lateral width of the p-type deep layer 36). Each p-type deep layer 36 extends from the lower surface of the body layer 34 to a depth lower than the bottom surface of each trench 14. Each p-type deep layer 36 is in contact with the gate insulating film 16 on the side surface of the trench 14 located below the body layer 34. Also, as shown in FIG. 3, each p-type deep layer 36 is in contact with the p-type trench lower layer 35 disposed below the trench 14 so as to intersect.

[0019] Each n-type deep layer 37 is an n-type layer that protrudes downward from the lower surface of the body layer 34. The concentration of n-type impurities in each n-type deep layer 37 is higher than the concentration of n-type impurities in the drift layer 38. The concentration of n-type impurities in each n-type deep layer 37 is lower than the concentration of p-type impurities in each p-type deep layer 36. Alternatively, each n-type deep layer 37 may have the same concentration of n-type impurities as the drift layer 38. As shown in Figures 1, 2, and 5, each n-type deep layer 37 is positioned at a corresponding interval among a plurality of intervals defined by adjacent p-type deep layers 36. As shown in Figure 4, when the semiconductor substrate 12 is viewed from above, each n-type deep layer 37 extends long in the x-direction and is perpendicular to the longitudinal direction of the trench 14 (y-direction in this example). Each n-type deep layer 37 is in contact with the sides of the p-type deep layers 36 on both sides. In the yz cross-section, the n-type deep layer 37 has a shape that is long in the z-direction. That is, the dimension of the n-type deep layer 37 in the z direction (i.e., the height of the n-type deep layer 37) is greater than the dimension of the n-type deep layer 37 in the y direction (i.e., the width of the n-type deep layer 37). In this embodiment, the height of the n-type deep layer 37 is equal to the height of the p-type deep layer 36. In this specification, considering the variability of the ion implantation process, if the difference in height between the n-type deep layer 37 and the p-type deep layer 36 is within 3%, then the heights of the n-type deep layer 37 and the p-type deep layer 36 are considered to be the same. The width of the n-type deep layer 37 is approximately equal to the width of the p-type deep layer 36. As shown in Figures 1, 2, and 5, each n-type deep layer 37 extends from the lower surface of the body layer 34 to below the bottom surface of each trench 14. Each n-type deep layer 37 is in contact with the gate insulating film 16 on the side surface of the trench 14 located below the body layer 34. Furthermore, as shown in Figure 3, each n-type deep layer 37 is in contact with the p-type trench lower layer 35 located below the trench 14, intersecting it.

[0020] The drift layer 38 is an n-type layer located beneath multiple p-type deep layers 36 and multiple n-type deep layers 37. The concentration of n-type impurities in the drift layer 38 is lower than the concentration of n-type impurities in the n-type deep layers 37. The drift layer 38 is in contact with the n-type deep layers 37 from below.

[0021] Each n-type high-concentration layer 39 is an n-type layer that is in contact with the entire lower surface of the corresponding p-type deep layer 36. The concentration of n-type impurities in each n-type high-concentration layer 39 is higher than the concentration of n-type impurities in the drift layer 38. The concentration of n-type impurities in each n-type high-concentration layer 39 may be lower than the concentration of n-type impurities in the n-type deep layer 37. Each n-type high-concentration layer 39 is positioned between the drift layer 38 and the p-type deep layer 36, separating the drift layer 38 and the p-type deep layer 36. Each n-type high-concentration layer 39 is partially provided so as to be in contact with the lower surface of the p-type deep layer 36, and is not provided so as to cover at least a portion of the lower surface of the n-type deep layer 37. In other words, each n-type high-concentration layer 39 does not extend continuously between adjacent p-type deep layers 36, but is divided on the underside of the n-type deep layer 37. Therefore, the n-type deep layer 37 and the drift layer 38 are in contact in the region between adjacent n-type high-density layers 39. When the semiconductor substrate 12 is viewed from above, each n-type high-density layer 39 extends along the longitudinal direction (y-direction in this example) of the corresponding p-type deep layer 36, and extends continuously from one end to the other in the longitudinal direction of the p-type deep layer 36. Also, as shown in Figure 5, each n-type high-density layer 39 is in contact with the lower surface of the p-type trench lower layer 35 that intersects with the corresponding p-type deep layer 36, and is positioned between the drift layer 38 and the p-type trench lower layer 35. Note that adjacent n-type high-density layers 39 may be connected on the underside of the p-type trench lower layer 35. In this example, the n-type high-density layer 39 extends in the y-direction along the lower surface of the p-type trench lower layer 35 and may be formed to separate the drift layer 38 and the p-type trench lower layer 35.

[0022] The drain layer 40 is an n-type layer with a higher concentration of n-type impurities than the drift layer 38 and the n-type deep layer 37. The drain layer 40 is in contact with the drift layer 38 from below. The drain layer 40 is located in an area that includes the lower surface 12b of the semiconductor substrate 12. The drain layer 40 is in ohmic contact with the drain electrode 24.

[0023] Next, the operation of the semiconductor device 10 will be described. The semiconductor device 10 is used with a higher potential applied to the drain electrode 24 than to the source electrode 22. When a potential above the gate threshold is applied to each gate electrode 18, a channel is formed in the body layer 34 near the gate insulating film 16. The channel connects the source layer 30 and the n-type deep layer 37. As a result, electrons flow from the source layer 30 to the drain layer 40 via the channel, the n-type deep layer 37, and the drift layer 38. In other words, the semiconductor device 10 is turned on. When the potential of each gate electrode 18 is lowered from a value above the gate threshold to a value below the gate threshold, the channel disappears and the flow of electrons stops. In other words, the semiconductor device 10 is turned off.

[0024] If the n-type high-density layer 39 is not provided, when the semiconductor device 10 is turned on, a depletion layer spreads from the p-type deep layer 36 toward the drift layer 38. In particular, if the depletion layer spreads toward the drift layer 38 beneath the n-type deep layer 37, there is a concern that the current path will narrow and the on-resistance will increase. This increase in on-resistance is called the JFET effect. On the other hand, in the semiconductor device 10, since the n-type high-density layer 39 is provided so as to be in contact with the lower surface of the p-type deep layer 36, the spreading of the depletion layer toward the drift layer 38 from the p-type deep layer 36 is suppressed. As a result, a wide current conduction path is secured, and the semiconductor device 10 can have the characteristic of low on-resistance. Note that the thickness of the n-type high-density layer 39 may be greater than the thickness of the depletion layer generated by the built-in potential at the pn junction between the p-type deep layer 36 and the n-type high-density layer 39. The JFET effect can be suppressed effectively. Furthermore, the n-type high-density layer 39 is partially provided on the underside of the p-type deep layer 36, but not on at least a portion of the underside of the n-type deep layer 37, and is not formed continuously in the plane direction of the semiconductor substrate 12. In this way, because the n-type high-density layer 39 is partially provided, the decrease in the breakdown voltage of the semiconductor device 10 is suppressed. The semiconductor device 10 can achieve both low on-resistance and high breakdown voltage.

[0025] In the modified example shown in Figure 6, the n-type high-concentration layer 39 is selectively positioned at both ends in the width direction of the lower surface of the corresponding p-type deep layer 36, and does not contact the entire lower surface of the p-type deep layer 36. Even in this modified example, when the semiconductor device 10 is turned on, it is possible to suppress the depletion layer from spreading from the p-type deep layer 36 toward the drift layer 38 beneath the n-type deep layer 37. Furthermore, since a portion of the p-type deep layer 36 is in contact with the drift layer 38, when the semiconductor device 10 is turned off, the depletion layer spreads well from the p-type deep layer 36 toward the drift layer 38. For this reason, the breakdown voltage can be improved in this modified example.

[0026] In the modified example shown in Figure 7, the width of the n-type high-density layer 39 is greater than the width of the corresponding p-type deep layer 36. As a result, the n-type high-density layer 39 is in contact with the entire lower surface of the corresponding p-type deep layer 36, as well as with the n-type deep layer 37 adjacent to the corresponding p-type deep layer 36. In this example, when the semiconductor device 10 is turned on, the expansion of the depletion layer from the p-type deep layer 36 toward the drift layer 38 can be effectively suppressed.

[0027] In the modified example shown in Figure 8, the p-type deep layer 36 extends below the n-type deep layer 37. The n-type high-density layer 39 is in contact with the entire lower surface of the p-type deep layer 36, as well as with the side surface of the p-type deep layer 36 that is below the n-type deep layer 37. When the p-type deep layer 36 extends below the n-type deep layer 37, the breakdown voltage of the semiconductor device 10 is improved. Furthermore, since the n-type high-density layer 39 is also arranged on the side surface of the p-type deep layer 36, even when the p-type deep layer 36 extends below the n-type deep layer 37, it is possible to suppress the spread of the depletion layer from the p-type deep layer 36 towards the drift layer 38 below the n-type deep layer 37 when the semiconductor device 10 is turned on. In this modified example, the trade-off between on-resistance and breakdown voltage can be further improved. Note that, even in this modified example, as shown in Figure 6, the n-type high-density layer 39 may not be provided on a part of the lower surface of the p-type deep layer 36, and the p-type deep layer 36 and the drift layer 38 may be formed to be in contact.

[0028] Next, the manufacturing method of the semiconductor device 10 will be described. The semiconductor device 10 is manufactured from a semiconductor substrate composed entirely of a drain layer 40. First, as shown in Figure 9, an n-type epitaxial layer 50 is formed on the drain layer 40 using epitaxial growth technology.

[0029] Next, as shown in Figure 10, an n-type layer 60 is formed by introducing n-type impurities to a predetermined depth range away from the surface of the epitaxial layer 50 using ion implantation technology. A portion of the epitaxial layer 50 below the n-type layer 60 becomes the drift layer 38.

[0030] Next, as shown in Figure 11, a mask 52 having an opening is patterned on the epitaxial layer 50.

[0031] Next, as shown in Figure 12, ion implantation technology is used to introduce n-type impurities into the upper part of the drift layer 38 through the opening of the mask 52, forming a high-concentration n-type layer 39.

[0032] Next, as shown in Figure 13, ion implantation technology is used to introduce p-type impurities into a portion of the n-type layer 60 through the opening in the mask 52, thereby forming multiple p-type deep layers 36. The portion of the n-type layer 60 that did not form multiple p-type deep layers 36 becomes multiple n-type deep layers 37. In this specification, the process of forming multiple p-type deep layers 36 and multiple n-type deep layers 37, as illustrated in Figures 10 to 13, is an example of a deep layer formation process. After forming the multiple p-type deep layers 36, the mask 52 is removed.

[0033] In this example, the mask 52 serves as both an ion implantation mask for forming the n-type high-concentration layer 39 and an ion implantation mask for forming the p-type deep layer 36. This reduces the number of steps and lowers manufacturing costs. The n-type high-concentration layer 39 may be formed after the p-type deep layer 36. Furthermore, when forming the n-type high-concentration layer 39, the modified n-type high-concentration layer 39 shown in Figure 6 can be formed by oblique ion implantation from a predetermined angle to the upper surface of the epitaxial layer 50. Alternatively, without using the same mask 52, the modified n-type high-concentration layer 39 can be formed by making the opening width of the ion implantation mask for forming the n-type high-concentration layer 39 larger than the opening width of the ion implantation mask for forming the p-type deep layer 36, as shown in Figure 7.

[0034] Next, as shown in Figure 14, the source layer 30 and contact layer 32 are formed by introducing n-type and p-type impurities into the surface layer of the epitaxial layer 50 using ion implantation technology.

[0035] Next, as shown in Figure 15, trenches 14 are formed using etching techniques, extending from the surface of the epitaxial layer 50 to the n-type deep layer 37 and the p-type deep layer 36. The depth of the trenches 14 is adjusted so as not to exceed the depth of the n-type deep layer 37 and the p-type deep layer 36. When the epitaxial layer 50 is viewed from above, the trenches 14 intersect with multiple p-type deep layers 36 and multiple n-type deep layers 37.

[0036] Next, as shown in Figure 16, a body layer 34 and a p-type trench lower layer 35 are formed by introducing p-type impurities in multiple stages toward the surface of the epitaxial layer 50 using ion implantation technology. The body layer 34 is formed above the n-type deep layer 37 and the p-type deep layer 36, and below the source layer 30 and the contact layer 32. The p-type trench lower layer 35 is formed below the bottom surface of the trench 14.

[0037] Subsequently, the semiconductor device 10 is completed by forming the trench 14, gate insulating film 16, gate electrode 18, interlayer insulating film 20, source electrode 22, and drain electrode 24.

[0038] Although embodiments have been described in detail above, these are merely illustrative and do not limit the scope of the claims. The technologies described in the claims include various modifications and changes to the specific examples illustrated above. The technical elements described in this specification or drawings exhibit technical usefulness individually or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technologies illustrated in this specification or drawings achieve multiple objectives simultaneously, and achieving even one of these objectives constitutes technical usefulness.

Claims

1. Semiconductor device (10), A semiconductor substrate (12) having a trench (14) on its upper surface, A gate insulating film (16) covering the inner surface of the trench, The system comprises a gate electrode (18) disposed within the trench and insulated from the semiconductor substrate by the gate insulating film, The aforementioned semiconductor substrate An n-type source layer (30) in contact with the gate insulating film on the side surface of the trench, A p-type body layer (34) is located below the source layer and is in contact with the gate insulating film on the side surface of the trench, A plurality of p-type deep layers (36), each extending from the body layer to below the bottom surface of the trench, and when viewed from above on the semiconductor substrate, extending along a first direction and arranged at intervals from each other in a second direction perpendicular to the first direction, A plurality of n-type deep layers (37), each of which is arranged at a corresponding interval among a plurality of intervals defined between adjacent p-type deep layers, and which are in contact with the gate insulating film on the side surface of the trench located below the body layer, An n-type drift layer (38) is positioned below the plurality of p-type deep layers and the plurality of n-type deep layers and is in contact with the plurality of n-type deep layers, A semiconductor device having an n-type high-concentration layer (39) that is in contact with at least a portion of the lower surface of a corresponding p-type deep layer among the plurality of p-type deep layers, and has a higher concentration of n-type impurities than the drift layer.

2. The semiconductor device according to claim 1, wherein the n-type high-concentration layer is in contact with at least both ends of the lower surface of the corresponding p-type deep layer in the second direction.

3. The semiconductor device according to claim 2, wherein the n-type high-concentration layer is in contact with the entire lower surface of the corresponding p-type deep layer.

4. The semiconductor device according to claim 3, wherein the width of the n-type high-concentration layer in the second direction is greater than the width of the p-type deep layer in the second direction, and as a result, the n-type high-concentration layer is in contact with the n-type deep layer adjacent to the p-type deep layer.

5. The semiconductor device according to any one of claims 1 to 4, wherein the plurality of p-type deep layers extend below the plurality of n-type deep layers.

6. The semiconductor device according to claim 5, wherein the n-type high-concentration layer is also in contact with the side surface of the p-type deep layer which is located below the plurality of n-type deep layers.

7. The semiconductor device according to any one of claims 1 to 6, wherein the n-type high-concentration layer has a lower concentration of n-type impurities than the plurality of n-type deep layers.

8. A method for manufacturing a semiconductor device (10), A deep layer formation step comprising forming a plurality of p-type deep layers (36) and a plurality of n-type deep layers (37) on an n-type epitaxial layer (50), wherein each of the plurality of p-type deep layers extends along a first direction when the epitaxial layer is viewed from above and is spaced apart from each other in a second direction perpendicular to the first direction, and each of the plurality of n-type deep layers is positioned at a corresponding interval among a plurality of intervals defined between adjacent p-type deep layers, An n-type high-concentration layer formation step, which forms an n-type high-concentration layer that is in contact with at least a portion of the lower surface of a corresponding p-type deep layer among the plurality of p-type deep layers and has a higher concentration of n-type impurities than the epitaxial layer, A method for manufacturing a semiconductor device, comprising the same equipment.

9. The method for manufacturing a semiconductor device according to claim 8, wherein the ion implantation mask for forming the plurality of p-type deep layers in the deep layer formation step and the ion implantation mask for forming the n-type high-concentration layer in the n-type high-concentration layer formation step are common.

10. The method for manufacturing a semiconductor device according to claim 8, wherein the opening width in the second direction of the ion implantation mask for forming the n-type high-concentration layer in the n-type high-concentration layer formation step is greater than the opening width in the second direction of the ion implantation mask for forming the plurality of p-type deep layers in the deep layer formation step.

11. A method for manufacturing a semiconductor device according to any one of claims 8 to 10, wherein the n-type high-concentration layer is formed using oblique ion implantation technology in the n-type high-concentration layer formation step.

12. The method for manufacturing a semiconductor device according to any one of claims 8 to 11, wherein the n-type high-concentration layer has a lower concentration of n-type impurities than the plurality of n-type deep layers.

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