Method for manufacturing a semiconductor device and semiconductor device

Abstract

The present invention provides a method for manufacturing a semiconductor device and a semiconductor device that can obtain a film structure of a desired shape. [Solution] The method for manufacturing a semiconductor device according to this embodiment comprises forming a laminate in which a sacrificial layer and an insulating layer are alternately stacked in a first direction. The manufacturing method also comprises forming a second layer on a first layer. The manufacturing method also comprises forming a first charge storage layer on a third layer. The manufacturing method also comprises exposing the second layer by removing the first layer in the region where the sacrificial layer has been removed. The manufacturing method also comprises selectively forming a fifth insulating layer on the insulating layer and the first layer. The manufacturing method also comprises selectively forming a second charge storage layer on the exposed first charge storage layer. The manufacturing method also comprises forming a sixth insulating layer on the second charge storage layer.

Description

Technical Field

[0005]

[0001] Embodiments of the present invention relate to a method for manufacturing a semiconductor device and a semiconductor device.

Background Art

[0002] A NAND flash memory in which memory cells are arranged three-dimensionally as a semiconductor device is known. In this NAND flash memory, a memory hole penetrating the stacked body is provided in a stacked body in which a plurality of electrode layers and insulating layers are alternately stacked. By providing a charge storage layer and a semiconductor layer in this memory hole, a memory string in which a plurality of memory cells are connected in series is formed. Data is stored in the memory cell by controlling the amount of charge held in the charge storage layer.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0004] Provided are a method for manufacturing a semiconductor device and a semiconductor device capable of obtaining a film structure having a desired shape.​​​​​​The manufacturing method for a semiconductor device according to this embodiment comprises forming a laminate in which a sacrificial layer and an insulating layer are alternately stacked in a first direction. The manufacturing method also comprises forming a hole penetrating the laminate in a first direction. The manufacturing method also comprises forming a first insulating film on the inner surface of the hole. The manufacturing method also comprises forming a second film on the first film. The manufacturing method also comprises forming a third insulating film on the second film. The manufacturing method also comprises forming a first charge storage film on the third film. The manufacturing method also comprises forming a fourth insulating film on the first charge storage film. The manufacturing method also comprises forming a semiconductor layer on the fourth film. The manufacturing method also comprises removing the sacrificial layer so that the first film is exposed. The manufacturing method also comprises exposing the second film by removing the first film in the region where the sacrificial layer has been removed. The manufacturing method also comprises selectively forming a fifth insulating film on the insulating layer and the first film. Furthermore, this manufacturing method comprises exposing the first charge storage film by removing the second film and the third film in the region where the sacrificial layer has been removed. Furthermore, this manufacturing method comprises selectively forming the second charge storage film on the exposed first charge storage film. Furthermore, this manufacturing method comprises forming the sixth insulating film on the second charge storage film. [Brief explanation of the drawing]

[0006] [Figure 1A] A schematic cross-sectional view of a memory cell of a semiconductor device according to the first embodiment. [Figure 1B] A schematic cross-sectional view of a memory cell of a semiconductor device according to the first embodiment. [Figure 2] A cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment. [Figure 3] A cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment. [Figure 4] A cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment. [Figure 5] A cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment. [Figure 6]A cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment. [Figure 7] A cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment. [Figure 8] A cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment. [Figure 9] A cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment. [Figure 10] A cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment. [Figure 11] A cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment. [Figure 12] A cross-sectional view showing the manufacturing process of a semiconductor device according to the second embodiment. [Figure 13] A cross-sectional view showing the manufacturing process of a semiconductor device according to the second embodiment. [Modes for carrying out the invention]

[0007] Embodiments of the present invention will be described below with reference to the drawings. These embodiments are not limiting to the present invention. The drawings are schematic or conceptual, and the proportions of each part may not necessarily be the same as those of actual objects. In the specification and drawings, elements similar to those described above with respect to previously shown drawings are denoted by the same reference numerals, and detailed explanations are omitted as appropriate.

[0008] (First Embodiment) The semiconductor device of the first embodiment is a three-dimensional NAND flash memory.

[0009] Figures 1A and 1B are schematic cross-sectional views of the memory cell array 100 of the semiconductor device according to the first embodiment. Figures 1A and 1B show cross-sections of multiple memory cells MC in a single memory string within the memory cell array 100.

[0010] FIG. 1A is a yz cross-sectional view of the memory cell array 100. FIG. 1A is a cross-section taken along line BB' of FIG. 1B. FIG. 1B is an xy cross-sectional view of the memory cell array 100. FIG. 1B is a cross-section taken along line AA' of FIG. 1A. In FIG. 1A, the region surrounded by the dashed line is one memory cell MC.

[0011] As shown in FIGS. 1A and 1B, the memory cell array 100 includes a plurality of word lines 40, a semiconductor layer 32, a plurality of insulating layers 21, a tunnel insulating film 30, a charge storage film 28, a plurality of charge storage films 29, a block film 37a, a plurality of block films 37, a core insulating film 33, and a plurality of cover films 26. The plurality of word lines 40 and the plurality of insulating layers 21 constitute a stacked body 20.

[0012] The memory cell array 100 is provided, for example, on a semiconductor substrate (not shown). The semiconductor substrate has a surface parallel to the x direction and the y direction.

[0013] The word lines 40 and the insulating layers 21 are alternately stacked in the z direction (the first direction) on the semiconductor substrate. The word lines 40 are spaced apart in the z direction. The word lines 40 are repeatedly arranged in the z direction while being spaced apart from each other. The plurality of word lines 40 and the plurality of insulating layers 21 constitute a stacked body 20. The word lines 40 function as control electrodes of the memory cell transistors.

[0014] The word line 40 is a plate-shaped conductor. The word line 40 is, for example, metal, metal nitride, metal carbide, or semiconductor. The word line 40 is, for example, tungsten (W) or molybdenum (Mo). The thickness of the word line 40 in the z direction is, for example, 5 nm or more and 20 nm or less.

[0015] The insulating layer 21 separates the word lines 40 from each other. The insulating layer 21 electrically separates the word lines 40 from each other.

[0016] The insulating layer 21 is, for example, oxide, oxynitride, or nitride. The insulating layer 21 is, for example, silicon oxide. The thickness of the insulating layer 21 in the z direction is, for example, 5 nm or more and 20 nm or less.

[0017] The semiconductor layer 32 is provided within the laminate 20. The semiconductor layer 32 extends in the z direction. The semiconductor layer 32 extends in a direction perpendicular to the surface of the semiconductor substrate.

[0018] The semiconductor layer 32 is provided penetrating the laminate 20. The semiconductor layer 32 is surrounded by a plurality of word lines 40. The semiconductor layer 32 is, for example, cylindrical. The semiconductor layer 32 functions as a channel for a memory cell transistor.

[0019] The semiconductor layer 32 is, for example, a polycrystalline semiconductor. The semiconductor layer 32 is, for example, polycrystalline silicon.

[0020] The tunnel insulating film 30 is provided between the semiconductor layer 32 and the word lines 40. The tunnel insulating film 30 is provided between the semiconductor layer 32 and multiple word lines 40. The tunnel insulating film 30 is provided between the semiconductor layer 32 and the charge storage film 29. The tunnel insulating film 30 is provided between the semiconductor layer 32 and the charge storage film 28.

[0021] The tunnel insulating film 30 has the function of allowing charge to pass through in accordance with the voltage applied between the word line 40 and the semiconductor layer 32.

[0022] The tunnel insulating film 30 includes, for example, silicon (Si) and oxygen (O). The tunnel insulating film 30 includes, for example, silicon (Si), oxygen (O), and nitrogen (N).

[0023] The tunnel insulating film 30 includes, for example, silicon oxide or silicon oxynitride. The tunnel insulating film 30 is, for example, a laminated film of a silicon oxide film, a silicon oxynitride film, and a silicon oxide film.

[0024] The thickness of the tunnel insulating film 30 in the y-direction is, for example, 3 nm to 8 nm.

[0025] The charge storage film 28 is provided between the tunnel insulating film 30 and the charge storage film 29. The charge storage film 28 is provided between the tunnel insulating film 30 and the insulating layer 21. The charge storage film 28 is in contact with the charge storage film 29.

[0026] The charge storage film 28 functions as a seed film when the charge storage film 29 is formed by vapor phase growth.

[0027] The charge storage film 28 contains silicon (Si) and nitrogen (N). The charge storage film 28 contains, for example, silicon nitride. The charge storage film 28 is, for example, a silicon nitride film.

[0028] The charge storage film 28 includes, for example, silicon (Si), nitrogen (N), and oxygen (O). The charge storage film 28 also includes, for example, silicon oxynitride.

[0029] The thickness of the charge storage film 28 in the y-direction is, for example, between 1 nm and 5 nm.

[0030] The charge storage film 29 is provided between the tunnel insulating film 30 and the word line 40. The charge storage film 29 is provided between the tunnel insulating film 30 and the block film 37. Multiple charge storage films 29 are separated from each other. A cover film 26 is sandwiched between two adjacent charge storage films 29 in the z direction.

[0031] The charge storage film 29 has the function of trapping and storing electric charge. This charge is, for example, electrons. The threshold voltage of the memory cell transistor changes depending on the amount of charge stored in the charge storage film 29. By utilizing this change in threshold voltage, a single memory cell MC can store data.

[0032] For example, a change in the threshold voltage of a memory cell transistor changes the voltage at which the memory cell transistor turns on. If we define a high threshold voltage state as data "0" and a low threshold voltage state as data "1", then the memory cell MC can store 1-bit data of "0" and "1".

[0033] The charge storage film 29 contains silicon (Si) and nitrogen (N). The charge storage film 29 contains, for example, silicon nitride. The charge storage film 29 is, for example, a silicon nitride film.

[0034] The block film 37a has a first portion 37a_1 and a second portion 37a_2. In the example shown in Figure 1A, the first portion 37a_1 and the second portion 37a_2 are connected. However, the first portion 37a_1 and the second portion 37a_2 do not necessarily have to be connected.

[0035] The first portion 37a_1 of the block film 37a is provided between the charge storage film 29 and the block film 37.

[0036] The first portion 37a_1 of the block film 37a has the function of blocking the current flowing between the charge storage film 29 and the word line 40.

[0037] The second portion 37a_2 of the block film 37a is provided between the insulating layer 21 and the charge storage film 29.

[0038] The block film 37a (including the first portion 37a_1 and the second portion 37a_2) contains, for example, silicon and oxygen. The block film 37a contains, for example, silicon oxide. The block film is, for example, a silicon oxide film. The second portion 37a_2 according to the first embodiment contains nitrogen, as will be described later.

[0039] The block film 37 is provided between the first portion 37a_1 of the block film 37a and the word line 40. The block film 37 is in contact with the insulating layer 21 in the z direction.

[0040] The blocking film 37 has the function of blocking the current flowing between the charge storage film 29 and the word line 40.

[0041] The block film 37 contains, for example, aluminum oxide. The block film 37 is, for example, an aluminum oxide layer.

[0042] The core insulating film 33 is provided within the laminate 20. The core insulating film 33 extends in the z direction. The core insulating film 33 penetrates the laminate 20. The core insulating film 33 is surrounded by the semiconductor layer 32. The core insulating film 33 is surrounded by a plurality of word lines 40. The core insulating film 33 is columnar. The core insulating film 33 is, for example, cylindrical.

[0043] The core insulating film 33 is, for example, an oxide, an oxynitride, or a nitride. The core insulating film 33 includes, for example, silicon oxide. The core insulating film 33 is, for example, a silicon oxide layer.

[0044] The cover film 26 is provided between the charge storage film 28 and the insulating layer 21. The cover film 26 is in contact with the charge storage film 28 and the insulating layer 21. The cover film 26 contains, for example, silicon and oxygen. The cover film 26 is, for example, a silicon oxide film.

[0045] The thickness of the cover film 26 in the y-direction is, for example, 3 nm to 8 nm.

[0046] The cover film 26a is provided between the insulating layer 21 and the second portion 37a_2 of the block film 37a. The cover film 26a contains, for example, silicon and oxygen. The cover film 26a is, for example, a silicon oxide film.

[0047] The thickness of the cover film 26a in the y-direction is, for example, 2 nm to 3 nm. Therefore, in the y-direction intersecting the z-direction, the cover film 26 is thicker than the cover film 26a.

[0048] A semiconductor device according to the first embodiment will be described with reference to Figures 2 to 11. The semiconductor device of this embodiment is manufactured, for example, by the method shown below. First, as shown in Figure 2, insulating layers 21 and sacrificial layers 22 are alternately stacked on a semiconductor substrate 10. This forms a laminate 20 stacked in the z direction (up and down direction in the figure). The insulating layer 21 is, for example, a silicon oxide layer. The sacrificial layer 22 is, for example, a silicon nitride layer.

[0049] The insulating layer 21 and the sacrificial layer 22 are formed, for example, by the CVD (Chemical Vapor Deposition) method. A portion of the insulating layer 21 becomes an interlayer insulating layer.

[0050] Next, as shown in Figure 3, memory holes 24 are formed in the laminate 20 along the z-direction. In the drawings from Figure 3 onward, the semiconductor substrate 10 is omitted. These memory holes 24 penetrate the laminate 20 that constitutes the insulating layer 21 and the sacrificial layer 22. These memory holes 24 are formed, for example, using lithography and RIE (Reactive Ion Etching).

[0051] Next, as shown in Figure 4, a silicon oxide film with a thickness of 2 nm to 3 nm is formed on the inner wall of the memory hole 24 as a cover film 26a. The cover film 26a also functions as a stopper film. On this cover film 26a, a silicon nitride film with a thickness of 2 nm is formed as a cover film 37b. That is, the cover film 37b contains silicon and nitrogen. The cover film 37b also functions as a stopper film. On this cover film 37b, a silicon oxide film with a thickness of 5 nm is formed as a cover film 26. The cover film 26 also functions as a stopper film. On this cover film 26, a silicon nitride film with a thickness of 2 nm is formed as a charge storage film 28, which becomes part of the charge storage film. On this charge storage film 28, a silicon oxynitride film with a thickness of 5 nm is formed as a tunnel insulating film 30. On this tunnel insulating film 30, a semiconductor layer 32 with a thickness of 7 nm is formed. The cover film 26, charge storage film 28, and tunnel insulating film 30 are formed, for example, by CVD. Polysilicon is typically used as the material for the semiconductor layer 32. However, from the viewpoint of surface roughness, a method is used in which amorphous silicon is formed at a low temperature (for example, around 500°C) and then crystallized by heat treatment at, for example, 800°C or higher. Note that the materials for the cover films 26a, 37b, 26, charge storage film 28, and tunnel insulating film 30 are examples and are not particularly limited as long as they are materials that can realize the structure of the semiconductor device of the embodiment described in Figures 1A and 1B.

[0052] Furthermore, the cover film 37b is not limited to a silicon nitride film. The cover film 37b includes a material that can provide etching selectivity with the cover films 26 and 26a, which are silicon oxide films. In addition, the cover film 37b includes a material that can be converted into an oxide film by oxidation treatment in a later process, for example.

[0053] Next, as shown in Figure 5, the memory holes 24 are filled with a core insulating film 33. The core insulating film 33 is, for example, a silicon oxide film. In the following description, the cross-section is symmetrical with respect to the center line CC shown in Figure 5, so the cross-section to the left of the center line CC will be described. Note that the tunnel insulating film 30, semiconductor layer 32, and core insulating film 33 are not shown in the following drawings.

[0054] Subsequently, grooves are opened around the memory holes 24, penetrating the laminate 20, and the sacrificial layer 22 is removed from these grooves. Removal of the sacrificial layer 22 exposes the cover film 26a. Typically, heated phosphoric acid solution is used to remove the sacrificial layer 22. This chemical treatment creates voids 22a in the area where the silicon nitride layer was removed. These voids 22a trace the shape of the original sacrificial layer 22 (see Figure 6).

[0055] Next, as shown in Figure 7, the cover film 26a is partially removed with a hydrofluoric acid (HF) solution diluted to approximately 0.5%. This exposes a portion of the cover film 37b in the void 22a.

[0056] Furthermore, a portion of the insulating layer 21 is also eroded, resulting in a thinner film thickness T in the z direction of the insulating layer 21. In the example shown in Figure 7, the cover film 26a shows more removal in the z direction compared to the insulating layer 21. The etching rate of the cover film 26a is higher than that of the insulating layer 21. The difference in etching rates is adjusted by, for example, the film quality (film density) and impurity concentration. For example, the cover film 26a is formed to have a relatively low film density. The insertion position of the cover film 37b is determined according to the allowable film thickness of the insulating layer 21.

[0057] Next, as shown in Figure 8, a protective film 51 is selectively formed on the insulating layer 21 and the cover film 26a. More specifically, the protective film 51 is selectively grown from the insulating layer 21 and the cover film 26a by area selective deposition (ASD).

[0058] The protective film 51 includes, for example, silicon, oxygen, and carbon. The protective film 51 is, for example, a silicon oxycarbide (SiOC) film or a carbon-containing silicon oxide film. The material of the protective film 51 is not limited to these. The protective film 51 includes a material having an etching rate lower than that of the cover film 26.

[0059] The protective film 51 can compensate for the thinning of the insulating layer 21 due to partial erosion, thereby extending the processing time for the cover film 26 in subsequent processes.

[0060] Selective growth of the protective film 51 is carried out, for example, by supplying an inhibitor that selectively adsorbs onto the cover film 37b, which is a silicon nitride film, and supplying a precursor containing silicon (Si) and a precursor containing carbon (C), or a precursor containing both silicon and carbon.

[0061] Next, as shown in Figure 9, the cover film 37b is partially removed. This exposes a portion of the cover film 26. Subsequently, the cover film 26 is partially removed. This exposes a portion of the charge storage film 28. In addition, the protective film 51 is removed along with the portion of the cover film 26. Some of the protective film 51 may remain, but it is preferable that it be completely removed.

[0062] A portion of the cover film 26 and the protective film 51 are removed, for example, by a hydrofluoric acid solution.

[0063] If the film thickness T is too thin, silicon oxide (SiO2) may be formed on the insulating layer 21 by selective growth to compensate for the thinness.

[0064] Next, as shown in Figure 10, a charge storage film 29 is selectively formed on the charge storage film 28. More specifically, the charge storage film 29 is grown by selective growth. In addition, silicon nitride (SiN) may also grow on the exposed cover film 37b to form a film 52.

[0065] Next, as shown in Figure 11, a block film 37a is formed on the charge storage film 29. More specifically, a first portion 37a_1 and a second portion 37a_2 of the block film 37a are formed by oxidizing a portion of the charge storage film 29 and the cover film 37b. That is, silicon nitride is oxidized to form silicon oxide. The oxidation process is carried out until the thickness of the charge storage film 29 in the y-direction reaches the desired film thickness. The portion of the charge storage film 29 that is not oxidized remains as the charge storage film 29.

[0066] Furthermore, when silicon nitride oxidizes, it expands, and the second portion 37a_2, which was the cover film 37b, and the first portion 37a_1, which was the charge storage film 29, become connected. However, the first portion 37a_1 and the second portion 37a_2 do not necessarily have to be connected.

[0067] In the example shown in Figure 11, the oxidation of the film 52 makes it easier for the first part 37a_1 and the second part 37a_2 to connect.

[0068] Furthermore, since the block film 37a is formed by the oxidation of a portion of the silicon nitride film, it may contain nitrogen.

[0069] The graph shown on the right side of Figure 11 is a schematic graph showing the nitrogen concentration in the second part, 37a_2. The vertical axis represents the position in the z direction. The horizontal axis represents the nitrogen concentration.

[0070] The nitrogen concentration is highest in the center of the second section 37a_2 in the z direction, and decreases towards the upper and lower ends in the z direction. In other words, the nitrogen concentration in the center of the second section 37a_2 is higher than the nitrogen concentration at the ends closer to the word line 40. This is because nitrogen is less likely to escape during the oxidation process in the center.

[0071] Furthermore, the cover film 37b, which is a silicon nitride film, is formed to have a lower nitrogen concentration than the charge storage film 28, which is also a silicon nitride film. This prevents silicon nitride from remaining in the second portion 37a_2 of the block film 37a without being completely oxidized, thus preventing charge from being trapped.

[0072] The charge storage film of this embodiment includes a charge storage film 28 and a charge storage film 29. This process forms a charge storage film 29, which becomes part of the charge storage layer, with a thickness of approximately 1 nm to 2 nm in the y-direction. As a result, in the y-direction of the void 22a, the thickness of the charge storage film in the y-direction is the sum of the thickness of the charge storage film 28 (approximately 1 nm to 3 nm) and the thickness of the charge storage film 29 (approximately 1 nm to 2 nm). However, in areas where the charge storage film 29 is not provided, the charge storage film becomes the charge storage film 28, with a thickness of approximately 1 nm to 3 nm. That is, the charge storage film 28 constituting the charge storage film is continuous in the direction in which the semiconductor layer 32 extends (z-direction), but the charge storage film 29 is divided in the z-direction by the cover film 26. Therefore, a pseudo-divided structure of the charge storage film is formed.

[0073] Subsequently, a block film 37, for example, containing aluminum oxide, is formed to cover the bottom and sides of the void 22a. Alternatively, a barrier metal, for example, containing TiN, may be formed to cover the block film 37. Next, the void 22a is filled with a wiring material, for example, W (tungsten), to form word wires (electrodes) 40, and the semiconductor device is completed.

[0074] As described above regarding the pseudo-disruption structure of the charge storage film, the sum of the thicknesses of the charge storage film 28 and the charge storage film 29 in the y-direction is greater than the thickness of the charge storage film 28 in the y-direction.

[0075] As described above, according to the first embodiment, the cover film 37b is exposed by removing the cover film 26a in the region where the sacrificial layer 22 has been removed. In addition, a protective film 51 is selectively formed on the insulating layer 21 and the cover film 26a. The protective film 51 allows the insulating layer 21 to be selectively thickened while the cover film 37b remains exposed. After thickening the insulating layer 21 to the target film thickness, the charge storage film 28 is exposed by removing the cover film 37b and the cover film 26. A charge storage film 29 can be selectively formed on the exposed charge storage film 28 to obtain the desired segmented shape.

[0076] When forming a pseudo-disrupted structure of a charge storage film, for example, the silicon oxide stopper film (cover film) may be made thicker to accommodate the cell portion within the memory hole 24, taking back-to-back arrangement into consideration. However, it can be difficult to process a thick cover film into the appropriate shape.

[0077] Furthermore, if the laminate 20 is formed by laminating an OSiOC layer on the upper and lower surfaces of the insulating layer 21 in order to suppress the abrasion of the insulating layer 21 when the cover film is removed, the cost will increase.

[0078] In contrast, in the first embodiment, a silicon nitride film, which is a cover film 37b, is inserted between the silicon oxide film, which is a cover film 26a, and the cover film 26. Furthermore, a protective film 51 containing SiOC is formed on the insulating layer 21 by selective growth. This makes it possible to reduce interference between adjacent cells and costs while ensuring the thickness of the insulating layer 21.

[0079] (Second Embodiment) A semiconductor device according to the second embodiment will be described with reference to Figures 12 to 13. In the second embodiment, the material of the cover film 37b is different from that of the first embodiment. Therefore, in the second embodiment, the film 52 is not formed.

[0080] The cover film 37b includes, for example, silicon (Si). The steps shown in Figures 2 to 9 in the first embodiment are the same as the steps in the second embodiment.

[0081] After partially removing the cover film 37b and cover film 26 so that a portion of the charge storage film 28 is exposed (see Figure 9), a charge storage film 29 is selectively formed on the charge storage film 28 as shown in Figure 12. More specifically, the charge storage film 29 is grown by selective growth.

[0082] Next, as shown in Figure 13, a portion of the charge storage film 29 and the cover film 37b are oxidized to form the first portion 37a_1 and the second portion 37a_2 of the block film 37a. The process shown in Figure 13 is the same as the process shown in Figure 11.

[0083] The cover film 37b according to the second embodiment does not have charge-trapping properties even if it remains unoxidized.

[0084] As in the second embodiment, the material of the cover film 37b may be changed. The semiconductor device according to the second embodiment can obtain the same effects as the first embodiment.

[0085] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of Symbols]

[0086] 10 Semiconductor substrate, 20 Laminate, 21 Insulating layer, 21a Impurity, 21b Impurity-containing layer, 22 Sacrificial layer, 22a Void, 24 Memory hole, 26 Cover film, 26a Cover film, 28 Charge storage film, 29 Charge storage film, 37 Block film, 37a Block film, 37a_1 First part, 37a_2 Second part, 37b Cover film, 51 Protective film, 52 Film

Claims

1. A laminate is formed in which a sacrificial layer and an insulating layer are alternately stacked in the first direction. A hole is formed in the laminate that penetrates in the first direction, A first insulating film is formed on the inner surface of the hole. A second film is formed on the first film. A third insulating film is formed on the second film. A first charge storage film is formed on the third film, A fourth insulating film is formed on the first charge storage film. A semiconductor layer is formed on the aforementioned fourth film. Remove the sacrificial layer so that the first film is exposed. By removing the first film in the region where the sacrificial layer has been removed, the second film is exposed. A fifth insulating film is selectively formed on the insulating layer and the first film. By removing the second and third films in the region where the sacrificial layer has been removed, the first charge storage film is exposed. A second charge storage film is selectively formed on the exposed first charge storage film, and a sixth insulating film is formed on the second charge storage film. A method for manufacturing a semiconductor device, comprising the following:

2. The method for manufacturing a semiconductor device according to claim 1, wherein the etching rate of the fifth film is lower than the etching rate of the third film.

3. The method for manufacturing a semiconductor device according to claim 1, wherein the fifth film comprises silicon, oxygen, and carbon.

4. The method for manufacturing a semiconductor device according to claim 1, wherein removing the third film in the region where the sacrificial layer has been removed includes removing the third film and removing the fifth film.

5. The method for manufacturing a semiconductor device according to claim 1, wherein the second film contains silicon.

6. The first charge storage film contains nitrogen, The second film further contains nitrogen, The method for manufacturing a semiconductor device according to claim 5, wherein the nitrogen concentration of the second film is lower than the nitrogen concentration of the first charge storage film.

7. A method for manufacturing a semiconductor device according to claim 1, wherein selectively forming the second charge storage film on the exposed first charge storage film includes forming the second charge storage film and forming a seventh insulating film on the second film.

8. A method for manufacturing a semiconductor device according to claim 1, wherein each of the first and third films comprises silicon and oxygen.

9. The method for manufacturing a semiconductor device according to claim 1, wherein the second charge storage film comprises silicon and nitrogen.

10. The method for manufacturing a semiconductor device according to claim 1, wherein the fourth film is a tunnel insulating film.

11. A laminate in which electrode layers and insulating layers are alternately stacked in a first direction, A semiconductor layer arranged along the first direction within the laminate, A first insulating film is disposed between the laminate and the semiconductor layer along the first direction, A first charge storage film is disposed between the laminate and the first insulating film along the first direction, A second charge storage film is disposed between the electrode layer and the first charge storage film, A second insulating film is disposed between the insulating layer and the first charge storage film, A third insulating film having a first portion and a second portion, wherein the first portion is disposed between the electrode layer and the second charge storage film, and the second portion is disposed between the insulating layer and the second insulating film, A fourth insulating film is disposed between the insulating layer and the second portion, Equipped with, The first and second parts comprise silicon and oxygen. The second part further contains nitrogen, and is a semiconductor device.

12. The semiconductor device according to claim 11, wherein in a second direction intersecting the first direction, the second insulating film is thicker than the fourth insulating film.

13. The semiconductor device according to claim 11, wherein the concentration of nitrogen in the central part of the second part is higher than the concentration of nitrogen in the end of the second part that is closer to the electrode layer than the central part.

14. The semiconductor device according to claim 11, wherein the second part is connected to the first part.

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