VCSEL component and method for manufacturing the same

Abstract

This invention provides a method for manufacturing VCSEL components that simplifies subsequent processes and improves heat dissipation efficiency. [Solution] A method for manufacturing a VCSEL member includes the steps of: providing an indium phosphide substrate; performing an epitaxial process to form an epitaxial structure on the indium phosphide substrate; performing a first mesa forming process to form a first mesa on the epitaxial structure; performing an epitaxial process to form a tunnel junction on the first mesa; removing the indium phosphide substrate; performing a second mesa forming process to form a second mesa on the epitaxial structure and to form a gap between the first and second mesa; performing a deposition process to form an insulating layer on the epitaxial structure; and performing a metallization process to form an N-type electrode located at the bottom surface of the epitaxial structure and a P-type electrode extending from the top surface of the epitaxial structure along the side wall to the bottom surface.

Description

Technical Field

[0001] The present invention relates to a VCSEL member and a manufacturing method thereof, particularly to a VCSEL member and a manufacturing method thereof that simplify post-processes and improve heat dissipation efficiency.

Background Art

[0002] A laser diode has the characteristic of emitting strong light like a laser with a small volume and is widely applied in various fields such as optical transmission, medical treatment, 3D sensing, and 3C products. Based on the difference between the epitaxial direction and the resonance and emission directions of the laser light, laser diodes can be mainly divided into vertical-cavity surface-emitting lasers (VCSELs) and edge-emitting lasers (EELs). Since VCSEL members have characteristics such as high optical purity and low energy consumption compared to EEL members, they have gradually become the mainstream of laser diodes in recent years.

[0003] Taking a conventional indium phosphide (InP) VCSEL member as an example, the whole forms a single vertical mesa structure, which assists in the execution of each process. However, a conventional InP VCSEL member needs to cooperate with related processes such as packaging and wire bonding in the post-process of the manufacturing process, making the whole process complicated and increasing costs. After packaging and wire bonding, the volume and area occupied by the InP VCSEL member also increase, which is disadvantageous for heat dissipation and prone to problems such as component failures.

[0004] Therefore, how to design a VCSEL member and a manufacturing method thereof that can improve the above problems is an issue worthy of research.

Summary of the Invention

Problems to be Solved by the Invention

[0005] The objective of the present invention is to provide a method for manufacturing a VCSEL member that simplifies subsequent processes and improves heat dissipation efficiency. [Means for solving the problem]

[0006] To achieve the above objective, the present invention provides: the steps of providing an indium phosphide substrate; performing an epitaxial process to form an epitaxial structure on the indium phosphide substrate, wherein the epitaxial structure includes a top surface and a bottom surface, and the epitaxial structure is formed by sequentially laminating an N-type indium gallium arsenide layer, an N-type distributed Bragg mirror layer, an emissive layer, a P-type distributed Bragg mirror layer, and a P-type indium gallium arsenide layer starting from a location adjacent to the indium phosphide substrate on the bottom surface; performing a first mesa forming process to form a first mesa on the epitaxial structure from the top surface; and performing an epitaxial process to form a first A method for manufacturing a VCSEL member is provided, comprising the steps of: forming a tunnel junction within a mesa; removing an indium phosphide substrate; performing a second mesa forming process to form a second mesa on the epitaxial structure from the top surface and creating a gap between the second mesa and the first mesa; performing a deposition process to form an insulating layer on the epitaxial structure; and performing a metallization process to form an N-type electrode and a P-type electrode on the epitaxial structure, wherein the N-type electrode is located on the bottom surface of the epitaxial structure and the P-type electrode extends from the top surface of the epitaxial structure along the side wall to the bottom surface.

[0007] In one embodiment of the present invention, the tunnel junction is formed within a P-type distributed Bragg mirror layer and is adjacent to the light-emitting layer.

[0008] In one embodiment of the present invention, the first mesa and the second mesa are each extended from the top surface to the bottom surface of the epitaxial structure to the light-emitting layer, and the first mesa and the second mesa are made coplanar based on the N-type distributed Bragg mirror layer.

[0009] In one embodiment of the present invention, the insulating layer is formed on all surfaces of the epitaxial structure except the bottom surface and the first top surface of the first mesa.

[0010] In one embodiment of the present invention, the P-type electrode extends from the first upper surface of the first mesa to the bottom surface along the gap, the second upper surface of the second mesa, and the side wall of the epitaxial structure, with a portion of the P-type electrode and the N-type electrode both in contact with the bottom surface.

[0011] The present invention further provides a VCSEL member. The VCSEL member of the present invention includes an epitaxial structure, an insulating layer, an N-type electrode, and a P-type electrode. The epitaxial structure includes a top surface, a bottom surface, a first mesa, and a second mesa, and consists of an N-type indium gallium arsenide layer, an N-type distributed Bragg mirror layer, an emissive layer, a P-type distributed Bragg mirror layer, and a P-type indium gallium arsenide layer stacked in order from the bottom surface, with the first mesa and the second mesa extending from the top surface to the bottom surface to the emissive layer, the first mesa and the second mesa being coplanar based on the N-type distributed Bragg mirror layer, and a gap being formed between the second mesa and the first mesa, with a tunnel junction included within the first mesa. [Effects of the Invention]

[0012] The method for manufacturing the VCSEL member of the present invention can simplify subsequent processes and improve heat dissipation efficiency. [Brief explanation of the drawing]

[0013] [Figure 1] This is a flowchart of the manufacturing method for the VCSEL member of the present invention. [Figure 2] This is an explanatory diagram of the structure corresponding to each step in the manufacturing method of the VCSEL member of the present invention. [Figure 3] This is an explanatory diagram of the overall structure of the VCSEL member of the present invention. [Modes for carrying out the invention]

[0014] The various aspects and embodiments are merely illustrative and not limiting; therefore, after reviewing this specification, those skilled in the art may have other aspects and embodiments without departing from the scope of the present invention. The following detailed description and claims will make the features and advantages of the embodiments clearer.

[0015] In this specification, the terms "one" or "one" are used to describe elements and components described herein. This is for convenience of explanation and only provides a general meaning to the scope of the invention. Thus, unless it is evident that there is a different meaning, such descriptions shall be interpreted as including one or at least one, and the singular form also includes the plural.

[0016] In this specification, terms such as "first" and "second" are used primarily to distinguish or refer to identical or similar elements or structures, and do not necessarily imply a spatial or temporal order of these elements or structures. In certain situations or configurations, the ordinal numbers may be interchanged without affecting the implementation of the present invention.

[0017] In this specification, terms such as “includes” and “have” are intended to cover non-exclusive inclusion. For example, an element or structure that includes multiple requirements is not limited to the requirements listed herein, but may include other requirements that are not explicitly listed but are generally inherent to that element or structure.

[0018] In the following, Figures 1 and 2 will be used together. Figure 1 is a flowchart of the method for manufacturing a VCSEL member according to the present invention, and Figure 2 is an explanatory diagram of the structure corresponding to each step of the method for manufacturing a VCSEL member according to the present invention. As shown in Figures 1 and 2, the method for manufacturing a VCSEL member according to the present invention includes the following steps.

[0019] Step S1: Provide an indium phosphide substrate.

[0020] First, the present invention provides an indium phosphide (InP) substrate 10. The indium phosphide substrate 10 is a temporary substrate for the VCSEL member 1 of the present invention and is used to place the related basic structure of the VCSEL member 1 of the present invention, which is formed thereafter.

[0021] Step S2: Execute an epitaxial process to form an epitaxial structure on an indium phosphide substrate.

[0022] After providing the indium phosphide substrate 10 in the aforementioned step S1, next, the present invention can perform an epitaxial process such as metal organic chemical vapor deposition (MOCVD) on the indium phosphide substrate 10 to form an epitaxial structure 20 on the indium phosphide substrate 10. The epitaxial structure 20 includes an opposing upper surface 201 and a bottom surface 202, and a plurality of sidewalls 203 between the upper surface 201 and the bottom surface 202. The epitaxial structure 20 is adjacent to the indium phosphide substrate 10 at the bottom surface 202. In one embodiment of the present invention, the epitaxial structure 20 sequentially stacks an N-type indium gallium arsenide (InGaAs) layer 21, an N-type distributed Bragg reflector (DBR) layer 22, a light-emitting layer 23, a P-type distributed Bragg reflector layer 24, and a P-type indium gallium arsenide (InGaAs) layer 25 starting from a location adjacent to the indium phosphide substrate 10 at the bottom surface 202, and the upper surface 201 is located on the opposite side of the P-type indium gallium arsenide layer 25, but the present invention is not limited thereto. The N-type distributed Bragg reflector layer 22 is formed by stacking a plurality of N-type semiconductor material layers, and the P-type distributed Bragg reflector layer 24 is formed by stacking a plurality of P-type semiconductor material layers. In one embodiment of the present invention, the light-emitting layer 23 may be a multiple quantum well (MQW) layer.

[0023] Step S3: Execute a first mesa forming process to form a first mesa from the upper surface on the epitaxial structure.

[0024] After forming the epitaxial structure 20 in the aforementioned step S2, a first mesa formation process (for example, a related process such as etching) can be executed on the epitaxial structure 20 to form a first mesa A1 from the upper surface 201 of the epitaxial structure 20. The first mesa A1 extends from the upper surface 201 to the light-emitting layer 23 towards the bottom surface 202 of the epitaxial structure 20 and constitutes the entire independent mesa structure. The first mesa A1 includes a first upper surface A11 and a plurality of first sidewalls A12. Since the horizontal cross-sectional area of the first mesa A1 gradually increases from top to bottom, inclined wall surfaces are formed on each of the first sidewalls A12.

[0025] Step S4: Execute an epitaxial process to form a tunnel junction on the first mesa.

[0026] After forming the first mesa A1 in the aforementioned step S3, the present invention can execute another epitaxial process on the first mesa A1 to form a tunnel junction 26 on the first mesa A1. In an embodiment of the present invention, the tunnel junction 26 is formed within the P-type distributed Bragg reflector layer 24 and is adjacent to the light-emitting layer 23. The tunnel junction 26 is a junction formed by a combination of a highly doped P-type semiconductor region and an N-type semiconductor region. With the tunnel junction 26, current can flow uniformly, and the light-emitting efficiency is improved.

[0027] Step S5: Remove the indium phosphide substrate.

[0028] After forming the tunnel junction 26 on the first mesa A1 in the aforementioned step S4, next, the present invention can perform a removal operation on the indium phosphide substrate 10 to leave the epitaxial structure 20 on which the first mesa A1 is formed.

[0029] Step S6: Execute a second mesa forming process to form a second mesa from the upper surface of the epitaxial structure.

[0030] After removing the indium phosphide substrate 10 in step S5 described above, the present invention can perform a second mesa forming process (e.g., related processes such as etching) on ​​the epitaxial structure 20 to form a second mesa A2 on the epitaxial structure 20 from the top surface 201. The second mesa A2 extends from the top surface 201 of the epitaxial structure 20 toward the bottom surface 202 toward the light-emitting layer 23, forming an entire independent mesa structure. The second mesa A2 includes a second top surface A21 and a plurality of second side walls A22, and the horizontal cross-sectional area of ​​the second mesa A2 gradually increases from top to bottom, so that inclined wall surfaces are formed on each second side wall A22. Since the first mesa A1 and the second mesa A2 are independent mesa structures, a gap D is formed between the first mesa A1 and the second mesa A2. The second mesa A2 can be considered an extended mesa of the first mesa A1, and in fact, the first mesa A1 and the second mesa A2 are coplanar based on the N-type distributed Bragg mirror layer 22.

[0031] Furthermore, in the process of forming the second mesa A2 in step S6, the outer contour of the first mesa A1 can also be modified, and the formed VCSEL member 1 can be cut to conform to the required specifications.

[0032] Step S7: Perform the deposition process to form an insulating layer on the epitaxial structure.

[0033] After forming the second mesa A2 in step S6 described above, the present invention can perform a deposition process on the epitaxial structure 20 to form an insulating layer 30 on the epitaxial structure 20. In one embodiment of the present invention, the insulating layer 30 is formed on all surfaces of the epitaxial structure 20 except the bottom surface 202 and the first top surface A11 of the first mesa A1. In other words, the insulating layer 30 covers a plurality of first side walls A12 of the first mesa A1, the second top surface A21 of the second mesa A2, a plurality of second side walls A22, and the remaining side walls 203 of the epitaxial structure 20. In one embodiment of the present invention, the insulating layer 30 is made of silicon nitride (SiN x The present invention is manufactured using the following materials, but is not limited thereto.

[0034] Step S8: Perform a metallization process to form N-type and P-type electrodes on the epitaxial structure.

[0035] After forming the insulating layer 30 in step S7 described above, the present invention can perform a metallization process on the epitaxial structure 20 to form an N-type electrode 40 and a P-type electrode 50 on the epitaxial structure 20. In one embodiment of the present invention, the N-type electrode 40 is located on the bottom surface 202 of the epitaxial structure 20, and the P-type electrode 50 extends from the top surface 201 of the epitaxial structure 20 along the side wall 203 to the bottom surface 202. In another embodiment of the present invention, the P-type electrode 50 extends from the first top surface A11 of the first mesa A1 along the gap D, the second top surface A21 of the second mesa A2 and the side wall 203 of the epitaxial structure 20 to the bottom surface 202, with a portion of the P-type electrode 50 and the N-type electrode 40 both in contact with the bottom surface 202. That is, in the VCSEL member 1 of the present invention, a portion of the P-type electrode 50 and the N-type electrode 40 are both installed on the bottom surface 202. Furthermore, the P-type electrode 50 has an opening 51 formed on the first upper surface A11 of the first mesa A1, and the position of the opening 51 corresponds to the tunnel junction 26, so that the light rays emitted from the light-emitting layer 23 pass sequentially through the tunnel junction 26 and the opening 51 of the P-type electrode 50 and are emitted to the outside. In one embodiment of the present invention, the N-type electrode 40 is made of germanium gold (GeAu) material and the P-type electrode 50 is made of titanium / platinum / gold (Ti / Pt / Au) material, but the present invention is not limited thereto.

[0036] Furthermore, as shown in Figure 3, the present invention further provides a VCSEL member 1. The VCSEL member 1 of the present invention can be manufactured by the manufacturing method described above. The VCSEL member 1 of the present invention mainly comprises an epitaxial structure 20, an insulating layer 30, an N-type electrode 40, and a P-type electrode 50. The epitaxial structure 20 includes a top surface 201, a bottom surface 202, a first mesa A1, and a second mesa A2. The epitaxial structure 20 is formed by sequentially laminating an N-type gallium indium arsenide layer 21, an N-type distributed Bragg mirror layer 22, an emissive layer 23, a P-type distributed Bragg mirror layer 24, and a P-type gallium indium arsenide layer 25 from the bottom surface 202. The first mesa A1 and the second mesa A2 each extend from the top surface 201 to the bottom surface 202 to the light-emitting layer 23, and the first mesa A1 and the second mesa A2 are made coplanar based on the N-type distributed Bragg reflector layer 22, and a gap is formed between the second mesa A2 and the first mesa A1. The first mesa A1 includes a tunnel joint 26.

[0037] In one embodiment of the present invention, the moist oxygen layer 26 is formed within the P-type distributed Bragg mirror layer 24 and is adjacent to the light-emitting layer 23.

[0038] In one embodiment of the present invention, the VCSEL member 1 of the present invention can be applied to long-wavelength optical bands such as the infrared optical band, but the present invention is not limited thereto.

[0039] In summary, the VCSEL member 1 of the present invention emits light rays through the first mesa A1, improves luminescence efficiency by combining it with the installation of a tunnel junction 26, extends the second mesa A2 to facilitate the installation of the P-type electrode 50, and extends the P-type electrode 50 from the top surface 201 to the bottom surface 202 of the epitaxial structure 20 to form an electrode flip-chip type. Since both the N-type electrode 40 and the P-type electrode 50 are present on the bottom surface 202 of the VCSEL member 1 of the present invention, the VCSEL member 1 of the present invention can be electrically conductive and operate simply by being directly installed on the corresponding device or component on the bottom surface 202, eliminating the need to separately perform processes such as wire bonding or packaging for the N-type electrode 40 or the P-type electrode 50, and thus more effectively reduces the overall volume and saves manufacturing costs compared to conventional VCSEL members. Furthermore, the formation of the second mesa A2 can increase the base contact area between the VCSEL member 1 of the present invention and the corresponding device or component, providing an even better heat dissipation effect.

[0040] The above-described embodiments are essentially for illustrative purposes only and are not intended to limit the embodiments of the claimed subject matter or the applications or uses of those embodiments. Furthermore, while the embodiments described herein present at least one exemplary embodiment, it should be understood that many variations of the invention are still possible. It should also be understood that the embodiments described herein are not intended to limit in any way the scope, uses, or configurations of the claimed subject matter. Conversely, the embodiments described herein provide a brief guide for those skilled in the art to implement one or more of the embodiments described herein. Furthermore, various modifications can be made to the function and arrangement of the components without departing from the scope defined by the claims, and the claims include all known and foreseeable equivalents at the time of filing this patent application. [Explanation of Symbols]

[0041] 1 VCSEL member 10 Indium phosphide substrates 20 Epitaxial structure 201 Top surface 202 Bottom 203 Side wall 21 N-type indium gallium arsenide layer 22 N-type distributed Bragg mirror layer 23. Emitting layer 24 P-type distributed Bragg mirror layer 25 P-type indium gallium arsenide layer 26 Tunnel Joining 30 Insulating layer 40 N-type electrode 50 P type electrode 51 Aperture A1 Mesa 1 A11 1st top surface A12 1st side wall A2 Second Mesa A21 2nd top surface A22 2nd side wall S1 Step S2 Step S3 Step S4 Step S5 Step S6 Step S7 Step S8 Step

Claims

1. The steps include providing an indium phosphide substrate, The steps include performing an epitaxial process to form an epitaxial structure on the indium phosphide substrate, wherein the epitaxial structure includes a top surface and a bottom surface, and the epitaxial structure is formed by sequentially stacking an N-type indium gallium arsenide layer, an N-type distributed Bragg mirror layer, an emissive layer, a P-type distributed Bragg mirror layer, and a P-type indium gallium arsenide layer starting from a location adjacent to the indium phosphide substrate on the bottom surface, A step of performing a first mesa forming process to form a first mesa on the epitaxial structure from the upper surface, The steps include: performing an epitaxial process to form a tunnel junction within the first mesa; The step of removing the indium phosphide substrate, A step of performing a second mesa forming process to form a second mesa on the epitaxial structure from the upper surface and to form a gap between the second mesa and the first mesa, The steps include: performing a deposition process to form an insulating layer on the epitaxial structure, The steps include: performing a metallization process to form an N-type electrode and a P-type electrode on the epitaxial structure, wherein the N-type electrode is located on the bottom surface of the epitaxial structure, and the P-type electrode extends from the top surface of the epitaxial structure along the side wall to the bottom surface; A method for manufacturing VCSEL components, including the method described above.

2. The method for manufacturing a VCSEL member according to claim 1, wherein the tunnel junction is formed within a P-type distributed Bragg reflector layer and adjacent to the light-emitting layer.

3. A method for manufacturing a VCSEL member according to claim 1, wherein the first mesa and the second mesa are each extended from the upper surface to the bottom surface of the epitaxial structure to the light-emitting layer, and the first mesa and the second mesa are made coplanar based on the N-type distributed Bragg mirror layer.

4. The method for manufacturing a VCSEL member according to claim 1, wherein the insulating layer is formed on all surfaces of the epitaxial structure except the bottom surface and the first upper surface of the first mesa.

5. The method for manufacturing a VCSEL member according to claim 1, wherein the P-type electrode extends from the first upper surface of the first mesa to the bottom surface along the gap, the second upper surface of the second mesa, and the side wall of the epitaxial structure, and a part of the P-type electrode and the N-type electrode are both in contact with the bottom surface.

6. The structure includes a top surface, a bottom surface, a first mesa, and a second mesa, with an N-type indium gallium arsenide layer, an N-type distributed Bragg mirror layer, an emissive layer, a P-type distributed Bragg mirror layer, and a P-type indium gallium arsenide layer stacked in that order from the bottom surface, the first mesa and the second mesa each extending from the top surface toward the bottom surface to the emissive layer, the first mesa and the second mesa being coplanar based on the N-type distributed Bragg mirror layer, and a gap being formed between the second mesa and the first mesa, and an epitaxial structure including a tunnel junction within the first mesa. An insulating layer formed on the epitaxial structure, An N-type electrode formed on the bottom surface of the epitaxial structure, A P-type electrode extending from the upper surface of the epitaxial structure along the side wall to the bottom surface, VCSEL component, including

7. The VCSEL member according to claim 6, wherein the tunnel junction is formed within the P-type distributed Bragg reflector layer and is adjacent to the light-emitting layer.

8. The VCSEL member according to claim 6, wherein the insulating layer is formed on all surfaces of the epitaxial structure except the bottom surface and the first upper surface of the first mesa.

9. The VCSEL member according to claim 6, wherein the P-type electrode extends from the first upper surface of the first mesa to the bottom surface along the gap, the second upper surface of the second mesa, and the side wall of the epitaxial structure, and a part of the P-type electrode and the N-type electrode are both in contact with the bottom surface.

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