Impedance conversion circuit

Abstract

This invention provides an impedance conversion circuit designed to reduce noise voltage. [Solution] The impedance conversion circuit 1 uses the microphone's capacitor C MIC The input signal from is received, and the input signal is received with high impedance so as not to attenuate, and the load 2 is driven with a low impedance output. The gate of the PMOS transistor M1 is the input T IN Connected to the source, output T OUT The current source 4 supplies current to the source of the PMOS transistor M1. The back gate potential supply circuit 8 supplies a back gate potential to the back gate of the PMOS transistor M1 that corresponds to the source potential of the PMOS transistor M1.

Description

[Technical Field]

[0001] This invention relates to an impedance conversion circuit. [Background technology]

[0002] With the increasing number of electronic devices that use voice input, such as smartphones, PCs, and smart speakers, the demand for microphones is on the rise. These electronic devices are becoming smaller, and battery-powered devices require low power consumption. Therefore, the required characteristics of microphones are, firstly, low noise for acoustic performance, secondly, small size, and thirdly, low power consumption.

[0003] Figure 7 shows the configuration of a conventional impedance conversion circuit 100 (for example, Patent Document 1). The impedance conversion circuit 100 is a microphone capacitor C MIC This circuit receives the signal with high impedance to prevent attenuation of the signal output from the device, and outputs it with low impedance to drive the load 2. The impedance conversion circuit 100 includes a PMOS transistor M1 that performs impedance conversion, a current source 4 that supplies current to the PMOS transistor M1, and a DC bias circuit 5 that applies a DC bias to the PMOS transistor M1.

[0004] Next, Figure 8 shows the configuration of a conventional impedance conversion circuit 100B designed to reduce current consumption. In addition to the PMOS transistor M1, current source 4, and DC bias circuit 5, the impedance conversion circuit 100B includes a current detection circuit 6 that detects the drain current of the PMOS transistor M1, and a feedback circuit 7 that controls the current source 4 according to the detection result of the current detection circuit 6.

[0005] By providing the current detection circuit 6 and the feedback circuit 7, only the amount of current required for operation can be supplied to the PMOS transistor M1, thereby achieving low current consumption. Furthermore, the operating current of the PMOS transistor M1 can be kept constant, preventing changes in the gate-source potential. Therefore, the input signal is output directly, and distortion reduction can also be improved.

[0006] Since the source of PMOS transistor M1 is a P-type semiconductor and the back gate is an N-type semiconductor, it has a diode structure. Due to this diode structure, the current I flowing from the source to the back gate BG is expressed by the following equation (1).

[0007]

Equation

[0008] Here, V SB is the forward voltage of the source (P-type) · back gate (N-type), I S is the reverse saturation current, and V T is the thermal voltage. Therefore, the back gate current I BG increases exponentially with V SB . To prevent current from flowing from the source to the back gate, the conventional impedance conversion circuit 100B shown in FIG. 8 connects the back gate of PMOS transistor M1 to the source to make V SB zero, thereby preventing current from flowing from the source to the back gate.

[0009] It is known that the thermal noise current generated in PMOS transistor M1 in FIG. 8 is generally expressed by equation (2).

[0010]

Equation

[0011] Here, k is the Boltzmann constant, T is the absolute temperature, and gm is the transconductance of PMOS transistor M1. The thermal noise current and the noise voltage v noise_GS between the gate and the source have the relationship shown in the following equation (3).

[0012]

Equation

[0013] Noise voltage v between gate and source noise_GS This is the gate-source parasitic capacitance C GS Parasitic capacity C between gate and back gate GB Because it is applied to, parasitic capacity C GS ,C GB A noise current flows through it. This noise current is then drawn to the microphone's capacitor C. MIC and gate-drain parasitic capacitance C GD The current flows into the input T of the impedance conversion circuit 100B. IN This becomes the noise voltage. Output T of the impedance conversion circuit 100B OUT The noise voltage is, input T IN The noise voltage of the gate-source voltage of PMOS transistor M1 and the noise voltage v noise_GS This is the sum of the two values. Output T OUT Noise voltage v no This is expressed by the following equation (4).

[0014]

number

[0015] v nFB This is the thermal noise obtained by converting the noise of the current detection circuit 6 and the feedback circuit 7 to the connection point of the drain of the PMOS transistor M1, r iDET This is the equivalent resistance of the current detection circuit 6. MIC >>C GS , C GB , G GD If so, the denominator of equation (4) is gm 2 However, capacitor C MIC The capacitance is small, on the order of pF, for example, 3pF. Therefore, the parasitic capacitance C GS , C GB , G GD The effect of cannot be ignored, and the denominator of equation (4) becomes small, resulting in the noise voltage v no There was a problem with it becoming too large. [Prior art documents] [Patent Documents]

[0016] [Patent Document 1] Special Publication No. 2024-518207 [Overview of the project] [Problems that the invention aims to solve]

[0017] This invention has been made in view of the above circumstances, and its purpose is to provide an impedance conversion circuit that reduces noise voltage. [Means for solving the problem]

[0018] To achieve the aforementioned objectives, the impedance conversion circuit according to the present invention is characterized by the following [1] to [7]. [1] In an impedance conversion circuit that receives a signal at high impedance to prevent attenuation of the input signal from the microphone's capacitor and outputs it at low impedance to drive the load, A first transistor with its gate connected to the input and its source connected to the output, A first current source that supplies current to the source of the first transistor, The system includes a back gate potential supply circuit that converts the source potential of the first transistor and supplies it as the back gate potential of the first transistor, It is an impedance conversion circuit. [2] In the impedance conversion circuit described in [1], The aforementioned back gate potential supply circuit is A second transistor that converts the potential of the source of the first transistor into current, A first resistor connected in series with the second transistor, A current mirror circuit that folds back the current flowing through the first resistor, It has a second resistor through which the current folded back by the current mirror circuit flows, The back gate potential is adjustable according to the ratio of the first resistor and the second resistor. It is an impedance conversion circuit. [3] In the impedance conversion circuit described in [2], The aforementioned back gate potential supply circuit is The current-voltage conversion circuit has the second resistor and converts the current folded back from the current mirror circuit into a voltage and supplies it as the back gate potential, It is an impedance conversion circuit. [4] In the impedance conversion circuit described in [3], The current-voltage conversion circuit has a third transistor connected in series with the second resistor and connected in diode mode. It is an impedance conversion circuit. [5] In the impedance conversion circuit described in [3], The back gate potential supply circuit further includes a second current source that supplies current to the current-voltage conversion circuit. It is an impedance conversion circuit. [6] In the impedance conversion circuit described in [2], The aforementioned back gate potential supply circuit is A fourth transistor that level-shifts the voltage across the second resistor, The fourth transistor is connected in series with a third current source, The voltage between the fourth transistor and the third current source is supplied as the back gate potential of the first transistor. It is an impedance conversion circuit. [7] In the impedance conversion circuit described in any one of items [1] to [6], A current detection circuit for detecting the current flowing through the first transistor, The system includes a feedback circuit that controls the current flowing through the first current source according to the detection result of the current detection circuit, It is an impedance conversion circuit. [Effects of the Invention]

[0019] According to the present invention, an impedance conversion circuit that reduces noise voltage can be provided.

[0020] The present invention has been briefly described above. Furthermore, the details of the present invention will be further clarified by referring to the attached drawings and reading through the embodiments for carrying out the invention described below (hereinafter referred to as "embodiments"). [Brief explanation of the drawing]

[0021] [Figure 1] Figure 1 is a circuit diagram showing an impedance conversion circuit in the first embodiment. [Figure 2] Figure 2 is a circuit diagram showing the details of the current-voltage conversion circuit shown in Figure 1. [Figure 3] Figure 3 is a circuit diagram showing details of a current-voltage conversion circuit in another embodiment. [Figure 4] Figure 4 is a circuit diagram showing details of a current-voltage conversion circuit in another embodiment. [Figure 5] Figure 5 is a circuit diagram showing details of a current-voltage conversion circuit in another embodiment. [Figure 6] Figure 6 is a circuit diagram showing the impedance conversion circuit in the second embodiment. [Figure 7] Figure 7 is a circuit diagram showing an example of a conventional impedance conversion circuit. [Figure 8] Figure 8 is a circuit diagram showing an example of a conventional impedance conversion circuit. [Modes for carrying out the invention]

[0022] Specific embodiments of the present invention will be described below with reference to the figures.

[0023] (First Embodiment) The impedance conversion circuit 1 of this embodiment uses the capacitor C of the condenser microphone.MIC This circuit receives the signal with high impedance to prevent attenuation of the signal output from the source, and outputs it with low impedance to drive load 2. Capacitor C MIC This is the connection between ground G1 and the input T of impedance conversion circuit 1. IN It is connected between the two. However, in the case of a MEMS microphone, a DC potential (e.g., 10V) is applied to ground G1 instead of 0V.

[0024] The impedance conversion circuit 1 comprises a PMOS transistor M1 as the first transistor, a current source 4 as the first current source, a DC bias circuit 5, a current detection circuit 6, a feedback circuit 7, and a back gate potential supply circuit 8.

[0025] The PMOS transistor M1 performs impedance conversion. The gate of the PMOS transistor M1 is connected to the input T IN Connected to the source, output T OUT It is connected to the current source 4. Current source 4 supplies current to the source of PMOS transistor M1. Current source 4 is connected to the power supply voltage V DD Power supply terminal T VDD It is connected between this and the source of the PMOS transistor M1.

[0026] The DC bias circuit 5 supplies a DC bias voltage to the gate of the PMOS transistor M1. The DC bias circuit 5 is connected between the gate of the PMOS transistor M1 and ground G2. In this embodiment, ground G2 is supplied with 0V. In this embodiment, the DC bias circuit 5 is composed of diodes D1 and D2 connected in parallel and inverse to each other. However, the DC bias circuit 5 is not limited to this and may be composed of resistors.

[0027] The current detection circuit 6 detects the drain current of the PMOS transistor M1. The current detection circuit 6 is connected between the drain of the PMOS transistor M1 and ground G2. The feedback circuit 7 controls the current source 4 according to the detection result of the current detection circuit 6, thereby controlling the drain current of the PMOS transistor M1 to a constant value.

[0028] The current value I4 of current source 4 is the sum of the current flowing through load 2 and the drain current of PMOS transistor M1, and is therefore expressed by the following equation (5).

[0029]

number

[0030] Here, V INp V is the amplitude level (0-peak) of the input signal. GS1 R is the gate-source voltage of PMOS transistor M1. L I is the equivalent resistance of load 2. D1 V is the drain current value of the PMOS transistor M1. From equation (5), the amplitude level V of the input signal is INp It can be seen that as V increases, the current value I4 also increases. In the configuration shown in Figure 7, which does not have the current detection circuit 6 and the feedback circuit 7, the amplitude level of the input signal V INp The current value I4 needs to be set so that current flows to load 2 and PMOS transistor M1 even when the amplitude level V of the input signal is at its maximum. INp When the value is less than the maximum value, current is wasted.

[0031] In the configuration shown in Figure 1, the PMOS transistor M1 controls the amplitude level of the input signal V. INp As it increases, the drain current value I D1 The drain current value I becomes smaller. D1 When V becomes small, the feedback circuit 7 controls the current value I4 of the current source 4 to increase. In other words, by providing the current detection circuit 6 and the feedback circuit 7, the current of the current source 4 is increased only when necessary, thereby reducing current consumption. When the PMOS transistor M1 is operated in the saturation region, the gate-source voltage V GS1 This is given by equation (6) below.

[0032]

number

[0033] Here, μ is the electron mobility, C OX is gate oxide film capacity / unit area, L is gate channel length, W is gate channel width, V TH This is the threshold voltage. From equation (6), the drain current value I D1 When this changes, the gate-source voltage V GS1 It can be seen that the amplitude level V of the input signal changes. In the configuration shown in Figure 7, which lacks the current detection circuit 6 and the feedback circuit 7, INp When this changes, the drain current value I D1 Because the gate-source voltage V changes, GS1 The output T changes. OUT The AC voltage level is V O Therefore, AC voltage level V O This is expressed by the following equation (7).

[0034]

number

[0035] Here, ΔV GS1 The drain current value I D1 Due to the change, the gate-source voltage V of the PMOS transistor M1 changes. GS1 This is the amount of change. In the configuration shown in Figure 1, the drain current value I is determined by the feedback circuit 7. D1 Because the amount of change is small, AC voltage level V O This is approximated by equation (8) below.

[0036]

number

[0037] In other words, because the output signal is output in a form similar to the input signal, the distortion rate also improves.

[0038] Next, the back gate potential supply circuit 8 will be described. The back gate potential supply circuit 8 is a circuit that supplies an appropriate voltage to the back gate of the PMOS transistor M1 according to the source potential. As mentioned above, since the source and back gate have a diode structure, the voltage supplied to the back gate is such that the back gate potential is greater than or equal to the source potential, or even if the back gate potential is less than or equal to the source potential, the current flowing from the source to the back gate is within an acceptable range. The back gate potential supply circuit 8 converts the source potential of the PMOS transistor M1 and supplies it as the back gate potential. That is, if the source potential of the PMOS transistor M1 increases, the back gate potential of the back gate potential supply circuit 8 also increases.

[0039] In this embodiment, the back gate of the PMOS transistor M1 is not connected to the source, but is connected to the back gate potential supply circuit 8. This allows the back gate to be isolated from the source. In this case, the thermal noise current can be expressed by the following equation (9).

[0040]

number

[0041] Here, g mb This is the transconductance of the PMOS transistor M1 due to the substrate voltage, v noise_BS This is the noise voltage of the back gate-source voltage. The thermal noise current i in equations (3) and (9) above is... noise It is constant. Therefore, in this embodiment, the noise voltage v of the gate-source voltage of the PMOS transistor M1 noise_GS The parasitic capacity C becomes smaller. GS Through capacitor C MIC and parasitic capacity C GD The noise current flowing through it also decreases. In other words, the noise voltage v noise_GS The capacitance C becomes smaller. MIC and parasitic capacity C GD The noise current flowing through it also becomes smaller, so the noise voltage v no It can be seen that it can be made smaller.

[0042] Next, the details of the back gate potential supply circuit 8 will be described. The back gate potential supply circuit 8 comprises an NMOS transistor M2 as a second transistor, a resistor R1 as a first resistor, a current mirror circuit 81, a current source 82 as a second current source, and a current-voltage conversion circuit 83. In this embodiment, the back gate potential supply circuit 8 can adjust the back gate potential according to the resistance ratio of the resistor R1 and the resistor R2 in the current-voltage conversion circuit 83, which will be described later.

[0043] The gate of the NMOS transistor M2 is connected to the source of the PMOS transistor M1, and the source of M2 is connected to ground G2 via a resistor R1, which will be described later. Resistor R1 is connected between the source of the NMOS transistor M2 and ground G2. The NMOS transistor M2 converts the source potential of the PMOS transistor M1 into current and flows through resistor R1.

[0044] The current mirror circuit 81 has PMOS transistors M41 and M42. The drain of PMOS transistor M41 is connected to the drain of NMOS transistor M2, and the source is connected to the power supply terminal T VDD The gate and drain of the PMOS transistor M42 are connected to the power supply terminal T. The drain of the PMOS transistor M42 is connected to the current-voltage conversion circuit 83, which will be described later, and the source is connected to the power supply terminal T. VDD It is connected to the gate, and its gate is connected to the gate-drain of PMOS transistor M41. A current flows through PMOS transistor M41 corresponding to the source potential of PMOS transistor M1 flowing through resistor R1, and this current is folded back into the drain current of PMOS transistor M42 and supplied to the current-voltage conversion circuit 83, which will be described later.

[0045] The current source 82 is connected to the power supply terminal T VDDIt is connected between the PMOS transistor M42 and the connection point of the current-voltage conversion circuit 83. The current source 82 supplies current to the current-voltage conversion circuit 83. The current-voltage conversion circuit 83 converts the sum of the current supplied from the current mirror circuit 81 and the current supplied from the current source 82 into a voltage and supplies it to the back gate of the PMOS transistor M1.

[0046] As shown in Figure 2, the current-voltage conversion circuit 83 includes a PMOS transistor M31 as a third transistor connected in series between the drain of PMOS transistor M42 and ground G2, and a resistor R2 as a second resistor. PMOS transistor M31 is connected in a so-called diode configuration, with its gate and drain connected. In the example shown in Figure 2, the source of PMOS transistor M31 is connected to the drain of PMOS transistor M42, and its gate and drain are connected to resistor R2. Resistor R2 is connected between the gate and drain of PMOS transistor M31 and ground G2.

[0047] With the above configuration, as the source potential of the PMOS transistor M1 increases, the current flowing through the NMOS transistor M2 increases, and the current supplied to the current-voltage conversion circuit 83 increases. When the current supplied to the current-voltage conversion circuit 83 increases, the voltage supplied to the back gate of the PMOS transistor M1 increases.

[0048] In this embodiment, the resistance value of resistor R2 is set to be smaller than the resistance value of resistor R1. Even with a small resistance value of resistor R2, a diode-connected PMOS transistor M31 and a current source 82 are provided to ensure an appropriate back gate potential relative to the source potential of PMOS transistor M1.

[0049] Noise voltage v of impedance conversion circuit 1 in this embodiment no It can be expressed by the following equations (10), (11), and (12).

[0050]

number

[0051]

Number

[0052]

Number

[0053] Here, g m2 is the transconductance of NMOS transistor M2, R1 is the resistance value of resistor R1, R2 is the resistance value of resistor R2, r D is the small-signal impedance of PMOS transistor M31, and v nBIAS is the noise voltage obtained by converting the noise of NMOS transistor M2, resistor R1, current mirror circuit 81, current source 82, and current-voltage conversion circuit 83 to the back gate of PMOS transistor M1.

[0054] Next, compare the first terms on the right sides of equations (4) and (10) that represent the noise of the conventional circuit. By separating the back gate of PMOS transistor M1 from the source, the term of g mb in the denominator increases, and it can be seen that the noise voltage V no of the first term can be reduced.

[0055] Also, the smaller the resistance value R2 is compared to the resistance value R1, the larger A shown in equation (11) becomes, and the coefficients of g m and g mb become larger, so it can be seen that the noise voltage v no of the first term can be reduced. The noise voltage v no of the impedance conversion circuit 1 of the present embodiment increases by the second term on the right side of equation (10), and the noise level becomes higher, but in many cases, the noise of the first term is dominant. Therefore, it can be seen that the noise voltage V no can be reduced.

[0056] When the back-gate potential of the PMOS transistor M1 drops below the source potential, the diode formed by the source and the back-gate is forward-biased, so it is necessary to apply an appropriate back-gate potential. Let the voltage obtained by subtracting the back-gate potential from the source potential of the PMOS transistor M1 be V SB Then, V SB is expressed by the following formula (13).

[0057]

Equation

[0058] Here, V GS2 is the gate-source voltage of the NMOS transistor M2, V GS31 is the gate-source voltage of the PMOS transistor M31, and I 82 is the current value of the current source 82. When R2 is decreased, V SB increases, and the source and the back-gate are forward-biased. Therefore, the resistance values R1 and R2 of the resistors R1 and R2 are set so that an appropriate back-gate potential is applied.

[0059] Also, the influence of the noise of the back-gate potential supply circuit 8 is the second term on the right side of formula (10). Looking at the coefficient of v nBIAS , it can be seen that the denominator is larger than the numerator by (C MIN +C GD )G ... GS Therefore, the noise of v nBIAS [[ID=зо]]is reduced by this coefficient. By designing considering the balance between the first term and the second term on the right side of formula (10), the output noise of the impedance conversion circuit 1 can be reduced.

[0060] Note that the current-voltage conversion circuit 83 is not limited to the example shown in FIG. 2. Instead of the current-voltage conversion circuit 83 shown in FIG. 2, the current-voltage conversion circuit 83B shown in FIG. 3 may be employed. The current-voltage conversion circuit 83B shown in FIG. 3 has a PMOS transistor M31 and a resistor R2, similar to the current-voltage conversion circuit 83.

[0061] PMOS transistor M31 has its gate and drain connected to ground G2, and its source connected to resistor R2. Resistor R2 is connected between the source of PMOS transistor M31 and the drain of PMOS transistor M42.

[0062] Alternatively, instead of the current-voltage conversion circuit 83 shown in Figure 2, the current-voltage conversion circuits 83C and 83D shown in Figures 4 and 5 may be used. The current-voltage conversion circuits 83C and 83D shown in Figures 4 and 5 may also be circuits having an NMOS transistor M32 as a third transistor connected in series between the drain of the PMOS transistor M42 and ground G2, and a resistor R2. The NMOS transistor M32 is connected gate-drain, in a so-called diode connection. In the example shown in Figure 4, the drain-gate of the NMOS transistor M32 is connected to the drain of the PMOS transistor M42, and the source is connected to resistor R2. Resistor R2 is connected between the source of the NMOS transistor M32 and ground G2.

[0063] In the example shown in Figure 5, the NMOS transistor M32 has its source connected to ground G2 and its gate and drain connected to resistor R2. Resistor R2 is connected between the drain of the PMOS transistor M42 and the gate and drain of the NMOS transistor M32.

[0064] When the current-voltage conversion circuits 83C and 83D shown in Figures 4 and 5 are adopted, the r in equation (10) D This changes to the small signal impedance of the NMOS transistor M32. SB The expression (13) that represents V GS31 The gate-source voltage V of the NMOS transistor M32 GS32 Change it.

[0065] With the above configuration, the noise voltage v no This is reduced by separating the back gate of the PMOS transistor M1 from the source. Furthermore, by making the value of resistor R2 smaller compared to resistor R1, the noise voltage v noThis can be made smaller. On the other hand, the back gate potential of the PMOS transistor M1 needs to be at an appropriate potential relative to the source potential, but if the value of resistor R2 is made smaller compared to resistor R1, the back gate potential will decrease. This is because the noise voltage v no This contradicts the condition for reducing the noise voltage v. By appropriately selecting the ratio of resistors R1 and R2, the noise voltage v no This allows for the creation of small impedance conversion circuits.

[0066] (Second Embodiment) Next, the impedance conversion circuit 1B of the second embodiment will be described with reference to Figure 6. In Figure 6, parts equivalent to the impedance conversion circuit 1 shown in Figure 1, which was already described in the first embodiment, are denoted by the same reference numerals, and their detailed description is omitted.

[0067] As shown in the figure, the impedance conversion circuit 1B includes a PMOS transistor M1, a current source 4, a DC bias circuit 5, a current detection circuit 6, a feedback circuit 7, and a back gate potential supply circuit 8B. The PMOS transistor M1, current source 4, DC bias circuit 5, current detection circuit 6, and feedback circuit 7 are equivalent to those in the first embodiment described above, so a detailed explanation is omitted.

[0068] The back gate potential supply circuit 8B comprises an NMOS transistor M2, a resistor R1, a current mirror circuit 81, a resistor R2, a PMOS transistor M4 as a fourth transistor, and a current source 84 as a third current source. The NMOS transistor M2, resistor R1, and current mirror circuit 81 are equivalent to those in the first embodiment described above, so a detailed explanation is omitted.

[0069] Resistor R2 is connected between the drain of PMOS transistor M42 and ground G2. PMOS transistor M4 has its gate connected to the connection point between the drain of PMOS transistor M42 and resistor R2, its drain connected to ground G2, and its source connected to the back gate of PMOS transistor M1 and current source 84.

[0070] Similar to the first embodiment, a current flows through resistor R2 that fluctuates according to the source potential of PMOS transistor M1, and this current is converted into a voltage. PMOS transistor M4 and current source 84 are connected in series. The current from current source 84 keeps the gate-source voltage of PMOS transistor M4 constant. PMOS transistor M4 performs a level shift by adding the gate-source voltage to the voltage across resistor R2.

[0071] With the above configuration, when the source potential of the PMOS transistor M1 increases, the current flowing through the NMOS transistor M2 increases, and the voltage across resistor R2 increases. When the voltage across resistor R2 increases, the gate-source voltage of the PMOS transistor M4 is added to the voltage across resistor R2 and applied to the back gate.

[0072] In this embodiment, the resistance value of resistor R2 is set to be smaller than the resistance value of resistor R1.

[0073] Noise voltage V of impedance conversion circuit 1B in this embodiment no This can be expressed by the following equations (14) and (15).

[0074]

number

[0075]

number

[0076] Here, v nBIAS2This is the noise voltage obtained by converting the noise of the NMOS transistor M2, resistor R1, current mirror circuit 81, resistor R2, PMOS transistor M4, and current source 82 to the back gate of the PMOS transistor M1. In this circuit as well, the smaller the value of R2 is compared to R1, the smaller the noise level of the first term on the right-hand side of equation (14) can be. The noise level increases due to the second term on the right-hand side of equation (14), but in many cases the noise of the first term is dominant.

[0077] Similar to the first embodiment, the back gate potential of the PMOS transistor M1 is forward-biased when it falls below the source potential, so it is necessary to provide an appropriate potential. In this embodiment, the voltage obtained by subtracting the back gate potential from the source potential of the PMOS transistor M1 is V SB Therefore, V SB This is expressed by the following equation (16).

[0078]

number

[0079] Here, V GS4 This is the gate-source voltage of the PMOS transistor M4. When R2 is reduced, V SB The voltage increases, and the source and back gate are forward-biased. Therefore, the resistance values ​​of resistors R1 and R2 are set so that an appropriate back gate potential is provided.

[0080] With the above configuration, by making the value of resistor R2 smaller than that of resistor R1, the noise voltage v no This can reduce the noise voltage v. On the other hand, if the value of resistor R2 is reduced compared to resistor R1, the back gate potential of PMOS transistor M1 decreases. This reduces the noise voltage v. no This contradicts the condition for reducing the noise voltage v. By appropriately selecting the ratio of resistors R1 and R2, the noise voltage v no This allows for the creation of small impedance conversion circuits.

[0081] Furthermore, the present invention is not limited to the embodiments described above, and can be modified, improved, etc., as appropriate. In addition, the material, shape, dimensions, number, placement, etc. of each component in the embodiments described above are arbitrary and not limited, as long as they can achieve the present invention.

[0082] According to the embodiment described above, a current detection circuit 6 and a feedback circuit 7 were provided, but the invention is not limited to this. Providing the current detection circuit 6 and the feedback circuit 7 is not essential and may be omitted.

[0083] In the embodiments described above, a MOS (microelectronics-optical) transistor was used as the transistor, but it is not limited to this. Except for the first transistor, a bipolar transistor may be used as the transistor. In this case, the gate is read as the base, the source as the emitter, and the drain as the collector.

[0084] According to the embodiments described above, the current-voltage conversion circuits 83 and 83B had diode-connected PMOS transistors M31 and NMOS transistors M32, but are not limited to this. The PMOS transistors M31 and NMOS transistors M32 may be omitted.

[0085] Furthermore, although the current from the current source 82 was supplied to the current-voltage conversion circuit 83 in the embodiment described above, this is not the only configuration. The current source 82 may be omitted. [Explanation of Symbols]

[0086] 1,1B Impedance Conversion Circuit 4. Current source (first current source) 6. Current detection circuit 7 Feedback Circuit 8,8B Back gate potential supply circuit 81 Current Mirror Circuit 82 Current source (second current source) 83, 83B, 83C, 83D Current-Voltage Conversion Circuits 84. Current source (third current source) C MIC Capacitor M1 PMOS transistor (first transistor) M2 NMOS transistor (second transistor) M31 PMOS transistor (third transistor) M32 NMOS transistor (third transistor) M4 PMOS transistor (fourth transistor) R1 Resistor (First resistor) R2 Resistor (Second resistor)

Claims

1. In an impedance conversion circuit that receives a signal at high impedance to prevent attenuation of the input signal from the microphone's capacitor and outputs it at low impedance to drive the load, A first transistor with its gate connected to the input and its source connected to the output, A first current source that supplies current to the source of the first transistor, The system includes a back gate potential supply circuit that converts the source potential of the first transistor and supplies it as the back gate potential of the first transistor. Impedance conversion circuit.

2. In the impedance conversion circuit described in claim 1, The aforementioned back gate potential supply circuit is A second transistor that converts the potential of the source of the first transistor into current, A first resistor connected in series with the second transistor, A current mirror circuit that folds back the current flowing through the first resistor, It has a second resistor through which the current folded back by the current mirror circuit flows, The back gate potential is adjustable according to the ratio of the first resistor and the second resistor. Impedance conversion circuit.

3. In the impedance conversion circuit described in claim 2, The aforementioned back gate potential supply circuit is The current-voltage conversion circuit has the second resistor and converts the current folded back from the current mirror circuit into a voltage and supplies it as the back gate potential. Impedance conversion circuit.

4. In the impedance conversion circuit described in claim 3, The current-voltage conversion circuit has a third transistor connected in series with the second resistor and connected in diode mode. Impedance conversion circuit.

5. In the impedance conversion circuit described in claim 3, The back gate potential supply circuit further includes a second current source that supplies current to the current-voltage conversion circuit. Impedance conversion circuit.

6. In the impedance conversion circuit described in claim 2, The aforementioned back gate potential supply circuit is A fourth transistor that level-shifts the voltage across the second resistor, The fourth transistor is connected in series with a third current source, The voltage between the fourth transistor and the third current source is supplied as the back gate potential of the first transistor. Impedance conversion circuit.

7. In the impedance conversion circuit according to any one of claims 1 to 6, A current detection circuit for detecting the current flowing through the first transistor, The system includes a feedback circuit that controls the current flowing through the first current source according to the detection result of the current detection circuit, Impedance conversion circuit.

Images