Impedance conversion circuit
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- NISSHINBO MICRO DEVICES INC
- Filing Date
- 2024-12-23
- Publication Date
- 2026-07-03
AI Technical Summary
Conventional impedance conversion circuits in microphones suffer from high noise voltage due to the parasitic capacitance between the gate and back gate of PMOS transistors, which is exacerbated by the diode structure and thermal noise current, leading to increased noise voltage in the output signal.
The impedance conversion circuit employs a back gate potential supply circuit with adjustable resistors and transistors to isolate the back gate from the source, using a series connection of resistors and transistors to level-shift the voltage and control the back gate potential, combined with a current detection and feedback circuit to manage current flow, thereby reducing noise voltage.
The proposed solution effectively reduces noise voltage by minimizing the parasitic capacitance and thermal noise current, resulting in a more stable and low-noise output signal.
Smart Images
Figure 2026111104000001_ABST
Abstract
Description
[Technical Field]
[0001] This invention relates to an impedance conversion circuit. [Background technology]
[0002] With the increasing number of electronic devices that use voice input, such as smartphones, PCs, and smart speakers, the demand for microphones is on the rise. These electronic devices are becoming smaller, and battery-powered devices require low power consumption. Therefore, the required characteristics of microphones are, firstly, low noise for acoustic performance, secondly, small size, and thirdly, low power consumption.
[0003] Figure 4 shows the configuration of a conventional impedance conversion circuit 100 (for example, Patent Document 1). The impedance conversion circuit 100 is a microphone capacitor C MIC This circuit receives the signal with high impedance to prevent attenuation of the signal output from the device, and outputs it with low impedance to drive the load 2. The impedance conversion circuit 100 includes a PMOS transistor M1 that performs impedance conversion, a current source 4 that supplies current to the PMOS transistor M1, and a DC bias circuit 5 that applies a DC bias to the PMOS transistor M1.
[0004] Next, Figure 5 shows the configuration of a conventional impedance conversion circuit 100B designed to reduce current consumption. In addition to the PMOS transistor M1, current source 4, and DC bias circuit 5, the impedance conversion circuit 100B includes a current detection circuit 6 that detects the drain current of the PMOS transistor M1, and a feedback circuit 7 that controls the current source 4 according to the detection result of the current detection circuit 6.
[0005] By providing the current detection circuit 6 and the feedback circuit 7, only the amount of current required for operation can be supplied to the PMOS transistor M1, thereby achieving low current consumption. Furthermore, the operating current of the PMOS transistor M1 can be kept constant, preventing changes in the gate-source potential. Therefore, the input signal is output directly, and distortion reduction can also be improved.
[0006] Since the source of the PMOS transistor M1 is a P-type semiconductor and the back gate is an N-type semiconductor, it has a diode structure. Due to this diode structure, the current I flowing from the source to the back gate is BG represented by the following equation (1).
[0007]
Equation
[0008] Here, V SB is the forward voltage between the source (P-type) and the back gate (N-type), I S is the reverse saturation current, and V T is the thermal voltage. Therefore, the back gate current I BG increases exponentially with V SB . The conventional impedance conversion circuit 100B shown in FIG. 5 connects the back gate of the PMOS transistor M1 to the source to prevent current from flowing from the source to the back gate by making V SB zero.
[0009] It is known that the thermal noise current generated in the PMOS transistor M1 in FIG. 5 is generally represented by equation (2).
[0010]
Equation
[0011] Here, k is the Boltzmann constant, T is the absolute temperature, and gm is the mutual conductance of the PMOS transistor M1. The thermal noise current and the noise voltage v noise_GS between the gate and the source have the relationship shown in the following equation (3).
[0012]
Equation
[0013] Noise voltage v between gate and source noise_GS This is the gate-source parasitic capacitance C GS Parasitic capacity C between gate and back gate GB Because it is applied to, parasitic capacity C GS ,C GB A noise current flows through it. This noise current is then drawn to the microphone's capacitor C. MIC and gate-drain parasitic capacitance C GD The current flows into the input T of the impedance conversion circuit 100B. IN This becomes the noise voltage. Output T of the impedance conversion circuit 100B OUT The noise voltage is, input T IN The noise voltage of the gate-source voltage of PMOS transistor M1 and the noise voltage v noise_GS This is the sum of the two values. Output T OUT Noise voltage v no This is expressed by the following equation (4).
[0014]
number
[0015] v nFB This is the thermal noise obtained by converting the noise of the current detection circuit 6 and the feedback circuit 7 to the connection point of the drain of the PMOS transistor M1, r iDET This is the equivalent resistance of the current detection circuit 6. MIC >>C GS , C GB , G GD If so, the denominator of equation (4) is gm 2 However, capacitor C MIC The capacitance is small, on the order of pF, for example, 3pF. Therefore, the parasitic capacitance C GS , C GB , G GD The effect of cannot be ignored, and the denominator of equation (4) becomes small, resulting in the noise voltage v no There was a problem with it becoming too large. [Prior art documents] [Patent Documents]
[0016] [Patent Document 1] Special Publication No. 2024-518207 [Overview of the Initiative] [Problems that the invention aims to solve]
[0017] This invention has been made in view of the above circumstances, and its purpose is to provide an impedance conversion circuit that reduces noise voltage. [Means for solving the problem]
[0018] To achieve the aforementioned objectives, the impedance conversion circuit according to the present invention is characterized by the following [1] to [7]. [1] In an impedance conversion circuit that receives a signal at high impedance to prevent attenuation of the input signal from the microphone's capacitor and outputs it at low impedance to drive the load, A first transistor with its gate connected to the input and its source connected to the output, A first current source that supplies current to the source of the first transistor, The system includes a back gate potential supply circuit that converts the potential of the source of the first transistor and supplies it as the back gate potential of the first transistor, The aforementioned back gate potential supply circuit is It has a first resistor and a second resistor connected in series with respect to the back gate potential, which is adjustable according to the ratio of the first resistor and the second resistor. It is an impedance conversion circuit. [2] In the impedance conversion circuit described in [1], The first resistor and the second resistor divide the potential of the source of the first transistor. The aforementioned back gate potential supply circuit is A second transistor that level-shifts the voltage divided by the first and second resistors, The device further comprises a second current source connected in series with the second transistor, The voltage between the second transistor and the second current source is supplied as the back gate potential of the first transistor. It is an impedance conversion circuit. [3] In the impedance conversion circuit described in [1], The aforementioned back gate potential supply circuit is A third transistor converts the potential of the source of the first transistor into current and supplies it to the first resistor and the second resistor, A fourth transistor that level-shifts the voltage between the first resistor and the second resistor, The system further comprises a third current source connected in series with the fourth transistor, The voltage between the fourth transistor and the third current source is supplied as the back gate potential of the first transistor. It is an impedance conversion circuit. [4] In the impedance conversion circuit described in [1], The aforementioned back gate potential supply circuit is A fifth transistor that level-shifts the potential of the source of the first transistor, The system further comprises a fourth current source connected in series with the fifth transistor, The first resistor and the second resistor divide the voltage between the fifth transistor and the fourth current source, and supply the divided voltage to the back gate of the first transistor. It is an impedance conversion circuit. [5] In the impedance conversion circuit described in [4], The aforementioned back gate potential supply circuit is The present invention further comprises a diode connected between the fifth transistor and the fourth current source. It is an impedance conversion circuit. [6] In the impedance conversion circuit described in [5], Multiple diodes are connected in series. It is an impedance conversion circuit. [7] In the impedance conversion circuit described in any one of items [1] to [6], A current detection circuit for detecting the current flowing through the first transistor, The system includes a feedback circuit that controls the current flowing through the first current source according to the detection result of the current detection circuit, It is an impedance conversion circuit. [Effects of the Invention]
[0019] According to the present invention, an impedance conversion circuit that reduces noise voltage can be provided.
[0020] The present invention has been briefly described above. Furthermore, the details of the present invention will be further clarified by referring to the attached drawings and reading through the embodiments for carrying out the invention described below (hereinafter referred to as "embodiments"). [Brief explanation of the drawing]
[0021] [Figure 1] Figure 1 is a circuit diagram showing an impedance conversion circuit in the first embodiment. [Figure 2] Figure 2 is a circuit diagram showing the impedance conversion circuit in the second embodiment. [Figure 3] Figure 3 is a circuit diagram showing the impedance conversion circuit in the third embodiment. [Figure 4] Figure 4 is a circuit diagram showing an example of a conventional impedance conversion circuit. [Figure 5] Figure 5 is a circuit diagram showing an example of a conventional impedance conversion circuit. [Modes for carrying out the invention]
[0022] Specific embodiments of the present invention will be described below with reference to the figures.
[0023] (First Embodiment) The impedance conversion circuit 1 of this embodiment uses the capacitor C of the condenser microphone. MIC This circuit receives the signal with high impedance to prevent attenuation of the signal output from the source, and outputs it with low impedance to drive load 2. Capacitor C MIC This is the connection between ground G1 and the input T of impedance conversion circuit 1. IN It is connected between the two. However, in the case of a MEMS microphone, a DC potential (e.g., 10V) is applied to ground G1 instead of 0V.
[0024] The impedance conversion circuit 1 comprises a PMOS transistor M1 as the first transistor, a current source 4 as the first current source, a DC bias circuit 5, a current detection circuit 6, a feedback circuit 7, and a back gate potential supply circuit 8.
[0025] The PMOS transistor M1 performs impedance conversion. The gate of the PMOS transistor M1 is connected to the input T IN Connected to the source, output T OUT It is connected to the current source 4. Current source 4 supplies current to the source of PMOS transistor M1. Current source 4 is connected to the power supply voltage V DD Power supply terminal T VDD It is connected between this and the source of the PMOS transistor M1.
[0026] The DC bias circuit 5 supplies a DC bias voltage to the gate of the PMOS transistor M1. The DC bias circuit 5 is connected between the gate of the PMOS transistor M1 and ground G2. In this embodiment, ground G2 is supplied with 0V. In this embodiment, the DC bias circuit 5 is composed of diodes D1 and D2 connected in parallel and inverse to each other. However, the DC bias circuit 5 is not limited to this and may be composed of resistors.
[0027] The current detection circuit 6 detects the drain current of the PMOS transistor M1. The current detection circuit 6 is connected between the drain of the PMOS transistor M1 and ground G2. The feedback circuit 7 controls the current source 4 according to the detection result of the current detection circuit 6, thereby controlling the drain current of the PMOS transistor M1 to a constant value.
[0028] The current value I4 of current source 4 is the sum of the current flowing through load 2 and the drain current of PMOS transistor M1, and is therefore expressed by the following equation (5).
[0029]
number
[0030] Here, V INp V is the amplitude level (0-peak) of the input signal. GS1 R is the gate-source voltage of PMOS transistor M1. L I is the equivalent resistance of load 2. D1 V is the drain current value of the PMOS transistor M1. From equation (5), the amplitude level V of the input signal is INp It can be seen that as V increases, the current value I4 also increases. In the configuration shown in Figure 4, which does not have the current detection circuit 6 and the feedback circuit 7, the amplitude level of the input signal V INp The current value I4 needs to be set so that current flows to load 2 and PMOS transistor M1 even when the amplitude level V of the input signal is at its maximum. INp When the value is less than the maximum value, current is wasted.
[0031] In the configuration shown in Figure 1, the PMOS transistor M1 controls the amplitude level of the input signal V. INp As it increases, the drain current value I D1 The drain current value I becomes smaller. D1When V becomes small, the feedback circuit 7 controls the current value I4 of the current source 4 to increase. In other words, by providing the current detection circuit 6 and the feedback circuit 7, the current of the current source 4 is increased only when necessary, thereby reducing current consumption. When the PMOS transistor M1 is operated in the saturation region, the gate-source voltage V GS1 This is given by equation (6) below.
[0032]
number
[0033] Here, μ is the electron mobility, C OX is gate oxide film capacity / unit area, L is gate channel length, W is gate channel width, V TH This is the threshold voltage. From equation (6), the drain current value I D1 When this changes, the gate-source voltage V GS1 It can be seen that the amplitude level V of the input signal changes. In the configuration shown in Figure 4, which lacks the current detection circuit 6 and the feedback circuit 7, INp When this changes, the drain current value I D1 Because the gate-source voltage V changes, GS1 The output T changes. OUT The AC voltage level is V O Therefore, AC voltage level V O This is expressed by the following equation (7).
[0034]
number
[0035] Here, ΔV GS1 The drain current value I D1 Due to the change, the gate-source voltage V of the PMOS transistor M1 changes. GS1 This is the amount of change. In the configuration shown in Figure 1, the drain current value I is determined by the feedback circuit 7. D1 Because the amount of change is small, AC voltage level V O This is approximated by equation (8) below.
[0036]
number
[0037] In other words, because the output signal is output in a form similar to the input signal, the distortion rate also improves.
[0038] Next, the back gate potential supply circuit 8 will be described. The back gate potential supply circuit 8 is a circuit that supplies an appropriate voltage to the back gate of the PMOS transistor M1 according to the source potential. As mentioned above, since the source and back gate have a diode structure, the circuit supplies voltage to the back gate so that the back gate potential is greater than or equal to the source potential, or so that even if the back gate potential is less than or equal to the source potential, the current flowing from the source to the back gate is within an acceptable range. The back gate potential supply circuit 8 supplies the back gate potential which is a conversion of the source potential of the PMOS transistor M1. That is, if the source potential of the PMOS transistor M1 increases, the back gate potential of the back gate potential supply circuit 8 also increases.
[0039] In this embodiment, the back gate of the PMOS transistor M1 is not connected to the source, but is connected to the back gate potential supply circuit 8. This allows the back gate to be isolated from the source. In this case, the thermal noise current can be expressed by the following equation (9).
[0040]
number
[0041] Here, g mb This is the transconductance of the PMOS transistor M1 due to the substrate voltage, v noise_BS This is the noise voltage of the back gate-source voltage. The thermal noise current i in equations (3) and (9) above is... noise It is constant. Therefore, in this embodiment, the noise voltage v of the gate-source voltage of the PMOS transistor M1 noise_GS The parasitic capacity C becomes smaller. GSThrough capacitor C MIC and parasitic capacity C GD The noise current flowing through it also decreases. In other words, the noise voltage v noise_GS The capacitance C becomes smaller. MIC and parasitic capacity C GD The noise current flowing through it also becomes smaller, so the noise voltage v no It can be made smaller.
[0042] Next, the details of the back gate potential supply circuit 8 will be described. The back gate potential supply circuit 8 comprises a resistor R1 as a first resistor, a resistor R2 as a second resistor, a PMOS transistor M2 as a second transistor, and a current source 81 as a second current source.
[0043] Resistors R1 and R2 are connected in series, and the back gate potential can be adjusted according to their resistance ratio. In this embodiment, resistors R1 and R2 divide the source potential of the PMOS transistor M1. Resistors R1 and R2 are connected in series between the source of the PMOS transistor M1 and ground G2, and output a voltage obtained by dividing the source potential from their connection point.
[0044] The drain of PMOS transistor M2 is connected to ground G2, and its gate is connected to the connection point of resistors R1 and R2, and is supplied with a voltage obtained by dividing the source potential of PMOS transistor M1.
[0045] The current source 81 is connected to the power terminal T VDDIt is connected between the source of PMOS transistor M2 and the current source 81, and is connected in series with PMOS transistor M2. The gate-source voltage of PMOS transistor M2 is kept constant by the current from the current source 81. The voltage at the connection point between PMOS transistor M2 and current source 81 is supplied to the back gate of PMOS transistor M1. In other words, the level shift is performed by adding the gate-source voltage of PMOS transistor M2 to the voltage divider of the source voltage of PMOS transistor M1. With the above configuration, as the source potential of PMOS transistor M1 increases, the voltage divider voltage across resistors R1 and R2 increases. When the voltage divider voltage across resistors R1 and R2 increases, the voltage supplied to the back gate of PMOS transistor M1 increases.
[0046] Noise voltage v of impedance conversion circuit 1 in this embodiment no It can be expressed by the following equations (10), (11), and (12).
[0047]
number
[0048]
number
[0049]
number
[0050] Here, R1 is the resistance value of resistor R1, R2 is the resistance value of resistor R2, v nBIAS This is the noise voltage obtained by converting the noise of resistors R1 and R2, the noise of PMOS transistor M2 and current source 81, to the back gate of PMOS transistor M1.
[0051] Next, we compare the first term on the right-hand side of equations (4) and (10), which represent the noise of the conventional circuit. By separating the back gate of the PMOS transistor M1 from the source, g is added to the denominator. mb The number of terms increases, and as a result, the noise voltage v of the first termno It can be seen that it can be made smaller.
[0052] Also, the smaller the resistance value R2 is compared to the resistance value R1, the larger the A shown in Equation (11) becomes, and g m , g mb Since the coefficient of becomes larger, it can be seen that the noise voltage v of the first term can be made smaller. The noise voltage v of the impedance conversion circuit 1 of this embodiment no Although the noise level increases by the second term on the right side of Equation (10), the noise of the first term is dominant in many cases. Therefore, it can be seen that the noise voltage v no can be reduced. no
[0053] Note that when the back gate potential of the PMOS transistor M1 drops below the source potential, the diode composed of the source and the back gate is forward-biased, so it is necessary to apply an appropriate back gate potential. If the voltage obtained by subtracting the back gate potential from the source potential of the PMOS transistor M1 is V SB , then V SB is represented by the following Equation (13).
[0054]
Equation
[0055] Here, V GS2 is the gate-source voltage of the PMOS transistor M2. When R2 is made smaller, V SB becomes larger, and the source and the back gate are forward-biased. Therefore, the current flowing from the source to the back gate becomes non-negligible. Therefore, the resistance values R1 and R2 of the resistors R1 and R2 are set so that an appropriate back gate potential is applied.
[0056] Also, the influence of the noise of the back gate potential supply circuit 8 is the second term on the right side of Equation (10). Looking at the coefficient of v nBIAS , the denominator is larger than the numerator by (C MIN + C GD )G GSIt can be seen that it is only large. Therefore, the noise of v nBIAS is reduced by this coefficient. By designing considering the balance between the first term and the second term on the right side of Equation (10), the output noise of the impedance conversion circuit 1 can be reduced.
[0057] According to the above configuration, the noise voltage v no is reduced by separating the back gate of the PMOS transistor M1 from the source. Furthermore, by making the value of the resistor R2 smaller than that of the resistor R1, the noise voltage v no can be made smaller. On the other hand, the back gate potential of the PMOS transistor M1 needs to be given an appropriate potential with respect to the source potential, but when the value of the resistor R2 is made smaller than that of the resistor R1, the back gate potential drops. This is contrary to the condition for reducing the noise voltage v no . By appropriately selecting the ratio of the resistor R1 and the resistor R2, an impedance conversion circuit with a small noise voltage v no can be realized.
[0058] (Second Embodiment) Next, the impedance conversion circuit 1B of the second embodiment will be described with reference to FIG. 2. In FIG. 2, for the parts equivalent to the impedance conversion circuit 1 shown in FIG. 1 already described in the above-described first embodiment, the same reference numerals are given and the detailed description thereof is omitted.
[0059] As shown in the figure, the impedance conversion circuit 1B includes a PMOS transistor M1, a current source 4, a DC bias circuit 5, a current detection circuit 6, a feedback circuit 7, and a back gate potential supply circuit 8B. Since the PMOS transistor M1, the current source 4, the DC bias circuit 5, the current detection circuit 6, and the feedback circuit 7 are equivalent to those in the above-described first embodiment, the detailed description thereof is omitted.
[0060] The back gate potential supply circuit 8B comprises an NMOS transistor M3 as a third transistor, resistors R1 and R2, a PMOS transistor M4 as a fourth transistor, and a current source 82 as a third current source. The gate of the NMOS transistor M3 is connected to the source of the PMOS transistor M1, and its drain is connected to the power supply terminal T VDD The source is connected to resistors R1 and R2, which are connected in series. Resistors R1 and R2 are connected in series between the source of NMOS transistor M3 and ground G2. NMOS transistor M3 converts the source potential of PMOS transistor M1 into current and supplies it to resistors R1 and R2.
[0061] The PMOS transistor M4 has its gate connected to the connection point of resistors R1 and R2, and its drain connected to ground G2. The current source 82 connects the source and power terminal T of the PMOS transistor M4. VDD It is connected between and in series with PMOS transistor M4. The gate-source voltage of PMOS transistor M4 is kept constant by the current from current source 82. The connection point between PMOS transistor M4 and current source 82 is connected to the back gate of PMOS transistor M1.
[0062] With the above configuration, as the source potential of PMOS transistor M1 increases, the current flowing through NMOS transistor M3 increases, and the voltage at the connection point of resistors R1 and R2 increases. The gate-source voltage of PMOS transistor M4 is added to the voltage at the connection point of resistors R1 and R2, and the resulting level-shifted voltage is supplied to the back gate of PMOS transistor M1. Therefore, as the voltage at the connection point of resistors R1 and R2 increases, the voltage supplied to the back gate of PMOS transistor M1 also increases.
[0063] Noise voltage v of impedance conversion circuit 1B in this embodiment no This can be expressed by the following equations (14) and (15).
[0064]
number
[0065]
number
[0066] Here, g m3 The transconductance of NMOS transistor M3 is v nBIAS2 This is the noise voltage obtained by converting the noise of the NMOS transistor M3, resistors R1 and R2, PMOS transistor M4, and current source 82 to the back gate of PMOS transistor M1.
[0067] Let's focus on D in equation (15). D in equation (15) can be transformed into equation (16) below.
[0068]
number
[0069] Next, we compare equation (16) with equation (11) of the first embodiment. When the resistance ratio of resistors R1 and R2 in the second embodiment is set to be the same as in the first embodiment, D in the second embodiment can be made larger than A in the first embodiment, and thus lower noise can be achieved. However, the source-back gate voltage V of the PMOS transistor M1 SB This is given by the following equation (17).
[0070]
number
[0071] Here, V GS3 This is the gate-source voltage of the NMOS transistor M3. Compared to equation (12) of the first embodiment, the back gate potential is lower by the amount of the second term on the right side, so the resistance value of resistor R2 must be increased. Therefore, as in the first embodiment, the resistance values R1 and R2 of resistors R1 and R2 must be set so that an appropriate back gate potential is provided.
[0072] With the above configuration, the noise voltage v no This can be reduced by making the value of resistor R2 smaller than that of resistor R1, and the noise reduction effect is improved by the NMOS transistor M3. On the other hand, making the value of resistor R2 smaller than that of resistor R1 lowers the back gate potential of PMOS transistor M1, and NMOS transistor M3 operates in a direction that further lowers the back gate potential of PMOS transistor M1. This reduces the noise voltage v no This contradicts the condition for reducing the noise voltage v. By appropriately selecting the ratio of resistors R1 and R2, the noise voltage v no This allows for the creation of small impedance conversion circuits.
[0073] (Third embodiment) Next, the impedance conversion circuit 1C of the third embodiment will be described with reference to Figure 3. In Figure 3, parts equivalent to the impedance conversion circuit 1 shown in Figure 1, which was already described in the first embodiment described above, are denoted by the same reference numerals, and their detailed description is omitted.
[0074] As shown in the figure, the impedance conversion circuit 1C comprises a PMOS transistor M1, a current source 4, a DC bias circuit 5, a current detection circuit 6, a feedback circuit 7, and a back gate potential supply circuit 8C. The PMOS transistor M1, current source 4, DC bias circuit 5, current detection circuit 6, and feedback circuit 7 are equivalent to those in the first embodiment described above, so a detailed explanation is omitted.
[0075] The back gate potential supply circuit 8C comprises a PMOS transistor M5 as the fifth transistor, a current source 83 as the fourth current source, a group of diodes 84, and resistors R1 and R2.
[0076] PMOS transistor M5 shifts the level of PMOS transistor M1 by adding the gate-source voltage of PMOS transistor M5 to the source potential of PMOS transistor M1. The gate of PMOS transistor M5 is connected to the source of PMOS transistor M1, and the drain is connected to ground G2. The current source 83 is connected to the power supply terminal T VDDIt is connected between the current source 83 and the source of the PMOS transistor M5. In other words, the current source 83 is connected in series with the PMOS transistor M5 and supplies current to the source of the PMOS transistor M5.
[0077] The diode group 84 consists of multiple diodes D8 connected in series with each other. The diode group 84 is inserted between the current source 83 and the source of the PMOS transistor M5. The cathodes of the multiple diodes D8 are connected toward the PMOS transistor M5 side, and the anodes are connected toward the current source 83 side. The potential at the connection point between the current source 83 and the diode group 84 is the source potential of the PMOS transistor M5 plus the forward voltage of the diode group 84.
[0078] Resistors R1 and R2 are connected in series between the connection point of the current source 83 and the diode group 84 and ground G2. The connection point of resistors R1 and R2 is connected to the back gate of PMOS transistor M1. As a result, resistors R1 and R2 divide the voltage obtained by adding the forward voltage of the diode group 84 to the source potential of PMOS transistor M5, and supply the divided voltage to the back gate of PMOS transistor M1.
[0079] In this embodiment, a diode group 84 is provided, and the voltage obtained by adding the forward voltage of diode D8 is divided by resistors R1 and R2 and supplied to the back gate of PMOS transistor M1. However, providing the diode group 84 is not essential. If the diode group 84 is not provided, resistors R1 and R2 are connected in series between the connection point between the source and current source 83 of PMOS transistor M5 and ground G2. The back gate of PMOS transistor M1 is supplied with a voltage obtained by adding the gate-source voltage of PMOS transistor M5 to the source potential of PMOS transistor M1 and dividing the voltage by resistors R1 and R2.
[0080] With the above configuration, as the source potential of the PMOS transistor M1 increases, the voltage at the connection point between the current source 83 and the PMOS transistor M5, or at the connection point between the current source 83 and the diode group 84, increases. When the voltage at the connection point between the current source 83 and the diode group 84 increases, the voltage divided by resistors R1 and R2 increases, and the voltage supplied to the back gate of the PMOS transistor M1 increases. Providing the diode group 84 as in this embodiment is preferable because it increases the voltage applied to the back gate of the PMOS transistor M1.
[0081] Noise voltage v of impedance conversion circuit 1C in this embodiment no This can be expressed by the following equations (18) and (19).
[0082]
number
[0083]
number
[0084] Here, v nBIAS3 V is the noise voltage obtained by converting the noise of the PMOS transistor M5, diode group 84, current source 83 and resistors R1 and R2 to the back gate voltage of the PMOS transistor M1. The first term of equation (18) is the same as the first term of equation (10) in the first embodiment. Source-back gate voltage V of PMOS transistor M1 SB This is expressed as shown in equation (20) below.
[0085]
number
[0086] Here, V GS5 V is the gate-source voltage of PMOS transistor M5. F is the forward voltage of diode D8, and N is the number of diodes D8 that make up diode group 84.
[0087] With the above configuration, the noise voltage v no This can be reduced by making the value of resistor R2 smaller than that of resistor R1. On the other hand, making the value of resistor R2 smaller than that of resistor R1 lowers the back gate potential of PMOS transistor M1. This is the noise voltage v no Although this contradicts the conditions for reducing the noise voltage v, the PMOS transistor M5 and diode group 84 allow for a reduction in resistance R2, and the effect increases with the number of diodes. By appropriately selecting the ratio of resistance R1 to resistance R2, the noise voltage v no This allows for the creation of small impedance conversion circuits.
[0088] Furthermore, the present invention is not limited to the embodiments described above, and can be modified, improved, etc., as appropriate. In addition, the material, shape, dimensions, number, placement, etc. of each component in the embodiments described above are arbitrary and not limited, as long as they can achieve the present invention.
[0089] According to the embodiment described above, a current detection circuit 6 and a feedback circuit 7 were provided, but the invention is not limited to this. Providing the current detection circuit 6 and the feedback circuit 7 is not essential and may be omitted.
[0090] In the embodiments described above, a MOS transistor was used as the transistor, but it is not limited to this. Except for the first transistor, bipolar transistors may also be used. In this case, the gate is read as the base, the source as the emitter, and the drain as the collector.
[0091] According to the embodiment described above, the back gate potential supply circuit 8C had a group of diodes 84, but it is not limited to this. Having a group of diodes 84 is not essential and may be omitted depending on the conditions. In this case, the connection point between the PMOS transistor M5 and the current source 83 is connected to resistors R1 and R2. [Explanation of Symbols]
[0092] 1,1B,1C Impedance Conversion Circuit 2 loads 4. Current source (first current source) 6. Current detection circuit 7 Feedback Circuit 8,8B,8C Back Gate Potential Supply Circuit 81. Current source (second current source) 82 Current source (third current source) 83. Current Source (Fourth Current Source) C MIC Capacitor D8 diode M1 PMOS transistor (first transistor) M2 PMOS transistor (second transistor) M3 NMOS transistor (third transistor) M4 PMOS transistor (fourth transistor) M5 PMOS transistor (the fifth transistor) R1 Resistor (First resistor) R2 Resistor (Second resistor)
Claims
1. In an impedance conversion circuit that receives a signal at high impedance to prevent attenuation of the input signal from the microphone's capacitor and outputs it at low impedance to drive the load, A first transistor with its gate connected to the input and its source connected to the output, A first current source that supplies current to the source of the first transistor, The system includes a back gate potential supply circuit that converts the source potential of the first transistor and supplies it as the back gate potential of the first transistor, The aforementioned back gate potential supply circuit is It has a first resistor and a second resistor connected in series with respect to the back gate potential, which is adjustable according to the ratio of the first resistor and the second resistor. Impedance conversion circuit.
2. In the impedance conversion circuit described in claim 1, The first resistor and the second resistor divide the potential of the source of the first transistor. The aforementioned back gate potential supply circuit is A second transistor that level-shifts the voltage divided by the first and second resistors, The system further comprises a second current source connected in series with the second transistor, The voltage between the second transistor and the second current source is supplied as the back gate potential of the first transistor. Impedance conversion circuit.
3. In the impedance conversion circuit described in claim 1, The aforementioned back gate potential supply circuit is A third transistor converts the potential of the source of the first transistor into current and supplies it to the first resistor and the second resistor, A fourth transistor that level-shifts the voltage between the first resistor and the second resistor, The system further comprises a third current source connected in series with the fourth transistor, The voltage between the fourth transistor and the third current source is supplied as the back gate potential of the first transistor. Impedance conversion circuit.
4. In the impedance conversion circuit described in claim 1, The aforementioned back gate potential supply circuit is A fifth transistor that level-shifts the potential of the source of the first transistor, The system further comprises a fourth current source connected in series with the fifth transistor, The first resistor and the second resistor divide the voltage between the fifth transistor and the fourth current source, and supply the divided voltage to the back gate of the first transistor. Impedance conversion circuit.
5. In the impedance conversion circuit described in claim 4, The aforementioned back gate potential supply circuit is The device further comprises a diode connected between the fifth transistor and the fourth current source. Impedance conversion circuit.
6. In the impedance conversion circuit described in claim 5, Multiple diodes are connected in series. Impedance conversion circuit.
7. In the impedance conversion circuit according to any one of claims 1 to 6, A current detection circuit for detecting the current flowing through the first transistor, The system includes a feedback circuit that controls the current flowing through the first current source according to the detection result of the current detection circuit, Impedance conversion circuit.