Semiconductor device, method for manufacturing a semiconductor device

Abstract

We provide highly reliable semiconductor devices. [Solution] A semiconductor device having a vertical transistor. An interlayer insulating layer is provided on a conductive layer that functions as the source electrode or drain electrode of the vertical transistor. The interlayer insulating layer has an opening that overlaps with the conductive layer. The semiconductor layer of the vertical transistor has a first region located inside the opening and a second region in contact with the upper surface of the interlayer insulating layer. The gate insulating layer and gate electrode of the vertical transistor are provided on the semiconductor layer such that they have a region located inside the opening. In the semiconductor layer, the concentration of impurity elements in at least a portion of the second region is higher than the concentration of impurity elements in the first region. The impurity elements are supplied after the gate electrode is formed. The semiconductor layer may contain indium oxide.

Description

Technical Field

[0001] One aspect of the present invention relates to a transistor, a semiconductor device, a memory device, and an electronic device. Another aspect of the present invention relates to a method for manufacturing a transistor and a semiconductor device.

[0002] Note that one aspect of the present invention is not limited to the above technical field. Examples of the technical field of one aspect of the present invention include a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, an electronic device, a lighting device, an input device (e.g., a touch sensor), an input / output device (e.g., a touch panel), a driving method thereof, or a manufacturing method thereof.

[0003] In this specification and the like, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including semiconductor elements (transistors, diodes, photodiodes, etc.), a device having the same circuit, and the like. It also refers to all devices that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip equipped with an integrated circuit, and an electronic component in which a chip is housed in a package are examples of semiconductor devices. In addition, a memory device, a display device, a light-emitting device, a lighting device, and an electronic device are semiconductor devices themselves and may each have a semiconductor device.

Background Art

[0004] Techniques for constructing a transistor using a semiconductor thin film formed on a substrate having an insulating surface have attracted attention. Such transistors are widely applied to electronic devices such as integrated circuits (ICs) and display devices. Although silicon-based semiconductor materials are widely known as semiconductor materials applicable to transistors, oxide semiconductors have attracted attention as other materials.

[0005] Furthermore, transistors using oxide semiconductors are known to have extremely low leakage current in the off state. For example, Patent Document 1 discloses a low-power CPU (Central Processing Unit) that utilizes the low leakage current characteristic of transistors using oxide semiconductors. Also, for example, Patent Document 2 discloses a memory device that can retain its contents for a long period of time by utilizing the low leakage current characteristic of transistors using oxide semiconductors.

[0006] Furthermore, examples of oxide semiconductors applicable to the active layer of a transistor include indium oxide and indium gallium zinc oxide. Non-patent document 1 reports on the use of In2O3 in thin-film transistors. Non-patent document 2 discloses a thin-film transistor using hydride polycrystalline indium oxide formed by low-temperature solid-phase crystallization as the active layer. [Prior art documents] [Patent Documents]

[0007] [Patent Document 1] Japanese Patent Publication No. 2012-257187 [Patent Document 2] Japanese Patent Publication No. 2011-151383 [Non-patent literature]

[0008] [Non-Patent Document 1] Dhananjay & Chu, CW Realization of In2O3 thin film transistors through reactive evaporation process. Appl. Phys. Lett. 91, 1-4 (2007). [Non-Patent Document 2] Y. Magari et al., “High-mobility hydrogenated polycrystalline In2O3(In2O3:H) thin-film transistors”, nature COMMUNICATIONS, 13, 1078 (2022) [Overview of the project] [Problems that the invention aims to solve]

[0009] One aspect of the present invention aims to provide a transistor with good electrical characteristics. One aspect of the present invention aims to provide a transistor with a large on-current. One aspect of the present invention aims to provide a transistor with low parasitic capacitance. One aspect of the present invention aims to provide a highly reliable transistor, semiconductor device, or memory device. One aspect of the present invention aims to provide a transistor, semiconductor device, or memory device that can be miniaturized or highly integrated. One aspect of the present invention aims to provide a semiconductor device or memory device with low power consumption. One aspect of the present invention aims to provide a semiconductor device or memory device with a fast operating speed. One aspect of the present invention aims to provide a semiconductor device or memory device with low manufacturing costs. One aspect of the present invention aims to provide a novel transistor, semiconductor device, or memory device. One aspect of the present invention aims to provide a method for manufacturing the above-mentioned transistor, semiconductor device, or memory device.

[0010] Furthermore, the description of these problems does not preclude the existence of other problems. One aspect of the present invention does not necessarily have to solve all of these problems. It is possible to extract other problems from the description in the specification, drawings, and claims. [Means for solving the problem]

[0011] One aspect of the present invention comprises a first conductive layer, a second conductive layer, a first insulating layer, a second insulating layer, and a semiconductor layer, wherein the first insulating layer has a region located on the first conductive layer, the first insulating layer has a first opening overlapping the first conductive layer, the semiconductor layer has a first region located inside the first opening and a second region in contact with the upper surface of the first insulating layer, the semiconductor layer has a region in contact with the first conductive layer, and the second insulating layer has a region in contact with the side surface of the first region of the semiconductor layer and a semi-semiconductor layer A semiconductor device comprising a second conductive layer having a region in contact with the upper surface of a second region of the conductive layer, the second conductive layer being provided on a second insulating layer such that it has a region located inside the first opening, the concentration of the first element in at least a portion of the second region being higher than the concentration of the first element in the first region, the semiconductor layer having indium oxide, and the first element being one or more of boron, phosphorus, titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, and silicon.

[0012] Alternatively, in the above embodiment, the semiconductor device has a third insulating layer, the third insulating layer having a third region along the side surface of the second conductive layer and a fourth region along the upper surface of the second insulating layer, and in the semiconductor layer, the concentration of the first element in the region overlapping with the third region may be lower than the concentration of the first element in the region overlapping with the fourth region.

[0013] Alternatively, in the above embodiment, the semiconductor device may have a third conductive layer, a fourth conductive layer, and a fifth conductive layer, wherein the semiconductor layer has a third region located on the first insulating layer, the third region is provided opposite to the second region with the second conductive layer in between, the third conductive layer has a region in contact with the upper surface of the second region of the semiconductor layer, the fourth conductive layer has a region in contact with the upper surface of the third region of the semiconductor layer, and the fifth conductive layer may have a region in contact with the third conductive layer and a region in contact with the fourth conductive layer.

[0014] Alternatively, in the above embodiment, the semiconductor device may have a third insulating layer, the third insulating layer being located on the second conductive layer and the second insulating layer, the second insulating layer and the third insulating layer each having a second opening overlapping with the second region and a third opening overlapping with the third region, the third conductive layer having a region located inside the second opening, the fourth conductive layer having a region located inside the third opening, and the fifth conductive layer having a region located on the third conductive layer, a region located on the fourth conductive layer and a region located on the third insulating layer.

[0015] Alternatively, in the above embodiment, the semiconductor layer may have a region extending in the first direction.

[0016] Alternatively, in the above embodiment, the semiconductor device has a third insulating layer and a third conductive layer, wherein the third insulating layer is provided so as to surround the side surface located outside the first opening of the second conductive layer in a plan view, the third conductive layer has a region in contact with the upper surface of the second conductive layer and a region located on the third insulating layer, and the third conductive layer may have a region extending in the second direction.

[0017] Alternatively, in the above embodiment, the second region has a concentration of the first element of 1 × 10⁻⁶ 18 atoms / cm 3 It may have a region that is greater than or equal to the above.

[0018] Alternatively, in the above embodiment, the first region has a concentration of the first element of 1 × 10⁻⁶ 18 atoms / cm 3 It may have a region that is less than [a certain value].

[0019] Alternatively, in the above embodiment, the semiconductor device may have an insulating layer, the insulating layer having a region located inside the first opening, and the semiconductor layer may have a region located on the insulating layer and a region in contact with the side surface of the insulating layer inside the first opening. The insulating layer may contain gallium and oxygen.

[0020] Alternatively, one aspect of the present invention is a method for manufacturing a semiconductor device comprising first to seventh steps: in the first step, a first conductive layer is formed; in the second step, a first insulating layer is formed so as to cover the first conductive layer; in the third step, a first opening is formed in the first insulating layer that reaches the first conductive layer; in the fourth step, a semiconductor layer having indium oxide is formed so as to have a region in contact with the upper surface of the first conductive layer and a region located on the first insulating layer; in the fifth step, a second insulating layer is formed so as to have a region in contact with the upper surface of the semiconductor layer and a region in contact with the side surface; in the sixth step, a second conductive layer is formed on the second insulating layer so as to have a region located inside the first opening; and in the seventh step, one or more of boron, phosphorus, titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, and silicon are supplied as a first element to a region of the semiconductor layer that does not overlap with the second conductive layer.

[0021] Alternatively, in the above embodiment, there is an eighth step, in which, after the sixth step, a third insulating layer is formed along the upper surface of the second conductive layer, the side surface of the second conductive layer, and the upper surface of the second insulating layer, and the seventh step is performed after the eighth step, and in the seventh step, the supply of the first element to the semiconductor layer may be performed using ion implantation, ion doping, or plasma immersion ion implantation.

[0022] Alternatively, in the above embodiment, in the eighth step, a third insulating layer may be formed on the second conductive layer and the second insulating layer; in the ninth step, a second opening and a third opening reaching the semiconductor layer may be formed in the third insulating layer and the second insulating layer, facing each other with the second conductive layer in between; in the tenth step, a third conductive layer located inside the second opening and a fourth conductive layer located inside the third opening may be formed having a region in contact with the semiconductor layer; and in the eleventh step, a fifth conductive layer may be formed having a region in contact with the third conductive layer, a region in contact with the fourth conductive layer, and a region located on the third insulating layer.

[0023] Alternatively, one aspect of the present invention comprises first to ten steps: in the first step, a first conductive layer is formed; in the second step, a first insulating layer is formed so as to cover the first conductive layer; in the third step, an opening is formed in the first insulating layer that reaches the first conductive layer; in the fourth step, a semiconductor layer having indium oxide is formed having a region in contact with the upper surface of the first conductive layer and a region located on the first insulating layer; in the fifth step, a second insulating layer is formed having a region in contact with the upper surface of the semiconductor layer and a region in contact with the side surface; and in the sixth step, the opening is formed This is a method for manufacturing a semiconductor device, comprising: forming a sacrificial layer on a semiconductor layer such that it has a region located in the opening; in the seventh step, supplying one or more of the following elements as a first element to a region of the semiconductor layer that does not overlap with the sacrificial layer: boron, phosphorus, titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, and silicon; in the eighth step, removing the sacrificial layer; in the ninth step, forming a second conductive layer on a second insulating layer such that it has a region located inside the opening; and in the tenth step, forming a third conductive layer such that it has a region in contact with the upper surface of the second conductive layer.

[0024] Alternatively, in the above embodiment, the method may include an eleventh step and a twelfth step, wherein in the eleventh step, after the sixth step, a third insulating layer is formed so as to cover the upper surface of the sacrificial layer and the side surface located outside the opening; the seventh step is performed after the eleventh step, in the seventh step, the supply of the first element to the semiconductor layer is performed using ion implantation, ion doping, or plasma immersion ion implantation; in the twelfth step, after the seventh step, the upper surface of the sacrificial layer is exposed by removing a portion of the third insulating layer; and the eighth step may be performed after the twelfth step.

[0025] Alternatively, in the above embodiment, a semiconductor layer may be formed in the fourth step so as to have a region extending in the first direction, and a third conductive layer may be formed in the tenth step so as to have a region extending in the second direction. [Effects of the Invention]

[0026] According to one aspect of the present invention, a transistor with good electrical characteristics can be provided. According to one aspect of the present invention, a transistor with a large on-current can be provided. According to one aspect of the present invention, a transistor with low parasitic capacitance can be provided. According to one aspect of the present invention, a highly reliable transistor, semiconductor device, or memory device can be provided. According to one aspect of the present invention, a transistor, semiconductor device, or memory device that can be miniaturized or highly integrated can be provided. According to one aspect of the present invention, a semiconductor device or memory device with low power consumption can be provided. According to one aspect of the present invention, a memory device or memory device with a fast operating speed can be provided. According to one aspect of the present invention, a semiconductor device or memory device with low manufacturing costs can be provided. According to one aspect of the present invention, a novel transistor, semiconductor device, or memory device can be provided. According to one aspect of the present invention, a method for manufacturing the above-mentioned transistor, semiconductor device, or memory device can be provided.

[0027] Furthermore, the description of these effects does not preclude the existence of other effects. One aspect of the present invention does not necessarily have to possess all of these effects. Other effects can be extracted from the description, drawings, and claims. [Brief explanation of the drawing]

[0028] [Figure 1] Figures 1(A) and 1(B) are perspective views showing examples of semiconductor device configurations. [Figure 2] Figures 2(A) and 2(B) are plan views showing examples of semiconductor device configurations. [Figure 3] Figures 3(A) and 3(B) are cross-sectional views showing examples of semiconductor device configurations. [Figure 4] Figures 4(A) to 4(C) are cross-sectional views showing examples of semiconductor device configurations. [Figure 5] Figure 5(A) is a plan view showing an example of the configuration of a semiconductor device. Figure 5(B) is a cross-sectional view showing an example of the configuration of a semiconductor device. [Figure 6] Figures 6(A) and 6(B) are perspective views showing examples of semiconductor device configurations. [Figure 7]Figures 7(A) and 7(B) are plan views showing examples of semiconductor device configurations. [Figure 8] Figures 8(A) and 8(B) are cross-sectional views showing examples of semiconductor device configurations. [Figure 9] Figures 9(A) and 9(B) are cross-sectional views showing examples of semiconductor device configurations. [Figure 10] Figures 10(A) and 10(B) are cross-sectional views showing examples of semiconductor device configurations. [Figure 11] Figures 11(A) and 11(B) are cross-sectional views showing examples of semiconductor device configurations. [Figure 12] Figures 12(A) and 12(B) are cross-sectional views showing examples of semiconductor device configurations. [Figure 13] Figures 13(A) and 13(B) are cross-sectional views showing examples of semiconductor device configurations. [Figure 14] Figures 14(A) and 14(B) are cross-sectional views showing examples of semiconductor device configurations. [Figure 15] Figures 15(A) and 15(B) are cross-sectional views showing examples of semiconductor device configurations. [Figure 16] Figures 16(A) to 16(C) are cross-sectional views showing examples of semiconductor device configurations. [Figure 17] Figure 17(A) is a plan view showing an example of the configuration of a semiconductor device. Figure 17(B) is a cross-sectional view showing an example of the configuration of a semiconductor device. [Figure 18] Figure 18(A) is a plan view showing an example of the configuration of a semiconductor device. Figure 18(B) is a cross-sectional view showing an example of the configuration of a semiconductor device. [Figure 19] Figures 19(A) and 19(B) are cross-sectional views showing examples of semiconductor device configurations. [Figure 20] Figure 20 is a cross-sectional view showing an example of the configuration of a semiconductor device. [Figure 21] Figures 21(A) and 21(B) are cross-sectional views showing examples of semiconductor device configurations. [Figure 22] Figures 22(A) to 22(F) are cross-sectional views showing an example of a method for manufacturing a semiconductor device. [Figure 23]Figures 23(A) to 23(D) are cross-sectional views showing an example of a method for manufacturing a semiconductor device. [Figure 24] Figures 24(A) to 24(F) are cross-sectional views showing an example of a method for manufacturing a semiconductor device. [Figure 25] Figures 25(A) to 25(F) are cross-sectional views showing an example of a method for manufacturing a semiconductor device. [Figure 26] Figure 26(A) is a plan view showing an example of the configuration of a storage device. Figures 26(B) and 26(C) are cross-sectional views showing an example of the configuration of a storage device. [Figure 27] Figure 27(A) is a plan view showing an example of the configuration of a storage device. Figures 27(B) and 27(C) are cross-sectional views showing an example of the configuration of a storage device. [Figure 28] Figure 28 is a cross-sectional view showing an example of a storage device configuration. [Figure 29] Figure 29 is a cross-sectional view showing an example of a storage device configuration. [Figure 30] Figure 30 is a block diagram showing an example configuration of a semiconductor device. [Figure 31] Figures 31(A) to 31(H) show examples of memory cell circuit configurations. [Figure 32] Figures 32(A) and 32(B) are perspective views showing examples of semiconductor device configurations. [Figure 33] Figure 33 is a block of the CPU. [Figure 34] Figures 34(A) and 34(B) are perspective views showing examples of semiconductor device configurations. [Figure 35] Figures 35(A) and 35(B) are perspective views showing examples of semiconductor device configurations. [Figure 36] Figures 36(A) and 36(B) show examples of electronic components. [Figure 37] Figures 37(A) through 37(C) show examples of large-scale computers. Figure 37(D) shows an example of space equipment. Figure 37(E) shows an example of a storage system applicable to data centers. [Modes for carrying out the invention]

[0029] Embodiments will be described in detail with reference to the drawings. However, it will be readily apparent to those skilled in the art that the present invention is not limited to the following description, and that its form and details can be modified in various ways without departing from the spirit and scope of the present invention. Accordingly, the present invention shall not be construed as being limited to the descriptions of the embodiments shown below.

[0030] In the invention described below, the same reference numerals are used in common across different drawings for identical parts or parts having similar functions, and repeated explanations are omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used, and reference numerals may not be assigned.

[0031] Furthermore, the position, size, and scope of each component shown in the drawings may not represent the actual position, size, and scope for the sake of ease of understanding. Therefore, the disclosed invention is not necessarily limited to the position, size, and scope disclosed in the drawings.

[0032] In this specification, the ordinal numbers "first" and "second" are used for convenience only and do not limit the number of components or the order of components (for example, process order or stacking order). Furthermore, the ordinal numbers used for components in one part of this specification may not be the same as those used for the same components in other parts of this specification or in the claims.

[0033] Furthermore, a transistor is a type of semiconductor device that can perform functions such as amplifying current or voltage, and switching operations that control conduction or non-conductivity. Transistors as used herein include IGFETs (Insulated Gate Field Effect Transistors) and thin-film transistors (TFTs).

[0034] In this specification, transistors using an oxide semiconductor or metal oxide in the semiconductor layer, and transistors having an oxide semiconductor or metal oxide in the channel formation region, may be referred to as OS (Oxide Semiconductor) transistors. Furthermore, transistors having silicon in the channel formation region may be referred to as Si transistors.

[0035] Furthermore, the functions of "source" and "drain" may be reversed when transistors with different polarities are used, or when the direction of current changes during circuit operation. For this reason, in this specification, the terms "source" and "drain" may be used interchangeably.

[0036] In this specification, an oxidized nitride is a material containing oxygen and nitrogen, and the nitrogen and oxygen content in its composition is not limited. In other words, oxidized nitrides include materials in which the oxygen content is greater than the nitrogen content, and materials in which the nitrogen content is greater than the oxygen content.

[0037] In this specification, the terms "film" and "layer" can be interchanged as needed or depending on the context. For example, the term "conductive layer" can be changed to the term "conductive film." Alternatively, the term "insulating film" can be changed to the term "insulating layer."

[0038] Furthermore, in this specification, "parallel" means a state in which two lines are positioned at an angle of -10 degrees or more and 10 degrees or less. Therefore, the case of -5 degrees or more and 5 degrees or less is also included. Also, "approximately parallel" means a state in which two lines are positioned at an angle of -20 degrees or more and 20 degrees or less. Also, "perpendicular" means a state in which two lines are positioned at an angle of 80 degrees or more and 100 degrees or less. Therefore, the case of 85 degrees or more and 95 degrees or less is also included. Also, "approximately perpendicular" means a state in which two lines are positioned at an angle of 70 degrees or more and 110 degrees or less.

[0039] In this specification, "connection" includes, for example, "electrical connection." The term "electrical connection" is sometimes used to define the connection relationship of circuit elements as a physical object. Furthermore, "electrical connection" includes both "direct connection" and "indirect connection." "A and B are directly connected" means that A and B are connected without the use of circuit elements (e.g., transistors, switches, etc.; wiring is not considered a circuit element). On the other hand, "A and B are indirectly connected" means that A and B are connected through one or more circuit elements. A, B, and C (described later) refer to objects such as elements, circuits, wiring, electrodes, terminals, semiconductor layers, and conductive layers.

[0040] For example, assuming a circuit containing A and B is in operation, if there is a timing during the circuit's operation when electrical signals are exchanged or potential interactions occur between A and B, then it can be defined that "A and B are indirectly connected" as physical objects. Furthermore, even if there is a timing during the circuit's operation when no electrical signals are exchanged or potential interactions occur between A and B, if there is a timing during the circuit's operation when electrical signals are exchanged or potential interactions occur between A and B, then it can be defined that "A and B are indirectly connected."

[0041] An example of a case where "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors. On the other hand, an example of a case where "A and B are not indirectly connected" is when an insulator is interposed in the path from A to B. Specifically, this includes cases where a capacitive element is connected between A and B, or where a transistor gate insulating film is interposed between A and B. Therefore, it cannot be said that "the gate (A) of a transistor and the source or drain (B) of a transistor are indirectly connected."

[0042] Another example of a situation where it cannot be said that "A and B are indirectly connected" is when multiple transistors are connected via source and drain in the path from A to B, and a constant potential V is supplied from a power supply, GND, etc., to the nodes between the transistors.

[0043] In this specification, a tapered shape refers to a shape in which at least a portion of the side surface of a structure is inclined with respect to the substrate surface or the surface to be formed. For example, it is preferable that there is a region in which the angle (also called the taper angle) between the inclined side surface and the substrate surface or the surface to be formed is greater than 0 degrees and less than 90 degrees. The side surface of the structure, the substrate surface, and the surface to be formed do not necessarily have to be perfectly flat, and may be substantially planar with a small curvature, or substantially planar with fine irregularities.

[0044] In this specification, "heights match" refers to a configuration in which the heights from a reference surface (for example, a flat surface such as the substrate surface) are equal in a cross-sectional view. For example, if there are two layers with different heights (here referred to as layer A and layer B) with respect to the reference surface, the heights match if the difference between the height of the top surface of layer A and the height of the top surface of layer B is 10 nm or less.

[0045] In this specification, "side edges coincide" means that, in a plan view, at least a portion of the contours of the stacked layers overlap. For example, in the case of two stacked layers (here referred to as layer A and layer B), if the shortest distance from the side edge of layer A to the side edge of layer B in a plan view is 10 nm or less, then the side edges also coincide.

[0046] In general, it can be difficult to clearly distinguish between "exact match" and "approximate match." Therefore, in this specification, "match" may include both exact matches and approximate matches.

[0047] In drawings and other illustrations relating to this specification, arrows indicating the X, Y, and Z directions may be included. In this specification, the "X direction" refers to the direction along the X-axis, and unless explicitly stated, forward and reverse directions may not be distinguished. The same applies to the "Y direction" and "Z direction." Furthermore, the X, Y, and Z directions are directions that intersect each other. For example, the X, Y, and Z directions are directions that are orthogonal to each other.

[0048] In this specification, the cubic crystal structure is sometimes referred to as cubic crystal, cubic structure, etc. The same applies to other crystal systems (hexagonal, trigonal, tetragonal, orthorhombic, monoclinic, and triclinic).

[0049] In this specification, the high power supply potential VDD (hereinafter also simply referred to as "VDD") refers to a power supply potential that is higher than the low power supply potential VSS (hereinafter also simply referred to as "VSS"). The low power supply potential VSS refers to a power supply potential that is lower than the high power supply potential VDD.

[0050] Potential H is the potential that turns an n-channel field-effect transistor (also called an "n-type transistor") on, and the potential that turns a p-channel field-effect transistor (also called a "p-type transistor") off. Similarly, potential L is the potential that turns an n-type transistor off, and the potential that turns a p-type transistor on. Therefore, potential H is higher than potential L. Potential H may be equal to VDD, and potential L may be equal to VSS.

[0051] In this specification and the like, the space group is represented using the Short notation of the international notation (or Hermann-Mauguin symbol). Also, the crystal plane and crystal orientation are represented using Miller indices. In crystallography, the notations for the space group, crystal plane, and crystal orientation are numbers with a bar above, but in this specification and the like, due to formatting constraints, instead of putting a bar above the number, a -(minus sign) may be attached before the number for expression. Also, the individual orientation indicating the orientation within the crystal is represented by [ ], the set orientation indicating all equivalent orientations is represented by < >, the individual plane indicating the crystal plane is represented by ( ), and the set plane having equivalent symmetry is represented by {}.

[0052] In this specification and the like, the content rate of a certain metal element in a metal oxide refers to the ratio of the number of atoms of that element to the total number of atoms of the metal elements contained in the metal oxide. For example, if the metal oxide contains metal element X, metal element Y, and metal element Z, and the number of atoms of metal element X, metal element Y, and metal element Z contained in the metal oxide are A X 、A Y 、A Z respectively, the content rate of metal element X can be expressed as A X / (A X +A Y +A Z ). Also, when the ratio of the number of atoms (atomic ratio) of metal element X, metal element Y, and metal element Z in the metal oxide is B X :B Y :B Z , the content rate of metal element X can be expressed as B X / (B X +B Y +B Z ).

[0053] In this specification and the like, the term "island-like" indicates a state in which two or more layers made of the same material formed in the same process are physically separated.

[0054] (Embodiment 1) This embodiment describes a semiconductor device according to one aspect of the present invention. The semiconductor device according to one aspect of the present invention has a vertical transistor. The semiconductor layer of the vertical transistor has a metal oxide. That is, the vertical transistor in the semiconductor device according to one aspect of the present invention is an OS transistor. Here, indium oxide can be used as the metal oxide.

[0055] In this specification, a vertical transistor refers to a transistor in which the source region and drain region are located at different heights. A vertical transistor has a channel length that has a component in the height direction (vertical direction). A vertical transistor is also called a VFET (Vertical Field Effect Transistor), vertical channel transistor, or vertical channel type transistor.

[0056] In a semiconductor device according to one aspect of the present invention, a first interlayer insulating layer is provided on a conductive layer that functions as one of the source electrode and drain electrode of a vertical transistor. The first interlayer insulating layer has an opening that overlaps with the conductive layer.

[0057] The semiconductor layer of the vertical transistor has a first region located inside the opening and a second region in contact with the upper surface of the first interlayer insulating layer. The semiconductor layer also has a region in contact with the conductive layer, specifically a region in contact with the upper surface of the conductive layer. In the semiconductor layer, the region in contact with the upper surface of the conductive layer and the region near it function as either the source region or the drain region of the vertical transistor.

[0058] The gate insulating layer of the vertical transistor is provided on the semiconductor layer and on the first interlayer insulating layer such that it has a region located inside the opening. The gate insulating layer has a region in contact with the upper surface of the first region of the semiconductor layer, a region in contact with the side surface of the first region, and a region in contact with the upper surface of the second region.

[0059] The gate electrode of a vertical transistor is provided on a gate insulating layer such that it has a region located inside the opening. The gate electrode has a region facing a semiconductor layer with the gate insulating layer in between. For example, the semiconductor layer has a region inside the opening that faces the side surface of the gate electrode with the gate insulating layer in between. Also, the semiconductor layer has a region on the first interlayer insulating layer that overlaps with the gate electrode via the gate insulating layer. These regions of the semiconductor layer function as channel-forming regions of the vertical transistor.

[0060] At least a portion of the second region of the semiconductor layer, i.e., the region in contact with the upper surface of the first interlayer insulating layer, contains impurity elements. Specifically, at least a portion of the region that does not overlap with the gate electrode contains impurity elements. The region containing the impurity elements functions as the other of the source region and drain region of the vertical transistor. In the semiconductor layer, the concentration of impurity elements in the other of the source region and drain region of the vertical transistor is higher than the concentration of impurity elements in the first region of the semiconductor layer, i.e., the region located inside the opening. Also, in the semiconductor layer, the concentration of impurity elements in the other of the source region and drain region of the vertical transistor is higher than the concentration of impurity elements in the channel formation region of the vertical transistor. The impurity elements can be one or more of, for example, boron, phosphorus, hydrogen, titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, and silicon. The impurity elements can be supplied to the semiconductor layer in a self-aligned manner using the gate electrode as a mask after the gate electrode has been formed.

[0061] When the semiconductor layer of a vertical transistor is, for example, an indium oxide film, the first region of the semiconductor layer preferably has crystalline properties, and more preferably a single-crystal film. Since a single-crystal film does not have grain boundaries, carrier scattering at the grain boundaries can be suppressed. Therefore, a transistor with high field-effect mobility can be provided. Furthermore, a highly reliable transistor can be provided.

[0062] One method for crystallizing the semiconductor layer of a vertical transistor is to perform a heat treatment after forming the semiconductor layer. However, if the heat treatment is performed after forming a conductive layer that functions as the other of the source electrode and drain electrode of the vertical transistor, oxygen contained in the semiconductor layer and oxygen contained in the heat treatment atmosphere may be absorbed by the conductive layer, causing it to oxidize. This can lead to an increase in the electrical resistance of the conductive layer, which can worsen the electrical characteristics of the vertical transistor. For example, the on-current of the vertical transistor may decrease. Furthermore, the reliability of the semiconductor device may decrease.

[0063] In one aspect of the present invention, a conductive layer that functions as the other of the source electrode and drain electrode is formed after the formation of the semiconductor layer. Therefore, the semiconductor layer can be crystallized while, for example, oxidation of the conductive layer can be suppressed. As a result, a transistor exhibiting good electrical characteristics and high reliability can be provided. Furthermore, a highly reliable semiconductor device can be provided.

[0064] A semiconductor device according to one aspect of the present invention may or may not have a conductive layer that functions as the other of the source and drain electrodes of a vertical transistor. When forming the conductive layer, after supplying impurity elements to the semiconductor layer, a second interlayer insulating layer is formed on the gate electrode and on the gate insulating layer. Subsequently, openings are formed in the second interlayer insulating layer and the gate insulating layer that reach the other of the source and drain regions of the vertical transistor. Then, a conductive layer that functions as the other of the source and drain electrodes of the vertical transistor is formed so as to be located inside the opening. The conductive layer is formed to have a region that is in contact with the other of the source and drain regions of the vertical transistor. After the formation of the conductive layer that functions as the other of the source and drain electrodes of the vertical transistor, routing can be formed, for example, having a region in contact with the conductive layer and a region located on the second interlayer insulating layer.

[0065] The aforementioned wiring has regions that extend in a predetermined direction. In this case, the semiconductor layer can be provided in an island-like manner. Furthermore, if a semiconductor device according to one aspect of the present invention does not have a conductive layer that functions as the other of the source electrode and drain electrode of a vertical transistor, the semiconductor layer can be provided so as to have regions that extend in a predetermined direction.

[0066] <Example 1 of semiconductor device configuration> Figure 1(A) is a perspective view showing an example of the configuration of a semiconductor device according to one embodiment of the present invention. Figure 1(B) is a perspective view obtained by cutting a part of Figure 1(A). Figure 2(A) is a plan view of the semiconductor device shown in Figures 1(A) and 1(B). In Figure 2(A), some elements have been omitted for clarity. In subsequent plan views, some elements may also be omitted. Figure 2(B) is a plan view obtained by omitting some elements from Figure 2(A).

[0067] Figure 3(A) is a cross-sectional view between the dashed lines A1 and A2 shown in Figures 2(A) and 2(B). Figure 3(B) is a cross-sectional view between the dashed lines B1 and B2 shown in Figures 2(A) and 2(B). Figure 4(A) is a cross-sectional view between the dashed lines C1 and C2 shown in Figure 3(A). Figure 4(A) is also called a plan view.

[0068] Figure 4(B) is an enlarged view of region R1 shown in Figure 3(A). Figure 4(C) is a view of Figure 4(B) with a different configuration in some parts.

[0069] The semiconductor device shown in Figures 1(A) to 4(A) comprises an insulating layer 87 on a substrate (not shown), an insulating layer 62 and an insulating layer 74 on the insulating layer 87, a transistor 50 on the insulating layer 87, an insulating layer 88 on the transistor 50 and on the insulating layer 62, an insulating layer 86 on the insulating layer 88, and a conductive layer 59 on the insulating layer 86. The insulating layer 62 has a region in contact with the upper surface of the insulating layer 87. At least one of the insulating layer 87, insulating layer 62, insulating layer 74, insulating layer 88, insulating layer 86, and conductive layer 59 may be considered a component of the transistor 50. Note that in Figures 2(A) and 2(B), the insulating layer 62 and insulating layer 86 are shown transparently.

[0070] The insulating layer 87 functions as a base insulating layer or an interlayer insulating layer. The insulating layers 62 and 86 function as interlayer insulating layers.

[0071] The insulating layer 87 preferably has barrier properties against hydrogen, although this will be described in detail later. The insulating layers 62 and 86 preferably use materials with low dielectric constants. Using materials with low dielectric constants for the interlayer insulating layers reduces parasitic capacitance between wirings. While materials with low dielectric constants will be described later, for example, silicon oxide films can be used for the insulating layers 62 and 86. Note that since the insulating layer 87 can function as an interlayer insulating layer, materials with low dielectric constants can also be used for it.

[0072] Figures 1(A), 1(B), 3(A), and 3(B) show examples where the insulating layer 87 has a single-layer structure. However, the insulating layer 87 can have a laminated structure of two or more layers. For example, the insulating layer 87 can have a two-layer structure consisting of a first insulating layer and a second insulating layer on the first insulating layer. For example, it is preferable to use a material with a low dielectric constant as the first insulating layer and a barrier insulating layer against hydrogen as the second insulating layer in contact with the conductive layer 55. Specifically, it is preferable to use a silicon oxide film as the first insulating layer and a silicon nitride film as the second insulating layer.

[0073] In this specification, a barrier insulating layer refers to an insulating layer having barrier properties. Barrier properties refer to the property of making it difficult for the corresponding substance to diffuse (also referred to as the property of making it difficult for the corresponding substance to permeate, the property of having low permeability to the corresponding substance, or the function of suppressing the diffusion of the corresponding substance). When hydrogen is described as a corresponding substance, it refers to at least one of the following: hydrogen atoms, hydrogen molecules, water molecules, and substances bonded to hydrogen such as OH-. When impurities are described as a corresponding substance, unless otherwise specified, they refer to impurities in the channel-forming region or semiconductor layer, and refer to at least one of the following: hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), copper atoms, etc. When oxygen is described as a corresponding substance, it refers to at least one of the following: oxygen atoms, oxygen molecules, etc.

[0074] The transistor 50 has a conductive layer 55 on an insulating layer 87, a semiconductor layer 51 on the conductive layer 55, on the insulating layer 62, and on the insulating layer 74, a conductive layer 58a and a conductive layer 58b on the semiconductor layer 51, an insulating layer 52 on the semiconductor layer 51 and on the insulating layer 62, and a conductive layer 53 on the insulating layer 52. The conductive layer 55 has a region that is in contact with the upper surface of the insulating layer 87.

[0075] The insulating layer 62 and the insulating layer 74 have regions located on the conductive layer 55. The insulating layer 88 has regions located on the conductive layer 53 and regions located on the insulating layer 52. The conductive layer 59 has regions located on the conductive layer 58a and regions located on the conductive layer 58b. In Figure 2(B), the conductive layer 59, conductive layer 53, conductive layer 58a, conductive layer 58b, and semiconductor layer 51 shown in Figure 2(A) are omitted.

[0076] In transistor 50, the semiconductor layer 51 can be provided in an island-like manner. Furthermore, the conductive layer 55, conductive layer 53, and conductive layer 59 can be provided so as to have regions that extend in a predetermined direction. Figures 1(A) to 3(B) show an example in which the conductive layer 55 and conductive layer 53 extend in the X direction, and the conductive layer 59 extends in the Y direction.

[0077] In transistor 50, the conductive layer 53 functions as a gate electrode. The insulating layer 52 functions as a gate insulating layer. The conductive layer 55 functions as either a source electrode or a drain electrode. The conductive layers 58a and 58b each function as either a source electrode or a drain electrode. The conductive layer 53 has a region that functions as gate wiring.

[0078] A metal oxide (hereinafter also referred to as an oxide semiconductor) that functions as a semiconductor can be used as the semiconductor layer 51. In this case, the transistor 50 can be called an OS transistor.

[0079] For the semiconductor layer 51, it is preferable to use an indium-containing oxide, and particularly preferable to use indium oxide. The band gap of the indium-containing oxide is 2.0 eV or more, or 2.5 eV or more. By using a metal oxide with a large band gap for the semiconductor layer 51, the off-current of the transistor can be reduced. Because the OS transistor has a small off-current, the power consumption of the semiconductor device can be sufficiently reduced. In addition, because the OS transistor has high frequency characteristics, the semiconductor device can be operated at high speed.

[0080] For information on indium oxide that can be used as the semiconductor layer 51, please refer to the description in Embodiment 2. A detailed explanation is omitted here. In addition, the semiconductor material described in [Semiconductor Layer] below can be used for the semiconductor layer 51.

[0081] As shown in Figures 1(A) to 4(A), the insulating layer 62 has an opening 63. The opening 63 overlaps with the conductive layer 55, and specifically reaches the conductive layer 55. Figures 2(A), 2(B), and 4(A) show examples where the opening 63 is circular in plan view. By making the opening 63 circular in plan view, the processing accuracy when forming the opening 63 can be improved.

[0082] The insulating layer 74 has a region located inside the opening 63. The insulating layer 74 is provided to reflect the shape of the opening 63. The side surface of the insulating layer 74 has a region in contact with the side surface of the insulating layer 62 at the opening 63. The lower end of the insulating layer 74 has a region in contact with the upper surface of the conductive layer 55.

[0083] Figures 3(A) and 3(B) show an example where the height of the upper end of the insulating layer 74 from the reference plane matches the height of the upper surface of the insulating layer 62 from the reference plane. This configuration reduces the step difference between the insulating layer 74 and the insulating layer 62. As a result, the coverage of the semiconductor layer 51 is improved, and defects such as porosity can be reduced. Note that the height of the upper end of the insulating layer 74 from the reference plane may be lower than the height of the upper surface of the insulating layer 62 from the reference plane. Therefore, the height of the upper end of the insulating layer 74 from the reference plane can be set to be less than or equal to the height of the upper surface of the insulating layer 62 from the reference plane.

[0084] In the example described above, the reference surface can be, for example, the top surface of the substrate or the top surface of the insulating layer 87. In subsequent examples, the top surface of the substrate or the top surface of the insulating layer 87 may also be used as the reference surface.

[0085] The semiconductor layer 51 has a region located inside the opening 63. Within the opening 63, the semiconductor layer 51 has a region in contact with the side surface of the insulating layer 74.

[0086] In the semiconductor layer 51, the region located inside the opening 63 has a shape that reflects the shape of the opening 63. The semiconductor layer 51 has recesses that reflect the shape of the side surface of the insulating layer 74 and the shape of the upper surface of the conductive layer 55. Furthermore, outside the opening 63, the semiconductor layer 51 has a region located on the insulating layer 62 and a region located on the insulating layer 74. The semiconductor layer 51 has a region in contact with the upper surface of the insulating layer 62. The semiconductor layer 51 may also have a region in contact with the upper end of the insulating layer 74.

[0087] The semiconductor layer 51 has a region that is in contact with the conductive layer 55. For example, the bottom surface of the semiconductor layer 51 has a region that is in contact with the top surface of the conductive layer 55. The semiconductor layer 51 can be in contact with the conductive layer 55 in the region that overlaps with the opening 63.

[0088] The thickness of the semiconductor layer 51 can be 1 nm to 50 nm, preferably 2 nm to 30 nm, more preferably 2 nm to 20 nm, and more preferably 2 nm to 10 nm. It is preferable that the semiconductor layer 51 has at least a portion of the above-mentioned thickness region.

[0089] The insulating layer 52 has a region located inside the opening 63. Within the opening 63, the insulating layer 52 has a region in contact with the side surface of the semiconductor layer 51. Furthermore, in the region located on the insulating layer 62, the insulating layer 52 has a region in contact with the upper surface of the semiconductor layer 51. In addition, in the region overlapping with the opening 63, the insulating layer 62 has a region in contact with the upper surface of the recess in the semiconductor layer 51. The insulating layer 52 can be provided so as to cover the semiconductor layer 51. The insulating layer 52 has a recess that reflects the shape of the recess in the semiconductor layer 51. The insulating layer 52 is provided along the recess in the semiconductor layer 51.

[0090] The insulating layer 52 can be made from an insulating material as described in the section [Insulating Layer] below.

[0091] The conductive layer 53 is provided on the insulating layer 52 such that it has a region located inside the opening 63. The conductive layer 53 is provided so as to fill at least a portion of the recess in the insulating layer 52. The conductive layer 53 can be provided, for example, so as to fill the opening 63. Inside the opening 63, the conductive layer 53 has a region facing the semiconductor layer 51 with the insulating layer 52 in between.

[0092] The conductive layer 53 can be made of a conductive material as described in the [Conductive Layer] section below. Preferably, the conductive layer 53 is made of a conductive material mainly composed of tungsten, copper, or aluminum. The conductive layer 53 may also be a laminated structure. For example, it can be a laminated structure of a titanium nitride film and a tungsten film on the titanium nitride film.

[0093] The insulating layer 88 has a region along the upper surface of the conductive layer 53, a region along the side surface of the conductive layer 53, and a region along the upper surface of the insulating layer 52. In Figures 4(B) and 4(C), the region along the side surface of the conductive layer 53 is designated as region 71a. The region along the upper surface of the insulating layer 52 is designated as region 71b.

[0094] When an oxide semiconductor is used as the semiconductor layer 51, it is preferable that the insulating layer 88 has a function to suppress hydrogen diffusion. For example, it is preferable to use silicon nitride, which has higher hydrogen barrier properties than silicon oxide, for the insulating layer 88. Here, as mentioned above, it is preferable that the insulating layer 87 also has hydrogen barrier properties.

[0095] As described above, by surrounding the transistor 50 with barrier insulating layers (insulating layers 87 and 88) against hydrogen, the diffusion of hydrogen into the semiconductor layer 51 can be suppressed. Therefore, when an oxide semiconductor is used as the semiconductor layer 51, hydrogen can enter the oxygen vacancies in the channel formation region, creating defects (hereinafter referred to as V O This reduces the H (sometimes referred to as H). This improves the electrical characteristics and reliability of transistor 50.

[0096] Furthermore, it is preferable that the insulating layer 88 has the function of capturing or fixing hydrogen. With such a configuration, hydrogen contained in the semiconductor layer 51 can be captured or fixed. Therefore, the amount of hydrogen contained in the semiconductor layer 51 can be reduced.

[0097] Furthermore, the insulating layer 88 may have a laminated structure of an insulating layer having the function of capturing or fixing hydrogen and a barrier insulating layer against hydrogen. The insulating layer 88 may have, for example, a laminated film of an aluminum oxide film and a silicon nitride film on the aluminum oxide film.

[0098] As described above, an insulating layer 86 is provided on the insulating layer 88. The insulating layer 52, insulating layer 88, and insulating layer 86 have openings 67a and 67b. Openings 67a and 67b overlap with the region located on the insulating layer 62 of the semiconductor layer 51. Specifically, openings 67a and 67b reach the upper surface of the semiconductor layer 51. Openings 67a and 67b are provided facing each other with the conductive layer 53 in between.

[0099] The conductive layer 58a is located inside the opening 67a and has a region in contact with the upper surface of the semiconductor layer 51. Similarly, the conductive layer 58b is located inside the opening 67b and has a region in contact with the upper surface of the semiconductor layer 51. The conductive layer 58a can be provided, for example, to fill the opening 67a. Similarly, the conductive layer 58b can be provided, for example, to fill the opening 67b.

[0100] The conductive layer 58a and conductive layer 58b can be made from the conductive materials described in the [Conductive Layer] section below. Preferably, the conductive layer 58a and conductive layer 58b are made from conductive materials mainly composed of, for example, tungsten, copper, or aluminum.

[0101] Figures 2(A) and 2(B) show examples where openings 67a and 67b are circular in plan view. By making openings 67a and 67b circular in plan view, the machining accuracy when forming openings 67a and 67b can be improved. The shape of openings 67a and 67b in plan view can be a shape that can be applied as the shape of opening 63 in plan view.

[0102] In this specification, the openings 67a and 67b are sometimes collectively referred to as opening 67. Similarly, the conductive layers 58a and 58b are sometimes collectively referred to as conductive layer 58.

[0103] It is preferable that the upper surfaces of the insulating layer 86, the conductive layer 58a, and the conductive layer 58b are flattened. This allows the conductive layer 59 to be provided on a flat surface. Therefore, it is possible to prevent the formation of irregularities in the conductive layer 59, which would otherwise result in areas with locally thinner film thicknesses. When the upper surfaces of the insulating layer 86, the conductive layer 58a, and the conductive layer 58b are flattened, the height of the upper surface of the insulating layer 86 from the reference plane, the height of the upper surface of the conductive layer 58a from the reference plane, and the height of the upper surface of the conductive layer 58b from the reference plane are equal to or approximately equal to each other.

[0104] The conductive layer 59 has a region in contact with the conductive layer 58a and a region in contact with the conductive layer 58b. This allows the conductive layer 58a and the conductive layer 58b to be connected. Specifically, the conductive layer 59 has a region in contact with the upper surface of the conductive layer 58a, a region in contact with the upper surface of the conductive layer 58b, and a region in contact with the upper surface of the insulating layer 86. The conductive layer 59 also has a region located above the opening 63.

[0105] The conductive layer 59 functions as a routing wire for the source electrode and the other drain electrode of the transistor 50. Here, as shown in Figure 2(A), the conductive layer 59 intersects with the conductive layer 53 in a plan view, for example, perpendicular or nearly perpendicular. This makes it possible to reduce the overlapping area of ​​the conductive layer 59 and the conductive layer 53 compared to when the conductive layer 59 and the conductive layer 53 are arranged parallel in a plan view. Therefore, the parasitic capacitance between the conductive layer 59 and the conductive layer 53 can be reduced. Thus, a semiconductor device according to one aspect of the present invention can be a semiconductor device capable of high-speed operation. However, if, for example, the thickness of the insulating layer 86 is sufficiently thick and the parasitic capacitance per unit area between the conductive layer 59 and the conductive layer 53 is negligibly small, the conductive layer 59 and the conductive layer 53 may be arranged parallel in a plan view.

[0106] The conductive layer 59 can be made of a conductive material as described in the [Conductive Layer] section below. For example, the conductive layer 59 can be made of a high-melting-point material such as tungsten or molybdenum that provides both heat resistance and conductivity. Alternatively, a low-resistance conductive material such as aluminum or copper can be used. Using a low-resistance conductive material can reduce the wiring resistance.

[0107] The semiconductor layer 51 has a region that faces the conductive layer 53 with the insulating layer 52 in between. For example, within the opening 63, the semiconductor layer 51 has a region that faces the side surface of the conductive layer 53 with the insulating layer 52 in between. Also, on the insulating layer 74 and the insulating layer 62, the semiconductor layer 51 has regions that overlap with the conductive layer 53 via the insulating layer 52. These regions of the semiconductor layer 51 function as the channel formation region 51i of the transistor 50.

[0108] The region of the semiconductor layer 51 near the conductive layer 55 functions as one of the source region and drain region of the transistor 50. The regions of the semiconductor layer 51 near conductive layer 58a and near conductive layer 58b function as the other of the source region and drain region of the transistor 50. Thus, the channel-forming region 51i is sandwiched between the source region and the drain region.

[0109] The semiconductor layer 51 has a region located inside the opening 63, along the side surface of the insulating layer 74. Furthermore, one of the source and drain electrodes of the transistor 50 (here, the conductive layer 55) has a region located below the insulating layer 74. Additionally, the other source and drain electrode of the transistor 50 (here, the conductive layer 58a and conductive layer 58b) is located above the insulating layer 74. As a result, at least a portion of the channel of the transistor 50 is formed inside the opening 63, along the side surface of the insulating layer 74. In other words, the transistor 50 has a configuration in which current flows in the vertical direction. This allows the transistor 50 to reduce its occupied area compared to a planar transistor where the channel formation region, source region, and drain region are separately provided on the XY plane. Therefore, the semiconductor device can be highly integrated. Furthermore, when a semiconductor device according to one embodiment of the present invention is used as a memory device, the storage capacity per unit area can be increased. It can be said that the channel length direction of the transistor 50 has a component in the height direction (vertical direction).

[0110] Based on the above, transistor 50 is a vertical transistor. The conductive layer 55 can be considered the lower electrode of transistor 50. The conductive layers 58a and 58b can be considered the upper electrodes of transistor 50.

[0111] In a semiconductor device according to one aspect of the present invention, the source region and the other drain region of the transistor 50 contain an impurity element to reduce the resistance of the semiconductor layer 51. In the transistor 50, the region containing the impurity element is referred to as the low-resistance region 51na or the low-resistance region 51nb. The low-resistance region 51na and the low-resistance region 51nb are located in positions that do not overlap with the conductive layer 53. The low-resistance region 51na and the low-resistance region 51nb are located opposite each other with the conductive layer 53 in between. The low-resistance region 51na includes a region in contact with the conductive layer 58a. The low-resistance region 51nb includes a region in contact with the conductive layer 58b.

[0112] The electrical resistivity of the low-resistivity region 51na and the low-resistivity region 51nb is at least lower than the electrical resistivity of the channel-forming region 51i. A lower electrical resistivity is preferable for the low-resistivity region 51na and the low-resistivity region 51nb. For example, the electrical resistivity of the low-resistivity region 51na and the low-resistivity region 51nb is 1 × 10⁻⁶. -5 Ω m or more 1×10 -3 It can be less than or equal to Ω·m.

[0113] The low-resistance region 51na and the low-resistance region 51nb contain impurity elements. Typical nonmetallic elements, typical metallic elements, or transition elements (transition metals) can be used as impurity elements. For example, elements such as boron, phosphorus, hydrogen, titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, and silicon can be used as impurity elements. The low-resistance region 51na and the low-resistance region 51nb may contain one or more of these elements as impurity elements.

[0114] In this specification, the impurity elements contained in the low-resistance region 51na and the low-resistance region 51nb may be referred to as the first element.

[0115] The concentrations of impurity elements in the low-resistance region 51na and the low-resistance region 51nb are higher than the concentrations of the impurity elements in the channel-forming region 51i. The concentrations of the impurity elements in the low-resistance region 51na and the low-resistance region 51nb are, for example, 1 × 10⁻⁶. 18 atoms / cm 3 The above 1 x 10 22 atoms / cm 3 The following is preferably 5 × 10 18 atoms / cm 3 The above 5 x 10 21 atoms / cm 3 More preferably 1 × 10 19 atoms / cm 3 The above 1 x 10 21 atoms / cm 3 The following is preferable. Furthermore, if multiple impurity elements are present, it is preferable that the concentration of each impurity element is within the above range.

[0116] By supplying impurity elements such as boron, phosphorus, or silicon to the low-resistance region 51na and the low-resistance region 51nb, these impurity elements remove oxygen from these regions, creating oxygen deficiencies (V O A vacancy is created. Then, the oxygen vacancy combines with hydrogen in the film to generate a carrier. In addition, by supplying hydrogen as an impurity element to the low-resistance region 51na and the low-resistance region 51nb, the hydrogen combines with the oxygen vacancies in these regions to generate a carrier. Furthermore, by supplying, for example, titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, or tin as an impurity element to the low-resistance region 51na and the low-resistance region 51nb, the carrier concentration in the low-resistance region 51na and the low-resistance region 51nb can be increased. As a result, the low-resistance region 51na and the low-resistance region 51nb of the transistor 50 can be made to have lower resistance than the channel formation region 51i.

[0117] Therefore, the contact resistance between the semiconductor layer 51 and the conductive layer 58a, and the contact resistance between the semiconductor layer 51 and the conductive layer 58b can be reduced, and the on-current of the transistor 50 can be increased. In particular, even if the main component of the semiconductor layer 51 (indium in the case of indium oxide) is different from the main components of the conductive layers 58a and 58b, the above-mentioned contact resistance can be reduced and the on-current of the transistor 50 can be increased by forming low-resistance regions 51na and 51nb in the semiconductor layer 51. Furthermore, by increasing the on-current of the transistor 50, the transistor 50 can obtain high frequency characteristics. Thus, a semiconductor device with high operating speed can be provided.

[0118] Furthermore, the aforementioned impurity elements may also be supplied to the channel formation region 51i in the semiconductor layer 51. Alternatively, due to the effects of heat during the manufacturing process, some of the impurity elements contained in the low-resistance region 51na and low-resistance region 51nb may diffuse into the channel formation region 51i. The concentration of impurity elements in the channel formation region 51i is preferably one-tenth or less of the concentration of impurity elements in the low-resistance region 51na and low-resistance region 51nb, and more preferably one-hundredth or less. The concentration of the impurity elements in the channel formation region 51i is, for example, 1 × 10⁻⁶ 18 atoms / cm 3 Less than 1 × 10 17 atoms / cm 3 More preferably 1 × 10 16 atoms / cm 3 More preferably 1 × 10 15 atoms / cm 3 The following is possible. There are no particular limitations on the lower limit of the impurity concentration in the channel-forming region 51i, but for example, 1 × 10 14 atoms / cm 3 It can be done this way.

[0119] For example, the concentration of impurity elements in the semiconductor layer 51 can be analyzed by analytical methods such as secondary ion mass spectrometry (SIMS) or X-ray photoelectron spectroscopy (XPS) or electron spectroscopy for chemical analysis (ESCA). When using XPS analysis, the concentration distribution in the depth direction can be determined by combining ion sputtering from the surface or back side with XPS analysis.

[0120] The low-resistance regions 51na and 51nb can be formed by supplying impurity elements to the semiconductor layer 51 after the formation of the conductive layer 53 and before the formation of the conductive layers 58a and 58b. The impurity elements can be supplied to the semiconductor layer 51 using, for example, ion implantation, ion doping, plasma immersion ion implantation, or plasma treatment. When supplying impurity elements to the semiconductor layer 51 using plasma treatment, a dry etching apparatus, a plasma-enhanced chemical vapor deposition (PECVD) apparatus, a high-density plasma CVD apparatus, etc., can be used as the plasma generating apparatus. Alternatively, impurity elements can be supplied to the semiconductor layer 51 by performing heat treatment in an atmosphere containing impurity elements. The impurity elements can be supplied to the semiconductor layer 51 by self-alignment using the conductive layer 53 as a mask.

[0121] The supply of impurity elements may be performed before the formation of the insulating layer 88, or after the formation of the insulating layer 88 and before the formation of the insulating layer 86. Alternatively, the supply of impurity elements may be performed after the formation of the insulating layer 86 and before the formation of the openings 67a and 67b, or after the formation of the openings 67a and 67b. Figures 1(B), 2(A), 3(A), and 4(B) show examples in which impurity elements are supplied after the formation of the insulating layer 88 and before the formation of the insulating layer 86. Figure 4(C) shows an example in which impurity elements are supplied before the formation of the insulating layer 88.

[0122] As mentioned above, Figure 4(B) is an enlarged view of region R1 shown in Figure 3(A). Region R1 includes insulating layer 62, insulating layer 74, semiconductor layer 51, insulating layer 52, conductive layer 53, insulating layer 88, insulating layer 86, and conductive layer 58a. Region R1 also includes the channel formation region 51i and the low-resistance region 51na of the semiconductor layer 51.

[0123] In Figures 4(B) and 4(C), the region overlapping with region 71a in the semiconductor layer 51 is defined as region 72. When the impurity elements are supplied after the formation of the insulating layer 88, the impurity elements are not supplied to region 72. Therefore, as shown in Figure 4(B), the low-resistance region 51na is not formed in region 72. On the other hand, when the impurity elements are supplied before the formation of the insulating layer 88, the low-resistance region 51na is formed in region 72 as shown in Figure 4(C). Even when the impurity elements are supplied after the formation of the insulating layer 88, the low-resistance region 51na may be formed in at least a part of region 72. For example, after supplying impurity elements to the semiconductor layer 51, heat treatment may be performed, causing the impurity elements to diffuse into region 72, and the low-resistance region 51na may be formed in at least a part of region 72. Similarly, although not shown in Figure 4(B), the low-resistance region 51nb may be formed in at least a part of region 72.

[0124] When supplying impurity elements to the semiconductor layer 51 using methods such as ion implantation, ion doping, or plasma immersion ion implantation, it is preferable to do so after the formation of the insulating layer 88. This suppresses the impurity elements from penetrating the semiconductor layer 51 and being supplied to, for example, the insulating layer 62. When supplying impurity elements to the semiconductor layer 51 after the formation of the insulating layer 88, the film thickness of the insulating layer 88 is controlled so that the impurity elements are supplied to the semiconductor layer 51 but do not penetrate it.

[0125] For example, when supplying impurity elements to the semiconductor layer 51 using plasma treatment, or when supplying impurity elements to the semiconductor layer 51 by heat treatment in an atmosphere containing impurity elements, it is preferable to do so before the formation of the insulating layer 88. This prevents the impurity elements from being blocked by the insulating layer 88 and not being supplied to the semiconductor layer 51. Even when using ion implantation, ion doping, plasma immersion ion implantation, etc., if the amount of impurity elements penetrating the semiconductor layer 51 is sufficiently small, the impurity elements may be supplied to the semiconductor layer 51 before the formation of the insulating layer 88. Furthermore, even when using plasma treatment or heat treatment in an atmosphere containing impurity elements, if the impurity elements can permeate the insulating layer 88, the impurity elements may be supplied to the semiconductor layer 51 after the formation of the insulating layer 88.

[0126] In the example shown in Figure 4(B), it is easier to prevent impurity elements contained in the low-resistance region 51na from contaminating the channel-forming region 51i compared to the example shown in Figure 4(C). Similarly, although not shown in Figure 4(B), it is easier to prevent impurity elements contained in the low-resistance region 51nb from contaminating the channel-forming region 51i. As a result, the reliability of the semiconductor device can be improved. On the other hand, in the example shown in Figure 4(C), the distance between the channel-forming region 51i and the low-resistance region 51na can be shortened compared to the example shown in Figure 4(B). Similarly, although not shown in Figure 4(C), the distance between the channel-forming region 51i and the low-resistance region 51nb can be shortened. As a result, the on-current of the transistor 50 can be increased. Therefore, the operating speed of the semiconductor device can be increased.

[0127] In the drawings shown below, unless otherwise specified, examples are shown in which impurity elements are supplied to the semiconductor layer 51 after the formation of the insulating layer 88. That is, examples are shown in which low-resistance regions such as low-resistance region 51na and low-resistance region 51nb are not provided in region 72 of the semiconductor layer 51. However, in the transistors disclosed in the drawings shown below, the supply of impurity elements to the semiconductor layer 51 may also be performed before the formation of the insulating layer 88. That is, in the semiconductor layer 51, low-resistance regions such as low-resistance region 51na and low-resistance region 51nb may be provided in region 72.

[0128] When an indium oxide film is used as the semiconductor layer 51, it is preferable that the semiconductor layer 51 is crystalline. For example, it is preferable that the semiconductor layer 51 has crystal grains. Examples of films having crystal grains include single-crystal films, polycrystalline films, and amorphous films containing crystal grains. A polycrystalline film is composed of two or more crystal grains, while a single-crystal film can be considered to be composed of one crystal grain. In polycrystalline films, crystal grain boundaries (also called grain boundaries) are observed, whereas in single-crystal films, crystal grain boundaries are not observed.

[0129] In the channel formation region 51i, unlike polycrystalline films, no grain boundaries are observed in single-crystal films. Impurities that inhibit carrier flow (typically insulating impurities, insulating oxides, etc.) tend to segregate at grain boundaries. Therefore, if grain boundaries are present in the channel formation region 51i, the variation in the characteristics of the transistor 50 at the grain boundaries becomes large. On the other hand, in a single-crystal film according to one aspect of the present invention, no grain boundaries are observed in the channel formation region 51i, so the variation in the characteristics of the transistor 50 caused by these grain boundaries can be suppressed. Furthermore, by using a single-crystal film as the semiconductor layer 51, carrier scattering at the grain boundaries can be suppressed. Therefore, the transistor 50 can be a transistor with high field-effect mobility. In addition, the transistor 50 can be a highly reliable transistor.

[0130] Furthermore, in this specification, a semiconductor layer in which no grain boundaries are observed in the channel formation region, a semiconductor layer in which the channel formation region is contained within a single crystal grain, or a semiconductor layer in which the crystal axis directions are the same in at least two regions within the channel formation region can be called a single crystal film. Alternatively, a semiconductor layer in which at least one crystal orientation is oriented in one direction in the channel formation region can be called a single crystal film. In the above cases, the grain size of the crystal grains can be made larger than both the channel length and channel width of the transistor. Note that if the grain size of the crystal grains of a semiconductor layer is larger than both the channel length and channel width of the transistor, the semiconductor layer may be considered a single crystal film.

[0131] In this specification, indium oxide having at least a crystalline portion or crystalline region in a film is referred to as crystalline indium oxide (Crystal IO) or crystalline indium oxide (Crystalline IO). Examples of Crystal IO or Crystalline IO include single-crystal indium oxide, polycrystalline indium oxide, and microcrystalline indium oxide.

[0132] The semiconductor layer 51 may be a polycrystalline film or an amorphous film containing crystal grains. In this case, it is preferable that no crystal grain boundaries are observed or that there are few grain boundary components in the channel formation region 51i. For example, by having one crystal grain located in the channel formation region 51i, a configuration can be achieved in which no crystal grain boundaries are observed in the channel formation region 51i. Even with such a configuration, the same effects as the configuration in which the indium oxide film is a single crystal film can be achieved.

[0133] The crystallinity of the semiconductor layer 51 can be analyzed, for example, by X-ray diffraction (XRD), transmission electron microscopy (TEM), or electron diffraction (ED). Alternatively, a combination of these methods may be used for the analysis.

[0134] Crystal grains can be identified, for example, in high-resolution TEM images. Furthermore, crystal grain boundaries can sometimes be identified, for example, in high-resolution TEM images. In other words, crystal grains and crystal grain boundaries can sometimes be observed in high-resolution TEM images of crystalline films. The overall magnification when acquiring TEM images is preferably 2 million times or more, and more preferably 4 million times or more.

[0135] One method for crystallizing the semiconductor layer 51 is to perform a heat treatment after forming the semiconductor layer 51. However, if this heat treatment is performed after forming the conductive layer that functions as the other of the source electrode and drain electrode of the transistor 50, oxygen contained in the semiconductor layer 51 and oxygen contained in the heat treatment atmosphere may be absorbed by the conductive layer, causing it to oxidize. As a result, the electrical resistance of the conductive layer that functions as the other of the source electrode and drain electrode of the transistor 50 may increase.

[0136] In one aspect of the present invention, a conductive layer that functions as the other of the source electrode and drain electrode is formed after the formation of the semiconductor layer 51. Therefore, while crystallizing the semiconductor layer 51, oxidation of the conductive layer, for example, can be suppressed. As a result, a transistor exhibiting good electrical characteristics and high reliability can be provided. Furthermore, a highly reliable semiconductor device can be provided.

[0137] Furthermore, in one aspect of the present invention, after supplying impurity elements to the semiconductor layer 51, conductive layers 58a and 58b, which function as the source electrode and drain electrode of the transistor 50, are formed. This makes it possible to reduce the contact resistance between the semiconductor layer 51 and conductive layer 58a, and the contact resistance between the semiconductor layer 51 and conductive layer 58b, compared to the case where no impurity elements are supplied to the semiconductor layer 51. As a result, the on-current of the transistor 50 can be increased. Also, as mentioned above, by increasing the on-current of the transistor 50, the transistor 50 can obtain high frequency characteristics. Therefore, a semiconductor device with a high operating speed can be provided.

[0138] In addition, the semiconductor layer 51 may crystallize during its deposition. For example, the semiconductor layer 51 may crystallize due to the heat applied during deposition. If the semiconductor layer 51 crystallizes during deposition, it is not necessary to perform heat treatment after the formation of the semiconductor layer 51. Furthermore, if the semiconductor layer 51 is formed after the formation of a conductive layer that functions as the source electrode and the other drain electrode of the transistor 50, even if heat treatment after the formation of the semiconductor layer 51 is not performed, the conductive layer may oxidize, for example, due to the heat applied during the deposition of the semiconductor layer 51.

[0139] OS transistors have oxygen vacancies (V) in the channel formation region of an oxide semiconductor. O The presence of oxygen vacancies and impurities can easily lead to fluctuations in electrical properties and reduced reliability. O H can generate electrons that act as carriers. Therefore, if oxygen vacancies and impurities are present in the channel formation region of an oxide semiconductor, the OS transistor is likely to exhibit normally-on characteristics. Consequently, it is preferable that oxygen vacancies and impurities are reduced as much as possible in the channel formation region of an oxide semiconductor. In other words, it is preferable that the carrier concentration in the channel formation region of an oxide semiconductor is reduced and that it is i-type (intrinsic) or substantially i-type.

[0140] On the other hand, the source and drain regions of an OS transistor have more oxygen vacancies than the channel formation region. O It is preferable that the carrier concentration increases and the resistance decreases due to a high concentration of H, or a high concentration of impurities such as hydrogen, nitrogen, or metal elements. In other words, it is preferable that the source region and drain region of an OS transistor have a higher carrier concentration and be an n-type region (low-resistance region) compared to the channel formation region.

[0141] Therefore, in one aspect of the present invention, an insulating film having barrier properties against oxygen is used as the insulating layer 74. This suppresses the diffusion of oxygen contained in the semiconductor layer 51, specifically the channel formation region 51i, into the insulating layer 62, thereby preventing the formation of oxygen vacancies in the channel formation region 51i. Thus, fluctuations in the electrical characteristics of the transistor 50 can be suppressed, and reliability can be improved. Consequently, a highly reliable semiconductor device can be provided.

[0142] For example, an insulating film having gallium and oxygen can be used as the insulating layer 74. Alternatively, an insulating film having aluminum and oxygen can be used as the insulating layer 74. For example, gallium oxide or aluminum oxide can be used as the insulating layer 74.

[0143] It is particularly preferable to use gallium oxide as the insulating layer 74. The ionic radius of gallium is close to that of indium compared to that of aluminum. In other words, the difference between the ionic radii of indium and gallium is smaller than the difference between the ionic radii of indium and aluminum. Therefore, when indium oxide is used as the semiconductor layer 51, using gallium oxide as the insulating layer 74 increases the frequency of bonding between the indium atoms in the semiconductor layer 51 and the gallium atoms in the insulating layer 74 via oxygen atoms. Thus, it is possible to suppress the generation of oxygen vacancies or oxygen with dangling bonds at the interface between the semiconductor layer 51 and the insulating layer 74.

[0144] Figures 1(B) and 3(A) to 4(C) show an example in which the insulating layer 74 has a two-layer structure consisting of insulating layer 74_1 and insulating layer 74_2 on top of insulating layer 74_1. Insulating layer 74_2 is provided on the inside of the opening 63 (opposite the side wall of the opening 63) from insulating layer 74_1.

[0145] In this specification, the side wall of an opening refers to the side surface within the opening of the layer in which the opening is formed. Similarly, the side wall of a recess refers to the side surface within the recess of the layer in which the recess is formed.

[0146] The insulating layer 74_1 is provided so as to cover the side and lower end of the insulating layer 74_2. Specifically, the insulating layer 74_1 is provided so as to cover the side and lower end of the insulating layer 74_2 opposite to the semiconductor layer 51. More specifically, the insulating layer 74_1 is provided so as to cover the side and lower end of the insulating layer 74_2 opposite to the side in contact with the semiconductor layer 51. The side edge of the insulating layer 74_1 can be made to coincide with the side of the insulating layer 74_2.

[0147] As the insulating layer 74_2, the same material that can be used for the insulating layer 74 described above can be used. This allows the insulating layer 74_2 having a region in contact with the channel formation region 51i of the semiconductor layer 51 to have barrier properties against oxygen. This suppresses the formation of oxygen vacancies in the channel formation region 51i. Therefore, as described above, fluctuations in the electrical characteristics of the transistor 50 can be suppressed and reliability can be improved. Thus, a highly reliable semiconductor device can be provided.

[0148] As the insulating layer 74_1, an insulating film having the function of capturing or fixing hydrogen (also called an insulating film having a gettering function) is used. This allows hydrogen contained in the semiconductor layer 51 to be captured or fixed. Therefore, the amount of hydrogen contained in the semiconductor layer 51 can be reduced. Consequently, the formation of VoH in the semiconductor layer 51, specifically in the channel formation region 51i, can be suppressed. As a result, it is possible to prevent the transistor 50 from exhibiting normally-on characteristics. Therefore, a transistor exhibiting good electrical characteristics and high reliability can be provided. Furthermore, a highly reliable semiconductor device can be provided.

[0149] For example, an insulating film having hafnium and oxygen can be used as the insulating layer 74_1. Specifically, as the insulating layer 74_1, hafnium oxide, hafnium zirconium oxide, an oxide containing hafnium and silicon, etc., can be used.

[0150] Here, gallium oxide and aluminum oxide are insulating materials with lower hydrogen barrier properties than, for example, silicon nitride. Therefore, even when an insulating layer 74_2 is provided in a semiconductor device according to one embodiment of the present invention, by using gallium oxide or aluminum oxide in the insulating layer 74_2, for example, hydrogen in the semiconductor layer 51 can permeate through the insulating layer 74_2. Thus, hydrogen in the semiconductor layer 51 can be captured or fixed to the insulating layer 74_1.

[0151] The insulating layer 74 may be a single-layer structure or a laminated structure of three or more layers. For example, the insulating layer 74 can be a single-layer structure of insulating layer 74_2.

[0152] Figures 3(A) and 3(B) show an example in which the conductive layer 55 has a recess (hereinafter sometimes referred to as the first recess) that overlaps with the insulating layer 74. By having the first recess in the conductive layer 55, the volume of the insulating layer 74 can be increased compared to the case in which the first recess does not exist. Furthermore, the contact area between the insulating layer 74 and the semiconductor layer 51 can be increased. Therefore, the diffusion of oxygen contained in the semiconductor layer 51 into the insulating layer 62 can be effectively suppressed.

[0153] Furthermore, Figures 3(A) and 3(B) show an example in which the conductive layer 55 has a recess that overlaps with the opening 63 but does not overlap with the insulating layer 74. To distinguish it from the first recess mentioned above, this recess is sometimes referred to as the second recess. By having the second recess in the conductive layer 55, the height of the bottom surface of the insulating layer 52 and the height of the bottom surface of the conductive layer 53 in the region overlapping with the opening 63 can be made lower than in the case without the second recess. For example, the height of the bottom surface of the insulating layer 52 and the height of the bottom surface of the conductive layer 53 in the region overlapping with the opening 63 can be made lower than the height of the upper surface of the conductive layer 55 in contact with the insulating layer 62. As a result, the gate electric field is more easily applied to the semiconductor layer 51, and the electrical characteristics of the transistor 50 can be improved.

[0154] Furthermore, because the conductive layer 55 has a second recess, the semiconductor layer 51 contacts not only the bottom of the second recess (the upper surface of the conductive layer 55) but also the side walls of the second recess. Therefore, the contact area between the semiconductor layer 51 and the conductive layer 55 can be increased. Consequently, the contact resistance between the semiconductor layer 51 and the conductive layer 55 can be reduced.

[0155] In the semiconductor device shown in Figures 3(A) and 3(B), the conductive layer 55 has a first recess and a second recess located inside the first recess. The second recess is deeper than the first recess. In other words, the bottom surface of the second recess is located below (towards the insulating layer 87) the bottom surface of the first recess. The first recess is provided in the conductive layer 55 when forming the opening 63. Furthermore, as will be described in detail later, the second recess is provided in the conductive layer 55 when forming the insulating layer 74. Therefore, in the example shown in Figures 3(A) and 3(B), the side wall of the first recess coincides with the side surface of the insulating layer 62 in the opening 63. Also, the side wall of the second recess coincides with the side surface of the insulating layer 74 on the semiconductor layer 51 side.

[0156] Preferably, the bottom of the second recess has a curved portion. The semiconductor layer 51, insulating layer 52, etc., provided on the curved portion may also have a curved portion. This reduces the concentration of the electric field on the insulating layer 52 near the second recess, improves the dielectric strength of the transistor 50, and suppresses electrostatic discharge breakdown of the transistor 50. Therefore, the reliability of the semiconductor device can be improved.

[0157] Furthermore, the conductive layer 55 does not necessarily have the first recess. Also, the conductive layer 55 does not necessarily have the first recess and the second recess. Moreover, the height of the first recess from the reference surface of the conductive layer 55 may be the same as or approximately the same as the height of the second recess from the reference surface.

[0158] The conductive layer 55 can be made from the conductive material described in the [Conductive Layer] section below. In particular, it is preferable to use a conductive material that is resistant to oxidation, a material that maintains conductivity even when absorbing oxygen, or a conductive material that has the function of suppressing the diffusion of oxygen as the conductive layer 55. Examples of such conductive materials include conductive materials containing nitrogen and conductive materials containing oxygen (also called oxide conductors). This makes it possible to suppress a decrease in the conductivity of the conductive layer 55.

[0159] The conductive layer 55 is particularly preferably an oxide conductor. The conductive layer 55 preferably contains at least one of the following: indium tin oxide (In-Sn oxide, also known as ITO), silicon-containing ITO (In-Sn-Si oxide, also known as ITSO), indium zinc oxide (In-Zn oxide), and indium titanium oxide (In-Ti oxide). These materials are preferred because, compared to materials composed of metallic elements (also known as metallic materials), they maintain conductivity even after absorbing oxygen. Furthermore, they are preferred because they can reduce the contact resistance between the conductive layer 55 and the semiconductor layer 51.

[0160] Figures 3(A) and 3(B) show an example in which the conductive layer 55 has a two-layer structure consisting of a conductive layer 55_1 and a conductive layer 55_2 on the conductive layer 55_1. The conductive layer 55_2, which has a region in contact with the semiconductor layer 51, preferably has the above-mentioned oxide conductor. This makes it possible to lower the contact resistance between the conductive layer 55 and the semiconductor layer 51. Furthermore, the conductive layer 55_1, which does not contact the semiconductor layer 51, preferably has a material with higher conductivity than the conductive layer 55_2. This makes it possible to make the conductivity of the conductive layer 55_1 higher than that of the conductive layer 55_2. Thus, the conductivity of the conductive layer 55 can be made higher than when the conductive layer 55 does not have a conductive layer 55_1. The conductive layer 55_1 can have at least one of, for example, tungsten, copper, and aluminum. Here, by configuring the second recess of the conductive layer 55 so that it does not reach the conductive layer 55_1, it is possible to prevent the semiconductor layer 51 from coming into contact with the conductive layer 55_1. This prevents the conductive layer 55_1 from being oxidized by oxygen contained in the semiconductor layer 51, thereby preventing an increase in the contact resistance between the semiconductor layer 51 and the conductive layer 55. The conductive layer 55 may also have a laminated structure of three or more layers. For example, it can have a three-layer structure consisting of a titanium nitride film or a tungsten nitride film, a tungsten film, a copper film, or an aluminum film, and a film having the oxide conductor described above.

[0161] Figures 2(A), 2(B), and 4(A) show an example where the opening 63 is circular in plan view. By making it circular, the processing accuracy when forming the opening 63 can be improved as described above. Also, by forming the opening 63 to be circular in plan view, the semiconductor layer 51, insulating layer 52, and conductive layer 53 are arranged concentrically, as shown in Figure 4(A). As a result, the distance between the conductive layer 53 and the semiconductor layer 51 becomes approximately uniform, so that the gate electric field can be applied to the semiconductor layer 51 approximately uniformly. In addition, the side surface of the conductive layer 53 located at the center of the opening 63 faces the side surface of the semiconductor layer 51 via the insulating layer 52. In other words, in plan view, the entire perimeter of the semiconductor layer 51 becomes the channel formation region 51i. At this time, the channel width of the transistor 50 is determined by the length of the outer circumference, the length of the inner circumference, or the length midway between the outer and inner circumferences of the semiconductor layer 51. If the opening 63 is circular in plan view, the channel width can be calculated, for example, by multiplying the value obtained by subtracting twice the thickness of the insulating layer 74 from the width (diameter) of the opening 63 by pi (π).

[0162] By increasing the width of the aperture 63, the channel width per unit area can be increased, and the on-current can be increased. On the other hand, by decreasing the width of the aperture 63, the area occupied by the transistor 50 can be reduced, and the semiconductor device can be highly integrated. The area occupied by the transistor 50, for example, the area of ​​the transistor 50 in a plan view, is roughly determined according to the width of the aperture 63.

[0163] The width of the opening 63 is determined by the thickness of the insulating layer 74, semiconductor layer 51, insulating layer 52, and conductive layer 53 provided inside the opening 63. The width of the opening 63 is preferably, for example, 5 nm to 100 nm, more preferably 10 nm to 60 nm, more preferably 20 nm to 50 nm, more preferably 20 nm to 40 nm, and even more preferably 20 nm to 30 nm.

[0164] In plan view, the opening 63 is not limited to being circular, but can be, for example, a roughly circular or elliptical shape, a triangle, a quadrilateral (including rectangles, rhombuses, and squares), a pentagon, a star polygon, or any of these polygons with rounded corners. Note that the circular shape is not limited to a perfect circle. Furthermore, the polygon can be either a concave polygon (a polygon with at least one interior angle exceeding 180 degrees) or a convex polygon (a polygon with all interior angles of 180 degrees or less).

[0165] The channel length of transistor 50 is the distance between the source region and the drain region. In other words, the channel length of transistor 50 is approximately determined by the thickness of the insulating layer 62 on the conductive layer 55, or the height of the insulating layer 74 on the conductive layer 55. Therefore, the channel length of transistor 50 does not affect the area occupied by transistor 50, for example, the area of ​​transistor 50 in a plan view. The channel length of transistor 50 can be considered, for example, in a cross-sectional view, as the distance between the region of the semiconductor layer 51 that is at the same height as the bottom surface of the conductive layer 53 and the region that overlaps with the side edge of the conductive layer 53.

[0166] The height of the insulating layer 62 on the conductive layer 55 can be 0.1 nm to 500 nm, 1 nm to 300 nm, 5 nm to 100 nm, 5 nm to 60 nm, 5 nm to 50 nm, 5 nm to 40 nm, 5 nm to 30 nm, 5 nm to 20 nm, or 5 nm to 10 nm. Typically, it can be 1 nm to 300 nm, preferably 5 nm to 100 nm. This improves productivity and yield in the formation of the insulating layer 62, the formation of the opening 63, etc. In addition, the on-current of the transistor 50 can be increased, improving the frequency characteristics.

[0167] As mentioned above, the conductive layer 59 intersects with the conductive layer 53 in a plan view, and is provided so as to be orthogonal or nearly orthogonal. The transistor 50 is provided at the intersection of the conductive layer 59 and the conductive layer 53. Thus, the transistor 50 can be said to have a structure that allows for high integration.

[0168] Figure 5(A) is a plan view showing an example of the semiconductor device shown in Figure 2(A) without conductive layers 58a, 58b, and 59. In other words, Figure 5(A) shows an example where the transistor 50 does not have an upper electrode. Figure 5(B) is a cross-sectional view between the dashed-dotted line A1 and A2 shown in Figure 5(A).

[0169] In the semiconductor device shown in Figures 5(A) and 5(B), the semiconductor layer 51 has a region that extends in a predetermined direction, similar to the conductive layer 59 shown in Figures 1(A) to 2(A), 3(A), and 3(B), for example, extending in the Y direction. With this configuration, the source region and the other drain region of the transistor 50 can be connected to, for example, another semiconductor element without providing conductive layers 58a, 58b, and 59 in the semiconductor device. The low-resistance region 51na and the low-resistance region 51nb can be used as substitutes for the other source electrode and drain electrode of the transistor 50. In addition, although Figures 5(A) and 5(B) show an example where the low-resistance region 51na and the low-resistance region 51nb are separated by the conductive layer 53 in a plan view, the low-resistance region 51na and the low-resistance region 51nb may be a single region without separation.

[0170] In one embodiment of the present invention, a semiconductor device without conductive layers 58a, 58b, and 59 can be configured to reduce the number of manufacturing steps for the semiconductor device compared to a configuration with conductive layers 58a, 58b, and 59. Therefore, a semiconductor device with lower manufacturing costs can be provided. On the other hand, the electrical resistivity of conductive layers 58a, 58b, and 59 can be made lower than the electrical resistivity of the low-resistance region 51na and low-resistance region 51nb of the semiconductor layer 51. Therefore, by configuring the semiconductor device with conductive layers 58a, 58b, and 59, the on-current of the transistor 50 can be increased compared to a configuration without conductive layers 58a, 58b, and 59.

[0171] In planar transistors, where the source and drain regions are located on the same plane, it is difficult to extend the semiconductor layer in a predetermined direction and connect the source or drain region of the transistor to, for example, another semiconductor element without using routing wires. On the other hand, transistor 50 has its source and drain regions located on different planes. Therefore, the other of the source and drain regions of transistor 50 can be connected to, for example, another semiconductor element without using routing wires.

[0172] <Example of semiconductor device configuration 2> The following describes a configuration example of a semiconductor device according to one aspect of the present invention, different from those shown in Figures 1(A) to 5(B). Note that explanations of parts that overlap with the above will be omitted, and only the differences will be described in detail. Furthermore, even if components differ in position or shape, if their function is the same, they may be given the same reference numeral and their explanation may be omitted.

[0173] Figure 6(A) is a perspective view showing an example configuration of a semiconductor device having transistor 50A. Figure 6(B) is a perspective view obtained by cutting off a portion of Figure 6(A). Figure 7(A) is a plan view of the semiconductor device shown in Figures 6(A) and 6(B). Figure 7(B) is a plan view obtained by omitting some elements from Figure 7(A).

[0174] Figure 8(A) is a cross-sectional view between the dashed lines A1 and A2 shown in Figures 7(A) and 7(B). Figure 8(B) is a cross-sectional view between the dashed lines B1 and B2 shown in Figures 7(A) and 7(B). For the cross-sectional view between the dashed lines C1 and C2 shown in Figure 8(A), please refer to Figure 4(A).

[0175] The semiconductor devices shown in Figures 6(A) to 8(B) differ primarily from those shown in Figures 5(A) and 5(B) in that they have a conductive layer 77. In Figure 7(B), the conductive layer 77 and conductive layer 53 shown in Figure 7(A) are omitted.

[0176] In transistor 50A, the configuration from the conductive layer 55 to the insulating layer 52 is the same as that of transistor 50 shown in Figures 5(A) and 5(B), so a detailed explanation is omitted.

[0177] As shown in Figures 8(A) and 8(B), the insulating layer 88 is provided on the insulating layer 52. The insulating layer 88 also has an opening 66 that reaches the insulating layer 52, with a region that overlaps with the opening 63. The side surface of the insulating layer 88 at the opening 66 is provided to be aligned with the side surface of the conductive layer 53. The lower surface of the insulating layer 88 is provided to be aligned with the upper surface of the insulating layer 52. Therefore, the side surface of the insulating layer 88 at the opening 66 is included in the region 71a shown in Figures 4(B) and 4(C). The lower surface of the insulating layer 88 is included in the region 71b shown in Figures 4(B) and 4(C). In a plan view, the region 71a of the insulating layer 88 is provided to surround the side surface of the conductive layer 53 that is located outside the opening 63.

[0178] In a semiconductor device having transistor 50A, the conductive layer 53 is provided in an island shape. The conductive layer 53 has a region located inside the opening 63 and a region located inside the opening 66. The conductive layer 53 can be provided so as to embed the openings 63 and 66. Inside the opening 63, the conductive layer 53 has a region in contact with the insulating layer 52. Also, inside the opening 66, the conductive layer 53 has a region in contact with the insulating layer 88.

[0179] In transistor 50A, the low-resistance region of the semiconductor layer 51 is provided so as to surround the island-shaped conductive layer 53 in a plan view. The low-resistance region provided in the semiconductor layer 51 of transistor 50A is referred to as the low-resistance region 51n. At least a portion of the low-resistance region 51n functions as the other of the source region and drain region of transistor 50A.

[0180] It is preferable that the upper surfaces of the insulating layer 86 and the conductive layer 53 are flattened. This allows the conductive layer 77 to be provided on a flat surface. Therefore, it is possible to prevent the formation of irregularities in the conductive layer 77, which would otherwise result in areas with locally thinner film thicknesses. When the upper surfaces of the insulating layer 86 and the conductive layer 53 are flattened, the height of the upper surface of the insulating layer 86 from the reference plane is equal to or approximately equal to the height of the upper surface of the conductive layer 53 from the reference plane. Also, the height of the upper end of the insulating layer 88 from the reference plane is equal to or approximately equal to the height of the upper surface of the conductive layer 53 and the height of the upper surface of the insulating layer 86 from the reference plane.

[0181] The conductive layer 77 has a region in contact with the upper surface of the conductive layer 53, a region located on the insulating layer 88, and a region located on the insulating layer 86. The conductive layer 77 also has a region located on the opening 66. Since the conductive layer 77 has a region in contact with the conductive layer 53, the conductive layer 53 and the conductive layer 77 are connected. The conductive layer 77 may also be considered a component of the transistor 50A.

[0182] The conductive layer 77 functions as a routing wire for the gate electrode of the transistor 50A. The conductive layer 77 functions as gate wiring. Figures 6(A) to 8(B) show an example in which the conductive layer 77 extends in the X direction, similar to the conductive layer 53 shown in Figures 5(A) and 5(B). Also, Figures 6(A) to 8(B) show an example in which the semiconductor layer 51 extends in the Y direction, similar to Figures 5(A) and 5(B). That is, Figures 6(A) to 8(B) show an example in which the conductive layer 77 intersects with the semiconductor layer 51 in a plan view, for example, orthogonal or nearly orthogonal.

[0183] The conductive layer 77 can be made of a conductive material as described in the [Conductive Layer] section below. For example, the conductive layer 77 can be made of a high-melting-point material such as tungsten or molybdenum that provides both heat resistance and conductivity. Alternatively, a low-resistance conductive material such as aluminum or copper can be used. Using a low-resistance conductive material can reduce the wiring resistance.

[0184] The region of the conductive layer 77 that does not overlap with the opening 66 is mainly located on the insulating layer 86. Therefore, the conductive layer 77 overlaps with the semiconductor layer 51 mainly via the insulating layers 86 and 88. This allows for a greater physical distance between the gate wiring and the semiconductor layer 51 compared to the semiconductor devices shown in Figures 5(A) and 5(B). As a result, the parasitic capacitance between the conductive layer 77 and the semiconductor layer 51 can be made smaller than the parasitic capacitance between the conductive layer 53 and the semiconductor layer 51 in the semiconductor device having the transistor 50. Therefore, the transistor 50A can achieve a larger on-current than the transistor 50 shown in Figures 5(A) and 5(B). As a result, the transistor 50A can obtain higher frequency characteristics than the transistor 50 shown in Figures 5(A) and 5(B). Therefore, the semiconductor device having the transistor 50A can be a semiconductor device with a faster operating speed than the semiconductor device shown in Figures 5(A) and 5(B). On the other hand, the semiconductor devices shown in Figures 5(A) and 5(B) require fewer manufacturing steps than the semiconductor device having transistor 50A.

[0185] Although Figures 7(A) and 7(B) show an example where the opening 66 is circular in a plan view, the present invention is not limited to this. The shapes applicable to the opening 66 are the same as the shapes applicable to the opening 63 described above.

[0186] Figures 9(A) and 9(B) show examples in which the insulating layer 52 shown in Figures 8(A) and 8(B), respectively, has a region located inside the opening 66. The insulating layer 52 is provided inside the opening 66 so as to be along the side surface of the insulating layer 88 in the opening 66. The conductive layer 53 can also be provided inside the opening 66 so as to be in contact with the side surface of the insulating layer 52. In the transistor 50A shown in Figures 9(A) and 9(B), the upper surface of the semiconductor layer 51 has a region in contact with the insulating layer 88.

[0187] In the semiconductor devices shown in Figures 9(A) and 9(B), impurity elements for forming the low-resistance region 51n are supplied to the semiconductor layer 51 without going through the insulating layer 52. On the other hand, in the semiconductor devices shown in Figures 8(A) and 8(B), impurity elements are supplied to the semiconductor layer 51 via the insulating layer 52.

[0188] Figures 10(A) and 10(B) show examples of semiconductor devices shown in Figures 3(A) and 8(A), respectively, that do not have an insulating layer 74. When a semiconductor device does not have an insulating layer 74, the number of manufacturing steps for the semiconductor device can be reduced compared to when an insulating layer 74 is present. Therefore, a semiconductor device with lower manufacturing costs can be provided. Here, when a semiconductor device does not have an insulating layer 74, the semiconductor layer 51 may have a region that is in contact with the side surface of the opening 63 of the insulating layer 62. Also, when a semiconductor device does not have an insulating layer 74, the channel length of transistor 50 and the channel length of transistor 50A can be considered as the distance between the edge of the region in contact with, for example, the conductive layer 55, and the region that overlaps with the side edge of the conductive layer 53 in the semiconductor layer 51. Note that the semiconductor devices shown in Figures 5(A) and 5(B), and the semiconductor devices shown in Figures 9(A) and 9(B), do not have an insulating layer 74. Also, the semiconductor devices shown hereafter do not have an insulating layer 74.

[0189] The following describes an example of the layering configuration of each layer in a semiconductor device according to one aspect of the present invention.

[0190] <Example of layered configuration> Figure 11(A) shows an example where the insulating layer 52 shown in Figure 3(A) has a three-layer structure consisting of an insulating layer 52_1 in contact with the semiconductor layer 51, an insulating layer 52_2 on insulating layer 52_1, and an insulating layer 52_3 on insulating layer 52_2.

[0191] The insulating layer 52_1 preferably has barrier properties against oxygen. This suppresses the diffusion of oxygen contained in the semiconductor layer 51 into the conductive layer 53 and the oxidation of the conductive layer 53. The insulating layer 52_1 can be made of the same material that can be used for the insulating layer 74_2. For example, gallium oxide or aluminum oxide is preferably used for the insulating layer 52_1, and gallium oxide is particularly preferred.

[0192] Furthermore, it is preferable to use a material with a high dielectric constant (high-k) for the insulating layer 52_1. By using a high-k material as the insulating layer 52_1, the potential applied to the conductive layer 53 during operation of the transistor 50 can be lowered while maintaining the physical thickness of the insulating layer 52, which functions as the gate insulating layer of the transistor 50. In addition, it becomes possible to thin the equivalent oxide thickness (EOT) of the insulating layer 52. As mentioned above, gallium oxide and aluminum oxide are also high-k materials and can therefore be suitably used for the insulating layer 52_1. In addition to gallium oxide and aluminum oxide, other high-k materials that can be used for the insulating layer 52_1 include, for example, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxidized nitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxidized nitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0193] For example, it is preferable to use a material with a low dielectric constant as the insulating layer 52_2. For example, it is preferable that the insulating layer 52_2 has a silicon oxide film or a silicon oxynitride film.

[0194] The insulating layer 52_3 preferably has barrier properties against hydrogen. This configuration suppresses the diffusion of hydrogen into the semiconductor layer 51. Furthermore, the insulating layer 52_3 preferably has barrier properties against oxygen. The insulating layer 52_3 is provided between the channel-forming region 51i and the conductive layer 53. This configuration suppresses the diffusion of oxygen contained in the channel-forming region 51i into the conductive layer 53, preventing the formation of oxygen vacancies in the channel-forming region 51i. It also suppresses the diffusion of oxygen contained in the semiconductor layer 51 into the conductive layer 53, preventing the oxidation of the conductive layer 53. The insulating layer 52_3 preferably has less oxygen permeability than the insulating layer 52_2. Furthermore, the insulating layer 52_3 preferably has a function to suppress hydrogen diffusion. This prevents impurities such as hydrogen contained in the conductive layer 53 from diffusing into the semiconductor layer 51. For example, silicon nitride is preferably used as the insulating layer 52_3.

[0195] Figure 11(B) shows an example in which an insulating layer 52_4 is provided between insulating layer 52_2 and insulating layer 52_3 shown in Figure 11(A). As insulating layer 52_4, an insulating material applicable to insulating layer 74_1 can be used. For example, by providing an insulating layer 52_4 having the function of capturing or fixing hydrogen between insulating layer 52_3 and insulating layer 52_2, hydrogen contained in insulating layer 52_2, etc., can be captured or fixed.

[0196] Preferably, the insulating layer 52 has a four-layer structure in which a gallium oxide film, a silicon oxide film, a hafnium oxide film, and a silicon nitride film are stacked in that order from the semiconductor layer 51 side. With this configuration, hydrogen in the semiconductor layer 51 diffuses into the insulating layer 52_4, and the hydrogen can be captured or fixed there. Therefore, the hydrogen concentration in the semiconductor layer 51 can be reduced.

[0197] The insulating layer 52 is preferably a thin film. For example, by setting the thickness of the insulating layer 52 to 1 nm or more and 20 nm or less, preferably 3 nm or more and 10 nm or less, the subthreshold swing value (also called the S value) can be reduced. The S value refers to the amount of change in gate voltage when the drain current is changed by one order of magnitude while the drain voltage is constant in the subthreshold region.

[0198] Furthermore, the film thickness of each layer constituting the insulating layer 52 is preferably 0.1 nm to 20 nm, more preferably 0.1 nm to 10 nm, more preferably 0.1 nm to 5.0 nm, more preferably 0.5 nm to 5.0 nm, more preferably 1.0 nm to less than 5.0 nm, and even more preferably 1.0 nm to 3.0 nm. It is preferable that each layer constituting the insulating layer 52 has at least a portion of the above-mentioned film thickness region.

[0199] Furthermore, in the four-layer insulating layer 52, the insulating layer 52_3 may be omitted. For example, insulating layer 52_1 can be an insulating layer having the function of capturing or fixing oxygen, insulating layer 52_2 can be an insulating layer made of a material with a low dielectric constant, and insulating layer 52_4 can be an insulating layer having the function of capturing or fixing hydrogen. Specifically, insulating layer 52 can be a three-layer structure in which an aluminum oxide film, a silicon oxide film, and a hafnium oxide film are stacked in that order from the semiconductor layer 51 side.

[0200] To make the thickness of insulating layers 52_1 to 52_4 as described above, it is preferable to deposit the films using the Atomic Layer Deposition (ALD) method. Furthermore, to form insulating layers 52_1 to 52_4 with good coverage inside the opening 63, it is preferable to deposit the films using the ALD method.

[0201] Furthermore, it is preferable to use the ALD process two or more times when forming the insulating layer 52 having a laminated structure of multiple insulating films. For example, it is preferable that two or more of the multiple insulating films of the insulating layer 52 are formed using the ALD process. By forming at least two or more insulating films using the ALD process, the coverage and uniformity of the film thickness of the insulating layer 52 can be improved. In addition, productivity can be increased by continuously forming, for example, two or more insulating films using the ALD process.

[0202] Although the above describes a configuration in which the insulating layer 52 has a three-layer or four-layer structure, the present invention is not limited to these. The insulating layer 52 can have at least one of the insulating layers 52_1 to 52_4. By configuring the insulating layer 52 with one, two, or three layers from the insulating layers 52_1 to 52_4, the manufacturing process of semiconductor devices can be simplified and productivity can be improved.

[0203] The laminated structure of the insulating layer 52 shown in Figure 11(A) and Figure 11(B) can also be applied to the transistor 50 shown in Figures 5(A) and 5(B). Furthermore, the laminated structure of the insulating layer 52 shown in Figure 11(A) and Figure 11(B) can also be applied to the transistor 50A. Moreover, it can also be applied to the insulating layer 52 of the transistors described below.

[0204] Figures 12(A) and 12(B) show examples where the semiconductor layer 51 shown in Figures 3(A) and 8(A), respectively, has a three-layer structure consisting of a semiconductor layer 51_1 in contact with the conductive layer 55_2, the insulating layer 74, etc., a semiconductor layer 51_2 on semiconductor layer 51_1, and a semiconductor layer 51_3 on semiconductor layer 51_2. Here, semiconductor layer 51_3 has a region in contact with the insulating layer 52.

[0205] The semiconductor layers 51_1, 51_2, and 51_3 can all contain indium and oxygen. For example, indium oxide can be used for all three semiconductor layers 51_1, 51_2, and 51_3. In this case, for example, the deposition conditions for semiconductor layer 51_2 can be different from those for semiconductor layers 51_1 and 51_3. However, the deposition conditions for semiconductor layer 51_1 and semiconductor layer 51_3 can be the same.

[0206] Semiconductor layer 51_1 and semiconductor layer 51_3 use films with higher film density and fewer defects than semiconductor layer 51_2. Semiconductor layer 51_2 uses a film with higher carrier mobility than semiconductor layer 51_1 and semiconductor layer 51_3.

[0207] As a result, transistors 50 and 50A can be made into transistors with high field-effect mobility and high reliability. Furthermore, by making the carrier mobility of the semiconductor layer 51_2 higher than the carrier mobility of the semiconductor layer 51_3 that is in contact with the insulating layer 52 inside the opening 63, the main path for carrier flow can be moved away from the interface between the insulating layer 52 and the semiconductor layer 51, compared to, for example, the case where the semiconductor layer 51_2 is in contact with the insulating layer 52 inside the opening 63. This reduces the effect of surface scattering. Therefore, for example, the on-current of transistors 50 and 50A can be increased. In addition, the field-effect mobility of transistors 50 and 50A can be increased.

[0208] Here, we will explain the reliability of transistors. One of the indicators for evaluating the reliability of a transistor is the GBT (Gate Bias Temperature) stress test, which involves applying an electric field to the gate and holding it at a high temperature. Among these, a test in which a positive potential (positive bias) is applied to the gate relative to the source potential and drain potential and held at a high temperature is called the PBTS (Positive Bias Temperature Stress) test, and a test in which a negative potential (negative bias) is applied to the gate and held at a high temperature is called the NBTS (Negative Bias Temperature Stress) test. Furthermore, PBTS and NBTS tests performed under light irradiation are called PBTIS (Positive Bias Temperature Illumination Stress) and NBTIS (Negative Bias Temperature Illumination Stress) tests, respectively.

[0209] In n-channel transistors, a positive potential is applied to the gate when the transistor is turned on (current is flowing). Therefore, the variation in the threshold voltage during PBTS testing is one of the important indicators of transistor reliability that should be considered.

[0210] Semiconductor layers 51_1 and 51_3 may contain indium, oxygen, and a second element that has a stronger bonding force with oxygen than indium. Specifically, indium oxide can be used for semiconductor layer 51_2, and indium oxide containing the second element can be used for semiconductor layers 51_1 and 51_3. This will result in oxygen vacancies and V near the surface of semiconductor layer 51. O The formation of H can be suppressed. Therefore, carrier scattering near the surface of the semiconductor layer 51, for example, near the surface of the semiconductor layer 51 on the insulating layer 52 side, can be reduced. Consequently, transistors 50 and 50A can be transistors with a large on-current.

[0211] The second element is preferably one or more selected from gallium, aluminum, yttrium, scandium, titanium, tungsten, molybdenum, tin, zirconium, hafnium, and tantalum. The second element is more preferably gallium, aluminum, yttrium, scandium, titanium, tungsten, molybdenum, or tin. The second element is even more preferably gallium, aluminum, yttrium, or scandium.

[0212] Gallium, aluminum, yttrium, and scandium primarily exist as trivalent cations, similar to indium atoms. Therefore, by using gallium, aluminum, yttrium, or scandium as the second element, the carrier concentration in semiconductor layers 51_1 and 51_3 can be kept low. When indium oxide is used as semiconductor layer 51, as shown in Embodiment 2, the lower the carrier concentration in semiconductor layer 51, the higher the field-effect mobility of transistors 50 and 50A can be. Thus, by using gallium, aluminum, yttrium, or scandium as the second element, transistors 50 and 50A can be made into transistors with high field-effect mobility.

[0213] Furthermore, titanium and tungsten have a stronger bonding force with oxygen compared to molybdenum and tin. Therefore, when titanium or tungsten is used as the second element contained in semiconductor layer 51_1 and semiconductor layer 51_3, oxygen vacancies and V are less likely to occur in semiconductor layer 51 than when molybdenum or tin is used. O The formation of H can be suppressed. On the other hand, molybdenum and tin have bond lengths with oxygen that are closer to the bond length between indium and oxygen compared to titanium and tungsten. Therefore, when molybdenum or tin is used as the second element, it is easier to maintain the crystal structure of semiconductor layer 51 even if the content of the second element in semiconductor layer 51_1 and semiconductor layer 51_3 is increased compared to when titanium or tungsten is used.

[0214] For example, indium oxide doped with gallium can be used for semiconductor layers 51_1 and 51_3, and indium oxide can be used for semiconductor layer 51_2. Alternatively, indium oxide doped with tungsten can be used for semiconductor layers 51_1 and 51_3, and indium oxide can be used for semiconductor layer 51_2.

[0215] For example, in the semiconductor layer 51_3, the ratio of the number of atoms of the second element to the sum of the number of atoms of indium and the second element is preferably 0.1% to 5%, and more preferably 0.5% to 3%. This prevents oxygen vacancies and V in the semiconductor layer 51_3 and near the interface between the semiconductor layer 51_3 and the insulating layer 52. O This suppresses the formation of H and reduces scattering near the surface of the semiconductor layer 51 on the insulating layer 52 side. Furthermore, the inclusion of the second element reduces the amount of carriers generated, preventing an increase in the carrier concentration of the semiconductor layer 51. Therefore, it is possible to suppress a decrease in the field-effect mobility of transistors 50 and 50A.

[0216] As mentioned above, aluminum atoms, gallium atoms, yttrium atoms, and scandium atoms in metal oxides mainly exist as trivalent cations, just like indium atoms. Therefore, when semiconductor layer 51_3 contains at least one of aluminum, gallium, yttrium, or scandium as the second element, the carrier concentration can be kept low even if the ratio of the number of atoms of the second element to the sum of the number of atoms of indium and the second element in semiconductor layer 51_3 is greater than the above range. This makes transistors 50 and 50A transistors with high field-effect mobility. However, in order to reduce scattering due to cation disorder, it is preferable to set the above ratio in semiconductor layer 51_3 within the above range. Here, the ratio of the number of atoms of the second element to the sum of the number of atoms of indium and the second element in semiconductor layer 51_1 can also be set to the same range as the ratio that can be taken in semiconductor layer 51_3.

[0217] The content of the second element in semiconductor layer 51_2 is lower than at least the content of the second element in semiconductor layer 51_1 and the content of the second element in semiconductor layer 51_3. For example, the ratio of the number of atoms of the second element to the sum of the number of atoms of indium and the second element in semiconductor layer 51_2 is preferably less than 0.1%. Furthermore, it is preferably below the detection limit in analysis using SIMS (also called SIMS analysis). The detection limit can be rephrased as background. The background in SIMS analysis differs for each element due to differences in ionization rate, detection sensitivity, etc., but when detecting metallic elements, it is approximately 1 × 10⁻⁶. 18 atoms / cm 3 This reduces the carrier concentration in the semiconductor layer 51_2, thereby increasing the field-effect mobility of transistors 50 and 50A. Furthermore, scattering originating from cation disorder in the semiconductor layer 51_2 can be reduced. Therefore, transistors with high on-current can be provided.

[0218] Furthermore, when indium oxide is used as semiconductor layer 51_2, and indium oxide containing a second element is used as semiconductor layers 51_1 and 51_3, the band gaps of semiconductor layers 51_1 and 51_3 may be larger than the band gap of semiconductor layer 51_2. Also, for example, the lower end of the conduction band of semiconductor layer 51_1 and semiconductor layer 51_3 may be located closer to the vacuum level than the lower end of the conduction band of semiconductor layer 51_2. In other words, the electron affinity of semiconductor layer 51_1 and semiconductor layer 51_3 may be smaller than the electron affinity of semiconductor layer 51_2. Because the electron affinity of semiconductor layer 51_3 is smaller than that of semiconductor layer 51_2, it is possible to create an embedded channel type transistor where the channel is farther away from the interface of the gate insulating layer. This reduces the effect of surface scattering. Therefore, for example, the on-current of transistor 50 and transistor 50A can be increased. The same may also be true when indium oxide is used as the semiconductor layer 51_2, which contains a second element and has a lower content of the second element than semiconductor layer 51_3.

[0219] It is preferable that the film thickness of semiconductor layer 51_1 and semiconductor layer 51_3 is thinner than the film thickness of semiconductor layer 51_2. For example, if the film thickness of semiconductor layer 51_2 is 4 nm or more, the film thickness of semiconductor layer 51_1 and semiconductor layer 51_3 are preferably 0.1 nm or more and 3 nm or less, more preferably 0.1 nm or more and 2 nm or less, more preferably 0.1 nm or more and 1 nm or less, and even more preferably 0.2 nm or more and 1 nm or less. This makes it possible to make transistors 50 and 50A transistors that can be subjected to a high electric field and have high field-effect mobility. Furthermore, it is possible to miniaturize or highly integrate semiconductor devices. Note that the boundary (also called the interface) between semiconductor layer 51_1 and semiconductor layer 51_2, and the boundary (also called the interface) between semiconductor layer 51_2 and semiconductor layer 51_3 may not be clearly visible. Therefore, in Figures 12(A) and 12(B), these interfaces are shown with dashed lines. In subsequent drawings, these interfaces will also be shown with dashed lines.

[0220] Figures 12(A) and 12(B) show an example in which the semiconductor layer 51 has a three-layer structure, but the present invention is not limited to this. The semiconductor layer 51 can have, for example, a two-layer structure, specifically a two-layer structure of semiconductor layer 51_2 and semiconductor layer 51_3. In this case, semiconductor layer 51_2 is in contact with the conductive layer 55_2, the insulating layer 74, etc.

[0221] The stacked semiconductor layer 51 structure shown in Figure 12(A) can also be applied to the transistors 50 shown in Figures 5(A) and 5(B), the transistor 50 shown in Figure 11(A), and the transistor 50 shown in Figure 11(B). Furthermore, the stacked semiconductor layer 51 structure shown in Figure 12(B) can also be applied to the transistors 50A shown in Figures 9(A) and 9(B). In addition, the stacked semiconductor layer 51 structures shown in Figures 12(A) and 12(B) can also be applied to the semiconductor layers 51 of the transistors described later.

[0222] Figures 13(A) and 13(B) show an example where the insulating layer 62 shown in Figure 3(A) has a three-layer structure consisting of insulating layer 62_1, insulating layer 62_2 on insulating layer 62_1, and insulating layer 62_3 on insulating layer 62_2. Figure 13(A) shows an example where the top surfaces of insulating layer 62_2 and insulating layer 62_3 are flat. Figure 13(B) shows an example where the top surfaces of insulating layer 62_1 are flat, in addition to the top surfaces of insulating layer 62_2 and insulating layer 62_3.

[0223] It is preferable to use an oxygen barrier insulating layer for insulating layer 62_1 and insulating layer 62_3. By using an oxygen barrier insulating layer for insulating layer 62_1, oxidation of the conductive layer 55 and an increase in electrical resistance can be suppressed. By using an oxygen barrier insulating layer for insulating layer 62_3, the supply of oxygen to the low-resistance region 51na and low-resistance region 51nb of the semiconductor layer 51 can be suppressed. As a result, oxygen vacancies, for example, are more likely to form in the low-resistance region 51na and low-resistance region 51nb. Therefore, it becomes easier to reduce the resistance of the source region and the other drain region of the semiconductor layer 51. Note that the insulating layer 62 may have a two-layer structure, for example, insulating layer 62_1 and insulating layer 62_2 on insulating layer 62_1. In other words, the insulating layer 62 does not have to have insulating layer 62_3.

[0224] It is preferable to use a material with a lower dielectric constant for the insulating layer 62_2 than for insulating layers 62_1 and 62_3. This suppresses the formation of parasitic capacitance between, for example, the conductive layer 55 and the conductive layer 53, and enables the provision of a semiconductor device capable of high-speed operation. In particular, it is preferable that the thickness of the insulating layer 62_2 is greater than the thickness of the insulating layer 62_1 and the insulating layer 62_3 in the region between the conductive layer 55 and the conductive layer 53, as this reduces the parasitic capacitance between the conductive layer 55 and the conductive layer 53.

[0225] For example, silicon nitride can be used as the insulating layer 62_1 and insulating layer 62_3. For example, silicon oxide can be used as the insulating layer 62_2. However, if an insulating material that is more permeable to oxygen than silicon nitride, such as silicon oxide, is used as the insulating layer 62_2, the conductive layer 55_1 may oxidize if the insulating layer 62_2 has a region in contact with the conductive layer 55_1. For example, during the film formation process of the semiconductor layer 51, or the heat treatment described above performed to crystallize the semiconductor layer 51, oxygen in the heat treatment atmosphere may be absorbed by the conductive layer 55_1, causing the conductive layer 55_1 to oxidize. This may increase the electrical resistance of the conductive layer 55_1. Therefore, in a semiconductor device according to one aspect of the present invention, the conductive layer 55 is covered with an insulating layer 62_1 that has barrier properties against oxygen, and an insulating layer 62_2 containing oxygen is provided on the insulating layer 62_1. This makes it possible to suppress oxidation of the conductive layer 55_1 while reducing the parasitic capacitance between the conductive layer 55 and the conductive layer 53, for example. As a result, a semiconductor device that is highly reliable and capable of high-speed operation can be provided. Furthermore, when the insulating layer 62 is a single-layer structure as shown in Figures 1(A) to 12(B), the insulating layer 62 can be made from a material that can be used for insulating layer 62_1, for example. That is, silicon nitride can be used as the insulating layer 62.

[0226] Furthermore, silicon nitride also possesses hydrogen barrier properties. Therefore, by using silicon nitride as one or both of the insulating layer 62_1 and insulating layer 62_3, the diffusion of hydrogen into the semiconductor layer 51 can be suppressed.

[0227] It is preferable that the concentration of impurities such as water and hydrogen in the insulating layer 62 be reduced. In particular, it is preferable that the concentration of impurities such as water and hydrogen in the thicker insulating layer 62_2 be reduced. This suppresses the incorporation of impurities such as water and hydrogen into the channel formation region 51i of the semiconductor layer 51. One method for reducing the concentration of impurities such as water and hydrogen in the insulating layer 62 is to perform heat treatment after the formation of the insulating layer 62_2 and before the formation of the insulating layer 74_1. This allows impurities such as water and hydrogen in the insulating layer 62 to diffuse outward. Furthermore, by forming the insulating layer 62_2 after the formation of the insulating layer 62_1, oxidation of the conductive layer 55_1 can be suppressed even during the heat treatment. Alternatively, heat treatment may be performed after the formation of the insulating layer 62_2 and before the formation of the insulating layer 62_3.

[0228] The configuration of the insulating layer 62 shown in Figure 13(A) and the configuration of the insulating layer 62 shown in Figure 13(B) can also be applied to the insulating layer 62 shown in Figures 5(A) to 12(B).

[0229] Figure 14(A) shows an example where the insulating layer 52 shown in Figure 13(A) has a three-layer structure consisting of an insulating layer 52_1 in contact with the semiconductor layer 51, an insulating layer 52_2 on insulating layer 52_1, and an insulating layer 52_3 on insulating layer 52_2. In other words, Figure 14(A) shows an example where the insulating layer 62 has a three-layer structure and the insulating layer 52 has a three-layer structure. Figure 14(B) is an enlarged view of region R2 shown in Figure 14(A). Figure 15(A) shows an example where an insulating layer 52_4 is provided between insulating layer 52_2 and insulating layer 52_3 shown in Figure 14(A). In other words, Figure 15(A) shows an example where the insulating layer 62 has a three-layer structure and the insulating layer 52 has a four-layer structure. Figure 15(B) is an enlarged view of region R2 shown in Figure 15(A). Region R2 includes insulating layers 62_2, 62_3, 74, 52, 53, 88, 86, and 58a. Region R2 also includes the channel formation region 51i and the low-resistance region 51na of the semiconductor layer 51.

[0230] Figures 14(A) to 15(B) show an example where the insulating layer 52_3 does not overlap with the low-resistance region 51na and low-resistance region 51nb of the semiconductor layer 51. This allows impurity elements necessary for forming the low-resistance region 51na and low-resistance region 51nb to be supplied to the semiconductor layer 51 without going through the insulating layer 52_3. Figures 14(A) to 15(B) also show an example where the low-resistance region 51na and low-resistance region 51nb are also provided in the region overlapping with region 71a in the semiconductor layer 51. In the example shown in Figures 14(A) to 15(B), the openings 67a and 67b are not formed in the insulating layer 52_3.

[0231] Figures 14(A) to 15(B) show examples where the side edge of the insulating layer 52_3 coincides with or substantially coincides with the side edge of the conductive layer 53. For example, the insulating layer 52_3 shown in Figures 14(A) to 15(B) can be formed by forming the insulating layer 52_3 and the conductive layer 53 using the same mask.

[0232] Figures 14(A) and 15(A) show an example where the insulating layer 62 has the configuration shown in Figure 13(A), but the insulating layer 62 may also have the configuration shown in Figure 13(B). Furthermore, the configurations of the insulating layer 62 and insulating layer 52 shown in Figures 14(A) to 15(B) can also be applied to the semiconductor device shown in Figures 5(A) to 12(B).

[0233] Figure 16(A) shows an example in which the conductive layer 58a shown in Figure 3(A) has a two-layer structure consisting of conductive layer 58a1 and conductive layer 58a2 on conductive layer 58a1, and conductive layer 58b has a two-layer structure consisting of conductive layer 58b1 and conductive layer 58b2 on conductive layer 58b1. Figure 16(B) is an enlarged view of the opening 67a shown in Figure 16(A) and the region near it. Figure 16(C) shows an example in which the shapes of conductive layer 58a1 and conductive layer 58a2 are different from those in Figure 16(B).

[0234] In FIGS. 16(A) and 16(B), an example of a two-layer structure of a conductive layer 58a is shown, which includes a conductive layer 58a1 provided along the side wall and bottom of the opening 67a, and a conductive layer 58a2 provided inside the conductive layer 58a1 so as to fill the opening 67a. Similarly, an example of a two-layer structure of a conductive layer 58b is shown, which includes a conductive layer 58b1 provided along the side wall and bottom of the opening 67b, and a conductive layer 58b2 provided inside the conductive layer 58b1 so as to fill the opening 67b. Further, in FIG. 16(A), an example is shown in which the upper end portion of the conductive layer 58a1, the upper surface of the conductive layer 58a2, the upper end portion of the conductive layer 58b1, the upper surface of the conductive layer 58b2, and the upper surface of the insulating layer 86 coincide with or substantially coincide with each other.

[0235] The conductive layers 58a1 and 58b1 preferably each have a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms. Thereby, it is possible to suppress impurities such as water and hydrogen from mixing into the semiconductor layer 51 through the conductive layer 58a2 and through the conductive layer 58b2. The conductive layers 58a1 and 58b1 can each have a single-layer structure or a laminated structure using one or more of, for example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, and ruthenium oxide. Note that the conductive layer 58a2 can use a conductive material applicable to the above-described conductive layer 58a. Similarly, the conductive layer 58b2 can use a conductive material applicable to the above-described conductive layer 58b.

[0236] In FIG. 16(C), an example is shown in which the upper end portion of the conductive layer 58a1 is located below the upper surface of the conductive layer 58a2. For example, when forming the conductive layer 58a1 using a sputtering method, the conductive layer 58a1 may not be formed along the side wall of the opening 67a, and the conductive layer 58a1 may be formed only on the upper surface of the low-resistance region 51na and in the vicinity thereof. Here, the configuration of the conductive layer 58a shown in FIG. 16(C) can also be applied to the conductive layer 58b. That is, the upper end portion of the conductive layer 58b1 may be located below the upper surface of the conductive layer 58b2.

[0237] FIG. 17(A) is a diagram showing an example in which an insulating layer 69a is provided inside the opening 67a shown in FIG. 2(B) and an insulating layer 69b is provided inside the opening 67b. FIG. 17(B) is a cross-sectional view taken between the dashed-dotted line A1 - A2 shown in FIG. 17(A).

[0238] The insulating layer 69a and the insulating layer 69b are provided in reflection of the shapes of the opening 67a and the opening 67b, respectively. The side surface of the insulating layer 69a has a region that contacts the side surfaces of the insulating layer 52, the insulating layer 88, and the insulating layer 86 at the opening 67a. Similarly, the side surface of the insulating layer 69b has a region that contacts the side surfaces of the insulating layer 52, the insulating layer 88, and the insulating layer 86 at the opening 67b. Also, the lower end portion of the insulating layer 69a can have a region that contacts the upper surface of the semiconductor layer 51, specifically, the upper surface of the low-resistance region 51na. Similarly, the lower end portion of the insulating layer 69b can have a region that contacts the upper surface of the semiconductor layer 51, specifically, the upper surface of the low-resistance region 51nb.

[0239] The conductive layer 58a is provided inside the opening 67a (opposite side to the side wall of the opening 67a) from the insulating layer 69a. The conductive layer 58b is provided inside the opening 67b (opposite side to the side wall of the opening 67b) from the insulating layer 69b. That is, the insulating layer 69a is provided between the side wall of the opening 67a and the conductive layer 58a. Similarly, the insulating layer 69b is provided between the side wall of the opening 67b and the conductive layer 58b.

[0240] In the example shown in FIG. 17(B), the upper surface of the insulating layer 86, the upper surface of the conductive layer 58a, and the upper surface of the conductive layer 58b are planarized. In this case, the height from the reference plane of the upper end portion of the insulating layer 69a and the height from the reference plane of the upper end portion of the insulating layer 69b coincide with or are substantially the same as the height from the reference plane of the upper surface of the insulating layer 86, the height from the reference plane of the upper surface of the conductive layer 58a, and the height from the reference plane of the upper surface of the conductive layer 58b, respectively.

[0241] For example, silicon nitride can be used as the insulating layer 69a and the insulating layer 69b. This makes it possible to suppress the incorporation of impurities such as water and hydrogen contained in the insulating layer 86, etc., into the semiconductor layer 51 through the conductive layer 58a or the conductive layer 58b, etc.

[0242] The configurations of the semiconductor devices shown in Figures 16(A) to 16(C), and the configurations of the semiconductor devices shown in Figures 17(A) and 17(B), can also be applied to the semiconductor devices shown in Figures 5(A) to 15(B). Furthermore, the configurations of the semiconductor devices shown in Figures 16(A) to 16(C), and the configurations of the semiconductor devices shown in Figures 17(A) and 17(B), can also be applied to the semiconductor devices shown hereafter.

[0243] <Example 3 of semiconductor device configuration> The following describes a configuration example of a semiconductor device according to one aspect of the present invention, different from those shown in Figures 1(A) to 4(A). Note that the explanation of parts that overlap with the above will be omitted, and only the differences will be explained in detail. Furthermore, even if components differ in position or shape, if their function is the same, they may be given the same reference numeral and their explanation may be omitted.

[0244] Figure 18(A) is a plan view showing an example of the configuration of a semiconductor device having transistor 50B. Figure 19(A) is a cross-sectional view between the dashed lines A1 and A2 shown in Figure 18(A). Figure 19(B) is a cross-sectional view between the dashed lines B1 and B2 shown in Figure 18(A). Figure 18(B) is a cross-sectional view between the dashed lines C1 and C2 shown in Figure 19(A).

[0245] The semiconductor devices shown in Figures 18(A) to 19(B) differ from those shown in Figures 1(A) to 4(A) mainly in that an insulating layer 65 is provided between the insulating layer 62 and the semiconductor layer 51, and between the insulating layer 62 and the insulating layer 52. Furthermore, transistor 50B differs from transistor 50 mainly in that it has a conductive layer 60. In other words, transistor 50B can be described as transistor 50 with a conductive layer 60 added. Note that transistor 50A may also have a conductive layer 60.

[0246] The conductive layer 60 is located on the insulating layer 62. The conductive layer 60 has a region facing the conductive layer 53, with the insulating layer 74, the semiconductor layer 51, and the insulating layer 52 in between. Figures 18(A) to 19(B) show an example in which the conductive layer 60 extends in the X direction.

[0247] The insulating layer 65 is located on the conductive layer 60 and the insulating layer 62. The semiconductor layer 51 also has a region located on the insulating layer 65. The openings 63 are provided not only in the insulating layer 62 but also in the conductive layer 60 and the insulating layer 65.

[0248] In transistor 50B, one of the conductive layer 53 and conductive layer 60 can be used as the gate electrode, and the other as the back gate electrode. In particular, transistor 50B may have a structure in which conductive layer 53 is used as the gate electrode and conductive layer 60 is used as the back gate electrode. By using conductive layer 53 as the gate electrode, the region facing the semiconductor layer 51 inside the opening 63 is larger than that of conductive layer 60, allowing the gate electric field to be applied to the semiconductor layer 51 more efficiently. Therefore, the electrical characteristics of transistor 50B may be improved. When conductive layer 53 functions as the gate electrode and conductive layer 60 functions as the back gate electrode, insulating layer 52 functions as the gate insulating layer and insulating layer 74 functions as the back gate insulating layer. Conductive layer 60 has a region that functions as a back gate wiring.

[0249] As mentioned above, transistor 50B has a back gate electrode. Therefore, the threshold voltage of transistor 50B can be controlled by the potential applied to the back gate electrode. By controlling the threshold voltage of transistor 50B, transistor 50B can be easily made into a normally-off transistor.

[0250] The conductive layer 60 can be made of a conductive material applicable to the conductive layer 53. The insulating layer 65 can be made of an insulating material applicable to the insulating layer 62.

[0251] Figure 20 shows an example where the semiconductor layer 51 shown in Figure 19(A) has a three-layer structure consisting of semiconductor layer 51_1, semiconductor layer 51_2, and semiconductor layer 51_3, similar to the semiconductor layer 51 shown in Figure 12(A) and Figure 12(B).

[0252] When indium oxide is used for all three semiconductor layers 51_1, 51_2, and 51_3, as described above, semiconductor layers 51_1 and 51_3 use films with higher film density and fewer defects than semiconductor layer 51_2. Furthermore, semiconductor layer 51_2 uses a film with higher carrier mobility than semiconductor layers 51_1 and 51_3. By making the carrier mobility of semiconductor layer 51_2 higher than that of semiconductor layer 51_1 and semiconductor layer 51_3, the main carrier paths can be moved away from the interface between insulating layer 74 and semiconductor layer 51, and between insulating layer 52 and semiconductor layer 51, compared to the case where semiconductor layer 51 is, for example, a single layer of semiconductor layer 51_2. This reduces the effect of surface scattering. Therefore, for example, the on-current of transistor 50B can be increased. Also, the field-effect mobility of transistor 50B can be increased. Furthermore, by using a film with a higher film density and fewer defects than semiconductor layer 51_2 as the semiconductor layer 51_1 in contact with the insulating layer 74 and the semiconductor layer 51_3 in contact with the insulating layer 52, the reliability of transistor 50B can be improved compared to the case where semiconductor layer 51_2 is in contact with insulating layer 74 and insulating layer 52.

[0253] As mentioned above, semiconductor layers 51_1 and 51_3 may contain indium, oxygen, and a second element that has a stronger bonding force with oxygen than indium. Specifically, indium oxide can be used for semiconductor layer 51_2, and indium oxide containing the second element can be used for semiconductor layers 51_1 and 51_3. This will prevent oxygen vacancies and V-voids from forming near the surface of semiconductor layer 51 on the insulating layer 74 side and near the surface of insulating layer 52. OThe formation of H can be suppressed. Therefore, carrier scattering near the surface of the semiconductor layer 51 on the insulating layer 74 side and near the surface of the insulating layer 52 side can be reduced. Consequently, the transistor 50B can be a transistor with a large on-current.

[0254] In semiconductor layer 51_1, the ratio of the number of atoms of the second element to the sum of the number of atoms of indium and the second element is preferably 0.1% to 5%, and more preferably 0.5% to 3%, similar to semiconductor layer 51_3 described above. This prevents oxygen vacancies and V in semiconductor layer 51_1 and near the interface between semiconductor layer 51_1 and insulating layer 74. O This suppresses the formation of H and reduces scattering near the surface of the semiconductor layer 51 on the insulating layer 74 side. Furthermore, the inclusion of the second element reduces the amount of carriers generated, preventing an increase in the carrier concentration of the semiconductor layer 51. Therefore, it is possible to suppress a decrease in the field-effect mobility of the transistor 50B.

[0255] As mentioned above, when indium oxide is used as semiconductor layer 51_2, and indium oxide containing a second element is used as semiconductor layers 51_1 and 51_3, the electron affinity of semiconductor layer 51_1 and semiconductor layer 51_3 may be smaller than the electron affinity of semiconductor layer 51_2. This allows the main carrier path to be moved away from the interface between insulating layer 74 and semiconductor layer 51, and the interface between insulating layer 52 and semiconductor layer 51, compared to the case where the electron affinity of semiconductor layer 51_1 and semiconductor layer 51_3 is greater than or equal to the electron affinity of semiconductor layer 51_2. This reduces the effect of surface scattering. Therefore, for example, the on-current of transistor 50B can be increased. The same may be true when indium oxide containing a second element is used as semiconductor layer 51_2, and the content of the second element is lower than that of semiconductor layers 51_1 and 51_3.

[0256] FIG. 21(A) and FIG. 21(B) show examples in which the insulating layer 62 shown in FIG. 19(A) has a three-layer structure similar to the examples shown in FIGS. 13(A) and 13(B), respectively. Also, FIGS. 21(A) and FIG. 21(B) show examples in which the insulating layer 65 shown in FIG. 19(A) has a three-layer structure of an insulating layer 65_1, an insulating layer 65_2 on the insulating layer 65_1, and an insulating layer 65_3 on the insulating layer 65_2. FIG. 21(A) shows an example in which the upper surfaces of the insulating layer 62_2, the insulating layer 62_3, the insulating layer 65_2, and the insulating layer 65_3 are flat. FIG. 21(B) shows an example in which, in addition to the upper surfaces of the insulating layer 62_2, the insulating layer 62_3, the insulating layer 65_2, and the insulating layer 65_3, the upper surfaces of the insulating layer 62_1 and the insulating layer 65_1 are flat.

[0257] For the insulating layer 65_1, a material that can be used for the insulating layer 62_1 can be used. For the insulating layer 65_3, a material that can be used for the insulating layer 62_3 can be used. For the insulating layer 65_1 and the insulating layer 65_3, for example, silicon nitride can be used. Thus, the insulating layer 65_1 and the insulating layer 65_3 can be barrier insulating layers against oxygen. For the insulating layer 65_2, a material that can be used for the insulating layer 62_2 can be used, and for example, silicon oxide can be used.

[0258] As described above, silicon nitride also has barrier properties against hydrogen. Thus, by using silicon nitride as at least one of the insulating layer 62_1, the insulating layer 62_3, the insulating layer 65_1, and the insulating layer 65_3, diffusion of hydrogen into the semiconductor layer 51 can be suppressed. Also, when hydrogen is supplied to the semiconductor layer 51 as an impurity element for forming the low-resistance region 51na and the low-resistance region 51nb, it is preferable to use an insulating film having barrier properties against hydrogen, such as silicon nitride, as the insulating layer 65_3. Thereby, diffusion of the hydrogen supplied to the semiconductor layer 51 into the insulating layer 65 can be suppressed.

[0259] By configuring the insulating layers 62 and 65 as shown in Figure 21(A) or Figure 21(B), the conductive layer 60 can be covered with insulating layers 62_3 and 65_1 in addition to the insulating layer 74. Since insulating layers 62_3 and 65_1 have barrier properties against oxygen, oxidation of the conductive layer 60 can be suppressed. This suppresses the increase in resistance of the conductive layer 60. Furthermore, because insulating layer 65_3 has barrier properties against oxygen, the supply of oxygen to the low-resistance region 51na and low-resistance region 51nb of the semiconductor layer 51 can be suppressed. Therefore, it becomes easier to reduce the resistance of the source region and the other drain region of the semiconductor layer 51. Note that insulating layer 65 may have a two-layer structure, for example, insulating layer 65_1 and insulating layer 65_2 on insulating layer 65_1. In other words, insulating layer 65 does not have to have insulating layer 65_3.

[0260] <Examples of semiconductor device fabrication methods> The following describes an example of a method for manufacturing a semiconductor device according to one aspect of the present invention.

[0261] Thin films (insulating films, semiconductor films, conductive films, etc.) that constitute semiconductor devices can be formed using methods such as sputtering, CVD, vacuum deposition, pulsed laser deposition (PLD), ALD, and molecular beam epitaxy (MBE). CVD methods include PECVD, thermal CVD, and photoCVD. Thermal CVD methods include metal-organic chemical vapor deposition (MOCVD) and metal chemical vapor deposition (metal CVD).

[0262] Thin films (insulating films, semiconductor films, conductive films, etc.) that constitute semiconductor devices can be formed by methods such as spin coating, dip coating, spray coating, inkjet printing, dispensing, screen printing, offset printing, slit coating, roll coating, and curtain coating.

[0263] Thin films constituting semiconductor devices can be processed using photolithography or other methods. Alternatively, thin films may be processed by nanoimprint lithography, lift-off lithography, or other methods. Furthermore, island-like thin films may be directly formed using a deposition method employing a shielding mask such as a metal mask.

[0264] Etching can be performed using methods such as dry etching or wet etching.

[0265] [Example of manufacturing method 1] In the following, examples of methods for manufacturing semiconductor devices shown in Figures 1(A) to 4(A) will be explained using Figures 22(A) to 23(D). Figures 22(A) to 23(D) correspond to the cross-sectional views shown in Figure 3(A).

[0266] First, as shown in Figure 22(A), an insulating layer 87 is formed on a substrate (not shown).

[0267] Next, as shown in Figure 22(A), a conductive layer 55 is formed on the insulating layer 87. Figure 22(A) shows an example in which a conductive layer 55_1 and a conductive layer 55_2 on the conductive layer 55_1 are formed as the conductive layer 55. As mentioned above, the conductive layer 55_1 can be formed using, for example, at least one of tungsten, copper, and aluminum. The conductive layer 55_2 can be formed using an oxide conductor such as ITO.

[0268] Figure 22(A) shows an example where the side surface of the conductive layer 55 is perpendicular to the surface to be formed. Depending on the processing conditions of the conductive film that will become the conductive layer 55, the side surface of the conductive layer 55 may have a tapered shape that is inclined with respect to the surface to be formed.

[0269] Next, as shown in Figure 22(A), an insulating layer 62 is formed on the conductive layer 55. The insulating layer 62 can be formed so as to cover the conductive layer 55.

[0270] As shown in Figure 22(A), it is preferable to perform a planarization treatment on the upper surface of the insulating layer 62. Furthermore, if the insulating layer 62 has a laminated structure, it is preferable to perform the planarization treatment on at least one layer. For example, CMP (Chemical Mechanical Polishing) can be used as the planarization treatment.

[0271] It is preferable to perform heat treatment after the formation of the insulating layer 62. This allows impurities such as water and hydrogen in the insulating layer 62 to diffuse outward. Therefore, the concentration of impurities such as water and hydrogen in the insulating layer 62 can be reduced.

[0272] There are no special limitations on the equipment used for heat treatment; it may be an apparatus that heats the workpiece by heat conduction or thermal radiation from a heat source such as a resistance heating element. For example, an electric furnace or an RTA (Rapid Thermal Anneal) apparatus such as an LRTA (Lamp Rapid Thermal Anneal) apparatus or a GRTA (Gas Rapid Thermal Anneal) apparatus can be used. An LRTA apparatus is an apparatus that heats the workpiece by radiation of light (electromagnetic waves) emitted from a lamp such as a halogen lamp, metal halide lamp, xenon arc lamp, carbon arc lamp, high-pressure sodium lamp, or high-pressure mercury lamp. A GRTA apparatus is an apparatus that performs heat treatment using high-temperature gas.

[0273] As the insulating layer 62, for example, as shown in Figures 13(A) to 15(B), an insulating layer 62_1, an insulating layer 62_2 on insulating layer 62_1, and an insulating layer 62_3 on insulating layer 62_2 can be formed. As mentioned above, insulating layer 62_1 and insulating layer 62_3 can be formed using materials that have barrier insulating properties against oxygen, such as silicon nitride. In addition, insulating layer 62_2 can be formed using insulating material with a lower dielectric constant than silicon nitride, such as silicon oxide. By forming insulating layer 62_2 after forming insulating layer 62_1 and then performing the heat treatment described above, oxidation of the conductive layer 55, specifically oxidation of conductive layer 55_1, caused by the heat treatment can be suppressed.

[0274] Next, as shown in Figure 22(A), an opening 63 reaching the conductive layer 55 is formed in the insulating layer 62. For example, a resist mask is formed in the region other than the region that will become the opening 63, and the insulating layer 62 in the region where the resist mask is not formed is removed by etching. After etching, the resist mask is removed. Dry etching is preferable as the etching process as it makes it easier to form fine openings 63. Here, due to the formation of the opening 63, a recess overlapping with the opening 63, specifically the first recess described above, may be formed in the conductive layer 55, specifically the conductive layer 55_2.

[0275] Next, as shown in Figure 22(B), an insulating layer 74 is formed on the insulating layer 62 and the conductive layer 55. In Figure 22(B), the insulating layer 74 consists of an insulating layer 74_1 and an insulating layer 74_2 on top of the insulating layer 74_1. The insulating layer 74 is formed to cover the side walls and bottom of the opening 63. It is preferable to form the insulating layer 74 using, for example, the ALD method, as this allows for good coverage of the insulating layer 74.

[0276] Next, the insulating layer 74 is processed by anisotropic etching. This removes the region of the insulating layer 74 located on the insulating layer 62, in other words, the region located outside the opening 63, as shown in Figure 22(C). Also, a portion of the region of the insulating layer 74 that overlaps with the opening 63 is removed, exposing the upper surface of the conductive layer 55, specifically the upper surface of the conductive layer 55_2. Figure 22(C) shows an example where the height of the upper end of the insulating layer 74 from the reference plane matches the height of the upper surface of the insulating layer 62 from the reference plane. This configuration reduces the step difference between the insulating layer 74 and the insulating layer 62, improving the coverage of the semiconductor layer 51 that is formed later. This reduces defects such as porosity. Note that the height of the upper end of the insulating layer 74 from the reference plane may be lower than the height of the upper surface of the insulating layer 62 from the reference plane.

[0277] As shown in Figure 22(C), the processing of the insulating layer 74 may result in the formation of the second recess described above in the conductive layer 55, specifically the conductive layer 55_2. As mentioned above, the second recess can be formed to be deeper than the first recess in the region overlapping with the insulating layer 74.

[0278] Next, as shown in Figure 22(D), the semiconductor layer 51 is formed having a region in contact with the upper surface of the conductive layer 55_2 (for example, the bottom of the second recess), a region in contact with the side surface of the insulating layer 74, a region located on the insulating layer 74, and a region in contact with the upper surface of the insulating layer 62. The semiconductor layer 51 can be formed to cover the insulating layer 74.

[0279] The semiconductor layer 51 is preferably formed using the ALD method. Since the ALD method is a film deposition method with superior coverage compared to the sputtering method, the coverage of the semiconductor layer 51 can be improved by depositing it using the ALD method. Furthermore, by using the ALD method, which deposits atoms individually during film deposition, rather than the sputtering method, which impacts the surface to be formed with particles, the formation of crystal nuclei in the film can be suppressed. For example, a precursor and an oxidizing agent can be used to form the semiconductor layer 51. The precursor preferably contains indium. In this case, a film containing indium and oxygen is formed as the semiconductor layer 51. When the precursor contains indium, the thermal ALD method can be used as the ALD method.

[0280] Examples of indium-containing precursors that can be used include trimethylindium, triethylindium, ethyldimethylindium, tris(1-methylethyl)indium, tris(2,2,6,6-tetramethyl-3,5-heptanedionic acid)indium, cyclopentadienylindium, indium(III) acetylacetonate, (3-(dimethylamino)propyl)dimethylindium, (diethylphosphino)dimethylindium, chlorodimethylindium, bromodimethylindium, and dimethyl(2-propanolato)indium.

[0281] Furthermore, inorganic precursors that do not contain hydrocarbons may be used as indium precursors. Examples of indium-containing inorganic precursors include halogenated indium compounds such as trifluoroindium (indium(III) fluoride), indium trichloride (indium(III) chloride), indium tribromide (indium(III) bromide), and indium triiodide (indium(III) iodide). Indium trichloride has a decomposition temperature of approximately 500°C to 700°C. Therefore, by using indium trichloride, film deposition by the ALD method can be performed while heating the substrate at approximately 400°C to 600°C, for example, at 500°C.

[0282] Examples of oxidizing agents that can be used include ozone (O3), oxygen (O2), water (H2O), nitrogen dioxide (NO2), nitrous oxide (N2O), hydrogen peroxide (H2O2), etc., and two or more of these may be used.

[0283] Unless otherwise specified in this specification, when ozone, oxygen, or water are used as oxidizing agents, these shall include not only gaseous or molecular states, but also plasma states, radical states, or ionic states.

[0284] When forming single crystals or polycrystalline films with large grain sizes, it is preferable to use an oxidizing agent containing hydrogen to suppress the formation of crystal nuclei in the initial stages of film formation. For example, it is preferable to use H2O or H2O2. After forming a film with few crystal nuclei, a single crystal film or a polycrystalline film with large grain sizes can be formed by growing crystals using the heat applied during film formation or by heat treatment after film formation. On the other hand, when reducing the hydrogen and nitrogen concentrations in the film, it is preferable to use O2 or O3 as the oxidizing agent, and it is particularly preferable to use O3.

[0285] When introducing the precursor into the reaction chamber, the substrate heating temperature is preferably set to a temperature corresponding to the decomposition temperature of the precursor. In the case of a thermal ALD method using triethylindium as the indium-containing precursor, for example, the substrate heating temperature can be 100°C to 350°C, preferably 150°C to 300°C.

[0286] The semiconductor layer 51 can also be formed using sputtering, CVD, MBE, or PLD. For example, when forming the semiconductor layer 51 using sputtering, it is preferable that the sputtering gas contains hydrogen (H2). By introducing hydrogen when forming the semiconductor layer 51 using sputtering, a semiconductor layer 51 with low crystallinity can be formed. In addition, the generation of crystal nuclei can be suppressed or the disappearance of crystal nuclei can be promoted during the formation of the semiconductor layer 51. As the sputtering gas, a noble gas (typically argon) or a single gas of oxygen, or a mixed gas of a noble gas and oxygen can also be used.

[0287] Furthermore, when forming the semiconductor layer 51 using the sputtering method, the substrate temperature during film formation of the semiconductor layer 51 is preferably between room temperature (25°C) and 250°C, more preferably between room temperature and 200°C, and even more preferably between room temperature and 140°C. For example, setting the substrate temperature to between room temperature and 140°C is preferable because it increases productivity. It is also preferable because it suppresses the generation of crystal nuclei. In addition, the semiconductor layer can be formed at room temperature or without heating the substrate.

[0288] Next, a heat treatment is performed. This causes crystal growth in the semiconductor layer 51. As a result, the crystal grains in the semiconductor layer 51 can be enlarged. This heat treatment is also called a heat treatment for crystallization of the semiconductor layer 51. This heat treatment may be performed immediately after the deposition of the semiconductor layer 51, or after the semiconductor layer 51 has been processed into a desired shape.

[0289] The heat treatment temperature is preferably 100°C to 450°C, more preferably 100°C to 350°C, more preferably 150°C to 350°C, more preferably 170°C to 350°C, and more preferably 200°C to 350°C. The heat treatment can be carried out in an atmosphere containing at least one of a noble gas, nitrogen, and oxygen. Dry air (CDA: Clean Dry Air) can be used as the nitrogen-containing atmosphere or the oxygen-containing atmosphere. It is preferable that the content of hydrogen, water, etc. in the atmosphere be kept to a minimum. It is preferable to use a high-purity gas with a dew point of -60°C or lower, preferably -100°C or lower, as the atmosphere. By using an atmosphere with a minimum content of hydrogen, water, etc., it is possible to prevent hydrogen, water, etc. from being incorporated into the insulating layer 62 as much as possible. For example, an oven can be used for the heat treatment.

[0290] If the heat treatment temperature is too high, crystal nuclei are more likely to form, and the crystal growth of these nuclei will also proceed more easily. On the other hand, if the heat treatment temperature is too low, the rate of crystal grain growth will slow down, which may reduce the productivity of semiconductor devices. By setting the heat treatment temperature within the aforementioned range, it is possible to suppress the formation and growth of crystal nuclei while accelerating the rate of crystal grain growth.

[0291] The heat treatment can be performed using an RTA (Restorative Temperature Adjustment) device. Using an RTA device can shorten the heat treatment time. When using an RTA device, the heat treatment temperature is preferably 100°C to 750°C, more preferably 200°C to 700°C, more preferably 300°C to 700°C, more preferably 400°C to 700°C, and more preferably 500°C to 700°C. The treatment time is preferably 1 minute to 10 minutes, more preferably 3 minutes to 10 minutes, and more preferably 5 minutes to 10 minutes.

[0292] Furthermore, the semiconductor layer 51 may be crystallized during film formation. For example, the heat applied during film formation can cause the semiconductor layer 51 to crystallize. In this case, the heat treatment described above after the formation of the semiconductor layer 51 does not need to be performed.

[0293] Microwave treatment may be performed after the heat treatment described above. Microwave treatment can reduce the concentration of impurities such as hydrogen or water in the semiconductor layer 51. In addition, the crystallinity of the semiconductor layer 51 may be improved. Details of microwave treatment will be described later.

[0294] Next, as shown in Figure 22(E), the insulating layer 52 is formed such that it has a region in contact with the upper surface of the semiconductor layer 51, a region in contact with the side surface of the semiconductor layer 51, and a region in contact with the upper surface of the insulating layer 62. It is preferable to use the ALD process two or more times when forming the insulating layer 52 which has a laminated structure of multiple insulating films. For example, it is preferable that two or more of the multiple insulating films of the insulating layer 52 are formed using the ALD process. By forming at least two or more insulating films using the ALD process, the coverage and uniformity of the film thickness of the insulating layer 52 can be improved. Furthermore, productivity can be increased by, for example, continuously forming two or more insulating films using the ALD process.

[0295] Next, it is preferable to perform microwave processing in an oxygen-containing atmosphere. Here, microwave processing refers to processing using, for example, a device having a power supply that generates high-density plasma using microwaves. Furthermore, in this specification, microwaves refer to electromagnetic waves having a frequency of 300 MHz or more and 300 GHz or less.

[0296] In microwave processing, it is preferable to use a microwave processing apparatus that has a power supply for generating a high-density plasma using microwaves. Here, the frequency of the microwave processing apparatus is preferably 300 MHz to 300 GHz, more preferably 2.4 GHz to 2.5 GHz, and can be, for example, 2.45 GHz. By using a high-density plasma, a high density of oxygen radicals can be generated. Furthermore, the power of the power supply that applies microwaves to the microwave processing apparatus is preferably 1000 W to 10000 W, and more preferably 2000 W to 5000 W. The microwave processing apparatus may also have a power supply for applying RF (Radio Frequency) to the substrate side. Furthermore, by applying RF to the substrate side, oxygen ions generated by the high-density plasma can be efficiently guided into the film.

[0297] Microwave treatment is preferably carried out under reduced pressure, with a pressure of 10 Pa to 1000 Pa, and more preferably 300 Pa to 700 Pa. The treatment temperature is preferably room temperature (25°C) to 750°C, more preferably 300°C to 500°C, and even more preferably 400°C to 450°C.

[0298] Furthermore, after microwave treatment or plasma treatment, heat treatment may be performed continuously without exposure to the outside air. The heat treatment temperature is preferably, for example, 100°C to 750°C, more preferably 300°C to 500°C, and even more preferably 400°C to 450°C.

[0299] Microwave processing can be carried out, for example, using oxygen gas and argon gas. Here, the oxygen flow rate ratio (O2 / (O2+Ar)) is preferably greater than 0% and 100% or less, more preferably greater than 0% and 50% or less, more preferably between 10% and 40%, and even more preferably between 10% and 30%.

[0300] When the insulating layer 52 is made into a laminated structure, the microwave treatment described above is not necessarily performed after the insulating layer 52 is formed. For example, when two or more layers are laminated as the insulating layer 52, the microwave treatment may be performed before forming the layer in contact with the conductive layer 53, or after forming the layer in contact with the semiconductor layer 51 and the insulating layer 62, or after forming the layer to be placed between them. Furthermore, the microwave treatment may be performed multiple times (at least two times).

[0301] By performing microwave processing in an oxygen-containing atmosphere, the above oxygen radicals are supplied to the semiconductor layer, and V in the semiconductor layer 51 O This can reduce H and oxygen deficiencies.

[0302] Next, as shown in Figure 22(E), a conductive layer 53 is formed on the insulating layer 52. Specifically, first, a conductive film that will become the conductive layer 53 is deposited. Next, a resist mask is formed on the conductive film. The resist mask is formed in an area that overlaps with at least the opening 63. After that, the conductive film in the areas where the resist mask is not formed is removed by etching. Through this process, the conductive layer 53 can be formed. After the conductive layer 53 is formed, the resist mask on the conductive layer 53 is removed.

[0303] The insulating layer 52 may be processed when forming the conductive layer 53. That is, a portion of the insulating layer 52 may be removed when forming the conductive layer 53. For example, if the insulating layer 52 has a laminated structure of two or more layers, a portion of the layer may be processed. For example, if the insulating layer 52 has the configuration shown in Figures 14(A) to 15(B), a portion of the insulating layer 52_3 is removed. In this case, processing the insulating layer 52 using the resist mask used for forming the conductive layer 53 is preferable because it reduces the number of manufacturing steps for the semiconductor device compared to using a different resist mask.

[0304] Next, as shown in Figure 22(F), an insulating layer 88 is formed on the conductive layer 53 and the insulating layer 52. Specifically, the insulating layer 88 is formed along the upper surface of the conductive layer 53, the side surface of the conductive layer 53, and the upper surface of the insulating layer 52. The insulating layer 88 can be formed using, for example, the ALD method, sputtering method, CVD method, MBE method, or PLD method, but the ALD method is preferable because it allows the insulating layer 88 to be formed to cover the conductive layer 53 with good coverage. Furthermore, forming the insulating layer 88 using the ALD method makes it easier to control the thickness of the insulating layer 88. Therefore, in the subsequent step of supplying impurity elements to the semiconductor layer 51, it is preferable to ensure that the impurity elements are supplied to the semiconductor layer 51 without penetrating the semiconductor layer 51.

[0305] Next, as shown in Figure 22(F), impurity elements 93 are supplied to the semiconductor device. The process shown in Figure 22(F) allows the impurity elements 93 to be supplied to regions of the semiconductor layer 51 that do not overlap with the conductive layer 53 and region 71a. That is, the impurity elements 93 can be supplied to the semiconductor layer 51 by self-alignment, using the conductive layer 53 as a mask. As a result, low-resistance regions 51na and 51nb can be formed. The low-resistance regions 51na and 51nb are formed facing each other with the conductive layer 53 in between.

[0306] As impurity element 93, typical nonmetallic elements, typical metallic elements, or transition elements (transition metals) can be used. For example, elements such as boron, phosphorus, hydrogen, titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, and silicon can be used as impurity elements.

[0307] For supplying impurity element 93, methods such as ion doping, ion implantation, or plasma immersion ion implantation can be used. These methods allow for highly precise control of the concentration profile in the depth direction by controlling the ion acceleration voltage and dose.

[0308] By using an ion implantation method, in which the source gas is ionized and the ions are separated by mass before irradiation, the supply of elements other than impurity element 93 to the semiconductor device can be suppressed compared to the ion doping method. On the other hand, by using an ion doping method, in which the source gas is ionized and the ions are irradiated without mass separation, the productivity of the semiconductor device can be increased compared to the ion implantation method.

[0309] As the raw material gas for impurity element 93, the aforementioned gases containing impurity elements can be used. When supplying boron, typical examples include B2H6 gas and BF3 gas. When supplying phosphorus, typical examples include PH3 gas. Alternatively, a mixed gas obtained by diluting these raw material gases with hydrogen or a noble gas may be used.

[0310] Other gases that can be used as raw materials include CH4, N2, NH3, HF, H2, and noble gases. These raw materials can be used individually or in mixtures of two or more. The ion source is not limited to gases; solids or liquids may be heated and vaporized.

[0311] Furthermore, for example, impurity elements 93 can be supplied to the semiconductor layer 51 using plasma processing. In the case of plasma processing, plasma is generated in a gas atmosphere containing the impurity elements 93 to be supplied, and the impurity elements 93 can be supplied to the semiconductor layer 51 by performing plasma processing. In this case, B2H6 gas, PH3 gas, H2 gas, N2 gas, noble gases, etc. can be used as the gas containing the impurity elements 93. As the apparatus for generating the plasma, as mentioned above, dry etching apparatus, plasma CVD apparatus, high-density plasma CVD apparatus, etc. can be used.

[0312] Furthermore, impurity elements 93 can be supplied to the semiconductor layer 51 by performing heat treatment in an atmosphere containing impurity elements 93. In this case, the substrate temperature can be 150°C or more and 600°C or less, preferably 200°C or more and 500°C or less, more preferably 200°C or more and 450°C or less, more preferably 250°C or more and 400°C or less, more preferably 250°C or more and 350°C or more and still preferably 300°C or more and 350°C or less.

[0313] Furthermore, even when supplying impurity elements 93 to the semiconductor layer 51 by ion doping, ion implantation, plasma immersion ion implantation, plasma treatment, etc., it is preferable to perform the supply process of impurity elements 93 while heating the substrate (not shown). This allows for the repair of damage to the semiconductor layer 51 that occurs when impurity elements 93 are supplied. In other words, the supply of impurity elements 93 to the semiconductor layer 51 and the repair of damage caused by said supply can be performed in parallel. The substrate temperature can be the substrate temperature described above.

[0314] Figure 22(F) shows an example in which impurity elements 93 are supplied to the semiconductor device after the formation of the insulating layer 88, but impurity elements 93 may also be supplied before the formation of the insulating layer 88. That is, impurity elements 93 may be supplied to the semiconductor device immediately after the formation of the conductive layer 53 in the process shown in Figure 22(E). When impurity elements 93 are supplied to the semiconductor device before the formation of the insulating layer 88, as described above, low-resistance regions 51na and 51nb are formed in the semiconductor layer 51 in the region that overlaps with region 71a.

[0315] As mentioned above, when supplying impurity elements 93 to the semiconductor layer 51 using methods such as ion implantation, ion doping, or plasma immersion ion implantation, it is preferable to do so after the formation of the insulating layer 88. This suppresses the impurity elements 93 from penetrating the semiconductor layer 51 and being supplied to, for example, the insulating layer 62. When supplying impurity elements 93 to the semiconductor layer 51 after the formation of the insulating layer 88, the film thickness of the insulating layer 88 is controlled so that the impurity elements 93 are supplied to the semiconductor layer 51 but do not penetrate it. As mentioned above, forming the insulating layer 88 using the ALD method is preferable because it makes it easier to control the film thickness of the insulating layer 88.

[0316] Furthermore, as mentioned above, when supplying impurity elements 93 to the semiconductor layer 51, for example, by plasma treatment or by heat treatment in an atmosphere containing impurity elements 93, it is preferable to do so before the formation of the insulating layer 88. This prevents the impurity elements 93 from being blocked by the insulating layer 88 and not being supplied to the semiconductor layer 51. Even when using ion implantation, ion doping, plasma immersion ion implantation, etc., if the amount of impurity elements 93 penetrating the semiconductor layer 51 is sufficiently small, the supply of impurity elements 93 to the semiconductor layer 51 may be performed before the formation of the insulating layer 88. Also, even when using plasma treatment or heat treatment in an atmosphere containing impurity elements 93, if the impurity elements 93 can permeate the insulating layer 88, the supply of impurity elements 93 to the semiconductor layer 51 may be performed after the formation of the insulating layer 88.

[0317] After supplying the impurity element 93, heat treatment may be performed. By performing this heat treatment, damage sustained by the semiconductor layer 51 during the supply process of the impurity element 93 can be repaired.

[0318] The temperature of the heat treatment after supplying impurity element 93 is preferably 150°C or higher and below the strain point of the substrate, more preferably 200°C or higher and 700°C or lower, more preferably 200°C or higher and 650°C or lower, more preferably 250°C or higher and 500°C or lower, and more preferably 250°C or higher and 450°C or lower.

[0319] Next, as shown in Figure 23(A), an insulating layer 86 is formed on the insulating layer 88. After that, it is preferable to perform a planarization treatment on the upper surface of the insulating layer 86. For example, the CMP method can be used for the planarization treatment.

[0320] Next, as shown in Figure 23(B), openings 67a and 67b reaching the semiconductor layer 51 are formed in the insulating layer 86, insulating layer 88, and insulating layer 52. Specifically, opening 67a is formed to reach the low-resistance region 51na. Opening 67b is formed to reach the low-resistance region 51nb. Openings 67a and 67b are formed facing each other with the conductive layer 53 in between. For example, a resist mask is formed in a region where neither opening 67a nor opening 67b is formed, and the insulating layer 86, insulating layer 88, and insulating layer 52 in the region where the resist mask is not formed are removed by etching. After etching, the resist mask is removed. Dry etching is preferable as it facilitates the formation of fine openings 67a and 67b.

[0321] Next, as shown in Figure 23(C), a conductive layer 58a located inside the opening 67a and a conductive layer 58b located inside the opening 67b are formed. For example, conductive films that will become conductive layers 58a and conductive layers 58b are deposited such that they have regions located inside the opening 67a and regions located inside the opening 67b. These conductive films can be deposited using, for example, sputtering, CVD, or ALD.

[0322] Next, a planarization process such as CMP is performed to remove a portion of the conductive film, exposing the upper surface of the insulating layer 86. As a result, the conductive film remains inside the openings 67a and 67b, forming conductive layers 58a and 58b. Conductive layers 58a and 58b are formed to have regions in contact with the semiconductor layer 51. Specifically, conductive layer 58a is formed to have a region in contact with the low-resistance region 51na. Conductive layer 58b is formed to have a region in contact with the low-resistance region 51nb. Thus, a transistor 50 can be fabricated.

[0323] Next, as shown in Figure 23(D), a conductive layer 59 is formed such that it has a region in contact with the conductive layer 58a, a region in contact with the conductive layer 58b, and a region located on the insulating layer 86. For example, the conductive layer 59 can be formed such that it has a region in contact with the upper surface of the conductive layer 58a, a region in contact with the upper surface of the conductive layer 58b, and a region in contact with the upper surface of the insulating layer 86. The conductive layer 59 is formed so that it has a region extending in a predetermined direction. In the example shown in Figure 23(D), the conductive layer 59 is formed so that it extends in the Y direction. As a result, the semiconductor device shown in Figures 1(A) to 4(A) can be manufactured.

[0324] In one embodiment of the present invention, a semiconductor device is fabricated by forming a semiconductor layer 51, performing a heat treatment to crystallize the semiconductor layer 51, and then forming conductive layers 58a and 58b, which function as the source electrode and drain electrode of a transistor 50, respectively. This prevents oxidation of the conductive layers 58a and 58b caused by the heat treatment. Specifically, oxygen contained in the semiconductor layer 51 and oxygen contained in the heat treatment atmosphere are absorbed by the conductive layers 58a and 58b, preventing oxidation of the conductive layers 58a and 58b. As a result, a transistor exhibiting good electrical characteristics and high reliability can be fabricated. Furthermore, a highly reliable semiconductor device can be fabricated.

[0325] [Example of manufacturing method 2] In the following section, examples of semiconductor device manufacturing methods shown in Figures 6(A) to 8(B) will be explained using Figures 24(A) to 24(F). Figures 24(A) to 24(F) correspond to the cross-sectional views shown in Figure 8(A). Note that explanations of parts that overlap with [Manufacturing Method Example 1] described above will be omitted, and only the differences will be explained in detail.

[0326] The steps up to the formation of the insulating layer 52 can be seen in Figures 22(A) to 22(E). Here, the semiconductor layer 51 is formed to have a region extending in a predetermined direction. In the example shown in Figure 24(A), the semiconductor layer 51 is formed to extend in the Y direction.

[0327] After the insulating layer 52 is formed, a sacrificial layer 95 is formed so as to have a region located inside the opening 63, as shown in Figure 24(A). In the example shown in Figure 24(A), the sacrificial layer 95 is formed on the insulating layer 52. As the sacrificial layer 95, for example, one or both of an SOC (Spin On Carbon) film and an SOG (Spin On Glass) film can be formed. Preferably, as the sacrificial layer 95, for example, an SOC film and an SOG film on the SOC film are formed.

[0328] Next, as shown in Figure 24(B), an insulating layer 88 is formed on the sacrificial layer 95 and the insulating layer 52. Specifically, the insulating layer 88 is formed to cover the upper surface of the sacrificial layer 95 and the side surface located outside the opening 63. The insulating layer 88 can be formed using, for example, the ALD method, sputtering method, CVD method, MBE method, or PLD method, but the ALD method is preferable because it allows the insulating layer 88 to be formed to cover the sacrificial layer 95 with good coverage.

[0329] Next, as shown in Figure 24(B), impurity elements 93 are supplied to the semiconductor device. In Figure 24(B), the region along the side surface of the sacrificial layer 95 in the insulating layer 88 is defined as region 73. Through the process shown in Figure 24(B), impurity elements 93 can be supplied to the region of the semiconductor layer 51 that does not overlap with the sacrificial layer 95 and region 73. In other words, impurity elements 93 can be supplied to the semiconductor layer 51 by self-alignment, using the sacrificial layer 95 as a mask. As a result, a low-resistance region 51n can be formed.

[0330] Figure 24(B) shows an example where impurity elements 93 are supplied to the semiconductor device after the formation of the insulating layer 88, but impurity elements 93 may also be supplied before the formation of the insulating layer 88. That is, impurity elements 93 may be supplied to the semiconductor device immediately after the formation of the sacrificial layer 95 in the process shown in Figure 24(A). When impurity elements 93 are supplied to the semiconductor device before the formation of the insulating layer 88, a low-resistance region 51n is formed in the semiconductor layer 51, even in the region that overlaps with region 73.

[0331] Next, as shown in Figure 24(C), an insulating layer 86 is deposited on the insulating layer 88. Then, as shown in Figure 24(D), the upper surfaces of the insulating layer 86 and the insulating layer 88 are subjected to a planarization treatment using the CMP method or the like. This removes a portion of the insulating layer 86 and a portion of the insulating layer 88, exposing the upper surface of the sacrificial layer 95. In this case, a portion of the sacrificial layer 95 may be removed by the planarization treatment. Note that the method for removing a portion of the insulating layer 86 and a portion of the insulating layer 88 is not limited to planarization treatment; for example, anisotropic etching may be used.

[0332] Next, as shown in Figure 24(E), the sacrificial layer 95 is removed. The method of removing the sacrificial layer 95 is not particularly limited. By removing the sacrificial layer 95, an opening 66 is formed in the insulating layer 88, having a region that overlaps with the opening 63.

[0333] Next, as shown in Figure 24(F), a conductive layer 53 is formed such that it has a region located inside the opening 63 and a region located inside the opening 66. The conductive layer 53 is formed on the insulating layer 52. For example, a conductive film to become the conductive layer 53 is deposited. Subsequently, the upper surface of the conductive film is planarized using a method such as CMP to expose the upper surface of the insulating layer 86. As a result, the conductive film remains inside the opening 63 and the opening 66, thereby forming the conductive layer 53. The transistor 50A can be manufactured by this process.

[0334] Next, as shown in Figure 24(F), a conductive layer 77 is formed such that it has a region in contact with the upper surface of the conductive layer 53, a region located on the insulating layer 88, and a region located on the insulating layer 86. The conductive layer 77 is formed so that it has a region extending in a predetermined direction. In the example shown in Figure 24(F), the conductive layer 77 is formed to extend in the X direction. With the above steps, the semiconductor device shown in Figures 6(A) to 8(B) can be manufactured.

[0335] [Example of manufacturing method 3] In the following section, an example of a semiconductor device manufacturing method shown in Figures 9(A) and 9(B) will be explained using Figures 25(A) to 25(F). Figures 25(A) to 25(F) correspond to the cross-sectional view shown in Figure 9(A). Note that the explanation of parts that overlap with the above-mentioned [Manufacturing Method Example 2] will be omitted, and only the differences will be explained in detail.

[0336] The steps up to the formation of the semiconductor layer 51 can be seen in Figures 22(A) to 22(D). Here, the semiconductor layer 51 is formed to have a region extending in a predetermined direction, similar to the example shown in Figure 24(A). In the example shown in Figure 25(A), the semiconductor layer 51 is formed to extend in the Y direction.

[0337] After the formation of the semiconductor layer 51, a sacrificial layer 95 is formed so as to have a region located inside the opening 63, as shown in Figure 25(A). In the example shown in Figure 25(A), the sacrificial layer 95 is formed on the semiconductor layer 51.

[0338] Next, as shown in Figure 25(B), an insulating layer 88 is formed on the sacrificial layer 95 and the semiconductor layer 51. Then, as shown in Figure 25(B), impurity elements 93 are supplied to the semiconductor device.

[0339] Next, as shown in Figure 25(C), an insulating layer 86 is deposited on the insulating layer 88. Then, as shown in Figure 25(D), the upper surfaces of the insulating layer 86 and the insulating layer 88 are subjected to a planarization treatment using the CMP method or the like. After that, as shown in Figure 25(E), the sacrificial layer 95 is removed.

[0340] Next, as shown in Figure 25(F), an insulating layer 52 and a conductive layer 53 on the insulating layer 52 are formed such that they have a region located inside the opening 63 and a region located inside the opening 66. The insulating layer 52 is formed on the semiconductor layer 51. The insulating layer 52 can be formed along the recesses of the semiconductor layer 51 and along the sides of the insulating layer 88 at the opening 66.

[0341] For example, an insulating film to form the insulating layer 52 and a conductive film to form the conductive layer 53 are deposited in sequence. Subsequently, the upper surfaces of the conductive film and the insulating film are planarized using methods such as CMP to expose the upper surface of the insulating layer 86. As a result, the insulating film and the conductive film remain inside the openings 63 and 66, respectively, forming the insulating layer 52 and the conductive layer 53. Transistor 50A can be manufactured in this manner.

[0342] Next, as shown in Figure 25(F), the conductive layer 77 is formed such that it has a region in contact with the upper surface of the conductive layer 53, a region located on the insulating layer 52, a region located on the insulating layer 88, and a region located on the insulating layer 86. Through this process, the semiconductor device shown in Figures 9(A) and 9(B) can be fabricated.

[0343] In the semiconductor device manufacturing method shown in Figures 25(A) to 25(F), the impurity element 93 shown in Figure 25(B) is supplied to the semiconductor layer 51 without passing through the insulating layer 52. Therefore, it is possible to prevent the impurity element 93 from being blocked by the insulating layer 52. On the other hand, in the semiconductor device manufacturing method shown in Figures 24(A) to 24(F), it is easier to suppress the impurity element 93 shown in Figure 24(B) from penetrating the semiconductor layer 51 and being supplied to, for example, the insulating layer 62, compared to the method shown in Figures 25(A) to 25(F).

[0344] <Component materials for semiconductor devices> The following describes materials that can be used in the semiconductor device of this embodiment. Note that each layer constituting the semiconductor device of this embodiment may be a single-layer structure or a multilayer structure.

[0345] [Semiconductor layer] As mentioned above, an indium oxide film can be used as the semiconductor layer (semiconductor layer 51, etc.) of the memory device. Alternatively, a metal oxide other than indium oxide may be used as the semiconductor layer. In this case, for example, gallium oxide or zinc oxide can be used as the semiconductor layer. When a metal oxide other than indium oxide is used as the semiconductor layer, it is preferable that the metal oxide contains one or more elements selected from indium, element M, and zinc. Element M is one or more elements selected from aluminum, gallium, silicon, yttrium, tin, copper, vanadium, chromium, manganese, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, calcium, strontium, barium, cobalt, and antimony. In particular, it is preferable that element M is one or more elements selected from gallium, tungsten, aluminum, yttrium, and tin. For example, metal oxides used in semiconductor layers include indium gallium oxide (In-Ga oxide, also known as IGO), indium zinc oxide (In-Zn oxide), or indium tungsten oxide (In-W oxide, also known as IWO).

[0346] Furthermore, indium gallium zinc oxide (In-Ga-Zn oxide, also known as IGZO) can be used as the metal oxide for the semiconductor layer. Alternatively, an oxide containing indium, tin, and zinc (In-Sb-Zn oxide, also known as ITZO®) can be used. Alternatively, an oxide containing indium, gallium, tin, and zinc (In-Ga-Sb-Zn oxide) can be used. Alternatively, an oxide containing indium, aluminum, and zinc (In-Al-Zn oxide, also known as IAZO) can be used. Alternatively, an oxide containing indium, aluminum, gallium, and zinc (In-Al-Ga-Zn oxide, also known as IAGZO) can be used.

[0347] Other semiconductor materials besides metal oxides may be used as the semiconductor layer. Examples of such other semiconductor materials include semiconductors composed of elemental elements or compound semiconductors.

[0348] Examples of semiconductors composed of single elements that can be used as semiconductor materials include silicon and germanium. Examples of silicon that can be used as semiconductor materials include single-crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. An example of polycrystalline silicon is low-temperature polysilicon (LTPS).

[0349] Examples of compound semiconductors that can be used in semiconductor materials include silicon carbide, silicon germanium, gallium arsenide, indium phosphide, boron nitride, and boron arsenide. Boron nitride that can be used in semiconductor layers preferably contains an amorphous structure. Boron arsenide that can be used in semiconductor layers preferably contains a cubic crystal structure. Other examples of compound semiconductors include organic semiconductors and nitride semiconductors. Note that the oxide semiconductors mentioned above are also a type of compound semiconductor. These semiconductor materials may contain impurities as dopants.

[0350] [Insulating layer] It is preferable to use inorganic insulating films for the insulating layers of a semiconductor device (insulating layer 52, insulating layer 62, insulating layer 65, insulating layer 69a, insulating layer 69b, insulating layer 74, insulating layer 86, insulating layer 87, insulating layer 88, etc.). Examples of inorganic insulating films include oxide insulating films, nitride insulating films, and oxidative nitride insulating films. Examples of oxide insulating films include silicon oxide films, aluminum oxide films, magnesium oxide films, gallium oxide films, germanium oxide films, yttrium oxide films, zirconium oxide films, lanthanum oxide films, neodymium oxide films, hafnium oxide films, tantalum oxide films, cerium oxide films, gallium zinc oxide films, and oxide films containing aluminum and hafnium. Examples of nitride insulating films include silicon nitride films and aluminum nitride films. Examples of oxidative nitride insulating films include silicon oxidative nitride films, aluminum oxidative nitride films, gallium oxidative nitride films, yttrium oxidative nitride films, and hafnium oxidative nitride films. Organic insulating films may also be used for the insulating layers of a semiconductor device.

[0351] For example, as transistors become smaller and more integrated, thinning of the gate insulating layer can lead to problems such as leakage current. By using a material with a high dielectric constant (high-k) for the gate insulating layer, it is possible to lower the voltage during transistor operation while maintaining the physical film thickness. It also becomes possible to thin the EOT of the gate insulating layer. On the other hand, by using a material with a low dielectric constant for the insulating layer that functions as an interlayer insulating layer, parasitic capacitance between wiring can be reduced. Therefore, it is preferable to select the material according to the function of the insulating layer. It should be noted that materials with a low dielectric constant also have high dielectric strength.

[0352] Examples of materials with a high dielectric constant include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, oxides containing hafnium and zirconium, oxides containing aluminum and hafnium, oxides containing aluminum and hafnium, oxides containing silicon and hafnium, oxides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0353] Examples of materials with low dielectric constant include inorganic insulating materials such as silicon oxide and silicon oxynitride, and resins such as polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic resin. Other inorganic insulating materials with low dielectric constant include silicon oxide containing fluorine, silicon oxide containing carbon, and silicon oxide containing carbon and nitrogen. Also, for example, silicon oxide having vacancies can be used. These silicon oxides may contain nitrogen.

[0354] Furthermore, a ferroelectric material may be used for the insulating layer of the semiconductor device. Preferably, an oxide containing one or both hafnium and zirconium is used as the ferroelectric material. Examples of such oxides include metal oxides such as hafnium oxide, zirconium oxide, and hafnium-zirconium oxide. Alternatively, a material may be used in which element J1 (where element J1 is one or more selected from the other of hafnium and zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) is added to a metal oxide containing either hafnium or zirconium as the ferroelectric material.

[0355] Furthermore, by adding a Group 3 element from the periodic table to an oxide containing one or both hafnium and zirconium, the oxygen vacancy concentration in the oxide increases, making it easier to form crystals with an orthorhombic crystal structure. This is preferable because it increases the proportion of crystals with an orthorhombic crystal structure and allows for a larger amount of remanent polarization. On the other hand, if too much Group 3 element is added, the crystallinity of the oxide may decrease, making it difficult to exhibit ferroelectric properties. Therefore, the content of Group 3 elements in an oxide containing one or both hafnium and zirconium is preferably 0.1 atomic% to 10 atomic%, more preferably 0.1 atomic% to 5 atomic%, and even more preferably 0.1 atomic% to 3 atomic%. Here, the content of Group 3 elements refers to the ratio of the number of Group 3 elements to the sum of the number of atoms of all metal elements contained in the layer. The Group 3 element is preferably one or more selected from scandium, lanthanum, and yttrium, and more preferably one or both of lanthanum and yttrium.

[0356] Furthermore, a material that may possess ferroelectric properties is a metal nitride having at least one of elements M1 and M2, and nitrogen. Here, element M1 is one or more selected from aluminum, gallium, indium, etc. Element M2 is one or more selected from boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, etc. Another material that may possess ferroelectric properties is a material in which element M3 is added to the above metal nitride. Element M3 is one or more selected from magnesium, calcium, strontium, zinc, cadmium, etc.

[0357] Furthermore, materials that may possess ferroelectric properties include perovskite-type oxidnitrides such as SrTaO2N and BaTaO2N, and GaFeO3 with a κ-alumina structure. In addition, lead titanate (PbTiO3) is another material that may possess ferroelectric properties. X), or piezoelectric ceramics having a perovskite structure such as barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), or barium titanate may be used.

[0358] While the above explanation uses metal oxides and metal nitrides as examples, it is not limited to these. For example, materials obtained by adding nitrogen to the aforementioned metal oxides, or materials obtained by adding oxygen to the aforementioned metal nitrides, may also be used.

[0359] Furthermore, as a material that may possess ferroelectricity, for example, a mixture or compound consisting of multiple materials selected from the materials listed above can be used. Incidentally, since the crystal structure (properties) of the materials listed above may change not only depending on the film deposition conditions but also on various processes, in this specification, materials that exhibit ferroelectricity are not only called ferroelectrics, but also materials that may possess ferroelectricity.

[0360] In this specification, a layered structure of a material capable of ferroelectricity may be referred to as a ferroelectric layer, a metal oxide layer, or a metal nitride film. Furthermore, a device having such a ferroelectric layer, metal oxide layer, or metal nitride film may be referred to as a ferroelectric device in this specification.

[0361] The ferroelectric layer is preferably composed of crystals having an orthorhombic crystal structure, as this exhibits ferroelectric properties. The crystal structure of the crystals included in the ferroelectric layer may be one or more selected from tetragonal, orthorhombic, monoclinic, and hexagonal systems. The ferroelectric layer may also have an amorphous structure. In this case, the ferroelectric layer may have a composite structure comprising both an amorphous and a crystalline structure.

[0362] Metal oxides containing either or both hafnium and zirconium are insulating materials that have the function of capturing or fixing hydrogen. Therefore, by using a metal oxide containing either or both hafnium and zirconium in at least a portion of the gate insulating layer, hydrogen contained in the oxide semiconductor layer can be captured or fixed, thereby reducing the hydrogen concentration in the oxide semiconductor layer. Furthermore, a transistor having this gate insulating layer can function as an FeFET (Ferroelectric Field Effect Transistor).

[0363] Furthermore, transistors using metal oxides can have their electrical characteristics stabilized by surrounding them with an insulating layer that has the function of suppressing the permeation of impurities and oxygen. As an insulating layer that has the function of suppressing the permeation of impurities and oxygen, for example, an insulating layer containing one or more selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum can be used in a single layer or multilayer configuration. Specifically, as the material for the insulating layer that has the function of suppressing the permeation of impurities and oxygen, metal oxides such as aluminum oxide, magnesium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide, nitrides such as aluminum nitride or silicon nitride, and oxidized nitrides such as silicon oxiditride can be used.

[0364] Specifically, materials for insulating layers that have the function of suppressing the permeation of impurities such as water and hydrogen, and oxygen, include metal oxides such as aluminum oxide, magnesium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, and oxides containing aluminum and hafnium. Also, nitrides such as aluminum nitride, titanium aluminum nitride, and silicon nitride are mentioned. Furthermore, oxidized nitrides such as silicon oxynitride are mentioned. Additionally, gallium oxide is mentioned as a material for insulating layers that has the function of suppressing oxygen permeation.

[0365] Furthermore, insulating layers that are in contact with the oxide semiconductor layer, such as gate insulating layers, or insulating layers provided near the oxide semiconductor layer, are preferably insulating layers that contain regions containing excess oxygen. For example, by having an insulating layer containing regions containing excess oxygen in contact with or near the oxide semiconductor layer, the oxygen vacancies in the oxide semiconductor layer can be reduced.

[0366] It is preferable to use a hydrogen barrier insulating layer for the insulating layer in contact with the oxide semiconductor layer, or an insulating layer provided near the oxide semiconductor layer. The insulating layer's hydrogen barrier properties suppress the diffusion of hydrogen into the oxide semiconductor layer. A hydrogen barrier insulating layer can also be described as an insulating layer that has the function of suppressing hydrogen diffusion.

[0367] Examples of insulating materials having the function of capturing or fixing hydrogen include metal oxides such as hafnium-containing oxides, magnesium-containing oxides, aluminum-containing oxides, aluminum and hafnium-containing oxides, and hafnium and silicon-containing oxides. Furthermore, these metal oxides may also contain zirconium; for example, examples include oxides containing hafnium and zirconium.

[0368] An insulating layer having the function of capturing or fixing hydrogen preferably has an amorphous structure. In metal oxides having an amorphous structure, some oxygen atoms have dangling bonds, thus having a high ability to capture or fix hydrogen. Therefore, by having an amorphous structure in the insulating layer, the function of capturing or fixing hydrogen can be enhanced.

[0369] By making the insulating layer amorphous, the formation of grain boundaries can be suppressed. Suppressing the formation of grain boundaries improves the flatness of the insulating layer. This makes the thickness distribution of the insulating layer more uniform, reducing areas with extremely thin thickness, and thus improving the dielectric strength of the insulating layer. Furthermore, the thickness distribution of the film provided on the insulating layer can be made more uniform. In addition, suppressing the formation of grain boundaries in the insulating layer reduces leakage current caused by defect levels at the grain boundaries. Therefore, the insulating layer can function as an insulating film with low leakage current.

[0370] Furthermore, the function of capturing or fixing a corresponding substance can also be described as the property of making the corresponding substance difficult to diffuse. Therefore, the function of capturing or fixing a corresponding substance can be rephrased as barrier properties.

[0371] Examples of materials for the barrier insulating layer against hydrogen include aluminum oxide, magnesium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxides containing hafnium and zirconium, silicon nitride, or silicon oxynitride.

[0372] The inorganic insulating layers listed as having the function of capturing or fixing hydrogen, and the function of suppressing hydrogen diffusion, also possess barrier properties against oxygen. Examples of materials for the oxygen barrier insulating layer include oxides containing one or both of aluminum and hafnium, magnesium oxide, zinc gallium oxide, silicon nitride, silicon oxynitride, etc. Examples of oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium, oxides containing hafnium and silicon, etc.

[0373] [Conductive layer] It is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, palladium, iridium, strontium, lanthanum, etc., or an alloy composed of the aforementioned metal elements, or an alloy combining the aforementioned metal elements, etc., for the conductive layers (conductive layer 53, conductive layer 55, conductive layer 58a, conductive layer 58b, conductive layer 59, conductive layer 60, conductive layer 77, etc.) of a semiconductor device. Alternatively, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements like phosphorus, or silicides such as nickel silicide may be used.

[0374] Furthermore, conductive materials containing nitrogen, such as nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing ruthenium, nitrides containing tantalum and aluminum, or nitrides containing titanium and aluminum; conductive materials containing oxygen, such as oxides containing ruthenium oxide, strontium and ruthenium, or oxides containing lanthanum and nickel; and materials containing metallic elements such as titanium, tantalum, or ruthenium are preferred because they are conductive materials that are resistant to oxidation, conductive materials that have the function of suppressing oxygen diffusion, or materials that maintain conductivity even when absorbing oxygen. Examples of conductive materials containing oxygen include indium oxide containing tungsten oxide, indium oxide containing titanium oxide, ITO, indium tin oxide containing titanium oxide, ITSO, In-Zn oxide, and indium zinc oxide containing tungsten oxide. In this specification, conductive films formed using conductive materials containing oxygen are sometimes referred to as oxide conductive films.

[0375] Furthermore, multiple conductive layers formed from the above materials may be used in a laminated structure. For example, a laminated structure may be formed by combining the aforementioned metal element material with an oxygen-containing conductive material. Alternatively, a laminated structure may be formed by combining the aforementioned metal element material with a nitrogen-containing conductive material. Alternatively, a laminated structure may be formed by combining the aforementioned metal element material with an oxygen-containing conductive material and a nitrogen-containing conductive material.

[0376] Furthermore, when using a metal oxide for the channel formation region of a transistor, it is preferable to use a laminated structure for the conductive layer that functions as the gate electrode, which combines a material containing the aforementioned metal element with a conductive material containing oxygen. In this case, it is preferable to provide the conductive material containing oxygen on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen detached from the conductive material is more easily supplied to the channel formation region.

[0377] [substrate] As substrates for forming transistors, for example, insulating substrates, semiconductor substrates, or conductive substrates can be used. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (such as yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Furthermore, there are semiconductor substrates having insulating regions within the aforementioned semiconductor substrates, such as SOI (Silicon On Insulator) substrates. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, or conductive resin substrates. Alternatively, there are substrates having metal nitrides or metal oxides. Furthermore, there are substrates on which a conductor or semiconductor is provided on an insulating substrate, substrates on which a conductor or insulator is provided on a semiconductor substrate, and substrates on which a semiconductor or insulator is provided on a conductive substrate. Alternatively, substrates on which elements are provided may be used. Elements provided on the substrate include capacitive elements, resistive elements, switch elements, light-emitting elements, or memory elements.

[0378] The above describes the materials that can be used in the semiconductor device of this embodiment.

[0379] This embodiment can be combined with other embodiments as appropriate. Furthermore, if multiple configuration examples are shown within a single embodiment in this specification, these configuration examples can be combined as appropriate.

[0380] (Embodiment 2) This embodiment describes an indium oxide film that can be used in the semiconductor layer of a transistor in a semiconductor device according to one aspect of the present invention.

[0381] Indium oxide is a semiconductor material with completely different physical properties from oxide semiconductors such as In-Ga-Zn oxide (hereinafter also referred to as IGZO) and zinc oxide.

[0382] This paper describes the carrier concentration dependence of the hole mobility of indium oxide, silicon, and IGZO.

[0383] IGZO tends to exhibit higher hole mobility as the carrier concentration increases. On the other hand, single-crystal indium oxide tends to exhibit higher hole mobility as the carrier concentration decreases. This trend is similar to that of silicon, where lower dopant (impurity) concentrations in the film reduce impurity scattering and increase hole mobility. In other words, the higher the purity and intrinsic nature of single-crystal indium oxide, the higher its hole mobility. From these results, it can be said that single-crystal indium oxide, unlike IGZO, is a material with physical properties closer to silicon. Note that when indium oxide is not single-crystal (e.g., polycrystalline), the trend may differ from that of single-crystal indium oxide.

[0384] The range of carrier concentrations suitable for the channel formation region of a transistor is 1 × 10⁻⁶. 15 cm -3 This range includes, for example, 1 × 10 14 cm -3 The above is 1 x 10 18 cm -3 The range is as follows: By sufficiently reducing the carrier concentration, the hole mobility value can be increased to 270 cm⁻¹. 2 It can be expected to be raised to the level of (V·s).

[0385] Indium oxide can contain elements that lower the carrier concentration. Examples of elements that lower the carrier concentration include magnesium, calcium, zinc, cadmium, and copper. These elements can lower the carrier concentration by substituting for indium. Other examples include nitrogen, phosphorus, arsenic, and antimony. These elements can lower the carrier concentration by substituting for oxygen.

[0386] On the other hand, electrical resistance can be reduced by increasing the carrier concentration. For example, the suitable carrier concentration range for the source and drain regions of a transistor, or for a resistor or transparent conductive film, is when the carrier concentration value is 1 × 10⁻⁶ 20cm -3 This range includes, for example, 1 × 10 19 cm -3 The above is 1 x 10 22 cm -3 The range is as follows: By making the carrier concentration sufficiently high, the resistivity can be increased to 1 × 10⁻⁶. -4 It is expected that the level can be reduced to below Ω·cm.

[0387] Indium oxide may contain elements that increase the carrier concentration. For example, it is preferable to include elements common to the source and drain electrodes of the transistor. Examples of such elements include titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, and silicon. It is particularly preferable to use elements in which the oxide is conductive or semiconducting.

[0388] Because indium oxide is an oxide whose valence electrons can be controlled, the region with a low carrier concentration can be used for the channel formation region of the transistor, and the region with a high carrier concentration can be used for the source and drain regions of the transistor. This makes it possible to create a so-called NIN junction (a junction between an n-type region, an i-type region, and an n-type region). Valence electron control in transistors using silicon is generally known. On the other hand, valence electron control in transistors using indium oxide is a novel technological concept that would not normally be conceived. By using this technological concept, it is possible to realize a transistor with high mobility, low off-current, normally-off capability, and high reliability.

[0389] The indium oxide film is preferably crystalline. In particular, the indium oxide film is preferably polycrystalline, and more preferably single-crystal. A single-crystal film does not have grain boundaries. By using a single-crystal film, carrier scattering at grain boundaries can be suppressed, enabling the realization of transistors with high field-effect mobility. Furthermore, it has the excellent effect of suppressing variations in transistor characteristics caused by these grain boundaries.

[0390] Furthermore, polycrystalline films are preferable because they can reduce carrier scattering and exhibit high field-effect mobility compared to microcrystalline or amorphous films. When using polycrystalline films, it is preferable to use films with the largest possible grain size and low grain boundary density. In a transistor to which a polycrystalline film is applied, if there are no grain boundaries in the channel formation region, or if no grain boundaries are observed, the channel formation region is located within the single-crystal region contained in the polycrystalline film, and therefore it can be considered a transistor to which a single-crystal film is applied.

[0391] The crystallinity of indium oxide can be analyzed, for example, by XRD, TEM, or ED. Alternatively, a combination of these methods may be used for analysis.

[0392] Furthermore, in this specification, a semiconductor layer in which no grain boundaries are observed in the channel formation region, a semiconductor layer in which the channel formation region is contained within a single crystal grain, or a semiconductor layer in which the direction of the crystal axes is the same in at least two regions within the channel formation region can be considered as a single crystal film.

[0393] The channel formation region refers to the region of the semiconductor layer that overlaps with (or faces) the gate electrode via the gate insulating layer, and is located between the region in contact with the source electrode and the region in contact with the drain electrode. The crystal grains, grain boundaries, crystal axes, and crystal orientation in the channel formation region can be confirmed by cross-sectional observation including the semiconductor layer, source electrode, and drain electrode.

[0394] Impurities in indium oxide can act as carrier scattering sources, thus potentially causing a decrease in field-effect mobility and inhibiting crystal growth. Examples of impurities in indium oxide films include gallium, zinc, boron, aluminum, and silicon. In indium oxide films, lower concentrations of these impurities in the channel-forming regions are preferable. For example, the concentration of each of the above impurity elements should be 0.1% or less, more preferably 0.01% (100 ppm) or less. Note that carbon, hydrogen, and other elements may be present in the deposition gas or precursor during film formation, and may remain in the indium oxide film in higher concentrations than the above impurities.

[0395] By using such an indium oxide film in a transistor, the field-effect mobility of the transistor can be increased to 50 cm². 2 / (V·s) or more, preferably 100cm 2 (V·s) or more, more preferably 150cm 2 / (V·s) or more, more preferably 200cm 2 / (V·s) or more, more preferably 250cm 2 It can be set to (V·s) or more.

[0396] One of the characteristics of indium oxide films is their higher oxygen permeability (diffusivity) compared to IGZO films. For example, oxygen diffusing into an indium oxide film permeates the film and is released as oxygen molecules. In some cases, it may also be released as water molecules by reacting with hydrogen contained in the film. Furthermore, if there is an oxygen deficiency in the film, diffusing oxygen atoms will fill the deficiency. Because oxygen diffuses easily into indium oxide films, it can be said that oxygen deficiencies are more easily filled in compared to IGZO films.

[0397] Thus, because indium oxide films are more prone to reducing oxygen vacancies in the film compared to IGZO films, applying such indium oxide films to transistors makes it possible to realize transistors with extremely high reliability.

[0398] Furthermore, the indium oxide film diffuses hydrogen. Hydrogen diffusing into the indium oxide film from the outside permeates the film and is released as hydrogen molecules. Alternatively, it reacts with oxygen contained in the film and is released as water molecules.

[0399] Indium oxide is characterized by a small effective electron mass and a large effective hole mass. Furthermore, the effective electron mass of indium oxide is largely independent of the crystal orientation. Therefore, using crystalline indium oxide in transistors allows for the realization of transistors with high field-effect mobility and high frequency characteristics (also known as f-response). Additionally, due to the large effective hole mass, transistors with extremely low off-currents can be realized. For example, by applying an indium oxide film to a vertical transistor, the off-current per 1 μm of channel width is 1 fA (1 × 10⁻¹⁶) at 125°C. -15 A) Less than or equal to, or 1aA(1 × 10 -18 A) is less than or equal to 1aA(1 × 10) under room temperature (25°C) conditions. -18 A) Less than or equal to 1zA(1×10) -21 A) The following is possible. Furthermore, because indium oxide has a smaller effective electron mass and a larger effective hole mass than silicon, it may be possible to realize transistors with higher field-effect mobility and lower off-current than Si transistors.

[0400] It is preferable to use a material containing crystals with a small difference in lattice constant (also called lattice mismatch) from indium oxide for the layer or substrate (hereinafter collectively referred to as the film to be formed) that forms the surface on which the crystalline indium oxide film is formed. This makes it possible to improve the crystallinity of the indium oxide film.

[0401] One method for evaluating the degree of lattice mismatch is the lattice mismatch index. The lattice mismatch index Δa [%] of the crystals of the forming film (in this case, the indium oxide film) relative to the crystals of the film being formed is calculated as Δa = ((L1 - L2) / L2) × 100. Here, L1 is the length of the unit cell vector or lattice constant of the crystals of the forming film, and L2 is the length of the unit cell vector or lattice constant of the crystals of the film being formed.

[0402] The lattice mismatch Δa between the formed film and the indium oxide film is preferably small in absolute value, and most preferably 0. For example, Δa can be -5% or more and 5% or less, preferably -4% or more and 4% or less, more preferably -3% or more and 3% or less, and even more preferably -2% or more and 2% or less.

[0403] Here, the indium oxide crystal has a cubic structure (bixbite type). For example, the YSZ crystal can have a cubic structure (fluorite type). The lattice mismatch of the indium oxide crystal with respect to the cubic YSZ crystal is in the range of -2% to 2%, and a single crystal film of indium oxide can be epitaxially grown on a YSZ substrate.

[0404] Furthermore, the crystal structure of the film to be formed and the crystal structure of the indium oxide film do not necessarily have to be the same in terms of crystal system or crystal orientation. For example, a film with a hexagonal or trigonal crystal structure can be used beneath an indium oxide film with a cubic crystal structure. For instance, by setting the crystal orientation of the surface of the film to be formed to

[0001] and the crystal orientation of the underside of the indium oxide film to

[0111] , the requirements related to crystal orientation necessary for epitaxial growth can be met. Examples of hexagonal or trigonal crystals include wurtzite-type structures, YbFe2O4-type structures, Yb2Fe3O7-type structures, and modified forms thereof. An example of a crystal having a YbFe2O4-type or Yb2Fe3O7-type structure is IGZO.

[0405] This embodiment can be combined with other embodiments as appropriate. Furthermore, if multiple configuration examples are shown within a single embodiment in this specification, these configuration examples can be combined as appropriate.

[0406] (Embodiment 3) This embodiment describes a storage device according to one aspect of the present invention. The storage device according to one aspect of the present invention has a memory cell. The memory cell has a transistor and a capacitive element.

[0407] The configuration of a memory device having memory cells will be explained using Figures 26(A) to 27(C). Figure 26(A) is a plan view of a memory device having memory cells 150. Figure 26(B) is a cross-sectional view between the dashed-dotted lines A1 and A2 shown in Figure 26(A). Figure 26(C) is a cross-sectional view between the dashed-dotted lines B1 and B2 shown in Figure 26(A).

[0408] The memory device shown in Figures 26(A) to 26(C) comprises an insulating layer 140 on a substrate (not shown), a conductive layer 110 on the insulating layer 140, memory cells 150 on the conductive layer 110, an insulating layer 180 on the conductive layer 110, and an insulating layer 62 on the insulating layer 180. The insulating layers 140 and 180 function as interlayer insulating layers. The conductive layer 110 functions as wiring.

[0409] The memory cell 150 includes a capacitive element 100 on a conductive layer 110 and a transistor 50 on the capacitive element 100.

[0410] The capacitive element 100 has a conductive layer 115 on a conductive layer 110, an insulating layer 130 on the conductive layer 115, and a conductive layer 55 on the insulating layer 130. The conductive layer 55 functions as one of a pair of electrodes (sometimes called the upper electrode), the conductive layer 115 functions as the other of a pair of electrodes (sometimes called the lower electrode), and the insulating layer 130 functions as a dielectric. In other words, the capacitive element 100 constitutes a MIM (Metal-Insulator-Metal) capacitance.

[0411] As shown in Figures 26(B) and 26(C), the insulating layer 180 is provided with an opening 190 that reaches the conductive layer 110. At least a portion of the conductive layer 115 is located inside the opening 190. The conductive layer 115 has a region that contacts the upper surface of the conductive layer 110 at the opening 190 and a region that contacts the side surface of the insulating layer 180 at the opening 190. At least a portion of the insulating layer 130 is located inside the opening 190. At least a portion of the conductive layer 55 is located inside the opening 190. The conductive layer 55 is provided so as to fill the opening 190. A capacitive element 100 having such a configuration may be called a trench-type capacitor or trench capacitor. It is preferable that the films provided in the opening 190 be formed using the ALD method. This results in good coverage of the films. For example, it is preferable that the conductive layer 115, the insulating layer 130, and the conductive layer 55 be formed using the ALD method.

[0412] In the capacitive element 100, the upper electrode and lower electrode face each other across the dielectric not only on the bottom surface but also on the sides of the opening 190, allowing for a large capacitance per unit area. Therefore, the deeper the opening 190, the larger the capacitance of the capacitive element 100 can be. By increasing the capacitance per unit area of ​​the capacitive element 100 in this way, the read operation of the memory device can be made more stable. Furthermore, miniaturization or high integration of the memory device can be promoted.

[0413] Figures 26(B) and 26(C) show an example where the side wall of the opening 190 is perpendicular to the upper surface of the conductive layer 110, and the opening 190 is circular in plan view. This configuration allows for miniaturization or high integration of the memory device.

[0414] The conductive layer 110 functions as a wiring CAL, as described later, and can be provided in a strip shape, for example. A strip shape refers to a shape having a region extending in a certain direction (for example, the X direction, Y direction, or Z direction).

[0415] The conductive layer 110 can be formed as a single layer or in a laminated form using the conductive material described in the [conductive layer] of Embodiment 1. For example, a highly conductive material such as tungsten can be used as the conductive layer 110. By using a highly conductive material, the conductivity of the conductive layer 110 can be improved, allowing it to function sufficiently as a wiring CAL.

[0416] The conductive layer 115 has a region with a curved corner within the recess of the conductive layer 110. This suppresses electric field concentration on the insulating layer 130 near the region, compared to, for example, when the region has a corner (right angle or acute angle) in cross-sectional view. Therefore, dielectric breakdown of the insulating layer 130 is suppressed, and a highly reliable memory device can be provided.

[0417] The conductive layer 115 is preferably made of a conductive material that is resistant to oxidation, or a conductive material that has the function of suppressing oxygen diffusion, and is used in a single layer or laminate. For example, titanium nitride or ITSO may be used. Alternatively, for example, a structure in which a titanium nitride film is laminated on a tungsten film may be used. Alternatively, for example, a structure in which a tungsten film is laminated on a first titanium nitride film, and a second titanium nitride film is laminated on the tungsten film may be used. By using such a structure, if an oxide is used for the insulating layer 130, oxidation of the conductive layer 110 by the insulating layer 130 can be suppressed. Also, if an oxide is used for the insulating layer 180, oxidation of the conductive layer 110 by the insulating layer 180 can be suppressed.

[0418] The insulating layer 130 is provided so as to be in contact with the upper and side surfaces of the conductive layer 115. In other words, it is preferable that the insulating layer 130 has a structure that covers the side edges of the conductive layer 110. This prevents the conductive layer 115 and the conductive layer 55 from short-circuiting.

[0419] It is preferable to use a high-k material as the insulating layer 130. By using a high-k material as the insulating layer 130, the insulating layer 130 can be made thick enough to suppress leakage current, while also ensuring sufficient capacitance of the capacitive element 100.

[0420] Furthermore, the insulating layer 130 is preferably made by laminating insulating layers made of high-k materials, and it is preferable to use a laminated structure of a high-k material and a material with a higher dielectric strength than the high-k material. For example, as the insulating layer 130, an insulating film laminated in the order of zirconium oxide, aluminum oxide, and zirconium oxide can be used. Alternatively, for example, an insulating film laminated in the order of zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide can be used. Alternatively, for example, an insulating film laminated in the order of hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide can be used. By laminating insulating layers with relatively high dielectric strength, such as aluminum oxide, the dielectric strength is improved, and electrostatic discharge breakdown of the capacitive element 100 can be suppressed.

[0421] Furthermore, a material capable of ferroelectricity may be used as the insulating layer 130. For details on materials capable of ferroelectricity, please refer to the description in Embodiment 1.

[0422] Ferroelectric materials are insulators that exhibit internal polarization when an external electric field is applied, and this polarization remains even when the electric field is removed. Therefore, non-volatile memory elements can be formed using capacitive elements (sometimes referred to as ferroelectric capacitors) that utilize this material as a dielectric. Non-volatile memory elements using ferroelectric capacitors are sometimes called FeRAM (Ferroelectric Random Access Memory) or ferroelectric memory. For example, a ferroelectric memory has a transistor and a ferroelectric capacitor, with one of the transistor's sources and drains connected to one terminal of the ferroelectric capacitor. Therefore, when a ferroelectric capacitor is used as the capacitive element 100, the memory device shown in this embodiment functions as a ferroelectric memory.

[0423] The conductive layer 55 is provided in contact with the upper surface of the insulating layer 130. The side edges of the conductive layer 55 can be structured to coincide with the side edges of the insulating layer 130. This structure allows the conductive layer 55 and the insulating layer 130 to be formed using the same mask, simplifying the manufacturing process of the memory device. The side edges of the conductive layer 55 may be positioned inward from the side edges of the insulating layer 130 in either the X or Y direction.

[0424] Since the insulating layer 180 functions as an interlayer insulating layer, it is preferable that it has a low dielectric constant. By using a material with a low dielectric constant as the interlayer insulating layer, parasitic capacitance between wiring can be reduced.

[0425] A detailed explanation of transistor 50 will be omitted as it can be found in the description in Embodiment 1. Furthermore, the transistors in the memory cell 150 are not limited to transistor 50, and various transistors such as transistor 50A and transistor 50B exemplified in Embodiment 1 can be applied. In addition, transistors with a planar structure or a GAA (Gate All Around) structure (including a GAA nanosheet structure) can also be applied.

[0426] As shown in Figures 26(A) to 26(C), the transistor 50 is provided so as to overlap with the capacitive element 100. Furthermore, the opening 63, through which part of the transistor 50's structure is provided, has an overlapping region with the opening 190, through which part of the capacitive element 100's structure is provided. In particular, the conductive layer 55 functions as both the source electrode and the drain electrode of the transistor 50, and as the upper electrode of the capacitive element 100; therefore, the transistor 50 and the capacitive element 100 share a portion of their structure. This configuration allows the transistor 50 and the capacitive element 100 to be provided without significantly increasing the occupied area in a plan view. This reduces the occupied area of ​​the memory cell 150, allowing for a higher density arrangement of the memory cell 150 and thus increasing the storage capacity of the memory device. In other words, the memory device can be highly integrated. Figures 26(B) and 26(C) show an example where the width of the opening 190 is smaller than the width of the opening 63. The relative sizes of the widths of the opening 190 and 63 are not particularly limited. From the viewpoint of miniaturization, it is preferable that the width of the opening 190 is the same as or smaller than the width of the opening 63.

[0427] Furthermore, by positioning the transistor 50 above the capacitive element 100, the transistor 50 is not affected by the heat treatment during the manufacturing of the capacitive element 100. Therefore, in the transistor 50, fluctuations in the threshold voltage, deterioration of electrical characteristics such as an increase in parasitic resistance, and an increase in variations in electrical characteristics due to the deterioration of electrical characteristics can be suppressed.

[0428] In the examples shown in Figures 26(A) to 26(C), the conductive layer 53 is provided extending in the X direction, and the conductive layer 59 is provided extending in the Y direction.

[0429] The configuration shown in Figures 26(A) to 26(C) functions as a memory cell. The memory cell will be described in detail in a later embodiment.

[0430] The memory cell 150 can also have transistors instead of capacitive elements. In this case, the memory cell 150 has two transistors.

[0431] Figure 27(A) is a plan view of the memory device. Figure 27(B) is a cross-sectional view between the dashed-dotted lines A1 and A2 shown in Figure 27(A). Figure 27(C) is a cross-sectional view between the dashed-dotted lines B1 and B2 shown in Figure 27(A).

[0432] The memory device shown in Figures 27(A) to 27(C) has a memory cell 150 on an insulating layer 87. The memory cell 150 has a transistor 50a and a transistor 50b on transistor 50a. Here, Figure 27(A) shows an example of the configuration of transistor 50b.

[0433] Figures 27(A) to 27(C) show examples where the transistor 50 shown in Figures 5(A) and 5(B) is used as transistor 50a. Also, examples where the transistor 50 shown in Figures 1(A) to 4(A) is used as transistor 50b are shown. Here, the semiconductor layer 51 of transistor 50b has a low-resistance region 51n.

[0434] Detailed explanations of transistors 50a and 50b are omitted as they can be found in the description of transistor 50 in Embodiment 1. The transistors in the memory cell 150 are not limited to the combination of transistors 50a and 50b, and one or more of the transistors exemplified in Embodiment 1 can be used.

[0435] As transistor 50a, a transistor having a conductive layer 60 that functions as a back gate electrode can be applied. Alternatively, a transistor having an upper electrode can be applied as transistor 50a. As transistor 50b, the transistor 50 shown in Figures 5(A) and 5(B) can be applied, similar to transistor 50a. Alternatively, transistor 50A or transistor 50B can be applied as transistor 50b. Furthermore, a planar structure or a GAA structure transistor can be applied to either transistor 50a or transistor 50b.

[0436] In the memory cell 150 shown in Figures 27(A) to 27(C), the conductive layer 110 serves as one of the source and drain electrodes of the transistor 50a. The conductive layer 110, like the conductive layer 55, can have a stacked structure of two or more layers.

[0437] In the memory cell 150 shown in Figures 27(A) to 27(C), the capacitance generated between the conductive layer 55 and the semiconductor layer 51 of the transistor 50a can be used. Therefore, in the memory cell 150 shown in Figures 27(A) to 27(C), data can be stored without forming a separate capacitive element.

[0438] As shown in Figures 27(A) to 27(C), transistor 50b is provided so as to overlap with transistor 50a. Furthermore, the opening 63, which contains part of the structure of transistor 50b, has a region that overlaps with the opening 63, which contains part of the structure of transistor 50a. In particular, since the conductive layer 55 functions as one of the source electrode and drain electrode of transistor 50b and as the gate electrode of transistor 50a, transistors 50b and 50a share part of their structure. With this configuration, transistors 50b and 50a can be provided without significantly increasing the occupied area in a plan view. As a result, the occupied area of ​​the memory cell 150 can be reduced, allowing for a high-density arrangement of the memory cell 150 and increasing the storage capacity of the memory device. In other words, the memory device can be highly integrated.

[0439] In the examples shown in Figures 27(A) to 27(C), the conductive layer 53 extends in the X direction, and the conductive layer 59 extends in the Y direction.

[0440] The insulating layer 62 shown in Figures 27(B) and 27(C) is preferably a laminated structure as shown in Figure 13(A) or Figure 13(B). In particular, the insulating layer 62 having a region located between the conductive layer 55 and the semiconductor layer 51 of the transistor 50b is preferably a laminated structure as described above. This effectively suppresses the diffusion of hydrogen into the semiconductor layer 51 of the transistor 50a, for example.

[0441] The configurations shown in Figures 27(A) to 27(C) function as memory cells. The memory cells will be described in detail in later embodiments.

[0442] The memory cell 150 shown in this embodiment can be used as a memory cell in a storage device. The transistor 50 is an OS transistor. Because the transistor 50 has a small off-current, using it in a storage device makes it possible to retain the stored contents for a long period of time. In other words, refresh operations are not required, or the frequency of refresh operations is extremely low, so the power consumption of the storage device can be significantly reduced. In addition, because the transistor 50 has a high frequency characteristic, reading and writing to the storage device can be performed at high speed.

[0443] A memory cell array can be constructed by arranging the memory cells 150 in a three-dimensional matrix. By stacking layers containing multiple memory cells (also called memory layers), cells can be integrated and arranged without increasing the occupied area of ​​the memory cell array. In other words, a 3D memory cell array can be constructed.

[0444] Figure 28 shows an example of a cross-sectional configuration of a memory device in which a memory layer is stacked on a layer containing a drive circuit including a sense amplifier.

[0445] In Figure 28, a memory cell 150 is provided above the transistor 300. Transistor 300 is one of the transistors in the sense amplifier. For details on the memory cell 150 shown in Figure 28, please refer to the description of the memory cell 150 mentioned above. In Figure 28, an example is shown in which the transistor 50 in the memory cell 150 is the same as the transistor 50 shown in Figures 1(A) to 4(A). Here, the semiconductor layer 51 shown in Figure 28 has a low-resistance region 51n. The transistor 50 shown in Figure 28 also has a conductive layer 58 as the other of the source electrode and drain electrode. The conductive layer 58 has a region located inside the opening 67 of the insulating layer 52, insulating layer 88, and insulating layer 86.

[0446] As shown in Figure 28, by configuring the sense amplifier to overlap with the memory cell 150, the bit line can be shortened. This reduces the bit line capacity and enables high-speed operation of the memory device.

[0447] The memory device shown in Figure 28 can be associated with the semiconductor device 900 described in Embodiment 4. Specifically, transistor 300 corresponds to the transistor in sense amplifier 927 of semiconductor device 900. Also, memory cell 150 corresponds to memory cell 950.

[0448] The transistor 300 is provided on a substrate 311 and includes a conductive layer 316 that functions as a gate, an insulating layer 315 that functions as a gate insulating layer, a semiconductor region 313 that is part of the substrate 311, and low-resistance regions 314a and 314b that function as a source region or drain region. The transistor 300 may be either a p-channel or an n-channel type. The substrate 311 preferably contains a silicon-based semiconductor, and more specifically, it preferably contains single-crystal silicon.

[0449] Furthermore, the substrate 311 can also be a structure in which a single-crystal oxide semiconductor film (typically an indium oxide film) is provided on a stabilized zirconia substrate. The indium oxide film deposited on the stabilized zirconia substrate has a single crystal structure. By using a portion of the indium oxide film as a semiconductor region 313, the field-effect mobility of the transistor 300 can be increased. In addition, the reliability of the transistor 300 can be improved.

[0450] In Figure 28, the transistor 300 has a convex shape in the semiconductor region 313 (part of the substrate 311) where the channel is formed. Furthermore, a conductive layer 316 covers the side and top surfaces of the semiconductor region 313 via an insulating layer 315. The conductive layer 316 may be made of a material that adjusts the work function. Such a transistor 300 is also called a FIN-type transistor because it utilizes the convex portion of the semiconductor substrate. It may also have an insulating layer in contact with the top of the convex portion, functioning as a mask for forming the convex portion. While this example shows the formation of the convex portion by processing a part of the semiconductor substrate, a semiconductor film with a convex shape may also be formed by processing an SOI substrate.

[0451] Between each structure, there may be a wiring layer containing an interlayer insulating layer, wiring, plugs, etc. Furthermore, multiple wiring layers may be provided depending on the design. Here, conductive layers functioning as plugs or wiring may be grouped together and assigned the same reference numeral. Also, in this specification, the wiring and the plug connected to the wiring may be a single integrated unit. That is, there may be cases where a part of the conductive layer functions as wiring, and cases where a part of the conductive layer functions as a plug.

[0452] For example, on the transistor 300, insulating layers 320, 322, 324, and 326 are stacked in order as interlayer insulating layers. In addition, a conductive layer 328 is embedded in insulating layers 320 and 322, and a conductive layer 330 is embedded in insulating layers 324 and 326. Conductive layers 328 and 330 function as plugs or wiring.

[0453] Furthermore, the insulating layer, which functions as an interlayer insulating layer, may also function as a planarizing film that covers the uneven shape beneath it. For example, the upper surface of the insulating layer 322 may be planarized by a planarizing treatment using the CMP method or the like to improve its flatness.

[0454] A wiring layer may be provided on the insulating layer 326 and the conductive layer 330. For example, in Figure 28, insulating layers 350, 352, and 354 are stacked in order. A conductive layer 356 is formed on insulating layers 350, 352, and 354. The conductive layer 356 functions as a plug or wiring.

[0455] The insulating layers 352, 354, etc., which function as interlayer insulating layers, can be the insulating layers used in semiconductor devices or memory devices as described above.

[0456] For conductive layers that function as plugs or wiring, such as conductive layer 328, conductive layer 330, conductive layer 356, etc., conductive materials applicable to conductive layer 58 can be used. It is preferable to use high-melting-point materials such as tungsten or molybdenum that provide both heat resistance and conductivity, and tungsten is preferred. Alternatively, it is preferable to form them with low-resistance conductive materials such as aluminum or copper. Using low-resistance conductive materials can reduce wiring resistance.

[0457] The low-resistance region 51n of transistor 50 is connected to the low-resistance region 314b via conductive layers 58, 59, 386, 385, 384, 383, 382, ​​381, 371, 356, 330, and 328.

[0458] The insulating layer 372 is located on the conductive layer 356 and the insulating layer 354. The memory cell 150 is located on the insulating layer 372. The insulating layer 372 has an opening 391 that reaches the conductive layer 356, and the conductive layer 371 is provided so as to fill the opening 391.

[0459] The conductive layer 381 is located on the conductive layer 371 and the insulating layer 372. The insulating layer 180 is located on the conductive layer 110, the conductive layer 381 and the insulating layer 372. The insulating layer 180 has an opening 392 that reaches the conductive layer 381, and the conductive layer 382 is provided so as to fill the opening 392. The conductive layer 383 is located on the conductive layer 382 and the insulating layer 180. Here, Figure 28 shows an example in which the conductive layer 383 has a two-layer structure consisting of conductive layer 383_1 and conductive layer 383_2 on conductive layer 383_1.

[0460] The insulating layer 62 is located on the conductive layer 55, the conductive layer 383, and the insulating layer 180. The insulating layer 52 is located on the semiconductor layer 51 and the insulating layer 62. The conductive layer 383_2, the insulating layer 62, and the insulating layer 52 have openings 394 that reach the conductive layer 383_1, and the conductive layer 384 is provided so as to fill the openings 394. The conductive layer 385 is located on the conductive layer 384 and the insulating layer 52.

[0461] The insulating layer 88 is located on the conductive layer 53, the conductive layer 385, and the insulating layer 52. The insulating layer 86 is located on the insulating layer 88. The insulating layers 88 and 86 have openings 396 that reach the conductive layer 385, and the conductive layer 386 is provided so as to fill the openings 396. The conductive layer 59 is located on the conductive layer 386, the conductive layer 58, and the insulating layer 86. The conductive layer 59 connects the conductive layer 386 and the conductive layer 58.

[0462] Conductive layer 381 can be formed using the same material and process as conductive layer 110. Conductive layer 383_1 can be formed using the same material and process as conductive layer 55_1. Conductive layer 383_2 can be formed using the same material and process as conductive layer 55_2. Conductive layer 385 can be formed using the same material and process as conductive layer 53. The opening 396 can be formed using the same process as opening 67. Conductive layer 386 can be formed using the same material and process as conductive layer 58.

[0463] By providing openings 394 not only in the insulating layers 62 and 52 but also in the conductive layer 383_2, the conductive layer 384 can come into contact with the conductive layer 383_1. As mentioned above, the conductive layer 383_1 can be made of the same material as the conductive layer 55_1, and the conductive layer 383_2 can be made of the same material as the conductive layer 55_2. Furthermore, the conductivity of the conductive layer 55_1 can be made higher than that of the conductive layer 55_2. As a result, the conductivity of the conductive layer 383_1 can be made higher than that of the conductive layer 383_2. Therefore, the contact resistance between the conductive layer 383 and the conductive layer 384 can be lowered compared to when, for example, the opening 394 is not provided in the conductive layer 383_2. In addition, by providing openings 394 in the conductive layer 383_2, the conductive layer 384 can come into contact with the side surface of the opening 394 in the conductive layer 383_2. This allows for a larger contact area between the conductive layer 383 and the conductive layer 384 compared to when the opening 394 is not provided in the conductive layer 383_2. Therefore, the contact resistance between the conductive layer 383 and the conductive layer 384 can be reduced.

[0464] Figure 29 shows an example in which the memory cell 150 shown in Figure 28 has a transistor 50A instead of transistor 50. Specifically, the memory cell 150 shown in Figure 29 has the transistor 50A shown in Figures 6(A) to 8(B). In the following, we will omit explanations of parts that overlap with the memory device shown in Figure 28 and explain only the differences in detail.

[0465] The memory device shown in Figure 29 has conductive layers 77 on conductive layer 53, insulating layer 88, and insulating layer 86. The memory device shown in Figure 29 does not have conductive layers 58, conductive layer 59, conductive layer 385, and conductive layer 386.

[0466] In the memory device shown in Figure 29, the opening 394 is provided in the conductive layer 383_2 and the insulating layer 62, but not in the insulating layer 52. Furthermore, the conductive layer 384, which is provided to embed the opening 394, is in contact with the lower surface of the semiconductor layer 51, specifically the lower surface of the low-resistance region 51n.

[0467] This embodiment can be combined with other embodiments as appropriate. Furthermore, if multiple configuration examples are shown within a single embodiment in this specification, these configuration examples can be combined as appropriate.

[0468] (Embodiment 4) This embodiment describes a semiconductor device 900 according to one aspect of the present invention. The semiconductor device 900 can function as a memory device.

[0469] Figure 30 shows a block diagram illustrating an example configuration of a semiconductor device 900. The semiconductor device 900 shown in Figure 30 includes a drive circuit 910 and a memory array 920. The memory array 920 has one or more memory cells 950. Figure 30 shows an example in which the memory array 920 has multiple memory cells 950 arranged in a matrix.

[0470] The memory cell 950 can be the same as the memory cell 150 described in Embodiment 3.

[0471] The drive circuit 910 includes a PSW 931 (power switch), a PSW 932, and a peripheral circuit 915. The peripheral circuit 915 includes a peripheral circuit 911, a control circuit 912, and a voltage generation circuit 928.

[0472] In the semiconductor device 900, each circuit, signal, and voltage can be appropriately selected or omitted as needed. Alternatively, other circuits or signals may be added. Signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are external input signals, and signal RDA is an external output signal. Signal CLK is a clock signal.

[0473] Furthermore, signals BW, CE, and GW are control signals. Signal CE is the chip enable signal, signal GW is the global write enable signal, and signal BW is the byte write enable signal. Signal ADDR is the address signal. Signal WDA is the write data, and signal RDA is the read data. Signals PON1 and PON2 are power gating control signals. Signals PON1 and PON2 may be generated by the control circuit 912.

[0474] The control circuit 912 is a logic circuit that has the function of controlling the overall operation of the semiconductor device 900. For example, the control circuit 912 performs logical operations on signals CE, GW, and BW to determine the operating mode of the semiconductor device 900 (e.g., write operation, read operation). Alternatively, the control circuit 912 generates control signals for the peripheral circuit 911 so that this operating mode is executed.

[0475] The voltage generation circuit 928 has the function of generating a negative voltage. The WAKE signal has the function of controlling the input of the CLK signal to the voltage generation circuit 928. For example, when a high-level signal is given as the WAKE signal, the CLK signal is input to the voltage generation circuit 928, and the voltage generation circuit 928 generates a negative voltage.

[0476] The peripheral circuit 911 is a circuit for writing and reading data to and from the memory cell 950. The peripheral circuit 911 includes a row decoder 941, a column decoder 942, a row driver 923, a column driver 924, an input circuit 925, an output circuit 926, and a sense amplifier 927.

[0477] The row decoder 941 and column decoder 942 have the function of decoding the signal ADDR. The row decoder 941 is a circuit for specifying the row to access, and the column decoder 942 is a circuit for specifying the column to access. The row driver 923 has the function of selecting the row specified by the row decoder 941. The column driver 924 has the function of writing data to the memory cell 950, reading data from the memory cell 950, and holding the read data, etc.

[0478] The input circuit 925 has the function of holding the signal WDA. The data held by the input circuit 925 is output to the column driver 924. The output data of the input circuit 925 is the data (Din) to be written to the memory cell 950. The data (Dout) read by the column driver 924 from the memory cell 950 is output to the output circuit 926. The output circuit 926 has the function of holding Dout. In addition, the output circuit 926 has the function of outputting Dout to the outside of the semiconductor device 900. The data output from the output circuit 926 is the signal RDA.

[0479] PSW931 provides V to peripheral circuit 915 DD It has the function of controlling the supply. PSW932 connects to the line driver 923. HM It has a function to control the supply. Here, the high power supply potential of semiconductor device 900 is V DD Therefore, the low power supply potential is GND (ground potential). Also, V HM This is a high power supply potential used to raise the word line to a high level, V DD It is higher than. The on / off state of PSW931 is controlled by signal PON1, and the on / off state of PSW932 is controlled by signal PON2. In Figure 30, in peripheral circuit 915, V DD The number of power domains supplied is set to 1, but it can be multiple. In this case, a power switch can be provided for each power domain.

[0480] Using Figures 31(A) to 31(H), other examples of memory cell configurations applicable to the memory cell 950 will be explained.

[0481] [DOSRAM] Figure 31(A) shows an example of the circuit configuration of a memory cell in a DRAM (Dynamic Random Access Memory). In this specification, a DRAM using an OS transistor is referred to as DOSRAM (Dynamic Oxide Semiconductor Random Access Memory). The memory cell 951 has a transistor M1 and a capacitive element CA.

[0482] Transistor M1 may have a front gate (sometimes simply called a gate) and a back gate. In this case, the back gate may be connected to a wire to which a constant potential or signal is supplied, or the front gate and back gate may be connected.

[0483] The first terminal of transistor M1 is connected to the first terminal of capacitive element CA, the second terminal of transistor M1 is connected to wiring BIL, and the gate of transistor M1 is connected to wiring WOL. The second terminal of capacitive element CA is connected to wiring CAL.

[0484] The wiring BIL functions as a bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitive element CA. When writing and reading data, it is preferable to apply a low-level potential (sometimes called a reference potential) to the wiring CAL.

[0485] Data writing and reading are performed by applying a high-level potential to the WOL wiring, turning on transistor M1, and creating a conductive state (a state in which current can flow) between the BIL wiring and the first terminal of the CA capacitor.

[0486] The memory cell 150 shown in Figures 26(A) to 26(C) is an example of the memory cell 951 shown in Figure 31(A). For example, transistor M1 corresponds to transistor 50, and capacitive element CA corresponds to capacitive element 100. In this case, wiring BIL corresponds to conductive layer 59, wiring WOL corresponds to conductive layer 53, and wiring CAL corresponds to conductive layer 110. Note that transistor 50A, transistor 50B, etc. may be used as transistor M1. The following describes the case where transistor 50 shown in Figures 1(A) to 4(A) is used as transistor M1.

[0487] In Figure 26(A), the wiring BIL (conductive layer 59) and the wiring WOL (conductive layer 53) are arranged intersecting each other. The wiring CAL (conductive layer 110) is arranged parallel to the wiring WOL (conductive layer 53). However, the present invention is not limited to this. For example, the wiring CAL may be arranged parallel to the wiring BIL (conductive layer 59).

[0488] Furthermore, the memory cells that can be used in memory cell 950 are not limited to memory cell 951, and the circuit configuration can be changed. For example, a configuration in which one wiring BIL is provided in common for two or more memory cells may be used. Alternatively, for example, the configuration of memory cell 952 as shown in Figure 31(B) may be used. Memory cell 952 is an example in which there is no capacitive element CA and wiring CAL. The first terminal of transistor M1 is electrically floating.

[0489] In memory cell 952, the potential written via transistor M1 is held in the capacitance (also called parasitic capacitance) between the first terminal and the gate, indicated by the dashed line. This configuration significantly simplifies the structure of the memory cell.

[0490] Furthermore, it is preferable to use an OS transistor as transistor M1. OS transistors have the characteristic of having an extremely low off-current. By using an OS transistor as transistor M1, the leakage current of transistor M1 can be made very small. In other words, the written data can be held by transistor M1 for a long time, so the frequency of memory cell refresh can be reduced. Alternatively, the memory cell refresh operation can be made unnecessary. In addition, because the leakage current is very small, multi-level data or analog data can be held in memory cells 951 and 952.

[0491] [NOSRAM] Figure 31(C) shows an example of a circuit configuration for a gain cell type memory cell with two transistors and one capacitance element. The memory cell 953 has a transistor M2, a transistor M3, and a capacitance element CB. In this specification, a memory device having a gain cell type memory cell using an OS transistor for transistor M2 is called NOSRAM (Nonvolatile Oxide Semiconductor RAM).

[0492] The first terminal of transistor M2 is connected to the first terminal of capacitive element CB, the second terminal of transistor M2 is connected to wiring WBL, and the gate of transistor M2 is connected to wiring WOL. The second terminal of capacitive element CB is connected to wiring CAL. The first terminal of transistor M3 is connected to wiring RBL, the second terminal of transistor M3 is connected to wiring SL, and the gate of transistor M3 is connected to the first terminal of capacitive element CB.

[0493] Wiring WBL functions as the write bit line, wiring RBL functions as the read bit line, and wiring WOL functions as the word line. Wiring CAL functions as wiring for applying a predetermined potential to the second terminal of the capacitive element CB. When writing data, during data retention, and when reading data, it is preferable to apply a low-level potential (sometimes called a reference potential) to wiring CAL.

[0494] Data writing is performed by applying a high-level potential to the WOL wiring, turning on transistor M2, and creating a conductive state between the WBL wiring and the first terminal of the capacitive element CB. Specifically, when transistor M2 is on, a potential corresponding to the information to be recorded is applied to the WBL wiring, and this potential is written to the first terminal of the capacitive element CB and the gate of transistor M3. Subsequently, a low-level potential is applied to the WOL wiring, turning off transistor M2, thereby maintaining the potential of the first terminal of the capacitive element CB and the gate of transistor M3.

[0495] Data is read by applying a predetermined potential to the wiring SL. The current flowing between the source and drain of transistor M3, and the potential of the first terminal of transistor M3, are determined by the potential of the gate and the potential of the second terminal of transistor M3. Therefore, by reading the potential of the wiring RBL connected to the first terminal of transistor M3, the potential held at the first terminal of the capacitive element CB (or the gate of transistor M3) can be read. In other words, the information written to this memory cell can be read from the potential held at the first terminal of the capacitive element CB (or the gate of transistor M3).

[0496] Alternatively, for example, the wiring WBL and wiring RBL may be combined into a single wiring BIL. An example of the circuit configuration of such a memory cell is shown in Figure 31(D). Memory cell 954 is configured such that the wiring WBL and wiring RBL of memory cell 953 are combined into a single wiring BIL, and the second terminal of transistor M2 and the first terminal of transistor M3 are connected to this wiring BIL. In other words, memory cell 954 is configured to operate with the write bit line and the read bit line as a single wiring BIL.

[0497] The memory cell 955 shown in Figure 31(E) is an example where the capacitive element CB and wiring CAL in memory cell 953 are omitted. Similarly, the memory cell 956 shown in Figure 31(F) is an example where the capacitive element CB and wiring CAL in memory cell 954 are omitted. By using such a configuration, the integration density of memory cells can be increased.

[0498] Furthermore, it is preferable to use an OS transistor for at least transistor M2. In particular, it is preferable to use OS transistors for transistors M2 and M3. By using an OS transistor as transistor M2, the written data can be held by transistor M2 for a long time, thus reducing the frequency of memory cell refresh. Alternatively, it may be possible to eliminate the need for memory cell refresh operations. In addition, because the leakage current is very small, multi-level data or analog data can be held in memory cells 953 to 956.

[0499] Memory cells 953 to and 956, which use an OS transistor as transistor M2, represent one form of NOSRAM.

[0500] Furthermore, a Si transistor may be used as transistor M3. Si transistors can increase field-effect mobility and can also be made into p-channel transistors, thus increasing the flexibility of circuit design.

[0501] The memory cell 150 shown in Figures 27(A) to 27(C) is an example of the memory cell 955 shown in Figure 31(E). For example, transistor M2 corresponds to transistor 50b, and transistor M3 corresponds to transistor 50a. Also, wiring WBL corresponds to the conductive layer 59 of transistor 50b, and wiring WOL corresponds to the conductive layer 53.

[0502] In Figure 27(A), the wiring WBL (conductive layer 59) and the wiring WOL (conductive layer 53) are arranged to intersect each other.

[0503] Figure 31(G) also shows a gain cell type memory cell 957 with three transistors and one capacitance element. The memory cell 957 has transistors M4 to M6 and a capacitance element CC.

[0504] The first terminal of transistor M4 is connected to the first terminal of capacitive element CC, the second terminal of transistor M4 is connected to wiring BIL, and the gate of transistor M4 is connected to wiring WOL. The second terminal of capacitive element CC is connected to the first terminal of transistor M5 and to wiring GNDL. The second terminal of transistor M5 is connected to the first terminal of transistor M6, and the gate of transistor M5 is connected to the first terminal of capacitive element CC. The second terminal of transistor M6 is connected to wiring BIL, and the gate of transistor M6 is connected to wiring RWL.

[0505] The BIL wire functions as a bit line, the WOL wire functions as a write word line, and the RWL wire functions as a read word line. The GNDL wire provides a low level potential.

[0506] Data writing is performed by applying a high-level potential to the WOL wiring, turning on transistor M4, and creating a conductive state between the BIL wiring and the first terminal of the CC capacitor. Specifically, when transistor M4 is ON, a potential corresponding to the information to be recorded in the BIL wiring is applied, and this potential is written to the first terminal of the CC capacitor and the gate of transistor M5. Subsequently, a low-level potential is applied to the WOL wiring, turning off transistor M4, thereby maintaining the potential of the first terminal of the CC capacitor and the gate of transistor M5.

[0507] Data is read by precharging the wiring BIL to a predetermined potential, then electrically freezing the wiring BIL, and applying a high-level potential to the wiring RWL. As the wiring RWL reaches a high-level potential, transistor M6 turns ON, and the wiring BIL and the second terminal of transistor M5 become conductive. At this time, the potential of the wiring BIL is applied to the second terminal of transistor M5, but the potential of the second terminal of transistor M5 and the potential of the wiring BIL change depending on the potential held at the first terminal of the capacitive element CC (or the gate of transistor M5). By reading the potential of the wiring BIL, the potential held at the first terminal of the capacitive element CC (or the gate of transistor M5) can be read. In other words, the information written to this memory cell can be read from the potential held at the first terminal of the capacitive element CC (or the gate of transistor M5).

[0508] Furthermore, it is preferable to use an OS transistor for at least transistor M4.

[0509] Note that Si transistors may be used as transistors M5 and M6. As mentioned above, Si transistors may have higher field-effect mobility than OS transistors depending on the crystal state of the silicon used in the semiconductor layer.

[0510] [OS-SRAM] Figure 31(H) shows an example of SRAM (Static Random Access Memory) using an OS transistor. In this specification, SRAM using an OS transistor is referred to as OS-SRAM (Oxide Semiconductor-SRAM). The memory cell 958 shown in Figure 31(H) is a memory cell of a backup-capable SRAM.

[0511] The memory cell 958 includes transistors M7 to M10, transistors MS1 to MS4, and capacitive elements CD1 and CD2. Transistors MS1 and MS2 are p-channel transistors, while transistors MS3 and MS4 are n-channel transistors.

[0512] The first terminal of transistor M7 is connected to wiring BIL, and the second terminal of transistor M7 is connected to the first terminal of transistor MS1, the first terminal of transistor MS3, the gate of transistor MS2, the gate of transistor MS4, and the first terminal of transistor M10. The gate of transistor M7 is connected to wiring WOL. The first terminal of transistor M8 is connected to wiring BILB, and the second terminal of transistor M8 is connected to the first terminal of transistor MS2, the first terminal of transistor MS4, the gate of transistor MS1, the gate of transistor MS3, and the first terminal of transistor M9. The gate of transistor M8 is connected to wiring WOL.

[0513] The second terminal of transistor MS1 is connected to wiring VDL. The second terminal of transistor MS2 is connected to wiring VDL. The second terminal of transistor MS3 is connected to wiring GNDL. The second terminal of transistor MS4 is connected to wiring GNDL.

[0514] The second terminal of transistor M9 is connected to the first terminal of capacitive element CD1, and the gate of transistor M9 is connected to wiring BRL. The second terminal of transistor M10 is connected to the first terminal of capacitive element CD2, and the gate of transistor M10 is connected to wiring BRL.

[0515] The second terminal of capacitive element CD1 is connected to wiring GNDL, and the second terminal of capacitive element CD2 is connected to wiring GNDL.

[0516] Wiring BIL and BILB function as bit lines, wiring WOL functions as a word line, and wiring BRL controls the on and off states of transistors M9 and M10.

[0517] Wiring VDL is a wire that provides a high potential, and wiring GNDL is a wire that provides a low potential.

[0518] Data is written by applying a high-level potential to the WOL wiring and also to the BRL wiring. Specifically, when transistor M10 is ON, a potential corresponding to the information to be recorded in the BIL wiring is applied, and this potential is written to the second terminal side of transistor M10.

[0519] Incidentally, since the memory cell 958 is configured as an inverter loop by transistors MS1 to MS2, an inverted signal of the data signal corresponding to the potential is input to the second terminal side of transistor M8. Because transistor M8 is ON, the inverted signal of the potential applied to wiring BIL, i.e., the signal input to wiring BIL, is output to wiring BILB. Also, because transistors M9 and M10 are ON, the potential of the second terminal of transistor M7 and the potential of the second terminal of transistor M8 are held at the first terminal of capacitive element CD2 and the first terminal of capacitive element CD1, respectively. Subsequently, by applying a low-level potential to wiring WOL and wiring BRL, and turning off transistors M7 to M10, the potentials of the first terminal of capacitive element CD1 and the first terminal of capacitive element CD2 are held.

[0520] Data is read by first precharging wiring BIL and wiring BILB to a predetermined potential, then applying a high-level potential to wiring WOL and wiring BRL. This refreshes the potential of the first terminal of capacitive element CD1 via the inverter loop of memory cell 958 and outputs it to wiring BILB. Similarly, the potential of the first terminal of capacitive element CD2 is also refreshed via the inverter loop of memory cell 958 and outputs it to wiring BIL. Since wiring BIL and wiring BILB change from their precharged potentials to the potentials of the first terminals of capacitive element CD2 and CD1, respectively, the potential held in the memory cells can be read from the potential of wiring BIL or wiring BILB.

[0521] Furthermore, it is preferable to use OS transistors as transistors M7 to M10. This allows the written data to be retained for a long time by transistors M7 to M10, thereby reducing the frequency of memory cell refreshes, or even eliminating the need for memory cell refresh operations altogether.

[0522] Note that Si transistors may be used as transistors MS1 through MS4.

[0523] The drive circuit 910 and memory array 920 of the semiconductor device 900 may be provided on the same plane. Alternatively, as shown in Figure 32(A), the drive circuit 910 and memory array 920 may be stacked on top of each other. Stacking the drive circuit 910 and memory array 920 shortens the signal propagation distance. Furthermore, as shown in Figure 32(B), multiple memory arrays 920 may be stacked on top of the drive circuit 910.

[0524] Next, an example of a processing unit that can be equipped with the above-mentioned memory device and other semiconductor devices will be described.

[0525] Figure 33 shows a block diagram of the arithmetic unit 960. The arithmetic unit 960 shown in Figure 33 can be applied to a CPU, for example. The arithmetic unit 960 can also be applied to processors such as GPUs (Graphics Processing Units), TPUs (Tensor Processing Units), and NPUs (Neural Processing Units) that have a large number of processor cores (tens to hundreds) capable of parallel processing, more so than a CPU.

[0526] The arithmetic unit 960 shown in Figure 33 has an ALU 962 (ALU: Arithmetic logic unit, arithmetic circuit), an ALU controller 962c, an instruction decoder 963, an interrupt controller 964, a timing controller 965, a register 966, a register controller 967, a bus interface 968, a cache 969, and a cache interface 969i on a substrate 961. The substrate 961 can be a semiconductor substrate, an SOI substrate, a glass substrate, etc. It may also have a rewritable ROM and a ROM interface. In addition, the cache 969 and the cache interface 969i may be provided on a separate chip.

[0527] The cache 969 is connected to the main memory located on a separate chip via a cache interface 969i. The cache interface 969i has the function of supplying a portion of the data held in the main memory to the cache 969. The cache interface 969i also has the function of outputting a portion of the data held in the cache 969 to the ALU 962 or register 966, etc., via the bus interface 968.

[0528] As will be described later, a memory array 920 can be stacked on the arithmetic unit 960. The memory array 920 can be used as a cache. In this case, the cache interface 969i may have the function of supplying data held in the memory array 920 to the cache 969. In this case, it is preferable that a drive circuit 910 is included in part of the cache interface 969i.

[0529] Alternatively, the cache 969 can be omitted, and only the memory array 920 can be used as the cache.

[0530] The arithmetic unit 960 shown in Figure 33 is merely one example of a simplified configuration, and actual arithmetic units 960 have a wide variety of configurations depending on their application. For example, it is preferable to have a so-called multi-core configuration in which the configuration including the arithmetic unit 960 shown in Figure 33 is considered one core, and multiple such cores are included, with each core operating in parallel. The more cores there are, the higher the computational performance can be. While a larger number of cores is preferable, it is preferable to have, for example, 2, preferably 4, more preferably 8, even more preferably 12, even more preferably 16 or more cores. Furthermore, in cases where very high computational performance is required, such as for server applications, it is preferable to have a multi-core configuration with 16 or more, preferably 32 or more, and even more preferably 64 or more cores. In addition, the number of bits that the arithmetic unit 960 can handle in its internal arithmetic circuitry, data bus, etc., can be, for example, 8 bits, 16 bits, 32 bits, 64 bits, etc.

[0531] Instructions input to the arithmetic unit 960 via the bus interface 968 are input to the instruction decoder 963, decoded, and then input to the ALU controller 962c, interrupt controller 964, register controller 967, and timing controller 965.

[0532] The ALU controller 962c, interrupt controller 964, register controller 967, and timing controller 965 perform various controls based on the decoded instructions. Specifically, the ALU controller 962c generates signals to control the operation of the ALU 962. The interrupt controller 964 processes interrupt requests from external input / output devices, peripheral circuits, etc., during program execution of the arithmetic unit 960, judging their priority, mask state, etc. The register controller 967 generates the address of register 966 and reads and writes to register 966 according to the state of the arithmetic unit 960.

[0533] Furthermore, the timing controller 965 generates signals that control the timing of the operation of the ALU 962, ALU controller 962c, instruction decoder 963, interrupt controller 964, and register controller 967. For example, the timing controller 965 includes an internal clock generation unit that generates an internal clock signal based on a reference clock signal, and supplies the internal clock signal to the various circuits mentioned above.

[0534] In the arithmetic unit 960 shown in Figure 33, the register controller 967 selects a data retention operation in register 966 according to instructions from ALU 962. That is, it selects whether to retain data in the memory cell of register 966 using a flip-flop or a capacitive element. If data retention using a flip-flop is selected, power potential is supplied to the memory cell in register 966. If data retention using a capacitive element is selected, data is rewritten to the capacitive element, and the supply of power potential to the memory cell in register 966 can be stopped.

[0535] The memory array 920 and the arithmetic unit 960 can be mounted on top of each other. Figures 34(A) and 34(B) show perspective views of the semiconductor device 970A. The semiconductor device 970A has a layer 930 on which memory arrays are provided on the arithmetic unit 960. The layer 930 is provided with memory arrays 920L1, 920L2, and 920L3. The arithmetic unit 960 and each memory array have overlapping regions. To make the configuration of the semiconductor device 970A easier to understand, Figure 34(B) shows the arithmetic unit 960 and layer 930 separately.

[0536] By stacking the layer 930 containing the memory array and the arithmetic unit 960, the connection distance between them can be shortened. Therefore, the communication speed between them can be increased. In addition, power consumption can be reduced due to the short connection distance.

[0537] As a method for stacking the layer 930 having the memory array and the arithmetic unit 960, one may use a method in which the layer 930 having the memory array is directly stacked on the arithmetic unit 960 (also called monolithic stacking), or one may use a method in which the arithmetic unit 960 and the layer 930 are formed on separate substrates, the two substrates are bonded together, and they are connected using through-via or conductive film bonding technology (such as Cu-Cu bonding). The former does not require consideration of positional misalignment during bonding, so not only can the chip size be reduced, but manufacturing costs can also be reduced.

[0538] Here, the arithmetic unit 960 does not have a cache 969, and the memory arrays 920L1, 920L2, and 920L3 provided in layer 930 can each be used as caches. In this case, for example, memory array 920L1 can be used as an L1 cache (also called a level 1 cache), memory array 920L2 can be used as an L2 cache (also called a level 2 cache), and memory array 920L3 can be used as an L3 cache (also called a level 3 cache). Of the three memory arrays, memory array 920L3 has the largest capacity and the lowest access frequency. Also, memory array 920L1 has the smallest capacity and the highest access frequency.

[0539] Furthermore, when the cache 969 provided in the arithmetic unit 960 is used as the L1 cache, each memory array provided in layer 930 can be used as a lower-level cache or main memory, respectively. Main memory has a larger capacity than cache and is accessed less frequently.

[0540] Furthermore, as shown in Figure 34(B), drive circuits 910L1, 910L2, and 910L3 are provided. Drive circuit 910L1 is connected to memory array 920L1 via connection electrode 940L1. Similarly, drive circuit 910L2 is connected to memory array 920L2 via connection electrode 940L2, and drive circuit 910L3 is connected to memory array 920L3 via connection electrode 940L3.

[0541] Note that while this example shows three memory arrays functioning as a cache, it may also use one, two, or four or more arrays.

[0542] When the memory array 920L1 is used as a cache, the drive circuit 910L1 may function as part of the cache interface 969i, or the drive circuit 910L1 may be configured to be connected to the cache interface 969i. Similarly, the drive circuits 910L2 and 910L3 may also function as part of the cache interface 969i, or be configured to be connected to it.

[0543] Whether the memory array 920 functions as a cache or as main memory is determined by the control circuit 912 of each drive circuit 910. Based on signals supplied from the arithmetic unit 960, the control circuit 912 can make some of the multiple memory cells 950 of the semiconductor device 900 function as RAM.

[0544] The semiconductor device 900 can have some of its multiple memory cells 950 function as a cache and the other part function as main memory. In other words, the semiconductor device 900 can have both cache and main memory functions. A semiconductor device 900 according to one aspect of the present invention can function as a universal memory, for example.

[0545] Alternatively, a layer 930 having a single memory array 920 may be superimposed on the arithmetic unit 960. Figure 35(A) shows a perspective view of the semiconductor device 970B.

[0546] In the semiconductor device 970B, a single memory array 920 can be divided into multiple areas, each used for a different function. Figure 35(A) shows an example where area L1 is used as the L1 cache, area L2 as the L2 cache, and area L3 as the L3 cache.

[0547] Furthermore, the semiconductor device 970B allows the capacity of each region L1 through L3 to be changed according to the situation. For example, if the capacity of the L1 cache is to be increased, this can be achieved by increasing the area of ​​region L1. This configuration makes arithmetic processing more efficient and improves processing speed.

[0548] Furthermore, multiple memory arrays may be stacked. Figure 35(B) shows a perspective view of the semiconductor device 970C.

[0549] The semiconductor device 970C has a stacked structure consisting of a layer 930L1 with a memory array 920L1, a layer 930L2 with a memory array 920L2 on top of it, and a layer 930L3 with a memory array 920L3 on top of that. The memory array 920L1, which is physically closest to the arithmetic unit 960, can be used as the upper cache, and the memory array 920L3, which is furthest away, can be used as the lower cache or main memory. By using this configuration, the capacity of each memory array can be increased, thereby improving processing power.

[0550] This embodiment can be combined with other ...

Claims

1. It comprises a first conductive layer, a second conductive layer, a first insulating layer, a second insulating layer, and a semiconductor layer. The first insulating layer has a region located on the first conductive layer, The first insulating layer has a first opening that overlaps with the first conductive layer, The semiconductor layer has a first region located inside the first opening and a second region in contact with the upper surface of the first insulating layer. The semiconductor layer has a region in contact with the first conductive layer, The second insulating layer has a region in contact with the side surface of the first region of the semiconductor layer and a region in contact with the upper surface of the second region of the semiconductor layer. The second conductive layer is provided on the second insulating layer such that it has a region located inside the first opening. The concentration of the first element in at least a portion of the second region is higher than the concentration of the first element in the first region. The semiconductor layer has indium oxide, A semiconductor device in which the first element is one or more of boron, phosphorus, titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, and silicon.

2. In claim 1, Having a third insulating layer, The third insulating layer has a third region along the side surface of the second conductive layer and a fourth region along the upper surface of the second insulating layer. A semiconductor device wherein, in the semiconductor layer, the concentration of the first element in the region overlapping with the third region is lower than the concentration of the first element in the region overlapping with the fourth region.

3. In claim 1, It has a third conductive layer, a fourth conductive layer, and a fifth conductive layer. The semiconductor layer has a third region located on the first insulating layer, The third region is provided in a position opposite to the second region, with the second conductive layer in between. The third conductive layer has a region that is in contact with the upper surface of the second region of the semiconductor layer, The fourth conductive layer has a region in contact with the upper surface of the third region of the semiconductor layer, A semiconductor device wherein the fifth conductive layer has a region in contact with the third conductive layer and a region in contact with the fourth conductive layer.

4. In claim 3, Having a third insulating layer, The third insulating layer is located on the second conductive layer and the second insulating layer, The second insulating layer and the third insulating layer each have a second opening that overlaps with the second region and a third opening that overlaps with the third region, The third conductive layer has a region located inside the second opening, The fourth conductive layer has a region located inside the third opening, A semiconductor device wherein the fifth conductive layer has a region located on the third conductive layer, a region located on the fourth conductive layer, and a region located on the third insulating layer.

5. In claim 1, The semiconductor device comprises a semiconductor layer having a region extending in a first direction.

6. In claim 5, It has a third insulating layer and a third conductive layer, The third insulating layer is provided so as to surround the side surface of the second conductive layer located outside the first opening in a plan view. The third conductive layer has a region in contact with the upper surface of the second conductive layer and a region located on the third insulating layer. The semiconductor device wherein the third conductive layer has a region extending in the second direction.

7. In claim 1, The second region has a concentration of the first element of 1 × 10⁻⁶ １８ atoms / cm ３ A semiconductor device having a region greater than or equal to the above.

8. In claim 7, The first region has a concentration of the first element of 1 × 10⁻⁶ １８ atoms / cm ３ A semiconductor device having a region that is less than [a certain value].

9. In any one of claims 1, 3, 5, 7, and 8, Having a third insulating layer, The third insulating layer has a region located inside the first opening, The semiconductor device has a semiconductor layer comprising a region located on the third insulating layer and a region inside the first opening that is in contact with the side surface of the third insulating layer.

10. In claim 9, The semiconductor device comprises a third insulating layer containing gallium and oxygen.

11. In any one of claims 2, 4, and 6, It has a fourth insulating layer, The fourth insulating layer has a region located inside the first opening, The semiconductor device has a semiconductor layer comprising a region located on the fourth insulating layer and a region inside the first opening that is in contact with the side surface of the fourth insulating layer.

12. In claim 11, The semiconductor device comprises a fourth insulating layer containing gallium and oxygen.

13. Having steps 1 through 7, In the first step described above, a first conductive layer is formed, In the second step described above, a first insulating layer is formed so as to cover the first conductive layer. In the third step, a first opening is formed in the first insulating layer that reaches the first conductive layer. In the fourth step, a semiconductor layer having indium oxide is formed such that it has a region in contact with the upper surface of the first conductive layer and a region located on the first insulating layer. In the fifth step described above, a second insulating layer is formed such that it has a region in contact with the upper surface and a region in contact with the side surface of the semiconductor layer. In the sixth step, a second conductive layer is formed on the second insulating layer such that it has a region located inside the first opening. A method for manufacturing a semiconductor device, wherein in the seventh step, one or more of the following elements are supplied as the first element to a region of the semiconductor layer that does not overlap with the second conductive layer: boron, phosphorus, titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, and silicon.

14. In claim 13, It has an eighth step, In the eighth step, after the sixth step, a third insulating layer is formed along the upper surface of the second conductive layer, the side surface of the second conductive layer, and the upper surface of the second insulating layer. The seventh step is performed after the eighth step. A method for manufacturing a semiconductor device, wherein in the seventh step, the supply of the first element to the semiconductor layer is performed using ion implantation, ion doping, or plasma immersion ion implantation.

15. In claim 13, It has eight to eleven steps, In the eighth step described above, a third insulating layer is formed on the second conductive layer and the second insulating layer. In the ninth step, a second opening and a third opening reaching the semiconductor layer are formed in the third insulating layer and the second insulating layer, facing each other with the second conductive layer in between. In the tenth step, the third conductive layer located inside the second opening and the fourth conductive layer located inside the third opening are formed such that they have a region in contact with the semiconductor layer. A method for manufacturing a semiconductor device, comprising forming a fifth conductive layer in the eleventh step, such that it has a region in contact with the third conductive layer, a region in contact with the fourth conductive layer, and a region located on the third insulating layer.

16. Having steps 1 through 10, In the first step described above, a first conductive layer is formed, In the second step described above, a first insulating layer is formed so as to cover the first conductive layer. In the third step, an opening is formed in the first insulating layer that reaches the first conductive layer. In the fourth step, a semiconductor layer having indium oxide is formed such that it has a region in contact with the upper surface of the first conductive layer and a region located on the first insulating layer. In the fifth step described above, a second insulating layer is formed such that it has a region in contact with the upper surface and a region in contact with the side surface of the semiconductor layer. In the sixth step described above, a sacrificial layer is formed on the semiconductor layer such that it has a region located inside the opening. In the seventh step, one or more of the following elements are supplied as the first element to a region of the semiconductor layer that does not overlap with the sacrificial layer: boron, phosphorus, titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, and silicon. In the eighth step described above, the sacrificial layer is removed, In the ninth step described above, a second conductive layer is formed on the second insulating layer such that it has a region located inside the opening. A method for manufacturing a semiconductor device, comprising forming a third conductive layer in the tenth step such that it has a region in contact with the upper surface of the second conductive layer.

17. In claim 16, The process comprises an eleventh step and a twelfth step, In the 11th step, after the 6th step, a third insulating layer is formed so as to cover the upper surface of the sacrificial layer and the side surface located outside the opening. The seventh step is performed after the eleventh step. In the seventh step, the supply of the first element to the semiconductor layer is performed using ion implantation, ion doping, or plasma immersion ion implantation. In the 12th step, after the 7th step, the upper surface of the sacrificial layer is exposed by removing a portion of the third insulating layer. The eighth step is a method for manufacturing a semiconductor device, performed after the twelfth step.

18. In claim 16 or claim 17, In the fourth step described above, the semiconductor layer is formed such that it has a region extending in the first direction. A method for manufacturing a semiconductor device, comprising forming the third conductive layer in the tenth step such that it has a region extending in the second direction.

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