Semiconductor device using a wiring board and method for manufacturing the same semiconductor device.

Abstract

To suppress the yield reduction associated with heat treatment when manufacturing semiconductor devices using the underfill method, and to provide highly reliable semiconductor devices that are less prone to damage. [Solution] The semiconductor element and the wiring board are essential components. The wiring board has a first electrode bump on its first main surface side, which consists of a plurality of bump electrodes to which electrical wiring is at least electrically connected. The semiconductor element has a second electrode bump on its first main surface side, which consists of a plurality of bump electrodes to which the electronic circuit of the semiconductor element is connected. The semiconductor element and the wiring board are arranged with their first main surfaces facing each other, and the plurality of first electrode bumps and the plurality of second electrode bumps are mechanically and electrically joined. A gap is formed between the first main surface of the wiring board and the first main surface of the semiconductor element, and the maximum gap between the first main surface of the wiring board and the first main surface of the semiconductor element is 10 nm or more and 50 μm or less.

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device using a wiring board and a method for manufacturing the same semiconductor device. [Background technology]

[0002] The process of manufacturing functional structures by joining multiple semiconductor elements with electrode bumps is becoming increasingly important. Mid-infrared cameras are realized by joining a detector made of III-V semiconductor material such as GaAs and a readout circuit made of Si with indium bumps. In printed circuit boards, solder bumps are commonly used to mount semiconductor circuits onto the circuit board. While miniaturization and high integration are progressing, recently, the development of systems that assume the joining of multiple semiconductor elements, such as chiplets and micro-LED displays, is advancing.

[0003] One widely used implementation method is called underfilling, which involves filling the joint with a thermosetting resin such as epoxy resin to protect it. This protects the joint from contaminants and chemicals during the manufacturing process, and is also expected to prevent deterioration of the joint over time after manufacturing.

[0004] Here, thermosetting resins have a coefficient of thermal expansion that is more than an order of magnitude higher than that of semiconductor materials. Therefore, in conventional underfill methods, the reliability of the underfill deteriorates due to the filling process. In particular, mid-infrared cameras are exposed to temperatures exceeding 100°C during the manufacturing process, but need to be cooled to around -200°C during use. Thermal expansion and contraction of the underfill material causes stress on the photodetector element, leading to variations in sensitivity characteristics for each pixel, as well as problems such as cracks in the detector, defective pixels due to injection failures, and non-uniformity. [Prior art documents] [Patent Documents]

[0005] [Patent Document 1] Japanese Patent Publication No. 2009-194010 [Non-patent literature]

[0006] [Non-Patent Document 1] Haruyoshi Katayama, Development of a Type II Superlattice Infrared Detector for Satellite Mounting, Applied Physics, Vol. 92, No. 12, pp. 723-729 (2023). [Non-Patent Document 2] Printing revolutionizes semiconductor back-end processes: 10μm pitch bumps also developed, NIKKWEI ELECTRONICS, October 2015 issue, pp. 26-27 (2015). [Overview of the Initiative] [Problems that the invention aims to solve]

[0007] The object of this invention is to solve the problem of reduced reliability due to thermal expansion of the underfill material, as described in the background section. Specifically, the objective is to provide a semiconductor device using a wiring board and a method for manufacturing such a semiconductor device that suppresses the decrease in yield due to heat treatment during manufacturing and solves the problem of the underfill material expanding or contracting due to temperature changes during use or the temperature difference between the manufacturing environment and the usage environment, thereby applying mechanical stress to the element and sometimes leading to damage. [Means for solving the problem]

[0008] The configuration of the present invention for solving the problem is shown below. (Composition 1) A semiconductor device having semiconductor elements and wiring substrates as essential components. The wiring board has a first electrode bump on the first main surface side of the wiring board, which consists of a plurality of bump electrodes to which electrical wiring is at least electrically connected. The semiconductor element has a second electrode bump consisting of a plurality of bump electrodes to which the electronic circuit of the semiconductor element is connected, on the first main surface side of the semiconductor element. The semiconductor element is arranged with respect to the wiring substrate, with their first main surfaces facing each other, and the plurality of first electrode bumps and the plurality of second electrode bumps are mechanically and electrically joined. A void is formed between the first main surface of the wiring substrate and the first main surface of the semiconductor element. A semiconductor device using a wiring substrate, wherein the maximum gap between the first main surface of the wiring substrate and the first main surface of the semiconductor element is 10 nm or more and 50 μm or less. (Configuration 2) The semiconductor device according to configuration 1, wherein the surface side of the semiconductor device is the second main surface side of the semiconductor element. (Composition 3) The semiconductor device according to configuration 1 or 2, wherein the bonding between the first electrode bump and the plurality of second electrode bumps is a solid-phase diffusion bonding. (Composition 4) The semiconductor device according to configuration 1, wherein the average thickness of the semiconductor element is 10 nm or more and 100 μm or less. (Composition 5) The semiconductor device according to configuration 1, wherein the maximum gap between the first main surface of the wiring substrate and the first main surface of the semiconductor element is 10 nm or more and 10 μm or less. (Composition 6) The semiconductor device according to configuration 1, wherein the semiconductor element is a light-receiving or light-emitting element. (Composition 7) The semiconductor device according to configuration 1, wherein the semiconductor element is an infrared light receiving element. (Composition 8) The semiconductor device described in Configuration 1 has an operating temperature of 4K or more and 400K or less. (Composition 9 places) The semiconductor device according to configuration 1, wherein a sealing material is arranged around the outer periphery of the semiconductor element to block outside air and reinforce mechanical strength. (Composition 10) The semiconductor device according to configuration 9, wherein the sealing material is made of epoxy resin. (Composition 11) The semiconductor device according to any one of Configurations 1 to 10, wherein the gap is formed in a region including at least a joint portion between the first bump and the second bump. (Configuration 12) A method of manufacturing a semiconductor device including a semiconductor element and a wiring substrate as essential components, preparing a first electrode bump including a plurality of bump electrodes at least electrically connected to an electrical wiring of the wiring substrate on a first main surface side, and preparing a wiring substrate having at least self-supporting rigidity; preparing a semiconductor element formed on a first main surface side of a self-supporting substrate, the semiconductor element having a plurality of bump electrodes to which at least a part of an electronic circuit of the semiconductor element is connected; opposing the first main surface side of the wiring substrate and the first main surface side of the semiconductor element, and mechanically contacting at least a part of the first electrode bump and the second electrode bump to form a joint by the first electrode bump and the second electrode bump; filling a gap formed between the first main surface of the wiring substrate and the first main surface of the semiconductor element with a filler made of a thermoplastic polymer whose viscosity changes with temperature and can be removed by a solvent; processing the second main surface side of the semiconductor element to a predetermined depth by etching, polishing, or both etching and polishing to thin the semiconductor element; forming a predetermined circuit on the second main surface side of the semiconductor element; A method of manufacturing a semiconductor device using a wiring substrate, wherein the filler is eluted from a sample in which a semiconductor element thinned on the wiring substrate is bump-bonded by heat treatment or using a solvent. (Configuration 13) The method of manufacturing a semiconductor device according to Configuration 12, wherein the filler is wax. (Configuration 14) The method of manufacturing a semiconductor device according to Configuration 12, wherein a maximum gap between the first main surface of the wiring substrate and the first main surface of the semiconductor element is 10 nm or more and 50 μm or less. (Configuration 15) The method for manufacturing a semiconductor device according to configuration 12, wherein the average thickness of the semiconductor element is 10 nm or more and 100 μm or less. (Composition 16) The method for manufacturing a semiconductor device according to configuration 12, wherein the semiconductor element is an infrared light receiving element. (Composition 17) The method for manufacturing a semiconductor device according to configuration 16, wherein the semiconductor element is an infrared light receiving element having a metamaterial structure, and the predetermined circuit has light receiving wiring and an antenna arranged therein. (Composition 18) A method for manufacturing a semiconductor device according to configuration 12, wherein a sealing material that blocks outside air is applied to the outer periphery of the semiconductor element to seal and protect the first electrode bump and the second electrode bump from outside air and to reinforce the mechanical strength of the semiconductor device. (Composition 19) The method for manufacturing a semiconductor device according to configuration 18, wherein the sealing material is made of epoxy resin. [Effects of the Invention]

[0009] According to the present invention, the problem of reduced reliability due to thermal expansion of the underfill material is solved. More specifically, the invention provides a semiconductor device using a wiring board and a method for manufacturing the semiconductor device, which suppresses the decrease in yield associated with heat treatment during manufacturing and solves the problem of mechanical stress being applied to the element due to expansion or contraction of the underfill material due to temperature changes during use or the temperature difference between the manufacturing and usage environments, sometimes leading to damage.

[0010] In particular, with mid-infrared cameras, despite the low operating temperature of -200°C, the large difference in processing temperature between the operating environment and the manufacturing process (180°C) results in a high defect rate with conventional methods, and problems with aging and reliability during use are also likely to occur. The present invention reduces variations in the sensitivity characteristics of each pixel of the photodetector due to residual stress, facilitating image calibration, and also solves problems such as defective pixels due to detector cracking or injection failure, non-uniformity, and aging degradation. [Brief explanation of the drawing]

[0011] [Figure 1] This is a cross-sectional structural diagram illustrating the configuration of a semiconductor device using a wiring board according to the first embodiment. [Figure 2] This is a flowchart illustrating the manufacturing process. [Figure 3] This is a manufacturing process diagram illustrating the manufacturing process of a semiconductor device using a wiring board according to the first embodiment, using a cross-sectional view. [Figure 4] This is a manufacturing process diagram illustrating the manufacturing process of a semiconductor device using a wiring board according to the first embodiment, using a cross-sectional view. [Figure 5] This is a manufacturing process diagram illustrating the manufacturing process of a semiconductor device using a conventional wiring board, with cross-sectional views. [Figure 6] This is a manufacturing process diagram illustrating the manufacturing process of a semiconductor device using a conventional wiring board, with cross-sectional views. [Figure 7] This is a cross-sectional view illustrating the structure of a semiconductor device using a wiring board in a second embodiment. [Figure 8] This is a manufacturing process diagram illustrating the manufacturing process of a semiconductor device using a wiring board, in which a protective seal according to the second embodiment is placed, using plan views and cross-sectional views. [Figure 9] This is a cross-sectional view illustrating the structure of an infrared imaging semiconductor device using a wiring board in a third embodiment. [Figure 10] This is a cross-sectional view illustrating the pixel and electrode bump processing steps for a semiconductor device in Example 1. [Figure 11] This is a band structure diagram illustrating the conduction band energy structure and subbands in Example 1. [Figure 12] This is a cross-sectional view illustrating the electrode bump processing process of the wiring board in Example 1. [Figure 13] This is a cross-sectional view illustrating the semiconductor element and wiring substrate bonding process in Example 1. [Figure 14] This is a characteristic diagram showing the voltage-current density measurement results of the infrared sensor fabricated in Example 1 under dark and background light conditions. [Figure 15] This is a characteristic diagram showing the relationship between the sensitivity spectrum of the infrared sensor fabricated in Example 1 and the absorption spectrum of H2O gas. [Figure 16] This is an example of an image taken with an infrared camera in Example 1. [Figure 17] This is an example of an image taken with an infrared camera in Example 1. [Modes for carrying out the invention]

[0012] The embodiments for carrying out the present invention will be described below with reference to the drawings. Note that A to B in the text refers to A and B, meaning A or greater and B or less.

[0013] (Embodiment 1) Embodiment 1 describes the basic semiconductor device configuration of the present invention and its manufacturing method.

[0014] <Overview and Structure> As shown in Figure 1, the present invention provides a method for manufacturing a semiconductor device, which involves a process of manufacturing a highly functional semiconductor device 1001 by joining one or more semiconductor elements 22 (not shown) equipped with electronic circuits to a wiring substrate 11 using electrode bumps 12 and 23. The method includes a step of filling the joint with a thermoplastic polymer material instead of the thermosetting resin that was conventionally used to protect the joint from contaminants, chemicals, and gases during the manufacturing process, and removing the thermoplastic polymer material after the processing step. Furthermore, the semiconductor device 1001 of the present invention is a semiconductor device 1001 in which one or more semiconductor elements 22 equipped with an electronic circuit (not shown) are joined to a wiring substrate 11 by electrode bumps 12 and 23, characterized in that at least the vicinity of the electrode bumps 12 and 23 is an air gap 43, and the electrode bumps are joined with the first main surface 19 of the wiring substrate 11 and the first main surface 29 of the semiconductor element 22 facing each other.

[0015] According to this manufacturing method, the sample is protected by a thermoplastic polymer material from chemical exposure, thermal exposure, and mechanical stress during polishing and other processes in the manufacturing process. The finished product has a void 43 around the bump joint, which relieves the thermosetting resin filler from mechanical stress caused by the ambient temperature, preventing failure due to that stress and improving reliability. This void 43 may be filled with air, which has a relatively low dielectric constant, is easy to handle and inexpensive, or it may be filled with an inert gas such as nitrogen or argon, which is chemically inert, to improve stability and reliability, or it may be vacuum-sealed, which is even more stable and has a lower dielectric constant. Here, the maximum distance between the first main surface 19 of the wiring substrate 1 and the first main surface 29 of the semiconductor element 22 is set to be between 10 nm and 50 μm. If the maximum distance is less than 10 nm, temporary filling of the void becomes difficult, and if it exceeds 50 μm, the bump size becomes large, making it difficult to achieve the objective of high-density mounting. The maximum distance is preferably between 10 nm and 10 μm, and more preferably between 10 nm and 2 μm.

[0016] Generally, both the wiring board 11 and the semiconductor element 22 are better suited to producing higher-quality elements and circuits on the first main surface (front) side than on the second main surface (back) side. Taking a Si wafer as an example, this is because the first main surface side has fewer crystal defects and has undergone processing that results in high smoothness and flatness. Although wafers with processing quality close to that of the first main surface are commercially available, it is not easy to form circuits and elements of the same high quality on both sides due to issues with maintaining the polishing and other processing. Many film deposition, polishing, etching, and lithography systems are also based on processing on the first main surface.

[0017] In this invention, a wiring board 11 and a semiconductor element 22 on which high-function circuits and elements are formed are manufactured or prepared, and the wiring board and the semiconductor element are joined together on their first main surface sides (19 and 29) via bump electrodes. Since the semiconductor element 22 is positioned with the first main surface 29 facing downwards, a semiconductor device 1001 with a high-performance thin-film semiconductor element 22 arranged on a wiring substrate 11 can be obtained relatively easily by etching and polishing from the second main surface side. A typical example of a thin-film semiconductor element where the back side, which is the second main surface, is the exposed surface side is a back-side photodetector element, and this structure and manufacturing method is particularly suitable for supplying a GaAs infrared photodetector incorporating a metamaterial structure that improves the signal-to-noise ratio characteristics by utilizing plasmon resonance. Furthermore, with this configuration, at least the vicinity of the bump electrode is an air gap 43, so unwanted capacitance can also be suppressed.

[0018] <Manufacturing method> The manufacturing method of the semiconductor device 1002 according to Embodiment 1 will be explained using Figure 2, which is a flowchart, and Figures 3 and 4, which illustrate the manufacturing process using a cross-sectional structure. Here, the example is given in which the semiconductor element 22 is an infrared image sensor (photodetector) having a metamaterial structure.

[0019] First, a wiring substrate 11 is prepared that has a rigid, self-supporting surface, and has a first electrode bump consisting of a plurality of bump electrodes 12 (not shown) to which the electrical wiring of an electrical circuit is at least electrically connected on the first main surface 19 side (step S11 in Figure 2, Figure 3(a)). There are no particular restrictions on the material of the wiring substrate, but examples include Si, GaAs, SiO2, SiON, Ge, InP, GaSb, GaP, InAs, InSb, SiC, GaN, AlN, sapphire, glass, and epoxy substrates. Any material used for electrode bumps can be used, but considering bonding strength, bonding stability, reliability, bonding resistance, corrosion resistance, and durability, Au, Ag, Cu, Al, Ti, Ni, Fe and alloys mainly composed of these, and eutectic alloys composed of In, Pb, Sn, Sb, Bi, Au, Ag, Al, Cu, Si, Ge, etc. can be used. Gold, in particular, is favored because it is resistant to corrosion, forms strong bump joints, and possesses excellent mechanical strength in addition to the electrical stability of the joints. Here, "self-supporting rigidity" means having the rigidity to maintain its shape even when placed vertically.

[0020] Next, a semiconductor device sample is prepared in which a semiconductor device 22 having a semiconductor layer is formed on the surface of a substrate 21 having self-supporting rigidity (step S12 in Figure 2, Figure 3(b)). Here, a second electrode bump 23 consisting of a plurality of bump electrodes is arranged on the first main surface 29 side of the semiconductor device 22. Here, the substrate 21 is preferably one that has self-supporting rigidity, insulating properties, and good processability by polishing and etching, and examples include Si, GaAs, SiO2, SiON, SiC, Ge, InP, GaSb, GaP, InAs, InSb, GaN, AlN, CdTe, CdZnTe, sapphire, glass, and epoxy substrates. While any material suitable for use as an electrode bump can be used, considering bonding strength, stability, reliability, resistance, corrosion resistance, and durability, gold (Au), Ag, Cu, Al, Ti, Ni, Fe, alloys mainly composed of these materials, and eutectic alloys composed of In, Pb, Sn, Sb, Bi, Au, Ag, Al, Cu, Si, Ge are preferred. Gold, in particular, is preferred because it is corrosion-resistant, provides strong bump bonding, and exhibits excellent electrical stability and mechanical strength. The thickness of the semiconductor element 22 is not particularly limited, but typically it is between 10 nm and 100 μm. Examples of semiconductor layers for the semiconductor device 22 include Si, GaAs, AlGaAs, AlAs, InGaAs, Ge, GaSb, GaP, InAs, InSb, AlSb, AlGaSb, InGaSb, GaN, InN, AlP, InP, AlN, InN, Ga2O3, PbS, PbSe, ZnTe, CdTe, HgTe, ZnSe, CdSe, and MgSe. The order in which the semiconductor device sample and the wiring board 11 are prepared does not matter; either can be done first, or they can be done simultaneously.

[0021] Subsequently, the first main surface 19 side of the wiring board 11 and the first main surface 29 side of the semiconductor element 22 are brought into contact, and at least a portion of the first electrode bump 12 and the second electrode bump 23 are mechanically brought into contact to form a solid-phase diffusion bond (solid-phase diffusion bonding) between the first electrode bump 12 and the second electrode bump 23 (step S13 in Figure 2, Figure 3(c)). The bonding pressure can be between 1 MPa and 10 MPa. The bonding temperature can be between 150°C and 300°C. Through solid-phase diffusion bonding, the bond between the first electrode bump 12 and the second electrode bump 23 provides mechanical strength and electrical conductivity suitable for extremely fine structures that fully utilize the metamaterial structure. When gold is used for the first and second electrode bumps 12 and 23, sufficient bonding can be obtained with contact at room temperature by performing surface activation.

[0022] Subsequently, a filler 31 made of a thermoplastic polymer whose viscosity changes with temperature and which can be removed by a solvent is filled into the void formed between the first main surface 19 of the wiring substrate 11 and the first main surface 29 of the semiconductor element 22 (step S14 in Figure 2, Figure 3(d)). The filler 31 preferably has a rigidity at room temperature comparable to that of a solid polymer material in order to protect the sample during the subsequent substrate removal step of 21. Since the filler 31 is ultimately removed without leaving any residue, it is preferable that it be completely removed by a solvent at room temperature or by a solvent in a temperature environment of 60°C to 200°C. Examples of thermoplastic polymers include linear, branched, and cyclic hydrocarbon waxes. Examples of solvents include chloroform, benzene, diethyl ether, and N-methyl-2-pyrrolidone.

[0023] Subsequently, the substrate 21 is etched, polished, or both etched and polished to a predetermined depth, starting from the second main surface side of the substrate 21 (opposite the first main surface 29 of the semiconductor element 22) (step S15 in Figure 2, Figure 4(a)). At this time, whether to protect the semiconductor element 22 by not completely removing the substrate 21, to remove the substrate 21 just enough, or to remove part of the semiconductor element 22 is a design matter and can be selected as appropriate. This process yields a thin-film semiconductor element 22. For polishing, either mechanical polishing or CMP (Chemical Mechanical Polishing) can be used. For etching, for example, in the case of a GaAs substrate, a solution obtained by mixing a 1 g / ml citric acid aqueous solution and hydrogen peroxide solution in a 10:1 ratio can be used.

[0024] Subsequently, if necessary, a predetermined circuit is formed on the second main surface side of the semiconductor element 22 (step S16 in Figure 2, Figure 4(b)). When fabricating an infrared image sensor with a metamaterial structure, fine antenna wiring for inducing plasmon resonance, electrodes and wiring for extracting electrical signals, and peripheral circuits such as amplifiers are formed. If the semiconductor element 22 does not require wiring on the back side, this step can be skipped.

[0025] Subsequently, the filler material 31 is dissolved from the sample in which the thin-film semiconductor element 22 is bump-bonded onto the wiring board 11 using the aforementioned heat treatment or solvent (step S17 in Figure 2, Figure 4(c)). Finally, the semiconductor device 1002 can be manufactured by attaching wires 32, etc. (Figure 4(d)).

[0026] According to this manufacturing method, the sample is protected by a thermoplastic polymer material from chemical exposure, thermal exposure, and mechanical stress during polishing and other processes in the manufacturing process. Because the finished product has a gap 43 around the bump joint, the thermosetting resin filler is freed from mechanical stress caused by the ambient temperature, preventing failure due to that stress and improving reliability.

[0027] For reference, the manufacturing method when filling and leaving some resin in the conventional method is shown below. First, a wiring substrate 11 is prepared that has a rigid, self-supporting structure and has a first electrode bump consisting of a plurality of bump electrodes 112 (not shown) to which the electrical wiring of the electrical circuit is at least electrically connected on the first main surface 19 side (Figure 5(a)). Next, a semiconductor device sample is prepared in which a semiconductor device 122 having a semiconductor layer is formed on the surface of a substrate 121 having self-supporting rigidity (Figure 5(b)). Here, a second electrode bump 23 consisting of multiple bump electrodes is arranged on the first main surface 29 side of the semiconductor device 22. In conventional methods, gold (Au) is often used as the material for the bump electrodes 23 and indium (In) is often used as the material for the bump electrodes 112. Subsequently, the first main surface 19 side of the wiring board 11 and the first main surface 29 side of the semiconductor element 122 are brought into contact, and at least a portion of the first electrode bump 112 and the second electrode bump 23 are mechanically brought into contact and heated and melted to form a bond between the first electrode bump 112 and the second electrode bump 23 (Figure 5(c)). Subsequently, a filler 131 made of epoxy resin is filled into the gap formed between the first main surface 19 of the wiring board 11 and the first main surface 29 of the semiconductor element 122, and the filler 131 is cured by heat treatment or other means as necessary (Figure 5(d)). Subsequently, the substrate 121 is processed to a predetermined depth by etching, polishing, or both, starting from the second main surface side of the substrate 121 (the side opposite to the first main surface 29 of the semiconductor element 122) (Figure 6(a)). Subsequently, if necessary, a predetermined circuit 124 is formed on the second main surface side of the semiconductor element 122 (Figure 6(b)). Finally, the semiconductor device 2001 is supplied with wires 32 and other components attached (Figure 6(c)). In conventional methods, while the bump electrodes 23 and 112 are protected from the external environment by the presence of the filler material 131, a problem arises in that they are more susceptible to damage and other issues due to stress caused by temperature changes.

[0028] (Embodiment 2) Embodiment 2 describes a semiconductor device structure and manufacturing method that prevents deterioration over time due to the influence of outside air, which is a concern with the structure in Embodiment 1 where the space near the bump electrode junction is a void, and that does not break down and operates normally even when some force is applied in a direction that separates the semiconductor element side and the substrate wiring side.

[0029] The semiconductor device 1003 of Embodiment 2, as shown in Figure 7, is a semiconductor device in which bumps 12 and 23 are arranged between a wiring board 11 and a semiconductor element 22, and the wiring board 11 and the semiconductor element 22 are at least electrically connected, characterized in that a sealing material 41 is provided on the outer periphery of the semiconductor element 22. This structure protects the bump junctions of the semiconductor device 1003 from the external environment, making them less susceptible to deterioration over time. Furthermore, the increased mechanical strength makes it more difficult for the semiconductor element 22 to peel off the wiring board 11, thus reducing damage and improving reliability. The void 43 is preferable in either a vacuum or inert gas-filled state, but air sealing is also acceptable for lower costs. Figure 7 also shows the metamaterial structure 24 and wire 32 described in Embodiment 1 for reference.

[0030] The semiconductor device 1003 can be manufactured using a B-stage epoxy, which is a one-component epoxy in a semi-solid state, by the following method.

[0031] First, as shown in Figure 8(a), blocks 41a of B-stage epoxy are placed around the outer periphery of the semiconductor element 22, and a vacuum is applied. The gap 43 becomes a vacuum due to the vacuum application. Here, it is preferable to place the B-stage epoxy discretely rather than evenly around the outer periphery. In this state, the sample is heated to a predetermined viscosity to fluidize the B-stage epoxy. The B-stage epoxy wets and spreads along the outer circumference of the semiconductor device substrate and is automatically drawn into gaps by capillary force, but its viscosity prevents it from penetrating too deeply, allowing it to stop after only a small amount of penetration. Next, by cooling without pressurizing while maintaining a vacuum, a semiconductor device is completed in which the gap 43 is surrounded by a sealing material 41 made of B-stage epoxy, which maintains the vacuum.

[0032] Although the semiconductor elements forming the joint are extremely thin and fragile, this method makes it possible to protect the bump joint from the outside air while increasing its mechanical strength. Furthermore, by introducing a gas of the appropriate type and pressure (for example, an inert gas such as Ar or N2) into the chamber before heating, the atmosphere in the gap can be changed to an optimal one. In addition to this method using B-stage epoxy, another method involves providing a liquid syringe whose position can be moved by external operation, and dispensing a one-component epoxy under a vacuum environment.

[0033] (Embodiment 3) Embodiment 3 introduces an example of applying the semiconductor device shown in Embodiment 1 to an image sensor. Photoelectric conversion elements, including image sensors, are preferably back-illuminated with a thin semiconductor layer to avoid the adverse effects of light shielding by wiring, substrates, etc. From this viewpoint, the element structure of the present invention, which has a thin-film semiconductor element structure and in which the exposed side of the semiconductor element is the second main surface side (back side), is suitable for this application.

[0034] Furthermore, when the target wavelength of the sensor is infrared, particularly in the mid-infrared region between 2.5 μm and 25 μm, it is often used at low temperatures such as -200°C due to the signal-to-noise ratio. On the other hand, since the sensor undergoes heat treatment at temperatures such as 180°C during manufacturing, it is necessary to create an element that is resistant to damage over a wide temperature range, does not compromise reliability, and maintains performance. From this perspective, conventional structures using resins such as epoxy resin, which have a coefficient of thermal expansion orders of magnitude larger than that of the semiconductor layer, have presented significant problems. In the structure of the present invention, at least the area near the bump junction is a void, and this area may be a vacuum. Therefore, the structure of the present invention is also suitable from the viewpoint of temperature adaptability, and can provide a semiconductor device that has fewer problems such as failure even in a temperature range of 4K to 400K.

[0035] Furthermore, the exposed surface of the semiconductor device is planarized and smoothed using methods such as CMP (Chemical Polishing). Therefore, it is also suitable for forming metamaterial structures that require fine pattern formation. Typical applications of the semiconductor device of the present invention include light-receiving elements and light-emitting elements.

[0036] Figure 9 shows the structure of an example application of the semiconductor device 1004 of the present invention to a mid-infrared image sensor with a wavelength of 2.5 μm to 25 μm. Here, the semiconductor device 1004 consists of a wiring board (ROIC, readout circuit) 11, a circuit inside the wiring board 11a, an Au bump 12, a semiconductor element 22, a GaAs semiconductor layer 22a, a pixel bump 23a, a peripheral circuit bump 23b, an antenna wiring for the metamaterial structure 24a, an electrode wiring for the metamaterial structure 24b, a peripheral circuit 24c, a quantum well layer 51 made of GaAs / AlGaAs, an insulator layer 52, a pixel region 61, a single pixel region 61a, a peripheral circuit region 62, a peripheral circuit formation region 62a, and a circuit protection region 62b. Details of the manufacturing method, etc., will be described in the examples. [Examples]

[0037] (Example 1) This invention was particularly utilized in the manufacture of metamaterial infrared cameras, which require delicate electrode bump bonding.

[0038] <Overview> First, let's outline Example 1. A silicon-based CMOS circuit was used for the readout circuit. The infrared detection material has a metamaterial structure in which GaAs / AlGaAs quantum wells are sandwiched between layers of Au. However, because the semiconductor layer is only about 200 nm thick, in conventional underfill methods where thermal stress is applied, a large difference in thermal contraction occurs between the electrode bumps and the underfill layer when cooled to -200°C during use, causing the semiconductor layer to rupture or the properties to change due to large stresses.

[0039] By using a wax based on commercially available electron wax as a thermoplastic underfill material, it was possible to protect the electrode bumps and circuit surfaces of the joints from contamination and corrosion caused by polishing powder, chemicals, and gases during processes such as substrate polishing, chemical etching, resist coating, development, resist removal, dry etching, and cleaning in the lithography process. Furthermore, after manufacturing, the wax was dissolved with an appropriate solvent, and the solvent was replaced and removed without applying surface tension, thereby creating a void at the joint. If surface protection is necessary, a vapor-depositable atomic layer deposition or parylene film can be deposited, and since infrared cameras are generally mounted in a vacuum chamber for cooling, the surface can be left as is. Cooling to -200°C is required during imaging, but since the electrode bump simply contracts and there is no other material in contact with the semiconductor layer above it, no changes in the semiconductor layer's properties due to stress occurred.

[0040] <Created> 1. Quantum well fabrication process The photovoltaic quantum well infrared detector shown in Figure 10(a) was fabricated using a molecular beam epitaxy (MBE) system (COMPACT21T, RIBER). First, an n-type GaAs(100) substrate 22b was prepared, and the oxide film on its surface was removed by heating at 580°C. Then, a GaAs buffer layer for surface planarization was grown to a thickness of 300 nm using an MBE apparatus. After that, Al at x=0.90 x Ga 1-x As sacrificial layer is 900 nm, Al x=0.55 x Ga 1-x An As sacrificial layer was formed to a thickness of 100 nm. The formation temperature at this time was 580°C. In Figure 10(a), both sacrificial layers are combined and represented as sacrificial layer 110. Subsequently, the multiple quantum well structure shown in Figure 11 and Table 1 was formed. The layers were stacked in the following order: a contact layer which would become the electron recovery layer (109), a final barrier layer, ... the first well layer (103), the first barrier layer (102), and finally a contact layer which would become the electron supply layer (101). The formation temperature for these layers and beyond was 530°C. Here, the multiple quantum well structure (51a in Figure 10(a)) functions like a conventional pn junction-based photodiode, acting as an electrical circuit that generates a photocurrent flowing in the thickness direction when infrared light is incident on it.

[0041] [Table 1]

[0042] 2. Pixel and electrode bump processing process for semiconductor devices To match the specifications of the wiring board to which it was bonded, the final image was divided into 332 horizontal and 268 vertical detection pixels, in addition to the 320 horizontal and 256 vertical detection pixels that make up the final image, by surrounding them with 6 ground pixels on each side. Each pixel is arranged in a square grid with a period of 30 μm.

[0043] The difference between ground pixels and detection pixels is that ground pixels penetrate the detection layer, and Al x Ga 1-x As forms through holes that reach the sacrificial layer, Al x Ga 1-xThe sacrificial layer is exposed on the first main surface side. Therefore, the electrode bumps formed on the detection pixels are electrically connected to the electron supply layer, while the electrode bumps formed on the ground pixels are connected to the electron recovery layer side. A closed circuit is formed from 320 horizontal and 256 vertical detection pixels to the ground pixels arranged on its outer periphery. Also, in this embodiment, the electrode bumps are formed in two layers.

[0044] The first layer (lower electrode bump) is also used as a mask for dry etching for pixel separation. By dry etching for pixel separation, the end face of the multiple quantum well structure is exposed. In this embodiment, a polyimide thin film is used for this protection, and finally, the second layer upper electrode bump with a sufficient thickness is formed, and this is joined to the first electrode bump of the wiring board. The polyimide thin film has an opening provided at the center of each pixel, and the lower electrode bump and the upper electrode bump are electrically connected here. Hereinafter, the pixel and electrode bump processing of the semiconductor element will be described by dividing it into five steps. For patterning, photolithography was used except for the metal patches of the plasmon resonator.

[0045] 2.1 First Step The first step is the formation of the through holes 25a of the ground pixels as shown in Fig. 10(b). A photoresist was applied, a predetermined pattern was drawn and developed, and four resist openings of 2μm×1μm were formed at the center of the ground pixels. Using this opening as a mask, a through hole with a depth of 250nm that penetrates the multiple quantum well structure (total thickness 164nm) and reaches the Al x Ga 1-x As sacrificial layer was formed. All the subsequent steps are common to the detection pixels and the ground pixels.

[0046] 2.2 Second Step The second step is the formation of the lower electrode bumps (see Figure 10(c)). Photoresist is applied, a predetermined pattern is drawn, and the image is developed to form a 27 μm square resist opening in the center of each pixel. 3 nm thick Ti and 150 nm thick Au are deposited on top of this, and by lift-off, 332 horizontal and 268 vertical 27 μm square lower electrode bumps 24′ are arranged. For the detection pixels, these lower electrode bumps 24′ also serve as one of the metal layers of the plasmon resonator. For the ground pixels, this metal layer penetrates deep into the previously formed through-holes and is exposed on the surface when the semiconductor device is later thinned, becoming the through-electrode 25′.

[0047] 2.3 Third process The third step is dry etching for pixel separation (see Figure 10(d)). The lower electrode bumps formed in the previous step are used as a mask, and dry etching is performed to a depth of 90 nm using inductively coupled plasma etching with a chlorine-nitrogen gas mixture. This depth extends from the electron supply layer beyond the second well layer to the layers beyond the third barrier layer. Since this multiple quantum well 51' is conductive in the in-plane direction in the Si-doped first well layer, each pixel can be electrically separated by drilling to a depth beyond this.

[0048] 2.4 Fourth process The fourth step is the formation of a polyimide protective film 52 to protect the sides of the multiple quantum well structure exposed by the dry etching in the previous step (see Figure 10(e)). The polyimide raw material was spin-coated over the entire substrate and cured by a predetermined baking process. A photoresist was applied on top of this, a predetermined pattern was drawn and developed to form a 19 μm square resist opening in the center of each pixel. From there, the polyimide was removed by plasma etching with oxygen gas to expose the surface of the lower electrode bump. Finally, the photoresist was removed.

[0049] 2.5 Fifth Step The fifth step is the formation of the upper electrode bumps (see Figure 10(f)). A photoresist was applied, a predetermined pattern was drawn, and the surface was developed to form a 23 μm square resist opening in the center of each pixel. On top of this, a 10 nm thick Ti film and a 250 nm thick Au film were deposited by sputtering, and 23 μm square upper electrode bumps (bump 23) were formed by lift-off. At this time, marks corresponding to the alignment marks patterned on the wiring substrate were formed at the four corners. As a result, the first main surface of the semiconductor device had 332 horizontally and 268 vertically arranged 25 μm square upper electrode bumps with a 30 μm period, the remaining area was covered with a polyimide protective film, and alignment marks to be used during subsequent alignment bonding were drawn at the four corners.

[0050] The resulting semiconductor device substrate is cut into a rectangular shape slightly larger than all the pixels, and slightly smaller than a wiring substrate with bonding pads for wiring around its outer edge. Furthermore, the second main surface of this semiconductor device has a uniformly exposed GaAs substrate.

[0051] 3. Pixel and electrode bump processing process for wiring boards Here, electrical wiring and the first electrode bump were fabricated on the first main surface side of a wiring board having a first electrode bump. The wiring board used in this embodiment is the FLIR ISC9705 readout integrated circuit. This is a dedicated wiring board for fabricating image sensors, and it is an integrated circuit formed using a CMOS process in which 320 horizontally and 256 vertically detection pixels, and 6 ground pixels surrounding their outer periphery, for a total of 332 horizontally and 268 vertically, are arranged in a square grid with a 30 μm period (see Figure 12(a)). Thirty-seven bonding pads are formed on the outer circumference, and by applying a predetermined voltage to a predetermined pad or inputting a voltage waveform, an image signal voltage waveform is generated at a predetermined pad. Solid-phase diffusion bonding was performed using gold (Au) as the electrode bump material.

[0052] First, an underbump metal layer 72, which serves as the base for the three-dimensional bumps, was formed on each pixel (see Figure 12(b)). To form the film, first, a 50 nm thick layer of Ti and a 100 nm thick layer of Au were sequentially deposited on the entire substrate using a sputtering method. A photoresist was then applied on top of this, a predetermined pattern was drawn, and the film was developed to form a 20 μm square resist opening in the center of each pixel. Subsequently, the Au and Ti layers were removed by dry etching.

[0053] Next, Au electrode bumps 12 were formed on the underbump metal layer 72 (see Figure 12(c)). First, a photoresist was applied to the front surface of the substrate, a predetermined pattern was drawn, and the film was developed to form openings defining electrode bumps on the underbump metal of each pixel. The shape of the electrode bumps varies depending on the required positioning accuracy and electrical characteristics, and is not fixed. For example, multiple circular patterns may be arranged to fill the square-shaped undermetal bump, or a single pattern of a specific shape may be formed. On this, Au of a thickness corresponding to the pattern was deposited mainly by sputtering, and electrode bumps with a height of 1 to 2.5 μm were formed by lift-off. These bumps are designed to collapse under load during bonding, and after bonding, their thickness becomes 0.1 to 0.5 μm. Furthermore, the second main surface of this wiring board has a uniformly exposed Si substrate.

[0054] 4. Electrode bump bonding process Next, the wiring board and semiconductor element were joined using an alignment bonding device that could align and contact the two substrates, and then pressurize and heat them (see Figure 13(a)). The wiring board and semiconductor element were held in the alignment bonding device so that their first main surfaces faced each other, and the alignment marks drawn on the four corners of both were aligned so that they overlapped complementaryly and the gap between them was not visible. Then, they were pressurized and heated under atmospheric pressure. The pressurizing load depended on the shape of the electrode bumps, but for example, a load was set such that each part was pressed at a pressure of 5 MPa. The temperature was 200 to 250°C. Under these conditions, the Au surfaces were joined by solid-phase diffusion bonding. In this way, 332 horizontally and 268 vertically, the first electrode bumps of the wiring board and the second electrode bumps of the semiconductor element were joined.

[0055] Here, the semiconductor element is cut slightly larger than all the pixels, but the wiring board has bonding pads even further around the outer edge of all the pixels and is cut outside of that, so the wiring board is larger, and the assembled body is such that the smaller semiconductor element is mounted on the larger wiring board with its second main surface exposed and margins on all four sides.

[0056] 5. Filling process for the filler material The core filler material 31 of this patent is Apiezon Wax W from M&I Materials. This material has long been known as a wax for electronic applications, can be easily applied by raising the temperature, and can protect important components and interfaces from various chemicals and solvents. Furthermore, this material can be easily removed with common solvents such as chloroform. In this embodiment, a solvent was added to make it easier to handle in the filling process. This was cut into an appropriate shape and placed along the four sides of the semiconductor element on the wiring board, so that when heated, it would flow into the gap where the electrode bumps were joined.

[0057] The sample was placed in a sealed container equipped with an observation window that allowed for heating and observation of the internal structure from the outside. The sealed container was then connected to a vacuum pump and evacuated. As a result, the gap between the electrode bumps became a vacuum, preventing the formation of bubbles even when a fluid was filled from the outside. In this state, the sample was heated to 185°C to melt the wax. As a result, the wax wetted and spread along the outer perimeter of the semiconductor device substrate, creating a vacuum in the gaps and completely surrounding the outer perimeter with molten wax. Although the wax was molten, it was not very fluid. Therefore, even if capillary action were to act, it would hardly penetrate into the gaps.

[0058] Next, the valve of the sealed container is opened, and nitrogen gas pressurized to 0.5 MPa is introduced. This forces the wax, which would not enter spontaneously, into the gaps due to the pressure from the outside. Since the inside is under vacuum, when pressurization is complete, there are no air bubbles, and the gaps are completely filled with wax. When this sample is cooled to room temperature, a bonded sample is obtained in which a wiring substrate and a semiconductor element are bonded together and the gaps filled with filler material are obtained (see Figure 13(b)).

[0059] 6. Thin-film deposition process for semiconductor devices Next, the semiconductor device was mechanically polished until its thickness was approximately 100 μm. Then, using a solution of 1 g / ml citric acid aqueous solution and hydrogen peroxide solution mixed in a 10:1 ratio, the GaAs and buffer layer were selectively removed at 38°C, exposing the sacrificial layer made of AlGaAs. Subsequently, the sacrificial layer consisting of AlGaAs was selectively removed with an aqueous hydrofluoric acid solution (see Figure 13(c)).

[0060] 7. Circuit formation process on the second main surface side of the semiconductor device Two types of microfabrication were applied to the second main surface of the exposed semiconductor device (see Figure 13(d)). The first microfabrication step is the formation of a plasmon resonator. The quantum wells shown in Figure 11 and Table 1 are based on intersubband transitions, which require an electric field component perpendicular to the substrate. Therefore, they alone are not sensitive to light incident perpendicular to the substrate (where the electric field is parallel to the substrate). While it is possible to achieve some sensitivity with oblique incidence, it is very small. However, when this photovoltaic quantum well infrared detector is combined with a plasmon resonator, it is possible to achieve a sensitivity nearly 1000 times greater than that of the oblique incidence method.

[0061] The second type of microfabrication is electrode wiring. A metal pattern was formed to cover the vertical and horizontal regions of each pixel, with a width of 8 μm, excluding the central 22 μm area which serves as the detection area. Furthermore, a metal pattern was formed to cover all or part of the outermost 6-pixel width ground electrode area, so that all of these are connected as a pattern. This entire area becomes equipotential and acts as the ground electrode 24b. In the ground pixels, the lower electrode pad is exposed to the surface through a through hole. Since a metal pattern was formed on top of this, the ground electrode is connected to the ground pixel of the wiring board, forming a closed circuit.

[0062] 8. Dissolution process of the filler Re-poration was performed to dissolve the filler material 31 from the wiring substrate to which the thin-film semiconductor elements were bump-bonded, thereby forming voids 43 (see Figure 13(e)). For dissolution, chloroform, which readily dissolves the wax used, was used as the solvent, and the temperature was raised to its boiling point to allow it to penetrate and dissolve even into narrow voids. To achieve this, a separable flask containing chloroform was placed on a hot plate, and a Graham condenser was connected to it, allowing for prolonged heating without losing the chloroform by evaporation. The wiring substrate was mounted on a dedicated jig and held vertically, and then completely immersed in the chloroform in the separable flask. When the hot plate was set to 100°C, the chloroform solution temperature was maintained at its boiling point of 61.2°C. This state was maintained for 1 to 2 hours to dissolve the filler material 31 that filled the space between the first main surface of the semiconductor element and the first main surface of the wiring circuit. The wiring board was held vertically during this process because the convection of the liquid in the vertical direction efficiently cleaned the inside of the void. As the chloroform solution gradually became contaminated with the dissolved filler material, the chloroform solution was replaced multiple times as needed to prevent any filler material from remaining, and finally, the chloroform was completely removed.

[0063] 9. Implementation Process Finally, the second main surface of the wiring board, on which the thin-film semiconductor elements were bump-bonded with air gaps, was mounted onto a 28-pin ceramic package using conductive epoxy, and the bonding pads located on the outer periphery of the first main surface of the wiring board and the bonding pads on the ceramic package were wire-bonded with Au wire. Through the above process, a semiconductor device 1005, which is a semiconductor image sensor sensitive to mid-infrared light, was fabricated (see Figure 13(f)).

[0064] <Rating> The current density and voltage characteristics of the fabricated semiconductor device at 77K were measured using a source meter. The results are shown in Figure 14. The characteristics of an infrared detector's current are important in two states: the dark state and the background light state. The dark state is when no radiation is incident on the photodetector and represents the noise characteristics of the infrared detector. In this measurement, the dark state was achieved by covering the front of the photodetector with a 29K cold shield coated with blackbody paint. The background light state is when 300K radiation is incident on the detector and represents the sensitivity of the infrared detector.

[0065] The readout integrated circuit ISC9705 used in this embodiment is equipped with four TEST pixels for evaluating the element characteristics as an infrared detector, in addition to the detection pixels that make up the image. Dedicated wiring is connected to the TEST pixels, and current-voltage characteristics and sensitivity spectra can be measured in the same way as a normal single detector. The circles and crosses in Figure 14 represent the dark state current density and background light state current density, respectively, for one of these TEST pixels.

[0066] Figure 14 also shows the characteristics of a single detector with identical specifications. This single detector is not a readout integrated circuit, but is fabricated by solid-state diffusion bonding of semiconductor elements to a simple Au substrate, similarly thinning it, and then wire bonding it. In Figure 14, the dark state current density and background light state current density of the single detector are shown as ● and +, respectively. However, ● and + almost completely overlap with ×, making them indistinguishable.

[0067] This indicates that, by the method described in this patent, a single pixel of an infrared camera in which the detector is bump-bonded to a wiring board and the filler material 31 is removed to form a gap 43 in the electrode bump portion has the same characteristics as a single infrared detector bonded seamlessly to an Au plate. Semiconductor devices are sensitive to defects and distortions, and these effects are particularly evident in noise, or dark-state current. However, since ○ and ● overlap precisely, the infrared camera fabricated by bonding to the wiring board 11 using the method described in this patent shows no degradation whatsoever from the original single detector's noise characteristics. Furthermore, since × and + overlap precisely, the sensitivity characteristics also show no degradation whatsoever. These results demonstrate that the manufacturing method according to this patent allows for the bonding of semiconductor elements without defects or distortion.

[0068] This infrared camera has a sensitivity peak at a wavelength of 6.4 μm and was designed to visualize H2O gas (water vapor, gaseous water). Figure 15 shows the sensitivity spectrum of a single detector (circles) and the absorption spectrum of H2O gas (lines). The two overlap across the entire range. Therefore, the camera fabricated with this detector can dynamically visualize the absorption and emission of H2O gas as an image. The sensitivity shown in Figure 15 is the zero-bias sensitivity, where no bias voltage is applied to the detector. The readout integrated circuit ISC9705 used in this embodiment has a function to apply a bias voltage to the detection pixel. When an appropriate bias voltage is applied to the detector used, the sensitivity increases several times while the sensitivity spectrum remains almost unchanged. Therefore, by applying an appropriate bias voltage, it is possible to visualize the flow of H2O gas with several times higher sensitivity.

[0069] Figures 16 and 17 are examples of actual images taken using this infrared camera. Figure 16 shows a human hand and water vapor emitted from a heated humidifier against a wall at room temperature. This camera is basically the same as a thermograph and can visualize infrared light emitted from an object. However, as shown in Figure 15, it differs in that it has a narrow sensitivity spectrum and visualizes only infrared light of a specific wavelength from the broad spectrum of infrared light emitted from an object. Figure 16(a) shows that the outlet of the heated humidifier is bright due to its high temperature, indicating that H2O gas is being released from it. The gas is brighter than the hand in the background, indicating that the H2O gas is hotter than human body temperature. Figure 16(b) shows the same image with the brightness adjusted so that the human hand is clearly visible. Figure 17 shows a human face photographed against a blackbody plane light source at 55°C. Figure 17(a) shows a person wearing glasses with their mouth open. Figure 17(b) is the same image displayed with adjusted brightness, where the H2O gas contained in the exhaled breath is visualized as a black cloud. As described above, we bonded the detector to the circuit board and fabricated an infrared camera that retained its original performance, successfully visualizing H2O gas as intended. [Industrial applicability]

[0070] The present invention provides a semiconductor device using a wiring board that suppresses the occurrence of crack defects during manufacturing, resulting in a high yield, and exhibits excellent long-term stability during use, particularly with significantly reduced breakdown due to temperature changes. This characteristic is especially suitable for infrared image sensors, which experience drastic temperature changes from manufacturing to the operating environment. Furthermore, the present invention can also provide a metamaterial quantum well type photodetector with excellent signal-to-noise ratio and high detection sensitivity, through a thin-film semiconductor layer with low light loss. Such photodetectors have a wide range of applications, including sensors and cameras for civilian, industrial, and military use. Therefore, we believe that this invention will have a significant social impact and a major influence on industry. [Explanation of Symbols]

[0071] 11: Wiring board, ROIC 11a: Circuitry inside the wiring board 12: Bump, Au Bump, Au 19: 1st main surface 21: Semiconductor device substrate 22: Semiconductor element section 22a: Semiconductor layer, GaAs 22b: GaAs substrate 23: Bump, Au Bump, Au 23a: Pixel bump, Au 23b: Peripheral circuit bump, Au 24: Metamaterial Structure 24′: Lower electrode bump 24a: Antenna wiring for metamaterial structures, metal patches 24b: Electrode wiring and ground wiring for metamaterial structures 24c: Peripheral Circuits 25′:Through electrode 25a: Through hole 29: 1st main surface 31: High-temperature curing polymers, waxes, and fillers 32: Wire 41: Fillers, sealants 41a: Fillers, sealants, and B-stage epoxy blocks 43: Void, gap, interstitial space 51: Quantum well layer, GaAs / AlGaAs 51′: Quantum well layer 51a: Quantum well layer 52: Insulating layer, protective film 53: Semiconductor substrate, GaAs 61: Pixel area 61a: Single pixel area 62: Peripheral Circuit Area 62a: Peripheral circuit formation region 62b: Circuit protection area 63:1 pixel area 71a: Pixel electrode 71b: Pixel electrode 72: Underbump Metal Layer 101: Electron supply layer, contact layer 102: The first barrier layer 103: The first well layer 104: The second barrier layer 105: Second well layer 106: The third barrier layer 107: The third well layer 108: The 7th Barrier Layer 109: Electron recovery layer, contact layer 110: Sacrificial Layer 112: Bump, In Bump, In 121: Semiconductor device substrate 122: Semiconductor element section 124: Wiring structure 131: Epoxy resin 1001: Semiconductor Device 1002: Semiconductor device 1003: Semiconductor device 1004: Semiconductor device for infrared imaging 1005: Semiconductor device 2001: (Conventional) Semiconductor Device

Claims

1. A semiconductor device having semiconductor elements and wiring substrates as essential components. The wiring board has a first electrode bump on the first main surface side of the wiring board, which consists of a plurality of bump electrodes to which electrical wiring is at least electrically connected. The semiconductor element has a second electrode bump consisting of a plurality of bump electrodes to which the electronic circuit of the semiconductor element is connected, on the first main surface side of the semiconductor element. The semiconductor element is arranged with the wiring substrate so that their first main surfaces face each other, and the plurality of first electrode bumps and the plurality of second electrode bumps are mechanically and electrically joined. A void is formed between the first main surface of the wiring board and the first main surface of the semiconductor element. A semiconductor device using a wiring substrate, wherein the maximum gap between the first main surface of the wiring substrate and the first main surface of the semiconductor element is 10 nm or more and 50 μm or less.

2. The semiconductor device according to claim 1, wherein the surface side of the semiconductor device is the second main surface side of the semiconductor element.

3. The semiconductor device according to claim 1 or 2, wherein the bonding between the first electrode bump and the plurality of second electrode bumps is a solid-phase diffusion bonding.

4. The semiconductor device according to claim 1, wherein the average thickness of the semiconductor element is 10 nm or more and 100 μm or less.

5. The semiconductor device according to claim 1, wherein the maximum gap between the first main surface of the wiring substrate and the first main surface of the semiconductor element is 10 nm or more and 10 μm or less.

6. The semiconductor device according to claim 1, wherein the semiconductor element is a light-receiving or light-emitting element.

7. The semiconductor device according to claim 1, wherein the semiconductor element is an infrared light receiving element.

8. The semiconductor device according to claim 1, wherein the semiconductor element has an operating temperature of 4K or more and 400K or less.

9. The semiconductor device according to claim 1, wherein a sealing material is arranged on the outer periphery of the semiconductor element to block outside air and reinforce its mechanical strength.

10. The semiconductor device according to claim 9, wherein the sealing material is made of epoxy resin.

11. The semiconductor device according to any one of claims 1 to 10, wherein the void is formed in a region including at least the joint between the first bump and the second bump.

12. A method for manufacturing a semiconductor device, wherein semiconductor elements and wiring substrates are essential components. The wiring board is prepared such that the electrical wiring of the wiring board has a first electrode bump formed on the first main surface side, which consists of a plurality of bump electrodes that are at least electrically connected, and the wiring board has at least enough rigidity to stand on its own. A semiconductor element is prepared in which a second electrode bump, consisting of a plurality of bump electrodes to which at least a part of the electronic circuit of the semiconductor element is connected, is formed on the first main surface side of a self-supporting substrate. The first main surface side of the wiring board and the first main surface side of the semiconductor element are brought into opposition, and at least a portion of the first electrode bump and the second electrode bump are mechanically brought into contact to form a joint between the first electrode bump and the second electrode bump. The void formed between the first main surface of the wiring board and the first main surface of the semiconductor element is filled with a filler made of a thermoplastic polymer whose viscosity changes with temperature and which can be removed by a solvent. The second main surface side of the semiconductor element is treated to a predetermined depth by etching, polishing, or both etching and polishing to thin the semiconductor element. A predetermined circuit is formed on the second main surface side of the semiconductor element, A method for manufacturing a semiconductor device using a wiring substrate, comprising dissolving the filler material from a sample in which a thin film of semiconductor elements is bump-bonded on the wiring substrate using heat treatment or a solvent.

13. The method for manufacturing a semiconductor device according to claim 12, wherein the filler is wax.

14. The method for manufacturing a semiconductor device according to claim 12, wherein the maximum gap between the first main surface of the wiring substrate and the first main surface of the semiconductor element is 10 nm or more and 50 μm or less.

15. The method for manufacturing a semiconductor device according to claim 12, wherein the average thickness of the semiconductor element is 10 nm or more and 100 μm or less.

16. The method for manufacturing a semiconductor device according to claim 12, wherein the semiconductor element is an infrared light receiving element.

17. The method for manufacturing a semiconductor device according to claim 16, wherein the semiconductor element is an infrared light receiving element having a metamaterial structure, and the predetermined circuit has a light receiving side wiring and an antenna.

18. A method for manufacturing a semiconductor device according to claim 12, wherein a sealing material that blocks outside air is applied to the outer periphery of the semiconductor element to seal and protect the first electrode bump and the second electrode bump from outside air and to reinforce the mechanical strength of the semiconductor device.

19. The method for manufacturing a semiconductor device according to claim 18, wherein the sealing material is made of epoxy resin.

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