Semiconductor devices and electronic equipment

Abstract

This technology provides ESD resistance while offering advantages in miniaturizing semiconductor devices. [Solution] The semiconductor device comprises a semiconductor substrate, a wiring structure disposed on the semiconductor substrate, and a varistor. The wiring structure includes a pad region including pads and a circuit region, each of which includes a plurality of wiring layers, an interlayer insulating film disposed between the plurality of wiring layers, and via plugs connecting the plurality of wiring layers to each other, the varistor is electrically connected to the pads, and the varistor is located in the circuit region and above the upper surface of the semiconductor substrate.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and an electronic device.

Background Art

[0002] A semiconductor device includes an ESD (Electro-Static Discharge) protection circuit for protecting an electronic circuit disposed therein from noise such as ESD discharge.

[0003] Patent Document 1 describes an ESD protection circuit disposed between two bonding pads. In the ESD protection circuit ESD described in Patent Document 1, a resistor R1 and a capacitor C1 are connected in series between a power supply voltage VCC and a reference potential VSS, and an input part of an inverter Iv1 is connected to a connection part between the resistor R1 and the capacitor C1. The inverter Iv1 is composed of a configuration in which a transistor T1 of a P-channel MOS and a transistor T2 of an N-channel MOS are connected in series between the power supply voltage VCC and the reference potential VSS. A gate of a clamping transistor T3 composed of an N-channel MOS is connected to an output part of the inverter Iv1. One end of the source / drain of the transistor T3 is connected to the power supply voltage VCC, and the other end of the source / drain of the transistor T3 is connected to the reference potential VSS. The gate of the transistor T3 is connected to the reference potential VSS via a resistor R2, and a parasitic diode DP is formed at a junction between the well region and the source of the transistor T3. Also, a diode D1 is connected between the power supply voltage VCC and the reference potential VSS. Generally, an ESD protection circuit incorporated in a semiconductor device has a complex configuration and may occupy a large area in the semiconductor device. Therefore, the ESD protection circuit is a factor that causes the semiconductor device to become larger.

[0004] Although it is not directly related to the present application, Patent Document 2 describes a non-volatile memory device comprising a lower electrode layer formed on a substrate, a resistive switching layer connected to the lower electrode layer, an upper electrode layer connected to the resistive switching layer, and an insulating metal oxide thin film layer formed on the lower electrode layer. Patent Document 2 also describes that the non-volatile memory device may further include a non-ohmic element connected in series with the resistive switching layer, and that the non-ohmic element may consist of a MIM diode, an MSM diode, or a varistor. [Prior art documents] [Patent Documents]

[0005] [Patent Document 1] Japanese Patent Publication No. 2015-88652 [Patent Document 2] Japanese Patent Publication No. 2008-305889 [Overview of the Initiative] [Problems that the invention aims to solve]

[0006] The present invention aims to provide a technology that offers advantages in miniaturizing semiconductor devices while providing ESD resistance. [Means for solving the problem]

[0007] A first aspect of the present invention relates to a semiconductor device having a semiconductor substrate, a wiring structure disposed on the semiconductor substrate, and a varistor, wherein the wiring structure includes a pad region including pads and a circuit region, each of the pad region and the circuit region including a plurality of wiring layers, an interlayer insulating film disposed between the plurality of wiring layers, and via plugs connecting the plurality of wiring layers to each other, the varistor is electrically connected to the pads, and the varistor is located in the circuit region and above the upper surface of the semiconductor substrate.

[0008] A second aspect of the present invention relates to an electronic device, wherein the electronic device comprises a semiconductor device relating to the first aspect. [Effects of the Invention]

[0009] According to the present invention, a technology is provided that offers advantages in miniaturizing semiconductor devices while providing ESD resistance. [Brief explanation of the drawing]

[0010] [Figure 1] A schematic plan view showing the configuration of a semiconductor device according to one embodiment. [Figure 2] A schematic cross-sectional view showing the configuration of a semiconductor device according to one embodiment. [Figure 3] A diagram illustrating an equivalent circuit of a part of a semiconductor device according to one embodiment. [Figure 4] (a) is a diagram showing the CAD layout of a conventional ESD protection circuit, and (b) is a diagram schematically showing the CAD layout of the varistor in this embodiment. [Figure 5] This graph shows an estimated relationship between the area occupied by protective elements and HBM (Human Body Model) resistance. [Figure 6] Cross-sectional view of a semiconductor device incorporating a conventional ESD protection circuit (ESDC). [Figure 7] Plan view of a semiconductor device incorporating a conventional ESD protection circuit (ESDC). [Figure 8] A cross-sectional view of the semiconductor device of the varistor V in this embodiment. [Figure 9] A plan view of the semiconductor device of the varistor V in this embodiment. [Figure 10] (a) is a schematic plan view of the varistor of the first embodiment, (b) is a schematic cross-sectional view of the varistor of the first embodiment, and (c) is a schematic cross-sectional view of a modified example of the varistor of the first embodiment. [Figure 11] (a) is a schematic plan view of the varistor of the second embodiment, (b) is a schematic cross-sectional view of the varistor of the second embodiment, and (c) is a schematic cross-sectional view of a modified example of the varistor of the second embodiment. [Figure 12] A schematic plan view of the varistor according to the third embodiment. [Figure 13](a) is a schematic cross-sectional view of the varistor of the third embodiment, and (b) is a schematic cross-sectional view of the varistor of the third embodiment. [Figure 14] Schematic plan view of the varistor of the fourth embodiment. [Figure 15] (a) is a schematic cross-sectional view of the varistor of the fourth embodiment, and (b) is a schematic cross-sectional view of the varistor of the fourth embodiment. [Figure 16] (a) is a schematic plan view of the varistor of the fifth embodiment, (b) is a schematic cross-sectional view of the varistor of the fifth embodiment, and (c) is a schematic cross-sectional view of a modified example of the varistor of the fifth embodiment. [Figure 17] Schematic plan view of the varistor of the sixth embodiment. [Figure 18] (a) is a schematic cross-sectional view of the varistor of the sixth embodiment, and (b) is a schematic cross-sectional view of the varistor of the sixth embodiment. [Figure 19] Diagram illustrating an electronic device according to an application example.

Embodiments for Carrying Out the Invention

[0011] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. Note that the following embodiments do not limit the invention according to the claims, and not all combinations of the features described in the embodiments are essential for the invention. Two or more of the features described in the embodiments may be arbitrarily combined. Also, the same or similar configurations are assigned the same reference numerals, and duplicate descriptions are omitted.

[0012] Figures 1 and 2 are schematic plan and cross-sectional views, respectively, showing the configuration of a semiconductor device 1 according to one embodiment. The semiconductor device 1 may include a semiconductor chip 12 having one or more varistors V and one or more pads 16. The semiconductor device 1 may also include one or more lead frames 14 and a package 10 that encloses the semiconductor chip 12. Each pad 16 of the semiconductor chip 12 and its corresponding lead frame 14 may be electrically and physically connected by bonding wires 18. When forming the bonding wires 18, bonding balls 17 may be formed on the pads 16, and the pads 16 and bonding wires 18 may be electrically and physically connected via the bonding balls 17. The semiconductor chip 12 may have a pad region including the pads 16 and a circuit region. Various circuit blocks, such as a power supply circuit, arithmetic circuit, ADC (analog-to-digital converter), memory circuit, audio processor, DAC (digital-to-analog converter), video processor, bus, clock circuit, etc., may be arranged in the circuit region.

[0013] Figure 3 illustrates an equivalent circuit of a portion of a semiconductor device 1 according to one embodiment. The semiconductor device 1 may include, for example, one or more power pads VDD, one or more ground pads GND, one or more input pads IN1, IN2, one or more output pads OUT1, OUT2, and one or more circuit blocks CB. Although not shown, the semiconductor device 1 may also include one or more input / output pads. Power pads, ground pads, input pads, output pads, and input / output pads may be collectively referred to as pads. Power pad VDD may be electrically connected to power line VDDL. Power line VDDL may be supplied with a voltage (a voltage converted by the power circuit) supplied from power pad VDD via a power circuit.

[0014] Two or more pads may be electrically connected to each other by a path including a varistor V. Alternatively, two or more pads may be electrically connected to each other by a path including a varistor V and a resistive element R. In other words, the varistor V may be electrically connected to the pads by a wiring pattern WP. Alternatively, the varistor V may be electrically connected to the pads via a wiring pattern WP and a resistive element R. The varistor V may be, for example, a varistor having a molybdenum oxide film as the resistive film. A varistor having a molybdenum oxide film as the resistive film is advantageous in that the varistor voltage can be adjusted over a wide range. The varistor V may also be, for example, a varistor having ceramics obtained by adding a metal oxide to ZnO (zinc oxide) and firing it as the resistive film. Alternatively, the varistor V may have a resistive film made of other materials.

[0015] Conventionally, semiconductor devices have protected their internal circuits from surge currents using an ESD protection circuit that includes a diode containing a PN junction formed in the semiconductor substrate. However, this ESD protection circuit, including the diode containing the PN junction, occupies a considerably large area, contributing to the increased size of the semiconductor device. In this embodiment, the semiconductor device 1 is miniaturized by incorporating a varistor V as a protection element. The varistor V can have a structure selected from various structures, as will be described later.

[0016] Figure 4(a) schematically shows a CAD layout of a conventional ESD protection circuit ESDC incorporated into a semiconductor device. The ESD protection circuit ESDC can be electrically connected to pad BP by a wiring pattern WP. Figure 4(b) schematically shows a CAD layout of a varistor V of this embodiment incorporated into a semiconductor device. The varistor V can be electrically connected to pad BP by a wiring pattern WP.

[0017] Figure 5 is a graph showing the approximate relationship between the area occupied by the protective element and HBM (Human Body Model) immunity. The solid line represents the case where the varistor of this embodiment is used as the protective element, and the dotted line represents the case where the conventional ESD protection circuit ESDC, schematically shown in Figure 4(a), is used as the protective element. According to this embodiment, excellent HBM immunity can be obtained while reducing the area of ​​the protective element.

[0018] Figures 6 and 7 show a cross-sectional view and a plan view, respectively, of a semiconductor device incorporating a conventional ESD protection circuit ESDC. In Figure 6, the surge current path in a conventional semiconductor device is schematically shown by thick arrows. The semiconductor device has a wiring structure WS on a semiconductor substrate SS. The semiconductor device also has an ESD protection circuit ESDC positioned adjacent to a pad region PR, which includes a pad BP to which a bonding wire BW is connected, and the pad BP and the ESD protection circuit ESDC are connected via a wiring pattern WP. The ESD protection circuit ESDC includes a PN junction formed in the semiconductor substrate SS.

[0019] Figures 8 and 9 show a cross-sectional view and a plan view of the semiconductor device 1 of this embodiment, in which a varistor V is incorporated, respectively. In Figure 8, the surge current path in the semiconductor device 1 of this embodiment is schematically shown by a thick arrow. The semiconductor device 1 has a wiring structure WS on a semiconductor substrate SS. The wiring structure WS includes a pad region PR including a pad BP and a circuit region CR, and each of the pad region PR and the circuit region CR may include a plurality of wiring layers WL, an interlayer insulating film ILIF disposed between the plurality of wiring layers WL, and via plugs VP that connect the plurality of wiring layers WL to each other. In this embodiment, the varistor V as a protective element is located in the circuit region CR and above the upper surface of the semiconductor substrate SS. On the other hand, conventional protective elements include PN junctions formed on the semiconductor substrate SS. A bonding wire BW may be electrically and physically connected to the upper surface of the pad BP via a bonding ball BB.

[0020] The varistor V may be positioned in the circuit region CR adjacent to the pad region PR. The varistor V may also be electrically connected to the pad BP by a wiring pattern WP. Alternatively, the varistor V may be electrically connected to the pad BP via a resistive element in addition to the wiring pattern WP. As schematically shown in Figure 1, the wiring structure WS of the semiconductor device 1 may have a plurality of pads 16 (including 16-1 and 16-2). The wiring structure WS may, for example, have a pad region PR-1 including a first pad 16-1 and a pad region PR-2 including a second pad 16-2, and the varistor V may be positioned between the first pad region PR-1 and the second pad region PR-2. The circuit region CR may include a transistor Tr positioned below the varistor V. This is advantageous for increasing the circuit size that can be incorporated into the semiconductor device 1.

[0021] As illustrated in Figure 8, the varistor V may have electrodes containing a conductive film located in the furthest wiring layer WLF, which is the furthest from the semiconductor substrate SS among the multiple wiring layers WL. In other words, as illustrated in Figure 8, the varistor V may include electrodes containing a conductive film located in at least two of the multiple wiring layers WL.

[0022] The following describes several embodiments of the varistor V that may be incorporated into the semiconductor device 1. However, these are merely examples, and the varistor V may have other structures.

[0023] Figure 10(a) schematically shows a plan view of the varistor V of the first embodiment. Figure 10(b) schematically shows a cross-sectional view of the varistor V of the first embodiment. The varistor V of the first embodiment may have a resistive film 110, a first electrode 121 positioned in a first region R1 of the main surface 111 (here, the top surface) of the resistive film 110, and a second electrode 122 positioned in a second region R2 of the main surface 111 of the resistive film 110. The second region R2 is separated from the first region R1. The first electrode 121 and the second electrode 122 may consist of a conductive film positioned in one of a plurality of wiring layers WL, for example, the furthest wiring layer WLF, which is furthest from the semiconductor substrate SS. The first electrode 121 and the second electrode 122 may be made of, for example, a metal (e.g., aluminum) or an alloy (e.g., aluminum with tungsten or copper added). The resistive film 110 may be a molybdenum oxide film, but it may also be a film made of other materials. The first electrode 121 and the second electrode 122 may have a circular, elliptical, or rounded shape. Alternatively, the first electrode 121 and the second electrode 122 may have a rectangular shape with rounded corners. Alternatively, the first electrode 121 and the second electrode 122 may have a square or polygonal shape with rounded corners, or they may have other shapes.

[0024] Figure 10(c) schematically shows a cross-sectional view of a modified example of the varistor V of the first embodiment. The modified varistor V of the first embodiment may have a resistive film 110, a first electrode 121 positioned in a first region R1 of the main surface 112 (here, the lower surface) of the resistive film 110, and a second electrode 122 positioned in a second region R2 of the main surface 112 of the resistive film 110. The second region R2 is separated from the first region R1. The first electrode 121 and the second electrode 122 may consist of a conductive film positioned in any one of a plurality of wiring layers WL.

[0025] Figure 11(a) schematically shows a plan view of the varistor V of the second embodiment. Figure 11(b) schematically shows a cross-sectional view of the varistor V of the second embodiment. Matters not mentioned with respect to the varistor V of the second embodiment (including modifications) can be described in the preceding text. The varistor V of the second embodiment may have an interlayer 130 disposed between the main surface 111 of the resistive film 110 and the first electrode 121, and between the main surface 111 of the resistive film 110 and the second electrode 122. The interlayer 130 may be, for example, a silicon film containing impurities (e.g., a polysilicon film or an amorphous silicon film). The interlayer 130 is advantageous in providing ohmic contact between the resistive film 110, which may be composed of a molybdenum oxide film, and the first electrode 121 and the second electrode 122.

[0026] Figure 11(c) schematically shows a cross-sectional view of a modified example of the varistor V of the second embodiment. The modified varistor V of the second embodiment may have an interlayer 130 disposed between the main surface 112 of the resistive film 110 and the first electrode 121, and between the main surface 112 of the resistive film 110 and the second electrode 122. The interlayer 130 may be, for example, a silicon film containing impurities (e.g., a polysilicon film or an amorphous silicon film). The interlayer 130 is advantageous in providing ohmic contact between the resistive film 110, which may be composed of a molybdenum oxide film, and the first electrode 121 and the second electrode 122.

[0027] Figure 12 schematically shows a plan view of the varistor V of the third embodiment. Figure 13(a) schematically shows a cross-sectional view of the varistor V of the third embodiment. Matters not mentioned with respect to the varistor V of the third embodiment (including modifications) can be described in the preceding text. The varistor V of the third embodiment may have a resistive film 110, a first electrode 121 disposed in a first region of the main surface 111 (here, the top surface) of the resistive film 110, and a second electrode 122 disposed in a second region of the main surface 111 of the resistive film 110. In the varistor V of the third embodiment, each of the first electrode 121 and the second electrode 122 includes at least two conductive films 201, 202 disposed in each of at least two wiring layers WL of a plurality of wiring layers WL. The varistor V of the third embodiment may further include a plug VP that electrically connects the at least two conductive films 201, 202. The two conductive films 201, 202 may include a first conductive film 201 containing a first pattern P1 and a second conductive film 202 containing a plurality of second conductive patterns P2 smaller than the first pattern P1. Such a configuration is advantageous for adjusting the varistor voltage of the varistor V. The varistor voltage can be adjusted, for example, by adjusting the area of ​​the second conductive patterns P2.

[0028] Figure 13(b) schematically shows a cross-sectional view of a modified example of the varistor V of the third embodiment. The modified example of the varistor V of the third embodiment may have a resistive film 110, a first electrode 121 positioned in a first region of the main surface 112 (here, the lower surface) of the resistive film 110, and a second electrode 122 positioned in a second region of the main surface 112 of the resistive film 110.

[0029] Figure 14 schematically shows a plan view of the varistor V of the fourth embodiment. Figure 15(a) schematically shows a cross-sectional view of the varistor V of the fourth embodiment. Matters not mentioned with respect to the varistor V of the fourth embodiment (including modifications) can be described in the preceding explanation. The varistor V of the fourth embodiment may have an interlayer 130 disposed between the main surface 111 (here, the top surface) of the resistive film 110 and the first electrode 121, and between the main surface 111 of the resistive film 110 and the second electrode 122.

[0030] Figure 15(b) schematically shows a cross-sectional view of a modified example of the varistor V of the fourth embodiment. The modified varistor V of the second embodiment may have an interlayer 130 disposed between the main surface 112 (here, the bottom surface) of the resistive film 110 and the first electrode 121, and between the resistive film 110 and the second electrode 122.

[0031] Figure 16(a) schematically shows a plan view of the varistor V of the fifth embodiment. Figure 16(b) schematically shows a cross-sectional view of the varistor V of the fifth embodiment. Matters not mentioned with respect to the varistor V of the fifth embodiment (including modifications) can be described in the preceding explanation. The varistor V of the fifth embodiment may have a first electrode 121, a resistive film 110 disposed on the first electrode 121, and a second electrode 122 disposed on the resistive film 110. In other words, the varistor V of the fifth embodiment may have a first electrode 121 disposed on one main surface 112 side of the resistive film 110 and a second electrode 122 disposed on the other main surface 111 side of the resistive film 110. In the first to fourth embodiments, the current path is formed so that the current flows in the direction along the main surface of the resistive film 110, whereas in the fifth embodiment, the current path is formed so that the current flows in the thickness direction of the resistive film 110. The second electrode 122 may consist of a conductive film located on one of the multiple wiring layers WL, for example, the furthest wiring layer WLF, which is furthest from the semiconductor substrate SS. The first electrode 121 may consist of a conductive film located on one of the multiple wiring layers WL. The first electrode 121 and the second electrode 122 may be made of a metal (e.g., aluminum) or an alloy (e.g., aluminum with tungsten or copper added).

[0032] Figure 16(c) schematically shows a cross-sectional view of a modified example of the varistor V of the fifth embodiment. The modified varistor V of the fifth embodiment may have an interlayer 130 disposed between the resistive film 110 and the first electrode 121, and between the resistive film 110 and the second electrode 122.

[0033] Figure 17 schematically shows a plan view of the varistor V of the sixth embodiment. Figure 18(a) schematically shows a cross-sectional view of the varistor V of the sixth embodiment. Matters not mentioned with respect to the varistor V of the sixth embodiment (including modifications) can be described in the preceding text. The varistor V of the sixth embodiment may have a first electrode 121, a resistive film 110 disposed on the first electrode 121, and a second electrode 122 disposed on the resistive film 110. In the varistor V of the sixth embodiment, the first electrode 121 includes at least two conductive films 201a, 202a disposed on at least two wiring layers WL of a plurality of wiring layers WL. In addition, the varistor V of the sixth embodiment has a second electrode 122 including at least two conductive films 201b, 202b disposed on at least two wiring layers WL of a plurality of wiring layers WL. Furthermore, the varistor V of the sixth embodiment may further include a plug VP for electrically connecting at least two conductive films 201a, 202a, and a plug VP for electrically connecting at least two conductive films 201b, 202b.

[0034] At least two conductive films 201a, 202a may include a first conductive film 201a containing a first pattern P1a and a second conductive film 202a containing a plurality of second conductive patterns P2a smaller than the first pattern P1a. At least two conductive films 201b, 202b may include a first conductive film 201b containing a first pattern P1b and a second conductive film 202b containing a plurality of second conductive patterns P2b smaller than the first pattern P1b. Such a configuration is advantageous for adjusting the varistor voltage of a varistor V. The varistor voltage can be adjusted, for example, by adjusting the area of ​​the second conductive pattern P2.

[0035] Figure 15(b) schematically shows a cross-sectional view of a modified example of the varistor V of the sixth embodiment. The modified varistor V of the second embodiment may have an interlayer 130 positioned between one main surface 112 (here, the bottom surface) of the resistive film 110 and the first electrode 121, and between the other main surface 112 (here, the top surface) of the resistive film 110 and the second electrode 122.

[0036] Figure 19 shows an example configuration of an electronic device 1100 as an application example of the semiconductor device 1 described above. The electronic device 1100 may be, for example, a computer, an information terminal, a communication terminal, a camera, a signal processing device, a vehicle control device, a flight control device, etc., or a composite of at least two of these electronic devices. The electronic device 1100 includes a plurality of semiconductor devices 1101, 1102, 1103, which may be arranged on one or more printed circuit boards (PCBs). At least one of the plurality of semiconductor devices 1101, 1102, 1103 may incorporate a varistor V, as in the semiconductor device 1 described above. The electronic device 1100 may also include one or more varistors Ve arranged outside the plurality of semiconductor devices 1101, 1102, 1103. The varistors Ve may have the configuration described as any of the first to sixth embodiments. The varistors Ve may be arranged between two or more signal lines 1112 in the electronic device 1100. Two or more such signal lines 1112 may be located adjacent to each other, or they may be located via other signal lines 1112. The varistor Ve may be located between the signal line 1112 and the power line. The varistor Ve may be located between the signal line 1112 and the ground line. The varistor Ve may be electrically connected to a pad or terminal 1111.

[0037] The invention is not limited to the embodiments described above, and various modifications and changes are possible within the scope of the gist of the invention. [Explanation of Symbols]

[0038]

Claims

1. A semiconductor device comprising a semiconductor substrate, a wiring structure disposed on the semiconductor substrate, and a varistor, The wiring structure includes a pad region including a pad and a circuit region, each of the pad region and the circuit region including a plurality of wiring layers, interlayer insulating films disposed between the plurality of wiring layers, and via plugs connecting the plurality of wiring layers to each other. The varistor is electrically connected to the pad, The varistor is located in the circuit region and above the upper surface of the semiconductor substrate. A semiconductor device characterized by the following features.

2. The varistor is positioned in the circuit region adjacent to the pad region. The semiconductor device according to feature 1.

3. The varistor is electrically connected to the pad by a wiring pattern. The semiconductor device according to feature 1.

4. The varistor is electrically connected to the pad via a wiring pattern and a resistive element. The semiconductor device according to feature 1.

5. The wiring structure further comprises a second pad region including a second pad, The varistor is positioned between the pad region and the second pad region. The semiconductor device according to feature 1.

6. The varistor has a molybdenum oxide film as a resistive film. The semiconductor device according to feature 1.

7. The varistor has an electrode that includes a conductive film located in the furthest wiring layer, which is the furthest from the semiconductor substrate among the plurality of wiring layers. The semiconductor device according to feature 1.

8. The varistor includes electrodes that include a conductive film disposed in each of at least two of the plurality of wiring layers. The semiconductor device according to feature 1.

9. The varistor comprises a resistive film, a first electrode positioned in a first region of the main surface of the resistive film, and a second electrode positioned in a second region of the main surface of the resistive film, wherein the second region is separated from the first region. The semiconductor device according to feature 1.

10. Each of the first electrode and the second electrode includes at least two conductive films disposed on each of at least two of the plurality of wiring layers, The semiconductor device according to feature 9.

11. The varistor further includes a plug that electrically connects the at least two conductive films. The semiconductor device according to feature 10.

12. The at least two conductive films include a first conductive film containing a first pattern and a second conductive film containing a plurality of second conductive patterns smaller than the first pattern. The semiconductor device according to feature 11.

13. The varistor further comprises an interlayer disposed between the resistive film and the first electrode, and between the resistive film and the second electrode. The semiconductor device according to feature 9.

14. The varistor includes a first electrode, a resistive film disposed on the first electrode, and a second electrode disposed on the resistive film. The semiconductor device according to feature 1.

15. Each of the first electrode and the second electrode includes at least two conductive films disposed on each of at least two of the plurality of wiring layers, The semiconductor device according to feature 14.

16. The varistor further includes a plug that electrically connects the at least two conductive films. The semiconductor device according to feature 15.

17. The at least two conductive films include a first conductive film containing a first pattern and a second conductive film containing a plurality of second conductive patterns smaller than the first pattern. The semiconductor device according to feature 16.

18. The varistor further comprises an interlayer disposed between the resistive film and the first electrode, and between the resistive film and the second electrode. The semiconductor device according to feature 14.

19. The circuit region includes a transistor located below the varistor. The semiconductor device according to any one of claims 1 to 18.

20. An electronic device characterized by comprising a semiconductor device according to any one of claims 1 to 18.

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