Semiconductor devices, imaging systems, and mobile devices

Abstract

This suppresses the increase in wiring required in the pixel section to detect counter failures. [Solution] The semiconductor device according to the present disclosure includes a pixel unit including a conversion unit that converts a pixel signal into a conversion signal and a holding unit that holds the conversion signal, a drive unit that generates a drive signal indicating whether or not to allow the holding unit to hold the conversion signal, and a test unit that generates a test signal for inspecting the holding unit, wherein in a first operating mode, the drive unit outputs the drive signal to the pixel unit via wiring to the pixel unit, and the holding unit holds and outputs the conversion signal based on the drive signal, and in a second operating mode, the test unit outputs the test signal to the pixel unit via the wiring, and the holding unit holds and outputs the test signal.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device, an imaging system, and a moving body.

Background Art

[0002] Patent Document 1 discloses an optical element that outputs a test signal to detect a failure of a counter that counts photons incident on a pixel unit.

Prior Art Document

Patent Document

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In Patent Document 1, additional wiring is required to detect a failure of the counter.

[0005] The present disclosure has been made in view of the above problems, and provides a semiconductor device in which an increase in wiring provided in a pixel unit for detecting a failure of a counter is suppressed.

Means for Solving the Problems

[0006] A semiconductor device according to an aspect of the present disclosure includes a pixel unit including a conversion unit that converts a pixel signal into a conversion signal and a holding unit that holds the conversion signal, a driving unit that generates a driving signal indicating whether to hold the conversion signal in the holding unit, and a test unit that generates a test signal for inspecting the holding unit. In a first operation mode, the driving unit outputs the driving signal to the pixel unit via wiring to the pixel unit, and the holding unit holds and outputs the conversion signal based on the driving signal. In a second operation mode, the test unit outputs the test signal to the pixel unit via the wiring, and the holding unit holds and outputs the test signal. [Effects of the Invention]

[0007] According to this disclosure, when detecting a failure in a counter included in a semiconductor device, it is possible to suppress an increase in the number of wirings within the pixel. [Brief explanation of the drawing]

[0008] [Figure 1] This is a schematic diagram of the semiconductor device in the first embodiment. [Figure 2] This figure shows an example of the arrangement of the sensor substrate in the first embodiment. [Figure 3] This is a block diagram showing an example of circuit board arrangement in the first embodiment. [Figure 4] This is a circuit diagram of the APD and pulse generation unit in the first embodiment. [Figure 5] This figure shows the relationship between the operation of the APD and the output signal in the first embodiment. [Figure 6] This is a block diagram showing the schematic configuration of a semiconductor device in the first embodiment. [Figure 7] This is a block diagram showing the signal flow within the semiconductor device in the first embodiment. [Figure 8] This is a block diagram showing the configuration of the pixel section and the signal flow between the pixel section and the peripheral section in the first embodiment. [Figure 9] This is a block diagram showing the signal flow within a semiconductor device in the second embodiment. [Figure 10] This is a block diagram showing the configuration of the pixel section and the signal flow between the pixel section and the peripheral section in the second embodiment. [Figure 11] This is a block diagram showing the signal flow within a semiconductor device in the third embodiment. [Figure 12] This is a block diagram showing two pixel portions in a semiconductor device according to the fourth embodiment. [Figure 13] This is a block diagram showing the signal flow within the semiconductor device in the fourth embodiment. [Figure 14]It is a block diagram showing the signal flow in the semiconductor device in the fifth embodiment. [Figure 15] It is a block diagram showing two pixel portions in the semiconductor device in the sixth embodiment. [Figure 16] It is a block diagram showing the signal flow in the semiconductor device in the sixth embodiment. [Figure 17] It is a block diagram showing the signal flow in the semiconductor device in a modified example of the sixth embodiment. [Figure 18] It is a block diagram showing the signal flow in the semiconductor device in the seventh embodiment. [Figure 19] It is a block diagram showing the signal flow in the semiconductor device in the eighth embodiment. [Figure 20] It is a block diagram of the imaging system in the ninth embodiment. [Figure 21] It is a block diagram of the light detection system in the tenth embodiment. [Figure 22] It is a schematic diagram of the endoscopic surgery system in the eleventh embodiment. [Figure 23A] It is a schematic diagram of the light detection system in the twelfth embodiment. [Figure 23B] It is a schematic diagram of the moving body in the twelfth embodiment. [Figure 24] It is a flowchart showing the operation of the light detection system in the twelfth embodiment. [Figure 25] It is a diagram showing a specific example of an electronic device in the thirteenth embodiment.

Embodiments for Carrying Out the Invention

[0009] Hereinafter, embodiments of the present invention will be described with reference to the drawings. The same elements or corresponding elements throughout the plurality of drawings are denoted by common reference numerals, and the description thereof may be omitted or simplified.

[0010] [First Embodiment] The semiconductor device according to this embodiment has a circuit board including various circuits and wiring for signal processing. The semiconductor device according to this embodiment may further include a sensor board electrically connected to the circuit board. The sensor board has SPAD pixels including avalanche photodiodes (hereinafter referred to as "APDs"). The semiconductor device according to this embodiment, including the circuit board, can operate as a signal processing device for imaging data. Furthermore, the semiconductor device according to this embodiment, including the circuit board and the sensor board, can operate as a photoelectric converter.

[0011] The configuration of the semiconductor device in this embodiment will be explained using Figures 1 to 4. Figure 1 is a schematic diagram of a semiconductor device operating as a photoelectric converter, showing the configuration of a stacked type photoelectric converter 100. The photoelectric converter 100 includes a sensor substrate 1 and a circuit board 2 stacked on top of each other, and the sensor substrate 1 and the circuit board 2 are electrically connected to each other. The photoelectric converter in this embodiment is a back-illuminated type photoelectric converter in which light is incident from the first surface of the sensor substrate 1 and the circuit board 2 is arranged on the second surface of the sensor substrate 1.

[0012] In the following description, the sensor substrate 1 and the circuit board 2 may be, but are not limited to, diced chips. For example, each substrate may be a wafer. Furthermore, each substrate may be stacked in a wafer state and then diced, or it may be made into chips and then stacked and bonded together. The sensor substrate 1 has a pixel region 1a, and the circuit board 2 has a circuit region 2a that processes the signals detected by the pixel region 1a.

[0013] Figure 2 shows an example of the arrangement of the sensor substrate 1. Multiple pixels 10 each contain an APD 11 and are arranged in a two-dimensional array in a planar view, forming a pixel region 1a.

[0014] Pixel 10 is typically a pixel used to form an image, but when used in TOF (Time of Flight), it is not necessarily required to form an image. In other words, pixel 10 may be a pixel used to measure the time and amount of light that arrives.

[0015] Figure 3 shows an example of the arrangement of the circuit board 2. The circuit board 2 has a signal processing unit 20, a vertical scanning circuit 21, a readout circuit 23, a horizontal scanning circuit 27, an output calculation unit 24, a control pulse generation circuit 25, scan lines 26, and signal lines 29. In a plan view, the circuit area 2a is arranged in the area that overlaps with the pixel area 1a in Figure 2. Furthermore, in a plan view, the vertical scanning circuit 21, readout circuit 23, horizontal scanning circuit 27, output calculation unit 24, and control pulse generation circuit 25 are arranged so as to overlap with the area between the edge of the sensor board 1 in Figure 2 and the edge of the pixel area 1a. In other words, the sensor board 1 has a pixel area 1a and a non-pixel area arranged around the pixel area 1a, and the vertical scanning circuit 21, readout circuit 23, horizontal scanning circuit 27, output calculation unit 24, and control pulse generation circuit 25 are arranged in the area that overlaps with the non-pixel area in a plan view.

[0016] The signal processing unit 20 is electrically connected to the pixels 10 via connecting wiring provided for each pixel 10, and is arranged in a two-dimensional array in a planar view, similar to the pixels 10. The signal processing unit 20 includes a binary counter that counts the photons incident on the pixels 10.

[0017] The vertical scanning circuit 21 receives control pulses supplied from the control pulse generation circuit 25 and supplies control pulses to the signal processing unit 20 corresponding to the pixels 10 of each row via the scan line 26. The vertical scanning circuit 21 may be composed of logic circuits such as a shift register and an address decoder.

[0018] The readout circuit 23 acquires the pulse count value of the digital signal from the signal processing unit 20 of each row via the signal line 29. Then, it outputs the output signal to an external signal processing circuit (signal processing unit) of the photoelectric converter 100 via the output calculation unit 24. The readout circuit 23 may also have the function of a signal processing circuit that performs correction of the count value. The horizontal scanning circuit 27 receives control pulses from the control pulse generation circuit 25 and sequentially outputs the count value of each column in the readout circuit 23 to the output calculation unit 24. As will be described later, if the pulse count value exceeds the threshold, the output calculation unit 24 estimates the actual image signal (pulse count value) based on the time count value and threshold included in the additional information and replaces the pulse count value with the estimated pulse count value (extrapolation). On the other hand, if the pulse count value is below the threshold, the pulse count value is output as is as the image signal.

[0019] The output calculation unit 24 performs predetermined processing on the pulse count value read by the readout circuit 23 and outputs the image signal to the outside. Furthermore, as will be described later, the output calculation unit 24 can perform processing such as calculation of the pulse count value when the pulse count value exceeds a threshold.

[0020] In Figure 2, the arrangement of photoelectric conversion elements in the pixel region 1a may be arranged in a one-dimensional manner. Furthermore, the effects of the present invention can be achieved even in a configuration with only one pixel 10, and a configuration with one pixel 10 can also be included in the present invention. In a photoelectric conversion device having multiple pixels 10, the effect of suppressing the circuit size according to this embodiment becomes even more pronounced. The signal processing unit 20 does not necessarily need to be provided for each pixel 10; for example, one signal processing unit 20 may be shared by multiple pixels 10, and signal processing may be performed sequentially.

[0021] Figure 4 is a block diagram of the APD and pulse generation unit in this embodiment. Figure 4 shows the pixel 10 of the sensor substrate 1 and the pulse generation unit 22 in the signal processing unit 20 of the circuit board 2. An APD 11 is placed on the pixel 10. The pulse generation unit 22 includes a quench element 221, a waveform shaping unit 222, a counter circuit 223, and a selection circuit 224.

[0022] The APD11 generates charge pairs corresponding to incident light through photoelectric conversion. A voltage VL (first voltage) is supplied to the anode of the APD11. In addition, a voltage VH (second voltage), which is higher than the voltage VL supplied to the anode, is supplied to the cathode of the APD11. A reverse bias voltage is applied to the anode and cathode, making the APD11 capable of avalanche multiplication. When a photon is incident on the APD11 under the reverse bias voltage, the charge generated by the photon undergoes avalanche multiplication, and an avalanche current is generated.

[0023] Depending on the reverse bias voltage, the APD11 can operate in Geiger mode or linear mode. Geiger mode is operation when the potential difference between the anode and cathode is greater than the breakdown voltage, while linear mode is operation when the potential difference between the anode and cathode is near or below the breakdown voltage. An APD operating in Geiger mode is specifically called a SPAD or SPAD type. For example, the voltage VL (first voltage) may be -30V and the voltage VH (second voltage) may be 1V. The APD11 may operate in linear mode or in Geiger mode. When the APD11 operates as a SPAD, the potential difference becomes larger compared to the linear mode APD11, and the voltage withstand effect becomes more pronounced, so it is preferable for the APD11 to operate as a SPAD.

[0024] The quench element 221 is placed between the power line supplying voltage VH and the cathode of the APD11. The quench element 221 functions as a load circuit (quench circuit) during signal multiplication by avalanche multiplication, suppressing the voltage supplied to the APD11 and thereby suppressing avalanche multiplication (quench operation). In addition, the quench element 221 also works to restore the voltage supplied to the APD11 to voltage VH by flowing current to compensate for the voltage drop caused by the quench operation (recharge operation).

[0025] The waveform shaping unit 222 functions as a signal generation unit that generates a detection pulse based on the output generated by the incidence of photons. That is, the waveform shaping unit 222 shapes the potential change of the cathode of the APD 11 obtained when a photon is detected and outputs a rectangular wave pulse signal (detection pulse). For example, an inverter circuit can be used as the waveform shaping unit 222. Figure 4 shows an example in which one inverter is used as the waveform shaping unit 222, but a circuit in which multiple inverters are connected in series may be used. In addition, other circuits that have a waveform shaping effect may be used.

[0026] The counter circuit 223 counts the pulse signals output from the waveform shaping unit 222 and holds the count value. The counter circuit 223 is also supplied with control pulses from the vertical scanning circuit 21 in Figure 3 via the drive line 226 of the scan line 26. When the control pulse becomes active, the signal held by the counter circuit 223 is reset.

[0027] The selection circuit 224 includes a switch circuit, a buffer circuit for outputting signals, and the like. The selection circuit 224 is supplied with control pulses from the vertical scanning circuit 21 in Figure 3 via the drive line 227. In response to the control pulses, the selection circuit 224 switches the electrical connection between the counter circuit 223 and the signal line 219.

[0028] Furthermore, switches such as transistors may be provided between the quench element 221 and the APD11, and between the APD11 and the signal processing unit 20. In addition, the supply of voltage VH or voltage VL may be electrically switched by switches such as transistors.

[0029] As described above, a counter circuit 223 is used in this embodiment. However, instead of the counter circuit 223, a Time to Digital Converter (TDC) and memory may be used to acquire the pulse detection timing. In this case, the generation timing of the pulse signal output from the waveform shaping unit 222 is converted into a digital signal by the TDC. A control pulse pREF (reference signal) is supplied to the TDC via a drive line from the vertical scanning circuit 21 in Figure 3 for measuring the timing of the pulse signal. The TDC uses the control pulse pREF as a reference and acquires the signal as a digital signal when the input timing of the signal output from each pixel via the waveform shaping unit 222 is considered as a relative time.

[0030] Figure 5 shows the relationship between the operation of the APD and the output signal in this embodiment. Figure 5(a) is an excerpt of the APD11, quench element 221, and waveform shaping unit 222 from Figure 4. When the input side of the waveform shaping unit 222 is nodeA and the output side is nodeB, Figure 5(b) shows the waveform change of nodeA, and Figure 5(c) shows the waveform change of nodeB.

[0031] Between times t0 and t1, a reverse bias voltage of VH-VL is applied to APD11. When a photon is incident on APD11 at time t1, avalanche multiplication occurs in APD11, an avalanche multiplication current flows through the quench element 221, and the voltage at nodeA drops. As the voltage drop increases further and the potential difference applied to APD11 decreases, the avalanche multiplication of APD11 stops at time t3, and the voltage level at nodeA stops dropping below a certain value. Subsequently, between times t3 and t5, a current flows from voltage VL to nodeA to compensate for the voltage drop, and at time t5, nodeA settles to its original voltage level. At this time, between times t2 and t4, when the voltage level at nodeA falls below the threshold of the waveform shaping unit 222, nodeB becomes high level. In other words, the voltage waveform of nodeA is shaped by the waveform shaping unit 222, and a square wave pulse signal is output from nodeB.

[0032] The configuration of the semiconductor device in this embodiment will be described in more detail with reference to Figures 6 to 8. Figure 6 is a block diagram showing the schematic configuration of a semiconductor device operating as a photoelectric converter. The photoelectric converter 100 includes a signal processing board 30 and a light receiving board 40 stacked with the signal processing board 30. The semiconductor device according to this disclosure may refer to the signal processing board 30, or it may refer to a photoelectric converter in which the signal processing board 30 and the light receiving board 40 are stacked. The signal processing board 30 corresponds to the circuit board 2 in Figure 1, and the light receiving board 40 corresponds to the sensor board 1 in Figure 1. The signal processing board 30 includes a pixel area 31 and a peripheral area 32.

[0033] Multiple pixel units 310 are arranged in a matrix within the pixel region 31. Each pixel unit 310 includes pixel units 310a and 310b that are adjacent to each other in the row direction. Each pixel unit 310 holds the input signal. The detailed configuration of the pixel units 310 will be described later.

[0034] The peripheral region 32 contains a drive unit 321, a test unit 322, a vertical control unit 323, and a signal processing unit 324. The drive unit 321 supplies a drive signal to each pixel unit 310. The drive signal is transmitted when the photoelectric converter 100 is operated as an imaging device (during imaging operation). The test unit 322 supplies a test signal to each pixel unit 310. The test unit 322 also supplies an expectation signal to the determination unit. The test signal and expectation signal are transmitted when inspecting the pixel unit 310 (during test operation). The specific configurations of the drive unit 321, test unit 322, and determination unit will be described later. The vertical control unit 323 and the horizontal control circuit (not shown) select a pixel unit 310 and input a drive signal or a test signal to the selected pixel unit 310. The vertical control unit 323 and the horizontal control circuit also cause the signal held by the selected pixel unit 310 to be output to the signal processing unit 324. The signal processing unit 324 receives the signal output from the pixel unit 310. The signal processing unit 324 performs predetermined processing on the input signal and outputs the processed signal to the outside of the signal processing board 30. Hereinafter, the multiple units, circuits, etc. arranged in the peripheral region 32 will be collectively referred to as the peripheral region. Furthermore, operating the photoelectric converter 100 as an imaging device may be referred to as the first operating mode, and inspecting the pixel section 310 may be referred to as the second operating mode.

[0035] The light-receiving substrate 40 includes a plurality of photoelectric conversion elements 401 arranged in a matrix. The photoelectric conversion elements 401 generate an electrical signal in response to the incidence of photons and output the generated electrical signal to the pixel section 310. In this embodiment, the photoelectric conversion elements 401 include single-photon avalanche diodes (SPADs). The electrical signal generated by the photoelectric conversion elements 401 corresponds to a pixel signal indicating the number of photons incident on the photoelectric conversion elements 401.

[0036] The operation of the photoelectric converter 100, which operates as an imaging device, will be explained with reference to Figure 7. Figure 7 is a block diagram showing the signal flow within the photoelectric converter 100 in this embodiment. In Figure 7, one pixel section 310 is shown among a plurality of pixel sections arranged in a matrix in the pixel region 31. The pixel section 310 includes a conversion section 311, a selection section 312, and a holding section 313.

[0037] During imaging, the conversion unit 311 receives a pixel signal s401 from the photoelectric conversion element 401. The conversion unit 311 converts the pixel signal s401 into a pulsed conversion signal s311. The conversion unit 311 is connected to the selection unit 312. The conversion unit 311 outputs the conversion signal s311 to the selection unit 312.

[0038] The selection unit 312 is a logical OR (OR) circuit. The selection unit 312 receives a conversion signal s311 from the conversion unit 311. In addition, during imaging, the selection unit 312 receives a low-level drive signal s321 as a selection signal s325, which will be described later. The selection unit 312 is connected to the holding unit 313. Based on the low-level drive signal s321, the selection unit 312 outputs the conversion signal s311 as a selection signal s312 to the holding unit 313.

[0039] The holding unit 313 holds the selection signal s312 corresponding to the conversion signal s311 received from the selection unit 312. Specifically, the holding unit 313 includes a counter that counts the conversion signal s311. The counter in the holding unit 313 counts the number of pulses contained in the selection signal s312 (i.e., the conversion signal s311). The number of pulses corresponds to the number of photons incident on the photoelectric conversion element 401. The holding unit 313 holds the counted number of pulses as the holding signal s313. The holding unit 313 outputs the holding signal s313 to the signal processing unit 324. The signal processing unit 324 performs predetermined processing on the holding signal s313, such as correction of the imaging data and data compression. The number of signal lines for outputting the holding signal s313 to the signal processing unit 324 may be multiple, depending on the number of bits of the signal held in the holding unit 313.

[0040] A selection unit 325 (switching unit) is located in the peripheral region 32. The selection unit 325 selectively connects the common wiring 331 to either the drive unit 321 or the test unit 322 in response to a control signal from the test unit 322. The selection unit 325 selectively outputs the drive signal s321 or the test signal s322T as a selection signal s325 to the selection unit 312 via the common wiring 331. The selection unit 325 is connected to both the drive unit 321 and the test unit 322. The selection unit 325 receives the drive signal s321 from the drive unit 321. The selection unit 325 also receives the test signal s322T from the test unit 322. During imaging, the selection unit 325 connects the common wiring 331 to the drive unit 321 in response to a control signal from the test unit 322. The selection unit 325 outputs the selected drive signal s321 as a selection signal s325 to the selection unit 312 via the common wiring 331. The control signal input to the selection unit 325 may be supplied by a control unit separate from the test unit 322.

[0041] Furthermore, during imaging, the operation of the holding unit 313 can be stopped by inputting a high-level drive signal s321 as a selection signal s325 to the selection unit 312. That is, since the selection unit 312 continues to output a high-level selection signal s312 to the holding unit 313 based on the high-level drive signal s321, the holding unit 313 does not perform counting operations. For example, the counting operation of the holding unit 313 of a pixel unit 310 located in a specific area where imaging is not performed can be stopped based on the drive signal s321, thereby reducing the power consumption of the photoelectric converter 100. The drive signal s321 corresponds to a control signal that instructs the pixel unit 310 whether or not to have the holding unit 313 hold the conversion signal s311 output from the conversion unit 311 during imaging.

[0042] The operation of the photoelectric converter 100 when inspecting the holding part 313 will be explained with reference to Figure 7. Hereinafter, the inspection of the holding part 313 will be referred to as the test operation.

[0043] During test operation, the conversion unit 311 receives a high-level pixel signal s401 from the photoelectric conversion element 401. The pixel signal s401 is fixed at a high level during test operation. The pixel signal s401 during test operation will be described later. The conversion unit 311 converts the pixel signal s401 into a conversion signal s311. The conversion signal s311 is fixed at a low level during test operation. The conversion unit 311 outputs the low-level conversion signal s311 to the selection unit 312.

[0044] During test operation, the selection unit 325 connects the common wiring 331 to the test unit 322 in response to a control signal from the test unit 322. The selection unit 325 selects the test signal s322T as the selection signal s325. The selection unit 325 outputs the test signal s322T as the selection signal s325 to the selection unit 312 via the common wiring 331. The test signal s322T has a pulsed waveform. Note that the control signal input to the selection unit 325 may be supplied by a control unit other than the test unit 322.

[0045] During test operation, a low-level conversion signal s311 is input to the selection unit 312. Therefore, the selection unit 312 outputs the test signal s322T received from the test unit 322 via the common wiring 331 to the holding unit 313 as the selection signal s312.

[0046] The holding unit 313 holds the selection signal s312 corresponding to the test signal s322T received from the selection unit 312. The holding unit 313 counts the number of pulses contained in the selection signal s312 (i.e., the test signal s322T). The number of pulses corresponds to the value indicated by the expected signal s322E output from the test unit 322 to the determination unit 601. The holding unit 313 holds the counted number of pulses as the holding signal s313. The holding unit 313 outputs the holding signal s313 to the determination unit 601.

[0047] The determination unit 601 receives a holding signal s313 from the holding unit 313 that corresponds to the number of pulses of the test signal s322T. The determination unit 601 also receives an expectation signal s322E from the test unit 322. The determination unit 601 compares the holding signal s313 and the expectation signal s322E. If the holding signal s313 and the expectation signal s322E show the same value, the determination unit 601 determines that the holding unit 313 is operating normally. If the holding signal s313 and the expectation signal s322E show different values, the determination unit 601 determines that the holding unit 313 is not operating normally or that the holding unit 313 is malfunctioning. The determination unit 601 determines the operation of the holding unit 313 for each of the pixel units 310 arranged in the pixel area 31. The determination unit 601 outputs a determination signal s601 to the storage unit 602 indicating the result of the determination for each of the pixel units 310. The memory unit 602 stores the result of the determination for each pixel unit 310, associating it with the coordinates of the corresponding pixel unit 310. The hold signal s313 output from a pixel unit 310 that is not functioning properly during imaging is corrected by the signal processing unit 324 based on the determination result stored in the memory unit 602. The determination unit 601 and the memory unit 602 may be located in the peripheral area 32, or they may be located outside the photoelectric converter 100.

[0048] The operation of the pixel unit 310 during imaging and test operations will be explained with reference to Figure 8. Figure 8 is a block diagram showing the circuit configuration of the pixel unit 310 and the signal flow between the pixel unit 310 and the peripheral part in the first embodiment.

[0049] The photoelectric conversion element 401 includes a SPAD. The pixel unit 310 includes a conversion unit 311, a selection unit 312, a holding unit 313, and a quench element 314. In this embodiment, the conversion unit 311 is a NOT gate circuit. The conversion unit 311 generates a conversion signal s311 by inverting the voltage level of node N connected to the cathode of the photoelectric conversion element 401. The conversion unit 311 is connected to the selection unit 312. The conversion unit 311 outputs the generated conversion signal s311 to the selection unit 312. The conversion unit 311 is also connected to the quench element 314 and the cathode of the photoelectric conversion element 401 via node N. A voltage VH is applied to the quench element 314. A voltage VL, lower than voltage VH, is applied to the anode of the photoelectric conversion element 401.

[0050] The operation of the photoelectric converter 100 according to this embodiment during imaging will be described below. The selection unit 325 selects the drive signal s321 generated by the drive unit 321. The selection unit 325 outputs the selected drive signal s321 as a selection signal s325 to the selection unit 316 via the common wiring 331. The selection unit 316 receives the low-level drive signal s321 as a selection signal s325.

[0051] The conversion unit 311 receives a pixel signal s401 generated according to the number of incident photons from the photoelectric conversion element 401. The conversion unit 311 inverts the voltage level of the pixel signal s401 to generate a conversion signal s311. The conversion unit 311 outputs the generated conversion signal s311 to the selection unit 312.

[0052] The selection unit 312 receives a selection signal s325 and a conversion signal s311 corresponding to a low-level drive signal s321. Based on the low-level drive signal s321, the selection unit 312 outputs the conversion signal s311 as a selection signal s312 to the holding unit 313. The holding unit 313 receives the conversion signal s311 corresponding to the pixel signal s401 as a selection signal s312. Based on the conversion signal s311, the holding unit 313 counts the photons incident on the photoelectric conversion element 401 and holds the number of counted photons. The holding unit 313 outputs a holding signal s313 corresponding to the number of counted photons to the signal processing unit 324.

[0053] The operation of the photoelectric converter 100 according to this embodiment during test operation will be described below. The selection unit 325 selects the test signal s322T generated by the test unit 322. The selection unit 312 is connected to the peripheral unit via a common wiring 331. The selection unit 325 outputs the selected test signal s322T as a selection signal s325 to the selection unit 312 via the common wiring 331.

[0054] The selection unit 312 receives a selection signal s325 corresponding to the test signal s322T and a conversion signal s311 fixed at a low level. During the manufacturing of the photoelectric converter 100, the photoelectric conversion element 401 is not electrically connected to node N before the signal processing board 30 as a semiconductor device is electrically connected to the light receiving board 40. That is, the signal processing board 30 as a semiconductor device does not have a photoelectric conversion element 401, and the voltage signal at node N is fixed at a high level. The voltage signal fixed at a high level is converted by the conversion unit 311 to a conversion signal s311 fixed at a low level. The conversion unit 311 outputs the conversion signal s311 fixed at a low level to the selection unit 312. The selection unit 312 outputs a selection signal s325 corresponding to the test signal s322T based on the low-level conversion signal s311 to the holding unit 313 as the selection signal s312. The holding unit 313 holds the selection signal s325 output from the selection unit 312 as a holding signal s313. The holding unit 313 outputs a holding signal s313 corresponding to the test signal s322T to the determination unit 601. The determination unit 601 determines whether the holding unit 313 is operating normally based on the holding signal s313 and the expectation signal s322E.

[0055] After the signal processing board 30 is electrically connected to the light receiving board 40, for example, the photoelectric conversion element 401 is shielded to create a state in which no photons are incident on the photoelectric conversion element 401. In the shielded state, the photoelectric conversion element 401 does not perform avalanche multiplication. Therefore, the voltage signal at node N is maintained at a high level, and the conversion signal s311 is fixed at a low level. In other words, even after the signal processing board 30 and the light receiving board 40 are electrically connected, the holding unit 313 can be inspected based on the test signal s322T and the expected signal s322E by creating a shielded state for the photoelectric conversion element 401.

[0056] In imaging devices, a counter is provided for each pixel to count the incident photons and store the counted number. If the counter is not functioning correctly, it cannot accurately store the number of photons incident on the photoelectric converter. Therefore, a pixel containing a counter that is not functioning correctly cannot output an accurate signal. Consequently, a configuration for detecting whether the counter is functioning correctly is necessary for the photoelectric converter to operate properly. In conventional technology, multiple wires were required for each pixel to select the signal to be stored in the counter and to transmit signals used to detect counter failures.

[0057] On the other hand, in order to achieve miniaturization of pixels in the imaging device and higher gradation of captured images, it is necessary to reduce the placement area of ​​the counter and increase the number of bits in the counter. In order to increase the number of bits in the counter while suppressing the increase in placement area, it is necessary to reduce the number of wires provided in each pixel for counter inspection.

[0058] According to this embodiment, the control signal (drive signal) for holding the pixel signal from the photoelectric conversion element in the counter and the test signal for inspecting the counter are transmitted to each pixel using common wiring. Therefore, the semiconductor device according to this embodiment can suppress the increase in wiring provided to each pixel for inspecting the counter, and can achieve miniaturization of pixels in the imaging device and high-gradation imaging of the captured image.

[0059] [Second Embodiment] The semiconductor device operating as a photoelectric converter according to the second embodiment of this disclosure will be described with reference to Figures 9 and 10, focusing on the differences from the first embodiment.

[0060] Figure 9 is a block diagram showing the signal flow within the photoelectric converter 100 in the second embodiment. The photoelectric converter 100 in this embodiment differs from the first embodiment in that a selection signal s326 for fixing the conversion signal s311 to a certain level is input to the pixel unit 310.

[0061] In this embodiment, the pixel unit 310 includes a selection unit 316. The selection unit 316 is a logical AND circuit. The selection unit 316 is connected to the conversion unit 311, the selection unit 325, and the holding unit 313. The selection unit 316 receives a conversion signal s311 from the conversion unit 311. The selection unit 316 also receives a selection signal s325 from the selection unit 325. The selection unit 316 selects either the conversion signal s311 or the selection signal s325, and outputs the selected signal as the selection signal s316 to the holding unit 313.

[0062] During imaging, the selection unit 316 receives a high-level drive signal s321 as a selection signal s325. Therefore, the selection unit 316 outputs the conversion signal s311, which corresponds to the pixel signal s401 received from the conversion unit 311, as a selection signal s316 to the holding unit 313.

[0063] In this embodiment, a selection unit 326 is located in the peripheral region 32. The selection unit 326 selects one signal from among multiple input signals and outputs the selected signal. The selection unit 326 is connected to the drive unit 321 and the test unit 322. The selection unit 326 receives a switch signal s321S from the drive unit 321. The selection unit 326 also receives a switch signal s322S from the test unit 322. The selection unit 326 selectively outputs either the switch signal s321S or the switch signal s322S as a selection signal s326 to the pixel unit 310 via a common wiring 332. Specifically, during imaging, the selection unit 326 selects the switch signal s321S based on a control signal from the test unit 322. On the other hand, during test operation, the selection unit 326 selects the switch signal s322S based on a control signal from the test unit 322. The switch signals s321S and s322S will be described later. The selection unit 326 outputs the selected switch signal s321S or switch signal s322S as the selection signal s326 to the pixel unit 310 via the common wiring 332. Note that the control signal input to the selection unit 326 may be supplied by a control unit separate from the test unit 322.

[0064] The operation of the pixel unit 310 during imaging and test operations will be explained with reference to Figure 10. Figure 10 is a block diagram showing the configuration of the pixel unit 310 and the signal flow between the pixel unit 310 and the peripheral area in the second embodiment.

[0065] The pixel unit 310 in this embodiment includes a conversion unit 311, a selection unit 316, a holding unit 313, a quench element 314, and a switch element 317. The selection unit 316 is connected to the conversion unit 311 and the holding unit 313. The conversion unit 311 is a negation (NOT) circuit (gate circuit). The selection unit 316 is connected to the selection unit 325 via a common wiring 331.

[0066] The switch element 317 is located between the quench element 314 and the photoelectric conversion element 401. The switch element 317 operates based on the selection signal s326 supplied from the selection unit 326. When the switch element 317 is closed, the photoelectric conversion element 401 and the quench element 314 are electrically connected. That is, when the switch element 317 is closed, a voltage VH is applied to the photoelectric conversion element 401, and the photoelectric conversion element 401 is charged. On the other hand, when the switch element 317 is open, the voltage VH is not applied to the photoelectric conversion element 401, and the photoelectric conversion element 401 is not charged.

[0067] The operation of the photoelectric converter 100 according to this embodiment during imaging will be described below. The selection unit 325 selects the drive signal s321 generated by the drive unit 321. The selection unit 325 outputs the selected drive signal s321 as a selection signal s325 to the selection unit 316 via the common wiring 331. The selection unit 316 receives the high-level drive signal s321 as a selection signal s325.

[0068] The selection unit 326 outputs a high-level switch signal s321S as a selection signal s326 via the common wiring 332, closing the switch element 317. By closing the switch element 317, the photoelectric conversion element 401 is recharged after avalanche multiplication. Therefore, the conversion unit 311 receives a pixel signal s401 corresponding to the incidence of photons on the photoelectric conversion element 401. The selection unit 316 receives a conversion signal s311 corresponding to the pixel signal s401. Based on the selection signal s325 corresponding to the high-level drive signal s321, the selection unit 316 outputs the conversion signal s311 as a selection signal s316 to the holding unit 313.

[0069] Furthermore, by inputting a low-level drive signal s321 as a selection signal s325 to the selection unit 316, the counting operation of the holding unit 313 can be stopped. For example, the counting operation by the holding unit 313 of the pixel unit 310 located in an area where imaging is not performed can be stopped based on the drive signal s321, thereby reducing the power consumption of the photoelectric converter 100. In addition, by inputting a low-level drive signal s321 as a selection signal s326 to the switch element 317, the switch can be opened, and the recharging of the photoelectric converter element 401 after avalanche multiplication can be stopped. By stopping the recharging of the photoelectric converter element 401 during periods when the counting operation of incident photons is not required, the power consumption of the pixel unit 310 can be reduced.

[0070] The operation of the photoelectric converter 100 according to this embodiment during test operation will be described below. The selection unit 325 selects the test signal s322T generated by the test unit 322. The selection unit 325 outputs the selected test signal s322T as a selection signal s325 to the selection unit 316 via the common wiring 331. The selection unit 316 receives the test signal s322T as a selection signal s325.

[0071] The selection unit 326 outputs a low-level switch signal s322S as a selection signal s326 via the common wiring 332, opening the switch element 317. When the switch element 317 opens, the photoelectric conversion element 401 is electrically disconnected from the quench element 314. Therefore, the voltage VH is not applied to the photoelectric conversion element 401, and charging of the photoelectric conversion element 401 is stopped. As a result, the voltage signal at node N becomes low level. Based on the low-level voltage signal at node N, a high-level conversion signal s311 is input to the selection unit 316 via the conversion unit 311. Based on the high-level conversion signal s311, the selection unit 316 outputs a test signal s322T as a selection signal s316 to the holding unit 313.

[0072] According to this embodiment, even after the signal processing board 30 is electrically connected to the light receiving board 40, the holding unit (counter) can be inspected without shielding the photoelectric conversion element 401. Furthermore, the drive signal s321 for holding the signal from the photoelectric conversion element 401 in the counter and the test signal s322T for inspecting the counter are transmitted to the pixel unit 310 using the common wiring 331. In addition, the switch signals s321S and s322S that control the operation of the switch element 317 during imaging and testing are both transmitted via the common wiring 332. Therefore, the semiconductor device according to this embodiment can suppress the increase in wiring provided in the pixel unit for counter inspection, and can achieve miniaturization of pixels in the imaging device and high-gradation imaging of captured images.

[0073] [Third Embodiment] The semiconductor device operating as a photoelectric converter according to the third embodiment of this disclosure will be described with reference to Figure 11, focusing on the differences from the first embodiment.

[0074] Figure 11 is a block diagram showing the signal flow within the photoelectric converter 100 in the third embodiment. The photoelectric converter 100 in this embodiment differs from the first embodiment in that the photoelectric converter element 401 outputs an analog signal as a pixel signal, and the pixel unit 310 converts the pixel signal into a digital signal.

[0075] In this embodiment, the photoelectric conversion element 401 includes a photodiode. When light is incident on the photodiode, a photovoltaic power is generated in the photodiode corresponding to the amount of incident light. The photoelectric conversion element 401 generates a pixel signal s401 that represents an analog value based on the photovoltaic power. The photoelectric conversion element 401 outputs the generated pixel signal s401 to the pixel unit 310. In this embodiment, the pixel unit 310 includes a conversion unit 318. The conversion unit 318 receives the pixel signal s401 generated by the photoelectric conversion element 401. The conversion unit 318 converts the pixel signal s401 that represents an analog value into a digital signal.

[0076] In this embodiment, a clock generation unit 603 and a ramp generation unit 604 are arranged in the peripheral region 32. The clock generation unit 603 generates a clock signal s603 having a clock-like waveform. The clock generation unit 603 outputs the generated clock signal s603 to the conversion unit 318. The ramp generation unit 604 generates a ramp signal s604. The ramp signal s604 has a ramp-like waveform in which the signal level rises substantially linearly to a predetermined value over a predetermined period. The ramp generation unit 604 outputs the generated ramp signal s604 to the conversion unit 318. Note that the clock generation unit 603 and the ramp generation unit 604 may be arranged in a region other than the peripheral region 32.

[0077] The conversion unit 318 includes a comparator and an AND circuit. During imaging, the comparator receives a pixel signal s401, which represents an analog value, from the photoelectric conversion element 401. The comparator also receives a lamp signal s604 from the lamp generation unit 604. The comparator compares the pixel signal s401 and the lamp signal s604. During the period when the analog value represented by the pixel signal s401 is higher than the signal level of the lamp signal s604, the comparator inputs a high-level comparison signal to the AND circuit of the conversion unit 318. On the other hand, during the period when the analog value represented by the pixel signal s401 is lower than or equal to the signal level of the lamp signal s604, the comparator inputs a low-level comparison signal to the AND circuit of the conversion unit 318. In other words, the lamp signal s604 is used as a reference signal when evaluating the signal level of the pixel signal s401.

[0078] The AND circuit of the conversion unit 318 receives a comparison signal from the comparator. The AND circuit of the conversion unit 318 also receives a clock signal s603 from the clock generation unit 603. The AND circuit of the conversion unit 318 outputs the clock signal s603 as a conversion signal s318 to the selection unit 312 only during the period when a high-level comparison signal is input. That is, the AND circuit of the conversion unit 318 outputs the clock signal s603 to the selection unit 312 during the period until the relative magnitudes of the ramp signal s604 and the pixel signal s401 are reversed. On the other hand, the AND circuit of the conversion unit 318 does not output the clock signal s603 to the selection unit 312 during the period when a low-level comparison signal is input. That is, the AND circuit of the conversion unit 318 does not output the clock signal s603 to the selection unit 312 during the period after the signal level of the ramp signal s604 reaches the analog value indicated by the pixel signal s401. Since the signal level of the ramp signal s604 rises approximately linearly during a predetermined period, the number of clocks in the clock signal s603 input to the selection unit 312 during that period changes according to the analog value of the pixel signal s401. As a result, the conversion unit 318 outputs a clock signal having a number of clocks corresponding to the analog value of the pixel signal s401 to the selection unit 312 as a conversion signal s318. Also, during imaging operation, the selection unit 312 receives a low-level drive signal s321 from the drive unit 321 via the common wiring 331 as a selection signal s325. The selection unit 312 selects the conversion signal s318 based on the low-level drive signal s321. The selection unit 312 outputs the selected conversion signal s318 to the holding unit 313 as a selection signal s312.

[0079] The holding unit 313 receives a selection signal s312 from the selection unit 312 that corresponds to the conversion signal s318. The holding unit 313 counts the number of clocks included in the selection signal s312. The number of clocks included in the selection signal s312 corresponds to the analog value of the pixel signal s401. The holding unit 313 holds the counted number of clocks as a digital value corresponding to the pixel signal s401. The holding unit 313 outputs the digital value corresponding to the pixel signal s401 as a holding signal s313 to the signal processing unit 324. Note that the counting operation of the holding unit 313 can be stopped by inputting a high-level drive signal s321 from the drive unit 321 to the selection unit 312 via the common wiring 331. For example, the counting operation of the holding unit 313 of a pixel unit 310 located in a specific area where imaging is not performed can be stopped based on the drive signal s321, thereby reducing the power consumption of the photoelectric converter 100.

[0080] During the test operation, the test unit 322 outputs a control signal to the clock generation unit 603, stopping the output of the clock signal s603 by the clock generation unit 603. In response to not receiving the input of the clock signal s603, the conversion unit 318 generates a low-level conversion signal s318. The conversion unit 318 outputs the generated conversion signal s318 to the selection unit 312. The selection unit 325 also outputs a test signal s322T to the selection unit 312 during the test operation. That is, during the test operation of this embodiment, the selection unit 312 outputs the test signal s322T as a selection signal s312 to the holding unit 313 based on the low-level conversion signal s318. The holding unit 313 outputs a holding signal s313 corresponding to the test signal s322T to the determination unit 601. The determination unit 601 inspects the holding unit 313 based on the holding signal s313 and the expectation signal s322E. The control signals input to the clock generation unit 603 may be supplied by a control unit separate from the test unit 322.

[0081] According to this embodiment, the conversion unit 318 and the holding unit 313 are operated as analog-to-digital (AD) conversion units. In addition, the drive signal s321 for holding the pixel signal s401 in the holding unit (counter) and the test signal s322T for inspecting the counter are transmitted to each pixel unit using the common wiring 331. Therefore, even when the photoelectric conversion element 401 is used in a CMOS sensor or the like and has a photodiode that generates a pixel signal in response to a photon, the increase in wiring provided to each pixel unit for inspecting the counter can be suppressed, and miniaturization of pixels in the imaging device and high-gradation imaging of the captured image can be achieved. Furthermore, even after the signal processing board 30 is electrically connected to the light receiving board 40, the holding unit 313 can be inspected without shielding the photoelectric conversion element 401 by controlling the clock generation unit 603.

[0082] [Fourth Embodiment] The semiconductor device according to the fourth embodiment of this disclosure will be described with reference to Figures 6, 12, and 13, focusing on the differences from the first embodiment.

[0083] Figure 12 is a block diagram showing two pixel sections 310a and 310b within a signal processing board 30, which is a semiconductor device in this embodiment. Figure 13 is a block diagram showing the signal flow within the signal processing board 30 in this embodiment. The semiconductor device according to this embodiment differs from the first embodiment in that it transmits two different test signals s322T and s327T to pixel sections 310a and 310b arranged in the same row, respectively.

[0084] As shown in Figure 6, the pixel region 31 has multiple pixel sections 310, including pixel sections 310a and 310b, arranged in a matrix. Also, as shown in Figures 6 and 12, the pixel sections 310a and 310b are arranged adjacent to each other. The holding section 313A of the pixel section 310a (first pixel section) includes multiple holding elements 313a. The holding section 313B of the pixel section 310b (second pixel section) includes multiple holding elements 313b. Each of the holding elements 313a and 313b is adjacent to each other and arranged symmetrically with respect to the vertical axis in Figure 12. The number of holding elements 313a and 313b may change depending on the number of bits of the signal held by the holding section 313.

[0085] In the first embodiment, a common test signal s322T generated by the test unit 322 is transmitted by the vertical control unit 323 to the pixel units 310a and 310b arranged in the same row. Therefore, the common test signal s322T is held in the holding units 313A and 313B. On the other hand, if a fault occurs, such as an electrical short circuit between adjacent holding elements 313a and 313b, common data may always be held in the holding elements 313a and 313b. In other words, when a common test signal s322T is transmitted to the pixel units 310a and 310b, it is not possible to detect a fault such as a short circuit between holding elements 313a and 313b. In order to detect a fault caused by a short circuit, it is necessary to transmit different test signals to the holding elements 313a and 313b.

[0086] As shown in Figure 13, the pixel unit 310a includes a conversion unit 311A, a selection unit 312A, and a holding unit 313A. The pixel unit 310b also includes a conversion unit 311B, a selection unit 312B, and a holding unit 313B. The conversion units 311A ​​and 311B, which output conversion signals s311A and s311B, correspond to the conversion unit 311 of the first embodiment, which outputs the conversion signal s311. The selection units 312A and 312B, which output selection signals s312A and s312B, correspond to the selection unit 312 of the first embodiment, which outputs the selection signal s312. The holding units 313A and 313B, which output holding signals s313A and s313B, correspond to the holding unit 313 of the first embodiment, which outputs the holding signal s313.

[0087] During test operation, the selection unit 325 according to this embodiment selects the test signal s322T (first test signal) as the selection signal s325 based on the control signal from the test unit 322 (first test unit), similar to the first embodiment. The selection unit 325 transmits the selected test signal s322T to the pixel unit 310a via the common wiring 331. The test signal s322T is held by the holding unit 313A via the selection unit 312A. The holding unit 313A transmits the held test signal s322T as the holding signal s313A to the determination unit 601.

[0088] The signal processing board 30 according to this embodiment further includes a test unit 327 (second test unit) and a selection unit 328. The test unit 327 transmits a test signal s327 (second test signal) to the selection unit 328. The test signal s327 is a signal that, for example, shows a different value from the test signal s322T in each bit. The test unit 327 also transmits an expected signal s327E corresponding to the test signal s327T to the determination unit 601.

[0089] During the test operation, the selection unit 328 selects the test signal s327T as the selection signal s328 based on the control signal from the test unit 327. The selection unit 328 transmits the selected test signal s327T to the pixel unit 310b via the common wiring 332. The test signal s327T is held by the holding unit 313B via the selection unit 312B. The holding unit 313B transmits the held test signal s327T as the holding signal s313B to the determination unit 601.

[0090] The determination unit 601 determines whether the holding unit 313A is functioning correctly based on the holding signal s313A and expectation signal s322E corresponding to the test signal s322T. The determination unit 601 also determines whether the holding unit 313B is functioning correctly based on the holding signal s313B and expectation signal s327E corresponding to the test signal s327T. Furthermore, the determination unit 601 compares the holding signals s313A and s313B. For example, if the holding signals s313A and s313B show the same value for a certain bit, the determination unit 601 determines that the holding elements 313a and 313b corresponding to that bit are not functioning correctly. On the other hand, if the holding signals s313A and s313B show different values ​​for all bits, the determination unit 601 determines that all holding elements 313a and 313b are functioning correctly.

[0091] In this embodiment, the drive unit 321 generates a drive signal s321A for the pixel unit 310a and a drive signal s321B for the pixel unit 310b. During imaging, the drive signal s321A is transmitted to the pixel unit 310a by the selection unit 325 via the common wiring 331. The drive signal s321B is transmitted to the pixel unit 310b by the selection unit 328 via the common wiring 332.

[0092] The test signals s322T and s327T and the expected signals s322E and s327E may be generated by a common test unit. Furthermore, the control signals input to the selection unit 328 may be supplied by a control unit separate from the test unit 327. Additionally, the determination unit 601 may be located outside the signal processing board 30.

[0093] According to this embodiment, even if a problem such as a short circuit occurs in the pixel units 310a and 310b arranged in the same row, a failure in the holding units 313A and 313B (counters) can be detected based on test signals s322T and s327T, which show different values ​​for each bit. In addition, the drive signals s321A and s321B for holding the pixel signal s401 in the counter, and the test signals s322T and s327T for inspecting the counter are transmitted to each pixel unit via common wiring 331 and 332. Therefore, according to this embodiment, the increase in wiring provided in each pixel unit for inspecting the counter can be suppressed, and the miniaturization of pixels in the imaging device and the high-gradation of the captured image can be achieved.

[0094] [Fifth Embodiment] The semiconductor device according to the fifth embodiment of this disclosure will be described with reference to Figure 14, focusing on the differences from the fourth embodiment.

[0095] Figure 14 is a block diagram showing the signal flow within the signal processing board 30, which is a semiconductor device in this embodiment. The semiconductor device according to this embodiment differs from the fourth embodiment in that it transmits a common test signal s322T to pixel units 310a and 310b arranged in the same row.

[0096] The pixel unit 310a in this embodiment includes a conversion unit 319. The conversion unit 319 receives a selection signal s325 from the selection unit 325 via a common wiring 331. During the test operation of the pixel unit 310a, the selection unit 325 transmits a test signal s322T as the selection signal s325 to the conversion unit 319. The conversion unit 319 determines that the selection signal s325 is a test signal based on the signal level of the selection signal s325. The conversion unit 319 inverts the polarity of the selection signal s325, which has been determined to be a test signal. Specifically, the conversion unit 319 inverts each bit value indicated by the test signal s322T to generate a conversion test signal s322T' (first conversion test signal). Each bit indicated by the conversion test signal s322T' has a different value from the corresponding bit indicated by the test signal s322T. During the test operation, the conversion unit 319 transmits the converted selection signal s325, which is the conversion test signal s322T', to the selection unit 312A as the conversion signal s319. During the test operation, the selection unit 312A transmits the conversion test signal s322T' to the holding unit 313A as the selection signal s312A. The conversion test signal s322T' held by the holding unit 313A is transmitted to the determination unit 601 as the holding signal s313A.

[0097] On the other hand, the pixel unit 310b in this embodiment does not have a conversion unit 319. Therefore, the test signal s322T transmitted to the pixel unit 310b during test operation is input to the selection unit 312B via the common wiring 331 without undergoing conversion processing. The selection unit 312B transmits the test signal s322T as a selection signal s312B to the holding unit 313B. The test signal s322T held by the holding unit 313B is transmitted to the determination unit 601 as a holding signal s313B. The holding signal s313B corresponding to the test signal s322T has not undergone conversion processing by the conversion unit 319. Therefore, the holding signal s313B shows a different value for each bit from the holding signal s313A corresponding to the converted test signal s322T'.

[0098] The determination unit 601 determines whether the holding unit 313A is operating normally based on the holding signal s313A and the expectation signal s322E. Specifically, the determination unit 601 generates an expectation signal s322E' corresponding to the conversion test signal s322T' based on the expectation signal s322E. For example, the determination unit 601 performs the same processing on the expectation signal s322E as the signal conversion processing performed by the conversion unit 319. The determination unit 601 compares the holding signal s313A corresponding to the conversion test signal s322T' with the expectation signal s322E'. If the holding signal s313A and the expectation signal s322E' show the same value, the determination unit 601 determines that the holding unit 313A is operating normally. If the holding signal s313A and the expectation signal s322E' show different values, the determination unit 601 determines that the holding unit 313A is not operating normally.

[0099] Similar to the first embodiment, the determination unit 601 determines whether the holding unit 313B is operating normally based on the holding signal s313B and the expected signal s322E corresponding to the test signal s322T. Furthermore, the determination unit 601 compares the holding signal s313A and the holding signal s313B. For example, if the holding signal s313A and the holding signal s313B show the same value for a certain bit, the determination unit 601 determines that the holding elements 313a and 313b corresponding to that bit are faulty. On the other hand, if the holding signal s313A and the holding signal s313B show different values ​​for all bits, the determination unit 601 determines that the holding elements 313a and 313b are operating normally. Note that the determination unit 601 may be located outside the signal processing board 30.

[0100] On the other hand, during imaging, the selection unit 325 transmits the drive signal s321, which is the selection signal s325 for the pixel unit 310a, to the conversion unit 319 via the common wiring 331. The conversion unit 319 determines that the selection signal s325 is a drive signal based on the signal level of the selection signal s325. The conversion unit 319 does not perform any conversion processing on the selection signal s325 which it has determined to be a drive signal. During imaging, the conversion unit 319 transmits the drive signal s321, which is the selection signal s325 during imaging, to the selection unit 312.

[0101] According to this embodiment, even if a problem such as a short circuit occurs in the pixel units 310a and 310b arranged in the same row, a failure in the holding units 313A and 313B (counters) can be detected using a common test signal s322T. Furthermore, the drive signal s321 for holding the pixel signal s401 in the counter and the test signal s322T for inspecting the counter are transmitted to each pixel unit, respectively, using a common wiring 331. Therefore, according to this embodiment, the increase in wiring provided to each pixel unit for counter inspection can be suppressed, and miniaturization of pixels in the imaging device and high-gradation imaging of captured images can be achieved.

[0102] [Sixth Embodiment] The semiconductor device according to the sixth embodiment of this disclosure will be described with reference to Figures 15 and 16, focusing on the differences from the fourth embodiment.

[0103] Figure 15 is a block diagram showing two pixel sections 310a and 310b within a signal processing substrate 30, which is a semiconductor device in this embodiment. Figure 16 is a block diagram showing the signal flow within the signal processing substrate 30 in this embodiment. The semiconductor device according to this embodiment differs from the fourth embodiment in that it further includes an aggregation section 312C and a holding section 313C.

[0104] As shown in Figure 15, a holding unit 313C (third holding unit) is provided in the pixel region 31. The holding unit 313C holds the sum of the selection signal s312A and the selection signal s312B. That is, the holding unit 313C holds the sum of the output values ​​of multiple pixel regions. The holding unit 313C includes multiple holding elements 313c. The holding elements 313c are arranged to correspond to the holding elements 313a and 313b. The number of holding elements 313c may vary depending on the number of bits of the signals held by the holding unit 313A (first holding unit) and the holding unit 313B (second holding unit). As shown in Figure 15, the holding unit 313C may be located in the region between the holding unit 313A and the holding unit 313B. However, the location of the holding unit 313C is not limited to the region between the holding unit 313A and the holding unit 313B.

[0105] According to this embodiment, three holding units 313A, 313B, and 313C are provided for two photoelectric conversion elements 401. The configuration according to this embodiment can be used, for example, when a photoelectric conversion device 100 performs autofocus using the output difference of pixels arranged adjacent to each other. When the photoelectric conversion device 100 performs autofocus, the selection signal s312A as the pixel signal s401 is held in the holding unit 313A, and the selection signal s312B as the pixel signal s401 is held in the holding unit 313B. On the other hand, when the photoelectric conversion device 100 does not perform autofocus, the selection signals s312A and s312B as the pixel signals s401 are added together, and the added value is held in the holding unit 313C. The operating principle of autofocus is not directly related to this disclosure, so a description is omitted. As another example, the configuration according to this embodiment can also be used when the photoelectric conversion device 100 has a binning function and the outputs from multiple photoelectric conversion elements 401 are totaled and held in a single holding unit.

[0106] In the fourth embodiment, the holding unit 313A is inspected using the test signal s322T generated by the test unit 322, and the holding unit 313B is inspected using the test signal s327T generated by the test unit 327. For example, suppose that the holding units 313A and 313B each hold 3 bits, the test signal s322T indicates "000", and the test signal s327T indicates "111". In this case, the holding unit 313C holds the value "111", which is the sum of the test signals s322T and s327T. Therefore, the holding units 313B and 313C hold the common value "111". On the other hand, if a fault occurs, such as an electrical short circuit between the holding units 313B and 313C, the holding units 313B and 313C may always hold the same value. In other words, if common data is transmitted between the holding unit 313A or 313B and 313C, it is not possible to detect faults such as short circuits between the holding unit 313A or 313B and 313C. In order to detect faults caused by short circuits, it is necessary to transmit different test signals to the holding units 313A, 313B, and 313C.

[0107] As shown in Figure 16, the signal processing board 30 according to this embodiment includes an aggregation unit 312C and a holding unit 313C. The aggregation unit 312C includes a logical OR circuit. During imaging, the aggregation unit 312C receives a selection signal s312A as a conversion signal s311A from the selection unit 312A. Also during imaging, the aggregation unit 312C receives a selection signal s312B as a conversion signal s311B from the selection unit 312B. The aggregation unit 312C adds the value indicated by the selection signal s312A (conversion signal s311A) and the value indicated by the selection signal s312B (conversion signal s311B). The aggregation unit 312C transmits the aggregated signal s312C, which indicates the value obtained by adding the selection signal s312A and the selection signal s312B, to the holding unit 313C. The holding unit 313C holds the summation signal s312C received from the summation unit 312C. The holding unit 313C transmits the summation signal s312C as a held signal s313C to the signal processing unit 324 and the determination unit 601.

[0108] During test operation, the selection unit 325 according to this embodiment transmits a test signal s322T to the pixel unit 310a via the common wiring 331, similar to the fourth embodiment. The test signal s322T is transmitted to the summing unit 312C and the holding unit 313A via the selection unit 312A. Similarly, the selection unit 328 according to this embodiment transmits a test signal s327T to the pixel unit 310b via the common wiring 332. The test signal s327T is transmitted to the summing unit 312C and the holding unit 313B via the selection unit 312B.

[0109] In this embodiment, the test units 322 and 327 output test signals s322T and s327T while continuously changing them. For example, when the holding units 313A, 313B, and 313C hold 3 bits of data, the test unit 322 sequentially outputs signals indicating "010", "101", "000", and "010" as the test signal s322T. On the other hand, the test unit 327 sequentially outputs signals indicating "101", "010", "000", and "010" as the test signal s327T. In this example, the summing unit 312C sums the test signals s322T and s327T, which represent the above values ​​respectively, and sequentially transmits the summing signal s312C (summing test signal) to the holding unit 313C. The holding unit 313C transmits the summation signal s312C, which indicates "111", "111", "000", and "100", to the sequential determination unit 601 as the holding signal s313C. Meanwhile, the holding unit 313A transmits the test signal s322T (selection signal s312A), which indicates "010", "101", "000", and "010", to the sequential determination unit 601. In addition, the holding unit 313B transmits the test signal s327T (selection signal s312B), which indicates "101", "010", "000", and "010", to the determination unit 601. In other words, the data indicated by the four holding signals s313C sequentially transmitted from the holding unit 313C to the determination unit 601 is different from the data indicated by the four holding signals s313A and s313B sequentially transmitted from the holding units 313A and 313B to the determination unit 601.

[0110] The determination unit 601 determines whether the holding unit 313A is operating normally based on the holding signal s313A and expectation signal s322E corresponding to the test signal s322T. The determination unit 601 also determines whether the holding unit 313B is operating normally based on the holding signal s313B and expectation signal s327E corresponding to the test signal s327T. Furthermore, the determination unit 601 generates an expectation signal s313E by summing the expectation signal s322E and the expectation signal s327E. The determination unit 601 determines whether the holding unit 313C is operating normally based on the expectation signal s313E and the holding signal s313C. The determination unit 601 also compares the sequentially transmitted holding signals s313A and s313B with the sequentially transmitted holding signal s313C. For example, if the four sequentially transmitted holding signals s313B show the same data as the four sequentially transmitted holding signals s313C, the determination unit 601 determines that a fault has occurred between the holding signals s313B and s313C due to a short circuit or the like. On the other hand, if the four sequentially transmitted holding signals s313B show different data from the four sequentially transmitted holding signals s313C, the determination unit 601 determines that no fault has occurred between the holding units 313B and 313C due to a short circuit or the like.

[0111] According to this embodiment, even if a problem such as a short circuit occurs between the holding parts 313A, 313B and the holding part 313C, a fault occurring between the holding parts 313A, 313B and the holding part 313C can be detected based on the test signals s322T, s327T and the holding signal s313C. For example, by adjusting the data indicated by the test signals s322T and s327T, each of the holding elements 313c can be made to hold a different value from the corresponding holding element 313a or holding element 313b. In other words, according to this embodiment, a fault caused by a short circuit or the like occurring between the holding element 313c and the corresponding holding elements 313a and 313b can be detected.

[0112] As a modification of this embodiment, a test unit 329 (third test unit) that generates a test signal s329T (third test signal) and an expected signal s329E may be further provided, as shown in Figure 17. In this modification, a logical OR circuit 314C is provided between the summing unit 312C and the holding unit 313C. During test operation, the test unit 329 transmits the test signal s329T to the logical OR circuit 314C. The test unit 329 transmits the expected signal s329E to the determination unit 601. The summing unit 312C also transmits the summing signal s312C (first summed test signal) to the logical OR circuit 314C. The logical OR circuit 314C sums the test signal s329T and the summing signal s312C to generate a summed signal s314C (second summed test signal). The summed signal s314C shows different data from the holding signals s313A and s313B. The OR circuit 314C transmits the sum signal s314C to the holding unit 313C. The holding unit 313C transmits the sum signal s314C as the holding signal s313C to the signal processing unit 324 and the determination unit 601. The determination unit 601 generates an expected signal corresponding to the sum signal s314C using the expected signals s322E, s327E, and s329E. Based on the generated expected signal and expected signals s322E and s327E, the determination unit 601 determines whether a fault has occurred between the holding units 313A, 313B and the holding unit 313C. Meanwhile, during imaging, the test unit 329 transmits a control signal to the OR circuit 314C. Based on the control signal, the OR circuit 314C adds the conversion signal s311A and the conversion signal s311B to generate a summed signal s312C, which is then transmitted to the holding unit 313C as a summed signal s314C. According to the above modified example of this embodiment, a fault occurring between the holding units 313A, 313B and the holding unit 313C can be detected based on the test signals s322T, s327T, and s329T.

[0113] [Seventh Embodiment] The semiconductor device according to the seventh embodiment of this disclosure will be described with reference to Figure 18, focusing on the differences from the fifth embodiment.

[0114] Figure 18 is a block diagram showing the signal flow within the signal processing board 30 in this embodiment. The semiconductor device according to this embodiment differs from the fifth embodiment in that it further comprises an aggregation unit 312C, a holding unit 313C, a conversion unit 350, and a logic OR circuit 351. According to this embodiment, similar to the sixth embodiment, the signal output from the photoelectric conversion element 401 is held by a plurality of holding units.

[0115] As shown in Figure 18, the signal processing board 30 according to this embodiment includes a summing unit 312C, a holding unit 313C, a conversion unit 350, and a logical OR circuit 351. During test operation, the conversion unit 350 receives a test signal s322T via a common wiring 331. The conversion unit 350 inverts at least a portion of the bit value indicated by the test signal s322T to generate a converted signal s350 (second converted test signal). The conversion unit 350 transmits the generated converted signal s350 to the logical OR circuit 351. The logical OR circuit 351 receives the converted signal s350 from the conversion unit 350. The logical OR circuit 351 also receives a selection signal s312A (first converted test signal s322T') from a selection unit 312A. The logical OR circuit 351 sums the converted signal s350 and the selection signal s312A to generate a summed signal s351 (third summed test signal). The OR circuit 351 transmits the generated sum signal s351 to the summing unit 312C.

[0116] The summing unit 312C receives a summing signal s351 from the OR circuit 351. The summing unit 312C also receives a selection signal s312B (test signal s322T) from the selection unit 312B. The summing unit 312C sums the summing signal s351 and the selection signal s312B to generate a summing signal s312C (fourth summing test signal). The data indicated by the summing signal s312C is different from the data indicated by the selection signals s312A and s312B. The summing unit 312C transmits the generated summing signal s312C to the holding unit 313. The holding unit 313 holds the summing signal s312C received from the summing unit 312C. The holding unit 313 transmits the held summing signal s312C as a held signal s313C to the signal processing unit 324 and the determination unit 601.

[0117] In the fifth embodiment, the holding unit 313B is inspected using the test signal s322T generated by the test unit 322, and the holding unit 313A is inspected using the converted test signal s322T' generated by the conversion unit 319. For example, assume that the holding units 313A and 313B each hold 3 bits, and the test signal s322T indicates "000". In this case, the converted test signal s322T' indicates "111". As a result, the sum of the test signal s322T and the converted test signal s322T' indicates "111". When the holding unit 313C holds this summation "111" during the test operation, a common value is held in the holding units 313A and 313C. On the other hand, if a fault occurs, such as an electrical short circuit in the holding units 313A and 313C, a common value may always be held in the holding units 313A and 313C. In other words, if common data is transmitted between the holding unit 313A or 313B and 313C, it is not possible to detect faults such as short circuits between the holding unit 313A or 313B and 313C. In order to detect faults caused by short circuits, it is necessary to transmit different test signals to the holding units 313A, 313B, and 313C.

[0118] According to this embodiment, similar to the fifth embodiment, the test signal s322T is input to the pixel units 310a and 310b. Meanwhile, the summation signal s312C, which is a test signal, is generated based on the test signal s322T and the converted test signal s322T' via the pixel units 310a and 310b, the conversion unit 350, the OR circuit 351, and the summation unit 312C. The generated test signal (summation signal s312C) is held in the holding unit 313C. The generated test signal, the summation signal s312C, shows a different value from the test signal s322T held in the holding unit 313B and the converted test signal s322T' held in the holding unit 313A. Therefore, even if a problem such as a short circuit occurs between the holding units 313A, 313B and the holding unit 313C, the fault occurring between the holding units 313A, 313B and the holding unit 313C can be detected based on the test signal s322T, the conversion test signal s322T', and the holding signal s313C.

[0119] The OR circuit 351 according to this embodiment generates a summed signal s351 by summing the conversion signal s350 and the selection signal s312A. In a modified example of this embodiment, the OR circuit 351 can generate a summed signal s351 by summing the conversion signal s350 and the selection signal s312B. In this case, the summing unit 312C generates a summed signal s312C as a test signal by summing the summed signal s351 and the selection signal s312A.

[0120] [Eighth Embodiment] The semiconductor device according to the eighth embodiment of this disclosure will be described with reference to Figure 19, focusing on the differences from the fifth embodiment.

[0121] Figure 19 is a block diagram showing the signal flow within the signal processing board 30 in this embodiment. The semiconductor device according to this embodiment differs from the fifth embodiment in that the pixel unit 310a is equipped with a control unit 360A instead of a conversion unit 319, and the pixel unit 310b is further equipped with a control unit 360B.

[0122] As shown in Figure 19, the pixel unit 310a in this embodiment includes a control unit 360A. The pixel unit 310b in this embodiment also includes a control unit 360B. The control units 360A and 360B include a logical AND circuit. During test operation, the control unit 360A receives a test signal s322T as a selection signal s325 and a control signal s325a ​​from the selection unit 325. The control signal s325a ​​may be a 1-bit signal. The control unit 360A generates a selection signal s360A based on the selection signal s325 and the control signal s325a. The control unit 360A transmits the generated selection signal s360A to the selection unit 312A. Specifically, when the control signal s325a ​​indicates "1", the control unit 360A transmits the test signal s322T to the selection unit 312A. On the other hand, when the control signal s325a ​​indicates "0", the control unit 360A does not transmit the test signal s322T to the selection unit 312A. Similarly, during test operation, the control unit 360B receives a test signal s322T as a selection signal s325 and a control signal s325b from the selection unit 325. The control signal s325b may be a 1-bit signal. Based on the selection signal s325 and the control signal s325b, the control unit 360B generates a selection signal s360B. The control unit 360B transmits the generated selection signal s360B to the selection unit 312B. Specifically, if the control signal s325b indicates "1", the control unit 360B transmits the test signal s322T to the selection unit 312B. On the other hand, if the control signal s325b indicates "0", the control unit 360B does not transmit the test signal s322T to the selection unit 312B.

[0123] According to this embodiment, the time at which the holding unit 313A holds the test signal s322T and the time at which the holding unit 313B holds the test signal s322T can be controlled. For example, at time t1 (first time), the selection unit 325 transmits a control signal s325a ​​indicating "1" to the control unit 360A and a control signal s325b indicating "0" to the control unit 360B. Then, at time t2 (second time), which is later than time t1, the selection unit 325 transmits a control signal s325a ​​indicating "0" to the control unit 360A and a control signal s325b indicating "1" to the control unit 360B. In this case, at time t1, the test signal s322T is stored in the holding unit 313A. On the other hand, at time t1, the test signal s322T is not stored in the holding unit 313B. Then, at time t2, the test signal s322T is stored in the holding unit 313B. On the other hand, at time t2, the test signal s322T is not stored in the holding unit 313A. Also, at time t3, which is different from times t1 and t2, the selection unit 325 inputs control signals s325a ​​and s325b indicating "1" to the control units 360A and 360B, respectively. In this case, at time t3, the test signal s322T is simultaneously held in the holding units 313A and 313B. In other words, according to this embodiment, the test signal s322T can be selectively held in the holding units 313A and 313B using control signals s325a ​​and s325b.

[0124] [Ninth Embodiment] Figure 20 is a block diagram of the imaging system in this embodiment. The photoelectric converter in the above-described embodiment is applicable to various imaging systems. Examples of imaging systems include digital still cameras, digital camcorders, camera heads, photocopiers, fax machines, mobile phones, in-vehicle cameras, observation satellites, and surveillance cameras. Figure 20 shows a block diagram of a digital still camera as an example of an imaging system.

[0125] The imaging system 7 includes a barrier 706, a lens 702, an aperture 704, an imaging device 70, a signal processing unit 708, a timing generation unit 720, an overall control / calculation unit 718, a memory unit 710, a recording medium control I / F unit 716, a recording medium 714, and an external I / F unit 712. The barrier 706 protects the lens, and the lens 702 forms an optical image of the subject on the imaging device 70. The aperture 704 varies the amount of light passing through the lens 702. The imaging device 70 is configured as a photoelectric converter in the above embodiment and converts the optical image formed by the lens 702 into image data. The signal processing unit 708 performs various corrections and data compression on the imaging data output from the imaging device 70.

[0126] The timing generation unit 720 outputs various timing signals to the imaging device 70 and the signal processing unit 708. The overall control and calculation unit 718 controls the entire digital still camera, and the memory unit 710 temporarily stores image data. The recording medium control I / F unit 716 is an interface for recording or reading image data to or from the recording medium 714, which is a removable recording medium such as a semiconductor memory for recording or reading imaging data. The external I / F unit 712 is an interface for communicating with an external computer or the like. Timing signals and the like may be input from outside the imaging system, and the imaging system only needs to have at least the imaging device 70 and the signal processing unit 708 that processes the image signals output from the imaging device 70.

[0127] In this embodiment, the imaging device 70 and the signal processing unit 708 are provided on separate semiconductor substrates, but the imaging device 70 and the signal processing unit 708 may be formed on the same semiconductor substrate.

[0128] Furthermore, each pixel includes a first photoelectric conversion unit and a second photoelectric conversion unit. The signal processing unit 708 processes the pixel signal based on the charge generated in the first photoelectric conversion unit and the pixel signal based on the charge generated in the second photoelectric conversion unit, and can acquire distance information from the imaging device 70 to the subject.

[0129] [Tenth Embodiment] Figure 21 is a diagram of the light detection system in this embodiment, and is a block diagram of a distance image sensor using the photoelectric conversion device described in the above embodiment.

[0130] As shown in Figure 21, the distance image sensor 410 comprises an optical system 402, a photoelectric converter 403, an image processing circuit 404, a monitor 405, and a memory 406. The distance image sensor 410 receives light (modulated light, pulsed light) that is emitted from the light source device 411 toward the subject and reflected from the surface of the subject. Based on the time from emission to reception, the distance image sensor 410 can acquire a distance image corresponding to the distance to the subject.

[0131] The optical system 402 includes one or more lenses and guides the image light (incident light) from the subject to the photoelectric converter 403, where it forms an image on the light-receiving surface (sensor part) of the photoelectric converter 403.

[0132] The photoelectric converter 403 can be any of the photoelectric converters described in the above-described embodiments. The photoelectric converter 403 supplies a distance signal indicating the distance obtained from the received light signal to the image processing circuit 404.

[0133] The image processing circuit 404 performs image processing to construct a distance image based on the distance signal supplied from the photoelectric converter 403. The distance image (image data) obtained through image processing can be displayed on the monitor 405 and stored (recorded) in the memory 406.

[0134] The distance image sensor 410 configured in this way can acquire more accurate distance images by applying the photoelectric conversion device described above, as the characteristics of the pixels are improved.

[0135] [Embodiment No. 11] The technology described herein can be applied to a variety of products. For example, the technology described herein may be applied to an endoscopic surgical system.

[0136] Figure 22 is a schematic diagram of the endoscopic surgical system in this embodiment. Figure 22 shows a surgeon (physician) 1131 performing surgery on a patient 1132 on a patient bed 1133 using the endoscopic surgical system 1103. As shown in the figure, the endoscopic surgical system 1103 includes an endoscope 1100, surgical instruments 1110, and a cart 1134 on which various devices for endoscopic surgery are mounted.

[0137] The endoscope 1100 comprises a barrel 1101, the tip of which is inserted into the body cavity of the patient 1132 for a predetermined length, a camera head 1102 connected to the base end of the barrel 1101, and an arm 1121. Figure 22 shows the endoscope 1100 configured as a so-called rigid endoscope having a rigid barrel 1101, but the endoscope 1100 may also be configured as a so-called flexible endoscope having a flexible barrel.

[0138] An opening into which an objective lens is fitted is provided at the tip of the endoscope tube 1101. A light source device 1203 is connected to the endoscope 1100, and the light generated by the light source device 1203 is guided to the tip of the endoscope tube by a light guide extending inside the endoscope tube 1101, and is irradiated through the objective lens towards the object to be observed inside the body cavity of the patient 1132. The endoscope 1100 may be a straight-viewing endoscope, an oblique-viewing endoscope, or a side-viewing endoscope.

[0139] The camera head 1102 contains an optical system and a photoelectric converter. Reflected light from the object being observed (observation light) is focused by the optical system into the photoelectric converter. The photoelectric converter converts the observation light into electrical signals, generating an electrical signal corresponding to the observation light, i.e., an image signal corresponding to the observed image. The photoelectric converter can be any of the photoelectric converters described in the embodiments described above. The image signal is transmitted as RAW data to the camera control unit (CCU) 1135.

[0140] The CCU1135 consists of a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), etc., and comprehensively controls the operation of the endoscope 1100 and the display device 1136. Furthermore, the CCU1135 receives image signals from the camera head 1102 and performs various image processing operations on these image signals, such as development processing (demosaic processing), to display images based on the image signals.

[0141] The display device 1136 displays an image based on an image signal that has been processed by the CCU 1135, under control from the CCU 1135.

[0142] The light source device 1203 is equipped with a light source such as an LED (Light Emitting Diode) and supplies illumination light to the endoscope 1100 when photographing the surgical area, etc.

[0143] The input device 1137 is an input interface for the endoscopic surgical system 1103. The user can input various types of information and instructions to the endoscopic surgical system 1103 via the input device 1137.

[0144] The treatment instrument control device 1138 controls the driving of the energy treatment instrument 1112 for purposes such as tissue cauterization, incision, or blood vessel sealing.

[0145] The light source device 1203 is capable of supplying illumination light to the endoscope 1100 when photographing the surgical area, and may be, for example, an LED, a laser light source, or a combination thereof to form a white light source. When a white light source is formed by a combination of RGB laser light sources, the output intensity and output timing of each color (each wavelength) can be controlled with high precision. Therefore, the white balance of the captured image can be adjusted in the light source device 1203. In this case, the laser light from each of the RGB laser light sources may be irradiated onto the observation target in a time-division manner, and the drive of the image sensor of the camera head 1102 may be controlled in synchronization with the irradiation timing. This makes it possible to capture images corresponding to each of the RGB colors in a time-division manner. With this method, a color image can be obtained without providing a color filter on the image sensor.

[0146] Furthermore, the drive of the light source device 1203 may be controlled so that the intensity of the light output from the light source device 1203 is changed at predetermined time intervals. By controlling the drive of the image sensor of the camera head 1102 in synchronization with the timing of the change in light intensity to acquire images in time division and combining these images, it is possible to generate a high dynamic range image without so-called black crushing and white clipping.

[0147] Furthermore, the light source device 1203 may be configured to supply light in a predetermined wavelength band corresponding to special light observation. In special light observation, for example, the wavelength dependence of light absorption in body tissue can be utilized. Specifically, by irradiating with narrowband light compared to the irradiation light used during normal observation (i.e., white light), predetermined tissues such as blood vessels on the surface of mucosa can be imaged with high contrast. Alternatively, in special light observation, fluorescence observation may be performed to obtain an image from fluorescence generated by irradiation with excitation light. In fluorescence observation, excitation light can be irradiated onto body tissue and fluorescence from the body tissue can be observed, or a reagent such as indocyanine green (ICG) can be injected into body tissue and excitation light corresponding to the fluorescence wavelength of the reagent can be irradiated onto the body tissue to obtain a fluorescence image. The light source device 1203 may be configured to supply narrowband light and / or excitation light corresponding to such special light observation.

[0148] [Twelfth Embodiment] The light detection system and mobile body of this embodiment will be described with reference to Figures 23A, 23B, and 24. In this embodiment, an example of an in-vehicle camera is shown as the light detection system.

[0149] Figure 23A is a schematic diagram of the photodetection system in this embodiment, showing an example of a vehicle system and a photodetection system mounted on the vehicle system. The photodetection system 1301 includes a photoelectric converter 1302, an image preprocessing unit 1315, an integrated circuit 1303, and an optical system 1314. The optical system 1314 forms an optical image of the subject on the photoelectric converter 1302. The photoelectric converter 1302 converts the optical image of the subject formed by the optical system 1314 into an electrical signal. The photoelectric converter 1302 is one of the photoelectric converters in each of the embodiments described above. The image preprocessing unit 1315 performs predetermined signal processing on the signal output from the photoelectric converter 1302. The functions of the image preprocessing unit 1315 may be incorporated into the photoelectric converter 1302. The photodetection system 1301 is provided with at least two sets of optical systems 1314, photoelectric converters 1302, and image preprocessing units 1315, and the output from each set of image preprocessing units 1315 is input to the integrated circuit 1303.

[0150] The integrated circuit 1303 is an integrated circuit for imaging system applications and includes an image processing unit 1304 with a storage medium 1305, an optical distance measuring unit 1306, a parallax calculation unit 1307, an object recognition unit 1308, and an anomaly detection unit 1309. The image processing unit 1304 performs image processing such as development and defect correction on the output signal of the image preprocessing unit 1315. The storage medium 1305 stores the primary storage of the captured image and the defect positions of the captured pixels. The optical distance measuring unit 1306 focuses on the subject and measures the distance. The parallax calculation unit 1307 calculates distance measurement information from multiple image data acquired by multiple photoelectric converters 1302. The object recognition unit 1308 recognizes subjects such as cars, roads, signs, and people. When the anomaly detection unit 1309 detects an anomaly in the photoelectric converter 1302, it alerts the main control unit 1313 to the anomaly.

[0151] The integrated circuit 1303 may be implemented by specially designed hardware, by a software module, or by a combination of these. It may also be implemented by an FPGA (Field Programmable Gate Array), an ASIC (Application Specific Integrated Circuit), or a combination of these.

[0152] The main control unit 1313 coordinates and controls the operation of the light detection system 1301, vehicle sensor 1310, control unit 1320, etc. Alternatively, the main control unit 1313 may be omitted, and the light detection system 1301, vehicle sensor 1310, and control unit 1320 may each have their own communication interfaces, and each may send and receive control signals via a communication network, for example, using the CAN standard.

[0153] The integrated circuit 1303 has the function of receiving control signals from the main control unit 1313 or transmitting control signals and set values ​​to the photoelectric converter 1302 via its own control unit.

[0154] The light detection system 1301 is connected to the vehicle sensor 1310 and can detect the vehicle's driving conditions, such as vehicle speed, yaw rate, and steering angle, as well as the external environment and the state of other vehicles and obstacles. The vehicle sensor 1310 also functions as a distance information acquisition unit, acquiring distance information to objects. Furthermore, the light detection system 1301 is connected to the driver assistance control unit 1311, which performs various driving assistance functions such as automatic steering, automatic cruising, and collision avoidance. In particular, regarding the collision judgment function, the system determines whether a collision with another vehicle or obstacle has occurred and estimates the collision based on the detection results of the light detection system 1301 and the vehicle sensor 1310. This enables avoidance control when a collision is estimated and activation of safety devices in the event of a collision.

[0155] Furthermore, the light detection system 1301 is also connected to a warning device 1312 that issues a warning to the driver based on the judgment result of the collision judgment unit. For example, if the collision judgment unit determines that there is a high probability of collision, the main control unit 1313 performs vehicle control such as applying the brakes, releasing the accelerator, and suppressing engine output to avoid a collision or mitigate damage. The warning device 1312 issues a warning to the user by means of emitting a sound or other warning, displaying warning information on display screens such as the car navigation system and meter panel, and applying vibration to the seat belt and steering wheel.

[0156] The light detection system 1301 in this embodiment can capture images of the area around the vehicle, for example, in front of or behind it. Figure 23B is a schematic diagram of a moving object in this embodiment, showing a configuration in which the area in front of the vehicle is captured by the light detection system 1301.

[0157] The two photoelectric converters 1302 are positioned in front of the vehicle 1300. Specifically, it is preferable that the center line of the vehicle 1300 with respect to its direction of movement or external shape (e.g., vehicle width) is considered as the axis of symmetry, and the two photoelectric converters 1302 are positioned symmetrically with respect to the axis of symmetry. This makes it possible to effectively acquire distance information between the vehicle 1300 and the object being photographed and to determine the possibility of collision. Furthermore, it is preferable that the photoelectric converters 1302 are positioned so as not to obstruct the driver's field of view when the driver is viewing the situation outside the vehicle 1300 from the driver's seat. The warning device 1312 is preferably positioned so as to be easily visible to the driver.

[0158] Next, the fault detection operation of the photoelectric converter 1302 in the photodetection system 1301 will be explained using Figure 24. Figure 24 is a flowchart showing the operation of the photodetection system in this embodiment. The fault detection operation of the photoelectric converter 1302 can be performed according to steps S1410 to S1480.

[0159] In step S1410, the startup settings for the photoelectric converter 1302 are performed. Specifically, setting information for the operation of the photoelectric converter 1302 is transmitted from outside the photodetection system 1301 (e.g., the main control unit 1313) or from inside the photodetection system 1301, and the photoelectric converter 1302 starts the imaging operation and fault detection operation.

[0160] Next, in step S1420, the photoelectric converter 1302 acquires a pixel signal from the active pixels. Also, in step S1430, the photoelectric converter 1302 acquires an output value from a fault detection pixel provided for fault detection. This fault detection pixel is equipped with a photoelectric conversion element, just like the active pixels. A predetermined voltage is written to this photoelectric conversion element. The fault detection pixel outputs a signal corresponding to the voltage written to this photoelectric conversion element. Note that steps S1420 and S1430 may be executed in the reverse order.

[0161] Next, in step S1440, the light detection system 1301 determines whether the expected output value of the fault detection pixel matches the actual output value from the fault detection pixel. If the result of the matching determination in step S1440 shows that the expected output value and the actual output value match, the light detection system 1301 proceeds to step S1450, determines that the imaging operation is being performed normally, and proceeds to step S1460. In step S1460, the light detection system 1301 transmits the pixel signals of the scan row to the storage medium 1305 for temporary storage. After that, the light detection system 1301 returns to step S1420 and continues the fault detection operation. On the other hand, if the result of the matching determination in step S1440 shows that the expected output value and the actual output value do not match, the light detection system 1301 proceeds to step S1470. In step S1470, the light detection system 1301 determines that there is an abnormality in the imaging operation and issues an alarm to the main control unit 1313 or the alarm device 1312. The alarm device 1312 displays that an abnormality has been detected on its display unit. Subsequently, in step S1480, the light detection system 1301 stops the photoelectric converter 1302 and terminates the operation of the light detection system 1301.

[0162] In this embodiment, an example is shown where the flowchart is looped every row, but the flowchart may be looped every multiple rows, or the fault detection operation may be performed every frame. The alarm in step S1470 may be notified to an external party via a wireless network.

[0163] Furthermore, although this embodiment describes control to avoid collisions with other vehicles, it can also be applied to control that automatically follows other vehicles or control that automatically drives without deviating from the lane. In addition, the light detection system 1301 can be applied not only to vehicles such as the vehicle itself, but also to moving objects (mobile devices) such as ships, aircraft, or industrial robots. Moreover, it can be applied not only to moving objects, but also to a wide range of devices that utilize object recognition, such as intelligent transportation systems (ITS). The photoelectric conversion device of the present invention may further be configured to acquire various types of information, such as distance information.

[0164] [13th Embodiment] Figure 25(a) shows a specific example of an electronic device in this embodiment, and shows eyeglasses 1600 (smart glasses). The eyeglasses 1600 are equipped with the photoelectric converters 1602 described in each of the embodiments above. A display device including a light-emitting device such as an OLED or LED may be provided on the back side of the lens 1601. There may be one or more photoelectric converters 1602. In addition, multiple types of photoelectric converters may be combined. The arrangement position of the photoelectric converters 1602 is not limited to that shown in Figure 25(a).

[0165] The eyeglasses 1600 further include a control device 1603. The control device 1603 functions as a power source that supplies power to the photoelectric converter 1602 and the aforementioned display device. The control device 1603 also controls the operation of the photoelectric converter 1602 and the display device. The lens 1601 has an optical system formed therein for focusing light onto the photoelectric converter 1602.

[0166] Figure 25(b) shows eyeglasses 1610 (smart glasses) relating to one application example. The eyeglasses 1610 have a control device 1612, which is equipped with a photoelectric converter corresponding to a photoelectric converter 1602 and a display device. The lens 1611 has an optical system formed therein for projecting the photoelectric converter in the control device 1612 and the light emitted from the display device, and an image is projected onto the lens 1611. The control device 1612 functions as a power supply that supplies power to the photoelectric converter and the display device, and also controls the operation of the photoelectric converter and the display device. The control device 1612 may have a gaze detection unit that detects the wearer's gaze. Gaze detection may use infrared light. The infrared light emitter emits infrared light towards the eyeball of the user who is gazing at the displayed image. An imaging unit having a light-receiving element detects the reflected light from the eyeball of the emitted infrared light, thereby obtaining an image of the eyeball. By having a reduction mechanism that reduces the amount of light transmitted from the infrared light-emitting part to the display part in a planar view, the degradation of image quality is reduced.

[0167] The user's gaze towards a displayed image is detected from an image of the eyeball obtained by imaging with infrared light. Any known method can be applied to gaze detection using an image of the eyeball. As an example, a gaze detection method based on the Purkinje image obtained by the reflection of the irradiated light from the cornea can be used.

[0168] More specifically, gaze detection processing is performed based on the pupil-corneal reflection method. Using the pupil-corneal reflection method, a gaze vector representing the orientation (rotation angle) of the eyeball is calculated based on the pupil image and Purkinje image contained in the captured image of the eyeball, thereby detecting the user's gaze.

[0169] The display device of this embodiment includes a photoelectric converter having a light-receiving element, and may control the display image of the display device based on the user's gaze information from the photoelectric converter.

[0170] Specifically, the display device determines, based on gaze information, a first field of view area that the user is fixated on and a second field of view area other than the first field of view area. The first and second field of view areas may be determined by the control device of the display device or by an external control device. Within the display area of ​​the display device, the display resolution of the first field of view area may be controlled to be higher than that of the second field of view area. In other words, the resolution of the second field of view area may be lower than that of the first field of view area.

[0171] Furthermore, the display area may include a first display area and a second display area different from the first display area. Based on gaze information, a higher priority area may be determined from the first and second display areas. The first and second view areas may be determined by the control device of the display device or by an external control device. The resolution of the higher priority area may be controlled to be higher than the resolution of the areas other than the higher priority area. In other words, the resolution of areas with relatively lower priority may be lower.

[0172] Artificial Intelligence (AI) may be used in determining the first field of view area and the area with the highest priority. The AI ​​may be a model configured to estimate the angle of gaze and the distance to the target object at the end of the line of sight from the image of the eyeball, using the image of the eyeball and the direction the eyeball was actually looking in the image as training data. The AI ​​program may be installed in the display device, the photoelectric converter, or an external device. If the external device has the AI ​​program, it may be transmitted to the display device from a server or the like via communication.

[0173] When display control is performed based on visual detection, this embodiment can be preferably applied to smart glasses further having a photoelectric conversion device for capturing images of the outside. The smart glasses can display the captured external information in real time.

[0174] [Other embodiments] The configurations described in this disclosure are not limited to the embodiments described above and can be modified in various ways. For example, examples in which a part of the configuration of one embodiment is added to another embodiment, or in which a part of the configuration of another embodiment is replaced, are also embodiments of the present invention. As a modification of each embodiment, for example, a data storage circuit for temporarily storing the holding signal s313 may be arranged between the holding unit 313 and the signal processing unit 324.

[0175] In the twelfth embodiment, a method for detecting a failure in a photoelectric converter (semiconductor device) during normal operation was described using a failure detection pixel provided for failure detection. On the other hand, according to the first to eleventh and thirteenth embodiments, failures in the holding parts included in a semiconductor device can be detected before shipment as a product, after shipment as a product, and while the semiconductor device is operating. For example, the test operation according to this disclosure can be performed before the semiconductor device is shipped as a product, and semiconductor devices containing faulty holding parts can be excluded from the shipped products. Furthermore, the test operation for the holding parts according to each embodiment may be performed periodically while the semiconductor device is operating. In addition, the semiconductor device according to this disclosure may be further provided with a function to notify the external party of the test results when a failure is detected.

[0176] The disclosures in this specification include the following components: (Composition 1) A pixel unit including a conversion unit that converts a pixel signal into a converted signal and a holding unit that holds the converted signal, A drive unit that generates a drive signal indicating whether or not to hold the conversion signal in the holding unit, A test unit that generates a test signal for inspecting the holding unit and Includes, In the first operating mode, the drive unit outputs the drive signal to the pixel unit via wiring to the pixel unit, and the holding unit holds and outputs the conversion signal based on the drive signal. In the second operating mode, the test unit outputs the test signal to the pixel unit via the wiring, and the holding unit holds and outputs the test signal. Semiconductor equipment. (Configuration 2) The system further includes a switching unit that selectively connects the aforementioned wiring to the drive unit or the test unit. In the first operating mode, the switching unit connects the wiring to the drive unit, and the holding unit holds the conversion signal based on the drive signal. In the second operating mode, the switching unit connects the wiring to the test unit, and the holding unit holds the test signal based on the conversion signal. The semiconductor device described in Configuration 1. (Composition 3) Includes a determination unit for determining a failure of the holding part, The test unit outputs an expected signal corresponding to the test signal to the determination unit. In the second operating mode, the determination unit compares the test signal output from the holding unit with the expected signal and determines whether the holding unit is faulty. The semiconductor device described in Configuration 2. (Composition 4) A semiconductor device according to any one of configurations 1 to 3, comprising a photoelectric conversion element that generates the pixel signal in response to incident light. (Composition 5) The semiconductor device according to configuration 4, wherein in the second operating mode, the pixel signal is fixed to a predetermined level. (Composition 6) The semiconductor device according to configuration 5, wherein charging to the photoelectric conversion element is stopped in the second operating mode. (Composition 7) The semiconductor device according to configuration 5, wherein the photoelectric conversion element is shielded in the second operating mode. (Composition 8) The aforementioned photoelectric conversion element includes an avalanche photodiode. The conversion unit includes a gate circuit that converts the pixel signal into a pulsed conversion signal. The holding unit includes a counter for counting the conversion signal. The semiconductor device described in Configuration 4. (Composition 9) The semiconductor device according to configuration 2, wherein the pixel portion is arranged in a matrix in the pixel region of the signal processing substrate, and the drive portion is arranged in a region of the signal processing substrate different from the pixel region. (Composition 10) The aforementioned test unit includes a first test unit and a second test unit. The pixel portion includes a first pixel portion and a second pixel portion arranged adjacent to the first pixel portion. In the second operating mode, the first test unit outputs a first test signal to the first pixel unit, and the second test unit outputs a second test signal different from the first test signal to the second pixel unit. The semiconductor device described in configuration 9. (Composition 11) The aforementioned retaining part is The first holding portion included in the first pixel portion, The second holding portion included in the second pixel portion, In the first operating mode, a third holding unit holds a signal generated by summing the conversion signal output from the first pixel unit and the conversion signal output from the second pixel unit. A semiconductor device as described in configuration 10, including the above. (Composition 12) In the second operating mode, the first holding unit holds the first test signal, the second holding unit holds the second test signal, and the third holding unit holds the combined test signal generated by summing the first test signal and the second test signal. The first test signal, the second test signal, and the combined test signal each indicate different data. The semiconductor device described in configuration 11. (Composition 13) The test unit further includes a third test unit that outputs a third test signal, In the second operating mode, the third holding unit holds a second combined test signal generated by summing the first combined test signal and the third test signal. The first combined test signal is generated by adding the first test signal and the second test signal. The semiconductor device described in configuration 11. (Composition 14) The pixel portion includes a first pixel portion and a second pixel portion arranged adjacent to the first pixel portion. In the second operating mode, the test unit outputs the test signal to the first pixel unit and the second pixel unit. The second pixel unit stores the test signal in the holding unit, the first pixel unit reverses the polarity of the test signal to generate a first conversion test signal, and stores the first conversion test signal in the holding unit. The semiconductor device described in configuration 9. (Composition 15) The aforementioned retaining part is The first holding portion included in the first pixel portion, The second holding portion included in the second pixel portion, In the second operating mode, a third holding unit holds a fourth combined test signal that is generated by adding the third combined test signal and the test signal output from the second pixel unit. Includes, The third combined test signal is generated by adding the first converted test signal and a second converted test signal, which is generated by converting at least some bits of the test signal. The semiconductor device described in configuration 14. (Composition 16) The pixel portion includes a first pixel portion and a second pixel portion arranged adjacent to the first pixel portion. The aforementioned retaining part is The first holding portion included in the first pixel portion, The second holding portion included in the second pixel portion, Includes, The first holding unit stores the test signal at a first time, and the second holding unit stores the test signal at a second time, which is different from the first time. The semiconductor device described in configuration 9. (Composition 17) The aforementioned pixel signal is an analog signal. In the first operating mode, the conversion unit compares the pixel signal with a reference signal that changes over time, and outputs the clock signal as the conversion signal to the holding unit for the period until the relative magnitudes of the reference signal and the pixel signal are reversed. The holding unit counts the clock signal. The semiconductor device described in Configuration 2. (Composition 18) Includes a photoelectric conversion element that generates the pixel signal in response to incident light, The aforementioned photoelectric conversion element includes a photodiode. The semiconductor device described in configuration 17. (Composition 19) An imaging device including a semiconductor device described in any one of configurations 1 to 18, A signal processing unit that processes the imaging data output from the imaging device. An imaging system equipped with the following features. (Composition 20) The semiconductor device according to configuration 19, wherein the signal processing unit generates a distance image representing distance information to an object based on the imaging data. (Composition 21) It is a mobile object, A semiconductor device described in any one of configurations 1 to 18, A distance information acquisition unit acquires distance information to an object from the signal output from the semiconductor device, A control unit that controls the moving body based on the distance information, A mobile body characterized by having the following features.

[0177] The present invention can also be realized by supplying a program that implements one or more of the functions of the above-described embodiments to a system or device via a network or storage medium, and by having one or more processors in the computer of that system or device read and execute the program. It can also be realized by a circuit (e.g., an ASIC) that implements one or more functions.

[0178] It should be noted that the embodiments described above are merely examples of how the present invention can be implemented, and the technical scope of the present invention should not be interpreted as being limited by them. In other words, the present invention can be implemented in various ways without departing from its technical concept or its main features. [Explanation of Symbols]

[0179] 30 Signal Processing Board 31 pixel area 32 Peripheral area 40 Light-receiving substrate 100 Photoelectric converter (semiconductor device) Pixel sections 310, 310a, and 310b 311, 311A, 311B conversion unit 312, 312A, 312B Selection Section 313, 313A, 313B, 313C holding part 321 Drive Unit 322 Test Department 401 Photoelectric conversion element 601 Judgment section

Claims

1. A pixel unit including a conversion unit that converts a pixel signal into a converted signal and a holding unit that holds the converted signal, A drive unit that generates a drive signal indicating whether or not to hold the conversion signal in the holding unit, A test unit that generates a test signal for inspecting the holding unit and Includes, In the first operating mode, the drive unit outputs the drive signal to the pixel unit via wiring to the pixel unit, and the holding unit holds and outputs the conversion signal based on the drive signal. In the second operating mode, the test unit outputs the test signal to the pixel unit via the wiring, and the holding unit holds and outputs the test signal. Semiconductor equipment.

2. The system further includes a switching unit that selectively connects the aforementioned wiring to the drive unit or the test unit. In the first operating mode, the switching unit connects the wiring to the drive unit, and the holding unit holds the conversion signal based on the drive signal. In the second operating mode, the switching unit connects the wiring to the test unit, and the holding unit holds the test signal based on the conversion signal. The semiconductor device according to claim 1.

3. Includes a determination unit for determining a failure of the holding part, The test unit outputs an expected signal corresponding to the test signal to the determination unit. In the second operating mode, the determination unit compares the test signal output from the holding unit with the expected signal and determines whether the holding unit is faulty. The semiconductor device according to claim 2.

4. The semiconductor device according to claim 1, comprising a photoelectric conversion element that generates the pixel signal in response to incident light.

5. The semiconductor device according to claim 4, wherein in the second operating mode, the pixel signal is fixed to a predetermined level.

6. The semiconductor device according to claim 5, wherein charging to the photoelectric conversion element is stopped in the second operating mode.

7. The semiconductor device according to claim 5, wherein the photoelectric conversion element is shielded in the second operating mode.

8. The aforementioned photoelectric conversion element includes an avalanche photodiode. The conversion unit includes a gate circuit that converts the pixel signal into a pulsed conversion signal. The holding unit includes a counter for counting the conversion signal. The semiconductor device according to claim 4.

9. The semiconductor device according to claim 2, wherein the pixel portion is arranged in a matrix in the pixel region of the signal processing substrate, and the drive portion is arranged in a region of the signal processing substrate different from the pixel region.

10. The aforementioned test unit includes a first test unit and a second test unit. The aforementioned pixel portion includes a first pixel portion and a second pixel portion arranged adjacent to the first pixel portion. In the second operating mode, the first test unit outputs a first test signal to the first pixel unit, and the second test unit outputs a second test signal different from the first test signal to the second pixel unit. The semiconductor device according to claim 9.

11. The aforementioned retaining part is The first holding portion included in the first pixel portion, The second holding portion included in the second pixel portion, In the first operating mode, a third holding unit holds a signal generated by summing the conversion signal output from the first pixel unit and the conversion signal output from the second pixel unit. The semiconductor device according to claim 10, including the above.

12. In the second operating mode, the first holding unit holds the first test signal, the second holding unit holds the second test signal, and the third holding unit holds the combined test signal generated by summing the first test signal and the second test signal. The first test signal, the second test signal, and the combined test signal each indicate different data. The semiconductor device according to claim 11.

13. The test unit further includes a third test unit that outputs a third test signal. In the second operating mode, the third holding unit holds the second combined test signal generated by summing the first combined test signal and the third test signal. The first combined test signal is generated by adding the first test signal and the second test signal. The semiconductor device according to claim 11.

14. The aforementioned pixel portion includes a first pixel portion and a second pixel portion arranged adjacent to the first pixel portion. In the second operating mode, the test unit outputs the test signal to the first pixel unit and the second pixel unit. The second pixel unit stores the test signal in the holding unit, the first pixel unit reverses the polarity of the test signal to generate a first conversion test signal, and stores the first conversion test signal in the holding unit. The semiconductor device according to claim 9.

15. The aforementioned retaining part is The first holding portion included in the first pixel portion, The second holding portion included in the second pixel portion, In the second operating mode, a third holding unit holds a fourth combined test signal generated by summing the third combined test signal and the test signal output from the second pixel unit. Includes, The third combined test signal is generated by adding the first converted test signal and a second converted test signal, which is generated by converting at least some bits of the test signal. The semiconductor device according to claim 14.

16. The aforementioned pixel portion includes a first pixel portion and a second pixel portion arranged adjacent to the first pixel portion. The aforementioned retaining part is The first holding portion included in the first pixel portion, The second holding portion included in the second pixel portion, Includes, The first holding unit stores the test signal at a first time, and the second holding unit stores the test signal at a second time, which is different from the first time. The semiconductor device according to claim 9.

17. The aforementioned pixel signal is an analog signal. In the first operating mode, the conversion unit compares the pixel signal with a reference signal that changes over time, and outputs the clock signal as the conversion signal to the holding unit for the period until the relative magnitudes of the reference signal and the pixel signal are reversed. The holding unit counts the clock signal. The semiconductor device according to claim 2.

18. Includes a photoelectric conversion element that generates the pixel signal in response to incident light, The aforementioned photoelectric conversion element includes a photodiode. The semiconductor device according to claim 17.

19. An imaging apparatus including a semiconductor device according to any one of claims 1 to 18, A signal processing unit that processes the imaging data output from the imaging device. An imaging system equipped with the following features.

20. The imaging system according to claim 19, wherein the signal processing unit generates a distance image representing distance information to an object based on the imaging data.

21. It is a mobile object, A semiconductor device according to any one of claims 1 to 18, A distance information acquisition unit acquires distance information to an object from the signal output from the semiconductor device, A control unit that controls the moving body based on the distance information. A mobile body characterized by having the following features.

Images