Semiconductor device and method for manufacturing the same

Abstract

To provide a semiconductor device equipped with highly integrated memory cells and a method for manufacturing the same. [Solution] A method for manufacturing a semiconductor device may include the steps of: forming a horizontal array of nanosheet target patterns having an initial sheet horizontally oriented on the upper part of a substrate and sheet expansion tabs located on both sides of the initial sheet; exposing the nanosheet target patterns to a surface treatment in order to form a horizontal array of narrow sheets and a nanosheet insulating layer surrounding the narrow sheets, respectively; and forming horizontal conductive lines on the nanosheet insulating layer that surround the horizontally arranged narrow sheets.

Description

Technical Field

[0001] The present invention relates to a semiconductor device, and more particularly to a semiconductor device including a three-dimensional memory cell and a method of manufacturing the same.

Background Art

[0002] In recent years, in order to cope with the increase in capacity and miniaturization of memory devices, three-dimensional memory devices (3D Memory devices) in which a plurality of memory cells (memory cells) are stacked have been proposed.

Summary of the Invention

Problems to be Solved by the Invention

[0003] Embodiments of the present invention provide a semiconductor device including a highly integrated memory cell and a method of manufacturing the same.

Means for Solving the Problems

[0004] A method of manufacturing a semiconductor device according to an embodiment of the present invention may include forming a horizontal array of a nano-sheet target pattern including an initial sheet horizontally oriented on a substrate and sheet extension tabs located on both side surfaces of the initial sheet; exposing the nano-sheet target pattern to a surface treatment to form a horizontal array of narrow sheets and nano-sheet insulating layers each surrounding the narrow sheet; and forming horizontal conductive lines surrounding the horizontal array of narrow sheets on the nano-sheet insulating layer.

[0005] A method for manufacturing a semiconductor device according to an embodiment of the present invention may include the steps of: forming a mold stack including a vertical arrangement of mold layers on the upper part of a substrate; forming a sacrificial isolation opening in the mold stack; forming a liner on the surface of the sacrificial isolation opening; forming a first linear opening in the mold stack; trimming a first portion of the mold layer through the first linear opening to form a horizontal arrangement of initial sheets; cutting the liner through the first linear opening to form sheet expansion tabs located on both sides of the initial sheets; exposing the initial sheets and sheet expansion tabs to a surface treatment in order to form a horizontal arrangement of narrow sheets and a nanosheet insulating layer surrounding the narrow sheets, respectively; and forming horizontal conductive lines on the nanosheet insulating layer that surround the horizontally arranged narrow sheets.

[0006] A semiconductor device according to an embodiment of the present invention may include: a horizontal arrangement of nanosheets including a first doped region, a second doped region, and channels between the first doped region and the second doped region; a nanosheet insulating layer having an oxidized portion surrounding each of the channels of the nanosheets and a vapor-deposited portion surrounding each of the oxidized portions; horizontal conductive lines oriented horizontally on the nanosheet insulating layer while surrounding the channels of the nanosheets; vertical conductive lines connected to the first doped region of the nanosheets; and data storage elements connected to the second doped region of the nanosheets. [Effects of the Invention]

[0007] This technology can improve the self-alignment margin of the word line in the gate-all-around shape of a three-dimensional memory cell by forming a nanosheet insulating layer through a deposition process and an oxidation process.

[0008] This technology can improve the characteristics of cell transistors by increasing the channel area.

[0009] This technology can improve the reliability of 3D memory devices. [Brief explanation of the drawing]

[0010] [Figure 1A] This is a schematic perspective view of a memory cell according to one embodiment. [Figure 1B] Figure 1A is a schematic cross-sectional view of the memory cell. [Figure 2A] This is a schematic perspective view of a semiconductor device according to one embodiment. [Figure 2B] This is a partial perspective view illustrating the first spacer. [Figure 2C] This is a partial perspective view illustrating the second spacer. [Figure 3] This is a schematic perspective view of a semiconductor device according to an embodiment. [Figure 4A] This is a schematic plan view of a semiconductor device according to an embodiment. [Figure 4B] This is a schematic cross-sectional view along line A-A' in Figure 4A. [Figure 4C] This is a schematic cross-sectional view along line B-B' in Figure 4A. [Figure 5A] These are diagrams and other images illustrating an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 5B] These are diagrams and other images illustrating an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 5C] These are diagrams and other images illustrating an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 6A] These are diagrams and other images illustrating an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 6B] These are diagrams and other images illustrating an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 7A] These are diagrams and other images illustrating an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 7B] These are diagrams and other images illustrating an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 8A] These are diagrams and the like for explaining an example of a method for manufacturing a semiconductor device according to an embodiment. [Figure 8B] These are diagrams and the like for explaining an example of a method for manufacturing a semiconductor device according to an embodiment. [Figure 9A] These are diagrams and the like for explaining an example of a method for manufacturing a semiconductor device according to an embodiment. [Figure 9B] These are diagrams and the like for explaining an example of a method for manufacturing a semiconductor device according to an embodiment. [Figure 10A] These are diagrams and the like for explaining an example of a method for manufacturing a semiconductor device according to an embodiment. [Figure 10B] These are diagrams and the like for explaining an example of a method for manufacturing a semiconductor device according to an embodiment. [Figure 10C] These are diagrams and the like for explaining an example of a method for manufacturing a semiconductor device according to an embodiment. [Figure 11A] These are diagrams and the like for explaining an example of a method for manufacturing a semiconductor device according to an embodiment. [Figure 11B] These are diagrams and the like for explaining an example of a method for manufacturing a semiconductor device according to an embodiment. [Figure 12A] These are diagrams and the like for explaining an example of a method for manufacturing a semiconductor device according to an embodiment. [Figure 12B] These are diagrams and the like for explaining an example of a method for manufacturing a semiconductor device according to an embodiment. [Figure 13A] These are diagrams and the like for explaining an example of a method for manufacturing a semiconductor device according to an embodiment. [Figure 13B] These are diagrams and the like for explaining an example of a method for manufacturing a semiconductor device according to an embodiment. [Figure 13C] These are diagrams and the like for explaining an example of a method for manufacturing a semiconductor device according to an embodiment. [Figure 13D] These are diagrams and the like for explaining an example of a method for manufacturing a semiconductor device according to an embodiment. [Figure 14A] These are diagrams and the like for explaining an example of a method for manufacturing a semiconductor device according to an embodiment. [Figure 14B] These are diagrams and other images illustrating an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 14C] These are diagrams and other images illustrating an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 15A] These are diagrams and other images illustrating an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 15B] These are diagrams and other images illustrating an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 15C] These are diagrams and other images illustrating an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 16A] These are diagrams and other images illustrating an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 16B] These are diagrams and other images illustrating an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 16C] These are diagrams and other images illustrating an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 17A] These are diagrams and other images illustrating an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 17B] These are diagrams and other images illustrating an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 18A] These are diagrams and other images illustrating an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 18B] These are diagrams and other images illustrating an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 19A] These are diagrams and other images illustrating an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 19B] These are diagrams and other images illustrating an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 20A] These are diagrams and other images illustrating an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 20B] These are diagrams and other images illustrating an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 21A] These are diagrams and other images illustrating an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 21B] These are diagrams and other images illustrating an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 22A] These are diagrams and other images illustrating an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 22B] These are diagrams and other images illustrating an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 23A] These are diagrams and other images illustrating an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 23B] These are diagrams and other images illustrating an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 24A] These are diagrams and other images illustrating an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 24B] These are diagrams and other images illustrating an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 25A] These are diagrams and other images illustrating an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 25B] These are diagrams and other images illustrating an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 26] This is a schematic cross-sectional view of a semiconductor device according to another embodiment. [Figure 27A] This is a schematic cross-sectional view of a semiconductor device according to another embodiment. [Figure 27B] This is a schematic cross-sectional view of a semiconductor device according to another embodiment. [Figure 28A] This diagram illustrates a stack assembly according to another embodiment. [Figure 28B] This diagram illustrates a stack assembly according to another embodiment. [Modes for carrying out the invention]

[0011] The embodiments described herein will be explained with reference to the cross-sectional view, plan view, and block diagram, which are ideal schematic representations of the present invention. Therefore, the form of the illustrative figures may be modified due to manufacturing techniques and / or tolerances. Accordingly, the embodiments of the present invention are not limited to the specific forms shown, but also include changes in form generated by the manufacturing process. Accordingly, the areas illustrated in the drawings have schematic attributes, and the shapes of the areas illustrated in the drawings are for illustrating specific forms of the element area and are not intended to limit the scope of the invention.

[0012] The embodiments described later relate to three-dimensional memory cells, which can increase memory cell density and reduce parasitic capacitance by stacking memory cells vertically.

[0013] Figure 1A is a schematic perspective view of a memory cell according to one embodiment. Figure 1B is a schematic cross-sectional view of the memory cell.

[0014] As shown in Figures 1A and 1B, the memory cell MC may include a first conductive line BL, a switching element TR, and a data storage element CAP.

[0015] The first conductive line BL can be vertically oriented along a first direction D1. The first conductive line BL can comprise a bit line. The first conductive line BL can be referred to as a vertical conductive line, a vertically-oriented bit line, a vertically-extended bit line, or a pillar-shaped bit line. The first conductive line BL can contain a conductive material. The first conductive line BL can contain a silicon-based material, a metal-based material, or a combination thereof. The first conductive line BL can contain polysilicon, metal, metal nitride, metal silicide, or a combination thereof. The first conductive line BL can contain polysilicon, titanium nitride, tungsten, or a combination thereof. For example, the first conductive line BL can contain a titanium nitride / tungsten stack (TiN / W) in which titanium nitride and tungsten are stacked in that order.

[0016] The switching element TR has the function of controlling the voltage (or current) supplied to the data storage element CAP during data writing and data reading operations. The switching element TR may comprise a nanosheet (HL), a nanosheet insulating layer GD, and a second conductive line WL. The second conductive line WL may comprise a horizontal conductive line or a horizontal word line, and the nanosheet HL may comprise an active layer. The switching element TR may comprise a transistor, in which case the second conductive line WL may act as a gate or gate electrode. The switching element TR may also be referred to as a nanosheet transistor, access element, or selection element. The second conductive line WL may be referred to as a horizontal gate electrode or a horizontal word line.

[0017] The nanosheet HL can extend along a second direction D2 intersecting a first direction D1. The second conductive line WL can extend horizontally along a third direction D3, which can intersect the first and second directions D1 and D2. The first direction D1 can be the vertical direction, the second direction D2 can be the first horizontal direction, and the third direction D3 can be the second horizontal direction. The nanosheet HL can extend along the first horizontal direction (i.e., the second direction D2), and the second conductive line WL can extend along the second horizontal direction (i.e., the third direction D3). The nanosheet HL can be referred to as the "horizontal layer".

[0018] The nanosheet HL may comprise a channel (CH), a first doped region SR between channel CH and a first conductive line BL, and a second doped region DR between channel CH and a data storage element CAP. The first doped region SR can be electrically connected to the first conductive line BL, and the second doped region DR can be electrically connected to the data storage element CAP. The height of the second doped region DR along the first direction D1 may be greater than the height of channel CH along the first direction D1. The length of the second doped region DR along the second direction D2 may be less than the length of channel CH along the second direction D2. The lengths of the first doped region SR, channel CH, and the second doped region DR along the third direction D3 may be the same as each other.

[0019] A nanosheet HL may comprise a first sheet region (NS) and a second sheet region (WS) arranged horizontally along a second direction D2. The second sheet region WS may extend from the first sheet region NS. The second sheet region WS may have a thickness that gradually increases along the second direction D2 from the first sheet region NS toward the data storage element CAP between the first sheet region NS and the data storage element CAP. The average vertical height (thickness) of the second sheet region WS along the first direction D1 may be greater than the average vertical height (thickness) of the first sheet region NS. Hereinafter, the first sheet region NS will be abbreviated as "Narrower sheet" and the second sheet region WS will be abbreviated as "Wide sheet".

[0020] The narrow sheet NS can be flat-plate shaped. The wide sheet WS can be fan-shaped, i.e., fan-shaped. The thickness of the wide sheet WS may gradually increase along the second direction D2. The narrow sheet NS can be called a flat plate-shaped sheet, and the wide sheet WS can be called a fan-shaped sheet. The upper and lower surfaces of the wide sheet WS may have curvature.

[0021] The first doped region SR and channel CH may be located within a narrow sheet NS, and the second doped region DR may be located within a wide sheet WS. The channel CH formed within the narrow sheet NS may be referred to as a narrow channel or flat channel. A portion of the second doped region DR may extend to be located within the narrow sheet NS. The second doped region DR may include a thick portion located within the wide sheet WS and a thin portion located within the narrow sheet NS. One side of the wide sheet WS and one side of the second doped region DR that are in contact with the data storage element CAP may have a flat side shape.

[0022] The horizontal length of the wide sheet WS along the second direction D2 can be less than the horizontal length of the narrow sheet NS. The narrow sheet NS may be called a long sheet, and the wide sheet WS may be called a short sheet.

[0023] Nanosheet HL can contain semiconductor materials. For example, nanosheet HL can contain polysilicon, single-crystal silicon, germanium, or silicon-germanium. In other embodiments, nanosheet HL can contain oxide semiconductor materials. For example, oxide semiconductor materials can include IGZO (Indium Gallium Zinc Oxide), InSnZnO, ZnSnO, or combinations thereof. In other embodiments, nanosheet HL can contain conductive metal oxides.

[0024] In other embodiments, the nanosheet HL may include a two-dimensional material or a two-dimensional semiconductor material. A two-dimensional semiconductor material may refer to a semiconductor material having a layered structure in which constituent atoms are bonded two-dimensionally. Two-dimensional semiconductor materials have excellent electrical properties and can maintain high mobility without their properties changing significantly even when their thickness is reduced to the nanoscale. For example, the nanosheet HL may include MoS2, WS2, or MoSe2.

[0025] If the nanosheet HL is an oxide semiconductor material, the channel CH may also be made of an oxide semiconductor material, and the first and second doped regions SR and DR may be omitted. The nanosheet HL may also be referred to as the active layer or thin-body.

[0026] The first doped region SR and the second doped region DR may be doped with impurities of the same conductivity type. The first doped region SR and the second doped region DR may be doped with N-type conductivity impurities or P-type conductivity impurities. For example, the conductivity impurities may include arsenic (As), phosphorus (P), boron (B), indium (In), or combinations thereof. The first doped region SR may be electrically connected to the first conductive line BL, and the second doped region DR may be electrically connected to the data storage element CAP. The first and second doped regions SR and DR may be referred to as the "first and second source / drain regions."

[0027] The nanosheet HL can be oriented horizontally along a second direction D2 from a first conductive line BL.

[0028] The second conductive line WL can be a gate all-around structure (GAA). For example, the second conductive line WL can extend along a third direction D3 while surrounding the nanosheet HL. A nanosheet insulating layer GD can be formed between the nanosheet HL and the second conductive line WL. The nanosheet insulating layer GD can surround the nanosheet HL. The second conductive line WL can surround the nanosheet HL on the nanosheet insulating layer GD.

[0029] The second conductive line WL may include metallic materials, metal-base materials, semiconductor materials, or combinations thereof. The second conductive line WL may include molybdenum, molybdenum nitride, ruthenium, titanium nitride, tungsten, polysilicon, or combinations thereof. For example, the second conductive line WL may include a TiN / W stack in which titanium nitride and tungsten are sequentially stacked. The second conductive line WL may include N-type work function materials or P-type work function materials. N-type work function materials may have a low work function lower than 4.5 eV, while P-type work function materials may have a high work function higher than 4.5 eV. The second conductive line WL may include stacks of low-work function materials and high-work function materials.

[0030] The nanosheet insulating layer GD can be located between the nanosheet HL and the second conductive line WL. The nanosheet insulating layer GD may be referred to as the "gate dielectric layer" or the "channel-side dielectric layer". The nanosheet insulating layer GD may include silicon oxide, silicon nitride, metal oxides, metal oxides and nitrides, metal silicates, high-k materials, ferroelectric materials, anti-ferroelectric materials, or combinations thereof. The nanosheet insulating layer GD may include SiO2, Si3N4, HfO2, Al2O3, ZrO2, AlON, HfON, HfSiO, HfSiON, HfZrO, or combinations thereof. The nanosheet insulating layer GD can be formed by thermal oxidation of a semiconductor material. The nanosheet insulating layer GD can be formed by a combination of deposition of the nanosheet insulating material and oxidation of the semiconductor material.

[0031] The data storage element CAP may include a memory element such as a capacitor. The data storage element CAP may be positioned horizontally along a second direction D2 from the switching element TR. The data storage element CAP may comprise a first electrode SN, a second electrode PN on the first electrode SN, and a dielectric layer DE between the first electrode SN and the second electrode PN. The first electrode SN may extend horizontally from a nanosheet HL along the second direction D2. The first electrode SN, the dielectric layer DE, and the second electrode PN may be arranged horizontally along the second direction D2. The first electrode SN may include an inner space and a plurality of outer surfaces, and the inner space of the first electrode SN may include a plurality of inner surfaces. The outer surfaces of the first electrode SN may include a vertical outer surface and a plurality of horizontal outer surfaces. The vertical outer surface of the first electrode SN can extend perpendicularly along the first direction D1, and the horizontal outer surface of the first electrode SN can extend horizontally along the second direction D2 or the third direction D3. The inner space of the first electrode SN can be a three-dimensional space. The dielectric layer DE can conformally cover the inner surface of the first electrode SN. The second electrode PN can be placed in the inner space of the first electrode SN on the dielectric layer DE. A portion of the outer surface of the first electrode SN can be electrically connected to the second doped region DR of the nanosheet HL. The second electrode PN of the data storage element CAP can be connected to the common plate (PL).

[0032] The data storage element CAP can have a three-dimensional structure. The first electrode SN has a three-dimensional structure, but the three-dimensional structure of the first electrode SN can be a horizontal three-dimensional structure oriented along a second direction D2. As an example of a three-dimensional structure, the first electrode SN can have a cylinder shape. The cylinder shape of the first electrode SN can include a cylinder inner surface and a cylinder outer surface. A portion of the cylinder outer surface of the first electrode SN can be electrically connected to a second doped region DR of the nanosheet HL. A dielectric layer DE and a second electrode PN can be placed on the cylinder inner surface and cylinder outer surface of the first electrode SN.

[0033] In other embodiments, the first electrode SN may be pillar-shaped or pyrinder-shaped. The pyrinder shape may refer to a structure in which the pillar shape and the cylinder shape are merged.

[0034] The first electrode SN and the second electrode PN may include metals, noble metals, metal nitrides, conductive metal oxides, conductive noble metal oxides, metal carbides, metal silicides, or combinations thereof. For example, the first electrode SN and the second electrode PN may include titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium dioxide (RuO2), iridium (Ir), iridium oxide (IrO2), platinum (Pt), molybdenum (Mo), molybdenum oxide (MoO), titanium nitride / tungsten (TiN / W) stacks, tungsten nitride / tungsten (WN / W) stacks, titanium silicon nitride / titanium nitride (TiSiN / TiN) stacks, titanium nitride / titanium nitride / tungsten (TiSiN / TiN / W) stacks, or combinations thereof. The second electrode PN may also include combinations of metal-based materials and silicon-based materials. For example, the second electrode PN can be a stack of titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN). In the titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN) stack, silicon germanium can be the gap fill material filling the inside of the first electrode SN, titanium nitride (TiN) can play the role of the second electrode PN of the data storage element CAP, and tungsten nitride can be the low-resistance material.

[0035] The dielectric layer DE may be referred to as a capacitor dielectric layer or a memory layer. The dielectric layer DE may include silicon oxide, silicon nitride, high dielectric constant materials, perovskite materials, or combinations thereof. High dielectric constant materials may include hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium pentoxide (Nb2O5), or strontium titanate (SrTiO3). In other embodiments, the dielectric layer DE may consist of a composite layer comprising two or more of the aforementioned high dielectric constant materials.

[0036] The dielectric layer DE can be formed from a zirconium-based oxide (Zr-base oxide). The dielectric layer DE can be a stacked structure containing zirconium oxide (ZrO2). The dielectric layer DE can include a ZA (ZrO2 / Al2O3) stack or a ZAZ (ZrO2 / Al2O3 / ZrO2) stack. The ZA stack can be a structure in which aluminum oxide (Al2O3) is stacked on top of zirconium oxide (ZrO2). The ZAZ stack can be a structure in which zirconium oxide (ZrO2), aluminum oxide (Al2O3), and zirconium oxide (ZrO2) are stacked sequentially. The ZA stack and ZAZ stack can be referred to as a zirconium oxide-base layer (ZrO2-base layer).

[0037] In other embodiments, the dielectric layer DE can be formed of a hafnium-base oxide (Hf-base oxide). The dielectric layer DE can be a stack structure containing hafnium oxide (HfO2). The dielectric layer DE can include an HA (HfO2 / Al2O3) stack or an HAH (HfO2 / Al2O3 / HfO2) stack. The HA stack can be a structure in which aluminum oxide (Al2O3) is stacked on top of hafnium oxide (HfO2). The HAH stack can be a structure in which hafnium oxide (HfO2), aluminum oxide (Al2O3), and hafnium oxide (HfO2) are stacked sequentially. The HA stack and HAH stack can be referred to as a hafnium oxide-base layer (HfO2-base layer). In ZA stacks, ZAZ stacks, HA stacks, and HAH stacks, aluminum oxide (Al2O3) can have a higher band gap energy than zirconium oxide (ZrO2) and hafnium oxide (HfO2). Aluminum oxide (Al2O3) can have a lower dielectric constant than zirconium oxide (ZrO2) and hafnium oxide (HfO2). Therefore, the dielectric layer DE can contain stacks of high dielectric constant materials and high band gap materials with a higher band gap energy than high dielectric constant materials. In addition to aluminum oxide (Al2O3), the dielectric layer DE can also contain silicon oxide (SiO2) as another high band gap material. Leakage current can be suppressed by including high band gap materials in the dielectric layer DE. High band gap materials can be thinner than high dielectric constant materials.

[0038] In other embodiments, the dielectric layer DE may include a stacked structure in which high dielectric constant materials and high bandgap materials are alternately stacked. For example, the dielectric layer DE may be a ZAZA (ZrO2 / Al2O3 / ZrO2 / Al2O3) stack, a ZAZAZ (ZrO2 / Al2O3 / ZrO2 / Al2O3 / ZrO2) stack, a HAHA (HfO2 / Al2O3 / HfO2 / Al2O3) stack, a HAHAH ((HfO2 / Al2O3 / HfO2 / Al2O3 / HfO2) stack, a HZAZH (HfO2 / ZrO2 / Al2O3 / ZrO2 / HfO2) stack, or a ZHZAZHZ (ZrO2 / HfO2 / ZrO2 / Al2O3 / ZrO2 / HfO2 / ZrO2) stack. The stack may include a stack, an HZHZ (HfO2 / ZrO2 / HfO2 / ZrO2) stack, an AHZAZHA (Al2O3 / HfO2 / ZrO2 / Al2O3 / ZrO2 / HfO2 / Al2O3) stack, or a ZHZAZHZAT (ZrO2 / HfO2 / ZrO2 / Al2O3 / ZrO2 / HfO2 / ZrO2 / Al2O3 / TiO2) stack. In such stack structures, the aluminum oxide (Al2O3) can be thinner than the zirconium oxide (ZrO2) and hafnium oxide (HfO2).

[0039] In other embodiments, the dielectric layer DE may include a high dielectric constant material and a high bandgap material, but may also include a laminated structure in which multiple high dielectric constant materials and multiple high bandgap materials are stacked, or a mixed structure in which the high dielectric constant material and the high bandgap material are intermixed.

[0040] In other embodiments, the dielectric layer DE may include a ferroelectric material, an antiferroelectric material, or a combination thereof. For example, the dielectric layer DE may include HfZrO.

[0041] In other embodiments, the dielectric layer DE may include a combination of a high dielectric material and a ferroelectric material, a combination of a high dielectric material and an antiferroelectric material, or a combination of a high dielectric material or a ferroelectric material and an antiferroelectric material. In other embodiments, the data storage element CAP may further comprise a plurality of interface control layers for leakage current improvement. The interface control layers may include titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium pentoxide (Nb2O5), niobium nitride (NbN), niobium oxynitride (NbON), or a combination thereof. The data storage element CAP may include a first interface control layer, a second interface control layer, or a combination thereof. The first and second interface control layers may be conductive or insulating. The first interface control layer may be formed between the first electrode SN and the dielectric layer DE, and the second interface control layer may be formed between the dielectric layer DE and the second electrode PN. The first and second interface control layers may be the same material or different materials. For example, a structure in which a first interface control layer, a dielectric layer DE, and a second interface control layer are stacked in that order for a data storage element CAP may include an NZHZAZHZATN(Nb2O5 / ZrO2 / HfO2 / ZrO2 / Al2O3 / ZrO2 / HfO2 / ZrO2 / Al2O3 / TiO2 / Nb2O5) stack.

[0042] The data storage element CAP may include a three-dimensional capacitor. The data storage element CAP may include a MIM (Metal-Insulator-Metal) capacitor. The data storage element CAP can also be replaced with other data storage materials. For example, the data storage material may be a thyristor, a phase conversion material, an MTJ (Magnetic Tunnel Junction), or a variable resistor material.

[0043] The memory cell MC may further comprise a first contact node BLC and a second contact node SNC. The first contact node BLC may be located between the first conductive line BL and the nanosheet HL. The first contact node BLC may include a metal-based material or a semiconductor material. For example, the first contact node BLC may include titanium, titanium nitride, tungsten, or a combination thereof. The first contact node BLC may also include doped polysilicon, and the first doped region SR may include impurities diffused from the first contact node BLC. The second contact node SNC may be located between the nanosheet HL and the first electrode SN. The second contact node SNC may include a metal-based material or a semiconductor material. For example, the second contact node SNC may include titanium, titanium nitride, tungsten, or a combination thereof. The second contact node SNC may also include doped silicon, and the second doped region DR may include impurities diffused from the second contact node SNC. The height of the first contact node BLC along the first direction D1 may be less than the height of the second contact node SNC along the first direction D1. The height of the first contact node BLC along the first direction D1 may be greater than the height of the channel CH along the first direction D1. The first and second contact nodes BLC and SNC may include phosphorus-doped polysilicon or arsenic-doped polysilicon. In other embodiments, the second contact node SNC can be selectively grown from a wide sheet WS of a nanosheet HL. The second contact node SNC can be formed by selective epitaxial growth SEG. For example, the second contact node SNC can be a silicon epitaxial layer formed by selective epitaxial growth SEG. The second contact node SNC can be a doped silicon epitaxial layer.

[0044] In other embodiments, the first contact node BLC can also be selectively grown from a narrow sheet WS of a nanosheet HL. The first contact node BLC can be formed by selective epitaxial growth SEG. For example, the first contact node BLC can be a silicon epitaxial layer formed by selective epitaxial growth SEG. The first contact node BLC can be a doped silicon epitaxial layer.

[0045] The first contact node BLC can be a narrower sheet-side contact node, and the second contact node SNC can be a wider sheet-side contact node.

[0046] The nanosheet HL may comprise a first edge and a second edge. The first edge may represent a portion of a first doped region SR electrically connected to a first conductive line BL, and the second edge may represent a portion of a second doped region DR electrically connected to a first electrode SN of the data storage element CAP. The memory cell MC may further comprise an ohmic contact layer BLO between a first contact node BLC and a first conductive line BL. The ohmic contact layer BLO may include a metallic silicide such as titanium silicide or molybdenum silicide.

[0047] The memory cell MC may further comprise a first spacer SP1 and a second spacer SP2. The first spacer SP1 may be positioned between a second conductive line WL and a second doped region DR. The second spacer SP2 may be positioned between a first conductive line BL and a second conductive line WL. The first and second spacers SP1 and SP2 may contain an insulating material. The first and second spacers SP1 and SP2 may contain silicon oxide, silicon nitride, or a combination thereof. The first spacer SP1 may contain silicon nitride. The second spacer SP2 may be a stack of silicon nitride and silicon oxide. The first and second spacers SP1 and SP2 may contain silicon oxide, silicon nitride, or a combination thereof. The first spacer SP1 may contain silicon nitride. The second spacer SP2 may be a stack of silicon nitride and silicon oxide. The first and second spacers SP1 and SP2 may be positioned on both side walls of the second conductive line WL. That is, the first and second spacers SP1 and SP2 can extend along a third direction D3. The first spacer SP1 can surround the second doped region DR of the nanosheet HL, and the second spacer SP2 can surround the first doped region of the nanosheet HL.

[0048] Figure 2A is a schematic diagram of a semiconductor device according to one embodiment. Figure 2B is a partial perspective view illustrating a first spacer. Figure 2C is a partial perspective view illustrating a second spacer.

[0049] Figure 2A shows a horizontal array HMCA, which can have a structure in which multiple memory cells MC, as shown in Figures 1A and 1B, are arranged along a third direction D3.

[0050] As shown in Figures 1A, 1B, and 2A, a horizontal array HMCA can include a horizontal arrangement of memory cells MC. The memory cells MC of the horizontal array HMCA can be horizontally separated along a third direction D3. Each memory cell MC of the horizontal array HMCA can be connected to a first conductive line BL. The memory cells MC of the horizontal array HMCA can share one second conductive line WL. An individual memory cell MC may comprise a first conductive line BL, a nanosheet HL, and a data storage element CAP. The nanosheet HL may comprise a first doped region SR, a channel CH, and a second doped region DR. A first contact node BLC and an ohmic contact layer BLO may be formed between the first doped region SR and the first conductive line BL of the nanosheet HL. A second contact node SNC may be formed between the second doped region DR and the data storage element CAP of the nanosheet HL. The nanosheet HL may be surrounded by a nanosheet insulating layer GD. The second conductive line WL can extend along a third direction D3 while surrounding the channel CH of the nanosheet HL on the nanosheet insulating layer GD.

[0051] The horizontal array HMCA may further include a first spacer SP1 and a second spacer SP2, as shown in Figure 1B.

[0052] As further shown in Figure 2B, the first spacer SP1 can be a single, integrated structure extending along the first direction D1. The first spacer SP1 can surround a portion of the nanosheet HL, i.e., a second doped region DR of the nanosheet HL at the same horizontal level. A portion of the first spacer SP1 can be located between the nanosheets HL, thereby allowing the first spacer SP1 to extend perpendicularly along the first direction D1. The cross-section of the first spacer SP1 can be cup-shaped.

[0053] As further shown in Figure 2C, the second spacer SP2 can extend along a third direction D3 while surrounding a portion of the nanosheet HL, i.e., the first doped region SR of the nanosheet HL at the same horizontal level.

[0054] Figure 3 is a schematic perspective view of a semiconductor device according to one embodiment. Figure 4A is a schematic plan view of a semiconductor device according to one embodiment. Figure 4B is a schematic cross-sectional view along line A-A' in Figure 4A. Figure 4C is a schematic cross-sectional view along line B-B' in Figure 4A. For detailed explanations of overlapping components and the like, please refer to Figures 1A to 2C.

[0055] As shown in Figures 3 and 4A to 4C, the semiconductor device 100 may include a memory cell array MCA. The memory cell array MCA may include a three-dimensional array of memory cells MC. For a detailed description of the memory cells MC, refer to Figures 1A and 1B. The memory cell array MCA may be placed on a substructure LS.

[0056] The lower structure LS can be located at a lower level than the memory cell array MCA.

[0057] The underlying structure LS can be a material suitable for semiconductor processing. The underlying structure LS may include a semiconductor substrate, a conductive material, a dielectric material, a semiconductive material, or a combination thereof. The underlying structure LS may include silicon, monocrystalline silicon, polysilicon, amorphous silicon, silicon germanium, single-crystal silicon germanium, polycrystalline silicon germanium, carbon-doped silicon, epitaxial silicon, combinations thereof, or multilayers thereof. The underlying structure LS may also include other semiconductor materials such as germanium. The underlying structure LS may also comprise a III / V semiconductor substrate, such as a compound semiconductor substrate like GaAs.

[0058] In other embodiments, the substructure LS may comprise a metal wiring structure, an insulating structure, a conductive structure, a bonding pad structure, other memory, or peripheral circuitry. For example, the substructure LS may include a structure in which peripheral circuitry, metal wiring structure, and bonding pad structure are stacked in that order. The memory cell array MCA and the peripheral circuitry of the substructure LS can be bonded by wafer bonding. Wafer bonding may include pad bonding, hybrid bonding, oxide-to-oxide bonding, metal-to-metal bonding, or a combination thereof.

[0059] A discrete memory cell MC may comprise a first conductive line BL, a switching element TR, and a data storage element CAP, and the switching element TR may comprise a second conductive line WL, a nanosheet insulating layer GD, and a nanosheet HL.

[0060] The semiconductor device 100 may include a column array AR1 of memory cells MC and a row array AR2 of memory cells MC. The column array AR1 may include a plurality of memory cells MC stacked vertically along a first direction D1. The memory cells MC in the column array AR1 may share a first conductive line BL. The row array AR2 may include a plurality of memory cells MC arranged horizontally along a third direction D3. The memory cells MC in the row array AR2 may share a second conductive line WL. The first direction D1 may be vertical, and the third direction D3 may be horizontal. The semiconductor device 100 may further include a horizontal level array AR3, which may include a plurality of memory cells MC located at the same horizontal level along a second direction D2. Adjacent memory cells MC in the horizontal level array AR3 may share a first conductive line BL.

[0061] The semiconductor device 100 may include a horizontal array of multiple first conductive lines BL and a vertical array of multiple second conductive lines WL. A vertical array of memory cells MC stacked along a first direction D1 may share one first conductive line BL. A horizontal array of memory cells MC arranged along a third direction D3 may be connected to different first conductive lines BL. A horizontal array of memory cells MC arranged along a third direction D3 may share one second conductive line WL. A vertical array of memory cells MC stacked along a first direction D1 may be connected to different second conductive lines WL.

[0062] The semiconductor device 100 may comprise a first subcell array MCA1 and a second subcell array MCA2. The first subcell array MCA1 and the second subcell array MCA2 may each comprise a three-dimensional array of memory cells MC. The first subcell array MCA1 and the second subcell array MCA2 may share a first conductive line BL. The first conductive line BL may comprise a first vertical conductive line BLA and a second vertical conductive line BLB, and the bottom portions of the first vertical conductive line BLA and the second vertical conductive line BLB may be merged with each other. The combination of the first vertical conductive line BLA and the second vertical conductive line BLB may give the first conductive line BL a U-shape. The memory cells MC of the first subcell array MCA1 may share the first vertical conductive line BLA, and the memory cells MC of the second subcell array MCA2 may share the second vertical conductive line BLB. Thus, the first and second subcell arrays MCA1 and MCA2, adjacent to each other along the second direction D2, can be mirror-type structures sharing the first conductive line BL. When viewed from a top view, the first and second vertical conductive lines BLA and BLB can be rectangular in shape.

[0063] A first inter-cell dielectric layer (IL1) may be placed between adjacent data storage elements CAP along a third direction D3. A second inter-cell dielectric layer (IL2) may be placed between second conductive lines WL stacked perpendicularly along the first direction D1. A third inter-cell dielectric layer (IL3) may be placed between the first electrodes SN of data storage elements CAP stacked perpendicularly along the first direction D1. The first to third inter-cell dielectric layers (IL1, IL2, IL3) may include silicon oxide, silicon oxide-bonded carbide (SiCO), silicon nitride, or a combination thereof. The first inter-cell dielectric layer (IL1) may be referred to as a device isolation layer.

[0064] The memory cell array MCA may further comprise a first contact node BLC and a second contact node SNC. The first contact node BLC may be positioned between the first and second vertical conductive lines BLA, BLB and the nanosheet HL. The first contact node BLC may include a metal-based material or a semiconductor material. For example, the first contact node BLC may include titanium, titanium nitride, tungsten, or a combination thereof. The first contact node BLC may also include doped polysilicon, and the first doped region SR may include impurities diffused from the first contact node BLC. The second contact node SNC may be positioned between the nanosheet HL and the first electrode SN. The second contact node SNC may include a metal-based material or a semiconductor material. For example, the second contact node SNC may include titanium, titanium nitride, tungsten, or a combination thereof. Furthermore, the second contact node SNC may contain doped polysilicon, and the second doped region DR may contain impurities diffused from the second contact node SNC. The height of the first contact node BLC along the first direction D1 may be less than the height of the second contact node SNC along the first direction D1. The height of the first contact node BLC along the first direction D1 may be greater than the height of the channel CH along the first direction D1. The first and second contact nodes BLC and SNC may contain doped polysilicon, for example, phosphorus-doped polysilicon or arsenic-doped polysilicon.

[0065] The memory cell array MCA may further comprise an ohmic contact layer BLO between the first contact node BLC and the first conductive line BL. The ohmic contact layer BLO may include a metallic silicide such as titanium silicide or molybdenum silicide.

[0066] As shown in Figures 1A, 1B, and 2B, the thickness of the first contact node BLC and the ohmic contact layer BLO along the first direction D1 can be even greater than that of the nanosheet HL.

[0067] The memory cell array MCA may further comprise a first spacer SP1 and a second spacer SP2. The first spacer SP1 may be positioned between a second conductive line WL and a second doped region DR. The second spacer SP2 may be positioned between a first conductive line BL and a second conductive line WL. The first and second spacers SP1 and SP2 may include an insulating material. The first and second spacers SP1 and SP2 may include silicon oxide, silicon nitride, or a combination thereof. The first and second spacers SP1 and SP2 may extend along a third direction D3 on both side walls of the second conductive line WL, as shown in Figures 2B and 2C. The first and second spacers SP1 and SP2 may surround a horizontal arrangement of nanosheets HL along the third direction D3. The first spacer SP1 may also extend vertically along the first direction D1.

[0068] The memory cell array MCA may comprise a plurality of second conductive lines WL stacked vertically along a first direction D1. The memory cell array MCA may comprise a plurality of nanosheets HL stacked vertically along the first direction D1. The memory cell array MCA may comprise a plurality of data storage elements CAP stacked vertically along the first direction D1. The memory cell array MCA may comprise a plurality of first conductive lines BL spaced apart along a third direction D3. The memory cell array MCA may comprise dummy second conductive lines WLU, WLL located at a level higher than the highest-level second conductive line WL and at a level lower than the lowest-level second conductive line WL, respectively. The dummy second conductive lines WLU, WLL may have a horizontally extending linear shape.

[0069] The memory cell array (MCA) may include a stack of multiple hard mask layers HM1, HM2, and HM3 located at a higher level than the top-level dummy second conductive line WLU.

[0070] The memory cell array MCA may comprise a plurality of first and second bottom protection layers BT1 and BT2. The first bottom protection layer BT1 can prevent electrical contact between the first conductive line BL and the lower structure LS. The second bottom protection layer BT2 can prevent electrical contact between the data storage element CAP and the lower structure LS. The first and second bottom protection layers BT1 and BT2 may contain insulating material.

[0071] An array separation layer BLF may be located between the first vertical conductive line BLA and the second vertical conductive line BLB of the first conductive line BL. The array separation layer BLF may contain an insulating material. For example, the array separation layer BLF may contain silicon oxide, silicon nitride, silicon oxide with an embedded air gap, or a combination thereof.

[0072] Nanosheets HL of switching elements TR arranged horizontally along a third direction D3 can share one second conductive line WL. Nanosheets HL of switching elements TR arranged horizontally along a third direction D3 can be connected to different first conductive lines BL. Switching elements TR stacked along a first direction D1 can share one first conductive line BL. Switching elements TR arranged horizontally along a third direction D3 can share one second conductive line WL.

[0073] The second electrode PN of the data storage element CAP can be connected to the common plate (PL). The second electrode PN of the data storage element CAP can be merged together to form the common plate PL.

[0074] As further shown in Figure 4C, a vertical arrangement of second conductive lines WL and a vertical arrangement of second intercellular insulating layers IL2 can be formed. The second intercellular insulating layers IL2 can be located between the second conductive lines WL. Dummy second conductive lines WLU and WLL can be provided, located at a level higher than the uppermost second conductive line WL and at a level lower than the lowermost second conductive line WL, respectively. The dummy second conductive lines WLU and WLL can have a horizontally extending linear shape.

[0075] The nanosheet insulating layer GD can surround the nanosheet HL, and the second conductive line WL can surround the nanosheet HL on the nanosheet insulating layer GD.

[0076] The nanosheet insulating layer GD may comprise a vapor-deposited portion GD1 and an oxidized portion GD2. The step of forming the nanosheet insulating layer GD may include the step of forming the vapor-deposited portion GD1 and the step of performing an oxidation process to form the oxidized portion GD2. While the oxidized portion GD2 is being formed, the vapor-deposited portion GD1 may be re-oxidized. In this embodiment, the vapor-deposited portion GD1 and the oxidized portion GD2 of the nanosheet insulating layer GD may be silicon oxide. In other embodiments, the vapor-deposited portion GD1 of the nanosheet insulating layer GD may be a metal oxide and the oxidized portion GD2 may be silicon oxide. In other embodiments, the vapor-deposited portion GD1 of the nanosheet insulating layer GD may include silicon nitride, metal oxidnitride, metal silicate, high-k material, ferroelectric material, anti-ferroelectric material, or a combination thereof. The nanosheet insulating layer GD may contain SiO2, Si3N4, HfO2, Al2O3, ZrO2, AlON, HfON, HfSiO, HfSiON, or combinations thereof.

[0077] The nanosheet insulating layer GD can be formed on all surfaces of the nanosheet HL.

[0078] As will be described later, since the oxidized portion GD2 of the nanosheet insulating layer GD is formed by oxidation of the sheet expansion layer, the spacing HG between nanosheets HL arranged at the same horizontal level may become narrower.

[0079] In this embodiment, the spacing HG between nanosheets HL arranged at the same horizontal level is narrow, which improves the self-aligning contact margin of the second conductive line WL. Furthermore, in this embodiment, the width of the nanosheets HL can be increased, which can increase the area of ​​the channel CH. An increase in the area of ​​the channel CH can improve the characteristics of the switching element TR.

[0080] Figures 5A to 25B are diagrams illustrating an example of a method for manufacturing a semiconductor device according to this embodiment.

[0081] Figure 5A is a plan view of the second mold layer level illustrating the method of forming the mold stack SB, Figure 5B is a cross-sectional view along A-A' in Figure 5A, and Figure 5C is a cross-sectional view along B-B' in Figure 5A.

[0082] As shown in Figures 5A to 5C, a mold stack SB can be formed on the substrate 11. The substrate 11 can be a material suitable for semiconductor processing. The substrate 11 can include a semiconductor substrate, a conductive material, a diode material, a semiconductive material, or a combination thereof. The substrate 11 can comprise silicon, monocrystalline silicon, polysilicon, amorphous silicon, silicon germanium, single-crystal silicon germanium, polycrystalline silicon germanium, carbon-doped silicon, epitaxial silicon, a combination thereof, or multilayers thereof. The substrate 11 may also contain other semiconductor materials such as germanium. The substrate 11 may also comprise a III / V semiconductor substrate, such as a compound semiconductor substrate like GaAs. The mold stack SB can include an alternating stack of a first mold layer 12 and a second mold layer 13.

[0083] To form a mold stack SB, the first mold layer 12 and the second mold layer 13 can be epitaxially grown alternately several times. The first mold layer 12 and the second mold layer 13 can be different semiconductor materials. The first mold layer 12 can include silicon germanium or single-crystal silicon germanium. The second mold layer 13 can include single-crystal silicon. The first mold layer 12 and the second mold layer 13 can be formed by epitaxial growth. The lowest level first mold layer 12 can act as a seed layer during the epitaxial growth process. The first mold layer 12 can be thinner than the second mold layer 13. The first mold layer 12 may include a first epitaxially grown layer, and the second mold layer 13 may include a second epitaxially grown layer.

[0084] In this embodiment, the mold stack SB can be constructed by alternately stacking multiple silicon-germanium layers and multiple single-crystal silicon layers. For example, stacks of silicon-germanium layers / single-crystal silicon layers ("SiGe / Si stacks") can be stacked several times. The first mold layer 12 may be referred to as a "sacrificial layer," and the second mold layer 13 may be referred to as a nanosheet target layer or a recess target layer. The bottommost and topmost layers of the mold stack SB may be the first mold layer 12.

[0085] The mold stack SB can be referred to as a vertical stack. The mold stack SB can be formed by alternately forming multiple sacrificial layers and multiple nanosheet target layers. The sacrificial layers can be silicon germanium layers, and the nanosheet target layers can be single-crystal silicon layers.

[0086] In the mold stack SB, the thickness ratio of the first mold layer 12 to the second mold layer 13 can be varied. For example, the thickness of the first mold layer 12 can be 5 to 20 nm, and the thickness of the second mold layer 13 can be 50 to 80 nm. The number of layers of the first mold layer 12 and the second mold layer 13 in the mold stack SB can be varied. In another embodiment, a triple stack may be defined in the mold stack SB, comprising a first mold layer 12 / second mold layer 13 / third mold layer 12 at the bottom and top. The second mold layer 13 in the triple stack can be thinner than the other second mold layers 13.

[0087] A first hard mask layer 14 can be formed on the mold stack SB. The first hard mask layer 14 may include an oxide-based material, a nitride-based material, a carbon-based material, or a combination thereof as an insulating material. For example, the first hard mask layer 14 may include SiO2, Si3N4, amorphous carbon, or a combination thereof.

[0088] Next, a portion of the mold stack SB can be etched using the first hard mask layer 14 as a barrier to form a plurality of sacrificial isolation openings 15. The sacrificial isolation openings 15 can be initial openings for cell isolation. When viewed from a top view, the sacrificial isolation openings 15 can be rectangular. In other embodiments, the sacrificial isolation openings 15 can be circular or elliptical. In other embodiments, the sacrificial isolation openings 15 can be referred to as "sacrificial isolation trenches". The sacrificial isolation openings 15 can extend vertically along a first direction D1 and can extend elongated along a second direction D2. The sacrificial isolation openings 15 can be arranged at regular intervals along a third direction D3. The bottom surface of the sacrificial isolation openings 15 can extend into the interior of the substrate 11.

[0089] Figure 6A is a plan view of the second mold layer level illustrating the method for forming the pre-sheet extension layer 13L', and Figure 6B is a cross-sectional view along line B-B' in Figure 6A.

[0090] As shown in Figures 6A and 6B, a conformally formed pre-sheet expansion layer 13L' can be formed on the sacrificial separation opening 15 and the first hard mask layer 14. The pre-sheet expansion layer 13L' may contain polysilicon. The pre-sheet expansion layer 13L' may be epi-like polysilicon. Epi-like polysilicon refers to polysilicon grown with the same crystallinity as the epitaxial layer. After forming the pre-sheet expansion layer 13L', an annealing process may be performed, which can enhance the crystallinity. In other embodiments, the pre-sheet expansion layer 13L' may be referred to as a "polysilicon liner". The formation of epi-like polysilicon can be similar to a general polysilicon deposition process. For example, epi-like polysilicon refers to a material grown in epitaxy form on single-crystal silicon when polysilicon is deposited in a thin thickness. The pre-sheet expansion layer 13L' may have a thickness of 30-45 Å.

[0091] A preliminary sacrificial separation layer 16' that fills the sacrificial separation opening 15 can be formed on the preliminary sheet expansion layer 13L'. The preliminary sacrificial separation layer 16' may contain the same material. The preliminary sacrificial separation layer 16' can be formed of an insulating material. The preliminary sacrificial separation layer 16' may have an etching selectivity ratio with respect to the mold stack SB. For example, the preliminary sacrificial separation layer 16' may contain silicon oxide, silicon nitride, oxide-bonded silicon carbide, nitride-bonded silicon carbide, or a combination thereof. The step of forming the preliminary sacrificial separation layer 16' may include the step of forming a sacrificial separation material on the mold stack SB to fill the sacrificial separation opening 15. The step of forming the preliminary sacrificial separation layer 16' may include the step of conformally forming a sacrificial separation liner layer 16A on the sheet expansion layer 13L' and the step of forming a sacrificial separation gap fill layer 16B that fills the sacrificial separation opening 15 on the sacrificial separation liner layer 16A. The sacrificial separation liner layer 16A may be silicon nitride, and the sacrificial separation gap fill layer 16B may be silicon oxide.

[0092] Figure 7A is a plan view of the second mold layer level illustrating the method for forming the sheet expansion layer 13L and the sacrificial separation layer 16, and Figure 7B is a cross-sectional view along line B-B' of Figure 7A.

[0093] As shown in Figures 7A and 7B, a preliminary sacrificial separation layer 16' can be selectively etched to form multiple sacrificial separation layers 16. For example, the steps of planarizing the sacrificial separation gap fill layer 16B and exposing the sacrificial separation liner layer 16A to a washing process can be performed sequentially. Each of the sacrificial separation layers 16 may include a stack of the sacrificial separation liner layer 16A and the sacrificial separation gap fill layer 16B. Next, in order to form the sheet expansion layer 13L, the preliminary sheet expansion layer 13L' can be exposed to the washing process.

[0094] The upper surface of the sacrificial gap fill layer 16B may be at a higher level than the upper surface of the sacrificial separation liner layer 16A, and the upper surface of the sacrificial separation liner layer 16A may be at a higher level than the upper surface of the sheet expansion layer 13L. The upper surface of the sacrificial gap fill layer 16B may be at a higher level than the upper surface of the first hard mask layer 14. A portion of the first hard mask layer 14 may be recessed during the washing process for forming the sacrificial separation liner layer 16A and the sheet expansion layer 13L. The upper surfaces of the sacrificial separation liner layer 16A, the sheet expansion layer 13L, and the first hard mask layer 14 may be at the same level.

[0095] The sacrificial separation layer 16 can extend vertically along a first direction D1 and can extend for a longer distance along a second direction D2. The sacrificial separation layer 16 can be arranged at regular intervals along a third direction D3.

[0096] Each sheet extension layer 13L can be located within the sacrificial separation opening 15. The sheet extension layers 13L can be commonly connected to the first and second mold layers 12 and 13. The sheet extension layers 13L may have a U-shaped outer surface formed within the sacrificial separation opening 15. The U-shaped outer surface of the sheet extension layer 13L can be commonly connected to the second mold layer 13 stacked along the first direction D1. The U-shaped outer surface of the sheet extension layer 13L can be commonly connected to adjacent second mold layers 13 along the second direction D2. When viewed from a top view, each individual sheet extension layer 13L can have a closed loop shape surrounding the side of the individual sacrificial separation opening 15.

[0097] Figure 8A is a plan view of the second mold layer level illustrating the method of forming the sacrificial linear openings 18, 19, and Figure 8B is a cross-sectional view along A-A' in Figure 8A.

[0098] As shown in Figures 8A and 8B, a second hard mask layer 17 can be formed on the mold stack SB and the sacrificial separation layer 16. The second hard mask layer 17 may contain silicon nitride. The second hard mask layer 17 can be formed by etching a second hard mask material using a mask layer such as a photoresist. The second hard mask layer 17 may have multiple line-shaped openings defined.

[0099] The second hard mask layer 17 can be used as an etching barrier to etch a portion of the mold stack SB. This allows for the formation of multiple sacrificial linear openings 18, 19 between the sacrificial isolation layers 16. The sacrificial linear openings 18, 19 may comprise a first sacrificial linear opening 18 and a second sacrificial linear opening 19. When viewed from a top view, the first sacrificial linear opening 18 and the second sacrificial linear opening 19 may be linear openings extending along a third direction D3. The first sacrificial linear opening 18 and the second sacrificial linear opening 19 may extend perpendicularly along a first direction D1. A sacrificial isolation layer 16 may be positioned between the first sacrificial linear opening 18 and the second sacrificial linear opening 19 along a second direction D2. When viewed from a top view, the cross-sections of the first and second sacrificial linear openings 18, 19 may be rectangular. In other embodiments, the cross-sections of the first and second sacrificial linear openings 18, 19 may be circular or elliptical. The first and second sacrificial linear openings 18 and 19 may have a width along the second direction D2 that is smaller than the width along the third direction D3. The first and second sacrificial linear openings 18 and 19 may be referred to as "sacrificial linear trenches". The first sacrificial linear opening 18 and the second sacrificial linear opening 19 may have different horizontal lengths along the third direction D3.

[0100] Figure 9A is a plan view of the second mold layer level illustrating the method for forming the linear sacrificial layers 18L and 19L, and Figure 9B is a cross-sectional view along A-A' in Figure 9A.

[0101] As shown in Figures 9A and 9B, linear sacrificial layers 18L, 19L can be formed to satisfy the first and second sacrificial linear openings 18, 19. The linear sacrificial layers 18L, 19L may comprise a first linear sacrificial layer 18L and a second linear sacrificial layer 19L. When viewed from a top view, the first linear sacrificial layer 18L and the second linear sacrificial layer 19L may be linear in shape extending along a third direction D3. The first linear sacrificial layer 18L and the second linear sacrificial layer 19L may extend perpendicularly along a first direction D1. A sacrificial separation layer 16 may be positioned between the first linear sacrificial layer 18L and the second linear sacrificial layer 19L along a second direction D2. When viewed from a top view, the cross-sections of the first and second linear sacrificial layers 18L, 19L may be rectangular. In other embodiments, the cross-sections of the first and second linear sacrificial layers 18L, 19L may be circular or elliptical. The first and second linear sacrificial layers 18L and 19L may contain the same material. The first and second linear sacrificial layers 18L and 19L may be formed of an insulating material. For example, the first and second linear sacrificial layers 18L and 19L may contain silicon oxide, silicon nitride, oxide-bonded silicon carbide, nitride-bonded silicon carbide, or a combination thereof. The sacrificial separation layer 16 and the first and second linear sacrificial layers 18L and 19L may not be in contact.

[0102] Figure 10A is a plan view of the second mold layer level to illustrate the resetting of the first and second mold layers 12 and 13, and Figure 10B is a cross-sectional view along A-A' in Figure 10A. Figure 10C is a cross-sectional view along B-B' in Figure 10A.

[0103] As shown in Figures 10A to 10C, the first linear sacrificial layer 18L can be selectively removed from the second linear sacrificial layer 19L. This can form a first linear opening 20. When viewed from a top view, the first linear opening 20 may be located horizontally separated from the second linear sacrificial layer 19L along the second direction D2.

[0104] Next, the first mold layer 12 can be selectively recessed through the first linear opening 20.

[0105] To selectively recess the first mold layer 12, the difference in etching selectivity between the first mold layer 12 and the second mold layer 13 can be utilized. The first mold layer 12 can be removed using wet etching or dry etching. For example, if the first mold layer 12 comprises a silicon-germanium layer and the second mold layer 13 comprises a single-crystal silicon layer, the silicon-germanium layer can be etched using an etching solution or etching gas having a selectivity ratio with respect to the single-crystal silicon layer. The first mold layer of its original thickness can remain, as indicated by the drawing reference numeral "12A".

[0106] Next, a portion (the first portion) of the second mold layer 13 can be recessed to form the initial sheet (13P). Wet etching or dry etching can be used to recess the second mold layer 13. The partial recess of the second mold layer 13 can form the original body portion (13A) and the initial sheet 13P. The original body portion 13A can maintain its original thickness (T1), and the initial sheet 13P can have a thickness T2' that is thinner than the original thickness T1. The horizontal lengths of the original body portion 13A and the initial sheet 13P along the second direction D2 can be the same or different from each other. The combination of the original body portion 13A and the initial sheet 13P can be referred to as a "pre-activated layer". The initial sheet 13P can be referred to as a flat plate type sheet or a protruding narrow sheet.

[0107] The recessing process for forming the initial sheet 13P can be referred to as a thinning process or trimming process of the second mold layer 13. The top, bottom, and sides of the second mold layer 13 may be recessed to form the initial sheet 13P. The initial sheet 13P can be referred to as a thin-body active layer. The initial sheet 13P may comprise a single-crystal silicon layer. For example, the recessing process for forming the initial sheet 13P can use HSC1 (Hot SC-1). HSC1 may include a solution of ammonium hydroxide (NH4OH), hydrogen peroxide (H2O2), and water (H2O) mixed in a 1:4:20 ratio. The second mold layer 13 can be selectively etched using such HSC1.

[0108] An initial sheet 13P may be formed by a partial recess process on the second mold layer 13 as described above, and an inter-nano sheet recess (21) may be formed between vertically positioned initial sheets 13P. The upper and lower surfaces of the initial sheets 13P may each have a flat surface. The boundary between the original body portion 13A and the initial sheet 13P may be vertical or have curvature. A first mold layer 12A may be positioned between vertically stacked original body portions 13A.

[0109] A portion of the sheet expansion layer 13L can be cut during or after a partial recess of the second mold layer 13. This allows sheet expansion tabs 13T to be formed at each end of the initial sheet 13P along the third direction D3. A lower sheet expansion tab 13T1 may be formed on the substrate 11, and an upper sheet expansion tab 13T2 adjacent to the first hard mask layer 14 may be formed.

[0110] The combination of the initial sheet 13P and the sheet extension tab 13T can be referred to as a "nanosheet target pattern". The nanosheet target pattern can be arranged vertically along a first direction D1, and the nanosheet target pattern can be arranged horizontally along a third direction D3. That is, by forming the initial sheet 13P and the sheet extension tab 13T, both horizontal and vertical arrangements of the nanosheet target pattern can be formed.

[0111] Figure 11A is a plan view of a narrow sheet level illustrating the method of forming the sacrificial separation layer-level opening 22, and Figure 11B is a cross-sectional view along B-B' of Figure 11A.

[0112] As shown in Figures 11A and 11B, the sacrificial separation layer 16 can be selectively stripped through the inter-nanosheet recess 21. This allows for the formation of a sacrificial separation layer-level opening 22 between the original body portions 13A along a third direction D3.

[0113] The sacrificial separation layer-level opening 22 allows the sides of the first mold layer 12A, the sides of the original body portion 13A, and the sides of the initial sheet 13P to be exposed along the third direction D3.

[0114] After the sacrificial separation layer-level opening 22 is formed, sheet expansion tabs 13T may remain at each end of the initial sheet 13P along a third direction D3. A combination of the initial sheet 13P and the sheet expansion tabs 13T, i.e., a portion of the sacrificial separation layer-level opening 22, may be formed between horizontally aligned nanosheet target patterns.

[0115] Figure 12A is a narrow-sheet level plan view illustrating the method for forming the first inter-cell insulating layer 23. Figure 12B is a cross-sectional view along line B-B' in Figure 12A.

[0116] As shown in Figures 12A and 12B, a first inter-cell insulating layer 23 can be formed in the sacrificial isolation layer-level opening 22. The first inter-cell insulating layer 23 may include an insulating material. The first inter-cell insulating layer 23 may include silicon oxide, silicon nitride, oxide-bonded silicon carbide, or a combination thereof. The step of forming the first inter-cell insulating layer 23 may include the step of forming an insulating material that fills the sacrificial isolation layer-level opening 22 and the step of etching back the insulating material.

[0117] The first inter-cell insulating layer 23 can fill a portion of the sacrificial isolation layer-level opening 22. The sides of the first mold layer 12A and the sides of the original body portion 13A can be covered by the first inter-cell insulating layer 23 along the third direction D3. The first inter-cell insulating layer 23 can expose the sides of the initial sheet 13P. The remaining portion of the sacrificial isolation layer-level opening 22, i.e., the non-gap fill portion, can expose the sides of the initial sheet 13P. The non-gap fill portion can be defined between the initial sheets 13P along the third direction D3.

[0118] After forming the first intercellular insulating layer 23, a nanosheet all-open recess (24) can be formed that opens all of the initial sheets 13P. The nanosheet all-open recess 24 can refer to a combination of an inter-nanosheet recess 21 and a non-gap-fill portion of the first intercellular insulating layer 23. The nanosheet all-open recess 24 can expose all of the multiple initial sheets 13P along the third direction D3. Figure 13A is a narrow-sheet level plan view illustrating the method for forming the nanosheet insulating layer 25. Figure 13B is a cross-sectional view along line A-A' in Figure 13A. Figure 13C is a cross-sectional view along line B-B' in Figure 13A.

[0119] As shown in Figures 13A to 13C, the nanosheet target pattern can be exposed to surface treatment. That is, the initial sheet 13P and the sheet expansion tab 13T can be exposed to surface treatment. This allows for the formation of narrow sheets 13N and a nanosheet insulating layer 25 surrounding the narrow sheets 13N. The nanosheet insulating layer 25 can be referred to as a gate insulating layer. The surface treatment may include a vapor deposition process and an oxidation process. The nanosheet insulating layer 25 can surround the narrow sheets 13N. The narrow sheets 13N can be arranged vertically along a first direction D1 and horizontally along a third direction D3. That is, vertical and horizontal arrangements of narrow sheets 13N can be formed after the nanosheet insulating layer 25 has been formed.

[0120] The nanosheet insulating layer 25 may comprise a vapor-deposited portion 25A and an oxidized portion 25B. The step of forming the nanosheet insulating layer 25 may include the step of forming the vapor-deposited portion 25A on an initial sheet 13P and a sheet expansion tab 13T, and the step of oxidizing the initial sheet 13P and the sheet expansion tab 13T to form the oxidized portion 25B. While the oxidized portion 25B is being formed, the vapor-deposited portion 25A and the oxidized portion 25B of the nanosheet insulating layer 25 may be silicon oxide. In other embodiments, the vapor-deposited portion 25A of the nanosheet insulating layer 25 may be a metal oxide, and the oxidized portion 25B may be silicon oxide. In other embodiments, the vapor-deposited portion 25A of the nanosheet insulating layer 25 may include silicon nitride, metal oxide nitride, metal silicate, high-k material, ferroelectric material, anti-ferroelectric material, or a combination thereof. The nanosheet insulating layer 25 may include SiO2, Si3N4, HfO2, Al2O3, ZrO2, AlON, HfON, HfSiO, HfSiON, or a combination thereof.

[0121] The size of the initial sheet 13P may decrease during the formation of the nanosheet insulating layer 25. This may result in the formation of a narrow sheet 13N. The narrow sheet 13N may have a sheet thickness T2, which can be thinner than the thickness of the initial sheet 13P (T2' in Figure 10C).

[0122] The nanosheet insulating layer 25 can be formed on all surfaces of the narrow sheet 13N. The sheet expansion tab 13T that contacts the first intercellular insulating layer 23 can remain as a dummy sheet expansion tab 13R. That is, the dummy sheet expansion tab 13R can be prevented from being exposed to the deposition and oxidation processes by the first intercellular insulating layer 23 while the nanosheet insulating layer 25 is being formed.

[0123] Since the oxidized portion 25B of the nanosheet insulating layer 25 is formed by oxidation of the sheet expansion tab 13T, the spacing 13G between the narrow sheets 13N may become narrower.

[0124] Figure 13D is a diagram illustrating a method for forming a nanosheet insulating layer 25' according to a comparative example. As shown in Figure 13D, the comparative example can form a nanosheet insulating layer 25' on a preliminary narrow sheet 13P without sheet expansion tabs. The nanosheet insulating layer 25' of the comparative example may comprise a vapor-deposited portion 25A' and an oxidized portion 25B'. The step of forming the nanosheet insulating layer 25' may include the step of forming a vapor-deposited portion 25A on the initial sheet 13P and the step of oxidizing the surface of the initial sheet 13P to form the oxidized portion 25B. The size of the initial sheet 13P may decrease during the formation of the nanosheet insulating layer 25'. This may result in the formation of a narrow sheet 13N' of the comparative example, and the nanosheet insulating layer 25' may be formed on all surfaces of the narrow sheet 13N'.

[0125] The spacing 13G' between narrow sheets 13N' in the comparative example can be even larger than the spacing 13G between narrow sheets 13N in the embodiment. The width W2 of the narrow sheet 13N' in the comparative example can be even smaller than the width W1 of the narrow sheet 13N in the embodiment.

[0126] In this embodiment, since the oxidized portion 25B of the nanosheet insulating layer 25 is formed by oxidation of the sheet expansion tab 13T, the spacing 13G between the narrow sheets 13N can be narrowed.

[0127] In this embodiment, the spacing 13G between narrow sheets 13N is reduced, thereby improving the self-alignment contact margin of the subsequent horizontal conductive line. Furthermore, in this embodiment, the width of the narrow sheets 13N is increased, which increases the channel area, thereby improving the characteristics of the switching element (i.e., the cell transistor).

[0128] Figure 14A is a plan view of a narrow sheet level illustrating the method for forming the first spacer layer 26A. Figure 14B is a cross-sectional view along line A-A' in Figure 14A. Figure 14C is a cross-sectional view along line B-B' in Figure 14A.

[0129] As shown in Figures 14A to 14C, a first spacer layer 26A can be formed on the nanosheet insulating layer 25. The first spacer layer 26A may contain silicon nitride. The first spacer layer 26A can surround and cover the narrow sheet 13N on the nanosheet insulating layer 25. The first spacer layer 26A may be thicker than the nanosheet insulating layer 25.

[0130] A second inter-cell insulating layer 27A can be formed on the first spacer layer 26A. The second inter-cell insulating layer 27A may contain silicon dioxide.

[0131] The nanosheet insulating layer 25 and the first spacer layer 26A can also be formed on the surface of the substrate 11.

[0132] As described above, the first spacer layer 26A may be positioned between the narrow sheets 13N along the third direction D3.

[0133] Figure 15A is a plan view of a narrow sheet level illustrating the method for forming the first spacer 26. Figure 15B is a cross-sectional view along line A-A' in Figure 15A. Figure 15C is a cross-sectional view along line B-B' in Figure 15A.

[0134] As shown in Figures 15A to 15C, the second inter-cell insulating layer 27A can be cut through the first linear opening 20. Subsequently, the first spacer layer 26A can be selectively recessed. The remaining first spacer layer can become the first spacer 26, and the second inter-cell insulating layer can remain as indicated by the drawing reference numeral "27".

[0135] By forming a first spacer 26, linear surrounding recesses 28 that surround the narrow sheets 13N can be formed on the nanosheet insulating layer 25. A second intercellular insulating layer 27 may be located between the vertically arranged linear surrounding recesses 28. Dummy recesses 28U and 28L may be formed at higher and lower levels than the linear surrounding recesses 28.

[0136] The first spacer 26 can surround the narrow sheet 13N at the same horizontal level along the third direction D3. Figure 16A is a plan view of a narrow sheet level illustrating the method for forming the horizontal conductive line 29. Figure 16B is a cross-sectional view along line A-A' in Figure 16A. Figure 16C is a cross-sectional view along line B-B' in Figure 16A.

[0137] As shown in Figures 16A to 16C, a horizontal conductive line 29 can be formed that fills the linear surrounding recess 28. The horizontal conductive line 29 can extend horizontally along the third direction D3.

[0138] The step of forming the horizontal conductive line 29 may include the step of depositing a conductive material onto the nanosheet insulating layer 25 to fill linear surrounding recesses 28 and the step of horizontal etch back the conductive material. Each of the horizontal conductive lines 29 can simultaneously surround the same level of narrow sheet 13N. The horizontal conductive line 29 may include a metal-base material, a semiconductor material, or a combination thereof. The horizontal conductive line 29 may include molybdenum, molybdenum nitride, ruthenium, titanium nitride, tungsten, polysilicon, or a combination thereof. For example, the horizontal conductive line 29 may include a TiN / W stack in which titanium nitride and tungsten are sequentially stacked. The horizontal conductive line 29 may include an N-type work function material or a P-type work function material. The N-type work function material may have a low work function lower than 4.5 eV, and the P-type work function material may have a high work function higher than 4.5 eV. A second intercellular insulating layer 27 may be positioned between multiple horizontal conductive lines 29 along a first direction D1. The horizontal conductive lines 29 surrounding the narrow sheet 13N can be referred to as gate-all-around GAA electrodes. The narrow sheet 13N can be referred to as a nanosheet channel, nanowire, or nanowire channel.

[0139] A lower-level dummy horizontal electrode 29L may be formed on the surface of the substrate 11, and an upper-level dummy horizontal electrode 29U may be formed on the uppermost horizontal conductive line 29. The dummy horizontal electrodes 29L and 29U may have a non-surrounding shape.

[0140] Figure 17A is a plan view of a narrow sheet level illustrating the method for forming the second spacer 30. Figure 17B is a cross-sectional view along line A-A' in Figure 17A.

[0141] As shown in Figures 17A and 17B, a second spacer 30 can be formed on one side of the horizontal conductive line 29. The second spacer 30 may include silicon oxide, silicon nitride, oxide-bonded silicon carbide, an embedded air gap, or a combination thereof. Vapor deposition and etch-back of the spacer material may be performed to form the second spacer 30. The second spacer 30 may include a stack of silicon oxide liners and silicon nitride liners.

[0142] After forming the second spacer 30, a portion of the nanosheet insulating layer 25 can be cut to expose one side of the nanosheet 13N.

[0143] The second spacer 30 can surround the narrow sheet 13N at the same horizontal level along the third direction D3 on one side of the horizontal conductive line 29.

[0144] Figure 18A is a plan view of the narrow sheet level to illustrate the method for forming the narrow sheet cut 32. Figure 18B is a cross-sectional view along line A-A' in Figure 18A.

[0145] As shown in Figures 18A and 18B, a first bottom protective layer 31 can be formed on the surface of the substrate 11. The first bottom protective layer 31 may contain a material having an etching selectivity ratio with respect to the substrate 11. The first bottom protective layer 31 may contain an insulating material. The first bottom protective layer 31 may contain silicon oxide, silicon nitride, oxide-bonded silicon carbide, or a combination thereof.

[0146] Next, one side of the narrow sheet 13N and one side of the nanosheet insulating layer 25 can be cut. This can form a narrow sheet cut 32 that is horizontally recessed from the edge of the second spacer 30. While the narrow sheet cut 32 is being formed, the surface of the substrate 11 can be protected by the first bottom protective layer 31.

[0147] Figure 19A is a narrow sheet-level plan view illustrating the method for forming the first contact node 33. Figure 19B is a cross-sectional view along line A-A' in Figure 19A.

[0148] As shown in Figures 19A and 19B, a first contact node 33 can be selectively formed from the edge of the narrow sheet 13N. The first contact node 33 can be formed via selective epitaxial growth SEG. The first contact node 33 can be an epitaxial layer of a silicon layer. The first contact node 33 can be a doped silicon epitaxial layer.

[0149] A first doped region 34 can be formed within one side surface of the narrow sheet 13N. A heat treatment process can be performed to form the first doped region 34, thereby allowing the dopant to diffuse from the first contact node 33.

[0150] Figure 20A is a plan view of a narrow sheet level illustrating the method for forming vertical conductive lines 36A and 36B. Figure 20B is a cross-sectional view along line A-A' in Figure 20A.

[0151] As shown in Figures 20A and 20B, vertical conductive lines 36A and 36B may be formed on the first contact node 33. An ohmic contact layer 35 may be formed on the first contact node 33 before the vertical conductive lines 36A and 36B are formed. The ohmic contact layer 35 may contain a metallic silicide such as titanium silicide or molybdenum silicide.

[0152] The steps for forming the vertical conductive lines 36A and 36B may include a step of depositing a metallic material and a step of etching the metallic material. The bottom portions of adjacent vertical conductive lines 36A and 36B can be interconnected.

[0153] The vertical conductive lines 36A and 36B can be vertically oriented along a first direction D1. The vertical conductive lines 36A and 36B can include bit lines. The vertical conductive lines 36A and 36B can include metals, metal-base materials, or combinations thereof. The vertical conductive lines 36A and 36B can include metals, metal nitrides, metal silicides, or combinations thereof. The vertical conductive lines 36A and 36B can include titanium nitride, tungsten, or combinations thereof. For example, the vertical conductive lines 36A and 36B can include titanium nitride / tungsten stacks (TiN / W) with titanium nitride and tungsten stacked in that order. The bottom portions of the vertical conductive lines 36A and 36B can be merged with each other.

[0154] Figure 21A is a nanosheet-level plan view illustrating the method for forming the second linear opening 39. Figure 21B is a cross-sectional view along A-A' in Figure 21A.

[0155] As shown in Figures 21A and 21B, an array separation layer 37 can be formed between the vertical conductive lines 36A and 36B. The array separation layer 37 may contain an insulating material. The array separation layer 37 can fill the space between the vertical conductive lines 36A and 36B. The array separation layer 37 may contain silicon dioxide.

[0156] The step of forming the array separation layer 37 may include a step of depositing an insulating material and a planarization step.

[0157] Next, the second linear sacrificial layer 19L can be selectively removed using the third hard mask layer 38. This can then form the second linear opening 39.

[0158] After forming the second linear opening 39, the first mold layer 12A can be selectively recessed through the second linear opening 39. To selectively recess the first mold layer 12A, the difference in etching selectivity between the first mold layer 12A and the original body portion 13A can be utilized. The first mold layer 12A can be removed using wet etching or dry etching. For example, if the first mold layer 12A comprises a silicon-germanium layer and the original body portion 13A comprises a single-crystal silicon layer, the silicon-germanium layer can be etched using an etching solution or etching gas that has a selectivity ratio with respect to the single-crystal silicon layer.

[0159] Next, the original body section 13A can be recessed. To recess the original body section 13A, wet etching or dry etching can be used. The original body section 13A may have a thinner vertical thickness, like "13S". Hereinafter, this will be abbreviated as recessed body section 13S.

[0160] Inter-body recesses 40 can be formed between vertically arranged recessed body sections 13S.

[0161] Figure 22A is a nanosheet-level plan view illustrating the method for forming nanosheet HL. Figure 22B is a cross-sectional view along line A-A' in Figure 22A.

[0162] As shown in Figures 22A and 22B, a third inter-cell insulating layer 41 can be formed that fills the inter-body recess 40. The third inter-cell insulating layer 41 may contain silicon oxide.

[0163] After forming the third inter-cell insulating layer 41, a second bottom protective layer 42 can be formed at the bottom of the second linear opening 39. The second bottom protective layer 42 may include a material having an etching selectivity ratio with respect to the substrate 11. The second bottom protective layer 42 may include an insulating material. The second bottom protective layer 42 may include silicon oxide, silicon nitride, oxide-bonded silicon carbide, or a combination thereof.

[0164] After forming the second bottom protective layer 42, a storage opening (43) may be formed by horizontal resetting of the recessed body portion 13S. The storage opening 43 may be referred to as a capacitor opening. Horizontal resetting of the recessed body portion 13S may result in a nanosheet HL. Each nanosheet HL may comprise a first doped region 34, a narrow sheet 13N, and a wide sheet 13W. The wide sheet 13W of the nanosheet HL may refer to the recessed body portion 13S remaining after resetting. The average vertical height of the wide sheet 13W of the nanosheet HL along the first direction D1 may be greater than the average vertical height of the narrow sheet 13N. The thickness of the wide sheet 13W of the nanosheet HL may gradually increase along the second direction D2. The horizontal length of the wide sheet 13W along the second direction D1 may be less than the horizontal length of the narrow sheet 13N. The wide sheet 13W of the nanosheet HL can be fan-shaped. The wide sheet 13W can be called a fan-shaped sheet, and the narrow sheet 13N can be called a flat plate-type sheet.

[0165] To form a nanosheet HL comprising a wide sheet 13W, the recessed body portion 13S can be isotropically etched or anisotropically etched. One side of the wide sheet 13W, i.e., the side exposed by the storage opening 43, can be flat.

[0166] One side of the wide sheet 13W can have various shapes. For example, one side of the wide sheet 13W can have a rounded concave shape, a rounded convex shape, an angled concave shape, or an angled convex shape.

[0167] The second bottom protective layer 42 and the lowest level third inter-cell insulating layer 41 can prevent loss of the substrate 11 during the recessing process of the recessed body portion 13S. A storage opening 43 may be located between the third inter-cell insulating layer 41 along the first direction D1.

[0168] In another embodiment, the horizontal recessing of the recessed body portion 13S for forming the wide seat 13W can be stopped in the boundary area between the narrow seat 13N and the wide seat 13W.

[0169] The first spacer 26 can surround wide sheets 13W arranged along the third direction D3 at the same horizontal level, and the second spacer 30 can surround narrow sheets 13N arranged along the third direction D3 at the same horizontal level.

[0170] Figure 23A is a nanosheet-level plan view illustrating the method for forming the first electrode 47. Figure 23B is a cross-sectional view along line A-A' in Figure 23A.

[0171] As shown in Figures 23A and 23B, a pre-cleaning step may be performed on the surface of the wide sheet 13W.

[0172] A second contact node 44 can be formed on the wide sheet 13W. The step of forming the second contact node 44 may include selective epitaxial growth (SEG). For example, a semiconductor material can be grown from the side of the wide sheet 13W via selective epitaxial growth SEG. The second contact node 44 may include SEG Si. Since the wide sheet 13W contains single-crystal silicon, a silicon layer can be epitaxially grown along the crystal plane of the side of the wide sheet 13W.

[0173] The second contact node 44 may contain a dopant. When growing a silicon layer using selective epitaxial growth SEG, dopant doping can be performed in-situ. Therefore, the second contact node 44 can be a doped epitaxial layer. The second contact node 44 may contain an N-type dopant as the dopant. The N-type dopant may contain phosphorus, arsenic, antimony, or a combination thereof. The second contact node 44 may contain a phosphorus-doped silicon epitaxial layer by selective epitaxial growth, i.e., a doped SEG SiP. In other embodiments, the second contact node 44 may be formed via deposition and etch-back of doped polysilicon.

[0174] The second contact node 44 can be located between the vertically stacked third inter-cell insulating layers 41. The second contact node 44 can correspond to the second contact node SNC in Figure 4B.

[0175] A second doped region 45 may be formed within the wide sheet 13W. A heat treatment process can be performed to form the second doped region 45, thereby allowing the dopant to diffuse from the second contact node 44.

[0176] A channel 46 may be defined between the first doped region 34 and the second doped region 45. The horizontal arrangement of the first doped region 34, the channel 46, and the second doped region 45 can form a nanosheet HL.

[0177] Each nanosheet HL may comprise a first doped region 34, a second doped region 45, and a channel 46. The first doped region 34 and the channel 46 may be formed within a narrow sheet 13N, and the second doped region 45 may be formed within a wide sheet 13W. A portion of the second doped region 45 may extend within the narrow sheet 13N. One side of the second doped region 45 of the nanosheet HL may be connected to a channel 46, and the other side of the second doped region 45 of the nanosheet HL may be connected to a second contact node 44.

[0178] The first spacer 26 can surround a second doped region 45 at the same horizontal level, arranged along the third direction D3, and the second spacer 30 can surround a first doped region 34 at the same horizontal level, arranged along the third direction D3. The horizontal conductive line 29 can surround a channel 46 at the same horizontal level, arranged along the third direction D3.

[0179] In other embodiments, an ohmic contact layer containing a metal silicide may be further formed after the formation of the second contact node 44.

[0180] As described above, the second mold layer 13 of the mold stack SB may have nanosheets HL formed by subsequent selective re-cleansing, and each nanosheet HL may comprise a narrow sheet 13N and a wide sheet 13W. A first doped region 34 and channel 46 may be formed within the narrow sheet 13N, and a second doped region 45 may be formed within the wide sheet 13W.

[0181] Next, first electrodes 47 of the data storage element can be formed on the second contact node 44. The first electrodes 47 may be in a horizontally oriented cylindrical shape. Each of the first electrodes 47 may be positioned within the storage opening 43. Adjacent first electrodes 47 along the second direction D2 can be separated by a second linear opening 39. Adjacent first electrodes 47 along the first direction D1 can be separated from each other by a third inter-cell insulating layer 41. The steps of forming the first electrodes 47 may include a metal material deposition step, a sacrificial material gap filling step, and a step of separating the metal material vertically / horizontally. The sacrificial material may include oxides or polysilicon.

[0182] The first electrode 47 may include an inner space and a plurality of outer surfaces, and the inner space of the first electrode 47 may include a plurality of inner surfaces. The outer surfaces of the first electrode 47 may include a vertical outer surface and a plurality of horizontal outer surfaces. The vertical outer surface of the first electrode 47 may extend vertically along a first direction D1, and the horizontal outer surface of the first electrode 47 may extend horizontally along a second direction D2 or a third direction D3. The inner space of the first electrode 47 may be a three-dimensional space. The first electrode 47 may be cylindrical in shape.

[0183] Of the outer surfaces of the first electrode 47, the vertical outer surface can be electrically connected to the nanosheet HL and the second contact node 44.

[0184] The first electrode 47 may include metals, noble metals, metal nitrides, conductive metal oxides, conductive noble metal oxides, metal carbides, metal silicides, or combinations thereof. For example, the first electrode 47 may include titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium dioxide (RuO2), iridium (Ir), iridium oxide (IrO2), platinum (Pt), molybdenum (Mo), molybdenum oxide (MoO), titanium nitride / tungsten (TiN / W) stacks, tungsten nitride / tungsten (WN / W) stacks, titanium silicon nitride / titanium nitride (TiSiN / TiN) stacks, or combinations thereof.

[0185] Figure 24A is a nanosheet-level plan view illustrating the partial reduction of the first and third intercellular insulating layers 23 and 41. Figure 24B is a cross-sectional view along A-A' in Figure 24A.

[0186] As shown in Figures 24A and 24B, portions of the first and third inter-cell insulating layers 23 and 41 can be horizontally recessed (see reference numeral 41R). This allows the outer wall of the first electrode 47 to be partially exposed. The first electrode 47 can have a semi-cylindrical shape. The horizontal recess depth of the third inter-cell insulating layer 41 can be such that the second contact node 44 is not exposed. The semi-cylindrical shape of the first electrode 47 can include an inner cylinder surface and a semi-cylindrical outer surface. The semi-cylindrical outer surface of the first electrode 47 can be exposed along the first direction D1 and the third direction D3.

[0187] Figure 25A is a nanosheet-level plan view illustrating a method for forming the second electrode 49. Figure 25B is a cross-sectional view along A-A' in Figure 25A. As shown in Figures 25A and 25B, a dielectric layer 48 and a second electrode 49 can be sequentially formed on the first electrode 47. The first electrode 47, the dielectric layer 48, and the second electrode 49 can form a data storage element CAP. The second electrode 49 of the data storage element CAP can be merged to form a common plate PL.

[0188] A dielectric layer 48 and a second electrode 49 may be arranged on the inner surface of the cylinder of the first electrode 47. Parts of the dielectric layer 48 and the second electrode 49 may extend so as to be located on the semi-cylinder outer surface of the first electrode 47. The second electrode 49 may extend perpendicularly along the first direction D1.

[0189] The dielectric layer 48 may be referred to as a capacitor dielectric layer or a memory layer. The dielectric layer 48 may include silicon oxide, silicon nitride, high dielectric constant materials, ferroelectric materials, antiferroelectric materials, perovskite materials, or combinations thereof. The dielectric layer 48 may also include hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium pentoxide (Nb2O5), or strontium titanate (SrTiO3). The dielectric layer 48 consists of ZA (ZrO2 / Al2O3) stacks, ZAZ (ZrO2 / Al2O3 / ZrO2) stacks, ZAZA (ZrO2 / Al2O3 / ZrO2 / Al2O3) stacks, ZAZAZ (ZrO2 / Al2O3 / ZrO2 / Al2O3 / ZrO2) stacks, HAHA (HfO2 / Al2O3 / HfO2 / Al2O3) stacks, HAHAH (HfO2 / Al2O3 / HfO2 / Al2O3 / HfO2) stacks, and HZAZH (HfO2 / ZrO2 / Al2O3 / ZrO This may include a 2 / HfO2) stack, a ZHZAZHZ(ZrO2 / HfO2 / ZrO2 / Al2O3 / ZrO2 / HfO2 / ZrO2) stack, a HZHZ(HfO2 / ZrO2 / HfO2 / ZrO2) stack, an AHZAZHA(Al2O3 / HfO2 / ZrO2 / Al2O3 / ZrO2 / HfO2 / Al2O3) stack, or a ZHZAZHZAT(ZrO2 / HfO2 / ZrO2 / Al2O3 / ZrO2 / HfO2 / ZrO2 / Al2O3 / TiO2) stack.

[0190] The second electrode 49 may include metals, noble metals, metal nitrides, conductive metal oxides, conductive noble metal oxides, metal carbides, metal silicides, or combinations thereof. For example, the second electrode 49 may include titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium dioxide (RuO2), iridium (Ir), iridium oxide (IrO2), platinum (Pt), molybdenum (Mo), molybdenum oxide (MoO), titanium nitride / tungsten (TiN / W) stacks, tungsten nitride / tungsten (WN / W) stacks, titanium silicon nitride / titanium nitride (TiSiN / TiN) stacks, titanium silicon nitride / titanium nitride / tungsten (TiSiN / TiN / W) stacks, or combinations thereof. The second electrode 49 may also include a combination of a metal-based material and a silicon-based material. For example, the second electrode 49 can be stacked in the order of titanium nitride / tungsten / polysilicon.

[0191] In other embodiments, the interface control layer may further include multiple interface control layers for leakage current improvement between the first electrode 47 and the dielectric layer 48 and between the second electrode 49 and the dielectric layer 48. The interface control layer may include titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium pentoxide (Nb2O5), niobium nitride (NbN), niobium oxynitride (NbON), or a combination thereof. The data storage element CAP may include the first interface control layer, the second interface control layer, or a combination thereof. The first interface control layer and the second interface control layer may be conductive or insulating. The first interface control layer may be formed between the first electrode 47 and the dielectric layer 48, and the second interface control layer may be formed between the dielectric layer 48 and the second electrode 49. The first interface control layer and the second interface control layer may be the same material or different materials. For example, a structure in which a first interface control layer, a dielectric layer 48, and a second interface control layer of a data storage element CAP are stacked in that order may include an NZHZAZHZATN(Nb2O5 / ZrO2 / HfO2 / ZrO2 / Al2O3 / ZrO2 / HfO2 / ZrO2 / Al2O3 / TiO2 / Nb2O5) stack.

[0192] In other embodiments, the resetting of the first and third inter-cell insulating layers 23 and 41 in Figure 24B may be omitted. Subsequently, a dielectric layer 48 and a second electrode 49 may be formed, as shown in Figure 25B. This may form a data storage element CAP having a concave first electrode 49.

[0193] According to the embodiment described above, the area of ​​the channel 46 can be increased by the sheet expansion tab 13T. Furthermore, because the sheet expansion tab 13T is formed, even if the spacing between nanosheets HL increases due to etching or other processes such as cleaning, connection failures between the horizontal conductive lines 29 can be prevented.

[0194] Figure 26 is a schematic cross-sectional view of a semiconductor device according to another embodiment. The semiconductor device 200 in Figure 26 can be similar to the semiconductor device 100 in Figures 3 to 4C. Figure 26 can be another embodiment along A-A' in Figure 4A.

[0195] As shown in Figure 26, the semiconductor device 200 may include a memory cell array MCA located on the upper part of a lower structure LS, and the memory cell array MCA may include a first subcell array MCA1 and a second subcell array MCA2. The first subcell array MCA1 may include a three-dimensional array of first memory cells MC1. The second subcell array MCA2 may include a three-dimensional array of second memory cells MC2. The first subcell array MCA1 may include vertical and horizontal arrangements of the first memory cells MC1, and the second subcell array MCA2 may include vertical and horizontal arrangements of the second memory cells MC2.

[0196] An individual first memory cell MC1 may comprise a first vertical conductive line BLA, a data storage element CAP, a nanosheet HL between the first vertical conductive line BLA and the data storage element CAP, a second conductive line WL surrounding the nanosheet HL, and a nanosheet insulating layer GD between the nanosheet HL and the second conductive line WL. An individual second memory cell MC2 may comprise a second vertical conductive line BLB, a data storage element CAP, a nanosheet HL between the first vertical conductive line BLA and the data storage element CAP, a second conductive line WL surrounding the nanosheet HL, and a nanosheet insulating layer GD between the nanosheet HL and the second conductive line WL. The nanosheet insulating layer GD may comprise a deposited portion GD1 and an oxidized portion GD2, as shown in Figure 4C. The data storage element CAP may comprise a first electrode SN, a dielectric layer DE, and a second electrode PN, and the second electrode PN of the data storage element CAP may be merged to form a common plate PL. The nanosheet HL may comprise a first doped region SR, a channel CH, and a second doped region DR.

[0197] Each of the first and second memory cells MC1 and MC2 may further comprise a first spacer SP1, a second spacer SP2, a first contact node BLC, a second contact node SNC, and an ohmic contact layer BLO. The first contact node BLC can be positioned between the first and second vertical conductive lines BLA and BLB and the nanosheet HL. The second contact node SNC can be positioned between the nanosheet HL and the first electrode SN.

[0198] A first inter-cell insulating layer IL1 may be placed between adjacent data storage elements CAP along a third direction D3. A second inter-cell insulating layer IL2 may be placed between second conductive lines WL stacked vertically along a first direction D1. A third inter-cell insulating layer IL3 may be placed between the first electrodes SN of data storage elements CAP stacked vertically along a first direction D1.

[0199] The memory cell array MCA may include dummy second conductive lines WLU and WLL located at a level higher than the highest-level second conductive line WL and at a level lower than the lowest-level second conductive line WL, respectively. The dummy second conductive lines WLU and WLL may have a horizontally extending linear shape.

[0200] A memory cell array (MCA) can include a stack of multiple hard mask layers HM1, HM2, and HM3 located at a level higher than the top-level second conductive line WL.

[0201] The memory cell array MCA may include a plurality of first and second bottom protection layers BT1 and BT2. The first bottom protection layer BT1 can prevent electrical contact between the first conductive line BL and the lower structure LS. The second bottom protection layer BT2 can prevent electrical contact between the data storage element CAP and the lower structure LS.

[0202] The first memory cell MC1 of the first subcell array MCA1 can share the first vertical conductive line BLA. The second memory cell MC2 of the second subcell array MCA2 can share the second vertical conductive line BLB. The first vertical conductive line BLA and the second vertical conductive line BLB can be electrically isolated. An array isolation layer BLF may be located between the first vertical conductive line BLA and the second vertical conductive line BLB. The bottom portions of the first and second vertical conductive lines BLA and BLB can be separated from each other by a first bottom protective layer BT1.

[0203] The first contact nodes BLC of the first and second subcell arrays MCA1 and MCA2 can be selectively grown from nanosheets HL. The first contact node BLC can be formed by selective epitaxial growth SEG. For example, the first contact node BLC can be a silicon epitaxial layer formed by selective epitaxial growth SEG. The first contact node BLC can be a doped silicon epitaxial layer. The first doped region SR can contain impurities diffused from the first contact node BLC.

[0204] As described above, the semiconductor device 200 can electrically isolate the first vertical conductive line BLA of the first subcell array MCA1 and the second vertical conductive line BLB of the second subcell array MCA2.

[0205] Figures 27A and 27B are schematic cross-sectional views of a semiconductor device according to another embodiment.

[0206] As shown in Figure 27A, the semiconductor device 300 may comprise a memory cell array MCA, a peripheral circuit section PERI, and a bonding interface BS. The bonding interface BS may be located between the memory cell array MCA and the peripheral circuit section PERI. The semiconductor device 300 may have the memory cell array MCA positioned at a higher level than the peripheral circuit section PERI. The semiconductor device 300 may also be referred to as a PUC (Peri Under Cell array) structure. The memory cell array MCA may comprise a backgrounded substrate and an array of memory cells. For example, as shown in Figure 25B, after forming the data storage element CAP, the substrate 11 may be flipped over via a wafer flip, and then the back side of the substrate 11 may be partially background.

[0207] As shown in Figure 27B, the semiconductor device 301 may comprise a memory cell array MCA, a peripheral circuit section PERI, and a bonding interface BS. The bonding interface BS may be located between the memory cell array MCA and the peripheral circuit section PERI. The semiconductor device 301 may have the memory cell array MCA positioned at a lower level than the peripheral circuit section PERI. The semiconductor device 301 may also be referred to as a CUP (Cell array Under Peri) structure. The step of forming the peripheral circuit section PERI may include the steps of forming a plurality of control circuits on a peripheral circuit board and forming multilayer level wiring on the control circuits.

[0208] In Figures 27A and 27B, the bonding interface BS may include pad bonding, hybrid bonding, oxide-to-oxide bonding, metal-to-metal bonding, or a combination thereof. Hybrid bonding may refer to a combination of pad bonding and oxide-to-oxide bonding. A pad bonding method may include the steps of forming cell bonding pads for a memory cell array, forming peripheral circuit bonding pads for peripheral circuit sections, performing a wafer flip so that the cell bonding pads and peripheral circuit bonding pads face each other, and performing wafer bonding.

[0209] The semiconductor device 300 in Figure 27A can perform a wafer flip on a substrate on which a memory cell array is formed so that the cell bonding pad and peripheral circuit bonding pad face each other, after the cell bonding pad and peripheral circuit bonding pad have been formed respectively. The semiconductor device 301 in Figure 27B can perform a wafer flip on a substrate on which a peripheral circuit portion has been formed so that the cell bonding pad and peripheral circuit bonding pad face each other, after the cell bonding pad and peripheral circuit bonding pad have been formed respectively.

[0210] Figures 28A and 28B illustrate a stack assembly according to another embodiment.

[0211] As shown in Figure 28A, the stack assembly 400 may comprise an assembly of semiconductor dies. For example, the stack assembly 400 may comprise a first semiconductor die BSD and a plurality of second semiconductor dies 401. The first semiconductor die BSD may comprise a logic circuit. Each of the second semiconductor dies 401 may comprise a memory cell array according to the embodiments described above.

[0212] Each of the second semiconductor dies 401 may have a stacked structure comprising a memory cell array and a peripheral circuit section, for example, semiconductor device 300 in Figure 27A or semiconductor device 301 in Figure 27B. The logic circuit of the first semiconductor die BSD and the peripheral circuit section of the second semiconductor die 401 may be different from each other. The second semiconductor die 401 may be chip-level or wafer-level.

[0213] The second semiconductor die 401 can be electrically interconnected via multiple through-silicon vias (TSVs) and bonding interfaces (CBS). The first semiconductor die BSD and the lowest-level second semiconductor die 401 can be electrically interconnected via bonding interfaces (CBS). The second semiconductor die 401 may be referred to as a core die, semiconductor chip, or memory chip.

[0214] Bonding interfaces (CBS) can include micro-bump, pad bonding, hybrid bonding, oxide-to-oxide bonding, metal-to-metal bonding, or a combination thereof.

[0215] As shown in Figure 28B, the stack assembly 500 may comprise an assembly of semiconductor dies. For example, the stack assembly 500 may comprise a first semiconductor die BSD, a plurality of second semiconductor dies 501, and a plurality of third semiconductor dies 502. The first semiconductor die BSD may comprise a logic circuit. Each of the second semiconductor die 501 and the third semiconductor die 502 may comprise a memory cell array according to the embodiments described above. The second semiconductor die 501 and the third semiconductor die 502 may have different structures from each other.

[0216] Each of the second semiconductor dies 501 may include a semiconductor device 300 as shown in Figure 27A, in which a memory cell array is stacked on top of a peripheral circuit section, and each of the third semiconductor dies 502 may include a semiconductor device 301 as shown in Figure 27B, in which a peripheral circuit section is stacked on top of a memory cell array.

[0217] In other embodiments, each of the second semiconductor dies 501 may include a semiconductor device 301 as shown in Figure 27B, in which a peripheral circuit section is stacked on top of the memory cell array, and each of the third semiconductor dies 502 may include a semiconductor device 300 as shown in Figure 27A, in which a memory cell array is stacked on top of the peripheral circuit section.

[0218] The logic circuit of the first semiconductor die BSD and the peripheral circuit sections of the second and third semiconductor dies 501 and 502 can be different from each other. The second and third semiconductor dies 501 and 502 can be chip-level or wafer-level.

[0219] The second and third semiconductor dies 501 and 502 can be electrically interconnected via multiple through-silicon vias (TSVs) and bonding interfaces (CBS). The first semiconductor die (BSD) and the lowest-level second semiconductor die 501 can be electrically interconnected via bonding interfaces (CBS). The second and third semiconductor dies 501 and 502 may be referred to as core dies, semiconductor chips, or memory chips.

[0220] Bonding interfaces (CBS) can include micro-bump, pad bonding, hybrid bonding, oxide-to-oxide bonding, metal-to-metal bonding, or a combination thereof.

[0221] In other embodiments, wafer flipping and backgrinding may be performed to form a bonding interface CBS. For example, a second semiconductor die 501 and / or a third semiconductor die 502 may be wafer flipped and backgrinded.

[0222] The stack assemblies 400 and 500 shown in Figures 28A and 28B can be high-bandwidth memories.

[0223] The present invention described above is not limited by the embodiments described above and the accompanying drawings, and it will be apparent to those with ordinary skill in the art to which the present invention pertains that various substitutions, modifications, and changes are possible without departing from the technical spirit of the present invention. [Explanation of Symbols]

[0224] BL First conductive line WL Second conductive line HL Nanosheet GD Nanosheet Insulating Layer GD1 Vapor deposition part GD2 Oxidation Unit CH Channel SR 1st Doped Area DR Second Doped Area TR switching element CAP data storage element SN First electrode DE dielectric layer PN Second electrode PL Common Plate MCA Memory Cell Array MC memory cell BLC First Contact Node SNC's second contact node IL1 First inter-cell insulating layer IL2 Second inter-cell insulating layer IL3 Third inter-cell insulating layer

Claims

1. The steps include forming a horizontal arrangement of nanosheet target patterns comprising an initial sheet horizontally oriented on the upper part of a substrate and sheet expansion tabs located on both sides of the initial sheet, The steps include: exposing the nanosheet target pattern to surface treatment in order to form a horizontal arrangement of narrow sheets and a nanosheet insulating layer surrounding each of the narrow sheets; The steps include forming horizontal conductive lines on the nanosheet insulating layer that surround the horizontally arranged narrow sheets, A method for manufacturing a semiconductor device containing [a specific component].

2. The method for manufacturing a semiconductor device according to claim 1, wherein the sheet expansion tab comprises an epitaxial layer.

3. The method for manufacturing a semiconductor device according to claim 1, wherein the initial sheet and the sheet expansion tab are made of the same substance.

4. The method for manufacturing a semiconductor device according to claim 1, wherein the initial sheet and sheet expansion tab contain a silicon-containing material.

5. The step of exposing the nanosheet target pattern for surface treatment is: The steps include forming a deposition area that surrounds the nanosheet target pattern, The steps include: oxidizing the surface of the nanosheet target pattern to form an oxidized portion; A method for manufacturing a semiconductor device according to claim 1, including the following:

6. The method for manufacturing a semiconductor device according to claim 5, wherein the vapor-deposited portion and the oxidation portion contain silicon dioxide.

7. The method for manufacturing a semiconductor device according to claim 5, wherein the deposited portion comprises a metal-based oxide, and the oxidized portion comprises silicon oxide.

8. The step of forming the horizontal arrangement of the nanosheet target pattern is: The steps include forming a mold stack on the upper part of the substrate, which includes a vertical arrangement of mold layers, The steps include forming a sacrificial separation opening in the mold stack, The steps include forming a liner on the surface of the sacrificial separation opening, The steps include forming a sacrificial separation layer on the liner that fills the sacrificial separation opening, The steps include forming a linear opening in the mold stack, The steps include trimming a portion of the mold layer through the linear opening to form a horizontal arrangement of the initial sheets, The step of removing the sacrificial separation layer through the linear opening, The steps include cutting the liner through the linear opening to form the sheet expansion tab, A method for manufacturing a semiconductor device according to claim 1, including the following:

9. The method for manufacturing a semiconductor device according to claim 8, wherein the liner comprises epitaxial polysilicon.

10. After the step of forming the liner, The method for manufacturing a semiconductor device according to claim 8, further comprising the step of performing an annealing process.

11. The steps include forming a mold stack on the upper part of the substrate, which includes a vertical arrangement of mold layers, The steps include forming a sacrificial separation opening in the mold stack, The steps include forming a liner on the surface of the sacrificial separation opening, The steps include forming a first linear opening in the mold stack, The steps include trimming a first portion of the mold layer through the first linear opening to form a horizontal arrangement of initial sheets, The steps include cutting the liner through the first linear opening to form sheet extension tabs located on both sides of the initial sheet, The process involves exposing the initial sheet and the sheet expansion tab to a surface treatment in order to form a horizontal arrangement of narrow sheets and a nanosheet insulating layer surrounding the narrow sheets, The steps include forming horizontal conductive lines on the nanosheet insulating layer that surround the horizontally arranged narrow sheets, A method for manufacturing a semiconductor device containing [a specific component].

12. The method for manufacturing a semiconductor device according to claim 11, wherein the liner layer comprises epitaxial polysilicon.

13. After the step of forming the liner layer, The method for manufacturing a semiconductor device according to claim 11, further comprising the step of performing an annealing process.

14. The step of exposing the initial sheet and sheet expansion tab for surface treatment is, The steps include forming a vapor deposition portion that surrounds the initial sheet and the sheet expansion tab, The steps include: oxidizing the surface of the initial sheet and the sheet expansion tab to form an oxidized portion; A method for manufacturing a semiconductor device according to claim 11, including the following:

15. The method for manufacturing a semiconductor device according to claim 14, wherein the vapor-deposited portion and the oxidation portion contain silicon dioxide.

16. The method for manufacturing a semiconductor device according to claim 14, wherein the deposited portion comprises a metal-based oxide, and the oxidized portion comprises silicon oxide.

17. The mold stack further includes a vertical arrangement of sacrificial mold layers, A method for manufacturing a semiconductor device according to claim 11, wherein the mold layer and the sacrificial mold layer are alternately stacked in order to form the mold stack.

18. The method for manufacturing a semiconductor device according to claim 17, wherein the mold layer comprises single-crystal silicon and the sacrificial mold layer comprises silicon germanium.

19. After the step of forming the horizontal conductive line, The steps include forming a first contact node connected to the narrow sheet, The steps include forming a vertical conductive line on the first contact node, The steps include forming a second linear opening in the mold stack, The steps include forming a wide sheet by horizontally recessing a second portion of the mold layer through the second linear opening, The steps include forming a second contact node on the wide sheet, The steps include forming a data storage element on the second contact node, A method for manufacturing a semiconductor device according to claim 11, further comprising:

20. The method for manufacturing a semiconductor device according to claim 19, wherein the first and second contact nodes are doped silicon layers formed by selective epitaxial growth.

21. A horizontal arrangement of nanosheets comprising a first doped region, a second doped region, and channels between the first doped region and the second doped region, A nanosheet insulating layer comprising an oxidizing portion that surrounds each of the channels of the nanosheet and a deposition portion that surrounds each of the oxidizing portions, A horizontal conductive line is horizontally oriented on the nanosheet insulating layer while surrounding the channels of the nanosheet, A vertical conductive line connected to each of the first doped regions of the nanosheet, Data storage elements connected to the second doped region of the nanosheet, A semiconductor device equipped with a semiconductor device.

22. The semiconductor device according to claim 21, wherein the deposition portion and the oxidation portion contain silicon dioxide.

23. The semiconductor device according to claim 21, wherein the deposited portion comprises a metal-based oxide, and the oxidized portion comprises silicon oxide.

24. A first contact node between the first doped region and the vertical conductive line, A second contact node between the second doped region and the data storage element, The semiconductor device according to claim 21, further comprising

25. The semiconductor device according to claim 24, wherein the first and second contact nodes are each comprising a selective epitaxial layer.

26. A first spacer is horizontally oriented on the nanosheet insulating layer while surrounding the second doped region of the nanosheet, A second spacer is horizontally oriented on the nanosheet insulating layer while surrounding the first doped region of the nanosheet, The semiconductor device according to claim 21, further comprising

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