Semiconductor device and method for manufacturing the same

Abstract

To provide a semiconductor device equipped with highly integrated memory cells and a method for manufacturing the same. [Solution] The semiconductor device may include a vertical and horizontal arrangement of nanosheets, a horizontal conductive line oriented horizontally while surrounding the horizontal arrangement of nanosheets, pads connected to the edges of the horizontal conductive line, an inter-pad insulating layer located between the pads, contact plugs connected to each of the pads, and contact spacers containing a first low dielectric constant material formed on each side wall of the contact plugs.

Description

Technical Field

[0001] The present invention relates to a semiconductor device, and more particularly, to a semiconductor device including three-dimensional memory cells and a method for manufacturing the same.

Background Art

[0002] In recent years, in order to cope with the increase in capacity and miniaturization of memory devices, three-dimensional memory devices (3D Memory devices) in which a plurality of memory cells (memory cells) are stacked have been proposed.

Summary of the Invention

Problems to be Solved by the Invention

[0003] Embodiments of the present invention provide a semiconductor device including highly integrated memory cells and a method for manufacturing the same.

Means for Solving the Problems

[0004] A semiconductor device according to an embodiment of the present invention can include a vertical and horizontal arrangement of nanosheets, a horizontal conductive line horizontally oriented while surrounding the horizontal arrangement of the nanosheets, a pad connected to an edge portion of the horizontal conductive line, an inter-pad insulating layer located between the pads, a contact plug connected to each of the pads, and a contact spacer including a first low dielectric constant material formed on each sidewall of the contact plug.

[0005] A non-staircase (Stair-less) structure including a vertical and horizontal arrangement of nanosheets, a horizontal conductive line horizontally oriented while surrounding the horizontal arrangement of the nanosheets, a horizontally oriented pad connected to an edge portion of the horizontal conductive line, and a low dielectric constant inter-pad insulating layer between the horizontally oriented pads, contact pillars vertically oriented and connected to each of the horizontally oriented pads, and a low dielectric constant spacer surrounding each outer wall of the contact pillars can be provided.

[0006] A method for manufacturing a semiconductor device according to an embodiment of the present invention may include the steps of: forming an alternating stack of a sacrificial sheet and an inter-pad insulating layer on the upper part of a substrate; forming contact holes in the alternating stack whose height gradually decreases along the stacking direction of the sacrificial sheet and the inter-pad insulating layer; forming a low dielectric constant spacer on the side wall of the contact hole; forming sacrificial plugs on the low dielectric constant spacer to fill each of the contact holes; removing the sacrificial sheet from the alternating stack to form a pad-shaped opening; forming pads to fill the pad-shaped opening; removing the sacrificial plug to form a plug opening; cutting a portion of the low dielectric constant spacer through the plug opening to expose each of the pads; and forming contact plugs that fill each of the plug openings and are connected to each of the pads.

[0007] A semiconductor device according to an embodiment of the present invention may include a substrate, a cell array region having a plurality of horizontal conductive lines stacked vertically along a first direction on the upper part of the substrate, a connecting region having pads and low dielectric constant inter-pad insulating layers stacked alternately along the first direction, contact plugs connected to each of the pads, and low dielectric constant spacers formed on each side wall of the contact plugs. [Effects of the Invention]

[0008] This technology reduces parasitic capacitance between the contact plug and the surrounding pad because the contact spacer contains a low dielectric constant material. This technology, by incorporating a low dielectric constant material into the contact spacer, can increase the speed of semiconductor devices and reduce power consumption.

[0009] This technology can improve the reliability of 3D memory devices. [Brief explanation of the drawing]

[0010] [Figure 1A] This is a schematic perspective view of a memory cell according to one embodiment. [Figure 1B] Figure 1A is a schematic cross-sectional view of the memory cell. [Figure 2A] This is a schematic perspective view of a semiconductor device according to one embodiment. [Figure 2B] This is a partial perspective view illustrating the first spacer. [Figure 2C] This is a partial perspective view illustrating the second spacer. [Figure 3] This is a schematic perspective view of a semiconductor device according to an embodiment. [Figure 4A] This is a schematic perspective view of a semiconductor device according to an embodiment. [Figure 4B] Figure 4A is a schematic cross-sectional view of the semiconductor device. [Figure 4C] This is a schematic cross-sectional view along line A-A' in Figure 4B. [Figure 4D] This is a schematic cross-sectional view along line B-B' in Figure 4B. [Figure 4E] This is a cross-sectional view along line B-B' in Figure 4B. [Figure 5A] These are diagrams and other images illustrating an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 5B] These are diagrams and other images illustrating an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 5C] These are diagrams and other images illustrating an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 6A] These are diagrams and other images illustrating an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 6B] These are diagrams and other images illustrating an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 7A] These are diagrams and other images illustrating an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 7B] These are diagrams and other images illustrating an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 8A] It is a figure or the like for explaining an example of a method for manufacturing a semiconductor device according to an embodiment. [Figure 8B] It is a figure or the like for explaining an example of a method for manufacturing a semiconductor device according to an embodiment. [Figure 9A] It is a figure or the like for explaining an example of a method for manufacturing a semiconductor device according to an embodiment. [Figure 9B] It is a figure or the like for explaining an example of a method for manufacturing a semiconductor device according to an embodiment. [Figure 9C] It is a figure or the like for explaining an example of a method for manufacturing a semiconductor device according to an embodiment. [Figure 10A] It is a figure or the like for explaining an example of a method for manufacturing a semiconductor device according to an embodiment. [Figure 10B] It is a figure or the like for explaining an example of a method for manufacturing a semiconductor device according to an embodiment. [Figure 10C] It is a figure or the like for explaining an example of a method for manufacturing a semiconductor device according to an embodiment. [Figure 11A] It is a figure or the like for explaining an example of a method for manufacturing a semiconductor device according to an embodiment. [Figure 11B] It is a figure or the like for explaining an example of a method for manufacturing a semiconductor device according to an embodiment. [Figure 11C] It is a figure or the like for explaining an example of a method for manufacturing a semiconductor device according to an embodiment. [Figure 11D] It is a figure or the like for explaining an example of a method for manufacturing a semiconductor device according to an embodiment. [Figure 12A] It is a figure or the like for explaining an example of a method for manufacturing a semiconductor device according to an embodiment. [Figure 12B] It is a figure or the like for explaining an example of a method for manufacturing a semiconductor device according to an embodiment. [Figure 12C] It is a figure or the like for explaining an example of a method for manufacturing a semiconductor device according to an embodiment. [Figure 12D] It is a figure or the like for explaining an example of a method for manufacturing a semiconductor device according to an embodiment. [Figure 13A]These are diagrams and other images illustrating an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 13B] These are diagrams and other images illustrating an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 13C] These are diagrams and other images illustrating an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 14A] These are diagrams and other images illustrating an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 14B] These are diagrams and other images illustrating an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 14C] These are diagrams and other images illustrating an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 15A] These are diagrams and other images illustrating an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 15B] These are diagrams and other images illustrating an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 15C] These are diagrams and other images illustrating an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 16A] These are diagrams and other images illustrating an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 16B] These are diagrams and other images illustrating an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 17A] These are diagrams and other images illustrating an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 17B] These are diagrams and other images illustrating an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 18A] These are diagrams and other images illustrating an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 18B] These are diagrams and other images illustrating an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 19A] These are diagrams and other images illustrating an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 19B]These are diagrams and other images illustrating an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 20A] These are diagrams and other images illustrating an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 20B] These are diagrams and other images illustrating an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 20C] These are diagrams and other images illustrating an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 21A] These are diagrams and other images illustrating an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 21B] These are diagrams and other images illustrating an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 21C] These are diagrams and other images illustrating an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 22A] These are diagrams and other images illustrating an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 22B] These are diagrams and other images illustrating an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 22C] These are diagrams and other images illustrating an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 23A] These are diagrams and other images illustrating an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 23B] These are diagrams and other images illustrating an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 23C] These are diagrams and other images illustrating an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 24A] These are diagrams and other images illustrating an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 24B] These are diagrams and other images illustrating an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 24C] These are diagrams and other images illustrating an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 25A]These are diagrams and other images illustrating an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 25B] These are diagrams and other images illustrating an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 25C] These are diagrams and other images illustrating an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 26A] These are diagrams and other images illustrating an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 26B] These are diagrams and other images illustrating an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 26C] These are diagrams and other images illustrating an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 27A] These are diagrams and other images illustrating an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 27B] These are diagrams and other images illustrating an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 27C] These are diagrams and other images illustrating an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 28A] These are diagrams and other images illustrating an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 28B] These are diagrams and other images illustrating an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 28C] These are diagrams and other images illustrating an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 29A] These are diagrams and other images illustrating an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 29B] These are diagrams and other images illustrating an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 30A] These are diagrams and other images illustrating an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 30B] These are diagrams and other images illustrating an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 31A]These are diagrams and other images illustrating an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 31B] These are diagrams and other images illustrating an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 32A] These are diagrams and other images illustrating an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 32B] These are diagrams and other images illustrating an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 33A] These are diagrams and other images illustrating an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 33B] These are diagrams and other images illustrating an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 34A] These are diagrams and other images illustrating an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 34B] These are diagrams and other images illustrating an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 35] This is a schematic cross-sectional view of a semiconductor device according to another embodiment. [Figure 36] This is a schematic cross-sectional view of a semiconductor device according to another embodiment. [Figure 37] This is a schematic cross-sectional view of a semiconductor device according to another embodiment. [Figure 38] This is a schematic cross-sectional view of a semiconductor device according to another embodiment. [Figure 39A] This is a schematic cross-sectional view of a semiconductor device according to another embodiment. [Figure 39B] This is a schematic cross-sectional view of a semiconductor device according to another embodiment. [Figure 40A] This diagram illustrates a stack assembly according to another embodiment. [Figure 40B] This diagram illustrates a stack assembly according to another embodiment. [Modes for carrying out the invention]

[0011] The embodiments described herein will be explained with reference to the cross-sectional view, plan view, and block diagram, which are ideal schematic representations of the present invention. Therefore, the form of the illustrative figures may be modified due to manufacturing techniques and / or tolerances. Accordingly, the embodiments of the present invention are not limited to the specific forms shown, but also include changes in form generated by the manufacturing process. Accordingly, the areas illustrated in the drawings have schematic attributes, and the shapes of the areas illustrated in the drawings are for illustrating specific forms of the element area and are not intended to limit the scope of the invention.

[0012] The embodiments described later relate to three-dimensional memory cells, which can increase memory cell density and reduce parasitic capacitance by stacking memory cells vertically.

[0013] Figure 1A is a schematic perspective view of a memory cell according to one embodiment. Figure 1B is a schematic cross-sectional view of the memory cell.

[0014] As shown in Figures 1A and 1B, the memory cell MC may include a first conductive line BL, a switching element TR, and a data storage element CAP.

[0015] The first conductive line BL can be vertically oriented along a first direction D1. The first conductive line BL can comprise a bit line. The first conductive line BL can be referred to as a vertical conductive line, a vertically-oriented bit line, a vertically-extended bit line, or a pillar-shaped bit line. The first conductive line BL can contain a conductive material. The first conductive line BL can contain a silicon-based material, a metal-based material, or a combination thereof. The first conductive line BL can contain polysilicon, metal, metal nitride, metal silicide, or a combination thereof. The first conductive line BL can contain polysilicon, titanium nitride, tungsten, or a combination thereof. For example, the first conductive line BL can contain a titanium nitride / tungsten stack (TiN / W) in which titanium nitride and tungsten are stacked in that order.

[0016] The switching element TR has the function of controlling the voltage (or current) supplied to the data storage element CAP during data writing and data reading operations. The switching element TR may comprise a nanosheet (HL), a nanosheet insulating layer GD, and a second conductive line WL. The second conductive line WL may comprise a horizontal conductive line or a horizontal word line, and the nanosheet HL may comprise an active layer. The switching element TR may comprise a transistor, in which case the second conductive line WL may act as a gate or gate electrode. The switching element TR may also be referred to as a nanosheet transistor, access element, or selection element. The second conductive line WL may be referred to as a horizontal gate electrode or a horizontal word line.

[0017] The nanosheet HL can extend along a second direction D2 intersecting a first direction D1. The second conductive line WL can extend horizontally along a third direction D3, which can intersect the first and second directions D1 and D2. The first direction D1 can be a vertical direction, the second direction D2 can be a first horizontal direction, and the third direction D3 can be a second horizontal direction. The nanosheet HL can extend along the first horizontal direction (i.e., the second direction D2), and the second conductive line WL can extend along the second horizontal direction (i.e., the third direction D3). The nanosheet HL can be referred to as a "horizontal layer" or "channel body".

[0018] The nanosheet HL may comprise a channel (CH), a first doped region SR between channel CH and a first conductive line BL, and a second doped region DR between channel CH and a data storage element CAP. The first doped region SR can be electrically connected to the first conductive line BL, and the second doped region DR can be electrically connected to the data storage element CAP. The height of the second doped region DR along the first direction D1 may be greater than the height of channel CH along the first direction D1. The length of the second doped region DR along the second direction D2 may be less than the length of channel CH along the second direction D2. The lengths of the first doped region SR, channel CH, and the second doped region DR along the third direction D3 may be the same as each other.

[0019] A nanosheet HL may comprise a first sheet region (NS) and a second sheet region (WS) arranged horizontally along a second direction D2. The second sheet region WS may extend from the first sheet region NS. The second sheet region WS may have a thickness that gradually increases along the second direction D2 from the first sheet region NS toward the data storage element CAP between the first sheet region NS and the data storage element CAP. The average vertical height (thickness) of the second sheet region WS along the first direction D1 may be greater than the average vertical height (thickness) of the first sheet region NS. Hereinafter, the first sheet region NS will be abbreviated as "Narrower sheet" and the second sheet region WS will be abbreviated as "Wide sheet".

[0020] The narrow sheet NS can be flat-plate shaped. The wide sheet WS can be fan-shaped, i.e., fan-shaped. The thickness of the wide sheet WS may gradually increase along the second direction D2. The narrow sheet NS can be called a flat plate-shaped sheet, and the wide sheet WS can be called a fan-shaped sheet. The upper and lower surfaces of the wide sheet WS may have curvature.

[0021] The first doped region SR and channel CH may be located within a narrow sheet NS, and the second doped region DR may be located within a wide sheet WS. The channel CH formed within the narrow sheet NS may be referred to as a narrow channel or flat channel. A portion of the second doped region DR may extend to be located within the narrow sheet NS. The second doped region DR may include a thick portion located within the wide sheet WS and a thin portion located within the narrow sheet NS. One side of the wide sheet WS and one side of the second doped region DR that are in contact with the data storage element CAP may have a flat side shape.

[0022] The horizontal length of the wide sheet WS along the second direction D2 can be less than the horizontal length of the narrow sheet NS. The narrow sheet NS may be called a long sheet, and the wide sheet WS may be called a short sheet.

[0023] Nanosheet HL can contain semiconductor materials. For example, nanosheet HL can contain polysilicon, single-crystal silicon, germanium, or silicon-germanium. In other embodiments, nanosheet HL can contain oxide semiconductor materials. For example, oxide semiconductor materials can include IGZO (Indium Gallium Zinc Oxide), InSnZnO, ZnSnO, or combinations thereof. In other embodiments, nanosheet HL can contain conductive metal oxides.

[0024] In other embodiments, the nanosheet HL may include a two-dimensional material or a two-dimensional semiconductor material. A two-dimensional semiconductor material may refer to a semiconductor material having a layered structure in which constituent atoms are bonded two-dimensionally. Two-dimensional semiconductor materials have excellent electrical properties and can maintain high mobility without their properties changing significantly even when their thickness is reduced to the nanoscale. For example, the nanosheet HL may include MoS2, WS2, or MoSe2.

[0025] If the nanosheet HL is an oxide semiconductor material, the channel CH may also be made of an oxide semiconductor material, and the first and second doped regions SR and DR may be omitted. The nanosheet HL may also be referred to as the active layer or thin-body.

[0026] The first doped region SR and the second doped region DR may be doped with impurities of the same conductivity type. The first doped region SR and the second doped region DR may be doped with N-type conductivity impurities or P-type conductivity impurities. For example, the conductivity impurities may include arsenic (As), phosphorus (P), boron (B), indium (In), or combinations thereof. The first doped region SR may be electrically connected to the first conductive line BL, and the second doped region DR may be electrically connected to the data storage element CAP. The first and second doped regions SR and DR may be referred to as the "first and second source / drain regions."

[0027] The nanosheet HL can be oriented horizontally along a second direction D2 from a first conductive line BL.

[0028] The second conductive line WL can be a gate allaround structure (GAA). For example, the second conductive line WL can extend along a third direction D3 while surrounding the nanosheet HL. A nanosheet insulating layer GD can be formed between the nanosheet HL and the second conductive line WL. The nanosheet insulating layer GD can surround the nanosheet HL. The second conductive line WL can surround the nanosheet HL on the nanosheet insulating layer GD.

[0029] The second conductive line WL may include metallic materials, metal-base materials, semiconductor materials, or combinations thereof. The second conductive line WL may include molybdenum, molybdenum nitride, ruthenium, titanium nitride, tungsten, polysilicon, or combinations thereof. For example, the second conductive line WL may include a TiN / W stack in which titanium nitride and tungsten are sequentially stacked. The second conductive line WL may include N-type work function materials or P-type work function materials. N-type work function materials may have a low work function lower than 4.5 eV, while P-type work function materials may have a high work function higher than 4.5 eV. The second conductive line WL may include stacks of low-work function materials and high-work function materials.

[0030] The nanosheet insulating layer GD can be located between the nanosheet HL and the second conductive line WL. The nanosheet insulating layer GD can be referred to as the "gate dielectric layer" or the "channel-side dielectric layer". The nanosheet insulating layer GD can include silicon oxide, silicon nitride, metal oxides, metal oxides and nitrides, metal silicates, high-k materials, ferroelectric materials, anti-ferroelectric materials, or combinations thereof. The nanosheet insulating layer GD can include SiO2, Si3N4, HfO2, Al2O3, ZrO2, AlON, HfON, HfSiO, HfSiON, HfZrO, or combinations thereof. The nanosheet insulating layer GD can be formed by thermal oxidation of a semiconductor material. The nanosheet insulating layer GD can be formed by combining the deposition of nanosheet insulating material and the oxidation of semiconductor material.

[0031] The data storage element CAP may include a memory element such as a capacitor. The data storage element CAP may be positioned horizontally along a second direction D2 from the switching element TR. The data storage element CAP may comprise a first electrode SN, a second electrode PN on the first electrode SN, and a dielectric layer DE between the first electrode SN and the second electrode PN. The first electrode SN may extend horizontally from a nanosheet HL along the second direction D2. The first electrode SN, the dielectric layer DE, and the second electrode PN may be arranged horizontally along the second direction D2. The first electrode SN may include an inner space and a plurality of outer surfaces, and the inner space of the first electrode SN may include a plurality of inner surfaces. The outer surfaces of the first electrode SN may include a vertical outer surface and a plurality of horizontal outer surfaces. The vertical outer surface of the first electrode SN can extend perpendicularly along the first direction D1, and the horizontal outer surface of the first electrode SN can extend horizontally along the second direction D2 or the third direction D3. The inner space of the first electrode SN can be a three-dimensional space. The dielectric layer DE can conformally cover the inner surface of the first electrode SN. The second electrode PN can be placed in the inner space of the first electrode SN on the dielectric layer DE. A portion of the outer surface of the first electrode SN can be electrically connected to the second doped region DR of the nanosheet HL. The second electrode PN of the data storage element CAP can be connected to the common plate (PL).

[0032] The data storage element CAP can have a three-dimensional structure. The first electrode SN has a three-dimensional structure, but the three-dimensional structure of the first electrode SN can be a horizontal three-dimensional structure oriented along a second direction D2. As an example of a three-dimensional structure, the first electrode SN can have a cylinder shape. The cylinder shape of the first electrode SN can include a cylinder inner surface and a cylinder outer surface. A portion of the cylinder outer surface of the first electrode SN can be electrically connected to a second doped region DR of the nanosheet HL. A dielectric layer DE and a second electrode PN can be placed on the cylinder inner surface and cylinder outer surface of the first electrode SN.

[0033] In other embodiments, the first electrode SN may be pillar-shaped or pyrinder-shaped. The pyrinder shape may refer to a structure in which the pillar shape and the cylinder shape are merged.

[0034] The first electrode SN and the second electrode PN may include metals, noble metals, metal nitrides, conductive metal oxides, conductive noble metal oxides, metal carbides, metal silicides, or combinations thereof. For example, the first electrode SN and the second electrode PN may include titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium dioxide (RuO2), iridium (Ir), iridium oxide (IrO2), platinum (Pt), molybdenum (Mo), molybdenum nitride (MoN), molybdenum oxide (MoO), titanium nitride / tungsten (TiN / W) stack, tungsten nitride / tungsten (WN / W) stack, titanium silicon nitride / titanium nitride (TiSiN / TiN) stack, titanium nitride / titanium nitride / tungsten (TiSiN / TiN / W) stack, or combinations thereof. The second electrode PN may also include combinations of metal-based materials and silicon-based materials. For example, the second electrode PN can be a stack of titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN). In the titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN) stack, silicon germanium can be the gap fill material filling the inside of the first electrode SN, titanium nitride (TiN) can play the role of the second electrode PN of the data storage element CAP, and tungsten nitride can be the low-resistance material.

[0035] The dielectric layer DE may be referred to as a capacitor dielectric layer or a memory layer. The dielectric layer DE may include silicon oxide, silicon nitride, high dielectric constant materials, perovskite materials, or combinations thereof. High dielectric constant materials may include hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium pentoxide (Nb2O5), or strontium titanate (SrTiO3). In other embodiments, the dielectric layer DE may consist of a composite layer comprising two or more of the aforementioned high dielectric constant materials.

[0036] The dielectric layer DE can be formed from a zirconium-based oxide (Zr-base oxide). The dielectric layer DE can be a stacked structure containing zirconium oxide (ZrO2). The dielectric layer DE can include a ZA (ZrO2 / Al2O3) stack or a ZAZ (ZrO2 / Al2O3 / ZrO2) stack. The ZA stack can be a structure in which aluminum oxide (Al2O3) is stacked on top of zirconium oxide (ZrO2). The ZAZ stack can be a structure in which zirconium oxide (ZrO2), aluminum oxide (Al2O3), and zirconium oxide (ZrO2) are stacked sequentially. The ZA stack and ZAZ stack can be referred to as a zirconium oxide-base layer (ZrO2-base layer).

[0037] In other embodiments, the dielectric layer DE can be formed of a hafnium-base oxide (Hf-base oxide). The dielectric layer DE can be a stack structure containing hafnium oxide (HfO2). The dielectric layer DE can include an HA (HfO2 / Al2O3) stack or an HAH (HfO2 / Al2O3 / HfO2) stack. The HA stack can be a structure in which aluminum oxide (Al2O3) is stacked on top of hafnium oxide (HfO2). The HAH stack can be a structure in which hafnium oxide (HfO2), aluminum oxide (Al2O3), and hafnium oxide (HfO2) are stacked sequentially. The HA stack and HAH stack can be referred to as a hafnium oxide-base layer (HfO2-base layer). In ZA stacks, ZAZ stacks, HA stacks, and HAH stacks, aluminum oxide (Al2O3) can have a higher band gap energy than zirconium oxide (ZrO2) and hafnium oxide (HfO2). Aluminum oxide (Al2O3) can have a lower dielectric constant than zirconium oxide (ZrO2) and hafnium oxide (HfO2). Therefore, the dielectric layer DE can contain stacks of high dielectric constant materials and high band gap materials with a higher band gap energy than high dielectric constant materials. In addition to aluminum oxide (Al2O3), the dielectric layer DE can also contain silicon oxide (SiO2) as another high band gap material. Leakage current can be suppressed by including high band gap materials in the dielectric layer DE. High band gap materials can be thinner than high dielectric constant materials.

[0038] In other embodiments, the dielectric layer DE may include a stacked structure in which high dielectric constant material and high bandgap material are alternately stacked. For example, the dielectric layer DE may be a ZAZA (ZrO2 / Al2O3 / ZrO2 / Al2O3) stack, a ZAZAZ (ZrO2 / Al2O3 / ZrO2 / Al2O3 / ZrO2) stack, a HAHA (HfO2 / Al2O3 / HfO2 / Al2O3) stack, a HAHAH (HfO2 / Al2O3 / HfO2 / Al2O3 / HfO2) stack, a HZAZH (HfO2 / ZrO2 / Al2O3 / ZrO2 / HfO2) stack, or a ZHZAZHZ (ZrO2 / HfO2 / ZrO2 / Al2O3 / ZrO2) stack. The stacks may include an HfO2 / ZrO2 stack, an HZHZ(HfO2 / ZrO2 / HfO2 / ZrO2) stack, an AHZAZHA(Al2O3 / HfO2 / ZrO2 / Al2O3 / ZrO2 / HfO2 / Al2O3) stack, an AHZAHZA(Al2O3 / HfO2 / ZrO2 / Al2O3 / HfO2 / ZrO2 / Al2O3) stack, or a ZHZAZHZAT(ZrO2 / HfO2 / ZrO2 / Al2O3 / ZrO2 / HfO2 / ZrO2 / Al2O3 / TiO2) stack. In such stack structures, the aluminum oxide (Al2O3) can be thinner than the zirconium oxide (ZrO2) and hafnium oxide (HfO2).

[0039] In other embodiments, the dielectric layer DE may include a high dielectric constant material and a high bandgap material, but may also include a laminated structure in which multiple high dielectric constant materials and multiple high bandgap materials are stacked, or a mixed structure in which the high dielectric constant material and the high bandgap material are intermixed.

[0040] In other embodiments, the dielectric layer DE may include a ferroelectric material, an antiferroelectric material, or a combination thereof. For example, the dielectric layer DE may include HfZrO.

[0041] In other embodiments, the dielectric layer DE may include a combination of a high dielectric material and a ferroelectric material, a combination of a high dielectric material and an antiferroelectric material, or a combination of a high dielectric material or a ferroelectric material and an antiferroelectric material.

[0042] In other embodiments, the data storage element CAP may further comprise a plurality of interface control layers for leakage current improvement. The interface control layers may include titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium pentoxide (Nb2O5), niobium nitride (NbN), niobium oxynitride (NbON), or a combination thereof. The data storage element CAP may include a first interface control layer, a second interface control layer, or a combination thereof. The first and second interface control layers may be conductive or insulating. The first interface control layer may be formed between the first electrode SN and the dielectric layer DE, and the second interface control layer may be formed between the dielectric layer DE and the second electrode PN. The first and second interface control layers may be the same material or different materials. For example, a structure in which a first interface control layer, a dielectric layer DE, and a second interface control layer are stacked in that order for a data storage element CAP may include an NZHZAZHZATN(Nb2O5 / ZrO2 / HfO2 / ZrO2 / Al2O3 / ZrO2 / HfO2 / ZrO2 / Al2O3 / TiO2 / Nb2O5) stack.

[0043] The data storage element CAP may include a three-dimensional capacitor. The data storage element CAP may include a MIM (Metal-Insulator-Metal) capacitor. The data storage element CAP can also be replaced with other data storage materials. For example, the data storage material may be a thyristor, a phase conversion material, an MTJ (Magnetic Tunnel Junction), or a variable resistor material.

[0044] The memory cell MC may further comprise a first contact node BLC and a second contact node SNC. The first contact node BLC may be located between the first conductive line BL and the nanosheet HL. The first contact node BLC may include a metal-based material or a semiconductor material. For example, the first contact node BLC may include titanium, titanium nitride, tungsten, or a combination thereof. The first contact node BLC may also include doped polysilicon, and the first doped region SR may include impurities diffused from the first contact node BLC. The second contact node SNC may be located between the nanosheet HL and the first electrode SN. The second contact node SNC may include a metal-based material or a semiconductor material. For example, the second contact node SNC may include titanium, titanium nitride, tungsten, or a combination thereof. The second contact node SNC may also include doped silicon, and the second doped region DR may include impurities diffused from the second contact node SNC. The height of the first contact node BLC along the first direction D1 may be less than the height of the second contact node SNC along the first direction D1. The height of the first contact node BLC along the first direction D1 may be greater than the height of the channel CH along the first direction D1. The first and second contact nodes BLC and SNC may include phosphorus-doped polysilicon or arsenic-doped polysilicon.

[0045] In other embodiments, the second contact node SNC can be selectively grown from a wide sheet WS of a nanosheet HL. The second contact node SNC can be formed by selective epitaxial growth SEG. For example, the second contact node SNC can be a silicon epitaxial layer formed by selective epitaxial growth SEG. The second contact node SNC can be a doped silicon epitaxial layer.

[0046] In other embodiments, the first contact node BLC can also be selectively grown from a narrow sheet WS of a nanosheet HL. The first contact node BLC can be formed by selective epitaxial growth SEG. For example, the first contact node BLC can be a silicon epitaxial layer formed by selective epitaxial growth SEG. The first contact node BLC can be a doped silicon epitaxial layer.

[0047] The first contact node BLC can be a narrow sheet-side contact node, and the second contact node SNC can be a wide sheet-side contact node.

[0048] The nanosheet HL may comprise a first edge and a second edge. The first edge may represent a portion of a first doped region SR electrically connected to a first conductive line BL, and the second edge may represent a portion of a second doped region DR electrically connected to a first electrode SN of the data storage element CAP.

[0049] The memory cell MC may further comprise an ohmic contact layer BLO between a first contact node BLC and a first conductive line BL. The ohmic contact layer BLO may include a metallic silicide such as titanium silicide or molybdenum silicide.

[0050] The memory cell MC may further comprise a first spacer SP1 and a second spacer SP2. The first spacer SP1 may be positioned between a second conductive line WL and a second doped region DR. The second spacer SP2 may be positioned between a first conductive line BL and a second conductive line WL. The first and second spacers SP1 and SP2 may include an insulating material. The first and second spacers SP1 and SP2 may include silicon oxide, silicon nitride, or a combination thereof. The first spacer SP1 may include silicon nitride. The second spacer SP2 may be a stack of silicon nitride and silicon oxide. The first and second spacers SP1 and SP2 may be positioned on both side walls of the second conductive line WL. That is, the first and second spacers SP1 and SP2 may extend along a third direction D3. The first spacer SP1 can surround the second doped region DR of the nanosheet HL, and the second spacer SP2 can surround the first doped region of the nanosheet HL. The second spacer SP2 may include a stack of the first liner L1 and the second liner L2. The first liner L1 of the second spacer SP2 may be silicon nitride, and the second liner L2 may be silicon oxide. The second liner L2 may partially fill the inner space of the first liner L1.

[0051] The first conductive line BL may comprise a plurality of horizontal extensions BLE1, BLE2, and BLE3. The horizontal extensions (BLE1, BLE2, and BLE3) may extend along a second direction D2. The horizontal extensions BLE1, BLE2, and BLE3 may comprise an inner horizontal extension BLE2 and outer horizontal extensions BLE1 and BLE3. The inner horizontal extension BLE2 of the first conductive line BL may extend to be located within the gap between vertically adjacent first liners L1, thereby enabling the inner horizontal extension BLE2 of the first conductive line BL to be electrically connected to the ohmic contact layer BLO.

[0052] The outer horizontal extensions BLE1 and BLE3 of the first conductive line BL can extend so as to be located within one side surface of the second spacer SP2, thereby allowing them to contact the second liner L2 of the second spacer SP2.

[0053] Figure 2A is a schematic diagram of a semiconductor device according to one embodiment. Figure 2B is a partial perspective view illustrating a first spacer. Figure 2C is a partial perspective view illustrating a second spacer.

[0054] Figure 2A shows a horizontal array HMCA, which can have a structure in which multiple memory cells MC, as shown in Figures 1A and 1B, are arranged along a third direction D3.

[0055] As shown in Figures 1A, 1B, and 2A, a horizontal array HMCA can include a horizontal arrangement of memory cells MC. The memory cells MC of the horizontal array HMCA can be horizontally separated along a third direction D3. Each memory cell MC of the horizontal array HMCA can be connected to a first conductive line BL. The memory cells MC of the horizontal array HMCA can share one second conductive line WL. An individual memory cell MC may comprise a first conductive line BL, a nanosheet HL, and a data storage element CAP. The nanosheet HL may comprise a first doped region SR, a channel CH, and a second doped region DR. A first contact node BLC and an ohmic contact layer BLO may be formed between the first doped region SR and the first conductive line BL of the nanosheet HL. A second contact node SNC may be formed between the second doped region DR and the data storage element CAP of the nanosheet HL. The nanosheet HL may be surrounded by a nanosheet insulating layer GD. The second conductive line WL can extend along a third direction D3 while surrounding the channel CH of the nanosheet HL on the nanosheet insulating layer GD.

[0056] The horizontal array HMCA may further include a first spacer SP1 and a second spacer SP2, as shown in Figure 1B.

[0057] As further shown in Figure 2B, the first spacer SP1 can be a single, integrated structure extending along the first direction D1. The first spacer SP1 can surround a portion of the nanosheet HL, i.e., a second doped region DR of the nanosheet HL at the same horizontal level. A portion of the first spacer SP1 can be located between the nanosheets HL, thereby allowing the first spacer SP1 to extend perpendicularly along the first direction D1. The cross-section of the first spacer SP1 can be cup-shaped.

[0058] As further shown in Figure 2C, the second spacer SP2 can extend along a third direction D3 while surrounding a portion of the nanosheet HL, i.e., the first doped region SR of the nanosheet HL at the same horizontal level.

[0059] Figure 3 is a schematic perspective view of a semiconductor device according to one embodiment. The semiconductor device 100V in Figure 3 may include a structure in which the horizontal array HMCA of Figure 2A is stacked vertically along a first direction D1. For detailed descriptions of overlapping components, please refer to Figures 1A to 2C below.

[0060] As shown in Figure 3, the semiconductor device 100V may include a vertical stack of horizontal array HMCA. The semiconductor device 100V may include a horizontal array of multiple first conductive lines BL and a vertical array of multiple second conductive lines WL. A vertical array of memory cells MC stacked along a first direction D1 may share one first conductive line BL. A horizontal array of memory cells MC arranged along a third direction D3 may be connected to different first conductive lines BL.

[0061] A horizontal array of memory cells MC arranged along a third direction D3 can share one second conductive line WL. A vertical array of memory cells MC stacked along a first direction D1 can be connected to different second conductive lines WL.

[0062] Figure 4A is a schematic perspective view of a semiconductor device according to an embodiment. Figure 4B is a schematic plan view of the semiconductor device of Figure 4A. Figure 4C is a schematic cross-sectional view along A-A' in Figure 4B. Figure 4D is a schematic cross-sectional view along B-B' in Figure 4B. Figure 4E is a cross-sectional view along B1-B1' in Figure 4B. For detailed descriptions of overlapping components, please refer to Figures 1A to 3 below.

[0063] As shown in Figures 4A to 4E, the semiconductor device 100 may include a memory cell array MCA. The memory cell array MCA may include a three-dimensional array of memory cells MC. For a detailed description of the memory cells MC, refer to Figures 1A and 1B. The memory cell array MCA may be placed on a substructure LS.

[0064] A memory cell array (MCA) may comprise a first region R1 and a second region R2. The first region R1 may be the region where a three-dimensional array of memory cells (MCs) is formed, and the second region R2 may be the region where pads WP and contact plugs CT connected to the second conductive line WL of the memory cells (MCs) are formed. The first region R1 may be referred to as the array region, and the second region R2 may be referred to as the pad region or connection region. The first region R1 may include a vertical stack of memory cells (MCs), and the second region R2 may include a vertical stack of pads WP. The second region R2 may be referred to as a sharing connection region, a sharing contact region, or a common contact region.

[0065] The substructure LS can be located at a lower level than the memory cell array MCA. The substructure LS can be a material suitable for semiconductor processing. The substructure LS can include semiconductor substrates, conductive materials, dielectric materials, semiconductive materials, or combinations thereof. The substructure LS can comprise silicon, monocrystalline silicon, polysilicon, amorphous silicon, silicon germanium, single-crystal silicon germanium, polycrystalline silicon germanium, carbon-doped silicon, epitaxial silicon, combinations thereof, or multilayers thereof. The substructure LS may also contain other semiconductor materials such as germanium. The substructure LS may also include III / V semiconductor substrates, such as compound semiconductor substrates like GaAs.

[0066] In other embodiments, the substructure LS may comprise a metal wiring structure, an insulating structure, a conductive structure, a bonding pad structure, other memory, or peripheral circuitry. For example, the substructure LS may include a structure in which peripheral circuitry, metal wiring structure, and bonding pad structure are stacked in that order. The memory cell array MCA and the peripheral circuitry of the substructure LS can be bonded by wafer bonding. Wafer bonding may include pad bonding, hybrid bonding, oxide-to-oxide bonding, metal-to-metal bonding, or a combination thereof.

[0067] A discrete memory cell MC may comprise a first conductive line BL, a switching element TR, and a data storage element CAP, and the switching element TR may comprise a second conductive line WL, a nanosheet insulating layer GD, and a nanosheet HL.

[0068] The semiconductor device 100 may include a column array AR1 of memory cells MC and a row array AR2 of memory cells MC. The column array AR1 may include a plurality of memory cells MC stacked vertically along a first direction D1. The memory cells MC in the column array AR1 may share a first conductive line BL. The row array AR2 may include a plurality of memory cells MC arranged horizontally along a third direction D3. The memory cells MC in the row array AR2 may share a second conductive line WL. The first direction D1 may be vertical, and the third direction D3 may be horizontal.

[0069] The semiconductor device 100 may include a horizontal array of multiple first conductive lines BL and a vertical array of multiple second conductive lines WL. A vertical array of memory cells MC stacked along a first direction D1 may share one first conductive line BL. A horizontal array of memory cells MC arranged along a third direction D3 may be connected to different first conductive lines BL. A horizontal array of memory cells MC arranged along a third direction D3 may share one second conductive line WL. A vertical array of memory cells MC stacked along a first direction D1 may be connected to different second conductive lines WL.

[0070] The semiconductor device 100 may comprise a first subcell array MCA1 and a second subcell array MCA2. The first subcell array MCA1 and the second subcell array MCA2 may each comprise a three-dimensional array of memory cells MC. The first subcell array MCA1 and the second subcell array MCA2 may share a first conductive line BL. The first conductive line BL may comprise a first vertical conductive line BLA and a second vertical conductive line BLB, and the bottom portions of the first vertical conductive line BLA and the second vertical conductive line BLB may be merged with each other. The combination of the first vertical conductive line BLA and the second vertical conductive line BLB may give the first conductive line BL a U-shape. The memory cells MC of the first subcell array MCA1 may share the first vertical conductive line BLA, and the memory cells MC of the second subcell array MCA2 may share the second vertical conductive line BLB. Thus, the first and second subcell arrays MCA1 and MCA2, adjacent to each other along the second direction D2, can be a mirror-type structure sharing the first conductive line BL. When viewed from a top view, the first and second vertical conductive lines BLA and BLB can be rectangular in shape.

[0071] A first inter-cell dielectric layer (IL1) may be placed between adjacent data storage elements CAP along a third direction D3. A second inter-cell dielectric layer (IL2) may be placed between second conductive lines WL stacked perpendicularly along the first direction D1. A third inter-cell dielectric layer (IL3) may be placed between the first electrodes SN of data storage elements CAP stacked perpendicularly along the first direction D1. The first to third inter-cell dielectric layers (IL1, IL2, IL3) may include silicon oxide, silicon oxide-bonded carbide (SiCO), silicon nitride, or a combination thereof. The first inter-cell dielectric layer (IL1) may be referred to as a device isolation layer.

[0072] The memory cell array MCA may further comprise a first contact node BLC and a second contact node SNC. The first contact node BLC may be positioned between the first and second vertical conductive lines BLA, BLB and the nanosheet HL. The first contact node BLC may include a metal-based material or a semiconductor material. For example, the first contact node BLC may include titanium, titanium nitride, tungsten, or a combination thereof. The first contact node BLC may also include doped polysilicon, and the first doped region SR may include impurities diffused from the first contact node BLC. The second contact node SNC may be positioned between the nanosheet HL and the first electrode SN. The second contact node SNC may include a metal-based material or a semiconductor material. For example, the second contact node SNC may include titanium, titanium nitride, tungsten, or a combination thereof. Furthermore, the second contact node SNC may contain doped polysilicon, and the second doped region DR may contain impurities diffused from the second contact node SNC. The height of the first contact node BLC along the first direction D1 may be less than the height of the second contact node SNC along the first direction D1. The height of the first contact node BLC along the first direction D1 may be greater than the height of the channel CH along the first direction D1. The first and second contact nodes BLC and SNC may contain doped polysilicon, for example, phosphorus-doped polysilicon or arsenic-doped polysilicon.

[0073] The memory cell array MCA may further comprise an ohmic contact layer (see "BLO" in Figures 1A and 1B) between the first contact node BLC and the first conductive line BL. The ohmic contact layer may include a metallic silicide such as titanium silicide or molybdenum silicide.

[0074] The memory cell array MCA may further comprise a first spacer SP1 and a second spacer SP2. The first spacer SP1 may be positioned between a second conductive line WL and a second doped region DR. The second spacer SP2 may be positioned between a first conductive line BL and a second conductive line WL. The first and second spacers SP1 and SP2 may include an insulating material. The first and second spacers SP1 and SP2 may include silicon oxide, silicon nitride, or a combination thereof. The first and second spacers SP1 and SP2 may extend along a third direction D3 on both side walls of the second conductive line WL, as shown in Figures 2B and 2C. The first and second spacers SP1 and SP2 may surround a horizontal arrangement of nanosheets HL along the third direction D3. The first spacer SP1 may also extend vertically along the first direction D1.

[0075] The memory cell array MCA may comprise a plurality of second conductive lines WL stacked vertically along a first direction D1. The memory cell array MCA may comprise a plurality of nanosheets HL stacked vertically along the first direction D1. The memory cell array MCA may comprise a plurality of data storage elements CAP stacked vertically along the first direction D1. The memory cell array MCA may comprise a plurality of first conductive lines BL spaced apart along a third direction D3. The memory cell array MCA may comprise dummy second conductive lines WLU, WLL located at a level higher than the highest-level second conductive line WL and at a level lower than the lowest-level second conductive line WL, respectively. The dummy second conductive lines WLU, WLL may have a horizontally extending linear shape.

[0076] The memory cell array (MCA) may include a stack of multiple hard mask layers HM1, HM2, HM3, and HM4 located at a higher level than the top-level dummy second conductive line WLU.

[0077] The memory cell array MCA may comprise a plurality of first and second bottom protection layers BT1 and BT2. The first bottom protection layer BT1 can prevent electrical contact between the first conductive line BL and the lower structure LS. The second bottom protection layer BT2 can prevent electrical contact between the data storage element CAP and the lower structure LS. The first and second bottom protection layers BT1 and BT2 may contain insulating material.

[0078] An array separation layer BLF may be located between the first vertical conductive line BLA and the second vertical conductive line BLB of the first conductive line BL. The array separation layer BLF may contain an insulating material. For example, the array separation layer BLF may contain silicon oxide, silicon nitride, silicon oxide with an embedded air gap, or a combination thereof.

[0079] Nanosheets HL of switching elements TR arranged horizontally along a third direction D3 can share one second conductive line WL. Nanosheets HL of switching elements TR arranged horizontally along a third direction D3 can be connected to different first conductive lines BL. Switching elements TR stacked along a first direction D1 can share one first conductive line BL. Switching elements TR arranged horizontally along a third direction D3 can share one second conductive line WL.

[0080] The second electrode PN of the data storage element CAP can be connected to the common plate (PL). The second electrode PN of the data storage element CAP can be merged to form the common plate PL.

[0081] As further shown in Figures 4A, 4B, 4D, and 4E, the second conductive lines WL of the memory cell array MCA can be connected to pads WP1 to WP4, respectively. The second conductive lines WL may have concave edges WE. The pads WP1 to WP4 may have inner edges PE. The inner edges PE of pads WP1 to WP4 may be convex in shape. The inner edges PE of pads WP1 to WP4 may be located in the inner space of the edge portion WE of the second conductive line WL. The inner edges PE of pads WP1 to WP4 and the edge portion WE of the second conductive line WL can be electrically connected. The inner edges PE of pads WP1 to WP4 and the edge portion WE of the second conductive line WL can be in contact with the first spacer SP1.

[0082] The second region R2 may comprise an alternating stack of pads WP1-WP4 and inter-pad insulating layer PL, and an array of contact plugs CT1-CT4 having different heights. The contact plugs CT1-CT4 are located within the alternating stack of pads WP1-WP4 and inter-pad insulating layer PL and can be spaced apart from each other laterally along a first horizontal direction (i.e., a third direction D3). The contact plugs CT1-CT4 may have different heights along the first direction D1. The top surfaces of the contact plugs CT1-CT4 are located on the same horizontal plane, and the bottom portions of each contact plug CT1-CT4 can be adjoined to individual pads WP1-WP4.

[0083] As further shown in Figure 4D, the first contact plug CT1 can be electrically connected to the first pad WP1 of the first level L1, and further, to the second conductive line WL of the first level L1 via the first pad WP1. The second contact plug CT2 can be electrically connected to the second pad WP2 of the second level L2, and further, to the second conductive line WL of the second level L2 via the second pad WP2. The third contact plug CT3 can be electrically connected to the third pad WP3 of the third level L3, and further, to the second conductive line WL of the third level L3 via the third pad WP3. The fourth contact plug CT4 can be electrically connected to the fourth pad WP4 of the fourth level L4, and further, to the second conductive line WL of the fourth level L4 via the fourth pad WP4.

[0084] A first contact spacer CTS1 may be positioned on the side wall of a first contact plug CT1, and a second contact spacer CTS2 may be positioned on the side wall of a second contact plug CT2. A third contact spacer CTS3 may be positioned on the side wall of a third contact plug CT3, and a fourth contact spacer CTS4 may be positioned on the side wall of a fourth contact plug CT4. The vertical height of the fourth contact plug CT4 may be greater than the vertical height of the third contact plug CT3, and the vertical height of the third contact plug CT3 may be greater than the vertical height of the second contact plug CT2. The vertical height of the second contact plug CT2 may be greater than the vertical height of the first contact plug CT1. Here, vertical height may refer to the height along a first direction D1.

[0085] The fourth contact plug CT4 and the fourth contact spacer CTS4 can penetrate the pads WP1, WP2, and WP3 of the first level L1, the second level L2, and the third level L3. The fourth contact plug CT4 can be electrically isolated from the pads WP1, WP2, and WP3 of the first level L1, the second level L2, and the third level L3 by the fourth contact spacer CTS4.

[0086] The third contact plug CT3 and the third contact spacer CTS3 can penetrate the pads WP1 and WP2 at the first level L1 and the second level L2. The third contact plug CT3 can be electrically isolated from the pads WP1 and WP2 at the first level L1 and the second level L2 by the third contact spacer CTS3.

[0087] The second contact plug CT2 and the second contact spacer CTS2 can penetrate the first level L1 pad WP1. The second contact plug CT2 can be electrically isolated from the first level L1 pad WP1 by the second contact spacer CTS2.

[0088] The first pad WP1 can surround the sides of the second to fourth contact plugs CT2, CT3, and CT4. The second pad WP2 can surround the sides of the third and fourth contact plugs CT3 and CT4. The third pad WP3 can surround the side of the fourth contact plug CT4.

[0089] The first pad WP1 can directly contact the bottom surface of the first contact plug CT1. The second pad WP2 can directly contact the bottom surface of the second contact plug CT2. The third pad WP3 can directly contact the bottom surface of the third contact plug CT3. The fourth pad WP4 can directly contact the bottom surface of the fourth contact plug CT4.

[0090] At the same horizontal level, the second conductive line WL of the first subcell array MCA1 and the second conductive line WL of the second subcell array MCA2 can share pads WP1 to WP4 at each level. For example, the second pad WP2 can be connected in common to both the second conductive line WL of the first subcell array MCA1 and the second conductive line WL of the second subcell array MCA2.

[0091] As described above, the pads WP1 to WP4 of the second region R2 can be stairless. Since the pads WP1 to WP4 are formed in a stairless structure, the area (or volume) occupied by the pads WP1 to WP4 in the second region R2 can be reduced. In comparison, if the pads WP1 to WP4 are formed in a stairless structure, the second region R2 will have stairless pads WP1 to WP4, which may increase the area of ​​the second region R2.

[0092] Contact spacers CTS1 to CTS4 may include an insulating material. Contact spacers CTS1 to CTS4 may include silicon oxide, silicon nitride, or a combination thereof. In other embodiments, contact spacers CTS1 to CTS4 may include a low-k material having a dielectric constant of 4 or less, for example, 2.0 to 3.5. Contact spacers CTS1 to CTS4 may include SiCOH, SiOF, or a combination thereof. The dielectric constant of SiCOH can be about 3, which is lower than that of SiCO. The dielectric constant of SiCO can be about 4. Contact spacers CTS1 to CTS4 may have a dielectric constant lower than that of silicon oxide (SiO2) and SiCO.

[0093] An inter-pad insulating layer PIL may be located between pads WP1 to WP4. The inter-pad insulating layer PIL may contain an insulating material. The inter-pad insulating layer PIL may contain silicon oxide, silicon nitride, or a combination thereof. In other embodiments, the inter-pad insulating layer PIL may contain a low-k material having a dielectric constant of 4 or less, for example, a dielectric constant of 2.0 to 3.5. The inter-pad insulating layer PIL may contain SiCOH, SiOF, or a combination thereof. The dielectric constant of SiCOH can be about 3, which is lower than that of SiCO. The dielectric constant of SiCO can be about 4. The inter-pad insulating layer PIL may have a dielectric constant lower than that of silicon oxide (SiO2) and SiCO.

[0094] As further shown in Figure 4E, the outer edges of pads WP1 to WP4 can be in contact with the pad isolation layer WSL. The pad isolation layer WSL may include a stack of a first pad isolation layer WSL1, a second pad isolation layer WSL2, and a third pad isolation layer WSL3. The stack of the first pad isolation layer WSL1 and the second pad isolation layer WSL2 may form the lower pad isolation layer. A dummy sheet DP may be located between the first pad isolation layer WSL1 and the inter-pad insulating layer PIL. The dummy sheet DP may be made of the same material as the nanosheet HL.

[0095] As described above, the semiconductor device 100 may include vertical and horizontal arrangements of nanosheets HL, a second conductive line WL oriented horizontally while surrounding the horizontal arrangement of nanosheets HL, pads WP1 to WP4 connected to the edges of the second conductive line WL, an inter-pad insulating layer PIL located between pads WP1 to WP4, contact plugs CT1 to CT4 connected to pads WP1 to WP4 respectively, and contact spacers CTS1 to CTS4 formed on the side walls of contact plugs CT1 to CT4. The contact spacers CTS1 to CTS4 may include a low dielectric constant material. The inter-pad insulating layer PIL may also include a low dielectric constant material.

[0096] Since the contact spacers CTS1 to CTS4 contain a low dielectric constant material, the parasitic capacitance between the contact plugs CT2 to CT4 and the surrounding pads WP1 to WP3 can be reduced. In other words, because the contact spacers CTS1 to CTS4 contain a low dielectric constant material, the speed of the semiconductor device 100 can be increased and power consumption can be reduced.

[0097] Figures 5A to 34B are diagrams illustrating an example of a method for manufacturing a semiconductor device according to this embodiment.

[0098] Figure 5A is a plan view of the second mold layer level illustrating the method of forming the mold stack SB, Figure 5B is a cross-sectional view along A-A' in Figure 5A, and Figure 5C is a cross-sectional view along B-B' in Figure 5A.

[0099] As shown in Figures 5A to 5C, a mold stack SB can be formed on the substrate 11. The mold stack SB may include an alternating stack of a first mold layer 12 and a second mold layer 13. The mold stack SB can be formed in a first region R1 and a second region R2, respectively. The first region R1 may be a region in which a three-dimensional array of memory cells is formed, and the second region R2 may be a region in which pads and contact plugs connected to memory cells are formed. The first region R1 may be called an array region, and the second region R2 may be called a pad region or connection region. The second region R2 may be called a sharing connection region, a sharing contact region, or a common contact region.

[0100] The substrate 11 can be a material suitable for semiconductor processing. The substrate 11 may include a semiconductor substrate, a conductive material, a dielectric material, a semiconductive material, or a combination thereof. The substrate 11 may include silicon, monocrystalline silicon, polysilicon, amorphous silicon, silicon germanium, single-crystal silicon germanium, polycrystalline silicon germanium, carbon-doped silicon, epitaxial silicon, a combination thereof, or multilayers thereof. The substrate 11 may also contain other semiconductor materials such as germanium. The substrate 11 may also include a III / V semiconductor substrate, such as a compound semiconductor substrate like GaAs. The mold stack SB may include an alternating stack of a first mold layer 12 and a second mold layer 13.

[0101] To form the mold stack SB, the first mold layer 12 and the second mold layer 13 can be epitaxially grown alternately several times.

[0102] The first mold layer 12 and the second mold layer 13 can be made of different semiconductor materials. The first mold layer 12 can include silicon germanium or single-crystal silicon germanium. The second mold layer 13 can include single-crystal silicon. The first mold layer 12 and the second mold layer 13 can be formed by epitaxial growth. The lowest level first mold layer 12 can act as a seed layer during the epitaxial growth process. The first mold layer 12 can be thinner than the second mold layer 13. The first mold layer 12 can comprise a first epitaxially grown layer, and the second mold layer 13 can comprise a second epitaxially grown layer.

[0103] In this embodiment, the mold stack SB may consist of multiple single-crystal silicon-germanium layers and multiple single-crystal silicon layers stacked alternately. For example, the first mold layer 12 may be a single-crystal silicon-germanium layer, and the second mold layer 13 may be a single-crystal silicon layer. A stack of single-crystal silicon-germanium layers / single-crystal silicon layers ("SiGe / Si stack") may be stacked several times. The first mold layer 12 may be referred to as a "sacrificial layer," and the second mold layer 13 may be referred to as a nanosheet target layer or a recess target layer. The mold stack SB can be referred to as a vertical stack. The mold stack SB can alternately form multiple sacrificial layers and multiple nanosheet target layers. The sacrificial layer can be a single-crystal silicon germanium layer IL, and the nanosheet target layer can be a single-crystal silicon layer.

[0104] In the mold stack SB, the thickness ratio between the first mold layer 12 and the second mold layer 13 can be varied. For example, the thickness of the first mold layer 12 can be 5 to 20 nm, and the thickness of the second mold layer 13 can be 50 to 80 nm. The number of layers between the first mold layer 12 and the second mold layer 13 in the mold stack SB can also be varied. In another embodiment, a triple stack comprising the first mold layer 12 / second mold layer 13 / first mold layer 12 can be defined at the bottom and / or top of the mold stack SB. The second mold layer 13 of the triple stack can be thinner than the second mold layer 13 of the mold stack SB.

[0105] A first hard mask layer 14 can be formed on the mold stack SB. The first hard mask layer 14 may include an oxide-based material, a nitride-based material, a carbon-based material, or a combination thereof as an insulating material. For example, the first hard mask layer 14 may include SiO2, Si3N4, amorphous carbon, or a combination thereof.

[0106] Next, a portion of the mold stack SB can be etched using the first hard mask layer 14 as a barrier to form a plurality of sacrificial isolation openings 15. The sacrificial isolation openings 15 can be initial openings for cell isolation. When viewed from a top view, the cross-section of the sacrificial isolation opening 15 can be rectangular. In other embodiments, the cross-section of the sacrificial isolation opening 15 can be circular or elliptical. In other embodiments, the sacrificial isolation openings 15 can be referred to as "sacrificial isolation trenches". The sacrificial isolation openings 15 can extend vertically along a first direction D1 and can extend elongated along a second direction D2. The sacrificial isolation openings 15 can be arranged at regular intervals along a third direction D3. The bottom surface of the sacrificial isolation openings 15 can extend into the interior of the substrate 11.

[0107] A sacrificial separation opening 15 can be formed in the first region R1. While the sacrificial separation opening 15 is being formed, an edge sacrificial separation opening 15E can be formed. The edge sacrificial separation opening 15E can be formed at the boundary between the first region R1 and the second region R2. The edge sacrificial separation opening 15E may have a longer length along the second direction D2 than the sacrificial separation opening 15.

[0108] Figure 6A is a plan view of the second mold layer level illustrating the method of forming the sacrificial separation layer 16, and Figure 6B is a cross-sectional view along B-B' of Figure 6A.

[0109] As shown in Figures 6A and 6B, a sacrificial separation layer 16 can be formed to fill the sacrificial separation opening 15. The sacrificial separation layer 16 may contain the same material. The sacrificial separation layer 16 can be formed of an insulating material. The sacrificial separation layer 16 may have an etching selectivity ratio with respect to the mold stack SB. For example, the sacrificial separation layer 16 may contain silicon oxide, silicon nitride, oxide-bonded silicon carbide, nitride-bonded silicon carbide, or a combination thereof. The step of forming the sacrificial separation layer 16 may include the step of forming the sacrificial separation material on the mold stack SB to fill the sacrificial separation opening 15 and the step of planarizing the sacrificial separation material so that the surface of the first hard mask layer 14 is exposed.

[0110] The sacrificial separation layer 16 can extend perpendicularly along a first direction D1 and can extend elongated along a second direction D2. The sacrificial separation layers 16 can be arranged at regular intervals along a third direction D3. Individual sacrificial separation layers 16 may include a stack of a first sacrificial liner layer and a first sacrificial gap fill layer. The first sacrificial liner layer may be silicon nitride, and the first sacrificial gap fill layer may be silicon oxide. The sacrificial separation layer 16 can penetrate the mold stack SB along the first direction D1.

[0111] A sacrificial separation layer 16 can be formed in the first region R1. An edge sacrificial separation layer 16E can be formed while the sacrificial separation layer 16 is being formed. The edge sacrificial separation layer 16E can be formed at the boundary between the first region R1 and the second region R2. The edge sacrificial separation layer 16E can have a longer length along the second direction D2 than the sacrificial separation layer 16.

[0112] Figure 7A is a plan view of the second mold layer level illustrating the method of forming the sacrificial linear openings 18, 19, and Figure 7B is a cross-sectional view along A-A' in Figure 7A.

[0113] As shown in Figures 7A and 7B, a second hard mask layer 17 can be formed on the mold stack SB and the sacrificial separation layer 16. The second hard mask layer 17 may contain silicon nitride. The second hard mask layer 17 can be formed by etching the second hard mask material using a mask layer such as a photoresist. The second hard mask layer 17 may have multiple line-shaped openings defined.

[0114] The second hard mask layer 17 can be used as an etching barrier to etch a portion of the mold stack SB. This can form multiple sacrificial linear openings 18, 19 between the sacrificial isolation layers 16. The sacrificial linear openings 18, 19 may comprise a first sacrificial linear opening 18 and a second sacrificial linear opening 19. When viewed from a top view, the first sacrificial linear opening 18 and the second sacrificial linear opening 19 may be linear openings extending along a third direction D3. The first sacrificial linear opening 18 and the second sacrificial linear opening 19 may extend perpendicularly along a first direction D1. A sacrificial isolation layer 16 may be positioned between the first sacrificial linear opening 18 and the second sacrificial linear opening 19 along a second direction D2. When viewed from a top view, the cross-sections of the first and second sacrificial linear openings 18, 19 may be rectangular. In other embodiments, the cross-sections of the first and second sacrificial linear openings 18, 19 may be circular or elliptical. The first and second sacrificial linear openings 18 and 19 may have a width along the second direction D2 that is smaller than the width along the third direction D3. The first and second sacrificial linear openings 18 and 19 may be referred to as "sacrificial linear trenches". The sacrificial separation layer 16 and the first and second sacrificial linear openings 18 and 19 may not be in contact. The first sacrificial linear opening 18 and the second sacrificial linear opening 19 may have different horizontal lengths along the third direction D3.

[0115] The first and second sacrificial linear openings 18 and 19 can be formed in the first region R1. One end of the first sacrificial linear opening 18 can extend to be located between the edge sacrificial isolation layers 16E.

[0116] In the following section, the thicknesses of the first mold layer 12 and the second mold layer 13 will be shown enlarged in the cross-sectional view along A-A' for illustrative purposes. The thickness of the first mold layer 12 in the cross-sectional view along A-A' can be the same as the thickness of the first mold layer 12 in the cross-sectional view along B-B'. The thickness of the second mold layer 13 in the cross-sectional view along A-A' can be the same as the thickness of the second mold layer 13 in the cross-sectional view along B-B'.

[0117] Figure 8A is a plan view of the second mold layer level illustrating the method for forming the linear sacrificial layers 18L and 19L, and Figure 8B is a cross-sectional view along A-A' in Figure 8A.

[0118] As shown in Figures 8A and 8B, linear sacrificial layers 18L, 19L can be formed to satisfy the first and second sacrificial linear openings 18, 19. The linear sacrificial layers 18L, 19L may comprise a first linear sacrificial layer 18L and a second linear sacrificial layer 19L. When viewed from a top view, the first linear sacrificial layer 18L and the second linear sacrificial layer 19L may be linear in shape extending along a third direction D3. The first linear sacrificial layer 18L and the second linear sacrificial layer 19L may extend perpendicularly along a first direction D1. A sacrificial separation layer 16 may be positioned between the first linear sacrificial layer 18L and the second linear sacrificial layer 19L along a second direction D2. When viewed from a top view, the cross-sections of the first and second linear sacrificial layers 18L, 19L may be rectangular. In other embodiments, the cross-sections of the first and second linear sacrificial layers 18L, 19L may be circular or elliptical. The first and second linear sacrificial layers 18L and 19L may contain the same material. The first and second linear sacrificial layers 18L and 19L may be formed of an insulating material. For example, the first and second linear sacrificial layers 18L and 19L may contain silicon oxide, silicon nitride, oxide-bonded silicon carbide, nitride-bonded silicon carbide, or a combination thereof. The sacrificial separation layer 16 and the first and second linear sacrificial layers 18L and 19L may not be in contact.

[0119] The first and second linear sacrificial layers 18L and 19L can be formed in the first region R1. One end of the first linear sacrificial layer 18L can extend so as to be located between the edge sacrificial isolation layers 16E.

[0120] Figure 9A is a plan view of the second mold layer level to illustrate the resetting of the first mold layer 12, and Figure 9B is a cross-sectional view along A-A' in Figure 9A. Figure 9C is a cross-sectional view along B-B' in Figure 9A.

[0121] As shown in Figures 9A to 9C, the first linear sacrificial layer 18L can be selectively removed from the second linear sacrificial layer 19L. This can form a first linear opening 20. When viewed from a top view, the first linear opening 20 may be located horizontally separated from the second linear sacrificial layer 19L along the second direction D2.

[0122] The first mold layer 12 can be selectively recessed through the first linear opening 20.

[0123] To selectively recess the first mold layer 12, the difference in etching selectivity between the first mold layer 12 and the second mold layer 13 can be utilized. The first mold layer 12 can be removed using wet etching or dry etching. For example, if the first mold layer 12 comprises a silicon-germanium layer and the second mold layer 13 comprises a single-crystal silicon layer, the silicon-germanium layer can be etched using an etching solution or etching gas having a selectivity ratio with respect to the single-crystal silicon layer. The first mold layer of its original thickness may remain, as indicated by the drawing reference numeral "12A". The first mold layer 12A may remain in the first region R1, and the pad-side first mold layer 12B may remain in the second region R2.

[0124] Figure 10A is a plan view of the second mold layer level to illustrate the resetting of the second mold layer 13, and Figure 10B is a cross-sectional view along A-A' in Figure 10A. Figure 10C is a cross-sectional view along B-B' in Figure 10A.

[0125] As shown in Figures 10A to 10C, a portion (the first portion) of the second mold layer 13 can be recessed to form a narrow sheet (13N). Wet etching or dry etching can be used to recess the second mold layer 13. Partial recessing of the second mold layer 13 can form the original body portion (13A) and the narrow sheet (13N). The original body portion 13A can maintain its original thickness, while the narrow sheet 13N can have a thinner thickness than the original. The horizontal lengths of the original body portion 13A and the narrow sheet 13N along the second direction D2 can be the same or different. The combination of the original body portion 13A and the narrow sheet 13N can be referred to as a "pre-activated layer". The narrow sheet 13N can be referred to as a flat plate type sheet or a protruding narrow sheet.

[0126] The recessing process for forming the narrow sheet 13N can be referred to as a thinning process or trimming process of the second mold layer 13. The top, bottom, and sides of the second mold layer 13 can be recessed to form the narrow sheet 13N. The narrow sheet 13N can be referred to as a thin-body active layer. The narrow sheet 13N may comprise a single-crystal silicon layer. For example, the recessing process for forming the narrow sheet 13N can use HSC1 (Hot SC-1). HSC1 can include a solution of ammonium hydroxide (NH4OH), hydrogen peroxide (H2O2), and water (H2O) mixed in a 1:4:20 ratio. The second mold layer 13 can be selectively etched using such HSC1.

[0127] A narrow sheet 13N may be formed by a partial recess process on the second mold layer 13 as described above, and an inter-nano sheet recess (21) may be formed between vertically positioned narrow sheets 13N. The upper and lower surfaces of the narrow sheet 13N may each have a flat surface. The boundary between the original body portion 13A and the narrow sheet 13N may be vertical or have curvature. A first mold layer 12A may be positioned between vertically stacked original body portions 13A.

[0128] A narrow sheet 13N can be formed in the first region R1, and a pad-side narrow sheet 13P can be formed in the second region R2 while the narrow sheet 13N is being formed. The original body portion 13A may remain in the first region R1, and the second molded layer 13B on the pad side may remain in the second region R2.

[0129] Figure 11A is a plan view of a narrow sheet level illustrating the method of forming the sacrificial separation layer-level opening 22, and Figure 11B is a cross-sectional view along A-A' of Figure 11A. Figure 11C is a cross-sectional view along B-B' of Figure 11A. Figure 11D is a cross-sectional view along C-C' of Figure 11A.

[0130] As shown in Figures 11A to 11D, the sacrificial separation layer 16 can be selectively stripped through the inter-nanosheet recess 21. This allows for the formation of a sacrificial separation layer-level opening 22 between the original body portions 13A along a third direction D3.

[0131] The sacrificial separation layer-level opening 22 may expose the side of the first mold layer 12A, the side of the original body portion 13A, and the side of the narrow sheet 13N along the third direction D3.

[0132] A portion of the first hard mask layer 14 (see drawing reference numeral "14A" in Figure 11B) may be recessed while the sacrificial separation layer-level opening 22 is being formed. This may expand the space of the top-level inter-nanosheet recess 21.

[0133] The edge sacrificial isolation layer 16E may be removed while the sacrificial isolation layer-level opening 22 is being formed, thereby forming the edge sacrificial isolation layer-level opening 22E.

[0134] A sacrificial separation layer-level opening 22 can be formed in the first region R1.

[0135] Figure 12A is a narrow-sheet level plan view illustrating the method for forming the first inter-cell insulating layer 23. Figure 12B is a cross-sectional view along line B-B' of Figure 12A. Figure 12C is a cross-sectional view along line B-B' of Figure 12A. Figure 12D is a cross-sectional view along line C-C' of Figure 12A.

[0136] As shown in Figures 12A to 12D, a first inter-cell insulating layer 23 can be formed in the sacrificial isolation layer-level opening 22. The first inter-cell insulating layer 23 may include an insulating material. The first inter-cell insulating layer 23 may include silicon oxide, silicon nitride, oxide-bonded silicon carbide, or a combination thereof. The step of forming the first inter-cell insulating layer 23 may include the step of forming an insulating material that fills the sacrificial isolation layer-level opening 22 and the step of etching back the insulating material. While the first inter-cell insulating layer 23 is being formed, an edge inter-cell insulating layer 23E that fills the edge sacrificial isolation layer-level opening 22E may be formed.

[0137] The first inter-cell insulating layer 23 can fill a portion of the sacrificial isolation layer-level opening 23. The sides of the first mold layer 12A and the sides of the original body portion 13A can be covered by the first inter-cell insulating layer 23 along the third direction D3. The first inter-cell insulating layer 23 can expose the sides of the narrow sheet 13N. The remaining portion of the sacrificial isolation layer-level opening 22, i.e., the non-gapfilled portion (23G), can expose the sides of the narrow sheet 13N. The non-gapfilled portion (24G) can be defined between the narrow sheets 13N along the third direction D3. The first inter-cell insulating layer 23 can be formed in the first region R1.

[0138] After forming the first intercellular insulating layer 23, a nanosheet all-open recess (24) can be formed that opens all of the narrow sheets 13N. The nanosheet all-open recess 24 can be described as a combination of the inter-nanosheet recess 21 and the non-gap fill portion 23G of the sacrificial isolation layer-level opening 22. The nanosheet all-open recess 24 can expose all of the multiple narrow sheets 13N along the third direction D3.

[0139] Figure 13A is a plan view of a narrow sheet level illustrating the method for forming the first spacer layer 26A. Figure 13B is a cross-sectional view along line A-A' in Figure 13A. Figure 13C is a cross-sectional view along line B-B' in Figure 13A.

[0140] As shown in Figures 13A to 13C, a nanosheet insulating layer 25 can be formed on the exposed portion of the narrow sheet 13N. The nanosheet insulating layer 25 can be referred to as a gate insulating layer.

[0141] The nanosheet insulating layer 25 can be formed by oxidizing the surface of the narrow sheet 13N. In other embodiments, the nanosheet insulating layer 25 can be formed by a silicon oxide deposition step and an oxidation step. The nanosheet insulating layer 25 may include silicon oxide, silicon nitride, metal oxides, metal oxide nitrides, metal silicates, high-k materials, ferroelectric materials, anti-ferroelectric materials, or combinations thereof. The nanosheet insulating layer 25 may include SiO2, Si3N4, HfO2, Al2O3, ZrO2, AlON, HfON, HfSiO, HfSiON, or combinations thereof. The nanosheet insulating layer 25 can be formed on all surfaces of the narrow sheet 13N.

[0142] A first spacer layer 26A can be formed on the nanosheet insulating layer 25. The first spacer layer 26A may contain silicon nitride. The first spacer layer 26A can surround and cover the narrow sheet 13N on the nanosheet insulating layer 25. The first spacer layer 26A may be thicker than the nanosheet insulating layer 25.

[0143] A second inter-cell insulating layer 27A can be formed on the first spacer layer 26A. The second inter-cell insulating layer 27A may contain silicon dioxide.

[0144] The nanosheet insulating layer 25 and the first spacer layer 26A can also be formed on the surface of the substrate 11.

[0145] As described above, the first spacer layer 26A may be positioned between the narrow sheets 13N along the third direction D3.

[0146] Figure 14A is a plan view of a narrow sheet level illustrating the method for forming the first spacer 26. Figure 14B is a cross-sectional view along line A-A' in Figure 14A. Figure 14C is a cross-sectional view along line B-B' in Figure 14A.

[0147] As shown in Figures 14A to 14C, the second inter-cell insulating layer 27A can be cut through the first linear opening 20. Subsequently, the first spacer layer 26A can be selectively recessed. The remaining first spacer layer can become the first spacer 26, and the second inter-cell insulating layer can remain as indicated by the drawing reference numeral "27".

[0148] By forming the first spacer 26, linear surrounding recesses 28 that surround the narrow sheets 13N can be formed on the nanosheet insulating layer 25. A second inter-cell insulating layer 27 may be located between the vertically arranged linear surrounding recesses 28.

[0149] Figure 15A is a plan view of a narrow sheet level illustrating the method for forming the horizontal conductive line 29. Figure 15B is a cross-sectional view along line A-A' in Figure 15A. Figure 15C is a cross-sectional view along line B-B' in Figure 15A.

[0150] As shown in Figures 15A to 15C, a horizontal conductive line 29 can be formed that fills the linear surrounding recess 28. The horizontal conductive line 29 can extend horizontally along the third direction D3.

[0151] The step of forming the horizontal conductive line 29 may include the step of depositing a conductive material onto the nanosheet insulating layer 25 to fill linear surrounding recesses 28 and the step of horizontal etch back the conductive material. Each of the horizontal conductive lines 29 can simultaneously surround the same level of narrow sheet 13N. The horizontal conductive line 29 may include a metal-base material, a semiconductor material, or a combination thereof. The horizontal conductive line 29 may include molybdenum, molybdenum nitride, ruthenium, titanium nitride, tungsten, polysilicon, or a combination thereof. For example, the horizontal conductive line 29 may include a TiN / W stack in which titanium nitride and tungsten are sequentially stacked. The horizontal conductive line 29 may include an N-type work function material or a P-type work function material. The N-type work function material may have a low work function of 4.5 eV or less, and the P-type work function material may have a high work function of 4.5 eV or more. A second intercellular insulating layer 27 may be positioned between multiple horizontal conductive lines 29 along a first direction D1. The horizontal conductive lines 29 surrounding the narrow sheet 13N can be referred to as gate-all-around GAA electrodes. The narrow sheet 13N can be referred to as a nanosheet channel, nanowire, or nanowire channel.

[0152] A lower-level dummy horizontal electrode 29L may be formed on the surface of the substrate 11, and an upper-level dummy horizontal electrode 29U may be formed on the uppermost horizontal conductive line 29. The dummy horizontal electrodes 29L and 29U may have a non-surrounding shape.

[0153] Figure 16A is a plan view of a narrow sheet level illustrating the method for forming the second spacer 30. Figure 16B is a cross-sectional view along line A-A' in Figure 16A.

[0154] As shown in Figures 16A and 16B, a second spacer 30 can be formed on one side of the horizontal conductive line 29. The second spacer 30 may include silicon oxide, silicon nitride, oxide-bonded silicon carbide, an embedded air gap, or a combination thereof. Vapor deposition and etch-back of the spacer material may be performed to form the second spacer 30. The second spacer 30 may include a stack of silicon oxide liners and silicon nitride liners.

[0155] After forming the second spacer 30, a portion of the nanosheet insulating layer 25 can be cut to expose one side of the nanosheet 13N.

[0156] The second spacer 30 can surround the narrow sheet 13N at the same horizontal level along the third direction D3 on one side of the horizontal conductive line 29.

[0157] Next, a first bottom protective layer 31 can be formed on the surface of the substrate 11. The first bottom protective layer 31 may contain a material having an etching selectivity ratio with respect to the substrate 11. The first bottom protective layer 31 may contain an insulating material. The first bottom protective layer 31 may contain silicon oxide, silicon nitride, oxide-bonded silicon carbide, or a combination thereof.

[0158] Figure 17A is a plan view of the narrow sheet level to illustrate the method for forming the narrow sheet cut 32. Figure 17B is a cross-sectional view along line A-A' in Figure 17A.

[0159] As shown in Figures 17A and 17B, a first bottom protective layer 31 can be formed on the surface of the substrate 11. The first bottom protective layer 31 may contain a material having an etching selectivity ratio with respect to the substrate 11. The first bottom protective layer 31 may contain an insulating material. The first bottom protective layer 31 may contain silicon oxide, silicon nitride, oxide-bonded silicon carbide, or a combination thereof.

[0160] Next, one side of the narrow sheet 13N and one side of the nanosheet insulating layer 25 can be cut. This can form a narrow sheet cut 32 that is horizontally recessed from the edge of the second spacer 30. While the narrow sheet cut 32 is being formed, the surface of the substrate 11 can be protected by the first bottom protective layer 31. The narrow sheet cut 32 may be referred to as a "narrow sheet level recess".

[0161] Figure 18A is a narrow sheet-level plan view illustrating the method for forming the first contact node 33. Figure 18B is a cross-sectional view along line A-A' in Figure 18A.

[0162] As shown in Figures 18A and 18B, a first contact node 33 can be selectively formed from the edge of the narrow sheet 13N. The first contact node 33 can be formed via selective epitaxial growth SEG. The first contact node 33 can be an epitaxial layer of a silicon layer. The first contact node 33 can be a doped silicon epitaxial layer.

[0163] A first doped region 34 can be formed within one side surface of the narrow sheet 13N. A heat treatment process can be performed to form the first doped region 34, thereby allowing the dopant to diffuse from the first contact node 33.

[0164] Figure 19A is a plan view of a narrow sheet level illustrating the method for forming vertical conductive lines 35A and 35B. Figure 19B is a cross-sectional view along line A-A' in Figure 19A.

[0165] As shown in Figures 19A and 19B, a vertical conductive line 35 may be formed on the first contact node 33. An ohmic contact layer may be formed on the first contact node 33 before the vertical conductive line 35 is formed. The ohmic contact layer may include a metallic silicide such as titanium silicide or molybdenum silicide. The vertical conductive line 35 may comprise a first vertical conductive line 35A and a second vertical conductive line 35B.

[0166] The steps of forming the first and second vertical conductive lines 35A and 35B may include a step of depositing a metallic substance and a step of etching the metallic substance. The bottom portions 35C of adjacent first vertical conductive lines 35A and second vertical conductive lines 35B may be merged.

[0167] The first and second vertical conductive lines 35A and 35B can be vertically oriented along the first direction D1. The first and second vertical conductive lines 35A and 35B can comprise bit lines. The first and second vertical conductive lines 35A and 35B can include metals, metal-base materials, or combinations thereof. The first and second vertical conductive lines 35A and 35B can include metals, metal nitrides, metal silicides, or combinations thereof. The first and second vertical conductive lines 35A and 35B can include titanium nitride, tungsten, or combinations thereof. For example, the first and second vertical conductive lines 35A and 35B can include a titanium nitride / tungsten stack (TiN / W) in which titanium nitride and tungsten are stacked in that order.

[0168] The top portions of the first and second vertical conductive lines 35A and 35B can extend to a portion of the surface of the second hard mask layer 17.

[0169] The first and second vertical conductive lines 35A and 35B can be connected in common to a narrow sheet 13N arranged along the first direction D1.

[0170] Figure 20A is a nanosheet-level plan view illustrating the method for forming the pad separation opening 37. Figure 20B is a cross-sectional view along B-B' of Figure 20A. Figure 20C is a cross-sectional view along B1-B1' of Figure 20A.

[0171] As shown in Figures 20A to 20C, an array isolation layer 36 can be formed on the first and second vertical conductive lines 35A and 35B, satisfying a first linear opening 20. The array isolation layer 36 can extend vertically along a first direction D1 and horizontally along a third direction D3. The third direction D3 can form the array isolation layer 36 between the first vertical conductive line 35A and the second vertical conductive line 35B. The array isolation layer 36 may contain an insulating material. The array isolation layer 36 may contain silicon oxide, silicon nitride, an air gap, or a combination thereof.

[0172] Next, the first mold layer 12B on the pad side and the second mold layer 13B on the pad side can be etched in the second region R2 to form a plurality of pad separation openings 37. The pad separation openings 37 can extend horizontally along the third direction D3 and vertically along the first direction D1.

[0173] As further shown in Figures 20B and 20C, the edge portion 29E of the horizontal conductive line 29 can cover the edge of the second mold layer 13B on the pad side, with the nanosheet insulating layer 25 in between.

[0174] Figure 21A is a nanosheet-level plan view illustrating the method for forming the pad-side sheet 13PS. Figure 21B is a cross-sectional view along B-B' of Figure 21A. Figure 21C is a cross-sectional view along B1-B1' of Figure 21A.

[0175] As shown in Figures 21A to 21C, the first molded layer 12B and the second molded layer 13B on the pad side can be sequentially recessed in order to form the pad-side sheet 13PS. The first molded layer 12B on the pad side can be completely removed, and the upper and lower surfaces of the second molded layer 13B on the pad side can be recessed.

[0176] An inter-pad recess 38 may be formed between the pad-side sheets 13PS. The upper and lower surfaces of the narrow sheet 13N may each have a flat surface.

[0177] Of the 13 pad-side seats, the lowest level pad-side seat can be abbreviated as dummy seat 13DP.

[0178] The pad-side sheet 13PS can be a sacrificial sheet that will be replaced by the pad in a subsequent process. The horizontal lengths of the pad-side sheets 13PS can be the same as those of the other. The pad-side sheets 13PS can have a stair-less structure.

[0179] Figure 22A is a nanosheet-level plan view illustrating the method for forming the pad-side sacrificial layer 39. Figure 22B is a cross-sectional view along B-B' of Figure 22A. Figure 22C is a cross-sectional view along B1-B1' of Figure 22A.

[0180] As shown in Figures 22A to 22C, an inter-pad insulating layer 39 can be formed that fills the inter-pad recess 38. The inter-pad insulating layer 39 may have a selectivity ratio with respect to the pad-side sheet 13PS. The inter-pad insulating layer 39 may include silicon oxide, silicon nitride, or a combination thereof.

[0181] To form the inter-pad insulating layer 39, sacrificial material can be deposited and etched back. After the inter-pad insulating layer 39 is formed, the outer edges of the pad-side sheet 13PS and the dummy sheet 13DP may be exposed.

[0182] In other embodiments, the inter-pad insulating layer 39 may include a low-k material having a dielectric constant of 4 or less, for example, 2.0 to 3.5. The inter-pad insulating layer 39 may include SiCOH, Siof, or a combination thereof. The dielectric constant of SiCOH may be about 3, which is lower than that of SiCO. The dielectric constant of SiCO may be about 4.

[0183] Figure 23A is a nanosheet-level plan view illustrating the method for forming the initial contact holes 41A, 41B, 41C, and 41D. Figure 23B is a cross-sectional view along B-B' of Figure 23A. Figure 23C is a cross-sectional view along B1-B1' of Figure 23A. As shown in Figures 23A to 23C, first and second pad separation layers 40A and 40B can be formed to fill the bottom portion of the pad separation opening 37.

[0184] Next, multiple contact holes 41A, 41B, 41C, and 41D can be sequentially formed in the second region R2.

[0185] To form the first contact hole 41A, the first to third hard mask layers 14, 17, 17T and the uppermost level inter-pad insulating layer 39 can be etched. The first contact hole 41A can expose the upper surface of the pad-side sheet 13PS at the first level L1.

[0186] After masking the first contact hole 41A, the first to third hard mask layers 14, 17, 17T and the pad-side sheet 13PS at the first level can be etched to form the second contact hole 41B. Furthermore, the inter-pad insulating layer 39 at the uppermost level and the inter-pad insulating layer 39 between the first level L1 and the second level L2 can be etched to form the second contact hole 41B. The second contact hole 41B can expose the upper surface of the pad-side sheet 13PS at the second level L2.

[0187] After masking the first and second contact holes 41A and 41B, the first to third hard mask layers 14, 17, and 17T and the pad-side sheets 13PS at the first level L1 and the second level L2 can be etched to form the third contact hole 41C. Furthermore, to form the third contact hole 41C, the inter-pad insulating layer 39 at the top level, the inter-pad insulating layer 39 between the first level L1 and the second level L2, and the inter-pad insulating layer 39 between the second level L2 and the third level L3 can be etched. The third contact hole 41C can expose the upper surface of the pad-side sheet 13PS at the third level L3.

[0188] After masking the first, second, and third contact holes 41A, 41B, and 41C respectively, the first to third hard mask layers 14, 17, and 17T, the pad-side sheet 13PS at the first level, the pad-side sheet 13PS at the second level L2, and the pad-side sheet 13PS at the third level L3 can be etched to form the fourth contact hole 41D. Furthermore, to form the fourth contact hole 41D, the inter-pad insulating layer 39 at the top level, the inter-pad insulating layer 39 between the first level L1 and the second level L2, the inter-pad insulating layer 39 between the second level L2 and the third level L3, and the inter-pad insulating layer 39 between the third level L3 and the fourth level L4 can be etched. The fourth contact hole 41D can expose the upper surface of the pad-side sheet 13PS at the fourth level L4.

[0189] As described above, when forming the second contact hole 41B after forming the first contact hole 41A, the first contact hole 41A can be masked. When forming the third contact hole 41C, the first and second contact holes 41A and 41B can be masked. When forming the fourth contact hole 41D, the first, second, and third contact holes 41A, 41B, and 41C can be masked. In other embodiments, the order in which the first to fourth contact holes 41A to 41D are formed can be varied in various ways.

[0190] Through the series of contact hole formation steps described above, a first contact hole 41A, a second contact hole 41B, a third contact hole 41C, and a fourth contact hole 41D can be formed sequentially. The first contact hole 41A may be shallower than the second contact hole 41B, the second contact hole 41B may be shallower than the third contact hole 41C, and the third contact hole 41C may be shallower than the fourth contact hole 41D. The depths of the first to fourth contact holes 41A to 41D may gradually decrease along the lamination direction of the pad-side sheet 13PS, i.e., the first direction D1.

[0191] The second contact hole 41B can penetrate the pad-side sheet 13PS of the first level L1, and the third contact hole 41C can penetrate the pad-side sheets 13PS of the first and second levels L1 and L2. The fourth contact hole 41D can penetrate the pad-side sheets 13PS of the first to third levels L1, L2, and L3. The first contact hole 41A does not have to penetrate the pad-side sheet 13PS of the first level L1.

[0192] In other embodiments, the multiple contact holes 41A, 41B, 41C, and 41D can be formed sequentially from the deepest contact hole. For example, they can be formed in the order of the fourth contact hole 41D, the third contact hole 41C, the second contact hole 41B, and the first contact hole 41A. The order in which the fourth contact hole 41D, the third contact hole 41C, the second contact hole 41B, and the first contact hole 41A are formed can be varied in various ways.

[0193] Figure 24A is a nanosheet-level plan view illustrating the method for forming the contact spacers 42A-43D and sacrificial plugs 43A-43D. Figure 24B is a cross-sectional view along B-B' of Figure 24A. Figure 24C is a cross-sectional view along B1-B1' of Figure 24A.

[0194] As shown in Figures 24A to 24C, contact spacers 42A to 42D can be formed on the side walls of the first contact hole 41A, the second contact hole 41B, the third contact hole 41C, and the fourth contact hole 41D, respectively. Contact spacers 42A to 42D can be formed by vapor deposition and etching of an insulating material. Contact spacers 42A to 42D may include silicon oxide, silicon nitride, or a combination thereof. Contact spacers 42A to 42D may include low dielectric constant materials. Contact spacers 42A to 43D may include low-k material having a dielectric constant of 4 or less, for example, a dielectric constant of 2.0 to 3.5. Contact spacers 42A to 43D may include SiCOH, Siof, or a combination thereof. The dielectric constant of SiCOH can be about 3, which is lower than that of SiCO. The dielectric constant of SiCO can be about 4.

[0195] Next, sacrificial plugs 43A to 43D can be formed on the contact spacers 42A to 42D to fill the first contact hole 41A, the second contact hole 41B, the third contact hole 41C, and the fourth contact hole 41D. Sacrificial plugs 43A to 43D can be formed by a deposition and planarization process of the sacrificial plug material. Sacrificial plugs 43A to 43D can include a metal-base material. For example, sacrificial plugs 43A to 43D can be formed by deposition of a tungsten layer and chemical mechanical polishing (CMP).

[0196] Sacrificial plugs 43A to 43D may include a structure in which the height gradually decreases along the stacking direction of the pad-side sheet 13PS (i.e., the first direction D1).

[0197] As described above, a pad-side sheet 13PS, contact spacers 42A to 42D, and sacrificial plugs 43A to 43D may be formed in the second region R2.

[0198] A first contact spacer 42A may be positioned on the side wall of the first sacrificial plug 43A, and a second contact spacer 42B may be positioned on the side wall of the second sacrificial plug 43B. A third contact spacer 42C may be positioned on the side wall of the third sacrificial plug 43C, and a fourth contact spacer 42D may be positioned on the side wall of the fourth sacrificial plug 43D. The vertical height of the fourth sacrificial plug 43D may be greater than the vertical height of the third sacrificial plug 43C, and the vertical height of the third sacrificial plug 43C may be greater than the vertical height of the second sacrificial plug 43B. The vertical height of the second sacrificial plug 43B may be greater than the vertical height of the first sacrificial plug 43A. Here, vertical height may refer to the height along the first direction D1.

[0199] The fourth sacrificial plug 43D and the fourth contact spacer 42D can penetrate the pad-side sheet 13PS and the inter-pad insulating layer 39 at the first level L1, the second level L2, and the third level L3. The fourth contact plug 43D can be electrically isolated from the pad-side sheet 13PS at the first level L1, the second level L2, and the third level L3 by the fourth contact spacer 42D.

[0200] The third sacrificial plug 43C and the third contact spacer 42C can penetrate the pad-side sheet 13PS and the inter-pad insulating layer 39 of the first level L1 and the second level L2. The third sacrificial plug 43C can be electrically isolated from the pad-side sheet 13PS of the first level L1 and the second level L2 by the third contact spacer 42C.

[0201] The second sacrificial plug 43B and the second contact spacer 42B can penetrate the pad-side sheet 13PS and the inter-pad insulating layer 39 of the first level L1. The second sacrificial plug 43B can be electrically isolated from the pad-side sheet 13PS of the first level L1 by the second contact spacer 42B.

[0202] Figure 25A is a nanosheet-level plan view illustrating the method for forming the pad-type opening 45. Figure 25B is a cross-sectional view along B-B' of Figure 25A. Figure 25C is a cross-sectional view along B1-B1' of Figure 25A.

[0203] As shown in Figures 25A to 25C, the pad separation layers 40A and 40B can be recessed. This allows for the definition of a pad separation opening 44 with a reduced height above the recessed pad separation layers 40A and 40B.

[0204] The pad separation opening 44 allows the outer surfaces of the pad-side sheet 13PS and the inter-pad insulating layer 39 to be exposed. The dummy sheet 13DP may not be exposed by the recessed pad separation layers 40A and 40B.

[0205] Next, the pad-side sheet 13PS can be selectively removed to form a pad-type opening 45 between the pad-type insulating layers 39. The pad-type opening 45 may have an inner edge 45E, which can expose the nanosheet insulating layer 25.

[0206] Next, the nanosheet insulating layer 25 can be cut through the inner edge 45E of the pad-shaped opening 45. This allows the edge portion 29E of the horizontal conductive line 29 to be exposed.

[0207] Figure 26A is a nanosheet-level plan view illustrating the method of forming the pad 46. Figure 26B is a cross-sectional view along B-B' of Figure 26A. Figure 26C is a cross-sectional view along B1-B1' of Figure 26A.

[0208] As shown in Figures 26A to 26C, a pad 46 can be formed to fill the pad-shaped opening 45. To form the pad 46, deposition and etching of the pad material may be performed. The pad 46 and the horizontal conductive line 29 can be electrically connected. The pad 46 and the horizontal conductive line 29 can be made of the same material. The pad 46 may include titanium nitride, tungsten, or a combination thereof. The pad 46 may have an inner edge 46E, and the inner edge 46E of the pad 46 can be connected to the edge portion 29E of the horizontal conductive line 29.

[0209] As described above, an inter-pad insulating layer 39 may be located between the pads 46. If the inter-pad insulating layer 39 contains a low dielectric constant material, the parasitic capacitance between the pads 46 can be reduced. In other words, the parasitic capacitance between the horizontal conductive lines 29 can be reduced.

[0210] Figure 27A is a nanosheet-level plan view illustrating the method for forming plug openings 47A-47D. Figure 27B is a cross-sectional view along B-B' of Figure 27A. Figure 27C is a cross-sectional view along B1-B1' of Figure 27A.

[0211] As shown in Figures 27A to 27C, a third pad separation layer 40C can be formed that fills the pad separation opening 44.

[0212] Next, the sacrificial plugs 43A to 43D can be removed to form the plug openings 47A to 47D. Then, the bottom surfaces of the contact spacers 42A to 42D can be cut to expand the plug openings 47A to 47D.

[0213] The first plug opening 47A may be shallower than the second plug opening 47B, the second plug opening 47B may be shallower than the third plug opening 47C, and the third plug opening 47C may be shallower than the fourth plug opening 47D. The depths of the plug openings 47A to 47D may gradually decrease along the stacking direction of the pad 46, i.e., the first direction D1.

[0214] The second plug opening 47B can penetrate the pad 46 at the first level L1, and the third plug opening 47C can penetrate the pads 46 at the first and second levels L1 and L2. The fourth plug opening 47D can penetrate the pads 46 at the first to third levels L1, L2, and L3. The first plug opening 47A does not have to penetrate the pad 46 at the first level L1.

[0215] The first plug opening 47A can expose the upper surface of the pad 46 at the first level, and the second plug opening 47B can expose the upper surface of the pad 46 at the second level. The third plug opening 47C can expose the upper surface of the pad 46 at the third level, and the fourth plug opening 47D can expose the upper surface of the pad 46 at the fourth level. Here, the first through fourth levels are shown in Figure 23B.

[0216] Figure 28A is a nanosheet-level plan view illustrating the method for forming contact plugs 48A-48B. Figure 28B is a cross-sectional view along B-B' of Figure 28A. Figure 28C is a cross-sectional view along B1-B1' of Figure 28A.

[0217] As shown in Figures 28A to 28C, contact plugs 48A to 48D can be formed to satisfy the plug openings 47A to 47D. The contact plugs 48A to 48D can be formed by a deposition and planarization process of the plug material. The contact plugs 48A to 48D can contain a metal-base material. For example, the contact plugs 48A to 48D can be formed by deposition of a tungsten layer and chemical mechanical polishing (CMP).

[0218] The contact plugs 48A to 48D may include a structure in which the height gradually decreases along the stacking direction of the pad 46 (i.e., the first direction D1). The contact plugs 48A to 48B may be oriented vertically along the first direction D1. The contact plugs 48A to 48B may be referred to as contact pillars.

[0219] As described above, a pad 46, contact spacers 42A to 42D, and contact plugs 48A to 48D may be formed in the second region R2.

[0220] A first contact spacer 42A may be positioned on the side wall of the first contact plug 48A, and a second contact spacer 42B may be positioned on the side wall of the second contact plug 48B. A third contact spacer 42C may be positioned on the side wall of the third contact plug 48C, and a fourth contact spacer 42D may be positioned on the side wall of the fourth contact plug 48D. The vertical height of the fourth contact plug 48D may be greater than the vertical height of the third contact plug 48C, and the vertical height of the third contact plug 48C may be greater than the vertical height of the second contact plug 48B. The vertical height of the second contact plug 48B may be greater than the vertical height of the first contact plug 48A. Here, vertical height may refer to the height along the first direction D1.

[0221] The fourth contact plug 48D and the fourth contact spacer 42D can penetrate the pads 46 and inter-pad insulating layer 39 at the first level L1, the second level L2, and the third level L3. The fourth contact plug 48D can be electrically isolated from the pads 46 at the first level L1, the second level L2, and the third level L3 by the fourth contact spacer 42D. The fourth contact plug 48D can be electrically connected to the pad 46 at the fourth level L4.

[0222] The third contact plug 48C and the third contact spacer 42C can penetrate the pads 46 at the first level L1 and the second level L2 and the inter-pad insulating layer 39. The third contact plug 48C can be electrically isolated from the pads 46 at the first level L1 and the second level L2 by the third contact spacer 42C. The third contact plug 48C can be electrically connected to the pad 46 at the third level L3.

[0223] The second contact plug 48B and the second contact spacer 42B can penetrate the pad 46 at the first level L1 and the inter-pad insulating layer 39. The second contact plug 48B can be electrically isolated from the pad 46 at the first level L1 by the second contact spacer 42B. The second contact plug 48B can be electrically connected to the pad 46 at the second level L2.

[0224] The first contact plug 48A can be electrically connected to the pad 46 of the first level L1.

[0225] The second to fourth contact plugs 48B to 48D can constitute a stairless contact structure. In other embodiments, the number of contact plugs can be varied depending on the number of stacked memory cells.

[0226] Figure 29A is a nanosheet-level plan view illustrating the method for forming the second linear opening 49. Figure 29B is a cross-sectional view along A-A' in Figure 29A. As shown in Figures 29A and 29B, the second linear sacrificial layer 19L can be removed by using the fourth hard mask layer 49T as a barrier. This allows a second linear opening 49 to be formed in the first region R1.

[0227] After forming the second linear opening 49, the first mold layer 12A can be selectively recessed through the second linear opening 49. To selectively recess the first mold layer 12A, the difference in etching selectivity between the first mold layer 12A and the original body portion 13A can be utilized. The first mold layer 12A can be removed using wet etching or dry etching. For example, if the first mold layer 12A comprises a silicon-germanium layer and the original body portion 13A comprises a single-crystal silicon layer, the silicon-germanium layer can be etched using an etching solution or etching gas that has a selectivity ratio with respect to the single-crystal silicon layer.

[0228] Next, the original body portion 13A can be recessed. Wet etching or dry etching can be used to recess the original body portion 13A. The original body portion 13A can have a reduced vertical thickness, such as "13S". Hereinafter, it is abbreviated as the recessed body portion 13S.

[0229] An inter-body recess 12R can be formed between the vertically arranged recessed body portions 13S.

[0230] FIG. 30A is a plan view at the nano-sheet level for explaining the method of forming the nano-sheet HL. FIG. 30B is a cross-sectional view taken along the line A-A' of FIG. 30A.

[0231] As shown in FIGS. 30A and 30B, a third inter-cell insulating layer 50 filling the inter-body recess 12R can be formed. The third inter-cell insulating layer 50 can contain silicon oxide.

[0232] After forming the third inter-cell insulating layer 50, a second bottom protection layer 51T can be formed at the bottom of the second linear opening 49. The second bottom protection layer 51T can contain a material having an etching selectivity ratio with respect to the substrate 11. The second bottom protection layer 51T can contain an insulating material. The second bottom protection layer 51T can contain silicon oxide, silicon nitride, oxide-bonded silicon carbide, or a combination thereof.

[0233] After forming the second bottom protective layer 51T, a storage opening (51) may be formed by horizontal recessing of the recessed body portion 13S. The storage opening 51 may be referred to as a capacitor opening. Horizontal recessing of the recessed body portion 13S may result in a nanosheet HL. Each nanosheet HL may comprise a narrow sheet 13N and a wide sheet 13W. The wide sheet 13W of the nanosheet HL may refer to the recessed body portion 13S remaining after recessing. The average vertical height of the wide sheet 13W of the nanosheet HL along the first direction D1 may be greater than the average vertical height of the narrow sheet 13N. The thickness of the wide sheet 13W of the nanosheet HL may gradually increase along the second direction D2. The horizontal length of the wide sheet 13W along the second direction D1 may be less than the horizontal length of the narrow sheet 13N. The wide sheet 13W of the nanosheet HL may be fan-like in shape. The wide sheet 13W can be referred to as a fan-shaped sheet, and the narrow sheet 13N can be referred to as a flat plate-type sheet.

[0234] To form a nanosheet HL comprising a wide sheet 13W, the recessed body portion 13S can be isotropically or anisotropically etched. One side of the wide sheet 13W, i.e., the side exposed by the storage opening 44, can be flat. One side of the wide sheet 13W can have various shapes.

[0235] One side of the wide sheet 13W can have various shapes. For example, one side of the wide sheet 13W can have a rounded concave shape, a rounded convex shape, an angled concave shape, or an angled convex shape.

[0236] The second bottom protective layer 51T and the lowest level third inter-cell insulating layer 47 can prevent loss of the substrate 11 during the recessing process of the recessed body portion 13S. A storage opening 51 may be located between the third inter-cell insulating layer 50 along the first direction D1.

[0237] In another embodiment, the horizontal recessing of the recessed body portion 13S for forming the wide seat 13W can be stopped in the boundary area between the narrow seat 13N and the wide seat 13W.

[0238] The first spacer 26 can surround wide sheets 13W arranged along the third direction D3 at the same horizontal level, and the second spacer 30 can surround narrow sheets 13N arranged along the third direction D3 at the same horizontal level.

[0239] Figure 31A is a narrow sheet-level plan view illustrating the method for forming the second contact node 52. Figure 31B is a cross-sectional view along line A-A' in Figure 31A. As shown in Figures 31A and 31B, a pre-cleaning step may be performed on the surface of the wide sheet 13W.

[0240] A second contact node 52 can be formed on the wide sheet 13W. The step of forming the second contact node 52 may include selective epitaxial growth (SEG). For example, a semiconductor material can be grown from the side of the wide sheet 13W via selective epitaxial growth SEG. The second contact node 52 may include SEG Si. Since the wide sheet 13W contains single-crystal silicon, a silicon layer can be epitaxially grown along the crystal plane of the side of the wide sheet 13W.

[0241] The second contact node 52 may contain a dopant. When growing a silicon layer using selective epitaxial growth SEG, dopant doping can be performed in-situ. Therefore, the second contact node 52 may be a doped epitaxial layer. The second contact node 52 may contain an N-type dopant as the dopant. The N-type dopant may contain phosphorus, arsenic, antimony, or a combination thereof. The second contact node 52 may contain a phosphorus-doped silicon epitaxial layer by selective epitaxial growth, i.e., a doped SEG SiP. In other embodiments, the second contact node 52 may be formed via deposition and etch-back of doped polysilicon.

[0242] The second contact node 52 can be located between the vertically stacked third inter-cell insulating layers 50. The second contact node 52 can correspond to the second contact node SNC in Figure 4B.

[0243] A second doped region 53 can be formed within the wide sheet 13W. A heat treatment process can be performed to form the second doped region 53, thereby allowing the dopant to diffuse from the second contact node 52.

[0244] A channel 54 may be defined between the first doped region 34 and the second doped region 53. The horizontal arrangement of the first doped region 34, the channel 54, and the second doped region 53 can form a nanosheet HL.

[0245] Each nanosheet HL may comprise a first doped region 34, a second doped region 53, and a channel 54. The first doped region 34 and the channel 54 may be formed within a narrow sheet 13N, and the second doped region 53 may be formed within a wide sheet 13W. A portion of the second doped region 53 may extend within the narrow sheet 13N. One side of the second doped region 53 of the nanosheet HL may be connected to the channel 54, and the other side of the second doped region 53 of the nanosheet HL may be connected to a second contact node 52.

[0246] The first spacer 26 can surround a second doped region 53 at the same horizontal level, arranged along the third direction D3, and the second spacer 30 can surround a first doped region 34 at the same horizontal level, arranged along the third direction D3. The horizontal conductive line 29 can surround a channel 54 at the same horizontal level, arranged along the third direction D3.

[0247] In other embodiments, an ohmic contact layer containing a metal silicide may be further formed after the formation of the second contact node 52.

[0248] As described above, the second mold layer 13 of the mold stack SB may have nanosheets HL formed by subsequent selective re-cleansing, and each nanosheet HL may comprise a narrow sheet 13N and a wide sheet 13W. A first doped region 34 and channel 54 may be formed within the narrow sheet 13N, and a second doped region 53 may be formed within the wide sheet 13W.

[0249] Figure 32A is a narrow sheet-level plan view illustrating the method for forming the first electrode 55. Figure 32B is a cross-sectional view along line A-A' in Figure 32A.

[0250] As shown in FIGS. 32A and 32B, a first electrode 55 of a data storage element can be formed on the second contact node 52. The first electrode 55 can be in a horizontally oriented cylinder shape. The first electrodes 55 can be respectively disposed within the storage openings 51. The first electrodes 55 adjacent to each other along the second direction D2 can be separated by the second linear opening 49. The first electrodes 55 adjacent to each other along the first direction D1 can be separated from each other by the third inter-cell insulating layer 50. The step of forming the first electrode 55 can include a step of depositing a metal substance, a step of filling a sacrificial substance gap, and a step of separating the metal substance in the vertical / horizontal directions. The sacrificial substance can include an oxide or polysilicon.

[0251] The first electrode 55 can include an inner space and a plurality of outer surfaces. The inner space of the first electrode 55 can include a plurality of inner surfaces. The outer surfaces of the first electrode 55 can include vertical outer surfaces and a plurality of horizontal outer surfaces. The vertical outer surfaces of the first electrode 55 can extend vertically along the first direction D1, and the horizontal outer surfaces of the first electrode 55 can extend horizontally along the second direction D2 or the third direction D3. The inner space of the first electrode 55 can be a three-dimensional space. The first electrode 55 can be in a cylinder shape.

[0252] Among the outer surfaces of the first electrode 55, the vertical outer surfaces can be electrically connected to the nanosheet HL and the second contact node 52.

[0253] The first electrode 55 may include metals, noble metals, metal nitrides, conductive metal oxides, conductive noble metal oxides, metal carbides, metal silicides, or combinations thereof. For example, the first electrode 55 may include titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO2), iridium (Ir), iridium oxide (IrO2), platinum (Pt), molybdenum (Mo), molybdenum oxide (MoO), titanium nitride / tungsten (TiN / W) stacks, tungsten nitride / tungsten (WN / W) stacks, titanium silicon nitride / titanium nitride (TiSiN / TiN) stacks, or combinations thereof.

[0254] Figure 33A is a narrow-sheet level plan view illustrating the partial reduction of the third inter-cell insulating layer 50. Figure 33B is a cross-sectional view along line A-A' in Figure 33A.

[0255] As shown in Figures 33A and 33B, portions of the first and third inter-cell insulating layers 23 and 50 can be horizontally recessed (see reference numeral 56). This allows the outer wall of the first electrode 55 to be partially exposed. The first electrode 55 can have a semi-cylindrical shape. The horizontal recess depth of the third inter-cell insulating layer 50 can be such that the second contact node 52 is not exposed. The semi-cylindrical shape of the first electrode 55 can include an inner cylinder surface and a semi-cylindrical outer surface.

[0256] Figure 34A is a narrow sheet-level plan view illustrating the method for forming the second electrode 58. Figure 34B is a cross-sectional view along line A-A' in Figure 34A.

[0257] As shown in Figures 34A and 34B, a dielectric layer 57 and a second electrode 58 can be sequentially formed on the first electrode 55. The first electrode 52, the dielectric layer 54, and the second electrode 55 can become a data storage element CAP. The second electrode 58 of the data storage element CAP can be merged to form a common plate PL.

[0258] A dielectric layer 57 and a second electrode 58 may be arranged on the inner surface of the cylinder of the first electrode 55. A portion of the dielectric layer 57 and the second electrode 58 may extend so as to be located on the outer surface of the semi-cylinder of the first electrode 55.

[0259] The dielectric layer 57 may be referred to as a capacitor dielectric layer or a memory layer. The dielectric layer 57 may include silicon oxide, silicon nitride, high dielectric constant materials, ferroelectric materials, antiferroelectric materials, perovskite materials, or combinations thereof. The dielectric layer 57 may also include hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium pentoxide (Nb2O5), or strontium titanate (SrTiO3). The dielectric layer 49 consists of ZA (ZrO2 / Al2O3) stacks, ZAZA (ZrO2 / Al2O3 / ZrO2 / Al2O3) stacks, ZAZAZ (ZrO2 / Al2O3 / ZrO2 / Al2O3 / ZrO2) stacks, HAHA (HfO2 / Al2O3 / HfO2 / Al2O3) stacks, HAHAH (HfO2 / Al2O3 / HfO2 / Al2O3 / HfO2) stacks, and HZAZH (HfO2 / ZrO2 / Al2O3 / ZrO2 / HfO2) This may include a stack, a ZHZAZHZ (ZrO2 / HfO2 / ZrO2 / Al2O3 / ZrO2 / HfO2 / ZrO2) stack, an HZHZ (HfO2 / ZrO2 / HfO2 / ZrO2) stack, an AHZAZHA (Al2O3 / HfO2 / ZrO2 / Al2O3 / ZrO2 / HfO2 / Al2O3) stack, or an AHZAHZA (Al2O3 / HfO2 / ZrO2 / Al2O3 / HfO2 / ZrO2 / Al2O3) stack.

[0260] The second electrode 58 may include metals, noble metals, metal nitrides, conductive metal oxides, conductive noble metal oxides, metal carbides, metal silicides, or combinations thereof. For example, the second electrode 58 may include titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO2), iridium (Ir), iridium oxide (IrO2), platinum (Pt), molybdenum (Mo), molybdenum oxide (MoO), titanium nitride / tungsten (TiN / W) stacks, tungsten nitride / tungsten (WN / W) stacks, titanium silicon nitride / titanium nitride (TiSiN / TiN) stacks, titanium silicon nitride / titanium nitride / tungsten (TiSiN / TiN / W) stacks, or combinations thereof. The second electrode 58 may also include a combination of a metal-based material and a silicon-based material. For example, the second electrode 58 can be stacked in the order of titanium nitride / tungsten / polysilicon.

[0261] In other embodiments, the interface may further include multiple interface control layers for leakage current improvement between the first electrode 55 and the dielectric layer 57 and between the dielectric layer 57 and the second electrode 58. The interface control layers may include titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium pentoxide (Nb2O5), niobium nitride (NbN), niobium oxynitride (NbON), or a combination thereof. The data storage element CAP may include the first interface control layer, the second interface control layer, or a combination thereof. The first and second interface control layers may be conductive or insulating. The first interface control layer may be formed between the first electrode 55 and the dielectric layer 57, and the second interface control layer may be formed between the dielectric layer 57 and the second electrode 58. The first and second interface control layers may be the same material or different materials. For example, a structure in which a first interface control layer, a dielectric layer 57, and a second interface control layer of a data storage element CAP are stacked in that order may include an NZHZAZHZATN(Nb2O5 / ZrO2 / HfO2 / ZrO2 / Al2O3 / ZrO2 / HfO2 / ZrO2 / Al2O3 / TiO2 / Nb2O5) stack.

[0262] In other embodiments, the resetting of the first and third inter-cell insulating layers 23, 50 in Figure 33B may be omitted. Subsequently, a dielectric layer 57 and a second electrode 58 may be formed, as shown in Figure 34B. This may form a data storage element CAP having a concave first electrode 55.

[0263] Figures 35 to 37 are schematic cross-sectional views of semiconductor devices according to other embodiments. Figures 35 to 37 can be similar to the semiconductor device 100 of Figures 4A to 4E. For detailed descriptions of overlapping components, please refer to Figures 4A to 4E.

[0264] As shown in Figures 35 to 37, semiconductor devices 200, 210, and 220 may comprise a first region R1 and a second region R2. The second conductive line WL of the first region R1 may be connected to pads WP1 to WP4, respectively. The second conductive line WL may have a concave edge portion WE. The pads WP1 to WP4 may have an inner edge PE. The inner edge PE of pads WP1 to WP4 may be convex in shape. The inner edge PE of pads WP1 to WP4 may be located in the inner space of the edge portion WE of the second conductive line WL. The inner edge PE of pads WP1 to WP4 and the edge portion WE of the second conductive line WL may be electrically connected. The inner edge PE of pads WP1 to WP4 and the edge portion WE of the second conductive line WL may be in contact with the first spacer SP1.

[0265] The second region R2 may comprise an alternating stack of pads WP1-WP4 and inter-pad insulating layer PL, and an array of contact plugs CT1-CT4 located within the alternating stack, spaced apart from each other laterally along the first horizontal direction (i.e., the third direction D3), and having different heights from each other. The top surfaces of the contact plugs CT1-CT4 are located on the same horizontal plane, and the bottom portion of each contact plug CT1-CT4 can be adjoined to the individual pads WP1-WP4.

[0266] The first contact plug CT1 can be electrically connected to the first pad WP1 of the first level L1, and further, it can be electrically connected to the second conductive line WL of the first level L1 via the first pad WP1. The second contact plug CT2 can be electrically connected to the second pad WP2 of the second level L2, and further, it can be electrically connected to the second conductive line WL of the second level L2 via the second pad WP2. The third contact plug CT3 can be electrically connected to the third pad WP3 of the third level L3, and further, it can be electrically connected to the second conductive line WL of the third level L3 via the third pad WP3. The fourth contact plug CT4 can be electrically connected to the fourth pad WP4 of the fourth level L4, and further, it can be electrically connected to the second conductive line WL of the fourth level L4 via the fourth pad WP4.

[0267] A first contact spacer CTS1 may be positioned on the side wall of a first contact plug CT1, and a second contact spacer CTS2 may be positioned on the side wall of a second contact plug CT2. A third contact spacer CTS3 may be positioned on the side wall of a third contact plug CT3, and a fourth contact spacer CTS4 may be positioned on the side wall of a fourth contact plug CT4. The vertical height of the fourth contact plug CT4 may be greater than the vertical height of the third contact plug CT3, and the vertical height of the third contact plug CT3 may be greater than the vertical height of the second contact plug CT2. The vertical height of the second contact plug CT2 may be greater than the vertical height of the first contact plug CT1. Here, vertical height may refer to the height along a first direction D1.

[0268] The fourth contact plug CT4 and the fourth contact spacer CTS4 can penetrate the pads WP1, WP2, and WP3 of the first level L1, the second level L2, and the third level L3. The fourth contact plug CT4 can be electrically isolated from the pads WP1, WP2, and WP3 of the first level L1, the second level L2, and the third level L3 by the fourth contact spacer CTS4.

[0269] The third contact plug CT3 and the third contact spacer CTS3 can penetrate the pads WP1 and WP2 at the first level L1 and the second level L2. The third contact plug CT3 can be electrically isolated from the pads WP1 and WP2 at the first level L1 and the second level L2 by the third contact spacer CTS3.

[0270] The second contact plug CT2 and the second contact spacer CTS2 can penetrate the first level L1 pad WP1. The second contact plug CT2 can be electrically isolated from the first level L1 pad WP1 by the second contact spacer CTS2.

[0271] The first pad WP1 can surround the sides of the second to fourth contact plugs CT2, CT3, and CT4. The second pad WP2 can surround the sides of the third and fourth contact plugs CT3 and CT4. The third pad WP3 can surround the side of the fourth contact plug CT4.

[0272] The first pad WP1 can directly contact the bottom surface of the first contact plug CT1. The second pad WP2 can directly contact the bottom surface of the second contact plug CT2. The third pad WP3 can directly contact the bottom surface of the third contact plug CT3. The fourth pad WP4 can directly contact the bottom surface of the fourth contact plug CT4.

[0273] As shown in Figure 35, the contact spacers CTS1 to CTS4 can contain low dielectric constant materials such as SiCOH and SiOF.

[0274] Contact liners CTLs can be formed on the sidewalls of each contact spacer CTS1 to CTS4. The contact liners CTLs and contact spacers CTS1 to CTS4 can be made of different materials. The contact liners CTLs can include oxides, nitrides, or combinations thereof. The contact liners CTLs can enhance the interfacial adhesion between the contact spacers CTS1 to CTS4 and the interpad insulating layer PIL. The contact liners CTLs can also play a role in reducing silicon loss.

[0275] The inter-pad insulating layer (PIL) can contain low dielectric constant materials such as SiCOH and Siof.

[0276] As shown in Figure 36, the contact spacers CTS1 to CTS4 may contain low dielectric constant materials such as SiCOH and SiOF. Contact liners CTLs may be formed on the side walls of each contact spacer CTS1 to CTS4. The contact liners CTLs may contain oxides, nitrides, or combinations thereof.

[0277] An inter-pad liner ILL can be formed between the inter-pad insulating layer PIL and pads WP1-WP4. The inter-pad liner ILL can cover the outer surface of the inter-pad insulating layer PIL. The inter-pad liner ILL can be in direct contact with pads WP1-WP4. The inter-pad liner ILL and the inter-pad insulating layer PIL can be made of different materials. The inter-pad insulating layer PIL can be a low dielectric constant material, and the inter-pad liner ILL can have a higher dielectric constant than the inter-pad insulating layer PIL. The inter-pad liner ILL can include oxides, nitrides, or combinations thereof. The inter-pad liner ILL can enhance the interfacial adhesion between the pad-side sheet and the inter-pad insulating layer PIL while forming the inter-pad insulating layer PIL.

[0278] The inter-pad insulating layer (PIL) can contain low dielectric constant materials such as SiCOH and Siof.

[0279] As shown in Figure 37, the contact spacers CTS1 to CTS4 may contain low dielectric constant materials such as SiCOH and Siof. The inter-pad insulating layer PIL may also contain low dielectric constant materials such as SiCOH and Siof. An inter-pad liner ILL may be formed between the inter-pad insulating layer PIL and the pads WP1 to WP4. The inter-pad liner ILL may contain oxides, nitrides, or a combination thereof.

[0280] The semiconductor device 200 in Figure 35 may not have an interpad liner ILL. The semiconductor device 220 in Figure 37 may not have a contact liner CTL. The semiconductor device 210 in Figure 36 may have both an interpad liner ILL and a contact liner CTL.

[0281] The semiconductor device 100 shown in Figures 4A to 4E may include a low dielectric constant material in the interpad insulating layer PIL and contact spacers CTS1 to CTS4, and may not include the interpad liner ILL and contact liner CTL.

[0282] The semiconductor devices 200 and 210 in Figures 35 and 36 have contact spacers CTS1 to CTS4 containing a low dielectric constant material, which reduces the parasitic capacitance between the contact plugs CT2 to CT4 and the surrounding pads WP1 to WP3.

[0283] The semiconductor devices 200, 210, and 220 shown in Figures 35 to 37 contain a low dielectric constant material in the interpad insulating layer PIL, which has a dielectric constant of 4 or less, for example, a dielectric constant of 2.0 to 3.5. This reduces the parasitic capacitance between pads WP1 to WP4, thereby increasing the operating speed of the semiconductor devices 200, 210, and 220 and reducing power consumption.

[0284] The semiconductor devices 200 and 210 in Figures 35 and 36 are equipped with contact liners CTL, which can strengthen the interfacial adhesion between the contact spacers CTS1 to CTS4 and the interpad insulating layer PIL.

[0285] The semiconductor devices 210 and 220 in Figures 36 and 37 are equipped with inter-pad liners ILL, which allows for strengthening the interfacial adhesion between the pad-side sheet and the inter-pad insulating layer PIL during the formation of the inter-pad insulating layer PIL.

[0286] In the semiconductor devices 200, 210, and 220 shown in Figures 35 to 37, the pads WP1 to WP4 in the second region R2 may have a stairless structure. By forming the pads WP1 to WP4 with a stairless structure, the occupied area (or volume) of the pads WP1 to WP4 in the second region R2 can be reduced.

[0287] Figure 38 is a schematic cross-sectional view of a semiconductor device according to another embodiment. The semiconductor device 230 in Figure 36 can be similar to the semiconductor device 100 in Figures 4A to 4E. For a detailed description of the overlapping components, please refer to Figures 4A to 4E.

[0288] As shown in Figure 38, the semiconductor device 230 may include a first vertical conductive line BLA and a second vertical conductive line BLB, and the bottoms of the first vertical conductive line BLA and the second vertical conductive line BLB may be separated from each other (see reference numeral BLT in the drawing).

[0289] Figures 39A and 39B are schematic cross-sectional views of a semiconductor device according to another embodiment. As shown in Figure 39A, the semiconductor device 300 may comprise a memory cell array MCA, a peripheral circuit section PERI, and a bonding interface BS. The bonding interface BS may be located between the memory cell array MCA and the peripheral circuit section PERI. The semiconductor device 300 may have the memory cell array MCA positioned at a higher level than the peripheral circuit section PERI. The semiconductor device 300 may also be referred to as a PUC (Peri Under Cell array) structure. The memory cell array MCA may comprise a backgrounded substrate and an array of memory cells. For example, as shown in Figure 34B, after forming the data storage element CAP, the substrate 11 may be flipped over via a wafer flip, and then the substrate 11 may be partially background.

[0290] As shown in Figure 39B, the semiconductor device 301 may comprise a memory cell array MCA, a peripheral circuit section PERI, and a bonding interface BS. The bonding interface BS may be located between the memory cell array MCA and the peripheral circuit section PERI. The semiconductor device 301 may have the memory cell array MCA positioned at a lower level than the peripheral circuit section PERI. The semiconductor device 301 may also be referred to as a CUP (Cell array Under Peri) structure. The step of forming the peripheral circuit section PERI may include the steps of forming a plurality of control circuits on a peripheral circuit board and forming multilayer level wiring on the control circuits.

[0291] In Figures 39A and 39B, the bonding interface BS may include pad bonding, hybrid bonding, oxide-to-oxide bonding, metal-to-metal bonding, or a combination thereof. Hybrid bonding may refer to a combination of pad bonding and oxide-to-oxide bonding. A pad bonding method may include the steps of forming cell bonding pads for a memory cell array, forming peripheral circuit bonding pads for peripheral circuit sections, performing a wafer flip so that the cell bonding pads and peripheral circuit bonding pads face each other, and performing wafer bonding.

[0292] The semiconductor device 300 in Figure 39A can perform a wafer flip on a substrate on which a memory cell array is formed so that the cell bonding pad and peripheral circuit bonding pad face each other, after the cell bonding pad and peripheral circuit bonding pad have been formed respectively. The semiconductor device 301 in Figure 39B can perform a wafer flip on a substrate on which a peripheral circuit portion has been formed so that the cell bonding pad and peripheral circuit bonding pad face each other, after the cell bonding pad and peripheral circuit bonding pad have been formed respectively.

[0293] Figures 40A and 40B illustrate a stack assembly according to another embodiment.

[0294] As shown in Figure 40A, the stack assembly 400 may comprise an assembly of semiconductor dies. For example, the stack assembly 400 may comprise a first semiconductor die BSD and a plurality of second semiconductor dies 401. The first semiconductor die BSD may comprise a logic circuit. Each of the second semiconductor dies 401 may comprise a memory cell array according to the embodiment described above.

[0295] Each of the second semiconductor dies 401 may have a structure in which a memory cell array stack and a peripheral circuit section are stacked, for example, semiconductor device 300 in Figure 39A or semiconductor device 301 in Figure 39B. The logic circuit of the first semiconductor die BSD and the peripheral circuit section of the second semiconductor die 401 may be different from each other. The second semiconductor die 401 may be chip-level or wafer-level.

[0296] The second semiconductor die 401 can be electrically interconnected via multiple through-silicon vias (TSVs) and bonding interfaces (CBS). The first semiconductor die BSD and the lowest-level second semiconductor die 401 can be electrically interconnected via bonding interfaces (CBS). The second semiconductor die 401 may be referred to as a core die, semiconductor chip, or memory chip.

[0297] Bonding interfaces (CBS) can include micro-bump, pad bonding, hybrid bonding, oxide-to-oxide bonding, metal-to-metal bonding, or a combination thereof.

[0298] As shown in Figure 40B, the stack assembly 500 may comprise an assembly of semiconductor dies. For example, the stack assembly 500 may comprise a first semiconductor die BSD, a plurality of second semiconductor dies 501, and a plurality of third semiconductor dies 502. The first semiconductor die BSD may comprise a logic circuit. Each of the second semiconductor die 501 and the third semiconductor die 502 may comprise a memory cell array according to the embodiment described above. The second semiconductor die 501 and the third semiconductor die 502 may have different structures from each other.

[0299] Each of the second semiconductor dies 501 may include a semiconductor device 300 as shown in Figure 39A, in which a memory cell array is stacked on top of a peripheral circuit section, and each of the third semiconductor dies 502 may include a semiconductor device 301 as shown in Figure 39B, in which a peripheral circuit section is stacked on top of a memory cell array.

[0300] In other embodiments, each of the second semiconductor dies 501 may include a semiconductor device 301 as shown in Figure 39B, in which a peripheral circuit section is stacked on top of the memory cell array, and each of the third semiconductor dies 502 may include a semiconductor device 300 as shown in Figure 39A, in which a memory cell array is stacked on top of the peripheral circuit section.

[0301] The logic circuit of the first semiconductor die BSD and the peripheral circuit sections of the second and third semiconductor dies 501 and 502 can be different from each other. The second and third semiconductor dies 501 and 502 can be chip-level or wafer-level.

[0302] The second and third semiconductor dies 501 and 502 can be electrically interconnected via multiple through-silicon vias (TSVs) and bonding interfaces (CBS). The first semiconductor die (BSD) and the lowest-level second semiconductor die 501 can be electrically interconnected via bonding interfaces (CBS). The second and third semiconductor dies 501 and 502 may be referred to as core dies, semiconductor chips, or memory chips.

[0303] Bonding interfaces (CBS) can include micro-bump, pad bonding, hybrid bonding, oxide-to-oxide bonding, metal-to-metal bonding, or a combination thereof.

[0304] The stack assemblies 400 and 500 shown in Figures 40A and 40B can be high-bandwidth memories.

[0305] The present invention described above is not limited by the embodiments described above and the accompanying drawings, and it will be apparent to those with ordinary skill in the art to which the present invention pertains that various substitutions, modifications, and changes are possible without departing from the technical spirit of the present invention. [Explanation of Symbols]

[0306] BL First conductive line WL Second conductive line HL Nanosheet GD Nanosheet Insulating Layer CH Channel SR 1st Doped Area DR Second Doped Area TR switching element CAP data storage element SN First electrode DE dielectric layer PN Second electrode PL Common Plate MCA Memory Cell Array MC memory cell BLC First Contact Node SNC's second contact node IL1 First inter-cell insulating layer IL2 Second inter-cell insulating layer IL3 Third inter-cell insulating layer PIL pad inter-pad insulating layer CTS1~CTS4 Contact Spacer WP Pad CT1~CT4 Contact Plugs

Claims

1. Vertical and horizontal arrangement of nanosheets, A horizontally oriented conductive line surrounds the horizontal arrangement of the aforementioned nanosheets, A pad connected to the edge of the aforementioned horizontal conductive line, An inter-pad insulating layer located between the aforementioned pads, Each of the aforementioned pads is connected to a contact plug, A contact spacer comprising a first low dielectric constant material formed on each side wall of the contact plug, A semiconductor device equipped with a semiconductor device.

2. The first low dielectric constant material is silicon dioxide (SiO₂ ２ The semiconductor device according to claim 1, having a dielectric constant lower than ).

3. The semiconductor device according to claim 1, wherein the first low dielectric constant material has a dielectric constant lower than that of oxide-bonded silicon carbide (SiCO).

4. The semiconductor device according to claim 1, wherein the first low dielectric constant material includes SiCOH, SiOF, or a combination thereof.

5. Each of the aforementioned pad-to-pad insulating layers is The semiconductor device according to claim 1, comprising the second low dielectric constant material.

6. The semiconductor device according to claim 5, wherein the second low dielectric constant material has a dielectric constant lower than that of oxide-bonded silicon carbide (SiCO).

7. The semiconductor device according to claim 6, wherein the second low dielectric constant material comprises SiCOH, SiOF, or a combination thereof.

8. The semiconductor device according to claim 1, wherein the horizontal lengths of the pads are the same.

9. The edge portion of the horizontal conductive line includes a concave shape, and the pad has a convex-shaped edge. The semiconductor device according to claim 1, wherein the edge of the pad is in direct contact with the inner surface of the edge portion of the horizontal conductive line.

10. A vertical conductive line connected to the vertical arrangement of the nanosheets, Data storage elements connected to the vertically and horizontally arranged nanosheets, respectively, The semiconductor device according to claim 1, further comprising

11. A first contact node between the nanosheet and the vertical conductive line, A second contact node between the nanosheet and the data storage element, The semiconductor device according to claim 10, further comprising

12. The semiconductor device according to claim 1, further comprising a contact liner formed on the side wall of the contact spacer.

13. The semiconductor device according to claim 1, further comprising an inter-pad liner formed between the inter-pad insulating layer and the pad.

14. A contact liner formed on the side wall of the contact spacer, The pad-to-pad liner formed between the pad-to-pad insulating layer and the pad, Furthermore, The semiconductor device according to claim 1, wherein the contact liner and the inter-pad liner include an insulating material.

15. The semiconductor device according to claim 1, wherein the contact plugs have different vertical heights.

16. Vertical and horizontal arrangement of nanosheets, A horizontally oriented conductive line surrounds the horizontal arrangement of the aforementioned nanosheets, A non-stairless structure comprising a horizontally oriented pad connected to the edge of the horizontal conductive line and a low dielectric constant inter-pad insulating layer between the horizontally oriented pad, Each of the horizontally oriented pads is connected to a vertically oriented contact pillar, A low dielectric constant spacer surrounds the outer wall of each of the contact pillars, A semiconductor device equipped with a semiconductor device.

17. A contact liner formed on the side wall of the low dielectric constant spacer, The pad liner formed between the low dielectric constant pad-to-pad insulating layer and the pad, The semiconductor device according to claim 16, further comprising

18. The insulating layer between the low dielectric constant spacer and the low dielectric constant pad is made of oxide-bonded silicon carbide (SiCO) and silicon oxide (SiO ２ The semiconductor device according to claim 16, having a dielectric constant lower than ).

19. The semiconductor device according to claim 16, wherein the low dielectric constant spacer and the insulating layer between the low dielectric constant pads include SiCOH, SiOF, or a combination thereof.

20. A vertical conductive line connected to the vertical arrangement of the nanosheets, Data storage elements connected to the vertically and horizontally arranged nanosheets, respectively, A first contact node between the nanosheet and the vertical conductive line, The semiconductor device according to claim 16, further comprising a second contact node between the nanosheet and the data storage element.

21. The steps include forming an alternating stack of a sacrificial sheet and an inter-pad insulating layer on the upper part of the substrate, The steps include forming contact holes in the alternating stack in which the height gradually decreases along the stacking direction between the sacrificial sheet and the pad-inter-insulating layer, The steps include forming a low dielectric constant spacer on the side wall of the contact hole, The steps include forming sacrificial plugs on the low dielectric constant spacer to fill each of the contact holes, The steps include removing the sacrificial sheet of the alternating stack to form a pad-shaped opening, The steps include forming a pad that fills the pad-shaped opening, The steps include removing the sacrificial plug to form a plug opening, The steps include cutting a portion of the low dielectric constant spacer through the plug opening to expose each of the pads, The steps include forming contact plugs that are connected to each of the pads while satisfying each of the plug openings, A method for manufacturing a semiconductor device containing [a specific component].

22. Prior to the step of forming the low dielectric constant spacer, The method for manufacturing a semiconductor device according to claim 21, further comprising the step of forming a contact liner on the side wall of the contact hole.

23. Prior to the step of forming the low dielectric constant spacer, The method for manufacturing a semiconductor device according to claim 21, further comprising the step of forming a contact liner on the side wall of the contact hole.

24. The method for manufacturing a semiconductor device according to claim 21, wherein the low dielectric constant spacer and the inter-pad insulating layer include SiCOH, SiOF, or a combination thereof.

25. The method for manufacturing a semiconductor device according to claim 21, wherein the contact holes have different depths and are formed horizontally apart from each other.

26. The step of forming the contact hole is, A method for manufacturing a semiconductor device according to claim 21, comprising the step of etching the alternating stack in a non-stepped structure via a plurality of masks and a plurality of etching steps.

27. Prior to the step of forming the alternating stack, The steps include forming nanosheet target layers stacked vertically and spaced apart from each other on the upper part of the substrate, The steps include trimming a first portion of the nanosheet target layer to form a flat plate-type sheet, The steps include forming horizontally oriented horizontal conductive lines while surrounding the flat plate-type sheet, The steps include forming a vertical conductive line connected to the flat plate-type sheet, A method for manufacturing a semiconductor device according to claim 21, further comprising:

28. After the step of forming the pad, The steps include horizontally recessing a second portion of the nanosheet target layer to form a fan-shaped sheet, The steps include selectively growing contact nodes on each side surface of the fan-shaped sheet, The steps include forming a data storage element connected to each of the aforementioned contact nodes, A method for manufacturing a semiconductor device according to claim 27, further comprising:

29. The step of forming an alternating stack of a sacrificial sheet and an inter-pad insulating layer on the upper part of the substrate is, The steps include forming the sacrificial sheet and the interpad recess between the sacrificial sheets on the upper part of the substrate, To form the inter-pad insulating layer, the steps include forming a low dielectric constant insulating layer that satisfies the inter-pad recess, A method for manufacturing a semiconductor device according to claim 21, including the method described above.

30. Prior to the step of forming the low dielectric constant insulating layer, The method for manufacturing a semiconductor device according to claim 29, further comprising the step of conformally forming an inter-pad liner on the inter-pad recess.

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