Multilayer electronic components

Abstract

This provides electronic components with excellent crack resistance and moisture resistance reliability, even with small stacking dimensions. [Solution] In a stacked electronic component, the central region of the capacitance forming section includes internal electrodes 121 and 122 arranged alternately with the dielectric layer 111, and the internal electrodes include gaps 121b and 122b between a plurality of conductive parts 121a or between a plurality of conductive parts 122a, respectively, and when the average value of the internal electrode connectivity is ec, the average thickness of the internal electrodes is te, the average thickness of the dielectric layer is td, the size in the stacking direction of the electronic component is T, and the size in the width direction is W, the values ​​of te / (ec×td)≦0.800 and T / W≦0.714 are satisfied.

Description

[Technical Field]

[0001] This disclosure relates to a stacked electronic component. [Background technology]

[0002] Multi-Layered Ceramic Capacitors (MLCCs), a type of multilayer electronic component, are chip-type capacitors that are mounted on printed circuit boards of various electronic products such as LCDs (Liquid Crystal Displays) and PDPs (Plasma Display Panels), computers, smartphones, and mobile phones, and play a role in charging or discharging electricity. Due to their advantages of being small, yet guaranteeing high capacitance and being easy to mount, MLCCs are used as components in a wide range of electronic devices.

[0003] Generally, MLCCs have a similar width (W size) and thickness (T size). However, with the recent development of technologies such as 5G and foldable devices, there is a demand for smaller and thinner MLCCs, and development is underway for low-profile MLCCs, which have a special shape where the thickness is smaller than the width.

[0004] However, we found that low-profile MLCCs are even more susceptible to cracks (hereinafter referred to as shrinkage cracks) caused by the difference in firing shrinkage rates between the capacitance-forming section, where the dielectric layer and internal electrodes are stacked, and the cover / margin section, where the internal electrodes are not stacked, compared to conventional MLCCs. When shrinkage cracks occur, external moisture can penetrate into the interior of the low-profile MLCC, potentially reducing its moisture resistance reliability. [Overview of the Initiative] [Problems that the invention aims to solve]

[0005] One of the various purposes of this disclosure is to provide a stacked electronic component that is highly reliable despite having a small T size.

[0006] However, the purpose of this disclosure is not limited to what is described above, and this will become clearer in the course of describing specific embodiments of this disclosure. [Means for solving the problem]

[0007] A stacked electronic component according to one embodiment of the present disclosure includes a dielectric layer and internal electrodes arranged alternately with the dielectric layer in a first direction, and includes a body comprising first and second faces facing each other in the first direction, third and fourth faces connected to the first and second faces and facing each other in a second direction, fifth and sixth faces connected to the first, second, third and fourth faces and facing each other in a third direction, and external electrodes arranged on the third and fourth faces, wherein the internal electrodes include a plurality of conductive parts and cuts arranged between adjacent conductive parts, and when the average value of electrode connectivity, which is the ratio of the sum of the lengths of the plurality of conductive parts to the total length of the internal electrodes, is ec, the average thickness of the dielectric layer is td, the average thickness of the internal electrodes is te, the size of the stacked electronic component in the first direction is T, and the size of the stacked electronic component in the third direction is W, the following conditions can be met: te / (ec×td)≦0.800 and T / W≦0.714. [Effects of the Invention]

[0008] One of the various benefits of this disclosure is the ability to provide a highly reliable stacked electronic component with a small T size. [Brief explanation of the drawing]

[0009] [Figure 1] This is a schematic perspective view of a stacked electronic component according to one embodiment of the present disclosure. [Figure 2] Figure 1 is an exploded perspective view schematically showing the main body and side margins. [Figure 3] This is a schematic cross-sectional view showing a section along the line I-I' in Figure 1. [Figure 4] It is a cross-sectional view schematically showing a cross-section along the line II-II' in FIG. 1. [Figure 5] It is an enlarged view schematically showing the central region of the capacitance forming portion. [Figure 6] It is an enlarged view schematically showing the K1 region in FIG. 5. [Figure 7] It is an image obtained by photographing the central region of the capacitance forming portion of a stacked electronic component according to an embodiment of the present disclosure with a scanning electron microscope (SEM).

Mode for Carrying Out the Invention

[0010] Hereinafter, embodiments of the present disclosure will be described with reference to specific embodiments and the accompanying drawings. However, the embodiments of the present disclosure can be modified into several other forms, and the scope of the present disclosure is not limited to the embodiments described below. Also, the embodiments of the present disclosure are provided to more fully explain the present disclosure to ordinary technicians. Therefore, the shape and size of elements in the drawings may be enlarged, reduced (or emphasized or simplified) for clearer explanation, and elements denoted by the same reference numerals in the drawings are the same elements.

[0011] In addition, parts not related to the explanation are omitted in the drawings for clearly explaining the present disclosure, and the size and thickness of each illustrated configuration are arbitrarily shown for convenience of explanation, so the present disclosure is not necessarily limited by the illustration. Also, components having the same function within the scope of the same idea are explained using the same reference numerals. Further, throughout the specification, when a certain part "includes" a certain component, it means that other components can be further included, rather than excluding other components, unless there is a particularly contrary description.

[0012] In the drawings, the first direction D1 can be defined as the thickness direction, the second direction D2 as the length direction, and the third direction as the width D3 direction.

[0013] Stacked electronic component Figure 1 is a schematic perspective view of a stacked electronic component according to one embodiment of the present disclosure; Figure 2 is a schematic exploded perspective view of the main body and side margin portion of Figure 1; Figure 3 is a schematic cross-sectional view of a section along line I-I' of Figure 1; Figure 4 is a schematic cross-sectional view of a section along line II-II' of Figure 1; Figure 5 is a schematic enlarged view of the central region of the capacitance forming portion; Figure 6 is a schematic enlarged view of the K1 region of Figure 5; and Figure 7 is a scanning electron microscope (SEM) image of the central region of the capacitance forming portion of a stacked electronic component according to one embodiment of the present disclosure.

[0014] Hereinafter, with reference to Figures 1 to 7, a multilayer electronic component 100 according to one embodiment of this disclosure will be described in detail. While a multilayer ceramic capacitor will be described as an example of a multilayer electronic component, this disclosure is not limited to this and can be applied to a variety of multilayer electronic components, such as inductors, piezoelectric elements, varistors, or thermistors.

[0015] A stacked electronic component 100 according to one embodiment of the present disclosure may include a main body 110 and external electrodes 131 and 132.

[0016] There are no particular restrictions on the specific shape of the main body 110, but as shown in the figure, the main body 110 can be hexahedral or a similar shape. Due to the shrinkage of the ceramic powder contained in the main body 110 during the firing process and the polishing process on the corners of the main body 110, the main body 110 may not be a perfectly straight hexahedron, but it can be substantially hexahedral.

[0017] The main body 110 may have a first surface 1 and a second surface 2 facing each other in a first direction, a third surface 3 and a fourth surface 4 connected to the first surface 1 and the second surface 2 and facing each other in a second direction, a fifth surface 5 and a sixth surface 6 connected to the first surface 1, the second surface 2, the third surface 3 and the fourth surface 4 and facing each other in a third direction.

[0018] The main body 110 can include a dielectric layer 111 and internal electrodes 121 and 122 that are alternately arranged with the dielectric layer 111 in the first direction. The plurality of dielectric layers 111 forming the main body 110 are in a fired state, and the boundaries between adjacent dielectric layers 111 can be integrated so as to be difficult to confirm without using a scanning electron microscope (SEM).

[0019] The dielectric layer 111 can include, for example, a perovskite-type compound represented by ABO3 as a main component. The perovskite-type compound represented by ABO3 is, for example, BaTiO3, (Ba 1-x Ca x )TiO3 (0 < x < 1), Ba(Ti 1-y Ca y )O3 (0 < y < 1), (Ba 1-x Ca x )(Ti 1-y Zr y )O3 (0 < x < 1, 0 < y < 1), Ba(Ti 1-y Zr y )O3 (0 < y < 1), CaZrO3, and (Ca 1-x Sr x )(Zr 1-y Ti y )O3 (0 < x ≤ 0.5, 0 < y ≤ 0.5), and can include one or more of them.

[0020] The internal electrodes 121 and 122 can include a first internal electrode 121 and a second internal electrode 122 that are alternately arranged in the first direction with the dielectric layer 111 interposed therebetween. The first internal electrode 121 and the second internal electrode 122 can be electrically separated from each other by the dielectric layer 111 disposed therebetween.

[0021] The first internal electrode 121 may extend to the third surface 3, the fifth surface 5, and the sixth surface 6 and may be arranged spaced apart from the fourth surface 4. The second internal electrode 122 may extend to the fourth surface 4, the fifth surface 5, and the sixth surface 6 and may be arranged spaced apart from the third surface 3.

[0022] The conductive metals contained in the internal electrodes 121 and 122 may be one or more of Ni, Cu, Pd, Ag, Au, Pt, Sn, W, Ti, and alloys thereof, and may include, for example, Ni, but is not limited to these.

[0023] The internal electrodes 121 and 122 may include a plurality of conductive portions 121a and 122a and cut portions 121b and 122b arranged between adjacent conductive portions 121a and 122a. That is, the first internal electrode 121 may include a plurality of first conductive portions 121a and a first cut portion 121b arranged between adjacent first conductive portions 121a, and the second internal electrode 122 may include a plurality of second conductive portions 122a and a second cut portion 122b arranged between adjacent second conductive portions 122a.

[0024] The conductive portions 121a and 122a can represent regions where conductive metal is present, while the cut portions 121b and 122b can represent regions where conductive metal is not present. Due to the difference in sintering shrinkage start temperatures between the dielectric layer 111 and the internal electrodes 121 and 122, the shrinkage behavior between the dielectric layer 111 and the internal electrodes 121 and 122 may not coincide. In this case, the conductive metal of the internal electrodes 121 and 122 may locally aggregate to form voids, and these voids can form cut portions 121b and 122b through firing.

[0025] The main body 110 may include a capacitance forming section Ac disposed inside the main body 110 and including a dielectric layer 111 and internal electrodes 121, 122 to form a capacitance, and a first cover section 112 and a second cover section 113 disposed on both sides of the capacitance forming section Ac facing a first direction.

[0026] The stacked electronic component 100 may include side margin portions 141 and 142 located on the fifth face 5 and the sixth face 6. The stacked electronic component 100 may include a first side margin portion 141 located on the fifth face 5 and a second side margin portion 142 located on the sixth face 6. The side margin portions 141 and 142 may be positioned to cover the ends of internal electrodes 121 and 122 extending to the fifth face 5 and the sixth face 6.

[0027] The cover portions 112, 113 and the side margin portions 141, 142 may mainly contain a perovskite-type compound represented by ABO3. The cover portions 112, 113 and the side margin portions 141, 142 may have a different dielectric composition from the dielectric layer 111, but this disclosure is not limited thereto.

[0028] External electrodes 131 and 132 can be arranged on the third surface 3 and the fourth surface 4. The external electrodes 131 and 132 may include a first external electrode 131 arranged on the third surface 3 and connected to a first internal electrode 121, extending over parts of the first surface 1, the second surface 2, the fifth surface 5, and the sixth surface 6, and a second external electrode 132 arranged on the fourth surface 4 and connected to a second internal electrode 122, extending over parts of the first surface 1, the second surface 2, the fifth surface 5, and the sixth surface 6.

[0029] The type and form of the external electrodes 131 and 132 are not particularly limited and can have a multilayer structure. For example, the external electrodes 131 and 132 may include a base electrode layer that contacts the internal electrodes 121 and 122 and a plating layer disposed on the base electrode layer.

[0030] The above-mentioned base electrode layer may include a fired electrode layer containing metal and glass. The metal contained in the fired electrode layer may include, for example, Cu, Ni, Pd, Pt, Au, Ag, Pb and / or alloys containing these. The glass contained in the fired electrode layer may include, for example, one or more oxides of Ba, Ca, Zn, Al, B and Si.

[0031] The underlying electrode layer can be composed of only the fired electrode layer, but the present disclosure is not limited thereto. The underlying electrode layer can include a fired electrode layer containing metal and glass, and a resin electrode layer disposed on the fired electrode layer and containing metal particles and resin.

[0032] The metal particles contained in the resin electrode layer can include one or more of spherical particles and flaky particles. The metal particles contained in the resin electrode layer can include, for example, Cu, Ni, Pd, Pt, Au, Ag, Pb, Sn, and / or an alloy containing these. The resin contained in the resin electrode layer can include, for example, one or more of epoxy resin, acrylic resin, and ethyl cellulose.

[0033] The plating layer can include, for example, Ni, Sn, Pd, and / or an alloy containing these, and can also be formed of multiple layers. The plating layer can be, for example, a Ni plating layer or a Sn plating layer, or can be in a form where a Ni plating layer and a Sn plating layer are sequentially formed. The plating layer can include multiple Ni plating layers and / or multiple Sn plating layers.

[0034] In the drawings, a structure in which the multilayer electronic component 100 has two external electrodes 131 and 132 is described, but it is not limited thereto. The number, shape, etc. of the external electrodes 131 and 132 can vary according to the form of the internal electrodes 121 and 122 and other purposes.

[0035] According to an embodiment of the present disclosure, when the size of the multilayer electronic component 100 in the first direction is T and the size of the multilayer electronic component 100 in the third direction is W, T < W can be satisfied. More preferably, the multilayer electronic component 100 can satisfy T / W ≤ 0.714. Thereby, the size T of the multilayer electronic component 100 in the first direction can be reduced to miniaturize the multilayer electronic component 100. The lower limit of T / W is not particularly limited and can vary according to the specifications of the multilayer electronic component 100 required by the user. In one embodiment, considering the capacitance, etc. of the multilayer electronic component 100, the T / W can be 0.400 or more.

[0036] On the other hand, when the ratio of T to W (T / W) is reduced to 0.714 or less in order to miniaturize the multilayer electronic component 100, it was confirmed that the difference in firing shrinkage rate between the capacitance forming portion Ac and the cover portions 112, 113 and the side margin portions 141, 142 becomes large, resulting in the occurrence of a large number of shrinkage cracks. Therefore, when designing the multilayer electronic component 100 to satisfy T / W ≤ 0.714 in order to miniaturize the multilayer electronic component 100, further design is required to prevent shrinkage cracks.

[0037] Therefore, according to one embodiment of the present disclosure, when the average value of electrode connectivity, which is the ratio of the sum of the lengths of the multiple conductive parts 121a, 122a to the total length of the internal electrodes 121, 122, is denoted as ec, the average thickness of the dielectric layer 111 is denoted as td, and the average thickness of the internal electrodes 121, 122 is denoted as te, then the condition te / (ec × td) ≤ 0.800 can be satisfied. When te / (ec × td) ≤ 0.800 is satisfied, the difference in firing shrinkage rate between the capacitance forming part Ac and the cover parts 112, 113 and the side margin parts 114, 115 can be reduced, thereby suppressing the occurrence of shrinkage cracks.

[0038] There is no particular lower limit to te / (ec×td). This is because as te decreases, ec tends to decrease along with it. However, if te becomes smaller than a certain level relative to td, ec may decrease rapidly. In this case as well, although the occurrence of shrinkage cracks can be suppressed, the capacitance of the multilayer electronic component 100 may decrease or the short-circuit failure rate may increase. Therefore, in one embodiment, te / (ec×td) can exceed 0.758.

[0039] As long as te / (ec×td)≦0.800 is satisfied, the ranges of ec, td, and te are not particularly limited and can vary depending on the specifications, electrical characteristics, etc. of the multilayer electronic component 100 required by the user. For example, a multilayer electronic component 100 according to one embodiment can satisfy 0.30mm≦W≦0.75mm and 0.80mm≦L≦1.25mm. Here, L can represent the size of the multilayer electronic component 100 in the second direction. That is, the multilayer electronic component 100 can have a size of 1005 (L: approximately 1.0mm, W: approximately 0.5mm). For example, the multilayer electronic component 100 may satisfy 0.45mm≦W≦0.70mm, 0.85mm≦L≦1.15mm and / or T / W≦0.714, and its capacitance may be 4μF or more and 22μF or less.

[0040] The above ec is not particularly limited, but it can be satisfied with 0.924 ≤ ec by considering the capacitance of the multilayer electronic component 100. The upper limit of the above ec is not particularly limited and may be, for example, less than 1.0.

[0041] The above values ​​of td and te are not particularly limited, but considering the increased capacitance and reliability of the multilayer electronic component 100, the following conditions can be met: 450nm ≤ td ≤ 600nm and / or 370nm ≤ te ≤ 550nm.

[0042] The following describes an example of a method for measuring ec, td, and te, with reference to Figures 4 to 6.

[0043] The above ec can be measured by the following method. First, the cross-sections in the first and third directions of the multilayer electronic component 100 are exposed by polishing up to the center in the second direction. After this, a first image is obtained by magnifying the central region RC in the first direction of the capacitance forming portion Ac with a scanning electron microscope (SEM). As shown in Figure 5, multiple internal electrodes 121 and 122 can be observed in the above first image.

[0044] The electrode connectivity of internal electrodes 121 and 122 can be defined as the ratio (Le1 + Le2 + Le3 + Le4 / Le) of the total length of the multiple conductive parts 121a and 122a to the total length of the internal electrode. If the total number of internal electrodes 121 and 122 present in the first image above is n, then after measuring the electrode connectivity (En) of each of the n internal electrodes 121 and 122, the average value (E1 + E2 + ... En / n) can be defined as the average value ec1 of the electrode connectivity measured in the central region RC of the capacitance forming part Ac.

[0045] Next, a second image is obtained by magnifying the upper region RU adjacent to the first cover portion 112 of the capacitance forming portion Ac using a scanning electron microscope (SEM). After measuring the electrode connectivity of all internal electrodes 121 and 122 present in the second image, the average value can be defined as the average value ec2 of the electrode connectivity measured in the upper region RU.

[0046] Similarly, a third image is obtained by magnifying the lower region RL adjacent to the second cover portion 113 of the capacitance forming portion Ac using a scanning electron microscope (SEM). After measuring the electrode connectivity of all internal electrodes 121 and 122 present in the above third image, the average value can be defined as the average value ec3 of the electrode connectivity measured in the lower region RL.

[0047] The scanning electron microscope (SEM) magnification may be, for example, 50,000x or higher, but this disclosure is not limited thereto. In the first to third images above, ten or more internal electrodes 121, 122 can be observed, respectively.

[0048] The above ec can be defined as the average value between ec1, ec2, and ec3. That is, when ec1 is the average value of electrode connectivity measured in the central region RC in the first direction of the capacitance forming part Ac, ec2 is the average value of electrode connectivity measured in the upper region RU adjacent to the first cover part 112 of the capacitance forming part Ac, and ec3 is the average value of electrode connectivity measured in the lower region RC adjacent to the second cover part 113 of the capacitance forming part Ac, then the above ec can be (ec1 + ec2 + ec3) / 3.

[0049] The above td and te can be measured by the following method.

[0050] By measuring the thickness (te11, te12, te13, te14, te15, ...) of a single internal electrode 121, 122 present in the first image above at multiple points, for example, any five or more points, and then calculating the average value, the average thickness of the internal electrodes 121, 122 located in the central region RC can be measured. The five or more points mentioned above can be specified by multiple conductive parts 121a, 122a.

[0051] If the total number of internal electrodes 121 and 122 present in the first image above is n, then after measuring the average thickness TEn of each of the n internal electrodes 121 and 122, the average value (TE1 + TE2 + ... + TEn / n) can be defined as the average thickness te1 of the internal electrodes 121 and 122 measured in the central region RC.

[0052] Next, after measuring the average thickness of all internal electrodes 121 and 122 present in the second image, the average value can be defined as the average thickness te2 of the internal electrodes 121 and 122 measured in the upper region RU.

[0053] Similarly, after measuring the average thickness of all internal electrodes 121 and 122 present in the third image described above, the average value can be defined as the average thickness te3 of the internal electrodes 121 and 122 measured in the lower region RL.

[0054] The above te can be defined as the average value between te1, te2, and te3. That is, if te1 is the average thickness of internal electrodes 121 and 122 measured in the central region RC, te2 is the average thickness of internal electrodes 121 and 122 measured in the upper region RU, and te3 is the average thickness of internal electrodes 121 and 122 measured in the lower region RL, then the above te can be (te1 + te2 + te3) / 3.

[0055] Similarly, the average thickness of the dielectric layer 111 located in the central region RC can be measured by measuring its thickness (td11, td12, td13, td14, td15, ...) at multiple points, for example, any five or more points, and then calculating the average value. The five or more points can be specified between the first conductive part 121a and the second conductive part 122a, and can be specified on the same line as five or more points for measuring the thickness (te11, te12, te13, te14, te15, ...) of the internal electrodes 121, 122. However, the disclosure is not limited thereto.

[0056] If the total number of dielectric layers 111 present in the first image above is n, then after measuring the average thickness TDn of each of the n dielectric layers 111, the average value (TD1 + TD2 + ... + TDn / n) can be defined as the average thickness td1 of the dielectric layers 111 measured in the central region RC of the capacitance forming section Ac.

[0057] Next, after measuring the average thickness of all dielectric layers 111 present in the second image above, the average value can be defined as the average thickness td2 of the dielectric layers 111 measured in the upper region RU.

[0058] Similarly, after measuring the average thickness of all dielectric layers 111 present in the third image above, the average value can be defined as the average thickness td3 of the dielectric layers 111 measured in the lower region RL.

[0059] The above td can be defined as the average value between td1, td2, and td3. That is, if td1 is the average thickness of the dielectric layer 111 measured in the central region RC, td2 is the average thickness of the dielectric layer 111 measured in the upper region RU, and td3 is the average thickness of the dielectric layer 111 measured in the lower region RL, then the above td can be (td1 + td2 + td3) / 3.

[0060] The above values ​​ec, td, and te may be values ​​measured by automatically analyzing the first to third images using an image analysis program, or they may be values ​​measured by manually analyzing the first to third images.

[0061] The average thickness tc of the cover portions 112 and 113 is not particularly limited. The average thickness tc of the cover portions 112 and 113 may be, for example, 10 μm or more and 40 μm or less. Here, the average thickness tc of the cover portions 112 and 113 refers to the average thickness of the first cover portion 112 and the second cover portion 113, respectively. The average thickness tc of the cover portions 112 and 113 may be the average of the thickness in the first direction measured at five equally spaced points in the cross-section of the multilayer electronic component 100 in the first and third directions.

[0062] The average thickness (wm) of the side margin portions 141 and 142 is not particularly limited. The average thickness (wm) of the side margin portions 141 and 142 may be, for example, 5 μm or more and 30 μm or less. Here, the average thickness wm of the side margin portions 141 and 142 refers to the average thickness of the first side margin portion 141 and the second side margin portion 142, respectively. The average thickness wm of the side margin portions 141 and 142 may be the average value of the thickness in the third direction measured at five equally spaced points in the cross-section of the multilayer electronic component 100 in the first and third directions.

[0063] The following describes an example of a method for forming a stacked electronic component 100. However, the manufacturing method of the stacked electronic component 100 is not limited to this.

[0064] First, prepare the ceramic powder for forming the dielectric layer 111. The ceramic powder may be, for example, BaTiO3, (Ba 1-x Ca x )TiO3(0 <x<1)、Ba(Ti 1-y Ca y )O3(0 <y<1)、(Ba 1-x Ca x )(Ti 1-y Zr y )O3(0 <x<1、0<y<1)、Ba(Ti1-y Zr y )O3 (0 < y < 1), CaZrO3, and (Ca 1-x Sr x )(Zr 1-y Ti y )O3 (0 < x ≤ 0.5, 0 < y ≤ 0.5), and can contain one or more of them. BaTiO3 powder can be synthesized, for example, by reacting a titanium raw material such as titanium dioxide with a barium raw material such as barium carbonate. As the method for synthesizing the ceramic powder, for example, there are a solid-phase method, a sol-gel method, a hydrothermal synthesis method, etc., but the present invention is not limited thereto. Next, after drying and pulverizing the prepared ceramic powder, an organic solvent such as ethanol, a binder such as polyvinyl butyral, and other auxiliary components are mixed to produce a ceramic slurry, and then the ceramic slurry is applied and dried on a carrier film to prepare a sheet for forming a dielectric layer.

[0065] Next, an internal electrode pattern is formed by printing a conductive paste for an internal electrode containing a metal powder, a binder, an organic solvent, etc. with a predetermined thickness on the sheet for forming a dielectric layer using a screen printing method or a gravure printing method.

[0066] After that, after peeling the sheet for forming a dielectric layer with the internal electrode pattern printed thereon from the carrier film, it is laminated and pressure-bonded by a predetermined number of layers to form a ceramic laminate. On the upper and lower parts of the ceramic laminate, cover part forming sheets on which no internal electrode pattern is formed may be laminated by a predetermined number of layers in order to form cover parts 112 and 113 after firing. After that, the ceramic laminate is cut so as to have a predetermined chip size. At this time, the ends of the internal electrode pattern are exposed on both sides facing each other in the third direction of the cut chip.

[0067] Next, the side margin forming sheet is attached to both sides of the cut chip in the third direction, and then fired to form the main body 110 and the side margins 141 and 142. The above firing can be carried out, for example, in a 1.0%H2 / 99.0%N2 to 3.5%H2 / 96.5%N2 (H2O / H2 / N2 atmosphere) at a temperature of 1000°C to 1400°C for 1 to 3 hours.

[0068] On the other hand, ec, td, and te can be controlled by adjusting the particle size of the metal powder contained in the conductive paste for the internal electrodes, the particle size of the ceramic powder contained in the sheet for forming the dielectric layer, the thickness of the internal electrode pattern and the thickness of the sheet for forming the dielectric layer, firing conditions, etc.

[0069] Next, external electrodes 131 and 132 are formed. For example, if the base electrode layer includes a fired electrode layer, the main body 110 to which the side margins 141 and 142 are attached is dipped in a conductive paste for external electrodes containing metal powder, glass frit, binder, and organic solvent, and then the conductive paste for external electrodes is fired at a temperature of 500°C to 900°C to form a fired electrode layer.

[0070] For example, if the base electrode layer includes a resin electrode layer, the main body 110 to which the side margins 141 and 142 are attached can be dipped in a conductive resin composition containing metal powder, resin, binder, and organic solvent, and then cured at a temperature of 250°C to 550°C to form the resin electrode layer.

[0071] Furthermore, an electrolytic plating method and / or an electroless plating method may be used to further form a plating layer on the underlying electrode layer.

[0072] Experimental example The following experimental examples will provide further details of this disclosure. However, these are intended to aid in a concrete understanding of this disclosure and do not limit the scope of this disclosure.

[0073] Using the manufacturing method described above, sample chips of size 1005 (L: approximately 0.80 mm to 1.25 mm, W: approximately 0.30 mm to 0.75 mm) were prepared. The size T in the first direction and the size W in the third direction of the sample chips were measured and recorded in Table 1 below.

[0074] Next, after exposing the cross-sections in the first and third directions by polishing the sample chip to the center in the second direction, the central region in the first direction of the capacitance formation area was magnified with a scanning electron microscope (SEM) at 50,000x magnification to obtain the first image shown in Figure 7. In Figure 7, the relatively bright areas of the internal electrodes are conductive parts, and the relatively dark areas due to voids are breaks. The areas placed between the internal electrodes are dielectric layers.

[0075] The electrode connectivity (sum of the lengths of multiple conductive parts relative to the total length of the internal electrode) of all internal electrodes present in the first image above was measured, and the average value (ec1) was calculated.

[0076] Next, the average thickness of all internal electrodes present in the first image was measured. Specifically, the average thickness of a single internal electrode was determined by measuring its thickness at five arbitrary points and then calculating the average value. The five points were designated as conductive areas. After this, the average value (te1) of all internal electrodes present in the first image was calculated.

[0077] Next, the average thickness of the dielectric layers present in the first image was measured. Specifically, the average thickness of a dielectric layer was determined by measuring its thickness at five arbitrary points and then calculating the average value. The five points were specified between the first conductive part and the second conductive part. After this, the average thickness of all dielectric layers present in the first image was measured, and the average value (td1) was calculated.

[0078] Using a similar method, a second image was obtained by magnifying the upper region adjacent to the first cover portion of the capacitance formation portion with a scanning electron microscope (SEM). Then, the electrode connectivity of all internal electrodes present in the second image was measured and averaged (ec2), the average thickness of all internal electrodes present in the second image was measured and averaged (te2), and the average thickness of all dielectric layers present in the second image was measured and averaged (td2).

[0079] Similarly, a third image was obtained by magnifying the lower region adjacent to the second cover portion of the capacitance formation portion using a scanning electron microscope (SEM). Then, the electrode connectivity of all internal electrodes present in the third image was measured and averaged (ec3), the average thickness of all internal electrodes present in the third image was measured and averaged (te3), and the average thickness of all dielectric layers present in the third image was measured and averaged (td3).

[0080] Finally, the average electrode connectivity (ec) was calculated as (ec1+ec2+ec3) / 3, the average thickness of the internal electrodes (te) as (te1+te2+te3) / 3, and the average thickness of the dielectric layer (td) as (td1+td2+td3) / 3, and these results are shown in Table 1 below.

[0081] [Table 1]

[0082] Based on the values ​​in Table 1, te / (ec×td) and T / W were calculated and recorded in Table 2 below. Subsequently, 300 to 1000 sample chips were prepared for each sample number, and the shrinkage crack defect rate and short defect rate were measured. Finally, the characteristics of each sample number were evaluated as poor (×), good (△), or excellent (○).

[0083] [Table 2]

[0084] For samples 5-8, the T / W ≤ 0.714 condition was met, but te / (ec × td) exceeded 0.800. This confirms the occurrence of a large number of shrinkage cracks.

[0085] For samples 9-10, the T / W ratio exceeded 0.714 and the te / (ec×td) ratio exceeded 0.800. As a result, while shrinkage cracks due to miniaturization did not occur, the short-circuit failure rate increased slightly.

[0086] Samples 1-4, by satisfying T / W ≤ 0.714 and te / (ec×td) ≤ 0.800, were able to achieve miniaturization of multilayer electronic components while suppressing the occurrence of shrinkage cracks. However, in sample 1, te / (ec×td) was 0.758 or less, and it was confirmed that the short-circuit failure rate increased. This is presumably because the thickness of the internal electrodes was too thin relative to the thickness of the dielectric layer.

[0087] This disclosure is not limited by the embodiments described above and the accompanying drawings, but is limited by the claims attached. Therefore, within the scope of the technical idea of ​​this disclosure as described in the claims, various forms of substitution, modification, and alteration are possible by a person with ordinary skill in the art, and these also fall within the scope of this disclosure.

[0088] Furthermore, the expression "one embodiment" does not mean that each embodiment is identical to the others, but is provided to highlight and explain the unique and distinct characteristics of each embodiment. However, the above-presented embodiments do not preclude their implementation in combination with the features of other embodiments. For example, even if a matter described in one embodiment is not described in another embodiment, it can be understood as a description related to the other embodiment, unless there is a description in the other embodiment that contradicts or inconsists with that matter.

[0089] In this disclosure, the term "connected" includes not only direct connection but also indirect connection via an adhesive layer or the like. Furthermore, the term "electrically connected" includes both physically connected and non-connected cases. In addition, expressions such as "first," "second," etc., are used to distinguish one component from another and do not limit the order and / or importance of the components. In some cases, without departing from the scope of the rights, the first component may be named the second component, and similarly, the second component may be named the first component. [Explanation of Symbols]

[0090] 100 Stacked Electronic Components 110 Main Unit 111 Dielectric layer 112, 113 Cover section 121, 122 Internal electrode 121a, 122a Conductive part 121b, 122b Cut section 131, 132 External electrode 141, 142 Side margin section

Claims

1. As a stacked electronic component, A body comprising a dielectric layer and internal electrodes arranged alternately with the dielectric layer in a first direction, including a first and second surface facing each other in the first direction, a third and fourth surface connected to the first and second surfaces and facing each other in a second direction, and a fifth and sixth surface connected to the first, second, third and fourth surfaces and facing each other in a third direction, Includes external electrodes arranged on the third and fourth surfaces, The internal electrode includes a plurality of conductive parts and a cut portion disposed between adjacent conductive parts. When the average value of electrode connectivity, which is the ratio of the sum of the lengths of the plurality of conductive parts to the total length of the internal electrode, is ec, the average thickness of the dielectric layer is td, the average thickness of the internal electrode is te, the size of the multilayer electronic component in the first direction is T, and the size of the multilayer electronic component in the third direction is W, A multilayer electronic component satisfying te / (ec×td) ≤ 0.800 and T / W ≤ 0.

714.

2. A stacked electronic component according to claim 1, satisfying 0.758 < te / (ec × td).

3. The stacked electronic component according to claim 1, wherein the aforementioned ec satisfies 0.924 ≤ ec.

4. The multilayer electronic component according to claim 1, wherein td satisfies 450 nm ≤ td ≤ 600 nm.

5. The multilayer electronic component according to claim 1, wherein the te satisfies 370 nm ≤ te ≤ 550 nm.

6. A stacked electronic component according to claim 1, satisfying 0.400 ≤ T / W.

7. The stacked electronic component according to claim 1, wherein W satisfies 0.30 mm ≤ W ≤ 0.75 mm.

8. When the size of the stacked electronic component in the second direction is L, The stacked electronic component according to claim 1, wherein L satisfies the condition 0.80 mm ≤ L ≤ 1.25 mm.

9. The fifth and sixth surfaces include side margin portions, The stacked electronic component according to claim 1, wherein the side margin portion is arranged to cover the ends of the internal electrodes extending to the fifth and sixth surfaces.

10. The main body includes a capacitance forming portion including the dielectric layer and internal electrodes, and a first cover portion and a second cover portion, respectively, arranged on both sides of the capacitance forming portion facing the first direction. When the average value of the electrode connectivity measured in the central region of the first direction of the capacitance forming portion is denoted as ec1, the average value of the electrode connectivity measured in the upper region adjacent to the first cover portion of the capacitance forming portion is denoted as ec2, and the average value of the electrode connectivity measured in the lower region adjacent to the second cover portion of the capacitance forming portion is denoted as ec3, The stacked electronic component according to any one of claims 1 to 9, wherein the aforementioned ec is (ec1 + ec2 + ec3) / 3.

11. Let td1 be the average thickness of the dielectric layer measured in the central region, td2 be the average thickness of the dielectric layer measured in the upper region, and td3 be the average thickness of the dielectric layer measured in the lower region. When the average thickness of the internal electrode measured in the central region is denoted as te1, the average thickness of the internal electrode measured in the upper region is denoted as te2, and the average thickness of the internal electrode measured in the lower region is denoted as te3, The stacked electronic component according to claim 10, wherein td is (td1 + td2 + td3) / 3 and te is (te1 + te2 + te3) / 3.

12. A multilayer electronic component according to any one of claims 1 to 9, wherein the capacitance is 4 μF or more and 22 μF or less.

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