Semiconductor memory devices and memory systems

Abstract

To provide a semiconductor memory device that can operate suitably. [Solution] The semiconductor memory device comprises a memory cell array, a first pad electrode to which write data is input and read data is output, a comparator to which one input terminal is connected to the first pad electrode and a reference voltage is supplied to the other input terminal, a latch circuit to which the output signal of the comparator is latched according to a latch enable signal, and a second pad electrode to which a latch enable signal is supplied when write data is input. This semiconductor memory device is configured to perform a write data training operation. Furthermore, during the write data training operation, this semiconductor memory device receives test data of multiple bits via the first pad electrode and generates data indicating whether or not a bit error occurred when the test data was input. Furthermore, this semiconductor memory device is configured to output data indicating whether or not a bit error occurred.

Description

[Technical Field]

[0001] This embodiment relates to a semiconductor memory device and a memory system. [Background technology]

[0002] A memory system is known that has multiple semiconductor memory devices and a controller. The semiconductor memory device includes a memory cell array. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2015-176309 [Patent Document 2] Japanese Patent Publication No. 2022-154323 [Overview of the Initiative] [Problems that the invention aims to solve]

[0004] To provide a semiconductor memory device that can operate suitably. [Means for solving the problem]

[0005] A semiconductor memory device according to an embodiment includes a memory cell array, a first pad electrode to which write data is input when the write data is input to the memory cell array and from which read data is output when the read data read from the memory cell array is output, a first comparator having one input terminal connected to the first pad electrode and a reference voltage supplied to the other input terminal, a first latch circuit that latches the output signal of the first comparator in response to a first latch enable signal, and a second pad electrode to which the first latch enable signal is supplied when the write data is input. This semiconductor memory device is configured to be able to execute a write data training operation when adjusting the time interval between the timing of inputting write data to the first pad electrode and the timing of inputting the first latch enable signal to the second pad electrode, and when adjusting the reference voltage. Further, in this semiconductor memory device, during the write data training operation, a plurality of bits of test data are input via the first pad electrode, and data indicating whether or not a bit error has occurred during the input of the test data is generated. Also, this semiconductor memory device is configured to be able to output data indicating whether or not a bit error has occurred.

Brief Description of the Drawings

[0006] [Figure 1] It is a schematic block diagram showing the configuration of a memory system 10 according to the first embodiment. [Figure 2] It is a schematic side view showing a configuration example of the memory system 10. <000008 (It seems there is a typo here, should be [Figure 3] probably) It is a schematic plan view showing the same configuration example. [Figure 4] It is a schematic block diagram showing the configuration of a memory die MD according to the first embodiment. [Figure 5] It is a schematic circuit diagram showing a part of the configuration of the memory die MD. [Figure 6] It is a schematic perspective view showing a part of the configuration of the memory die MD. [Figure 7] It is a schematic circuit diagram showing a part of the configuration of the memory die MD. [Figure 8]It is a schematic circuit diagram showing a part of the configuration of the memory die MD. [Figure 9] It is a schematic timing chart showing the state of the write data training operation according to the first embodiment. [Figure 10] It is a schematic timing chart showing the state of the write data training operation according to the comparative example. [Figure 11] It is a schematic circuit diagram showing a configuration example of the input / output control circuit I / O according to the first embodiment. [Figure 12] It is a schematic circuit diagram showing an example of the configuration of the pointer generation circuit 250 according to the first embodiment. [Figure 13] It is a schematic waveform diagram showing the input / output signals of the pointer generation circuit 250 according to the first embodiment. [Figure 14] It is a schematic circuit diagram showing an example of the configuration of the parallel conversion circuit 260 according to the first embodiment. [Figure 15A] It is a schematic circuit diagram showing an example of the configuration of the data storage area 270 according to the first embodiment. [Figure 15B] It is a schematic circuit diagram showing an example of the configuration of the data storage area 270 according to the first embodiment. [Figure 16] It is a schematic timing chart showing the state of the write data training operation according to the first embodiment. [Figure 17] It is a diagram showing an example of the comparison result performed in the data storage area 270 according to the first embodiment. [Figure 18] It is a diagram showing an example of the comparison result performed in the data storage area 270 according to the first embodiment. [Figure 19] It is a schematic timing chart showing an example of the method of inputting the expected value according to the first embodiment. [Figure 20] It is a schematic circuit diagram showing a configuration example of the input / output control circuit I / O. [Figure 21] It is a schematic circuit diagram showing a configuration example of the input / output control circuit I / O. [Figure 22] It is a schematic circuit diagram showing a configuration example of the input / output control circuit I / O. [Figure 23] This is a schematic timing chart when the write data training operation according to the first embodiment is applied to SCA. [Figure 24] This is a schematic timing chart for simultaneously performing write data training operations on multiple memory dies (MDs). [Figure 25] This is a schematic circuit diagram showing a part of the configuration of the input / output control circuit I / O according to the second embodiment. [Figure 26] This is a schematic circuit diagram showing the configuration of the expectation value generator / comparator 280 according to the second embodiment. [Figure 27] This flowchart shows an example of the write data training operation of the input / output control circuit I / O according to the second embodiment. [Figure 28] This is a schematic timing chart showing a part of the write data training operation of the input / output control circuit I / O according to the second embodiment. [Figure 29] This is a schematic circuit diagram showing a part of the configuration of the input / output control circuit I / O according to the third embodiment. [Figure 30] This is a schematic circuit diagram showing the configuration of the expectation value generator / comparator 280b according to the third embodiment. [Figure 31] This is a diagram illustrating the write data training operation according to the fourth embodiment. [Figure 32] This is a diagram illustrating the write data training operation according to the fourth embodiment. [Figure 33] This is a schematic circuit diagram showing a part of the configuration of the input / output control circuit I / O according to the fourth embodiment. [Figure 34] This is a schematic circuit diagram showing the configuration of the error determination circuit 290 according to the fourth embodiment. [Figure 35] This is a schematic timing chart showing the write data training operation according to the fifth embodiment. [Modes for carrying out the invention]

[0007] Hereinafter, semiconductor memory devices according to the embodiments will be described in detail with reference to the drawings. Note that the following embodiments are merely examples and are not intended to limit the present invention. For the sake of explanation, some configurations may be omitted. Also, parts common to multiple embodiments are denoted by the same reference numerals, and their descriptions may be omitted.

[0008] Furthermore, in this specification, the term "semiconductor memory device" may refer to a memory die, or to a memory system including a controller die, such as a memory chip, memory card, or SSD (Solid State Drive). It may also refer to a configuration including a host computer, such as a smartphone, tablet device, or personal computer.

[0009] Furthermore, in this specification, when we say that the first configuration is "electrically connected" to the second configuration, the first configuration may be directly connected to the second configuration, or it may be connected to the second configuration via wiring, semiconductor components, or transistors. For example, when three transistors are connected in series, even if the second transistor is in the OFF state, the first transistor is "electrically connected" to the third transistor.

[0010] Furthermore, in this specification, when it is said that the first configuration is "connected between" the second and third configurations, it may mean that the first, second, and third configurations are connected in series, and that the second configuration is connected to the third configuration via the first configuration.

[0011] In this specification, a predetermined direction parallel to the upper surface of the substrate is referred to as the X direction, a direction parallel to the upper surface of the substrate and perpendicular to the X direction is referred to as the Y direction, and a direction perpendicular to the upper surface of the substrate is referred to as the Z direction.

[0012] Furthermore, in this specification, when we refer to the "width," "length," or "thickness" of a component, member, etc., in a predetermined direction, it may mean the width, length, or thickness of a cross-section observed by SEM (Scanning electron microscopy) or TEM (Transmission electron microscopy), etc.

[0013] [First Embodiment] [Memory System 10] Figure 1 is a schematic block diagram showing the configuration of the memory system 10 according to the embodiment.

[0014] The memory system 10 reads, writes, erases, etc., user data in response to signals transmitted from the host computer 20. The memory system 10 is, for example, a memory card, SSD, or other system capable of storing user data. The memory system 10 comprises a plurality of package PKGs and a controller die CD connected to these plurality of package PKGs and the host computer 20. Each package PKG contains a plurality of memory dies MD. Each memory die MD is capable of storing user data. The controller die CD includes, for example, a processor, RAM, etc., and performs processing such as logical address-to-physical address conversion, bit error detection / correction, garbage collection (compaction), and wear leveling.

[0015] Figure 2 is a schematic side view showing an example configuration of the memory system 10 according to this embodiment. Figure 3 is a schematic top view showing the same configuration example. For the sake of explanation, some components are omitted in Figures 2 and 3.

[0016] As shown in Figure 2, the memory system 10 according to this embodiment comprises a mounting substrate MSB, a plurality of memory dies MD stacked on the mounting substrate MSB, and a controller die CD stacked on the memory dies MD. Pad electrodes P are provided on the upper surface of the mounting substrate MSB at the Y-direction end region, and some other regions are bonded to the lower surface of the memory dies MD via adhesive or the like. Pad electrodes P are provided on the upper surface of the memory dies MD at the Y-direction end region, and other regions are bonded to the lower surface of other memory dies MD or controller die CD via adhesive or the like. Pad electrodes P are provided on the upper surface of the controller die CD at the Y-direction end region.

[0017] As shown in Figure 3, the mounting substrate MSB, the multiple memory dies MD, and the controller die CD each have multiple pad electrodes P arranged in the X direction. The multiple pad electrodes P on the mounting substrate MSB, the multiple memory dies MD, and the controller die CD are each connected to one another via bonding wires B.

[0018] Note that the configurations shown in Figures 2 and 3 are merely examples, and the specific configuration can be adjusted as appropriate. For example, in the examples shown in Figures 2 and 3, controller dies CD are stacked on multiple memory dies MD, and these components are connected by bonding wires B. In such a configuration, multiple memory dies MD and controller dies CD are contained within a single package. However, the controller die CD may be contained in a separate package from the memory dies MD. Also, multiple memory dies MD and controller dies CD may be connected to each other via through-electrodes or the like, instead of bonding wires B.

[0019] [Memory die MD configuration] Figure 4 is a schematic block diagram showing the configuration of the memory die MD according to this embodiment. Figure 5 is a schematic circuit diagram showing a part of the configuration of the memory die MD. Figure 6 is a schematic perspective view showing a part of the configuration of the memory die MD. Figures 7 and 8 are schematic circuit diagrams showing a part of the configuration of the memory die MD. For the sake of explanation, some configurations are omitted in Figures 4 to 8.

[0020] Figure 4 illustrates multiple control terminals. These control terminals may be represented as terminals corresponding to high-active signals (positive logic signals), as terminals corresponding to low-active signals (negative logic signals), or as terminals corresponding to both high-active and low-active signals. In Figure 4, the symbols for control terminals corresponding to low-active signals include an overline. In this specification, the symbols for control terminals corresponding to low-active signals include a slash (" / "). Note that the description in Figure 4 is illustrative, and the specific configuration can be adjusted as appropriate. For example, some or all high-active signals may be treated as low-active signals, or some or all low-active signals may be treated as high-active signals. It is also possible to use the letter B as the initial instead of an overline or slash (" / ").

[0021] Furthermore, arrows indicating input / output directions are illustrated next to the multiple control terminals shown in Figure 4. In Figure 4, control terminals with arrows pointing from left to right can be used for inputting data or other signals from the controller die CD to the memory die MD. In Figure 4, control terminals with arrows pointing from right to left can be used for outputting data or other signals from the memory die MD to the controller die CD. In Figure 4, control terminals with arrows pointing in both directions can be used for both inputting data or other signals from the controller die CD to the memory die MD, and outputting data or other signals from the memory die MD to the controller die CD.

[0022] As shown in Figure 4, the memory die MD comprises memory cell arrays MCA0 and MCA1 for storing user data, and peripheral circuits PC connected to the memory cell arrays MCA0 and MCA1. In the following description, the memory cell arrays MCA0 and MCA1 may be referred to as the memory cell array MCA. Also, the memory cell arrays MCA0 and MCA1 may be referred to as the planes PLN0 and PLN1.

[0023] [Memory Cell Array (MCA) Configuration] As shown in Figure 5, the memory cell array MCA comprises multiple memory blocks BLK. Each of these memory blocks BLK comprises multiple string units SU. Each of these string units SU comprises multiple memory strings MS. One end of each of these memory strings MS is connected to a peripheral circuit PC via a bit line BL. The other end of each of these memory strings MS is connected to the peripheral circuit PC via a common source line SL.

[0024] A memory string MS comprises a drain-side selection transistor STD connected in series between the bit line BL and the source line SL, multiple memory cells MC (memory cell transistors), a source-side selection transistor STS, and a source-side selection transistor STSb. Hereinafter, the drain-side selection transistor STD, source-side selection transistor STS, and source-side selection transistor STSb may simply be referred to as selection transistors (STD, STS, STSb).

[0025] A memory cell MC is a field-effect transistor comprising a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer functions as a channel region. The gate insulating film includes a charge storage film. The threshold voltage of the memory cell MC varies depending on the amount of charge in the charge storage film. The memory cell MC stores one or more bits of user data. Word lines WL are connected to the gate electrodes of multiple memory cell MCs corresponding to one memory string MS. These word lines WL are each commonly connected to all memory string MS in one memory block BLK.

[0026] A selection transistor (STD, STS, STSb) is a field-effect transistor comprising a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer functions as a channel region. A selection gate line (SGD, SGS, SGSb) is connected to the gate electrode of each selection transistor (STD, STS, STSb). The drain-side selection gate line SGD is provided corresponding to a string unit SU and is commonly connected to all memory strings MS in one string unit SU. The source-side selection gate line SGS is commonly connected to all memory strings MS in a memory block BLK. The source-side selection gate line SGSb is commonly connected to all memory strings MS in a memory block BLK.

[0027] The memory cell array (MCA) is located above the semiconductor substrate 100, as shown in Figure 6, for example. In the example shown in Figure 6, multiple transistors Tr, which constitute the peripheral circuit PC, are provided between the semiconductor substrate 100 and the memory cell array (MCA).

[0028] The memory cell array (MCA) comprises multiple memory blocks (BLK) arranged in the Y direction. Furthermore, an interblock insulating layer (ST) made of silicon oxide (SiO2) or the like is provided between two adjacent memory blocks (BLK) in the Y direction.

[0029] The memory block BLK comprises, for example, a plurality of conductive layers 110 arranged in the Z direction, a plurality of semiconductor pillars 120 extending in the Z direction, and a plurality of gate insulating films 130 provided between the plurality of conductive layers 110 and the plurality of semiconductor pillars 120, respectively.

[0030] The conductive layer 110 is a substantially plate-shaped conductive layer stretched in the X direction. The conductive layer 110 may contain a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). The conductive layer 110 may also contain polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). An insulating layer 101 such as silicon oxide (SiO2) is provided between a plurality of conductive layers 110 aligned in the Z direction.

[0031] Furthermore, of the multiple conductive layers 110, two or more conductive layers 110 located at the bottom function as gate electrodes for the source-side selection gate lines SGS, SGSb (Figure 5) and the multiple source-side selection transistors STS, STSb connected thereto. These multiple conductive layers 110 are electrically independent for each memory block BLK.

[0032] Furthermore, the multiple conductive layers 110 located above this function as gate electrodes for the word line WL (Figure 5) and the multiple memory cells MC (Figure 5) connected thereto. Each of these multiple conductive layers 110 is electrically independent for each memory block BLK.

[0033] Furthermore, one or more conductive layers 110 located above this function as gate electrodes for the drain-side selection gate wire SGD and the multiple drain-side selection transistors STD (Figure 5) connected thereto. These multiple conductive layers 110 have a smaller width in the Y direction than the other conductive layers 110.

[0034] A semiconductor layer 112 is provided below the conductive layer 110. The semiconductor layer 112 may contain, for example, polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). An insulating layer 101, such as silicon oxide (SiO2), is provided between the semiconductor layer 112 and the conductive layer 110.

[0035] The semiconductor layer 112 functions as a source line SL (Figure 5). The source line SL is provided in common for all memory blocks BLK included in the memory cell array MCA, for example.

[0036] The semiconductor pillars 120 are arranged in a predetermined pattern in the X and Y directions, as shown in Figure 6, for example. The semiconductor pillars 120 function as channel regions for multiple memory cells MC and selection transistors (STD, STS, STSb) included in one memory string MS (Figure 5). The semiconductor pillars 120 are semiconductor layers, such as polycrystalline silicon (Si). The semiconductor pillars 120 have a substantially bottomed cylindrical shape, as shown in Figure 6, for example, and an insulating layer 125, such as silicon oxide, is provided in the central part. The outer surfaces of the semiconductor pillars 120 are each surrounded by conductive layers 110 and face the conductive layers 110.

[0037] An impurity region 121 containing N-type impurities such as phosphorus (P) is provided at the upper end of the semiconductor column 120. The impurity region 121 is connected to the bit line BL via contacts Ch and Cb.

[0038] The gate insulating film 130 has a substantially bottomed cylindrical shape that covers the outer circumferential surface of the semiconductor column 120. The gate insulating film 130 includes, for example, a tunnel insulating film, a charge storage film, and a block insulating film laminated between the semiconductor column 120 and the conductive layer 110. The tunnel insulating film and the block insulating film are insulating films such as silicon oxide (SiO2). The charge storage film is a charge-storing film such as silicon nitride (Si3N4). The tunnel insulating film, the charge storage film, and the block insulating film have a substantially cylindrical shape and extend in the Z direction along the outer circumferential surface of the semiconductor column 120, excluding the contact portion between the semiconductor column 120 and the semiconductor layer 112.

[0039] Furthermore, the gate insulating film 130 may include a floating gate made of, for example, polycrystalline silicon containing N-type or P-type impurities.

[0040] Multiple contacts CC are provided at the ends of the multiple conductive layers 110 in the X direction. The multiple conductive layers 110 are connected to the peripheral circuit PC via these multiple contacts CC. As shown in Figure 6, these multiple contacts CC extend in the Z direction and are connected to the conductive layer 110 at their lower ends. The contacts CC may include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W).

[0041] [Peripheral Circuit PC Configuration] The peripheral circuit PC includes, for example, row decoders RD0 and RD1 connected to memory cell arrays MCA0 and MCA1, respectively, and sense amplifiers SA0 and SA1, as shown in Figure 4. The peripheral circuit PC also includes a voltage generation circuit VG and a sequencer SQC. Furthermore, the peripheral circuit PC includes an input / output control circuit I / O (first circuit), a logic circuit CTR, a register RG, and a data output timing adjustment unit TCT. Register RG includes an address register ADR, a command register CMR, and a status register STR. In the following description, row decoders RD0 and RD1 may be referred to as row decoder RD, and sense amplifiers SA0 and SA1 may be referred to as sense amplifier SA.

[0042] [Row Decoder RD Configuration] The row decoder RD (Figure 4), as shown in Figure 5 for example, includes an address decoder 22 that decodes address data Add (Figure 4), and a block selection circuit 23 and a voltage selection circuit 24 that transfer operating voltages to the memory cell array MCA according to the output signal of the address decoder 22.

[0043] The address decoder 22 includes, for example, multiple block selection lines BLKSEL and multiple voltage selection lines 33, as shown in Figure 5. The address decoder 22 sequentially references the row address RA of the address register ADR (Figure 4) according to a control signal from the sequencer SQC, decodes this row address RA, and sets a predetermined block selection transistor 35 and voltage selection transistor 37 corresponding to the row address RA to the ON state, and the other block selection transistors 35 and voltage selection transistors 37 to the OFF state. For example, the voltage of the predetermined block selection line BLKSEL and voltage selection line 33 is set to the "H" state, and the other voltages are set to the "L" state. Note that if a P-channel type transistor is used instead of an N-channel type, the opposite voltage is applied to these wires.

[0044] In the illustrated example, the address decoder 22 is provided with one block selection line BLKSEL for each memory block BLK. However, this configuration can be changed as appropriate. For example, it may be provided with one block selection line BLKSEL for two or more memory blocks BLK.

[0045] The block selection circuit 23 includes a plurality of block selection units 34 corresponding to memory block BLK, as shown in Figure 5, for example. Each of these block selection units 34 includes a plurality of block selection transistors 35 corresponding to a word line WL and a selection gate line (SGD, SGS, SGSb). The block selection transistors 35 are, for example, field-effect type breakdown transistors. The drain electrodes of the block selection transistors 35 are electrically connected to the corresponding word line WL or selection gate line (SGD, SGS, SGSb). The source electrodes are electrically connected to the wiring CG and the voltage supply line 31 via the voltage selection circuit 24, respectively. The gate electrodes are commonly connected to the corresponding block selection line BLKSEL.

[0046] Furthermore, the block selection circuit 23 includes several transistors (not shown). These transistors are connected to a selection gate line (SGD, SGS, SGSb) and a ground voltage VSS These are field-effect type breakdown transistors connected between the voltage supply lines to which the ground voltage V is supplied. These transistors connect to the selected gate lines (SGD, SGS, SGSb) contained in the unselected memory block BLK with the ground voltage V SS This supplies the necessary resources. Note that multiple word lines WL included in the unselected memory block BLK will be in a floating state.

[0047] The voltage selection circuit 24 includes, for example, a plurality of voltage selection units 36 corresponding to word lines WL and selection gate lines (SGD, SGS, SGSb), as shown in Figure 5. Each of these plurality of voltage selection units 36 includes a plurality of voltage selection transistors 37. The voltage selection transistors 37 are, for example, field-effect type breakdown transistors. The drain terminals of the voltage selection transistors 37 are electrically connected to the corresponding word line WL or selection gate lines (SGD, SGS, SGSb) via wiring CG and block selection circuit 23, respectively. The source terminals are electrically connected to the corresponding voltage supply lines 31, respectively. The gate electrodes are connected to the corresponding voltage selection lines 33, respectively.

[0048] [SenseAmp SA Configuration] The sense amplifiers SA0 and SA1 (Figure 4) each comprise a sense amplifier module SAM0 and SAM1, and cache memories CM0 and CM1, respectively. The cache memories CM0 and CM1 each comprise latch circuits XDL0 and XDL1, respectively.

[0049] In the following explanation, sense amplifier modules SAM0 and SAM1 may be referred to as sense amplifier module SAM, cache memories CM0 and CM1 as cache memory CM, and latch circuits XDL0 and XDL1 as latch circuits XDL.

[0050] The sense amplifier module SAM comprises, for example, a sense circuit corresponding to each of several bit lines BL, and several latch circuits connected to the sense circuits.

[0051] The cache memory CM comprises multiple latch circuits XDL. Each of the multiple latch circuits XDL is connected to a latch circuit in the sense amplifier module SAM. The latch circuits XDL store, for example, user data Dat written to the memory cell MC or user data Dat read from the memory cell MC.

[0052] A column decoder COLD is connected to the cache memory CM, for example, as shown in Figure 7. The column decoder COLD decodes the column address CA stored in the address register ADR (Figure 4) and selects the latch circuit XDL corresponding to the column address CA.

[0053] Furthermore, the user data Dat contained in these multiple latch circuits XDL is sequentially transferred to the latch circuits in the sense amplifier module SAM during a write operation. Similarly, the user data Dat contained in the latch circuits in the sense amplifier module SAM is sequentially transferred to the latch circuits XDL during a read operation. Finally, the user data Dat contained in the latch circuits XDL is sequentially transferred to the input / output control circuit I / O via the column decoder COLD and multiplexer MPX during a data output operation.

[0054] [Configuration of the voltage generation circuit VG] The voltage generation circuit VG (Figure 4) is connected to multiple voltage supply lines 31, as shown in Figure 5, for example. The voltage generation circuit VG includes, for example, a step-down circuit such as a regulator and a step-up circuit such as a charge pump circuit 32. These step-down and step-up circuits each supply the power supply voltage V CC and ground voltage V SS(Figure 4) is connected to the voltage supply lines. These voltage supply lines are connected to the pad electrodes P, as described with reference to Figures 2 and 3. The voltage generation circuit VG generates multiple operating voltages to be applied to the bit line BL, source line SL, word line WL and selection gate lines (SGD, SGS, SGSb) during read, write, and erase operations on the memory cell array MCA, according to a control signal from the sequencer SQC, and outputs them simultaneously to multiple voltage supply lines 31. The operating voltages output from the voltage supply lines 31 are adjusted as appropriate according to the control signal from the sequencer SQC.

[0055] [Configuration of the SQC sequencer] The sequencer SQC (Figure 4) outputs internal control signals to the row decoders RD0 and RD1, the sense amplifier modules SAM0 and SAM1, and the voltage generation circuit VG, according to the command data Cmd stored in the command register CMR. The sequencer SQC also outputs status data Stt, which indicates the state of the memory die MD, to the status register STR as appropriate. The state of the memory die MD includes the ready / busy state of the memory die MD. Hereafter, the ready / busy state may simply be referred to as the "ready / busy state".

[0056] Furthermore, the sequencer SQC generates a ready / busy signal and outputs it to the RY / / BY terminal. The RY / / BY terminal is in the "L" state during operations that supply voltage to the memory cell array MCA, such as read operations, write operations, and erase operations, as well as during Get Feature and Set Feature operations, and in the "H" state at all other times. Note that the RY / / BY terminal will not be in the "L" state when operations that do not supply voltage to the memory cell array MCA, such as data-out operations and status reads, are performed. During the period when the RY / / BY terminal is in the "L" state (busy period), access to the memory die MD is basically prohibited. Conversely, during the period when the RY / / BY terminal is in the "H" state (ready period), access to the memory die MD is permitted. The RY / / BY terminal is implemented by the pad electrode P, as explained with reference to Figures 2 and 3.

[0057] Furthermore, the SQC sequencer includes a feature register FR. The feature register FR is a register that holds feature data Fd. The feature data Fd includes, for example, control parameters for the memory die MD.

[0058] [Address Register ADR Configuration] As shown in Figure 4, the address register ADR is connected to the input / output control circuit I / O and stores the address data Add input from the input / output control circuit I / O. The address register ADR comprises, for example, multiple 8-bit register sequences. When internal operations such as read, write, or erase operations are performed, the register sequences hold the address data Add corresponding to the internal operation being performed.

[0059] The address data Add includes, for example, the column address CA (Figure 4) and the row address RA (Figure 4). The row address RA includes, for example, the block address that identifies the memory block BLK (Figure 5), the page address that identifies the string unit SU and the word line WL, the plane address that identifies the memory cell array MCA (plane), and the chip address that identifies the memory die MD.

[0060] [Configuration of the Command Register CMR] The command register CMR is connected to the input / output control circuit I / O and stores the command data Cmd input from the I / O. The command register CMR comprises, for example, at least one set of 8-bit register sequences. When the command data Cmd is stored in the command register CMR, a control signal is sent to the sequencer SQC.

[0061] [Status Register STR Configuration] The status register STR is connected to the input / output control circuit I / O and stores status data Stt that is output to the input / output control circuit I / O. The status register STR comprises, for example, multiple 8-bit register sequences. When internal operations such as read, write, or erase operations are performed, the register sequences hold status data Stt related to the internal operation being performed. The register sequences also hold, for example, ready / busy information indicating the ready / busy state of memory cell arrays MCA0 and MCA1.

[0062] [Configuration of the Data Output Timing Adjustment Unit (TCT)] The data output timing adjustment unit TCT is connected to the bus wiring DB between the cache memories CM0 and CM1 and the input / output control circuit I / O. The data output timing adjustment unit TCT adjusts the start timing of the data output operation for cache memory CM1 so that, for example, when performing data output operations for cache memories CM0 and CM1 consecutively, the data output operation for cache memory CM1 starts immediately after the completion of the data output operation for cache memory CM0.

[0063] [Configuration of Input / Output Control Circuit I / O] The input / output control circuit I / O (Figure 4) includes data signal input / output terminals DQ0 to DQ7, data strobe signal input / output terminals DQS, / DQS (BDQS), a shift register, and a buffer circuit.

[0064] Each of the data signal input / output terminals DQ0 to DQ7 and the data strobe signal input / output terminals DQS, / DQS(BDQS) is implemented by a pad electrode P, as explained with reference to Figures 2 and 3. Data input via data signal input / output terminals DQ0 to DQ7 is input from the buffer circuit to the cache memory CM in accordance with an internal control signal from the logic circuit CTR. Similarly, data output via data signal input / output terminals DQ0 to DQ7 is input from the cache memory CM or status register STR to the buffer circuit in accordance with an internal control signal from the logic circuit CTR.

[0065] Signals input via the data strobe signal input / output terminals DQS and / DQS(BDQS) (e.g., data strobe signals and their complementary signals) are used when inputting data via the data signal input / output terminals DQ0 to DQ7. The data input via the data signal input / output terminals DQ0 to DQ7 is captured into the shift register in the input / output control circuit I / O at the timing of the rising edge of the voltage of the data strobe signal input / output terminal DQS and the falling edge of the voltage of the data strobe signal input / output terminal / DQS(BDQS), as well as at the timing of the falling edge of the voltage of the data strobe signal input / output terminal DQS and the rising edge of the voltage of the data strobe signal input / output terminal / DQS(BDQS).

[0066] Each of the data signal input / output terminals DQ0 to DQ7 and the data strobe signal input / output terminals DQS, / DQS(BDQS) is connected to the input circuit 201 and the output circuit 202, respectively, as shown in Figure 8, for example. The input circuit 201 is a receiver, such as a comparator. The output circuit 202 is a driver, such as an OCD (Off Chip Driver) circuit.

[0067] [Configuration of the logic circuit CTR] The logic circuit CTR (Figure 4) comprises multiple control terminals / CE, CLE, ALE, / WE, / RE(BRE), RE, and / WP, and logic circuits connected to these control terminals / CE, CLE, ALE, / WE, / RE(BRE), RE, and / WP. The logic circuit CTR receives external control signals from the controller die CD via the control terminals / CE, CLE, ALE, / WE, / RE(BRE), RE, and / WP, and outputs internal control signals to the input / output control circuit I / O accordingly.

[0068] Each of the control terminals / CE, CLE, ALE, / WE, / RE(BRE), RE, and / WP is connected to the input circuit 201, as shown in Figure 8, for example. In the illustrated example, each of the control terminals CLE, ALE, and / WP is further connected to the output circuit 202. Each of the control terminals / CE, CLE, ALE, / WE, / RE(BRE), RE, and / WP is realized by the pad electrodes P, as explained with reference to Figures 2 and 3, for example.

[0069] The signal input via the control terminal / CE (for example, the chip enable signal) is used when selecting the memory die MD. When "L" is input to the control terminal / CE, the memory die MD becomes capable of inputting and outputting user data Dat, command data Cmd, address data Add, and status data Stt (hereinafter sometimes simply referred to as "data"). When "H" is input to the control terminal / CE, the memory die MD becomes incapable of inputting and outputting data. As shown in Figure 8, the control terminal / CE is connected to the input circuit 201.

[0070] Signals input via the control terminal CLE (e.g., the command latch enable signal) are used when using the command register CMR, etc. Signals input via the control terminal CA1 (CLE) are also used when using the command register CMR, etc., and are also used as command data Cmd and address data Add. Furthermore, status data Stt is output from the status register STR via the control terminal CLE.

[0071] Signals input via the control terminal ALE (for example, the address latch enable signal) are used when using the address register ADR, etc. Furthermore, signals input via the control terminal ALE are used when using the address register ADR, etc., and are also used as command data Cmd and address data Add. In addition, status data Stt is output from the status register STR via the control terminal ALE. Furthermore, signals input via the control terminal ALE are used when using the address register ADR, etc., and are also used as command data Cmd and address data Add. In addition, status data Stt is output from the status register STR via the control terminal ALE.

[0072] Signals input via the control terminal / WE (e.g., write enable signal) are used for inputting data from the controller die CD to the memory die MD, etc.

[0073] Signals input via the control terminals / RE(BRE) and RE (e.g., the read enable signal and its complementary signal) are used when outputting data via the data signal input / output terminals DQ0 to DQ7. The data output from the data signal input / output terminals DQ0 to DQ7 is switched at the timing of the falling edge of the voltage at the control terminal / RE(BRE) (input signal switching) and the rising edge of the voltage at the control terminal RE (input signal switching), as well as at the timing of the rising edge of the voltage at the control terminal / RE(BRE) (input signal switching) and the falling edge of the voltage at the control terminal RE (input signal switching).

[0074] Signals input via the control terminal / WP (e.g., write-protect signals) are used to restrict the input of user data Dat from the controller die CD to the memory die MD. Signals input via the control terminal / WP may also be used as command data Cmd and address data Add, or status data Stt may be output from the status register STR via the control terminal / WP.

[0075] [Memory die MD operation] Next, we will explain the operation of the memory die MD.

[0076] The memory die MD is configured to perform read operations. The read operation involves reading user data Dat from the memory cell array MCA using the sense amplifier module SAM and transferring the read user data Dat to the latch circuit XDL. In the read operation, the user data Dat read from the memory cell array MCA is transferred to the latch circuit XDL via the bit line BL and the sense amplifier module SAM.

[0077] Furthermore, the memory die MD is configured to perform data-out operations. The data-out operation of user data Dat is the operation of outputting the user data Dat contained in the latch circuit XDL to the controller die CD. In the data-out operation of user data Dat, the user data Dat contained in the latch circuit XDL is output to the controller die CD via the column decoder COLD, multiplexer MPX, bus wiring DB, and input / output control circuit I / O, as explained with reference to Figure 7.

[0078] Furthermore, the memory die MD is configured to perform status reads. A status read is an operation that outputs the status data Stt contained in the status register STR to the controller die CD. In a status read, the status data Stt contained in the status register STR is output to the controller die CD via the logic circuit CTR.

[0079] Furthermore, the memory die MD is configured to execute Get Feature (characteristic information output operation). Get Feature is an operation that outputs the feature data Fd contained in the feature register FR (Figure 4) to the controller die CD (Figure 1). In Get Feature, the feature data Fd contained in the feature register FR is output to the controller die CD via the logic circuit CTR.

[0080] Furthermore, the memory die MD is configured to execute set features. Set feature is an operation that inputs feature data Fd into the feature register FR (Figure 4). In set feature, feature data Fd is input from the controller die CD to the feature register FR via the logic circuit CTR.

[0081] Furthermore, the memory die MD is configured to perform write data training operations.

[0082] As described above, the data input via data signal input / output terminals DQ0 to DQ7 is captured into the shift register in the input / output control circuit I / O at the timing of the voltage switching of the data strobe signal input / output terminals DQS, / DQS(BDQS). Therefore, the controller die CD normally switches the voltage of the data strobe signal input / output terminals DQS, / DQS(BDQS) while data is input to data signal input / output terminals DQ0 to DQ7. It is desirable that the time from when the signal input to data signal input / output terminal DQ<7:0> switches until the signal input to data strobe signal input / output terminals DQS, / DQS(BDQS) (data strobe signal) switches, and the time from when the signal input to data strobe signal input / output terminal DQS, / DQS(BDQS) (data strobe signal) switches until the signal input to data signal input / output terminal DQ<7:0> switches, be equal. Here, the optimal time (hereinafter sometimes referred to as "Skew") between inputting data to data signal input / output terminals DQ0 to DQ7 and switching the voltage of data strobe signal input / output terminals DQS, / DQS (BDQS) may vary depending on operating conditions such as temperature.

[0083] As explained with reference to Figure 8, the data signal input / output terminals DQ0 to DQ7 are connected to the input circuit 201, such as a comparator. Therefore, if the voltages of the data signal input / output terminals DQ0 to DQ7 are greater than the reference voltage of the input circuit 201, "1" is output from the input circuit 201, and if the voltages of the data signal input / output terminals DQ0 to DQ7 are less than the reference voltage of the input circuit 201, "0" is output from the input circuit 201. However, the optimal value of the reference voltage of the input circuit 201 may vary depending on operating conditions such as temperature.

[0084] During the write data training operation, the optimal values ​​for the reference voltages of the Skew and input circuit 201 are detected by sequentially switching the reference voltages of the Skew and input circuit 201, while inputting data from the controller die CD to the memory die MD and detecting bit errors. The write data training operation is performed, for example, when the memory die MD is powered on, or when there is a fluctuation in temperature or power supply voltage (VCCQ, etc.).

[0085] [Write data training operation] Figure 9 is a schematic timing chart showing the process when performing a write data training operation (Write DQ training operation). In the write data training operation according to this embodiment, first, expected data (pattern data) is input to the memory die MD. The expected data is input with sufficient time to avoid bit errors. For example, the voltage of the data strobe signal input / output terminals DQ, / DQS (BDQS) is switched after waiting long enough for the signal of the data signal input / output terminal DQ<7:0> to reach a value of "L" or "H". Next, while sequentially switching the reference voltage of Skew and input circuit 201, data identical to the expected data (pattern data) (hereinafter sometimes referred to as "test data") is input multiple times from the controller die CD to the memory die MD. The test data is executed in the same manner as normal data input when performing a write operation, for example. If the reference voltage of Skew and input circuit 201 is appropriate, no bit errors will occur during data input, and the expected data and the test data will match. If at least one of the reference voltages of the Skew and input circuit 201 is inappropriate, a bit error will occur during data input, resulting in discrepancies between the expected data and the test data.

[0086] In this embodiment, each memory die MD is assigned a different LUN (Logical Unit Number) address as LUN0 and LUN1, respectively, and can be identified by its LUN address. In other words, the two memory die MDs included in the memory system 10 are configured to function as LUN0 and LUN1, respectively. In the following, the LUN addresses assigned to the memory die MDs will be described as LUNs.

[0087] In this embodiment, as shown in Figure 9, at the start of the write data training operation (time t start In this process, the command data "63h" and the LUN address "LUN" are sequentially input from the controller die CD to the memory die MD via the data signal input / output terminals DQ0 to DQ7. The command data "63h" is the command data Cmd that instructs data input (write operation) during the write data training operation. The LUN address "LUN" included in this command set contains information about the memory cell array MCA (Figure 4) that is the target of the write operation.

[0088] After the LUN address "LUN" is entered, test data held in the memory die MD is input from the controller die CD to the memory die MD via the data signal input / output terminal DQ<7:0>. The input data is compared in real time with the expected value data held in the memory die MD. Here, the input data is user data Dat, which is a data pattern of a predetermined bit length (data D0~Dn) repeated n times. The predetermined bit length of the data pattern is determined by the write data training standard. Time T11 is the time from when the LUN address "LUN" is entered until the input of the data pattern begins, and time T12 is the time required for, for example, the predetermined bit length data pattern (data D0~Dn) to be input n times and compared with the expected value held in the memory die MD.

[0089] After the test data (data pattern) is input, the command data "7xh" is input from the controller die CD to the memory die MD via the data signal input / output terminals DQ0 to DQ7. The command data "7xh" is a command data Cmd that instructs a status read. After the command data "7xh" is input, a status read is performed on the memory die MD specified, for example, by the LUN address.

[0090] Time T13 is the time between the input of test data (data pattern) and the input of command data "7xh". Time T14 is the time between the input of command data "7xh" and the execution of the status read. Time T15 is the time required for the status read to be executed. When the status read is executed, the result of comparing the input data with the expected value held in the memory die MD is output as status data Stt.

[0091] Time T17 is the time required for the controller die CD to acquire the comparison result and perform a Pass / Fail determination. The controller die CD can perform a Pass / Fail determination using the comparison result (status data Stt) acquired by the status read. Time T16 is the time from when the comparison result is output to the status register STR until the Pass / Fail determination begins.

[0092] Time T c_total This occurs at the start of the write data training operation (time t start ) From the end of time T17, i.e., the end time of the Pass / Fail determination t end This is the time required for the data writing training operation up to that point.

[0093] [Write data training operation in comparative example] Figure 10 is a schematic timing chart showing the write data training operation for a comparative example.

[0094] In the comparative example, as shown in FIG. 10, at the start of the write data training operation (time t start ), the command data "63h" and the LUN address "LUN" are sequentially input from the controller die CD to the memory die MD via the data signal input / output terminals DQ0 to DQ7.

[0095] After the LUN address "LUN" is input, a data pattern of a predetermined bit length (data D0 to Dn) is input from the controller die CD to the memory die MD via the data signal input / output terminals DQ<7:0>. Note that the time T92 is, for example, the time required for inputting a data pattern of a predetermined bit length (data D0 to Dn).

[0096] After the data pattern of a predetermined bit length (data D0 to Dn) is input, the command data "64h" and the LUN address "LUN" are sequentially input from the controller die CD to the memory die MD via the data signal input / output terminals DQ0 to DQ7. The command data "64h" is the command data Cmd for instructing data out.

[0097] After the command data "64h" is input, data out of the input data (data D0 to Dn) is executed in the memory die MD specified by the LUN address.

[0098] Time T94 is the time between the input of the command data "64h" and the input of the LUN address "LUN". Time T95 is the time between the input of the LUN address "LUN" and the execution of data output, and is the same length as time T14. Time T96 is the time required for the data output of the input data (data D0~Dn) to be executed, and is longer than time T16. Once data output is executed, the input data is read out to the controller die CD. At time T97, the controller die CD compares the read data with the expected data held by the controller die CD, and adjusts the skew of the data strobe signal input to the data strobe signal input / output terminal DQS and the data input to the data signal input / output terminal DQ<7:0>, as well as the reference voltage VREF of the memory die MD, based on whether the read data and the expected data match.

[0099] After the end of time T97, time t start From the input of command data "63h", the end time t of time T97 end The sequence of actions up to this point is repeated n times.

[0100] Time T c_total This is the time required for the write data training operation to complete. Time T total So, time t start From the input of command data "63h", the end time t of time T97 end This is the time required for the sequence of actions up to that point to be repeated n times. Therefore, time T c_total is time T total It is longer than that.

[0101] [Effects, etc.] During data in and data out operations, bus wiring connected to the data signal input / output terminal DQ<7:0> is used between the controller die CD and the memory die MD. Therefore, while the write data training operation is running, other memory dies MD connected to the same bus wiring cannot perform data in and data out operations. Consequently, the time required to perform the write data training operation becomes a time overhead for the memory system 10.

[0102] In the comparative example's data training operation, the data used for comparison with the expected value only corresponds to data patterns of a predetermined bit length (data D0 to Dn) as defined by the standard. Therefore, when using data patterns longer than the predetermined bit length for comparison with the expected value, as explained in Figure 10, time t start From the input of command data "63h", the end time t of time T97 end Since it is necessary to repeat this series of sequential operations, it takes a long time, and the time overhead of the memory system 10 becomes large.

[0103] Therefore, in the write data training operation according to this embodiment, the expected value data is stored on the memory die MD instead of the controller die CD, and the data input via data input is compared with the expected value data. The comparison result is output as status data Stt. As a result, the repeated times T94 and T96 in the comparative example are unnecessary, and the time overhead of the memory system 10 in the write data training operation can be reduced.

[0104] Furthermore, in the write data training operation according to this embodiment, during the execution of data input, it is possible to input data that repeats a predetermined bit length data pattern (data D0 to Dn) n times and compare it with the expected value data. This makes it possible to use data patterns with bit lengths exceeding the predetermined bit length data patterns defined by the standard.

[0105] [Example configuration of input / output control circuit (I / O)] Next, the configuration of the input / output control circuit I / O for realizing the write data training operation according to this embodiment will be described. Figure 11 is a schematic circuit diagram showing an example of the configuration of the input / output control circuit I / O. Figure 12 is a schematic circuit diagram showing an example of the configuration of the pointer generation circuit 250 according to this embodiment. Figure 13 is a schematic waveform diagram showing the input and output signals of the pointer generation circuit 250 according to this embodiment. Figure 14 is a schematic circuit diagram showing an example of the configuration of the parallel conversion circuit 260 according to this embodiment. Figures 15A and 15B are schematic circuit diagrams showing an example of the configuration of the data storage area 270 according to this embodiment.

[0106] The input / output control circuit I / O (Figure 4), as shown in Figure 11 for example, includes an input circuit 210 and an output circuit 240 connected to the data signal input / output terminal DQ<7:0>, a comparator 221 connected to the data strobe signal input / output terminals DQS and BDQS, a signal propagation circuit 222 that propagates the output signal of the comparator 221, a pointer generation circuit 250, a parallel conversion circuit 260, and a data storage area 270. Also shown in Figure 11 as part of the logic circuit CTR are a comparator 231 connected to the control terminals REn and BREn, and a signal propagation circuit 232 that propagates the output signal of the comparator 231.

[0107] [Example configuration of comparator 221 and signal propagation circuit 222] Comparator 221 has one input terminal connected to the data strobe signal input / output terminal DQS, and the other input terminal connected to the data strobe signal input / output terminal BDQS. Signal propagation circuit 222 propagates the output signals Int.DQS and Int.BDQS from comparator 221. The output signals Int.DQS and Int.BDQS propagated by signal propagation circuit 222 are clock signals input via the data strobe signal input / output terminals DQS and BDQS. Note that the signal CLK_BDQS is the inverted signal of CLK_DQS. The output signals Int.DQS and Int.BDQS are input to the pointer generation circuit 250 as signals CLK_DQS and CLK_BDQS.

[0108] [Example configuration of input circuit 210] The input circuit 210 comprises a comparator 211 connected to the data signal input / output terminal DQ<7:0> and a circuit element 212 for latching data. The input circuit 210 is provided corresponding to the number of data signal input / output terminals DQ0 to DQ7. The comparator 211 has the same configuration as the input circuit 201 described with reference to Figure 8, with one input terminal connected to one of the data signal input / output terminals DQ0 to DQ7, and a reference voltage VREF supplied to the other input terminal. The circuit element 212 consists of, for example, three latch circuits: an odd latch circuit and an even latch circuit. One latch circuit uses the output signal Int.DQS as a latch enable signal and holds the output signal of the comparator 211 at the rising edge of DQS and the falling edge of BDQS. The remaining two latch circuits use the output signal Int.BDQS as a latch enable signal. At the falling edge of DQS and the rising edge of BDQS, they hold the data from the latch circuits and the output signal of comparator 211, outputting them to the parallel conversion circuit 260 as even data DATA_E<7:0> and odd data DATA_O<7:0>. In this way, the input circuit 210 can convert the 8-bit data input to the data signal input / output terminal DQ<7:0> into 16-bit data and output it to the parallel conversion circuit 260.

[0109] [Example configuration of comparator 231 and signal propagation circuit 232] Comparator 231 has one input terminal connected to control terminal RE and the other input terminal connected to control terminal BRE. Signal propagation circuit 232 propagates the output signal of comparator 231. The output signal propagated by signal propagation circuit 232 is input to data storage area 270.

[0110] [Example configuration of output circuit 240] The output circuit 240 includes a conversion circuit 241 capable of converting 96 bits to 12 bits by holding the input data, a demultiplexer 242, and a comparator 243, and operates when data output is performed. When data output is performed, the data holding unit GFIFO (Global First-in First-out) 271 of the data storage area 270 temporarily holds multiple data transferred from multiple latch circuits XDL and outputs them in the order they were held. The conversion circuit 241 holds, for example, 96-bit data (YRD_E[47:0], YRD_O[47:0]) output by the data holding unit GFIFO 271 of the data storage area 270 as 12-bit data, and also outputs them to the demultiplexer 242. The conversion circuit 241 also functions as an LFIFO (Local First-in First-out). The demultiplexer 242 serially converts 12 bits of data according to the output signal of the comparator 231 and outputs it to the comparator 243. The comparator 243 has the same configuration as the output circuit 202 described with reference to Figure 8, with one input terminal connected to the output terminal of the demultiplexer 242 and the other input terminal connected to the reference voltage VREF. The comparator 243 outputs the data output from the demultiplexer 242 to the data signal input / output terminal DQ<7:0>. In this way, the output circuit 240 can output, for example, 96 bits of data output from the data holding unit GFIFO 271 of the data storage area 270 as 8 bits to the data signal input / output terminal <7:0>.

[0111] [Example configuration of pointer generation circuit 250] The pointer generation circuit 250 (Figure 11) is a circuit for distributing data when performing serial conversion. The pointer generation circuit 250 (Figure 11) includes, for example, a plurality of latch circuits 251(0) to 251(11), a buffer circuit 252, and a signal propagation circuit 253, as shown in Figure 12.

[0112] Multiple latch circuits 251(0) to 251(11) receive the signal CLK_DQS or CLK_BDQS as the latch enable signal, and the signal SELCLK <0> ~SELCLK <11> This is output to the parallel conversion circuit 260. In the example shown in Figure 13, the signal SELCLK corresponds to the latch circuit 251(0). <0> is, time t p1 It rises at the timing of the rising edge of signal CLK_DQS and the falling edge of signal CLK_BDQS, and at time t p2 It rises at the timing of the rising edge of signal CLK_DQS and the falling edge of signal CLK_BDQS. Similarly, the signal SELCLK corresponds to the latch circuit 251(1). <1> is, time t p2 It rises at the timing of the rising edge of signal CLK_DQS and the falling edge of signal CLK_BDQS, and at time t p3 The rising edge and latch circuits 251(2) to 251(11) of the signal CLK_DQS are similar, so their explanation is omitted.

[0113] The buffer circuit 252 receives the signal SELCLK <11> It is connected to the output terminal of a latch circuit 251 that outputs the signal SELCLK, which is output from the latch circuit 251. <11> The signal is delayed and output to the parallel conversion circuit 260 as the signal REFCLK. Note that the signal REFCLK is the same as the signal SELCLK. <0> ~ <11> This is a clock signal used to synchronize the timing for outputting all the data up to that point. In the example shown in Figure 13, the signal REFCLK from buffer circuit 252 and the signal SELCLK from latch circuit 251(11) are used. <11> The time t when output p4 A time t later than p5 It rises at the timing of the rising edge of the CLK_DQS signal and the falling edge of the CLK_BDQS signal. p5 At the timing of the rising edge of the signal REFCLK, the signal SELCLK <0> ~ <11> The data is output to the parallel conversion circuit 260.

[0114] The signal propagation circuit 253 is connected to the output terminal of the buffer circuit 252 and delays the signal REFCLK output from the buffer circuit 252, outputting it as the signal LTC_PLS to the data storage area 270. The signal LTC_PLS is a clock signal used in the data storage area 270. In the example shown in Figure 13, the signal propagation circuit 253 is connected when the buffer circuit 252 outputs the signal REFCLK (at time t p6 ) at the time t p7 The signal LTC_PLS is output to the data storage area 270 at the rising edge of the CLK_DQS signal and the falling edge of the CLK_BDQS signal.

[0115] [Example configuration of parallel conversion circuit 260] The parallel conversion circuit 260 (Figure 11) is a circuit that converts a serial signal into a parallel signal. The parallel conversion circuit 260 includes, for example, a plurality of latch circuits 261(0)<7:0> to 261(11)<7:0> and a plurality of latch circuits 262(0)<7:0> to 262(11)<7:0>, as shown in Figure 14.

[0116] Multiple switches SW are provided at the output terminal of the parallel conversion circuit 260. When these multiple switches SW are ON, the parallel conversion circuit 260 outputs data DATA_PARA_0<7:0> to data DATA_PARA_11<7:0>.

[0117] The latch circuit 261(0)<7:0> uses the signal SELCLK as the latch enable signal. <0> The input signal DATA_E<7:0> is input, and the output signal is output to latch circuit 262(0)<7:0>. Latch circuit 261(1)<7:0> uses the signal SELCLK as the latch enable signal. <1> The input signal DATA_O<7:0> is input, and the output signal is output to latch circuit 262(1)<7:0>. Latch circuit 261(2)<7:0> uses the signal SELCLK as the latch enable signal. <2> The input signal DATA_E<7:0> is input, and the output signal is output to latch circuit 262(2)<7:0>. Latch circuit 261(3)<7:0> uses the signal SELCLK as the latch enable signal. <3> The input signal DATA_O<7:0> is input, and the output signal is output to latch circuit 262(3)<7:0>. Latch circuit 261(11)<7:0> uses the signal SELCLK as the latch enable signal. <11> The input is DATA_O<7:0>, and the data is input as the input signal. The output signal is then output to latch circuit 262(11)<7:0>. Latch circuits 261(4)<7:0>~(10)<7:0> are similar, so their explanation is omitted.

[0118] Latch circuit 262(0)<7:0> receives the signal REFCLK as the latch enable signal, the output of latch circuit 261(0)<7:0> as the input signal, and outputs the data DATA_PARA_0<7:0> as the output signal. Latch circuit 262(1)<7:0> receives the signal REFCLK as the latch enable signal, the output of latch circuit 261(1)<7:0> as the input signal, and outputs the data DATA_PARA_1<7:0> as the output signal. Latch circuit 262(2)<7:0> receives the signal REFCLK as the latch enable signal, the output of latch circuit 261(2)<7:0> as the input signal, and outputs the data DATA_PARA_2<7:0> as the output signal. The latch circuit 262(3)<7:0> receives the signal REFCLK as the latch enable signal, the output of latch circuit 261(3)<7:0> as the input signal, and outputs the data DATA_PARA_3<7:0> as the output signal. The latch circuit 262(11)<7:0> receives the signal REFCLK as the latch enable signal, the output of latch circuit 261(11)<7:0> as the input signal, and outputs the data DATA_PARA_11<7:0> as the output signal. The latch circuits 262(4)<7:0> to (10)<7:0> are similar, so their explanation is omitted. In this way, the parallel conversion circuit 260 can convert, for example, 16-bit data (DATA_O<7:0>, data DATA_E<7:0>) to 96-bit data (data DATA_PARA_0<7:0> to data DATA_PARA_11<7:0>).

[0119] [Example configuration of data storage area 270] The data storage area 270 (Figure 11) comprises a data holding unit GFIFO 271 and a comparator 274. The data holding unit GFIFO 271 also functions as an expected value holding area 272 and an input data holding area 273. The data storage area 270 further comprises a plurality of latch circuits 2701(0) to 2701(3) and AND circuits 2702a and 2702b, as shown in Figure 15B, for example. The comparator 274 may be located outside the data storage area 270.

[0120] Multiple switches SW are provided at the input terminal of the data storage area 270. When these multiple switches SW are in the ON state, data DATA_PARA_0<7:0> to data DATA_PARA_11<7:0> are input to the data storage area 270.

[0121] Multiple latch circuits 2701(0) to 2701(3) receive the signal LTC_PLS as the latch enable signal, and the signal LTC_PLS <0> ~ <3> The AND circuit 2702a, together with multiple latch circuits 2701(0) to 2701(3), constitutes a signal generation circuit. The AND circuit 2702a receives the output signals LTC_IN<3:0> from multiple latch circuits 2701(0) to 2701(3) as input to one input terminal, and the inverted signal of the signal COMP_EN as input to the other input terminal, and outputs the signal LTC_IN_A<3:0> from the output terminal. The signal LTC_IN_A<3:0> is input to the latch circuit in the expected value holding region 272. The AND circuit 2702b, together with multiple latch circuits 2701(0) to 2701(3), constitutes a signal generation circuit. The AND circuit 2702b receives the output signals LTC_IN<3:0> from multiple latch circuits 2701(0) to 2701(3) as inputs to one input terminal, the signal COMP_EN as input to the other input terminal, and outputs the signal LTC_IN_B<3:0> from its output terminal. The signal LTC_IN_B<3:0> is input to the latch circuit in the input data holding area 273.

[0122] As shown in Figure 15A, the data holding unit GFIFO271 includes an even data holding unit 2711_E and an odd data holding unit 2711_O. Each of the even data holding unit 2711_E and the odd data holding unit 2711_O is provided with a 4x12 stage latch circuit 2711, i.e., four latch circuits 2711(0) to 2721(3) for each data DATA_PARA_0<7:0> to DATA_PARA_11<7:0>.

[0123] In the data output (see Figure 21), the even data holding section 2711_E and the odd data holding section 2711_O of the data holding section GFIFO271 output data YRD_E[47:0] and data YRD_O[47:0] to the conversion circuit (LFIFO) 241 of the output circuit 240 (Figure 11), respectively, according to the pointer signal.

[0124] Furthermore, during data training (see Figure 22), the data holding unit GFIFO271 functions as an expected value holding area 272 and an input data holding area 273, as shown in Figure 15B.

[0125] The expected value storage area 272 is one half of the data storage unit GFIFO 271. During data-out operations, the expected value storage area 272 functions as part of the buffer memory. During write data training operations, it stores the expected value data. The expected value storage area 272 is used for the signal LTC_IN_A <0> ~Signal LTC_IN_A <3> The input is received, and the data DATA_PARA_0<7:0> to data DATA_PARA_11<7:0> are input and held as expected values. The expected value holding area 272 outputs the data DOUT_A_0<47:0> to data DOUT_A_7<47:0>. The expected value holding area 272 is equipped with a 4x12 stage latch circuit 2721, that is, four latch circuits 2721(0) to 2721(3) for each of the data DATA_PARA_0<7:0> to data DATA_PARA_11<7:0>.

[0126] The first stage latch circuit 2721(0) uses the signal LTC_IN_A as the latch enable signal. <0> (LTC_IN in the diagram) <0> The input is LTC_IN_A <1> (LTC_IN in the diagram) <1> ) is input, and for example, data DATA_PARA_0<7:0> (data DATA<7:0> in the diagram) is input as the input signal and held. The first stage latch circuit 2721(2) receives the signal LTC_IN_A as the latch enable signal. <2> (LTC_IN in the diagram) <2> ) is input, and for example, data DATA_PARA_0<7:0> (data DATA<7:0> in the diagram) is input as the input signal and held. The first stage latch circuit 2721(3) receives the signal LTC_IN_A as the latch enable signal. <3> (LTC_IN in the diagram) <3> ) is input, and for example, data DATA_PARA_0<7:0> (data DATA<7:0> in the diagram) is input as the input signal and held. The latch circuits 2721(0) to 2721(3) from the 2nd to 12th stages work similarly, so their explanation is omitted.

[0127] The input data holding area 273 is the other half of the data holding unit GFIFO 271. The expected value holding area 272 functions as part of the buffer memory during data output operations. It also holds test data during write data training operations. The input data holding area 273 is used for the signal LTC_IN_B <0> ~Signal LTC_IN_B <3> The input is received, and data DATA_PARA_0<7:0> to data DATA_PARA_11<7:0> are input and held as test data. Input data holding area 273 outputs data DOUT_B_0<47:0> to data DOUT_B_7<47:0>. Input data holding area 27 is provided with a 4x12 stage latch circuit 2731, that is, four latch circuits 2731(0) to 2731(3) for each data DATA_PARA_0<7:0> to data DATA_PARA_11<7:0>.

[0128] The first stage latch circuit 2731(0) uses the signal LTC_IN_B as the latch enable signal. <0> (LTC_IN in the diagram) <0> ) is input, and for example, data DATA_PARA_0<7:0> (data DATA<7:0> in the diagram) is input as the input signal and held. The first stage latch circuit 2731(1) has the signal LTC_IN_B as the latch enable signal. <1> (LTC_IN in the diagram) <1> ) is input, and for example, data DATA_PARA_0<7:0> (data DATA<7:0> in the diagram) is input as the input signal and held. The first stage latch circuit 2731(2) receives the signal LTC_IN_B as the latch enable signal. <2> (LTC_IN in the diagram) <2> ) is input, and for example, data DATA_PARA_0<7:0> (data DATA<7:0> in the diagram) is input as the input signal and held. The first stage latch circuit 2731(3) has the signal LTC_IN_B as the latch enable signal. <3> (LTC_IN in the diagram) <3> ) is input, and for example, data DATA_PARA_0<7:0> (data DATA<7:0> in the diagram) is input as the input signal and held. The latch circuits 2731(0) to 2731(3) from the 2nd to 12th stages work similarly, so their explanation is omitted.

[0129] The latch circuit 2721 included in the expected value holding area 272 and the latch circuit 2731 included in the input data holding area 273 correspond to the latch circuit 2711 included in the data holding unit GFIFO 271. In other words, the expected value holding area 272 and the input data holding area 273 in this embodiment are realized by reusing the configuration of the data holding unit GFIFO 271.

[0130] Comparator 274 compares the expected value data held in the expected value holding area 272 with the data held in the input data holding area 273. Comparator 274 compares the expected value data DOUT_A_0<47:0>~data DOUT_A_7<47:0> output from the expected value holding area 272 with the data DOUT_B_0<47:0>~data DOUT_B_7<47:0> output from the input data holding area 273, and the comparison result is processed by the signal COMP <0> ~Signal COMP <7> It is held as such and output to the PLC SQC.

[0131] The comparator 274 comprises multiple XOR circuits 2741(0)<47:0> to 2741(7)<47:0> and circuit elements 2742(0) to 2742(7).

[0132] XOR circuit 2741(0)<47:0> receives data DOUT_A_0<47:0> at one input terminal and data DOUT_B_0<47:0> at the other input terminal. XOR circuit 2741(7) receives data DOUT_A_7<47:0> at one input terminal and data DOUT_B_7<47:0> at the other input terminal. XOR circuits 2741(1)<47:0> to 2741(6)<47:0> are similar and therefore their explanation is omitted. XOR circuits 2741(0)<47:0> to 2741(7)<47:0> can output a comparison result indicating whether the expected value data and the test data match. Note that XOR circuit 2741(0)<47:0> corresponds to data input via the data signal input / output terminal DQ0. Similarly, the XOR circuits 2741(1)<47:0> to 2741(7)<47:0> correspond to the data input via the data signal input / output terminals DQ1 to DQ7.

[0133] Multiple circuit elements 2742(0) to 2742(7) each include an OR circuit and a latch circuit. The OR circuit in circuit element 2742(0) receives the output signal of the XOR circuit 2741(0)<47:0> and the output signal of the latch circuit in circuit element 2742(0). Therefore, the output signal of this OR circuit is "0" only when the 48-bit data DOUT_A_0<47:0> all match the 48-bit data DOUT_B_0<47:0> and the latch circuit outputs "0", otherwise it is "1". The latch circuit in circuit element 2742(0) holds the output signal of the OR circuit and also COMPs this output signal. <0> The output is sent to the SQC sequencer. Similarly, for circuit elements 2742(1) to 2742(7), the respective signals COMP are also output. <1> ~COMP <7> The signal is output to the PLC SQC. The PLC SQC stores the signal COMP<7:0> as status data Stt in the status register STR.

[0134] [Operation of I / O control circuits] Figure 16 is a schematic timing chart showing the write data training operation. Figure 17 is a diagram showing an example of the comparison results performed in the data storage area 270 according to the first embodiment. Figure 18 is a diagram showing an example of the comparison results performed in the data storage area 270 according to the first embodiment. Figure 19 is a schematic timing chart showing an example of the expected value input method according to the first embodiment.

[0135] In the write data training operation, time t 110In this process, command data "63h" and address data "00h" are sequentially input from the controller die CD to the memory die MD via data signal input / output terminals DQ0 to DQ7. Specifically, data "63h" (01100011) is set to data signal input / output terminals DQ0 to DQ7, the signal of control terminal CLE is set to "H" and the signal of control terminal ALE is set to "L", and the signal of control terminal / WE is raised from "L" to "H". Furthermore, data "00h" (00000000) is set to data signal input / output terminals DQ0 to DQ7, the signal of control terminal CLE is set to "L" and the signal of control terminal ALE is set to "H", and the signal of control terminal / WE is raised from "L" to "H". Command data "63h" is command data Cmd for the write data training operation. Address data "00h" includes the LUN address mentioned above.

[0136] The time t after the command data "00h" was entered. 111 Subsequently, at the timing of the rising or falling edge of the data strobe signal input to the data strobe signal input / output terminal DQS, the expected value data is input from the controller die CD to the memory die MD via the data signal input / output terminal DQ<7:0>. At this timing, since the signal COMP_EN is "L", the sequential pulse signal (signal LTC_IN_A<3:0>) is output only from the AND circuit 2702a<3:0> of the AND circuits 2702a and 2702b (Figure 15B). Therefore, the expected value data is stored in the expected value holding area 272. In this embodiment, the expected value data may contain 8 × 48 (=384) bits of information.

[0137] Next, time t 210 In this configuration, command data "63h" and address data "00h" are sequentially input from the controller die CD to the memory die MD via data signal input / output terminals DQ0 to DQ7.

[0138] The time t after the command data "00h" was entered. 212Subsequently, at the timing of the rising or falling edge of the data strobe signal input to the data strobe signal input / output terminal DQS, test data is input from the controller die CD to the memory die MD via the data signal input / output terminal DQ<7:0>. At this timing, since the signal COMP_EN is "H", only the AND circuit 2702b<3:0> of the AND circuits 2702a and 2702b (Figure 15B) outputs a sequential pulse signal (signal LTC_IN_B<3:0>). Therefore, the expected value data is taken into the input data holding area 273. In this embodiment, the test data may contain 8 × 48 (=384) bits of information.

[0139] When test data is input, a latch enable signal is input to the latch circuits in circuit elements 2742(0) to 2742(7), and the comparison result between the data in the expected value holding area 272 and the data in the input data holding area 273 is output to the sequencer SQC as the signal COMP<7:0>. 212 ~time t 310 If test data is input multiple times during this period, a latch enable signal is input each time data input is completed, and the signal COMP<7:0> is updated. The PLC SQC stores the signal COMP<7:0> as status data Stt in the status register STR.

[0140] Next, time t 310 In this configuration, command data "7xh" and address data "xxh" are sequentially input from the controller die CD to the memory die MD via data signal input / output terminals DQ0 to DQ7. Command data "7xh" is command data Cmd that instructs a status read.

[0141] Next, time t 311 When the signal input to the control terminal RE is pulled down to "L", the status register STR outputs the signal COMP<7:0> as status data Stt.

[0142] The controller die CD can perform a Pass / Fail determination using the acquired comparison results. Figures 17 and 18 show the comparison results obtained by status reading. If the data input via data signal input / output terminals DQ0 to DQ7 is the same as the expected data, "0" is shown to indicate Pass; otherwise, "1" is shown to indicate Fail. Figure 17 shows that all the data input via data signal input / output terminals DQ0 to DQ7 is the same as the expected data. On the other hand, Figure 18 shows that an error occurred in the data input via data signal input / output terminals DQ2 and DQ5 among the data input via data signal input / output terminals DQ0 to DQ7.

[0143] Figure 19 shows the period T in Figure 16. exd An example of the operation of the parallel conversion circuit 260 is shown.

[0144] In the illustrated example, from time t112 to time t113, 8 × 12 (=96) bits of data input to data signal input / output terminals DQ0 to DQ7 are captured by latch circuits 261(0)<7:0> to 261(11)<7:0> over 12 cycles.

[0145] For example, in the illustrated example, when 02h is input to data signal input / output terminals DQ0 to DQ7, Int.DQS and Int.BDQS switch in this state, so the data DATA_E_PRE<7:0> (Figure 11) becomes 02h. Next, when 03h is input to data signal input / output terminals DQ0 to DQ7, Int.DQS and Int.BDQS switch in this state, so even data DATA_E<7:0> becomes 02h and odd data DATA_O<7:0> becomes 03h.

[0146] Next, 04h is input to the data signal input / output terminals DQ0 to DQ7, and in this state Int.DQS and Int.BDQS are switched, so the data DATA_E_PRE<7:0> (Figure 11) is 04h. Next, 05h is input to the data signal input / output terminals DQ0 to DQ7, and in this state Int.DQS and Int.BDQS are switched, so even data DATA_E<7:0> is 04h and odd data DATA_O<7:0> is 05h.

[0147] Furthermore, the SELCLK signal is activated at a timing before the even data DATA_E<7:0> switches to 02h and the odd data DATA_O<7:0> switches to 03h, and before the even data DATA_E<7:0> switches to 04h and the odd data DATA_O<7:0> switches to 05h. <0> The circuit is raised, which causes 02h to be input to latch circuit 261(0)<7:0> (Figure 14) and 03h to latch circuit 261(1)<7:0> (Figure 14).

[0148] Similarly, the signal SELCLK occurs at a timing before the even data DATA_E<7:0> switches to 04h and the odd data DATA_O<7:0> switches to 05h, and before the even data DATA_E<7:0> switches to 06h and the odd data DATA_O<7:0> switches to 07h. <1> The circuit is powered up, which causes 04h to be input to latch circuit 261(2)<7:0> (Figure 14) and 05h to latch circuit 261(3)<7:0> (Figure 14).

[0149] Similarly, 06h to 17h are input to the latch circuits 261(4)<7:0> to 261(11)<7:0>.

[0150] Next, when the signal REFCLK rises at time t114, the data from latch circuits 261(0)<7:0> to 261(11)<7:0> is taken into latch circuits 262(0)<7:0> to 262(11)<7:0>, and data DATA_PARA_0<7:0> to data DATA_PARA_11<7:0> are switched.

[0151] Figures 20 to 22 are schematic circuit diagrams showing example configurations of input / output control circuit I / O. Figure 20 shows the data flow f1 during data input. Figure 21 shows the data flow f2 during data output. Figure 22 shows the data flow f3 during the write data training operation according to the first embodiment.

[0152] When data is input, as shown in Figure 20, for example, 8 bits of data are input via the data signal input / output terminal DQ<7:0>, 16 bits of data are output from the input circuit 210, and input to the parallel conversion circuit 260. 96 bits of data are output from the parallel conversion circuit 260. This data is output to the latch circuit XDL via the bus wiring DB. Note that the switch SW for the data storage area 270 is OFF, and no data is input to the data storage area 270.

[0153] When data is output, as shown in Figure 21, the 96 bits of data output from the latch circuit XDL are stored in the data holding unit GFIFO of the data storage area 270. The data holding unit GFIFO outputs 96 bits of data from the stored data to the output circuit 240. The output circuit 240 outputs 8 bits of data via the data signal input / output terminal DQ<7:0>. Note that the switch SW of the parallel conversion circuit 260 is OFF, and no data is output from the parallel conversion circuit 260.

[0154] During the write data training operation according to the first embodiment, as shown in Figure 22, the data input via the data signal input / output terminal DQ<7:0> is input to the data storage area 270 via the parallel conversion circuit 260. As explained with reference to Figure 16, the expected value data is input to the expected value holding area 272, and the test data is input to the input data holding area 273. Also, as explained with reference to Figure 16, during the write data training operation, the comparator 274 compares the data in the expected value holding area 272 with the data in the input data holding area 273 and outputs the signal COMP<7:0> to the sequencer SQC. The sequencer SQC stores the signal COMP<7:0> received from the comparator 274 in the data storage area 270 as status data Stt in the status register STR.

[0155] [Other data training operations] The data training operation of the semiconductor memory device according to the first embodiment has been described above. However, the data training operation illustrated so far is merely illustrative, and the data training operation can be performed in various ways.

[0156] [Example of applying SCA to write data training operations] In the above description, command data and address data for the write data training operation were input via data signal input / output terminals DQ0 to DQ7. However, in this embodiment, the command data and address data for the write data training operation may also be input via control terminal ALE or control terminal CLE. An operating mode in which command data and address data can be input via control terminal ALE or control terminal CLE, which has a different bus wiring from data signal input / output terminals DQ0 to DQ7, is sometimes referred to as SCA (Separate Command Address input).

[0157] Figure 23 is a schematic timing chart when the write data training operation according to this embodiment is applied to SCA.

[0158] In this modified example, as shown in Figure 23, the start of the write data training operation (time t) start In this process, the command data "63h", the LUN address "LUN" specifying LUN0, and the command data "SCE" are sequentially input from the controller die CD to the memory die MD via the control terminals CLE and ALE. The command data "SCE" is an abbreviation for "Select Chip Enable" and is input at the timing when data input or data output begins.

[0159] After the command data "SCE" is input, as shown in Figure 23, the test data held in the memory die MD is input from the controller die CD to the memory die MD to which LUN0 is assigned via the data signal input / output terminal DQ<7:0>. This executes a data input operation, in which the test data (a data pattern of a predetermined bit length (data D0~Dn) repeated n times) is input to the memory die MD to which LUN0 is assigned via the data signal input / output terminals DQ0~DQ7.

[0160] Furthermore, after the command data "SCE" is input, the command data "63h" and the LUN address "LUN" specifying LUN1 are sequentially input from the controller die CD to the memory die MD via the control terminals CLE and ALE.

[0161] After the LUN address "LUN" specifying LUN1 is entered, the command data "LUN SEL" and the command data "SCT" are sequentially input from the controller die CD to the memory die MD via the control terminals CLE and ALE. The command data "LUN SEL" identifies the memory die MD (in this case, the memory die MD assigned to LUN0) that the next command data (in this case, the command data "SCT") will target. The command data "SCT" is an abbreviation for "Select Chip Terminate" and is entered at the timing when data input or data output is terminated. This terminates data input to the memory die MD assigned to LUN0.

[0162] After the command data "SCT" is input, the command data "LUN SEL" and the command data "SCE" are input from the controller die CD to the memory die MD via the control terminals CLE and ALE. Here, the command data "LUN SEL" identifies and selects the memory die MD (in this case, the memory die MD assigned to LUN1) that the next command data (in this case, the command data "SCE") will target. As a result, the memory die MD assigned to LUN1 is selected.

[0163] After the command data "SCE" is input, as shown in Figure 23, the test data held in the memory die MD is input from the controller die CD to the memory die MD to which LUN1 is assigned via the data signal input / output terminal DQ<7:0>. This executes a data input operation, in which the test data (a data pattern of a predetermined bit length (data D0~Dn) repeated n times) is input to the memory die MD to which LUN1 is assigned via the data signal input / output terminals DQ0~DQ7.

[0164] Furthermore, after the command data "SCE" is input, the command data "LUN SEL" and the command data "7xh" are input from the controller die CD to the memory die MD via the control terminals CLE and ALE. The command data "LUN SEL" here identifies the memory die MD (in this case, the memory die MD assigned to LUN0) that the next command data (in this case, the command data "7xh") will access.

[0165] After the command data "7xh" is input, a status read of the memory die MD assigned to LUN0 is performed, for example. When the status read is performed, the result of comparing the data input to the memory die MD assigned to LUN0 with the expected value held within the memory die MD assigned to LUN0 is output as status data Stt via the control terminals CLE and ALE.

[0166] Furthermore, since the status read of the memory die MD assigned to LUN0 does not go through the data signal input / output terminals DQ0~DQ7, it can be performed in the background (in parallel with the data input) when data is being input to the memory die MD assigned to LUN1.

[0167] After the write data training operation of the memory die MD assigned to LUN0, the command data "LUN SEL" and the command data "7xh" are input from the controller die CD to the memory die MD via the control terminals CLE and ALE. The command data "LUN SEL" here identifies the memory die MD (in this case, the memory die MD assigned to LUN1) that the next command data (in this case, the command data "7xh") will access.

[0168] After the command data "7xh" is input, a status read of the memory die MD assigned to LUN1 is performed, for example. When the status read is performed, the result of comparing the data input to the memory die MD assigned to LUN1 with the expected value held within the memory die MD assigned to LUN1 is output as status data Stt via the control terminals CLE and ALE.

[0169] When the write data training operation according to this embodiment is applied to SCA, the input of command data and acquisition of status data Stt can be performed in the background of the data input, thus further reducing the time overhead caused by the write data training operation.

[0170] [Example of performing a write data training operation simultaneously on multiple memory dies (MD)] The above explanation described an example where, when performing a write data training operation on multiple memory dies MD, one memory die MD is selected at a time, and test data (a data pattern of a predetermined bit length (data D0~Dn) repeated n times) is input each time. However, it is also possible to perform the write data training operation on multiple memory dies MD simultaneously.

[0171] Figure 24 is a schematic timing chart for simultaneously performing write data training operations on multiple memory dies (MDs).

[0172] The write data training operation illustrated in Figure 24 is basically performed in the same way as the write data training operation described with reference to Figure 9.

[0173] However, in the example in Figure 24, the start of the write data training operation (time t) start In this case, the command data "xxh" is entered before the command data "63h". Here, the command data "xxh" is the command data Cmd that instructs the selection of memory die MD corresponding to all LUNs (in this case, LUN0 and LUN1).

[0174] As a result, at time T12, write data training operations will be performed simultaneously for all memory dies MD.

[0175] Furthermore, in the example shown in Figure 24, after the write data training operation is performed, the command data "xxh" is input from the controller die CD to the memory die MD via the data signal input / output terminals DQ0 to DQ7. Here, the command data "xxh" is the command data Cmd which instructs the deselection of all LUNs (in this case, LUN0 and LUN1).

[0176] In the example shown in Figure 24, after the input of command data "xxh", command data "Fnh" and command data "7xh" are sequentially input from the controller die CD to the memory die MD via data signal input / output terminals DQ0 to DQ7. Here, command data "Fnh" is command data Cmd, which selects the memory die MD.

[0177] After the command data "7xh" is entered, a status read of the selected memory die MD is performed. When the status read is performed, the result of comparing the data entered into the memory die MD with the expected value held within the memory die MD is output as status data Stt.

[0178] The input of command data "Fnh" and "7xh," and the output of status data Stt, are executed separately for each memory die MD.

[0179] After status reads of memory die MDs for the number of LUNs (n') have been performed, at time T27, the controller die CD adjusts the skew of the data strobe signal input to the data strobe signal input / output terminal DQS and the data input to the data signal input / output terminal DQ<7:0>, as well as the reference voltage VREF of the memory die MD, according to the comparison results obtained from the status reads.

[0180] [Second Embodiment] In the first embodiment, an example was described in which expected value data is input from the controller die CD to the memory die MD during the write data training operation. However, such operation is merely illustrative, and the specific method can be adjusted as appropriate. For example, the expected value data may be stored inside the memory die MD, or it may be generated inside the memory die MD.

[0181] In the second embodiment, an example is described in which a PRBS (Pseudo-Random Binary Sequence) generation circuit is provided inside the memory die MD, and this is used to generate expected value data inside the memory die MD.

[0182] Figure 25 is a schematic circuit diagram showing a part of the configuration of the input / output control circuit I / O according to the second embodiment. Figure 26 is a schematic circuit diagram showing the configuration of the expectation value generator / comparator 280 according to the second embodiment. Figure 27 is a flowchart showing an example of the write data training operation of the input / output control circuit I / O according to the second embodiment. Figure 28 is a schematic timing chart showing a part of the write data training operation of the input / output control circuit I / O according to the second embodiment. Figure 28 shows the operation of the expectation value generator / comparator 280.

[0183] The input / output control circuit I / O according to the second embodiment is basically configured the same as the input / output control circuit I / O according to the first embodiment. However, the input / output control circuit I / O according to the second embodiment includes an expected value generator / comparator 280, as shown in Figure 25, for example.

[0184] The expectation value generator / comparator 280 is a circuit that generates a data pattern of a predetermined bit length (data D0 to Dn) which will be the data of the expected value, and compares it with a data pattern of a predetermined bit length (data D0 to Dn) input to the input circuit 210 repeated n times. As shown in Figure 26, the expectation value generator / comparator 280 comprises a NOT circuit 2801, a plurality of latch circuits 2802(0) to 2802(7), an XOR circuit 2803, and a comparator 2804.

[0185] The NOT circuit 2801 receives the signal CLK_A, which is the output signal of comparator 221 (Figure 25). The output terminal of NOT circuit 2801 is connected to latch circuits 2802(0) to 2802(7). The output signal of NOT circuit 2801 is input to latch circuits 2802(0) to 2802(7) as a latch enable signal.

[0186] Multiple latch circuits 2802(0) to 2802(7) and XOR circuit 2803 form a PRBS generation circuit. The initial value (seed) of the PRBS generation circuit can be input externally via a special command or set feature to the memory die MD. The first stage latch circuit 2802(0) receives feedback input from the output of the XOR circuit 2803. The output of the fourth stage latch circuit 2802(4) is output to the comparator 2804 as the expected value data NODE_B. The outputs of the seventh stage latch circuit 2802(6) and the eighth stage latch circuit 2802(7) are input to the XOR circuit 2803. The output of the XOR circuit 2803 is output to the comparator 2804 as the expected value data NODE_A.

[0187] In the example shown in Figure 26, the input terminal of the first-stage latch circuit 2802(0) and the output terminal of the fourth-stage latch circuit 2802(4) are connected to the comparator 2804, but this configuration can be adjusted as needed. For example, the input and output terminals of any of the latch circuits 2802(0) to 2802(7) can be connected to the comparator 2804 in accordance with the rules of the predetermined bit length data pattern (data D0 to Dn) input from the input circuit 210.

[0188] Furthermore, the PRBS generation circuit illustrated in Figure 26 includes multiple latch circuits 2802(0) to 2802(7) and an XOR circuit 2803, but such configurations can also be adjusted as appropriate. Any configuration is acceptable as long as a data pattern of a predetermined bit length (data D0 to Dn) is formed with a pseudo-random signal.

[0189] The comparator 2804 comprises an XOR circuit 2804(1), an XOR circuit 2804(2), an OR circuit 2804(3), and a latch circuit 2804(4). The XOR circuit 2804(1) receives data DATA_E and the output of the XOR circuit 2803 as inputs. The XOR circuit 2804(2) receives data DATA_O and the output of the latch circuit 2802(3) as inputs. The OR circuit 2804(3) is a 3-input OR circuit and receives the output of the XOR circuit 2804(1), the output of the XOR circuit 2804(2), and the output of the latch circuit 2804(4) as inputs. The latch circuit 2804(4) receives the signal CLK_A as a latch enable signal, the output of the OR circuit 2804(3) as an input signal, and outputs the signal COMP which indicates the comparison result between the expected data and the input data. In this configuration, if the expected data differs from the input data, the output signal of the OR circuit 2804(3) becomes "H", and this state is held by the latch circuit 2804(4). Furthermore, from this point onward, the signal COMP is fixed at "H".

[0190] Next, the operation of the input / output control circuit I / O according to the second embodiment will be described. For example, as shown in Figure 27, the controller die CD inputs an initial value (seed) using a special command or set feature before executing the write data training operation (S210). Next, the controller die CD executes the write data training operation (S211). Next, the controller die CD performs a status read and reads the signal COMP indicating the comparison result (S212).

[0191] Next, the write data training operation according to this embodiment will be explained using Figure 28.

[0192] In the illustrated example, at time t410, D0h is input to data signal input / output terminals DQ0 to DQ7. In this state, Int.DQS and Int.BDQS switch, so the data DATA_E_PRE<7:0> (Figure 11) is D0h.

[0193] Next, at time t411, D1h is input to data signal input / output terminals DQ0~DQ7. In this state, Int.DQS and Int.BDQS are switched, so even data DATA_E<7:0> becomes D0h and odd data DATA_O<7:0> becomes D1h. Also, as signal CLK_A falls, data R0 is output from the PRBS generation circuit as the expected data NODE_A, and data R1 is output as the expected data NODE_B.

[0194] Next, at time t412, D2h is input to data signal input / output terminals DQ0~DQ7, and in this state Int.DQS and Int.BDQS are switched, so the data DATA_E_PRE<7:0> (Figure 11) is D2h. Also, the signal CLK_A rises, and the output signal of OR circuit 2804(3) is held in latch circuit 2804(4), and this signal is output as signal COMP.

[0195] Next, at time t413, D3h is input to data signal input / output terminals DQ0~DQ7. In this state, Int.DQS and Int.BDQS are switched, so even data DATA_E<7:0> becomes D2h and odd data DATA_O<7:0> becomes D3h. Also, as signal CLK_A falls, data R2 is output from the PRBS generation circuit as the expected value data NODE_A, and data R3 is output as the expected value data NODE_B.

[0196] Similarly, the write data training operation is performed by sequentially switching Int.DQS and Int.BDQS while switching the input data to data signal input / output terminals DQ0 to DQ7.

[0197] [Third Embodiment] The memory die MD according to the second embodiment is equipped with eight expectation value generators / comparators 280 corresponding to eight data signal input / output terminals DQ0 to DQ7. However, this configuration is merely an example, and the specific configuration can be adjusted as appropriate. For example, it is possible to use one expectation value generator / comparator 280 for two or more data signal input / output terminals DQ. This makes it possible to suppress an increase in circuit area.

[0198] Figure 29 is a schematic circuit diagram showing a part of the configuration of the input / output control circuit I / O according to the third embodiment. Figure 30 is a schematic circuit diagram showing the configuration of the expectation value generator / comparator 280b according to the third embodiment.

[0199] The input / output control circuit I / O according to the second embodiment is basically configured the same as the input / output control circuit I / O according to the second embodiment. However, the input / output control circuit I / O according to the second embodiment includes expectation value generators / comparators 280a and 280b instead of the expectation value generator / comparator 280, as shown in Figure 29, for example.

[0200] The expected value generators and comparators 280a and 280b are basically configured in the same way as the expected value generator and comparator 280 according to the second embodiment. However, the expected value generator and comparator 280a is provided in correspondence with data signal input / output terminals DQ4 to DQ7, and the data DATA_E<7:4> and data DATA_O<7:4> corresponding to these terminals are input to it. The expected value generator and comparator 280b is provided in correspondence with data signal input / output terminals DQ0 to DQ3, and the data DATA_E<3:0> and data DATA_O<3:0> corresponding to these terminals are input to it.

[0201] The expected value generator / comparator 280b comprises, for example, a NOT circuit 2801, a PRBS generation circuit 2802b, and a comparator 2804b, as shown in Figure 30.

[0202] The PRBS generation circuit 2802b includes latch circuits 2802(0) to 2802(7), similar to the expected value generation / comparator 280 in the second embodiment. In this embodiment, the output of the XOR circuit 2803 is output to the comparator 2804b as the expected value data NODE_A, and the output of the first-stage latch circuit 2802(0) is output to the comparator 2804b as the expected value data NODE_B. In addition, the output of the second-stage latch circuit 2802(1) is output to the comparator 2804b as the expected value data NODE_C, and the output of the third-stage latch circuit 2802(2) is output to the comparator 2804b as the expected value data NODE_D. Similarly, the output of the fourth-stage latch circuit 2802(3) is output to comparator 2804b as the expected value data NODE_E, the output of the fifth-stage latch circuit 2802(4) is output to comparator 2804b as the expected value data NODE_F, the output of the sixth-stage latch circuit 2802(5) is output to comparator 2804b as the expected value data NODE_G, and the output of the seventh-stage latch circuit 2802(6) is output to comparator 2804b as the expected value data NODE_H.

[0203] The comparator 2804b comprises a plurality of XOR circuits 2804b(1), a plurality of OR circuits 2804b(3), and a plurality of latch circuits 2804b(4).

[0204] In the illustrated example, eight XOR circuits 2804b(1) are provided, corresponding to the 8-bit data DATA_E<3:0> and DATA_O<3:0>. Each XOR circuit 2804b(1) receives one bit from either the 8-bit data DATA_E<3:0> or DATA_O<3:0> and one bit from either the 8-bit data NODE_A to NODE_H as input.

[0205] Furthermore, four OR circuits 2804b(3) are provided, corresponding to the four data signal input / output terminals DQ0 to DQ3. The OR circuit 2804b(3) is a 3-input OR circuit, receiving the output of the XOR circuit 2804b(1) corresponding to any one of the 4-bit data DATA_E<3:0>, the output of the XOR circuit 2804b(1) corresponding to any one of the 4-bit data DATA_O<3:0>, and the output of the latch circuit 2804b(4) as inputs.

[0206] The latch circuit 2804b(4) receives the signal CLK_A as the latch enable signal, and the output of the OR circuit 2804b(3) as the input signal, and the signal COMP indicates the result of comparing the expected value data with the input data. <0> This outputs the expected value data. With this configuration, the comparator 2804b can compare the expected value data with the test data for each DQ.

[0207] The configuration of the expectation value generator / comparator 280a is almost identical to that of the expectation value generator / comparator 280b, so its explanation is omitted.

[0208] Furthermore, to further simplify the outputs of the expectation value generators and comparators 280a and 280b according to the third embodiment, the signals COMP<3:0> and COMP<7:4> output by the expectation value generators and comparators 280a and 280b may be combined into a single bit and stored.

[0209] [Fourth Embodiment] In the embodiments, from the first to the third embodiment, during the write data training operation, the expected data and the test data are compared to check whether a bit error occurred during data reception, thereby confirming the appropriateness of the Skew and the reference voltage of the input circuit 201 (Figure 8). However, such methods are merely illustrative, and specific methods can be adjusted as appropriate.

[0210] In the write data training operation according to the fourth embodiment, a parity bit is added to the data input from the controller die CD to the memory die MD (input / output control circuit I / O) and encoded. After this data is input, the memory die MD calculates whether or not an error has occurred. In the fourth embodiment, an example is described in which a code indicating whether the number of "1"s in the bit sequence is even or odd is added to the data.

[0211] Figures 31 and 32 are diagrams illustrating the write data training operation according to the fourth embodiment. In the example in Figure 31, 8 bits × 11 cycles (= 88 bits) of data are input from the controller die CD to the memory die MD, and in the 12th cycle, 8 bits of data for parity checking are input. In the illustrated example, for the eight data signal input / output terminals DQ0 to DQ7, if the sum of the data input from the 1st to the 11th cycle is even, the parity bit input in the 12th cycle is "0", and if it is odd, the parity bit is "1".

[0212] For example, in the illustrated example, the 11-bit data input from controller die CD to data signal input / output terminal DQ0 is "1,1,0,1,0,0,0,0,0,0,1,0", and the sum is an even number of 4, so the parity bit corresponding to data signal input / output terminal DQ0 is set to "0". On the other hand, the 11-bit data input from controller die CD to data signal input / output terminal DQ3 is "0,1,1,0,1,0,1,0,0,0,1", and the sum is an odd number of 5, so the parity bit corresponding to data signal input / output terminal DQ3 is set to "1".

[0213] Thus, including the parity bit, the sum of the 12 bits of data input to the data signal input / output terminals DQ0 to DQ7 over 12 cycles will each be an even number. Therefore, for example, if you divide the sum of the ones in these 12 bits of data by 2 and the remainder is 1, it indicates that an error has occurred somewhere in the 12 bits of data input to the memory die MD (input / output control circuit I / O).

[0214] For example, in the example shown in Figure 32, the 12-bit data input to the data signal input / output terminal DQ3 contains an error in the 5th cycle. Therefore, dividing the sum of the 12 bits of data by 2 results in a remainder of 1, indicating that an error has occurred.

[0215] Next, the configuration of the input / output control circuit I / O for realizing the write data training operation according to this embodiment will be described.

[0216] Figure 33 is a schematic circuit diagram showing a part of the configuration of the input / output control circuit I / O according to the fourth embodiment. Figure 34 is a schematic circuit diagram showing the configuration of the error determination circuit 290 according to the fourth embodiment.

[0217] The input / output control circuit I / O (Figure 2) according to the fourth embodiment is basically configured the same as the input / output control circuit I / O according to the first embodiment. However, the input / output control circuit I / O according to the fourth embodiment includes an error determination circuit 290, as shown in Figure 33, for example.

[0218] The error detection circuit 290 comprises eight detection circuits corresponding to the eight data signal input / output terminals DQ0 to DQ7. Figure 34 illustrates two of these eight detection circuits: detection circuit 290a corresponding to data signal input / output terminal DQ7, and detection circuit 290b corresponding to data signal input / output terminal DQ0.

[0219] The determination circuit 290a includes XOR circuits 2901a(0) to 2901a(5), 2902a(0) to 2902a(2), 2903a, 2904a, OR circuit 2905a, and latch circuit 2906a.

[0220] The XOR circuit 2901a(0) sends the data DATA_PARA_0 to one of its input terminals. <7> The input is DATA_PARA_1, and the other input terminal receives the data DATA_PARA_1. <7> The following is input. The XOR circuit 2901a(1) sends the data DATA_PARA_2 to one of its input terminals. <7> The input is DATA_PARA_3, and the other input terminal receives the data DATA_PARA_3. <7> The following is input. The XOR circuit 2901a(2) receives the data DATA_PARA_4 at one of its input terminals. <7> The input is DATA_PARA_5, and the other input terminal receives the data DATA_PARA_5. <7> The following is input. The XOR circuit 2901a(3) receives the data DATA_PARA_6 at one of its input terminals. <7> The input is DATA_PARA_7, and the other input terminal receives the data DATA_PARA_7. <7> The following is input. The XOR circuit 2901a(4) receives the data DATA_PARA_8 at one of its input terminals. <7> The input is DATA_PARA_9, and the other input terminal receives the data DATA_PARA_9. <7> The following is input. The XOR circuit 2901a(5) receives the data DATA_PARA_10 at one of its input terminals. <7> The input is DATA_PARA_11, and the other input terminal receives the data DATA_PARA_11. <7> The following is entered.

[0221] XOR circuit 2902a(0) has the output of XOR circuit 2901a(0) input to one input terminal and the output of XOR circuit 2901a(1) input to the other input terminal. XOR circuit 2902a(1) has the output of XOR circuit 2901a(2) input to one input terminal and the output of XOR circuit 2901a(3) input to the other input terminal. XOR circuit 2902a(2) has the output of XOR circuit 2901a(4) input to one input terminal and the output of XOR circuit 2901a(5) input to the other input terminal.

[0222] XOR circuit 2903a has the output of XOR circuit 2902a(1) input to one input terminal and the output of XOR circuit 2902a(2) input to the other input terminal. XOR circuit 2904a has the output of XOR circuit 2902a(0) input to one input terminal and the output of XOR circuit 2903a input to the other input terminal.

[0223] The OR circuit 2905a has the output of the XOR circuit 2904a as input to one input terminal and the output of the latch circuit 2906a as input to the other input terminal. The latch circuit 2906a has the signal LTC_PLS (clock signal) as input as the latch enable signal, the output of the OR circuit 2905a as input as the input signal, and the signal COMP as the output signal. <7> This is output to the SQC sequencer.

[0224] With this configuration, the determination circuit 290a receives the data DATA_PARA_0 <7> ~Data DATA_PARA_11 <7> If the sum of the values ​​is even, the signal COMP outputs "0"; if it is odd, the signal COMP outputs "1". The judgment circuit 290a can also repeatedly perform error detection in units of, for example, 12 bits. If the judgment circuit 290a detects an error even once, the signal COMP is fixed to "1".

[0225] The remaining seven judgment circuits within the error judgment circuit 290, corresponding to the seven data signal input / output terminals DQ0 to DQ6, are configured in the same way as judgment circuit 290a. Therefore, a description of these seven judgment circuits will be omitted.

[0226] [Fifth Embodiment] As described above, the expected value data may be stored in advance inside the memory die MD. An example of this will be described below as the write data training operation according to the fifth embodiment. In the fifth embodiment, multiple expected value data sets are stored in advance on the memory die MD. Furthermore, during the write data training operation, the expected value data is selected by an address signal.

[0227] Figure 35 is a schematic timing chart showing the write data training operation according to the fifth embodiment.

[0228] The write data training operation according to the fifth embodiment is basically performed in the same manner as the write data training operation according to the first embodiment.

[0229] However, as explained with reference to Figure 16, in the write data training operation according to the first embodiment, command data "63h", address data "LUN", and expected value data are input from the controller die CD to the memory die MD.

[0230] On the other hand, as shown in Figure 35, in the write data training operation according to the fifth embodiment, the command data "62h", address data "LUN", and address data "add1", "add2", and "add3" are input from the controller die CD to the memory die MD, thereby selecting one of several expected value data held inside the memory die MD. The address data "add1", "add2", and "add3" are data used to select one expected value data from several expected value data.

[0231] In the example in Figure 16, the data strobe signal input / output terminals DQS and / DQS are used when inputting expected value data. On the other hand, in the example in Figure 35, since no expected value data is input, the data strobe signal input / output terminals DQS and / DQS are not used.

[0232] [Other embodiments] The semiconductor memory devices according to the first to fifth embodiments have been described above. However, the above description is merely illustrative, and the specific configuration and other details can be adjusted as appropriate.

[0233] For example, as explained with reference to Figure 23, the write data training operation according to the first embodiment can be applied to SCA. Similarly, the write data training operations according to the second to fifth embodiments can also be applied to SCA.

[0234] Furthermore, as explained with reference to Figure 24, for example, in the first embodiment, it is possible to simultaneously perform write data training operations on multiple memory dies MD. Similarly, in the write data training operations according to the second to fifth embodiments, it is possible to simultaneously perform write data training operations on multiple memory dies MD.

[0235] [others] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be implemented in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0236] CD...Controller die, Cmd...Command data, / CE,CLE,ALE, / WE, / RE,RE, / WP...Control terminals, Dat...User data, DQ0~DQ7,DQ<7:0>...Data signal input / output terminals, DQS, / DQS(BDQS)...Data strobe signal input / output terminals, MC...Memory cell, MCA...Memory cell array, MD...Memory die, PC...Peripheral circuitry, ADR...Address register, CMR...Command register.

Claims

1. Memory cell array and A first pad electrode receives write data when writing data to the memory cell array is input, and outputs read data when reading data read from the memory cell array is output, A first comparator, in which one input terminal is connected to the first pad electrode and a reference voltage is supplied to the other input terminal, A first latch circuit latches the output signal of the first comparator in accordance with a first latch enable signal, The second pad electrode to which the first latch enable signal is supplied when the aforementioned write data is input, Equipped with, The system is configured to perform a write data training operation when adjusting the time interval between inputting the write data to the first pad electrode and inputting the first latch enable signal to the second pad electrode, and when adjusting the reference voltage. During the aforementioned write data training operation, multiple bits of test data are input via the first pad electrode, and data is generated indicating whether or not a bit error occurred during the input of the test data. The system is configured to output data indicating whether or not the aforementioned bit error occurred. Semiconductor memory device.

2. During the aforementioned data writing training operation, Expected value data is entered, The test data that matches the expected value data is entered once or multiple times. Compare each bit of the expected value data with each bit of the input test data. The semiconductor memory device according to claim 1.

3. When the aforementioned write data is input, a parallel conversion circuit performs serial-to-parallel conversion on the write data output from the first latch circuit and outputs it to the memory cell array via the data bus. When outputting the read data, a plurality of second latch circuits latch the signal of each bit of the data bus in accordance with the second latch enable signal, A first signal generation circuit that, upon input of the expected value data, outputs the second latch enable signal to only a portion of the plurality of second latch circuits, A second signal generation circuit that, upon input of the test data, outputs the second latch enable signal to only a portion of the plurality of second latch circuits, A comparator that compares some of the data from the plurality of second latch circuits with other parts of the data from the plurality of second latch circuits. The semiconductor memory device according to claim 2, further comprising the above.

4. The aforementioned comparator is A plurality of exclusive OR output circuits, one of which has an input terminal connected to one of the parts of the plurality of second latch circuits, and the other input terminal connected to one of the other parts of the plurality of second latch circuits, A logic OR output circuit that receives the output signals of the plurality of exclusive OR output circuits and data indicating whether or not the bit error occurred and outputs a logic OR, A third latch circuit latches the output signal of the OR output circuit and outputs it as data indicating whether or not the bit error occurred. A semiconductor memory device according to claim 3, comprising:

5. It also includes an expectation value generator and comparator that generates expected value data, During the aforementioned data writing training operation, The test data that matches the expected value data is entered once or multiple times. Compare each bit of the expected value data with each bit of the input test data. The semiconductor memory device according to claim 1.

6. The aforementioned expectation value generator and comparator is, During the aforementioned write data training operation, an expected value data generation unit generates the expected value data based on the initial value, A first exclusive OR output circuit, in which one input terminal is connected to the first latch circuit and the other input terminal is connected to the expected value data generation unit, A first OR output circuit that takes the output signal of the first exclusive OR output circuit and data indicating whether or not the bit error occurred as input and outputs a logical OR, A third latch circuit latches the output signal of the first OR output circuit and outputs data indicating whether or not the bit error occurred. The semiconductor memory device according to claim 5, comprising:

7. A third pad electrode receives the write data when writing data to the memory cell array is input, and outputs the read data when reading data read from the memory cell array is output, A second comparator, to which one input terminal is connected to the third pad electrode and the reference voltage is supplied to the other input terminal, A fourth latch circuit latches the output signal of the second comparator in accordance with the first latch enable signal. Furthermore, The aforementioned expectation value generator and comparator is, A second exclusive OR output circuit, in which one input terminal is connected to the fourth latch circuit and the other input terminal is connected to the expected value data generation unit, A second OR output circuit that takes the output signal of the second exclusive OR output circuit and data corresponding to the third pad electrode as input and outputs an OR, A fifth latch circuit latches the output signal of the second OR output circuit and outputs it as data corresponding to the third pad electrode. The semiconductor memory device according to claim 6, further comprising the above.

8. During the aforementioned data writing training operation, Address data specifying the expected value data is entered. The test data that matches the expected value data is entered once or multiple times. Compare each bit of the expected value data with each bit of the input test data. The semiconductor memory device according to claim 1.

9. During the aforementioned data writing training operation, The test data, including the parity bit, is input once or multiple times. By performing a parity check, data is generated indicating whether or not a bit error occurred during the input of the test data. The semiconductor memory device according to claim 1.

10. When the aforementioned write data is input, a parallel conversion circuit performs serial-to-parallel conversion on the write data output from the first latch circuit and outputs it to the memory cell array via the data bus. A logic circuit that outputs "1" if the "1" signal among the signals of each bit of the data bus is even, and outputs "0" if it is odd, A first OR output circuit that takes the output signal of the logic circuit and data indicating whether or not the bit error occurred as input and outputs a logical OR, A third latch circuit latches the output signal of the first OR output circuit and outputs data indicating whether or not the bit error occurred. A semiconductor memory device according to claim 9, comprising:

11. Multiple semiconductor memory devices, A controller connected to the plurality of semiconductor storage devices Equipped with, The aforementioned plurality of semiconductor memory devices are Memory cell array and A first pad electrode receives write data when writing data to the memory cell array is input, and outputs read data when reading data read from the memory cell array is output, A first comparator, in which one input terminal is connected to the first pad electrode and a reference voltage is supplied to the other input terminal, A first latch circuit latches the output signal of the first comparator in accordance with a first latch enable signal, The second pad electrode to which the first latch enable signal is supplied when the aforementioned write data is input, Equipped with, The system is configured to perform a write data training operation when adjusting the time interval between inputting the write data to the first pad electrode and inputting the first latch enable signal to the second pad electrode, and when adjusting the reference voltage. During the aforementioned data writing training operation, The controller inputs multiple bits of test data to the semiconductor memory device via the first pad electrode. The semiconductor memory device generates data indicating whether or not a bit error occurred when inputting the test data. The semiconductor memory device is configured to output data indicating whether or not the bit error occurred. Memory system.

12. During the aforementioned write data training operation, the controller: The test data of multiple bits is input simultaneously to the aforementioned multiple semiconductor memory devices. The plurality of semiconductor memory devices are individually outputting data indicating whether or not the bit error occurred. The memory system according to claim 11.

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