Indication device

Abstract

To provide semiconductor devices that are highly reliable and enable narrow bezel designs. [Solution] The drive circuit has a first transistor having a first gate and a second gate electrically connected with a semiconductor film in between, and a second transistor whose source and drain are electrically connected to one of the source and drain of the first transistor, and the pixel part has a third transistor, a liquid crystal element and a capacitive element, and the liquid crystal element has a light-transmitting first conductive film electrically connected to one of the source and drain of the third transistor, and a second conductive film The capacitor element has a liquid crystal layer to which an electric field is applied between a first conductive film and a second conductive film, and the capacitor element has a first conductive film, a light-transmitting third conductive film, and a nitride insulating film located between the first conductive film and the third conductive film, the nitride insulating film located between the semiconductor film of the first transistor and the second gate.

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device. In particular, the present invention relates to a sequential circuit using a unipolar transistor. This relates to semiconductor devices such as semiconductor display devices that use the above-mentioned sequential circuits. [Background technology]

[0002] Semiconductor display devices such as liquid crystal displays and electroluminescent displays used in portable electronic devices are Therefore, it is required to narrow the area outside the pixel area (narrow the bezel). Part of the driving circuit Alternatively, a system-on-panel that fabricates everything on the same substrate as the pixel area satisfies the above requirements. This is effective. And, in the case of a system-on-panel setup, the drive circuit is unipolar, similar to the pixel unit. Using transistors would reduce the cost required to manufacture the panel, so it is desirable. It seems so. Patent documents 1 and 2 below describe the driving circuits of semiconductor display devices. A technology that constructs various circuits such as inverters and shift registers using unipolar transistors. This information has been disclosed. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2001-325798 [Patent Document 2] Japanese Patent Publication No. 2010-277652 [Overview of the Initiative] [Problems that the invention aims to solve]

[0004] By the way, in a liquid crystal display device, which is a type of semiconductor device, in the case of a transmissive type, the region through which light is transmitted Increasing the ratio of pixels to aperture ratio allows for more effective use of light emitted from the backlight. Because it can be used, power consumption can be reduced. However, improving the aperture ratio If we prioritize the pixel layout, then the transistors and capacitances that make up the pixels will be considered. The size of semiconductor elements such as components will also have to be reduced. The capacitance value of capacitive elements will decrease. This makes it difficult to control the orientation of liquid crystal molecules without reducing the driving frequency, affecting the image signal. This can lead to problems such as a shorter duration for maintaining position, resulting in a decrease in the displayed image quality. .

[0005] Furthermore, semiconductor display devices are required to have even narrower bezels. In addition, unipolar transients In the drive circuit of a semiconductor display device having a sta, the sequential circuit that outputs a pulsed signal In some cases, degradation of electrical characteristics such as threshold voltage shifts may be observed in transistors. Furthermore, semiconductor display devices are required to ensure reliability.

[0006] Given the technical background described above, one aspect of the present invention suppresses the degradation of image quality while reducing power consumption One of the objectives is to provide a semiconductor device that can reduce [a certain value]. Alternatively, one aspect of the present invention One of their challenges is to provide semiconductor devices that are highly reliable and can achieve a narrow bezel design. [Means for solving the problem]

[0007] A semiconductor device according to one aspect of the present invention is conductive and transparent to visible light. A metal oxide film having a visible light-transmitting pixel electrode and the metal oxide film A capacitive element having at least a nitride insulating film provided between the above-mentioned pixel electrodes is provided in the pixel In the above configuration, the capacitive element will be transparent to visible light. Therefore, Because it is possible to increase the pixel aperture ratio while securing the necessary capacity to obtain high image quality, the panel This allows for minimizing light loss within the device, thereby reducing the power consumption of semiconductor devices. It is possible.

[0008] Furthermore, as described above, a metal oxide film and a pixel electrode are used as a pair of electrodes in a capacitive element. In this case, to increase the capacitance value of the capacitive element, a resin film such as acrylic is used with the metal oxide film and the pixel electrode. It is preferable not to provide it in between. However, if a resin film is not provided, the side furthest from the gate electrode The region near the surface of the semiconductor film (back channel region) and the element in which the transistor is formed The distance to the surface of the sub-substrate becomes shorter compared to when a resin film is provided. Therefore, the element When moisture from the atmosphere adheres to the surface of the substrate, a positive fixed charge is generated near that surface. Consequently, the fixed charge mentioned above makes it easier for a negative charge to be generated in the back channel region. Therefore, there is a period during which the potential of the gate electrode is low relative to the source electrode or drain electrode. It has been empirically observed that the longer the transistor, the more likely the threshold voltage is to shift in the negative direction. Although it has been shown, the threshold voltage is lower in the absence of the resin film compared to the case where the resin film is provided. It was found that the shift towards the eggplant direction tends to be particularly large.

[0009] Therefore, in one aspect of the present invention, the sequential circuits and buffers included in the drive circuit have a trace Among transistors, those whose threshold voltage tends to shift in the negative direction are typically used in gaming. In addition to the gate electrode, the semiconductor film also has a gate electrode on the back channel region side. Then, the gate electrode on the back channel region side is electrically connected to the normal gate electrode. Let's assume they exist.

[0010] By placing the gate electrode on the back channel region side, negative current is supplied to the back channel region. This prevents the generation of load and suppresses the transistor's threshold voltage from shifting in the negative direction. This is possible. Also, instead of applying a constant potential to the gate electrode on the back channel region side, By electrically connecting the gate electrode to a normal gate electrode, the pair of gate electrodes are given the same potential. By providing this, the channel formation region can be increased, and the drain current can be increased. Therefore, it is possible to keep the size of the transistor small while suppressing the decrease in on-current. This allows the area of ​​the drive circuit to be kept small. [Effects of the Invention]

[0011] According to one aspect of the present invention, a semiconductor can reduce power consumption while suppressing a decrease in image quality. An apparatus can be provided. Alternatively, according to one aspect of the present invention, a highly reliable, narrow-bezel device can be provided. A semiconductor device can be provided. [Brief explanation of the drawing]

[0012] [Figure 1] A diagram showing the configuration of a sequential circuit. [Figure 2] A diagram showing the configuration of a transistor. [Figure 3] Timing chart. [Figure 4] Top view of a pixel. [Figure 5] Cross-sectional view of a pixel. [Figure 6] A diagram showing the configuration of a semiconductor display device. [Figure 7] A diagram showing the configuration of a sequential circuit. [Figure 8] A diagram showing the configuration of a shift register. [Figure 9] A diagram showing the buffer configuration. [Figure 10] A diagram showing the buffer configuration. [Figure 11] A diagram showing the method for manufacturing the element substrate. [Figure 12] A diagram showing the method for manufacturing the element substrate. [Figure 13] A diagram showing the method for manufacturing the element substrate. [Figure 14] A diagram showing the method for manufacturing the element substrate. [Figure 15] Top view of a liquid crystal display device. [Figure 16] Cross-sectional view of a liquid crystal display device. [Figure 17] A diagram showing the electrical characteristics of a transistor. [Figure 18] A diagram of an electronic device. [Figure 19] A diagram showing the configuration of a transistor. [Figure 20] A diagram showing the configuration of a transistor. [Figure 21] A diagram showing the configuration of a transistor. [Figure 22] A diagram showing circuit symbols and the configuration of transistors. [Figure 23] A diagram showing the cross-sectional structure of a transistor. [Figure 24] A diagram showing the configuration of a transistor. [Figure 25] Cross-sectional view of a transistor at the edge of an oxide semiconductor film. [Figure 26] Vg-Id characteristics of a transistor according to an embodiment. [Figure 27] Vg-Id characteristics of a transistor according to an embodiment. [Figure 28] Vg-Id characteristics of a transistor according to an embodiment. [Figure 29] A diagram illustrating the structure of the transistor used in the calculations and the resulting field-effect mobility and on-current. [Figure 30] A diagram illustrating the transistor model used in the calculations. [Figure 31] A diagram illustrating the channel length dependence of the saturation mobility obtained by calculation. [Figure 32]A diagram illustrating the channel length dependence of the on-current obtained by calculation. [Figure 33] A diagram illustrating the Vg-Id characteristics of a transistor and the current distribution in an oxide semiconductor film, obtained through calculations. [Figure 34] A diagram illustrating the Vg-Id characteristics of the transistor and the current distribution in the silicon film obtained by calculation. [Figure 35] A diagram illustrating the electron trap used in the calculation and the channel length dependence of the saturation mobility obtained from the calculation. [Figure 36] A diagram illustrating the carrier flow in the off and on states of a transistor. [Modes for carrying out the invention]

[0013] The embodiments of the present invention will be described in detail below with reference to the drawings. However, the present invention is... Not limited to the following description, the present invention may have forms and characteristics that do not depart from the spirit and scope of the invention. Those skilled in the art will readily understand that the details can be modified in various ways. Therefore, the present invention This shall not be interpreted as being limited to the contents of the embodiments described below.

[0014] Furthermore, the present invention relates to integrated circuits, RF tags, semiconductor display devices, and other devices that utilize transistors. This category includes all kinds of semiconductor devices. Note that integrated circuits include microprocessors, image processors, etc. Circuitry, DSP (Digital Signal Processor), Microcontroller LSI (Large Scale Integrated Circuit) including Trolla t), FPGA (Field Programmable Gate Array) and C Programmable logic circuits such as PLDs (Complex PLDs) (PLD: Progr Amplifiable Logic Devices (AMMABLE Logic Devices) fall into this category. Also, semiconductor tables... The display device includes a liquid crystal display device and a light-emitting device with light-emitting elements, such as organic light-emitting elements, in each pixel. Electronic paper, DMD (Digital Micromirror Device) , PDP (Plasma Display Panel), FED (Field Emi It has circuit elements using semiconductor films in its driving circuit, such as a ssion display. Semiconductor display devices fall into that category.

[0015] In this specification, a semiconductor display device refers to a device in which display elements such as liquid crystal elements and light-emitting elements each screen. A panel formed in its raw state, and a model in which an IC including a controller is mounted on the panel. This includes joules. Furthermore, a semiconductor display device according to one aspect of the present invention is said In the process of manufacturing semiconductor display devices, an element that corresponds to one form before the display element is completed. This category includes substrates, and such element substrates include transistors and pixel elements used in display elements. Each of the multiple pixels is equipped with electrodes, such as poles or common electrodes, and capacitive elements.

[0016] Furthermore, a semiconductor display device according to one aspect of the present invention includes a finger or stylus that points to something. A position input device that can detect a position and generate a signal containing that position information. Chipanel may be included as a component.

[0017] Furthermore, in this specification, "connection" means an electrical connection, and current, voltage, or potential is This corresponds to a state where it can be supplied or transmitted. Therefore, a connected state is a state where it is directly connected. It does not necessarily refer to a state in which current, voltage, or potential is available or To enable transmission, circuit elements such as wiring, resistors, diodes, and transistors are used. This category also includes situations where components are indirectly connected. Furthermore, components that appear independent on the circuit diagram are also included. Even when elements are connected to each other, in reality, for example, a part of the wiring acts as an electrode. In some cases, such as when it is possible, a single conductive film may possess the functions of multiple components. In the specification, connection means that one conductive film combines the functions of multiple components. Cases where this is the case are also included in that category.

[0018] Furthermore, the source of a transistor is the source region, which is a part of the semiconductor film that functions as the active layer. This refers to the region, or the source electrode connected to the semiconductor film mentioned above. Similarly, the transistor's Rain refers to a drain region which is part of the semiconductor film, or a region connected to the semiconductor film. It refers to the drain electrode. Similarly, "gate" refers to the gate electrode.

[0019] The source and drain of a transistor are provided to the transistor's conductivity type and each terminal. The name changes depending on the potential level. Generally, n-channel transistors In this case, the terminal to which a low potential is applied is called the source, and the terminal to which a high potential is applied is called the slave. It is called a p-channel transistor. Also, in a p-channel transistor, the terminal to which a low potential is applied is called a dove. The terminal to which a high potential is applied is called the source. For convenience, in this specification, Assuming the source and drain are fixed, the connection relationships of the transistor will be explained. In some cases, the terms "source" and "drain" are reversed according to the potential relationship described above. ru.

[0020] <Example of a sequential circuit configuration 1> Figure 1(A) shows an example of the configuration of a sequential circuit according to one aspect of the present invention. The sequential circuit 10 shown comprises circuit 11, transistor 12, and transistor 13. Circuit 11 controls the gate and transistor 12 according to the potentials of signals LIN and RIN. It has the function of controlling the gate potential of the transistor 13.

[0021] Transistor 12 is connected to a wiring to which a signal Sig or a high-level potential VDD is applied, and output It has a function to control the electrical connection with the power terminal OUT. Also, transistor 13 is Controls the electrical connection between the wiring to which a certain level of potential VSS is applied and the output terminal OUT. It has the function of transmitting a signal Sig. Specifically, one of the source and drain of transistor 12 transmits a signal Sig. Alternatively, it is connected to a wire to which a high-level potential VDD is applied, and transistor 13 One of the source and drain is connected to wiring to which a low potential VSS is applied. The signal Sig is a clock signal, which is the ratio of pulse width to pulse period. A signal with a utility ratio of approximately 0.5 can be used. Also, the source of transistor 12 The other side of the drain and the other side of the source and drain of transistor 13 are connected to output terminal OU T is connected.

[0022] Circuit 11 causes the gate potential of transistor 12 and the gate potential of transistor 13 to be By being controlled, the conduction or non-conductivity of transistor 12 is selected, and transistor 13 Conduction or non-conductivity is selected. And when transistor 12 is in a conducting state, When the generator 13 is in a non-conductive state, the wiring to which the signal Sig or potential VDD is applied is connected to the output The power terminal OUT is connected. Also, transistor 12 is in a non-conductive state, and the transistor When terminal 13 is in a conductive state, the wiring to which the potential VSS is applied is connected to the output terminal OUT. It can be done.

[0023] Furthermore, the output signal, including the potential of the output terminal OUT of the sequential circuit 10, is connected to multiple pixels. When supplying to a wiring called a bus line, such as a scan line, the duty cycle of the above output signal The ratio is significantly smaller than that of the clock signal, etc. In this case, transistor 12 is the output signal Because it is continuously in a non-conductive state during periods other than the pulse of the number, transistor 12 is non-conductive. The period during which the transistor 13 is in a conductive state is significantly longer than the period during which it is in a non-conductive state. Then, one of the source and drain of transistor 12 is connected to a signal Sig or a potential VD. Since D is given, transistor 12 has a value relative to either the source or the drain. The period during which the potential of the terminal is low is longer compared to transistor 13, and the threshold voltage is negative. It can be seen that it is easy to shift in the S direction.

[0024] Therefore, in one aspect of the present invention, the transistor 12 is electrically connected and is a semiconductor It shall have a pair of gate electrodes that overlap with a membrane in between. They are electrically connected. By providing a pair of gate electrodes on the transistor 12, a positive electrode is placed near the surface of the element substrate. Even if fixed charges are generated, these fixed charges will cause negative charges to be generated near the surface of the semiconductor film. This prevents the threshold voltage of transistor 12 from shifting in the negative direction. Therefore, the reliability of the sequential circuit 10, and by extension the semiconductor device using the sequential circuit 10, can be improved. It is possible.

[0025] Furthermore, by electrically connecting a pair of gate electrodes, one gate electrode can be electrically connected to only one of the pair. Unlike when a constant potential is applied, the same potential is applied to the pair of gate electrodes, so The Nellum formation region increases, which makes it possible to increase the drain current of transistor 12. Therefore, the size of transistor 12 can be kept small while suppressing the decrease in on-current. Therefore, the area of ​​the sequential circuit 10, and by extension the drive circuit using the sequential circuit 10, can be kept small. This is possible. In particular, the transistor 12 provided on the output side of the sequential circuit 10 is connected to the circuit 11 Because a larger current supply capacity is required than that of the transistors used, transistor 1 Since 2 has the pair of gate electrodes described above, other transistors in the sequential circuit 10 Compared to applying the same configuration to the other system, the area of ​​the sequential or drive circuit can be kept smaller. It can be said that the effect is significant.

[0026] Furthermore, by providing a pair of electrically connected gate electrodes, a depletion layer is not formed in the semiconductor film. Because the value is reduced, the S value (subthreshold value) of transistor 12 can be improved. ru.

[0027] Next, Figure 1(B) shows a more detailed example of the sequential circuit 10 shown in Figure 1(A). The sequential circuit 10 shown in 1(B) is the same as the sequential circuit 10 shown in Figure 1(A), and is connected to circuit 11. It has transistor 12 and transistor 13. And in Figure 1(B), circuit 1 This example illustrates the case where 1 has transistors 14 to 17.

[0028] Transistor 14 is selected to conduct or not conduct according to the potential of the signal LIN. When transistor 14 is in a conducting state, the wiring to which the potential VDD is applied and transistor 12 The gate is electrically connected. Transistor 15 conducts according to the potential of the signal RIN. Alternatively, non-conductivity is selected. When transistor 15 is in a conducting state, the potential VDD is given The wiring is electrically connected to the gate of transistor 13. Transistor 16 is Conduction or non-conductivity is selected according to the potential of the signal RIN. Transistor 16 is in the conducting state. When this is the case, the wiring to which the potential VSS is applied and the gate of transistor 12 are electrically connected. The transistor 17 is selected to conduct or not conduct according to the potential of the signal LIN. When transistor 17 is in a conducting state, the wiring to which the potential VSS is applied and the transistor The gate of station 13 is electrically connected to it.

[0029] Regarding the operation example of the sequential circuit 10 shown in Figure 1(B), the source and slave of transistor 12 Let's take the example of a case where one end of the wire is connected to a wire to which a signal Sig is supplied. Furthermore, Figure 3 illustrates the timing chart of the sequential circuit 10 shown in Figure 1(B). However, In Figure 3, the case where transistors 12 to 17 are all n-channel type An example of an timing chart is shown. Also, in Figure 3, the gate of transistor 12 is shown as a node. This is shown as α.

[0030] As shown in Figure 3, during period T1, the potential of signal Sig is low, and the potential of signal LIN is The signal RIN is at a high level, and its potential is low. Therefore, during period T1, the transient Transistor 14 and transistor 17 become conductive, and transistors 15 and 16 This becomes a non-conductive state. Therefore, at node α, the threshold voltage of transistor 14 is from the potential VDD. A potential drop equal to the pressure is applied. Also, the gate of transistor 13 has a potential VSS. As a result, transistor 13 becomes non-conductive.

[0031] Next, as shown in Figure 3, during period T2, the potential of signal Sig is high, and signal LIN The potential of is low, and the potential of signal RIN is also low. Therefore, during period T2, Because transistors 14 through 17 become non-conductive, node α becomes floating. This results in a state of ping. Therefore, the parasitic capacitance added to node α is the source of transistor 12. In the ideal state, where the capacitance formed between the gate is significantly smaller than the period T1, The change in the potential of the signal Sig that occurred during period T2, i.e., the low level of the signal Sig. The potential of node α rises by the potential difference between the potential of the node and the high-level potential. When the potential of α increases, the gate voltage of transistor 12 becomes sufficiently higher than its threshold voltage. Therefore, a high-level potential of the signal Sig is applied to the output terminal OUT.

[0032] The potential increase at node α is determined by the parasitic capacitance added to node α and the potential of transistor 14. It changes depending on the capacitance ratio with respect to the capacitance C formed between the source and the gate. In other words, no The smaller the parasitic capacitance attached to node α is compared to capacitance C, the greater the increase in potential at node α. The greater the parasitic capacitance attached to node α compared to capacitance C, the higher the potential of node α. The width is small. Therefore, the gate voltage of transistor 12 becomes sufficiently higher than its threshold voltage. To such an extent that the potential of node α rises, a shape is formed between the source and gate of transistor 14. It is desirable to make the resulting capacity C larger than the parasitic capacity attached to node α.

[0033] Next, as shown in Figure 3, during period T3, the potential of signal Sig is low, signal LIN The potential of is low, and the potential of signal RIN is high. Therefore, during period T3, Transistors 14 and 17 become non-conductive, and transistors 15 and 17 become non-conductive. The converter 16 becomes conductive. Therefore, the potential VSS is applied to node α, Transistor 12 becomes non-conductive. Also, the gate of transistor 13 has a potential VDD. Because of this, transistor 13 becomes a conduction. Therefore, the potential VSS becomes the output. It is supplied to terminal OUT.

[0034] Next, as shown in Figure 3, during period T4, the potential of signal Sig is high, and signal LIN The potential of is low, and the potential of signal RIN is also low. Therefore, during period T4, Transistors 14 through 17 become non-conductive. Therefore, transistor 12 The other component remains in a non-conductive state, while transistor 13 remains in a conductive state. Therefore, the potential VSS However, this is applied to the output terminal OUT.

[0035] As a result of the operation during the above periods T1 to T4, the output terminal OUT of the sequential circuit 10 will be: An output signal with pulses is output. Note that the potential of the output terminal OUT of the sequential circuit 10 is included. The output signal is transmitted to a bus line, a wiring system connected to multiple pixels, such as a scan line. When supplied, transistors 14 through 17, similar to transistor 12, The period during which the gate potential is lower than that of either the source or the drain is called a transient. Compared to the Ta13, it is longer, and it can be seen that the threshold voltage tends to shift in the negative direction.

[0036] Therefore, in one aspect of the present invention, at least one of transistors 14 to 17 However, a pair of gate electrodes are electrically connected and overlapping with a semiconductor film in between. It may have. In Figure 1(B), transistors 14 to 17 are electrically This illustrates the case where there is a pair of gate electrodes that are electrically connected. By providing the gate electrode of transistor 14 to transistor 17, transistor 1 This can prevent the threshold voltage of transistor 4 to transistor 17 from shifting in the negative direction. Therefore, the reliability of the sequential circuit 10, and by extension the semiconductor device using the sequential circuit 10, can be improved. It is possible.

[0037] Furthermore, the size of transistors 14 to 17 can be reduced while suppressing the decrease in on-current. Since it can be suppressed, the aspect of the sequential circuit 10, and by extension the drive circuit using the sequential circuit 10 The product can be kept small.

[0038] Furthermore, by providing a pair of electrically connected gate electrodes, a depletion layer is not formed in the semiconductor film. Because the value is reduced, the S value of transistors 14 to 17 can be improved.

[0039] <Example of transistor configuration> Next, as shown in Figure 1, transistors 12, 14, and 17 A transistor 20 having an electrically connected pair of gate electrodes can be used. A specific configuration example is shown in Figure 2. Figure 2(A) shows a top view of transistor 20. Oh, in Figure 2(A), in order to clarify the layout of transistor 20, the gate insulating film is shown. Various insulating films such as those shown have been omitted. Also, in the top view shown in Figure 2(A), the dashed line A1-A A cross-sectional view at point 2 is shown in Figure 2(B), and a cross-sectional view at the dashed line A3-A4 is shown in Figure 2(C). vinegar.

[0040] As shown in Figure 2, the transistor 20 has a gate electrode and a substrate 31 having an insulating surface. A conductive film 21 having the function of a gate insulating film, and a conductive film 2 having the function of a gate insulating film. An insulating film 22 located on 1, and an oxide semiconductor film overlapping the conductive film 21 on the insulating film 22. 23 is electrically connected to the oxide semiconductor film 23 and serves as either a source electrode or a drain electrode. It has conductive films 24 and 25 that have the function of a conductive film.

[0041] Furthermore, in Figure 2, an insulating film 26 and The insulating film 27 is arranged in a stacked manner. The transistor 20 is connected to the insulating film 26 and The insulating film 27 may also be included as a component. In Figure 2, the insulating films are stacked in order. Although film 26 and insulating film 27 are shown as examples, a single layer can be used instead of insulating film 26 and insulating film 27. An insulating film may be used, or three or more layers of insulating films may be used. .

[0042] Furthermore, a nitride insulating film 28 and an insulating film 29 are sequentially laminated on insulating films 26 and 27. It is provided in such a way. The insulating film 29 does not necessarily need to be provided. However, the insulating film 2 9, together with the nitride insulating film 28, functions as a dielectric film for the pixel's capacitive element, which will be described later. Nitride insulating film 28 has a higher dielectric constant than oxide insulating films such as silicon oxide, and internally... It tends to have a large force. Therefore, instead of using the insulating film 29 as the dielectric film of the capacitive element, nitrogen When only the nitride insulating film 28 is used, if the thickness of the nitride insulating film 28 is small, the capacitance value of the capacitive element The size becomes too large, and the speed of writing image signals to pixels is increased with low power consumption. This becomes difficult. Conversely, if the film thickness of the nitride insulating film 28 is large, the internal stress increases. As a result, the threshold voltage of the transistor shifts, and semiconductor elements formed using semiconductor films... This could lead to a deterioration in the characteristics of the child. Also, the internal stress of the nitride insulating film 28 could become too large. This makes the nitride insulating film 28 more likely to peel off from the substrate 31, hindering the improvement of yield. Furthermore, an insulating film 29 made of an insulator such as silicon oxide, which has a lower dielectric constant than the nitride insulating film 28, is used. By using it together with the nitride insulating film 28 as a dielectric film for the pixel's capacitive element, the dielectric film The dielectric constant can be adjusted to a desired value without increasing the thickness of the nitride insulating film 28. ru.

[0043] Insulating film 22, insulating film 26, insulating film 27, nitride insulating film 28, and insulating film 29 are located at the opening 3 It has 2. The opening 32 is different from the oxide semiconductor film 23, conductive film 24 and conductive film 25. It is provided in a region that overlaps with the conductive film 21.

[0044] Furthermore, the transistor 20 has a conductive film 30 that functions as a gate electrode, and an insulating film 29 Conductive film is provided on top of, or on the nitride insulating film 28 if the insulating film 29 is not provided. 30 is provided in a position that overlaps with the conductive film 21 and the oxide semiconductor film 23. Therefore, The transistor 20 is electrically connected and is a semiconductor film, an oxide semiconductor film. It will have a pair of gate electrodes that overlap with 23 in between. Also, conductive film 30 The conductive film 30 is electrically connected to the conductive film 21 at the opening 32. It is translucent.

[0045] In Figure 2(C), after forming openings in insulating film 26 and insulating film 27, the nitride insulating film 28 and insulating film 29 are formed, and then insulating film 22 and nitride are formed so as to overlap the opening. The example shows a case in which an opening 32 is formed in the insulating film 28 and the insulating film 29. However, In one aspect of the present invention, insulating film 22, insulating film 26, insulating film 27, nitride insulating film 28, and Even if an opening 32 is formed in the insulating film 29 by etching or the like using a mask, i. However, in the case where the insulating film 29 is not provided on the pixel, or when the insulating film 29 is not provided The pixel electrodes are provided on the nitride insulating film 28, and the pixel electrodes are insulated from the insulating film 22. A conductive film located between the film 26 and the insulating film 27, insulating film 26, insulating film 27, and nitride insulating film When electrically connected at an opening formed in the film 28 and the insulating film 29, the pixels There is a difference in the thickness of the insulating film to be removed by etching between the electrode opening and opening 32. Therefore, the aperture for the pixel electrode and the aperture 32 are formed in a single mask. In this case, the conductive film located between insulating film 22 and insulating film 26 and insulating film 27 is used for the pixel electrode. In the opening, some parts are etched too much, or not etched enough, resulting in opening 3 In step 2, there is a risk of problems such as the conductive film 21 not being exposed. However, Figure 2( Openings are formed in insulating film 26 and insulating film 27 so that the structure shown in the cross-sectional view C) is obtained. After that, when forming an opening 32 in the insulating film 22, nitride insulating film 28, and insulating film 29, Even if the above opening and opening 32 are formed together with the mask, etching will occur between the opening and opening 32. The removal process is less likely to result in variations in the thickness of the insulating film. Therefore, the aforementioned problems do not occur. It is less prone to spoilage and can improve yield.

[0046] Furthermore, the transistor 20 shown in Figure 2 has a conductive film 24 and an edge of the oxide semiconductor film 23. The edges that do not overlap with the conductive film 25, in other words, the edges where the conductive film 24 and conductive film 25 are located. The end portion located in a region different from the region overlaps with the conductive film 21 and the conductive film 30. The edges of the oxide semiconductor film 23 are subjected to etching to form the edges in the plasma. When exposed, chlorine radicals, fluorine radicals, etc., generated from etching gases become oxides. It readily bonds with the metal elements that make up the semiconductor. Therefore, at the edges of the oxide semiconductor film, the metal Because the oxygen bonded to the group element is in a state where it can easily be removed, an oxygen vacancy is formed, resulting in n-type formation. It is thought that this is easy. However, in the transistor 20 shown in Figure 2, the conductive film 24 and the conductive The edge of the oxide semiconductor film 23, which does not overlap with film 25, overlaps with the conductive film 21 and the conductive film 30. Therefore, by controlling the potential of the conductive film 21 and the conductive film 30, the electric field applied to the end is controlled. This allows for control of conductivity between the conductive film 24 and the oxide semiconductor film 23 via the edges of the oxide semiconductor film 23. The current flowing between the films 25 is controlled by the potential applied to the conductive films 21 and 30. It is possible.

[0047] Specifically, the conductive film 21 and conductive film 30 are set to a potential such that the transistor 20 becomes non-conductive. When applied, the off-current flowing between the conductive film 24 and the conductive film 25 through the end is reduced. This can be suppressed. Therefore, in transistor 20, in order to obtain a large on current, By shortening the channel length, as a result, the conductive film 24 and the conductive film at the edge of the oxide semiconductor film 23 Even if the length between 25 is shortened, the off-current of transistor 20 can be kept low. Therefore, by shortening the channel length, transistor 20 can be large when in the conduction state. It is possible to obtain an on-current and keep the off-current low when in a non-conductive state. To obtain a large on-current, the channel length should ideally be between 0.5 μm and 4.5 μm. Preferably, the particle size is 1 μm to 4 μm, and even more preferably 1 μm to 3.5 μm. The following are preferred, and more preferably 1 μm to 2.5 μm, with 2 μm being the most preferred. Most preferable.

[0048] Figure 25 shows an example of a cross-sectional view of the transistor 20 at the edge of the oxide semiconductor film 23. In Figure 25, in the channel width direction corresponding to the dashed line A3-A4 in Figure 2(A), acid This example illustrates the case where the edge of the ionized semiconductor film 23 is positioned to overlap with the conductive film 21. Furthermore, in Figure 25, insulating film 26, insulating film 27, nitride insulating film 28, and insulating film 29 are single layers. It is shown as an insulating film.

[0049] As shown in Figure 25, the distance between the edge of the oxide semiconductor film 23 and the edge of the conductive film 30 is Tov. The distance between conductive film 21 and conductive film 30 is defined as Tge. In one aspect of the present invention, Tov is equal to Tg If e is 1.0 times or more, the conductive film 24 and conductive film 2 are connected via the edge of the oxide semiconductor film 23. It is preferable because the current flowing during interval 5 can be controlled. Also, Tov is 7 of Tge. Having a ratio of 5 times or less allows for the control of the above current, and furthermore, This allows us to keep the size of the Ranjista 20 even smaller.

[0050] Furthermore, the conductive film 21 and the conductive film are set to a potential such that the transistor 20 becomes conductive. When applied to 30, the current flowing between the conductive film 24 and the conductive film 25 through that end is increased. This can be done. The current increases the field-effect mobility and on-current of transistor 20. This contributes to the following. And the edge of the oxide semiconductor film 23 overlaps with the conductive film 21 and the conductive film 30. As a result, in the oxide semiconductor film 23, carriers are released between the insulating film 22 and the insulating film 26 and the oxide Because it flows not only at the interface with the semiconductor film 23, but also over a wide area of ​​the oxide semiconductor film 23, The amount of carrier movement in transistor 20 increases. As a result, transistor 20 As the on-current increases, the field effect mobility also increases, and typically, when the field effect mobility is 1 0cm 2 / V·s or more, and even 20cm 2 The result is greater than / V·s. Note that the field effect here Transistor mobility is not an approximation of the mobility as a physical property of oxide semiconductor films, but rather the mobility of a transistor. This is the field-effect mobility in the saturation region.

[0051] Furthermore, the transistor 20 shown in Figure 2 is used to form conductive films 24 and 25. During chipping, an insulating film (protective insulating film) for protecting the surface of the oxide semiconductor film 23 is Unlike the structure provided (channel protection structure), the protective insulating film is not provided. It has a channel etch structure.

[0052] In the case of a transistor with a channel protection structure, the objective is to protect the surface of the oxide semiconductor film 23. To achieve the target, the edges of conductive film 24 and conductive film 25 are, respectively, on the protective insulating film. It needs to be located in a certain position. Therefore, conductive film 24 and conductive film 25 are shaped by etching. For aligning the mask used in the process, a transistor with a channel protection structure is preferable. Higher precision is required than with channel etch transistors. Therefore, channel In the case of a transistor with a protective structure, the edges of the conductive film 24 and the edges of the conductive film 25 are more securely protected. In order to position them on the protective insulating film, the ends of the conductive film 24 in the channel length direction and the conductive film 2 Shortening the distance of the end of 5 is desirable to suppress the decrease in yield. However, By shortening the distance between the edge of the conductive film 24 and the edge of the conductive film 25, the conductive film 24 and the conductive film 25 and acid Because the region that overlaps with the semiconductor film 23 becomes larger, the conductive film 3 that functions as a gate From 0, the electric field that should be applied to the oxide semiconductor film 23 is due to conductive films 24 and 25 This makes it easier to shield. Note that the channel length direction is the distance between conductive film 24 and conductive film 25. This corresponds to the direction in which the carrier moves over short distances.

[0053] On the other hand, in the case of the channel etch structure transistor 20, conductive films 24 and 25 are etched When forming by ching, the transition of the channel protection structure is used for aligning the mask. Higher precision than that is not required. Therefore, the channel etch structure transistor 20 The distance between the edge of conductive film 24 and the edge of conductive film 25 is greater than that of the transistor with channel protection structure. Even if the length is increased, the decrease in yield can be suppressed. Therefore, conductive film 24 and conductive film 25 and oxidation Because the region where the material semiconductor film 23 overlaps can be narrowed, the oxide semiconductor can be transmitted from the conductive film 30. The electric field that should be applied to the body membrane 23 is less likely to be shielded by the conductive films 24 and 25. Therefore, the transistor 20 with a channel etch structure is better than the transistor with a channel protection structure. Compared to lampistors, it is easier to obtain a larger on-current, and even with a shorter channel length, acid The off-current flowing at the edges of the ionized semiconductor film 23 can be kept to a minimum.

[0054] Furthermore, the protective insulating film is subjected to plasma etching during the formation of conductive films 24 and 25. Because of the exposure, oxygen is easily released, and it is thought that oxygen deficiency is likely to form. Therefore, the protective insulating film is made of oxide semiconductor film 23 in contact with the protective insulating film, and oxide semiconductor film 2 It can be said that the ability to supply enough oxygen to reduce the oxygen deficiency in 3 is poor. On the other hand, in the channel etch structure transistor 20, among the oxide semiconductor film 23, the conductive film 2 The portion that does not overlap with 4 and the conductive film 25 is the part formed when the conductive film 24 and conductive film 25 are formed. It is exposed to plasma during chapping. However, after the conductive film 24 and conductive film 25 are formed, The insulating film 26 and insulating film 27 have the ability to supply a certain amount of oxygen to the oxide semiconductor film 23. By forming this, oxygen vacancies in the oxide semiconductor film 23 can be reduced. Therefore, The transistor 20 with a channel etch structure is better than the transistor with a channel protection structure. This allows for high reliability.

[0055] In particular, in the channel etch structure transistor 20, CAAC is applied to the oxide semiconductor film 23. -OS(C Axis Aligned Crystalline Oxide Sem When using an iconductor film, an amorphous oxide semiconductor film or a microcrystalline oxide semiconductor film is used. Compared to the case where the conductive film is used as an oxide semiconductor film 23, the conductive films 24 and 25 are formed in this way. During etching, the oxide semiconductor film 23 overlaps with the conductive film 24 and conductive film 25. Areas that are not etched are difficult to remove by etching. Therefore, CAA Transistor 20 using a C-OS film offers higher reliability. CAAC-OS film Details of amorphous oxide semiconductor films and microcrystalline oxide semiconductor films will be described later.

[0056] Furthermore, transistors having an oxide semiconductor film are storage-type transistors. Here, In the off and on states of a transistor having an oxide semiconductor film, the carrier flow This will be explained using the schematic diagram shown in Figure 36. Figures 36(A) and 36(B) are also shown. Figure 36(C) is a cross-sectional view in the channel length direction, while Figure 36(C) is a cross-sectional view in the channel width direction.

[0057] In Figure 36, the transistor having an oxide semiconductor film has a gate electrode GE_1 and a gate electrode. Gate dielectric film GI_1 on the gate electrode GE_1, and oxide semiconductor film on the gate dielectric film GI_1 OS, electrodes S and D on the oxide semiconductor film OS, and on the oxide semiconductor film OS and electrodes S and D It has a gate insulating film GI_2 and a gate electrode GE_2 on the gate insulating film GI_2. The synthetic semiconductor film OS consists of a channel region i and a low-resistance region n in contact with electrodes S and D. + and The gate electrodes GE_1 and GE_2 are connected as shown in Figure 36(C). It is.

[0058] When the transistor is in the off state, as shown in Figure 36(A), the gate electrode GE_1, GE When a negative voltage is applied to _2, electrons are repelled from the channel region i of the oxide semiconductor film OS. Therefore, the channel region i is completely depleted. As a result, the transistor's off-current becomes extremely small. It will bloom.

[0059] On the other hand, when the device is ON, as shown in Figure 36(B), there is a low-resistance region n in contact with the electrode S. + from Low-resistance region n in contact with electrode D + Electrons accumulate along the current path, and as indicated by the arrow, the current path takes shape. This is achieved. As shown in Figure 36(C), gate electrode GE_1 and gate electrode GE_2 are the same. By setting the potential and having the side surface of the oxide semiconductor film OS facing the gate electrode GE_2, In the channel width direction, gate electrode GE_1 and gate electrode GE_2 are gate By surrounding the oxide semiconductor film OS via insulating film GI_1 and gate insulating film GI_2, as shown in Figure As shown in 36(B), in the oxide semiconductor film OS, the carriers are located in the gate insulating film GI_ 1. Not only the interface between GI_2 and the oxide semiconductor film OS, but also a wide area within the oxide semiconductor film OS. Because it flows within the enclosure, the amount of carrier movement in the transistor increases. As a result, As the on-current of a transistor increases, the field-effect mobility also increases, and typically, The field effect mobility is 10cm 2 / V·s or more, and even 20cm 2 It will be / V·s or greater. Here, the field-effect mobility is not an approximation of the mobility as a physical property of oxide semiconductor films. This is the field-effect mobility in the saturation region of the transistor. The length L is 0.5 μm or more and 6.5 μm or less, preferably greater than 1 μm and less than 6 μm. Preferably greater than 1 μm and 4 μm or less, more preferably greater than 1 μm and 3.5 μm or less. Furthermore, by setting the diameter to greater than 1 μm and less than or equal to 2.5 μm, the field effect mobility increases. The addition is significant. Also, the channel length is small, between 0.5 μm and 6.5 μm. Therefore, it is also possible to reduce the channel width. For this reason, as shown in Figure 36(C), Even if a region is provided to serve as the connection point between gate electrode GE_1 and gate electrode GE_2, It is possible to reduce the area of ​​the inverter.

[0060] Next, the specific structure of the transistor 20 having an electrically connected pair of gate electrodes An example is shown in Figure 19. Figure 19(A) shows a top view of transistor 20. Note that Figure 1 In 9(A), to clarify the layout of the transistor 20, the insulating film 26 and the insulating film are shown. Various insulating films other than film 27, such as the gate insulating film, have been omitted. Also, in Figure 19(A) Figure 19(B) shows a cross-sectional view of the top view shown, along the dashed line A1-A2, and the dashed line A3-A4 A cross-sectional view of the structure is shown in Figure 19(C).

[0061] The transistor 20 shown in Figure 19 has insulating films 26 and 27 around the periphery of the transistor 20. In that it is partially removed, its structure differs from that of transistor 20 shown in Figure 2. Specifically, in Figure 19, the conductive film 24 and conductive film 2 are located at the edge of the oxide semiconductor film 23. The insulating film 26 and insulating film 27 cover at least the edges that do not overlap with 5. 6 and the insulating film 27 are partially removed. In the transistor 20 shown in Figure 19, the above In this configuration, the conductive film 30, which functions as a gate, is placed at the edges of the insulating film 26 and insulating film 27. This allows it to be brought closer to the edge of the oxide semiconductor film 23. As described above, The edges of the semiconductor film 23 tend to become n-type, but the conductive film 30 is attached to the above edges of the oxide semiconductor film 23. By bringing it closer, the electric field applied from the conductive film 30 to that end can be made stronger. Therefore, the current that flows between the conductive film 24 and the conductive film 25 via the edge of the oxide semiconductor film 23 This can be controlled more reliably by the potential applied to the conductive film 30. As a result, Even if the channel length of transistor 20 is shortened, the off-current of transistor 20 can be kept to a minimum. This allows for greater on-current and ensures a larger on-current.

[0062] Furthermore, in the transistor 20 shown in Figures 2 and 19, the conductive film is located in the channel length direction. The end of 30 is positioned to overlap with the oxide semiconductor film 23, but the oxide semiconductor film 23 The end of the part may be positioned so as to overlap with the conductive film 30.

[0063] Furthermore, the specific configuration of the transistor 20 having an electrically connected pair of gate electrodes. An example is shown in Figure 20. Figure 20(A) shows a top view of transistor 20. In (A), in order to clarify the layout of transistor 20, each of the gate insulating film and other elements is shown. The type of insulating film is omitted. Also, in the top view shown in Figure 20(A), the dashed line A1-A2 A cross-sectional view is shown in Figure 20(B), and a cross-sectional view along the dashed line A3-A4 is shown in Figure 20(C). .

[0064] The transistor 20 shown in Figure 20 has a conductive film 3 within the region where the oxide semiconductor film 23 is located. In the point where 0 does not overlap with conductive film 24 and conductive film 25, in other words, oxide semiconductor Within the region where the body membrane 23 is located, there is a region different from the region where the conductive films 24 and 25 are located. The structure differs from that of the transistor 20 shown in Figure 2 in that the conductive film 30 is located in that region.

[0065] Furthermore, the specific configuration of the transistor 20 having an electrically connected pair of gate electrodes. An example is shown in Figure 21. Figure 21(A) shows a top view of transistor 20. Note that Figure 21 In (A), in order to clarify the layout of transistor 20, each of the gate insulating film and other elements is shown. The insulating film is omitted. Also, in the top view shown in Figure 21(A), the dashed line A1-A2 A cross-sectional view is shown in Figure 21(B), and a cross-sectional view along the dashed line A3-A4 is shown in Figure 21(C). .

[0066] The transistor 20 shown in Figure 21 has a conductive film 3 within the region where the oxide semiconductor film 23 is located. At point 0, where it overlaps with conductive film 24 but not with conductive film 25, the transistor shown in Figure 2 It has a different structure from ZISTA 20. In other words, within the region where the oxide semiconductor film 23 is located, A conductive film 30 is located in a part of the region where the conductive film 24 is located, and the oxide semiconductor film 23 Within the region where the conductive film 25 is located, the conductive film 30 is located in a region different from the region where the conductive film 25 is located. In this respect, its structure differs from that of transistor 20 shown in Figure 2.

[0067] Furthermore, the specific configuration of the transistor 20 having an electrically connected pair of gate electrodes. An example is shown in Figure 24. Figure 24(A) shows a top view of transistor 20. In (A), in order to clarify the layout of transistor 20, each of the gate insulating film and other elements is shown. The insulating film is omitted. Also, in the top view shown in Figure 24(A), the dashed line A1-A2 A cross-sectional view is shown in Figure 24(B), and a cross-sectional view along the dashed line A3-A4 is shown in Figure 24(C). .

[0068] The transistor 20 shown in Figure 24 has conductive film 21 and conductive film 30, and electrical current is transmitted through conductive film 34. In terms of being electrically connected, its structure differs from that of transistor 20 shown in Figure 2. Furthermore, the conductive film 34 is formed on the insulating film 22, and an opening 32a is formed in the insulating film 22. It is in contact with the conductive film 21. Furthermore, the conductive film 30 is formed in the insulating film 26 to insulating film 29. The formed opening 32b is in contact with the conductive film 34.

[0069] The transistor 20 shown in Figures 20, 21, and 24 is the same as the transistor shown in Figure 19. As shown, the insulating film 26 and insulating film 27 may be partially removed.

[0070] Furthermore, in the transistor 20 shown in Figures 2, 19, 20, and 21, an oxide semiconductor film 23 is not necessarily composed of a single oxide semiconductor film, but rather of multiple stacked oxide semiconductor films. It may also be composed of a conductive film. In Figure 23(A), the oxide semiconductor film 23 is a stack of three layers. This illustrates a case where the oxide semiconductor film is composed of the treated oxide semiconductor film. Specifically, Figure 23(A) In the transistor 20 shown, the oxide semiconductor film 23 is an oxide semiconductor film 23a to an oxide semiconductor film 23a or acid The ionized semiconductor films 23c are stacked sequentially from the insulating film 22 side.

[0071] Furthermore, the oxide semiconductor film 23a and the oxide semiconductor film 23c constitute the oxide semiconductor film 23b. It contains at least one of the constituent metal elements, and the energy at the lower end of the conduction band is acid 0.05 eV or more, 0.07 eV or more, 0.1 eV or more, or 0 0.15eV or greater, and 2eV or less, 1eV or less, 0.5eV or less, or 0.4eV or less, true It is an oxide film close to an empty state. Furthermore, the oxide semiconductor film 23b contains at least indium Including this is preferable because it increases carrier mobility.

[0072] Furthermore, as shown in Figure 23(B), the oxide semiconductor film 23c is composed of conductive film 24 and conductive film 25. It may also be configured to be superimposed on the insulating film 22 in the upper layer.

[0073] Next, a transistor having a pair of gate electrodes that overlap with a semiconductor film in between, The circuit symbol is shown in Figure 22(A). In the circuit symbol shown in Figure 22(A), the pair of gate electrodes are F The electrodes are denoted by G and BG, the source electrode by S, and the drain electrode by D. (See Figure 22(A)) In the circuit symbol, the conductive film 30 functions as the gate electrode, and the source electrode or drain electrode is also shown. There are no limitations on the positional relationship between the conductive film 24 and the conductive film 25, which function as such.

[0074] Figure 22(B1) shows the conductive film 24 and conductive film that function as source or drain electrodes. 25 is partially connected to the conductive film 30 which functions as a gate electrode on the oxide semiconductor film 23. The circuit symbol for transistor 20, which is superimposed on the other element, is shown in Figure 22(B1). In the same circuit symbol as shown in Figure 22(A), the pair of gate electrodes are indicated by FG ​​and BG, and the The drain electrode is denoted as S, and the drain electrode as D.

[0075] Figure 22(B2) shows a cross-section of transistor 20, corresponding to the circuit symbol shown in Figure 22(B1). A diagram is shown as an example. The transistor 20 shown in Figure 22(B2) is located in the channel length direction. The distance Wsd between the ends of conductive film 24 and conductive film 25 is equal to the distance W between the ends of conductive film 30. It is shorter than bg. And in the cross-sectional view in the channel length direction, the pair of ends of the conductive film 30 The part overlaps with conductive film 24 and conductive film 25.

[0076] Also, Figure 22(C1) shows the conductive film 24 and which function as a source electrode or drain electrode. The conductive film 25, on the oxide semiconductor film 23, has a conductive film 30 that functions as a gate electrode. The circuit symbol for transistor 20 that is not overlapping is shown. The circuit symbol is as shown in Figure 22(C1). In the same circuit symbol as shown in Figure 22(A), the pair of gate electrodes are indicated by FG ​​and BG, and the The main electrode is denoted as S, and the drain electrode as D.

[0077] Figure 22(C2) shows a cross-section of transistor 20, corresponding to the circuit symbol shown in Figure 22(C1). A diagram is shown as an example. The transistor 20 shown in Figure 22(C2) is located in the channel length direction. The distance Wsd between the ends of conductive film 24 and conductive film 25 is equal to the distance W between the ends of conductive film 30. It is longer than bg. And in the cross-sectional view in the channel length direction, the pair of ends of the conductive film 30 The part does not overlap with conductive film 24 and conductive film 25.

[0078] In the drawings attached to this specification, the circuit symbol shown in Figure 22(A) corresponds to the circuit in Figure 22(B1). Transistor 20 with a structure represented by the symbol, and the structure represented by the circuit symbol in Figure 22(C1) It shall include transistor 20.

[0079] <Measurement of the electrical characteristics of a transistor> Next, when light is irradiated onto a transistor having a channel formation region in an oxide semiconductor film, Next, we will describe the results of measuring the electrical characteristics of the transistor.

[0080] First, let's explain the structure of the transistor used for the measurement. For the measurement, one gate electrode was used. It has a first transistor and a pair of gate electrodes that overlap with a semiconductor film in between. A second transistor was used.

[0081] The first transistor has a gate electrode made of a tungsten film with a thickness of 200 nm on an insulating surface. On the electrode and the above gate electrode, a silicon nitride film with a thickness of 400 nm and a nitrogen oxide film with a thickness of 50 nm are present. It had a gate insulating film in which silicon dioxide films were sequentially stacked. Furthermore, the first transistor On the gate insulating film, at a position overlapping with the gate electrode, a 35nm thick In-Ga-Zn film is applied. It had a system oxide semiconductor film. In addition, the first transistor had a thickness on the oxide semiconductor film. A source electrode and a drain electrode having a tungsten film with a thickness of 50 nm, an aluminum film with a thickness of 400 nm, and a titanium film with a thickness of 200 n m were laminated in this order. Further, on the oxide semiconductor film, the source electrode, and the drain electrode, a silicon oxynitride film with a thickness of 50 nm, a silicon oxynitride film with a thickness of 400 nm, and a silicon nitride film with a thickness of 100 nm were provided so as to be laminated in this order.

[0082] The second transistor differed from the first transistor only in that it further had a gate electrode using an indium tin oxide film added with silicon oxide and having a thickness of 100 nm on the silicon nitride film. And, in the second transistor, the gate electrode using a tungsten film and the gate electrode using an indium tin oxide film added with silicon oxide were electrically connected.

[0083] In the first transistor and the second transistor, the In-Ga-Zn-based oxide semiconductor film was formed by sputtering using a target with a composition (atomic ratio) of In, Ga, and Zn of 1:1:1. Also, in the first transistor and the second transistor, the silicon oxynitride film with a thickness of 50 nm was formed by plasma CVD using silane with a flow rate of 20 sccm and dinitrogen monoxide with a flow rate of 3000 s ccm as source gases, setting the pressure in the processing chamber to 200 Pa, the substrate temperature to 350 °C, and supplying high-frequency power of 150 W (power density 2.5×10 W / cm -2 2 ) to the parallel plate electrode using a 27.12 MHz high-frequency power supply. 2 Also, in the first transistor and the second transistor, the silicon oxynitride film with a thickness of 400 nm The film is prepared using silane at a flow rate of 160 sccm and nitrous oxide at a flow rate of 4000 sccm as raw materials. The processing chamber pressure was set to 200 Pa, the substrate temperature to 220°C, and a high frequency of 27.12 MHz was used. Using a wave power supply, 1500W (power density 2.5 × 10⁻¹⁰ -1 W / cm 2 ) high-frequency power parallel It was formed by plasma CVD applied to a flat plate electrode. Also, the first transistor and In the second transistor, a silicon nitride film with a thickness of 100 nm is subjected to silane at a flow rate of 50 sccm. Using nitrogen at a flow rate of 5000 sccm and ammonia at a flow rate of 100 sccm as the raw material gases... The processing chamber pressure was set to 100 Pa, the substrate temperature to 350°C, and a 27.12 MHz high-frequency power supply was used. Using 1000W (power density 1.6 × 10⁻¹⁰ -1 W / cm 2 ) High-frequency power of parallel plate electric It was formed by plasma CVD applied to the electrode.

[0084] Furthermore, the first and second transistors have a channel length L of 6 μm and a channel width W The size was 50 μm.

[0085] Then, the electrical characteristics of the first and second transistors were measured using stress marking. Measurement of drain current before the stress application process (Measurement 1), Measurement of drain current after the stress application process (Measurement 1) The process was carried out in the order of 2). In the stress application process, the environment was such that no light was irradiated in the darkroom. The board temperature was maintained at 60°C and the gate voltage Vg at -30V for 1 hour. Specifically, the drain current measurements in Measurement 1 and Measurement 2 are performed without light irradiation in a darkroom. The measurements were performed under environmental conditions with a substrate temperature of 60°C. The gate voltage Vg was set to -1 The voltage between the source and drain electrodes is varied in increments of 0.25V between 5V and 30V. Vds was set to 0.1V or 10V.

[0086] Figure 17(A) shows the gate voltage Vg and drain voltage of the first transistor obtained by measurement. The relationship with current Id is shown. Furthermore, the relationship is obtained by calculation when the voltage Vds is 10V. The field-effect mobility μFE is also shown. Furthermore, Figure 17(B) shows the results obtained by measurement. The relationship between the gate voltage Vg and drain current Id of the second transistor is shown. Furthermore, the voltage V When ds is 10V, the calculated field-effect mobility μFE is also shown. From Figures 17(A) and 17(B), it can be seen that the second transistor is more efficient than the first transistor. It was found that the drain current Id and field-effect mobility μFE were large.

[0087] Table 1 below shows the results obtained from the measurement of the first transistor (Single Gat e) the threshold voltage (Vth) of the second transistor (Dual Gate) and the shift value ( This indicates the Shift value. Note that the shift value is the gate current when the drain current rises. Defined as the value of pressure. Specifically, the logarithmic scale of the gate voltage relative to the linear scale. In a semi-logarithmic graph showing the relationship between drain current and drain current, the change in the slope of the drain current is the steepest. At the point where the tangent line intersects with the scale line corresponding to the drain current of 1e-12[A] It is defined as the voltage at which the voltage Vds is applied. The shift value used was the value when the voltage Vds is 10V.

[0088] [Table 1]

[0089] As shown in Table 1, in the first transistor, the threshold voltage is -4 due to the stress application process. It was found that the shift value was shifted by -6.80 V at 48 V. Also, in the second transistor due to the stress application process, the threshold voltage was 0.27 V and the shift value was shifted by 0.25 V It was found. Therefore, it was found that the shift of the threshold voltage and the shift value in the negative direction of the second transistor were suppressed more than those of the first transistor.

[0090] Therefore, from the above measurement, it was found that by providing a pair of gate electrodes positioned sandwiching the semiconductor film, the shift of the threshold voltage of the transistor in the negative direction can be suppressed. Also, it was found that an increase in the drain current can be realized by applying the same potential to the pair of gate electrodes.

[0091] 〈Comparison of Channel Etch-Type Transistors and Channel Protection-Type Transistors in Dual Gate Drive〉 Here, the field-effect mobilities and on-currents of the channel etch-type transistor and the channel protection-type transistor are compared respectively. Here, the gate electrodes facing each other sandwiching the oxide semiconductor film are connected, and the field-effect mobility (μ ) and the on-current (Ion) of the transistor in Dual Gate Drive with the same potential are compared. FE

[0092] The electrical characteristics of the channel etch-type transistor and the channel protection-type transistor were calculated. Fig. 29(A) shows the structure of the channel protection-type transistor used in the calculation. Note that the device simulation software Atlas (manufactured by Silvaco) was used for the calculation.

[0093] The channel protection-type transistor has a gate insulating film GI_1 formed on the gate electrode GE_1 Then, an oxide semiconductor film OS is formed on the gate insulating film GI_1. Source electrode S and drain electrode D are formed on 1 and the oxide semiconductor film OS. A channel protection film CS is placed between the ends of the drain electrode S and the drain electrode D and the oxide semiconductor film OS. A channel is formed. This consists of an oxide semiconductor film OS, a source electrode S and a drain electrode D, and a channel A gate insulating film GI_2 is formed on the protective film CS. Pole GE_2 is formed. Also, gate electrode GE_1 and gate electrode GE_2 are gate In the openings (not shown) formed in the insulating film GI_1 and the gate insulating film GI_2 , connect.

[0094] In channel-etch type transistors, a channel protection film CS is not provided, and the source electrode S and The end of the drain electrode D is in contact with the oxide semiconductor film OS.

[0095] The conditions used in the calculations are shown in Table 2.

[0096] [Table 2]

[0097] Figure 29(A) shows a dual-gate driven transistor, but as a comparative example, Even with single-gate driven transistors that do not have a to electrode GE_2, D The same calculations were performed as for a ual-gate driven transistor.

[0098] In a channel-protected transistor, an oxide semiconductor film is transmitted via a channel protection film CS. Let Sov be the length of the region where OS and the source electrode S or drain electrode D overlap. In the source electrode S and drain electrode D, an oxide semiconductor is used via the channel protection film CS. The region overlapping with the film OS is defined as the Sov region. The relationship between Sov and field-effect mobility was calculated. The results are shown in Figure 29(B), and the relationship between Sov and the on-current is calculated and shown in Figure 29(C). show.

[0099] Furthermore, in channel etch type transistors, Sov is set to 0 μm, and the field effect transfer Mobility and on-current were calculated. The calculation results are shown in Figures 29(B) and 29(C), respectively. This will be shown.

[0100] Figure 29(B) shows the results when the drain voltage Vd is 1V. (C) shows the result when the drain voltage Vd is 1V and the gate voltage Vg is 10V.

[0101] As shown in Figure 29(B), in a channel etch type transistor (Sov = 0 μm), Compared to single-gate driven transistors, dual-gate driven transistors The field-effect mobility of the transistor is approximately doubled. On the other hand, the channel-protected transistor... So, the field-effect mobility of a dual-gate driven transistor is large when the length of Sov is large. It decreases as the value decreases.

[0102] Also, as shown in Figure 29(C), a channel etch type transistor (Sov is 0 μm) So, compared to a single-gate driven transistor, dual-gate driven... The on-current of the transistor is approximately twice as high. On the other hand, the channel-protected transistor... Therefore, the on-current of a dual-gate driven transistor increases as the length of Sov increases. It is decreasing accordingly.

[0103] In channel-protected transistors, the Sov region in the source electrode S and drain electrode D is The region shields the electric field of the gate electrode GE_2. Therefore, in oxide semiconductor film OS, The region where carrier density cannot be controlled by the voltage of electrode GE_2 expands. As a result, As the length of Sov increases, the field-effect mobility decreases, and the on-current decreases. It can be obtained. From the above, compared to channel-protected transistors, channel etching The transistor of this type has an increased effect on field-effect mobility in dual-gate drive. The current amplification effect is effective.

[0104] <Regarding the improvement of current drive power through dual gate drive> Dual Gate: A gate electrode facing each other across an oxide semiconductor film is connected and at the same potential. In the drive transistor, reducing the channel length L improves the current driving force. I will explain what to do.

[0105] <<Regarding saturation mobility in an ideal model>> First, we simulate an ideal model that does not consider effects such as interface levels and interface scattering. The study was conducted using a simulation. Figure 30 shows the transistor model used in the calculation. The device simulation software Atlas (manufactured by Silvaco) was used for the calculations. Ta.

[0106] The transistor shown in Figure 30 has a gate insulating film GI_1 formed on the gate electrode GE_1. Then, an oxide semiconductor film OS is formed on the gate insulating film GI_1. A source electrode S and a drain electrode D are formed on the oxide semiconductor film OS. A gate insulating film GI_2 is formed on the film OS, source electrode S, and drain electrode D. A gate electrode GE_2 is formed on the insulating film GI_2. Also, gate electrode GE_1 and The gate electrode GE_2 is formed in the gate insulating film GI_1 and the gate insulating film GI_2. The connection is made at the opening (not shown).

[0107] The conditions used in the calculations are shown in Table 3.

[0108] [Table 3]

[0109] Since gate electrodes GE_1 and GE_2 are connected, they are always at the same potential. Furthermore, because this model uses two-dimensional simulation, the effects in the channel width direction are affected. This is not considered. Also, the Vg-Id characteristic when the drain voltage (Vd) is 10V By substituting the value into Equation 1, the saturation mobility μ can be calculated. FE The saturated region was calculated. The field effect mobility in a region is explained as the saturation mobility. The maximum saturation mobility obtained by calculation is... The maximum value is in the saturation region (gate voltage (Vg) < drain voltage (Vd) + threshold voltage (Vth) An index of current-driven force in )), which approximates mobility as a physical property of oxide semiconductor films. The value is different.

[0110]

number

[0111] In equation 1, W is the channel width of the transistor, and C Bottom is, This is the capacitance value per unit area between the electrode GE_1 and the oxide semiconductor film OS. In the case of a gate-driven transistor, there is also a gate electrode GE_2 and an oxide semiconductor film OS Capacitance is also formed between them, but saturation mobility is used as an indicator to compare current driving capabilities. Therefore, the capacitance of the gate electrode GE_2 side in the Dual Gate drive transistor is omitted. And, Dual Gate drive transistors and Single Gate drive transistors The same formula 1 is being used.

[0112] Figure 31(A) shows the calculation results for a dual-gate driven transistor, and the gate electrode G Figure 31(B) shows the calculation results for a single-gate driven transistor that does not have E_2. This will be shown.

[0113] Figure 31 shows a dual-gate driven transistor and a single-gate driven transistor. A saturation mobility with a sharp peak was obtained for each of the transistors. The shorter the length, the higher the peak value of the saturation mobility.

[0114] Here, as the channel length L decreases, the saturation mobility improves, which is due to the transient The following explains whether this corresponds to an improvement in the current-driven power of the device.

[0115] In the results obtained from the simulation of an ideal model, the gate voltage is Vg = Vt The on-currents at h+5 and Vg=Vth+10 are plotted against the length of L. The graph is shown in Figure 32. The upper part of Figure 32 shows the ON current, and the lower part of Figure 32 shows the ON current. × Indicates channel length. Note that in Figure 32, the left column shows the total when the drain voltage (Vd) is 1V. The calculation results are shown, with the right column displaying the results when the drain voltage (Vd) is 10V.

[0116] The ON current shown in Figure 32 is inversely proportional to the channel length (L). This is because the ON current is inversely proportional to the channel length. This is because it is inversely proportional to the length of the channel (L).

[0117] If the on-current is perfectly inversely proportional to the channel length, then the value of on-current × channel length is It remains constant regardless of the channel length. In Figure 32, when the drain voltage (Vd) is 1V... The value of ON current × channel length is constant with respect to the channel length (L). When the drain voltage (Vd) is 10V, the on-voltage decreases as the channel length (L) decreases. The value of current × channel length is increasing. This is because, when the drain voltage (Vd) is 10V, The effective channel length (explained later) is the channel length (S) defined in Figure 30. This indicates that the distance between electrode S and drain electrode D is shorter than the distance between them.

[0118] <The theory of bulk current> Below, in the saturation mobility of an ideal model transistor, the peak at a low gate voltage is Let's explain the cause.

[0119] In the transistor shown in Figure 30, the electron density contained in the oxide semiconductor film OS is, Assume that the thickness of the semiconductor film OS is represented by a constant value n0(y) in the direction of film thickness. y is an oxide semiconductor. This represents an arbitrary position in the channel length direction within the film OS. The potential φ is given by equation 2 and is constant. However, the gate electrode GE_1 The gate voltage Vg_1 and the gate voltage Vg_2 of the gate electrode GE_2 are at the same potential, The flat band voltages on both the electrode GE_1 side and the gate electrode GE_2 side are flat. Band voltage V FB Let's assume that...

[0120]

number

[0121] In this case, in a transistor having an oxide semiconductor film that is a storage type, the drain current I d is the bulk current I as shown in Equation 3. bulk It is given approximately by only this.

[0122]

number

[0123] In equation 3, t is the thickness of the oxide semiconductor film, and μ is the electron mobility of the oxide semiconductor film. k B is Boltzmann's constant, T is absolute temperature, L is eff This is the effective channel length. Channel length is the distance between the source electrode and the drain electrode, and effective channel length is different from In oxide semiconductor films, the n region extends from below the source electrode and the n region extends from below the drain electrode. This represents the distance between n regions. In particular, when the channel length is short or the drain voltage is high In total, the effective channel length becomes shorter than the channel length.

[0124] Note that n0(0) is the source electrode side end of the region defined by the effective channel length described above. This is electron density and can be expressed by equation 4. Also, n0(L eff ) is the effective channel length mentioned above. This is the electron density at the drain electrode end of the region defined by [formula], and is expressed by equation 5. Oh, in equations 4 and 5, N D This is the donor density in the channel region of an oxide semiconductor film. q is the elementary charge.

[0125]

number

[0126]

number

[0127] In the saturation region where Vd > Vg - Vth and Vg > Vth, the drain voltage Vd is Vg - V Since it can be replaced with th, equation 3 becomes equation 6.

[0128]

number

[0129] For the drain current Id obtained by equation 6, the saturation mobility μ FE sat The formula is calculated as follows: The result is 7.

[0130]

number

[0131] In equation 7, if we let Vg be Vth, the denominator becomes 0, and the saturation mobility μ FE sat is none It diverges to a limited extent. This property is the low gate at saturated mobility as shown in Figure 31. This is the cause of the peak at voltage Vg. In other words, the bulk flowing inside the oxide semiconductor film OS The more current is the primary cause of the drain current, the greater the saturation when the channel length in Figure 31 is 2 μm. A more distinct peak appears, similar to that seen in sum mobility.

[0132] Another factor that increases saturation mobility is the effective channel length L. eff ga channel It is conceivable that the length L will be shorter than the length of the film. For example, in an oxide semiconductor film OS, In the vicinity of the region in contact with the drain electrode S and the drain electrode D, the n region expands, resulting in Effective channel length L eff This becomes shorter than the channel length L. This effect is due to the saturation shift shown in Equation 7. degree μ FE sat L / L eff This is also evident from the proportional relationship.

[0133] <Current density in oxide semiconductor film OS> The fact that bulk current affects saturation mobility is due to the presence of oxide semiconductor films, which are storage-type devices. This is a phenomenon specific to transistors that have a silicon film as the semiconductor film. In inverting devices like this one, the effect of bulk current is minimal.

[0134] Next, a graph plotting the current density distribution obtained from the device simulation. This is shown in Figure 33. Figure 33(A) shows the Vg-I obtained by calculation with a drain voltage of 10V. Figures 33(B) and 33(C) show the characteristics of the oxide semiconductor film, and the cross-sectional area of ​​A1-A2 of the oxide semiconductor film is shown. The current density distribution in the direction is shown. Figure 33(B) is the saturation region (Vg=0.5V), and Figure 33(C) is The current density distribution in the linear region (Vg = 15V) is shown. Note that the transistor used in the calculation is... The channel length L / channel width W is 2μm / 50μm, and the drain voltage Vd is 10V That's what I decided.

[0135] From Figure 33(B), in the saturation region (low gate voltage Vg), approximately [percentage missing] is present in the oxide semiconductor film OS. The current density is uniformly distributed. On the other hand, as shown in Figure 33(C), in the linear region (high current density) At the t voltage (Vg), the current flowing near the surface of the oxide semiconductor film OS is dominant. As shown in Figure 33(B), in the saturation region, the current density in the oxide semiconductor film OS is Since it is distributed uniformly, one of the reasons for the peak in saturation mobility is bulk It can be seen that this is an electric current.

[0136] On the other hand, the current density of the semiconductor film of the inverted device obtained by device simulation The distribution is shown in Figure 34. Figure 34 shows the oxide semiconductor film OS of the transistor shown in Figure 30, n - This is the calculation result when replaced with a semiconductor film (silicon) containing a pn junction. Semiconductor film The channel region contains 1 × 17 / cm 3 We assumed an acceptor-type impurity with the following density.

[0137] Figure 34(A) shows the Vg-Id characteristics obtained by calculation with a drain voltage of 10V. Figures 34(B) and 34(C) show the current density in the A1-A2 cross-sectional direction of the semiconductor film shown in Figure 30. The degree distribution is shown. Figure 34(B) is the saturation region (Vg=0.5V), and Figure 34(C) is the linear region ( This is the current density distribution at Vg = 15V. Note that the transistor channel used in the calculation The channel length L / channel width W was 2 μm / 50 μm, and the drain voltage Vd was set to 10 V.

[0138] Unlike transistors, which have oxide semiconductor films as storage devices, inverting devices A transistor having a certain semiconductor film, as shown in Figure 34(B), near the threshold voltage... Even in this case, the current flowing across the surface of the semiconductor film is large, and the contribution of bulk current is storage type It's smaller compared to a vise.

[0139] Based on the above, in a transistor having an oxide semiconductor film, which is a storage-type device, In an ideal model, bulk currents can be seen to cause a sharp peak in saturation mobility. .

[0140] Furthermore, the shorter the channel length L, the lower the peak value of saturation mobility generated by the bulk current. The reason for the increased cost is that in an oxide semiconductor film OS, the source electrode S and the drain electrode D In the vicinity of the touching region, the n region expands, resulting in an effective channel length L. eff ga channel It is possible that it will be shorter than the channel length L. Also, if the channel length L is small, the source electrode S and Furthermore, the energy (Ec) at the lower end of the conduction band of the oxide semiconductor film OS is lower due to the influence of the drain electrode D. This is a phenomenon where the energy at the lower end of the conduction band approaches the Fermi energy (CBL effect (Con The effective channel due to the duction band lowering effect. Long L eff It is possible that this becomes shorter than the channel length L. The saturation mobility is shown in Equation 7. As shown above, the effective channel length L eff As the size decreases, L / L eff Larger in proportion to Yes. This effect becomes more pronounced as the channel length L decreases, so if the channel length L is small... This suggests that the saturation mobility has improved to a certain extent.

[0141] <> Next, in order to approximate the saturation mobility of an actual transistor, the transistor of an ideal model In the st, electrons are trapped at the interface between the gate insulating film GI_1 and the oxide semiconductor film OS. Then, the calculation was performed assuming a negatively charged acceptor-type level, i.e., a shallow electron trap level. The results are shown in Figure 35.

[0142] Figure 35(A) shows the electrons assumed to be at the interface between the gate insulating film GI_1 and the oxide semiconductor film OS. This shows the density of state (DOS) at the wrap level.

[0143] Next, Dual Gate driven transistors and Single Gate driven transistors The saturation mobility of each transistor was calculated. Calculations for dual-gate driven transistors. The results are shown in Figure 35(B), and the calculation results for a single-gate driven transistor are shown in Figure 35(B). This is shown in 35(C).

[0144] From Figures 35(B) and 35(C), a dual-gate driven transistor and sin In the saturation mobility of a GLE-Gate driven transistor, obtained using an ideal model. No sharp peaks like that appeared. Also, from Figure 35(C), Single Gate In dynamic transistors, the peak value of saturation mobility is approximately independent of the channel length L. It was around 5. On the other hand, with dual-gate driven transistors, the channel length L is small. As the temperature rose, the peak value of the saturation mobility increased, reaching a value of 15 to just under 20. The results show the same trend as the results of the examples described later.

[0145] Therefore, in a dual-gate driven transistor, the channel length L can be reduced. It can be seen that the saturation mobility increases as this is done.

[0146] <Example of semiconductor display device configuration> Next, an example of the configuration of a semiconductor display device according to one aspect of the present invention will be described.

[0147] The semiconductor display device 70 shown in Figure 6(A) has a pixel section 71 with a plurality of pixels 55, and Wiring GL1 to GLy (where y is a natural number) are used to select each row of wiring GL. And, wiring SL1 to wiring SLx (x is) for supplying an image signal to the selected pixel 55. Wiring SL, denoted by a natural number, is provided. The signal input to wiring GL is the drive cycle. It is controlled by path 72. The input of the image signal to wiring SL is controlled by drive circuit 73. Multiple pixels 55 are connected to at least one of the wiring GLs and at least one of the wiring SLs. They are all connected to each other.

[0148] The type and number of wirings provided in the pixel section 71 are determined by the configuration, number, and arrangement of the pixels 55. Therefore, it can be determined. Specifically, in the case of the pixel section 71 shown in Figure 6(A), x columns × y rows The pixels 55 are arranged in a matrix, with wiring SL1 to SLx, wiring GL1 and This example illustrates the case where the wiring GLy is located within the pixel section 71.

[0149] In Figure 6(A), the drive circuits 72 and 73 are located on the same substrate as the pixel section 71. Although the example shows the case where it is formed on top, the drive circuits 72 and 73 are located in the pixel section 7 It may be formed on a different substrate than the one specified in 1.

[0150] Furthermore, Figure 6(B) shows an example of the configuration of the pixels 55. Each pixel 55 is connected to the liquid crystal element 60 and a transistor 56 that controls the supply of an image signal to the liquid crystal element 60, and the liquid crystal element 60 It has a capacitive element 57 for maintaining the voltage between the pixel electrode and the common electrode. The liquid crystal element 60 is It includes a pixel electrode, a common electrode, and a liquid crystal material to which a voltage is applied between the pixel electrode and the common electrode. It has a liquid crystal layer.

[0151] Transistor 56 controls whether or not to apply the potential of the wiring SL to the pixel electrodes of the liquid crystal element 60. A predetermined potential is applied to the common electrode of the liquid crystal element 60.

[0152] The specific connection configuration of transistor 56 and liquid crystal element 60 will be described below. Figure 6(B In this case, the gate of transistor 56 is connected to either wire GL1 or wire GLy. The source and drain of transistor 56 are connected from wiring SL1 to wiring SL It is connected to one of x, and the source and drain of transistor 56 are connected to a liquid crystal element. It is connected to the pixel electrode of sub-60.

[0153] In the liquid crystal element 60, the liquid crystal layer contains according to the voltage value applied between the pixel electrode and the common electrode. The orientation of the liquid crystal molecules changes, and the transmittance changes. Therefore, the liquid crystal element 60 is a pixel electrode. The transmittance is controlled by the potential of the image signal applied to it, thereby displaying grayscale. This is possible. And in each of the multiple pixels 55 that the pixel unit 71 has, liquid crystal element The gradation of sub-60 is adjusted according to the image signal containing image information, thereby the image in the pixel section 71. This will be displayed.

[0154] In Figure 6(B), at pixel 55, a switch controls the input of the image signal to pixel 55. The example then illustrates the case where transistor 56 is used. However, as a switch Multiple functional transistors may be used in pixel 55.

[0155] In one aspect of the present invention, a transistor 56 with a remarkably low off-current is used for the pixels 55 of an image signal. It is preferable to use it as a switch to control the input to. The off current of transistor 56 is If it is small, it can prevent charge leakage through transistor 56. Therefore, To more reliably maintain the potential of the image signal applied to the liquid crystal element 60 and the capacitive element 57. Therefore, the transmittance of the liquid crystal element 60 changes due to charge leakage within a single frame period. This prevents this and thereby improves the quality of the displayed image. If the off-current of transistor 56 is small, it prevents charge leakage through transistor 56. Therefore, during the period when a still image is displayed, the drive circuit 72 and drive circuit 73 The power potential or signal supply to the pixel unit 71 may be stopped. With the above configuration, the image signal This reduces the number of times the number is written to, thereby lowering the power consumption of the semiconductor display device.

[0156] For example, transistors containing oxide semiconductors in their semiconductor films have a remarkably low off-current, It is suitable to use this as transistor 56.

[0157] Furthermore, in Figure 6(B), the transistors 56 are arranged in pairs, with a semiconductor film in between. This illustrates the case where there is a gate electrode. The pair of gate electrodes are electrically connected. In one aspect of the present invention, the above configuration increases the on-current of the transistor 56, Furthermore, this can improve the reliability of transistor 56.

[0158] Next, Figure 6(C) shows another example of pixel 55. Pixel 55 receives the image signal to pixel 55. A transistor 95 controls the input, and a light-emitting element 98 controls the light-emitting element 98 according to the image signal. A transistor 96 controls the current value supplied to it, and a capacitor holds the potential of the image signal. It has element 97 and

[0159] The light-emitting element 98 is an LED (Light Emitting Diode) or an OLED (O2 Current or voltage, such as in an electromagnetic light-emitting diode. Therefore, elements whose brightness is controlled are included in that category. For example, an OLED has an EL layer and It has at least an anode and a cathode. The EL layer is placed between the anode and the cathode. It consists of one or more layers, and these layers contain a luminescent substance. It includes at least a light-emitting layer.

[0160] Furthermore, the EL layer is activated when the potential difference between the cathode and anode exceeds the threshold voltage of the light-emitting element 98. Electroluminescence is obtained by the current supplied when this occurs. Nessens exhibits luminescence (fluorescence) when returning from the singlet excited state to the ground state, and the triplet excited state. This includes the emission (phosphorescence) that occurs when returning to the ground state.

[0161] Either the anode or cathode of the light-emitting element 98 is connected to the image signal input to the pixel 55. Therefore, its potential is controlled. Of the anode and cathode, its potential is controlled according to the image signal. The controlled electrode is designated as the pixel electrode, and the other electrode is designated as the common electrode. A predetermined potential is applied to the electrodes, and the brightness of the light-emitting element 98 is determined between the pixel electrode and the common electrode. It is determined by the potential difference. Therefore, the brightness of the light-emitting element 98 changes according to the potential of the image signal. By being controlled, it is possible to display gradations. And the multiple pixels 5 that the pixel part has In each of the five, the gradation of the light-emitting element 98 is adjusted according to the image signal containing image information. As a result, an image is displayed in the pixel section 71.

[0162] Next, the pixel 55 has transistor 95, transistor 96, capacitive element 97, and light emission The connection configuration of element 98 will be explained below.

[0163] Transistor 95 has either its source or drain connected to wiring SL, and its source or The other end of the drain is connected to the gate of transistor 96. The wire is connected to wiring GL. Transistor 96 has either its source or drain connected to It is connected to the power line VL, and the other end of either the source or drain is connected to the light-emitting element 98. Specifically, the source or drain of transistor 96 is the anode of light-emitting element 98. It is connected to either the anode or the cathode of the light-emitting element 98. A predetermined potential is applied to the other side.

[0164] In Figure 6(C), transistor 96 is a pair of gates that overlap with a semiconductor film in between. This example illustrates a case where there are gate electrodes. The pair of gate electrodes are electrically connected. In one aspect of the present invention, the above configuration increases the on-current of the transistor 96, and further This can improve the reliability of transistor 96.

[0165] <Pixel composition> Next, we will take a liquid crystal display device, which is one of the semiconductor display devices 70 shown in Figure 6(A), as an example. Next, we will explain an example of the configuration of pixel 55. Figure 4 shows the base together with the transistor 20 shown in Figure 2. A top view of a pixel 55 formed on the plate 31 is shown as an example. Note that in Figure 4, pixel 55 To clarify the layout, various insulating films have been omitted. Also, the pixels shown in Figure 4 Figure 5 shows a cross-sectional view of a liquid crystal display device formed using an element substrate having 55. In the liquid crystal display device shown, the element substrate including the substrate 31 is located at the cross-section of the dashed line B1-B2 in Figure 4. This corresponds to a surface drawing.

[0166] The pixel 55 shown in Figures 4 and 5 has a transistor 56 and a capacitive element 57. The pixel 55 shown in Figure 5 has a liquid crystal element 60.

[0167] The transistor 56 has a gate electrode function on a substrate 31 having an insulating surface. A conductive film 40 and an insulating film that functions as a gate insulating film and is located on the conductive film 40. The film 22, the oxide semiconductor film 41 which overlaps with the conductive film 40 on the insulating film 22, and the oxide semiconductor A conductive electrode electrically connected to the body membrane 41, which functions as a source electrode or drain electrode. It has a film 43 and a conductive film 44. The conductive film 40 is a wiring GL as shown in Figure 6(B). It has the ability to function as wiring SL as shown in Figure 6(B).

[0168] Furthermore, the pixel 55 has a metal oxide film 42 on the insulating film 22. The metal oxide film 42 is It is a conductive film that is transparent to light. And on the metal oxide film 42, A conductive film 61 is provided electrically connected to the physical film 42. The conductive film 61 is a metal oxide. It functions as wiring that supplies a predetermined potential to the film 42.

[0169] Furthermore, in Figure 5, the oxide semiconductor film 41, conductive film 43 and conductive film 44 and the metal oxide film 4 An insulating film 26 and an insulating film 27 are provided on 2 and the conductive film 61 in order to be laminated. Transistor 56 may include insulating film 26 and insulating film 27 as its components. Note that Figure 5 illustrates the sequentially stacked insulating film 26 and insulating film 27, but the insulation Instead of film 26 and insulating film 27, a single insulating film may be used, or a laminated film may be used. Three or more insulating layers may be used.

[0170] Furthermore, the insulating film 26 and insulating film 27 have openings 58 at positions that overlap with the metal oxide film 42. The opening 58 is in a region different from the oxide semiconductor film 41, the conductive film 43, and the conductive film 44. It is present and located in a region that overlaps with the metal oxide film 42.

[0171] Furthermore, in Figure 5, the metal oxide film 42 on insulating film 26 and insulating film 27 and at the opening 58 A nitride insulating film 28 and an insulating film 29 are arranged on top of each other in a stacked manner.

[0172] Furthermore, an oxide semiconductor film is formed on the insulating film 22, and a nitride is formed in contact with the oxide semiconductor film. By forming the insulating film 28, the conductivity of the oxide semiconductor film can be increased. The oxide semiconductor film with increased conductivity can then be used as the metal oxide film 42. The conductivity of the oxide semiconductor film increases when the opening 58 is formed, or when the nitride insulating film 2 When 8 is formed, oxygen vacancies are formed in the oxide semiconductor film and diffuse from the nitride insulating film 28. This is thought to be because the hydrogen binds to the oxygen deficiency, generating the donor. The resistivity of the metal oxide film 42 is typically 1 × 10⁻⁶. -3 Ωcm or more, 1 × 10 4 Ωcm Less than, more preferably, a resistivity of 1 × 10⁻⁶ -3 Ωcm or more, 1 × 10 -1 Less than Ωcm It would be good to do so.

[0173] The metal oxide film 42 preferably has a higher hydrogen concentration than the oxide semiconductor film 41. In the material film 42, secondary ion mass spectrometry (SIMS) was performed. The hydrogen concentration obtained by (assess spectrometry) is 8 × 10 19 Atom s / cm 3 Preferably 1 × 10 20 atoms / cm 3 The above is a comfortable 5x 10 20 atoms / cm 3 That concludes the explanation. In the oxide semiconductor film 41, the secondary ion mass The hydrogen concentration obtained by the analytical method is 5 × 10⁻⁶ 19 atoms / cm 3 Less than 5 ×10 18 atoms / cm 3 Less than 1 × 10 18 atoms / cm 3 below, Comfortable 5x10 17 atoms / cm 3 More preferably 1 × 10 16 a toms / cm 3 The following applies:

[0174] Examples of nitride insulating film 28 include silicon nitride, silicon nitride oxide, and aluminum nitride. Aluminum nitride oxide and the like can be used. Nitride insulating film using the above-mentioned materials 28 is more resistant to external impurities compared to oxide insulating films such as silicon oxide and aluminum oxide. Substances such as water, alkali metals, and alkaline earth metals diffuse into the oxide semiconductor film 41. This can prevent that.

[0175] Furthermore, the nitride insulating film 28 and insulating film 29 are provided with openings 62 at positions that overlap with the conductive film 44. It is made transparent to visible light on the nitride insulating film 28 and insulating film 29. A conductive film 45 is provided, which has an open At the opening 62, it is electrically connected to the conductive film 44. Also, the conductive film 45 is at the opening At 58, it overlaps with the metal oxide film 42. The conductive film 45 and the metal oxide film 42 are nitrogen The overlapping portion of the oxide insulating film 28 and the insulating film 29, with the film sandwiched in between, functions as a capacitive element 57. .

[0176] The capacitive element 57 consists of a metal oxide film 42 and a conductive film 45 that function as a pair of electrodes, and a dielectric The nitride insulating film 28 and insulating film 29, which function as a film, are transparent to visible light. Therefore, the capacitive element 57 has light transmission to visible light, and the capacitive element Compared to pixels with low light transmittance to visible light, the aperture ratio of pixel 55 can be increased. Therefore, while securing the necessary capacity to obtain high image quality, the loss of light within the panel is minimized. This can reduce power consumption in semiconductor devices.

[0177] As mentioned above, the insulating film 29 is not necessarily required, but the nitride insulating film 28 Furthermore, an insulating film 29 made of an insulator with a lower dielectric constant is used together with a nitride insulating film 28 as a dielectric film. By using this, the dielectric constant of the dielectric film of the capacitive element 57 is increased, and the thickness of the nitride insulating film 28 is increased. It can be adjusted to the desired value without any effort.

[0178] An orientation film 52 is provided on the conductive film 45.

[0179] Furthermore, a substrate 46 is provided opposite the substrate 31. Visible light A shielding film 47 that has the function of blocking light, and a colored layer 48 that transmits visible light in a specific wavelength range, A resin film 50 is provided on the shielding film 47 and the colored layer 48, and the resin A conductive film 59, which functions as a common electrode, is provided on the film 50. An orientation film 51 is provided on 59.

[0180] Then, between substrate 31 and substrate 46, the liquid crystal is sandwiched between alignment film 52 and alignment film 51. A liquid crystal layer 53 containing the material is provided. The liquid crystal element 60 has a conductive film 45, a conductive film 59, and It has a liquid crystal layer 53.

[0181] In Figures 4 and 5, the driving method for the liquid crystal is TN (Twisted Nematic). The example given was using the ) mode, but as for the LCD driving method, FFS (Fringe Field Switching (STN) mode, STN (Super Twisted Ne matic) mode, VA (Vertical Alignment) mode, MVA ( Multi-domain Vertical Alignment) mode, IPS ( In-Plane Switching mode, OCB (Optically Com Pensated Birefringence mode, Blue phase mode, TBA (T (Transverse Bend Alignment) mode, VA-IPS mode, E CB(Electrically Controlled Birefringence) ) Mode, FLC (Ferroelectric Liquid Crystal) Mode AFLC (AntiFerroelectric Liquid Crystal) Mode, PDLC (Polymer Dispersed Liquid Crystal) l) Mode, PNLC (Polymer Network Liquid Crystal) l) Mode, Guest Host Mode, ASV (Advanced Super View) It is also possible to apply modes and other settings.

[0182] Furthermore, in a liquid crystal display device according to one aspect of the present invention, the liquid crystal layer includes, for example, thermotropic Liquid crystal materials classified as chlorotropic liquid crystals or liotropic liquid crystals can be used. The liquid crystal layer may include, for example, nematic liquid crystal, smectic liquid crystal, cholesteric liquid crystal, and For this, liquid crystal materials classified as discotic liquid crystals can be used. Alternatively, the liquid crystal layer can be For example, this involves using liquid crystal materials classified as ferroelectric liquid crystals or antiferroelectric liquid crystals. Yes, it is possible. Alternatively, the liquid crystal layer may contain, for example, a main-chain polymer liquid crystal, a side-chain polymer liquid crystal, or By using liquid crystal materials classified as polymer liquid crystals, such as composite polymer liquid crystals, or low molecular weight liquid crystals... This is possible. Alternatively, the liquid crystal layer may be classified as, for example, polymer-dispersed liquid crystal (PDLC). Liquid crystal materials can be used.

[0183] Alternatively, a liquid crystal exhibiting a blue phase without an alignment layer may be used as the liquid crystal layer. The blue phase is the liquid crystal phase. One such example is when a cholesteric liquid crystal is heated, and it transitions from the cholesteric phase to the isotropic phase. This phase appears just before transfer. The blue phase only appears within a narrow temperature range, so Kaira The temperature range is improved by adding a curing agent or UV-curing resin. The liquid crystal exhibits a blue phase and a chiral agent. A liquid crystal composition containing these elements has a short response time of 1 msec or less and is optically isotropic, therefore orientation It is preferable because it requires no processing and has low dependence on the viewing angle.

[0184] Furthermore, Figure 5 shows a liquid crystal display device that uses a color filter to display a color image. As illustrated, one aspect of the present invention is a liquid crystal display device that emits light of different hues. The system may have a configuration that displays a color image by sequentially turning on the light sources.

[0185] <Example of a sequential circuit configuration 2> Next, a configuration example of a sequential circuit according to one aspect of the present invention, different from that shown in Figure 1, will be described.

[0186] Figure 7(A) shows an example of the configuration of a sequential circuit 10 according to one aspect of the present invention. The sequential circuit 10 has transistors 80 to 86. The signals RES, LIN, RIN, CK1, and CK2 are input to this. In addition, the sequential circuit 10 is supplied with a high-level potential VDD and a low-level potential VSS. It is supplied. And, according to the potential of the above signal, transistors 80 to 8 The continuity or non-continuity of 6 is selected, respectively, and the output terminals A and of the sequential circuit 10 A signal including the potential VSS or potential VDD is output from output terminal B.

[0187] Specifically, the gate of transistor 80 is connected to the wiring to which the signal LIN is input. The source and drain of transistor 80 are such that one is connected to output terminal A. The other end is connected to a wire to which potential VDD is applied. The gate of transistor 81 is It is connected to output terminal B. The source and drain of transistor 81 are such that one of them is It is connected to a wiring to which the potential VSS is supplied, and the other end is connected to output terminal A. The gate of transistor 82 is connected to the wiring to which signal CK2 is input. The source and drain of transistor 82 are, on the other hand, the source and drain of transistor 83. It is connected to the other side, and the other side is connected to a wire to which a potential VDD is applied. The gate of transistor 83 is connected to the wiring to which signal CK1 is input. The source and drain of 83 are such that one is connected to output terminal B, and the other is connected to It is connected to either the source or drain of transistor 82. The gateway of transistor 84. The source of transistor 84 is connected to the wiring into which the signal RIN is input. The drain is connected to output terminal B on one side and to a terminal that is given potential VDD on the other side. It is connected to a wire. The gate of transistor 85 is connected to the wire into which the signal LIN is input. The source and drain of transistor 85 are such that one of them is given a potential VSS. One end is connected to the wiring, and the other end is connected to output terminal B. Transistor 86 The gate is connected to the wiring to which the signal RES is input. The transistor 86 has The drain and the other are connected to output terminal B, and the other is given a potential VDD. It is connected to the wiring.

[0188] Note that the output terminal A of the sequential circuit 10 shown in Figure 7(A) is the same as the output terminal shown in Figure 1(A). This corresponds to OUT, and transistor 80 functions as transistor 12 in Figure 1(A). Transistor 81 functions as transistor 13 in Figure 1(A). The transistors 82 through 86 function as circuit 11 in Figure 1(A).

[0189] Furthermore, in one aspect of the present invention, transistor 80, transistor 82, transistor 83 , at least one of transistors 84, 85, and 86 However, a pair of gate electrodes are electrically connected and overlapping with a semiconductor film in between. It is assumed to have poles. In Figure 7(A), transistor 80, transistor 82, and transistor All of transistors, including transistor 83, transistor 84, transistor 85, and transistor 86, are above This illustrates the case where there is a pair of gate electrodes as described above. A pair of electrically connected gates By providing electrodes on one or all of the above-mentioned transistors, near the surface of the element substrate Even if a positive fixed charge is generated, the fixed charge will cause a negative charge to be generated near the surface of the semiconductor film. This prevents the occurrence of [unspecified event] and suppresses a negative shift in the threshold voltage of the transistor. Therefore, the reliability of the sequential circuit 10, and by extension the reliability of the semiconductor device using the sequential circuit 10, can be improved. It can enhance sexual performance.

[0190] Furthermore, by electrically connecting a pair of gate electrodes, one gate electrode can be electrically connected to only one of the pair. Unlike when a constant potential is applied, the same potential is applied to the pair of gate electrodes, so The Nellum formation region increases, which makes it possible to increase the drain current of the transistor. Therefore, it is possible to keep the size of the above transistor small while suppressing the decrease in on-current. Therefore, the area of ​​the sequential circuit 10, and by extension the drive circuit using the sequential circuit 10, can be kept small. It is possible.

[0191] Furthermore, by providing a pair of electrically connected gate electrodes, a depletion layer is not formed in the semiconductor film. Because the value decreases, the S value (subthreshold value) of the above transistor can be improved. ru.

[0192] Figure 8 shows a shift circuit configured by connecting multiple sequential circuits 10 shown in Figure 7(A). Zista is shown as an example.

[0193] The shift register shown in Figure 8 has sequential circuits 10_1 to 10_y. Paths 10_1 through sequential circuit 10_y are the same as sequential circuit 10 shown in Figure 7(A). It has a configuration. However, in the sequential circuits 10_1 to 10_y shown in Figure 8, the signal C As K1 and signal CK2, any two of signals CLK1 through CLK8 are respectively It is used. Also, the shift register shown in Figure 8 is buffer BUF_1 to buffer It has multiple buffers BUF, indicated by BUF_y. Buffers BUF_1 to Buffer The output signals from sequential circuits 10_1 through 10_y are input to BUF_y, respectively. Furthermore, the shift register shown in Figure 8 is used as a dummy sequential circuit 10_D It has UM and buffer BUF_DUM. The output signal from the sequential circuit 10_DUM is... This is entered into BUF_DUM.

[0194] Specifically, in sequential circuit 10_8m+1, the signals CK1 and CK2 are, and the signal CLK Signals 6 and CLK7 are used, respectively. In the sequential circuit 10_8m+2, signal CK1 And as signal CK2, signals CLK3 and CLK4 are used, respectively. On route 10_8m+3, signals CK1 and CK2 are used, and signals CLK8 and CLK 1 is used in each case. In the sequential circuit 10_8m+4, the signals CK1 and CK2 and Then, signals CLK5 and CLK6 are used, respectively. Sequential circuit 10_8m+5 So, signals CK1 and CK2, and signals CLK2 and CLK3 are used respectively. It can be there. In the sequential circuit 10_8m+6, the signals CK1 and CK2 are the same as the signal CLK. 7 and signal CLK8 are used, respectively. In the sequential circuit 10_8m+7, signal CK1 And as signal CK2, signals CLK4 and CLK5 are used, respectively. In road 10_8m, signals CK1 and CK2 are, and signals CLK1 and CLK2 are Each is used. However, 8m to 8m+7 is used when the total number of sequential circuits 10 is y. Let be any natural number that satisfies the following conditions:

[0195] Furthermore, in the sequential circuit 10_DUM, the signals used as signals CK1 and CK2 are the preceding stage It depends on the number of stages in the sequential circuit 10. For example, if the sequential circuit 10_8m+1 is in the preceding stage... In this case, in the sequential circuit 10_DUM, signals CK1 and CK2 are used as signals CLK3 and The signals CLK4 are used respectively. When a sequential circuit 10_8m+2 exists in the preceding stage, In sequential circuit 10_DUM, signals CK1 and CK2 are CLK8 and C LK1 is used in each case. If a sequential circuit 10_8m+3 exists in the preceding stage, the sequential circuit In 10_DUM, signals CK1 and CK2 are used, and signals CLK5 and CLK6 are used. Each is used. If a sequential circuit 10_8m+4 exists in the preceding stage, then sequential circuit 10_D In UM, signals CK1 and CK2 are used, and signals CLK2 and CLK3 are used, respectively. It is used. If a sequential circuit 10_8m+5 exists in the preceding stage, then in sequential circuit 10_DUM Signals CK1 and CK2 are used, and signals CLK7 and CLK8 are used, respectively. If a sequential circuit 10_8m+6 exists in the preceding stage, then in the sequential circuit 10_DUM, signal C Signals CLK4 and CLK5 are used as K1 and CK2, respectively. If sequential circuit 10_8m+7 exists, then in sequential circuit 10_DUM, the signals CK1 and Signals CLK1 and CLK2 are used as signal CK2, respectively. If path 10_8m exists, in sequential circuit 10_DUM, signals CK1 and CK2 and Signals CLK6 and CLK7 are then used.

[0196] Furthermore, in the shift register shown in Figure 8, the sequential circuit 10_j (where j is a natural number less than or equal to y) The positions of each wire connected to ) are schematically shown in Figure 7(B). From Figure 8 and Figure 7(B) As shown above, in sequential circuit 10_j, the signal LIN is the output of the preceding sequential circuit 10_j-1. The buffer BUF connected to power terminal A and output terminal B has output terminal GOUT5(j The output signal from -2)+5 is used. However, in the first stage sequential circuit 10_1, the signal Signal SP is used as LIN.

[0197] Furthermore, in sequential circuit 10_j, the signal RIN is the output terminal of the subsequent sequential circuit 10_j+1. The buffer BUF connected to child A and output terminal B has output terminal GOUT5j+2 The output signals of these are used. However, in the y-th stage sequential circuit 10_y, sequential circuit 10_D The buffer BUF_DUM connected to output terminals A and B of UM has, The output signal from sub-OUT2 is used.

[0198] Furthermore, in the shift register shown in Figure 8, the position of each wire connected to the buffer BUF This is schematically shown in Figure 9(A). As shown in Figure 9(A), the buffer BUF contains sequential times In addition to the output signals from output terminals A and B of the path 10, signals CK1 to CK5 The following is input. In buffer BUF, signals CK1 through CK5 are used as signals CLK. Five signals from 1 through CLK8 are used.

[0199] Specifically, in buffer BUF_8m+1, signals CK1 through CK5 are used, and signal CL Signals K1 through CLK5 are used, respectively. In buffer BUF_8m+2, signal C K1 to signal CK5, signals CLK6 to signal CLK8, and signals CLK1 and C LK2 and the other are used respectively. In buffer BUF_8m+3, signals CK1 to signals Signals CLK3 through CLK7 are used as CK5, respectively. Buffer BUF In _8m+4, signals CK1 to CK5 are used, along with signal CLK8 and signal CLK1 to Signals CLK4 and CLK4 are used respectively. In buffer BUF_8m+5, signal CLK1 is used As signal CK5, signals CLK5 to CLK8 and signal CLK1 are used respectively. It can be there. In buffer BUF_8m+6, signals CK1 to CK5 are used as signals CL K2 through signal CLK6 are used respectively. In buffer BUF_8m+7, signal C K1 to signal CK5, signals CLK7 and CLK8, and signals CLK1 to signal C LK3 is used for each. In buffer BUF_8m, signals CK1 to CK5 Signals CLK4 through CLK8 are used as such.

[0200] Furthermore, in the shift register shown in Figure 8, each distribution connected to the buffer BUF_DUM The position of the line is schematically shown in Figure 9(B). As shown in Figure 9(B), buffer BUF_D In addition to the output signals from output terminals A and B of the sequential circuit 10, UM also receives the signal CK. Signal 1 and signal CK2 are input. In buffer BUF_DUM, signals CK1 and signal As CK2, any two of signals CLK1 through CLK8 are used. ru.

[0201] In buffer BUF_DUM, the signals used as signals CK1 and CK2 are from the preceding buffer It depends on the number of buffer BUF stages. For example, if there is a buffer BUF_8m+1 in the preceding stage... In this case, buffer BUF_DUM will use signals CK1 and CK2, and signal CLK6 And signal CLK7 is used respectively. In total, buffer BUF_DUM has signals CK1 and CK2, and signals CLK3 and The signal CLK4 is used in each case. If a buffer BUF_8m+3 exists in the preceding stage, In buffer BUF_DUM, signals CK1 and CK2 are used, and signals CLK8 and signal CLK1 is used in each case. If a buffer BUF_8m+4 exists in the preceding stage, In BUF_DUM, signals CK1 and CK2 are used as signals CLK5 and CL K6 is used in each case. If buffer BUF_8m+5 exists in the preceding stage, the buffer In BUF_DUM, signals CK1 and CK2 are used, and signals CLK2 and CLK3 are used. These are used respectively. If buffer BUF_8m+6 exists in the preceding stage, buffer BU In F_DUM, signals CK1 and CK2 are used, and signals CLK7 and CLK8 are used. Each is used. If buffer BUF_8m+7 exists in the preceding stage, buffer BUF_ In DUM, signals CK1 and CK2 are used, and signals CLK4 and CLK5 are used respectively. This is used. If buffer BUF_8m exists in the preceding stage, buffer BUF_DUM is used. In this case, signals CK1 and CK2 are used as signals CLK1 and CLK2, respectively. It can be done.

[0202] Furthermore, buffers BUF_1 through BUF_y are connected to output terminals OUT1 through OUT, respectively. It has a power terminal OUT5. All outputs of buffers BUF_1 to BUF_y Output signals GOUT1 to GOUTy are sent from power terminals OUT1 to OUT5. These are output respectively. Buffer BUF_DUM is output to output terminal DUMOUT1 and output terminal It has a child DUMOUT2.

[0203] Figure 9(C) shows a more specific example of the configuration of the buffer BUF. The BUF has five buffers 90. Each buffer 90 has an output from the sequential circuit 10. In addition to the output signals from terminal A and output terminal B, one of signals CK1 to CK5 Each of these is input. And each output terminal of the five buffers 90 is a buffer These correspond to output terminals OUT1 through OUT5 of the BUF.

[0204] In Figures 8, 9(A), and 9(C), the buffer BUF consists of five buffers 90. The example shows a case where there are multiple buffers, but the number of buffers BUF has is not five. It can be a number or a singular. The number of buffers 90 that buffer BUF has. The more there are, the smaller the number of sequential circuits 10 that the shift register can be, This reduces the area of ​​the drive circuit containing the shift register, enabling a narrower bezel for semiconductor display devices. It is possible.

[0205] Furthermore, Figure 9(D) shows a more specific example of the configuration of buffer BUF_DUM. The buffer BUF_DUM shown in D) has two buffers 90. In addition to the output signals from output terminals A and B of the sequential circuit 10_DUM, signal C Either K1 or signal CK2 is input to each. And two buffers Each output terminal of the A90 is connected to the output terminal OUT1 and output terminal OUT of the buffer BUF_DUM. This corresponds to each of the two. Note that in Figures 8, 9(B), and 9(D), the buffer BUF The example shows that _DUM has two buffers 90, but buffer BUF_DU The number of buffers 90 that M possesses may be more than two, or it may be singular.

[0206] Figure 10 shows a more specific configuration example of buffer 90. The buffer 90 shown in Figure 10 is It has transistors 91 to 93. Transistor 91 has a gate at potential V It is connected to the given wiring of DD. Also, transistor 91 is source and slave. One end of the circuit is connected to output terminal B of the sequential circuit 10_DUM, and the source and drain are connected. The other end is connected to the gate of transistor 92. Transistor 92 has a source and One of the drains is connected to one of the output terminals OUT1 through OUT5 of the buffer 90. It is connected to one (shown as output terminal OUT in Figure 10), and the source and drain On the other hand, if any one of signals CK1 through CK5 (shown as signal CK in Figure 10) It is connected to the input wiring. Transistor 93 has a gate that is connected to sequential circuit 10_DU It is connected to output terminal A of M. Transistor 93 has a source and drain. One side is connected to the wiring to which the potential VSS is applied, and the other side of the source and drain is output One of the power terminals OUT1 to output terminal OUT5 (as shown as output terminal OUT in Figure 10) It is connected to (shown).

[0207] Furthermore, in one aspect of the present invention, a transistor to which the signal CK is applied to the source and the other drain. ZISTA92 is electrically connected and overlaps with a semiconductor film in between, It shall have a gate electrode. A pair of electrically connected gate electrodes are connected to transistor 9. By providing it at 2, even if a positive fixed charge is generated near the surface of the element substrate, the fixed charge will This prevents negative charges from being generated near the surface of the semiconductor film, and the threshold voltage of transistor 92 This can prevent the pressure from shifting in the negative direction. Therefore, the buffer BUF extends This can improve the reliability of semiconductor devices using a buffer (BUF).

[0208] Furthermore, by electrically connecting a pair of gate electrodes, one gate electrode can be electrically connected to only one of the pair. Unlike when a constant potential is applied, the same potential is applied to the pair of gate electrodes, so The Nellum formation region increases, which allows for an increase in the drain current of transistor 92. Therefore, it is possible to keep the size of transistor 92 small while suppressing the decrease in on-current. Therefore, the area of ​​the buffer (BUF), and by extension the drive circuit using the buffer (BUF), can be kept small. This is possible. In particular, the transistor 92 provided on the output side of the buffer BUF is Because a larger current supply capacity is required than that of transistor 91, transistor 92 is as described above. By having a pair of gate electrodes, the same configuration can be applied to transistor 91. Compared to a combined design, the effect of reducing the area of ​​the buffer (BUF) or drive circuit is significant. .

[0209] Furthermore, by providing a pair of electrically connected gate electrodes, a depletion layer is not formed in the semiconductor film. Because the value decreases, the S value (subthreshold value) of transistor 92 can be improved. ru.

[0210] <About semiconductor films> Furthermore, impurities such as water or hydrogen, which act as electron donors, are reduced, and acid Purified oxide semiconductors (purified Oxi) are achieved by reducing elemental defects. Because there are few carrier sources, type i (intrinsic semiconductor) It can be made to be as close as possible to type i (or body). Therefore, a highly purified oxide semiconductor can be produced. Transistors with a channel-forming region in the film have significantly low off-current and high reliability. Furthermore, the transistor in which a channel formation region is formed in the oxide semiconductor film has a threshold voltage. It tends to exhibit electrical characteristics where the voltage is positive (also known as normally-off characteristics).

[0211] Specifically, a transistor having a channel formation region in a highly purified oxide semiconductor film The small current can be proven through various experiments. For example, if the channel width is 1 × 1 0 6 Even with a μm element and a channel length of 10 μm, the voltage between the source electrode and the drain electrode When the drain voltage is in the range of 1V to 10V, the off-current is measured by the semiconductor parameter analyzer. Below the measurement limit of the riser, i.e., 1 × 10⁻⁶ -13 It is possible to obtain the characteristic of being A or less. In this case, the off-current normalized by the transistor channel width is 100 Hz A / μm or less. It can be seen that there is a capacitive element and a transistor are connected so that the current flows into the capacitive element or The off-current is measured using a circuit that controls the charge flowing out of a capacitive element with the transistor. The measurement was performed using a highly purified oxide semiconductor film as the channel of the transistor. Used in the formation region, the transistor's off state is determined from the change in the amount of charge per unit time of the capacitive element. The current was measured. As a result, the voltage between the source and drain electrodes of the transistor was 3V. In some cases, it was found that even smaller off-currents, such as tens of yA / μm, can be obtained. Therefore Therefore, transistors that use a highly purified oxide semiconductor film in the channel formation region are off-voltage. The current is significantly lower compared to transistors using crystalline silicon.

[0212] Furthermore, when using an oxide semiconductor film as the semiconductor film, the oxide semiconductor must be at least It is preferable that the oxide semiconductor contains indium (In) or zinc (Zn). As a stabilizer to reduce variations in the electrical characteristics of transistors using, In addition to these, it is preferable to have gallium (Ga). Also, as a stabilizer, It is preferable to have s(Sn). Also, hafnium(Hf) is used as a stabilizer. It is preferable to have it. Furthermore, it is preferable to have aluminum (Al) as a stabilizer. This is preferable. It is also preferable to include zirconium (Zr) as a stabilizer.

[0213] Among oxide semiconductors, In-Ga-Zn oxides and In-Sn-Zn oxides are carbon Unlike silicon dioxide, gallium nitride, or gallium oxide, sputtering and wet processes This makes it possible to fabricate transistors with excellent electrical characteristics, and offers superior mass-producibility. These are some of the advantages. Also, unlike silicon carbide, gallium nitride, or gallium oxide The above In-Ga-Zn oxide is used to form transistors with excellent electrical properties on a glass substrate. It is possible to manufacture these. Furthermore, it can accommodate larger substrate sizes.

[0214] Also, other stabilizers include lanthanides such as lanthanum (La) and cerium ( Ce, praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), hol Mium (Ho), Erbium (Er), Thulium (Tm), Ytterbium (Yb), Lu It may contain one or more types of tecium (Lu).

[0215] For example, as oxide semiconductors, indium oxide, gallium oxide, tin oxide, zinc oxide, I n-Zn oxides, Sn-Zn oxides, Al-Zn oxides, Zn-Mg oxides, S n-Mg oxides, In-Mg oxides, In-Ga oxides, In-Ga-Zn oxides Materials (also written as IGZO), In-Al-Zn oxides, In-Sn-Zn oxides, Sn-Ga-Zn oxides, Al-Ga-Zn oxides, Sn-Al-Zn oxides, I n-Hf-Zn oxides, In-La-Zn oxides, In-Pr-Zn oxides, In -Nd-Zn oxides, In-Ce-Zn oxides, In-Sm-Zn oxides, In- Eu-Zn oxides, In-Gd-Zn oxides, In-Tb-Zn oxides, In-D y-Zn oxides, In-Ho-Zn oxides, In-Er-Zn oxides, In-Tm -Zn oxides, In-Yb-Zn oxides, In-Lu-Zn ​​oxides, In-Sn- Ga-Zn oxides, In-Hf-Ga-Zn oxides, In-Al-Ga-Zn oxides Substances, In-Sn-Al-Zn oxides, In-Sn-Hf-Zn oxides, In-Hf- Al-Zn oxides can be used.

[0216] For example, an In-Ga-Zn oxide is an oxide containing In, Ga, and Zn. This is about taste, and the ratio of In, Ga, and Zn is not important. Also, metal elements other than In, Ga, and Zn are not considered. It may contain. In-Ga-Zn oxides have sufficiently high resistance in the absence of an electric field and are off-electric. It is possible to significantly reduce the flow rate, and it also has high mobility.

[0217] For example, high mobility can be obtained relatively easily with In-Sn-Zn oxides. However, Furthermore, even with In-Ga-Zn oxides, mobility can be increased by reducing the bulk defect density. It is possible to do so.

[0218] The structure of oxide semiconductor films will be described below.

[0219] Oxide semiconductor films are broadly classified into single-crystal oxide semiconductor films and non-single-crystal oxide semiconductor films. Single-crystal oxide semiconductor films include amorphous oxide semiconductor films, microcrystalline oxide semiconductor films, and polycrystalline oxide films. This refers to monocrystalline semiconductor films, CAAC-OS films, etc.

[0220] Amorphous oxide semiconductor films have an irregular arrangement of atoms within the film and do not contain crystalline components. It is a crystalline semiconductor film. Even in minute regions, it does not have crystalline areas; the entire film has a completely amorphous structure. Oxide semiconductor films are a typical example.

[0221] Microcrystalline oxide semiconductor films are, for example, microcrystals (nanocrystals) with a size of 1 nm to less than 10 nm. It is also called. ) contains. Therefore, microcrystalline oxide semiconductor films are more fundamental than amorphous oxide semiconductor films. The arrangement of the microcrystalline elements is highly regular. Therefore, microcrystalline oxide semiconductor films are superior to amorphous oxide semiconductor films. It also has the characteristic of having a low defect level density.

[0222] CAAC-OS film is one of the oxide semiconductor films having multiple crystalline regions, and most of the bonds The crystal portion is small enough to fit within a cube with sides less than 100 nm. Therefore, CAAC-O The crystalline portion contained in the S film is within a cube with sides less than 10 nm, less than 5 nm, or less than 3 nm. This also includes cases where the size fits within the given space. CAAC-OS films have fewer defects than microcrystalline oxide semiconductor films. It is characterized by a low void density. CAAC-OS film is examined using a transmission electron microscope (TEM:T). Observed using a transmission electron microscope. Then, we can confirm the clear boundaries between the crystalline parts, that is, the grain boundaries (also called grain boundaries). It is not possible. Therefore, the CAAC-OS film has an electron mobility due to grain boundaries. It can be said that a decline is unlikely to occur.

[0223] The CAAC-OS film was observed by TEM from a direction roughly parallel to the sample surface (cross-sectional TEM observation). ) This confirms that metal atoms are arranged in layers in the crystalline region. Each layer has irregularities on the surface (also called the surface to be formed) or the upper surface that forms the CAAC-OS film. The shape reflects this, and the elements are arranged parallel to the surface or top surface of the CAAC-OS film.

[0224] In this specification, "parallel" means that two straight lines are positioned at an angle of -10° or more and 10° or less. This refers to a state where something is positioned vertically. Therefore, it also includes cases where the angle is between -5° and 5°. This refers to a state where two straight lines are positioned at an angle of 80° to 100°. Therefore, This also includes cases where the angle is between 85° and 95°.

[0225] On the other hand, the CAAC-OS film was observed by TEM from a direction roughly perpendicular to the sample surface (planar TEM). (M observation) In the crystalline region, metal atoms are arranged in a triangular or hexagonal shape. This can be confirmed. However, no regularity is observed in the arrangement of metal atoms between different crystalline regions. stomach.

[0226] Cross-sectional TEM observation and planar TEM observation revealed that the crystalline portion of the CAAC-OS film exhibits orientation. You can tell they are there.

[0227] X-ray diffraction (XRD) applied to the CAAC-OS film. When structural analysis is performed using this method, for example, a CAAC-OS film having InGaZnO4 crystals is found. In the out-of-plane analysis, the diffraction angle (2θ) shows a peak near 31°. This peak may appear. This peak is attributed to the (009) plane of the InGaZnO4 crystal. Therefore, the crystals of the CAAC-OS film have c-axis orientation, and the c-axis is generally aligned with the surface to be formed or the upper surface. It can be confirmed that it is facing in a nearly vertical direction.

[0228] On the other hand, in-pl X-rays are incident on the CAAC-OS film from a direction approximately perpendicular to the c-axis. In analysis using the ANE method, a peak may appear when 2θ is around 56°. This peak is It is attributed to the (110) plane of the InGaZnO4 crystal. Single crystal oxidation of InGaZnO4 For a solid semiconductor film, fix 2θ to around 56°, and use the normal vector of the sample surface as the axis (φ axis). When the sample is rotated while the analysis (φ scan) is performed, the crystal plane equivalent to the (110) plane is found. Six attributed peaks are observed. In contrast, in the case of the CAAC-OS film, 2θ is set to 5 Even when fixed at approximately 6° and scanned using the φ scan function, no clear peak appears.

[0229] From the above, it can be concluded that in CAAC-OS films, the orientation of the a-axis and b-axis is inconsistent between different crystalline regions. It is a rule, but it has c-axis orientation and the c-axis is parallel to the normal vector of the surface to be formed or the upper surface. It can be seen that it is facing in a certain direction. Therefore, it is arranged in layers as confirmed by the aforementioned cross-sectional TEM observation. Each layer of arranged metal atoms is a plane parallel to the ab-plane of the crystal.

[0230] The crystalline portion is formed when the CAAC-OS film is deposited, or when crystallization treatment such as heat treatment is performed. It is formed when this occurs. As mentioned above, the c-axis of the crystal is the surface on which the CAAC-OS film is formed or It is oriented in a direction parallel to the normal vector of the upper surface. Therefore, for example, the shape of the CAAC-OS film When the shape is altered by etching or other means, the c-axis of the crystal becomes the surface on which the CAAC-OS film is formed. Alternatively, it may not be parallel to the normal vector of the top surface.

[0231] Furthermore, the degree of crystallinity in the CAAC-OS film does not need to be uniform. For example, the CAAC-OS film When the crystalline portion is formed by crystal growth from near the upper surface of the CAAC-OS film, the upper surface The nearby region may have a higher degree of crystallinity than the region near the surface being formed. Also, CAA When impurities are added to a C-OS film, the degree of crystallinity in the region where the impurities are added changes, and some areas Regions with different degrees of crystallinity may also be formed.

[0232] Furthermore, the out-of-plane method for CAAC-OS films containing InGaZnO4 crystals. Analysis revealed that in addition to a peak near 2θ = 31°, a peak also appeared near 2θ = 36°. In some cases, this may occur. Peaks near 36° 2θ indicate c-axis orientation in a portion of the CAAC-OS film. This indicates that it contains crystals that do not have [the specified characteristic]. The CAAC-OS film has 2θ near 31°. It is preferable that a peak is observed, and that no peak is observed near 36° for 2θ.

[0233] Transistors using CAAC-OS film exhibit changes in electrical characteristics due to irradiation with visible light or ultraviolet light. The dynamics are small. Therefore, this transistor is highly reliable.

[0234] Note that oxide semiconductor films include, for example, amorphous oxide semiconductor films, microcrystalline oxide semiconductor films, and CA The AC-OS film may be a multilayer film having two or more types.

[0235] Furthermore, it is preferable to apply the following conditions for forming the CAAC-OS film.

[0236] By reducing the inclusion of impurities during film formation, it is possible to suppress the disruption of the crystalline state due to impurities. For example, the concentration of impurities present in the processing room (hydrogen, water, carbon dioxide, and nitrogen, etc.) It would be good to reduce it. Also, it would be good to reduce the impurity concentration in the film formation gas. Specifically, the dew point is A film-forming gas with a temperature of -80°C or lower, preferably -100°C or lower, is used.

[0237] Furthermore, by increasing the substrate heating temperature during film deposition, the sputtering particles can be prevented from migrating after reaching the substrate. A reaction occurs. Specifically, the substrate heating temperature is preferably between 100°C and 740°C. The film is deposited at a temperature between 200°C and 500°C. By increasing the substrate heating temperature during film deposition, the flat When plate-shaped or pellet-shaped sputtering particles reach the substrate, migration occurs on the substrate. A reaction occurs, and the flat surface of the sputtered particles adheres to the substrate.

[0238] Furthermore, by increasing the oxygen content in the deposition gas and optimizing the power, plasma damage during film deposition can be reduced. It is preferable to reduce this. The oxygen content in the film-forming gas is 30% by volume or more, preferably 100% by volume. Let the product be %.

[0239] As an example of a target, an In-Ga-Zn oxide target is shown below.

[0240] InO X powder, GaO Y Powder and ZnO Z The powders are mixed in a predetermined molar ratio and then subjected to pressure treatment. By heat treatment at temperatures between 1000°C and 1500°C, polycrystalline In-Ga - A Zn-based oxide target is used. X, Y, and Z are arbitrary positive numbers. Here, A constant molar ratio is, for example, InO X powder, GaO Y Powder and ZnO Z The powder is in a 2:1 ratio. 3, 2:2:1, 8:4:3, 3:1:1, 1:1:1, 4:2:3 or 3:1:2 Yes, it exists. Note that the type of powder and the molar ratio in which they are mixed will vary depending on the target being prepared. You can change it as needed.

[0241] Alkali metals are not elements that make up oxide semiconductors, and are therefore impurities. Earth metals also become impurities when they are not elements that constitute oxide semiconductors. Among alkali metals, Na is used when the insulating film in contact with the oxide semiconductor film is an oxide. Na diffuses into the insulating film. + This is the result. Furthermore, Na is present in the oxide semiconductor film. It breaks the bond between the metal and oxygen that make up the conductor, or intervenes in that bond. For example, normalization due to a shift in the threshold voltage in the negative direction, low mobility In lower-grade transistors, the electrical characteristics deteriorate, and variations in characteristics also occur. Specifically, the measured Na concentration by secondary ion mass spectrometry was 5 × 10⁻⁶. 16 / cm 3 below Preferably 1 × 10 16 / cm 3 More preferably 1 × 10 15 / cm 3 The following It would be good to do so. Similarly, the measured value of Li concentration is 5 × 10 15 / cm 3 The following is preferably 1×1 0 15 / cm 3 The following is recommended. Similarly, the measured value of the K concentration is 5 × 10 15 / cm 3 Below Below, preferably 1 × 10 15 / cm 3 The following is recommended.

[0242] Furthermore, when metal oxides containing indium are used, the bond energy with oxygen is Larger silicon and carbon atoms than indium break the bond between indium and oxygen, resulting in an oxygen deficiency. This can form. Therefore, if silicon or carbon is mixed into the oxide semiconductor film, Similar to alkali metals and alkaline earth metals, degradation of the transistor's electrical characteristics occurs. It is prone to stiffness. Therefore, it is desirable that the concentrations of silicon and carbon in oxide semiconductor films be low. Specifically, the measured values ​​of C concentration or Si concentration by secondary ion mass spectrometry. is 1 × 10 18 / cm 3 The following is preferable. With the above configuration, the electrical characteristics of the transistor This can prevent degradation of performance and improve the reliability of semiconductor devices.

[0243] Furthermore, depending on the conductive material used for the source electrode and drain electrode, the source electrode and The metal in the drain electrode may extract oxygen from the oxide semiconductor film. In this case, acid In the semiconductor film, the regions in contact with the source electrode and drain electrode are affected by the formation of oxygen vacancies. It will be converted to the n-type.

[0244] Because the n-type region functions as either a source region or a drain region, in oxide semiconductors... This can reduce the contact resistance between the film and the source and drain electrodes. Therefore, the formation of an n-type region increases the transistor's mobility and on-current. This makes it possible to achieve high-speed operation of semiconductor devices using transistors. It is possible.

[0245] Furthermore, the extraction of oxygen by metal in the source electrode and drain electrode is performed by the source electrode and drain electrode. This can occur when forming the rain electrode by sputtering or other methods, and the source electrode and the do This can also occur due to the heat treatment performed after the formation of the rain electrode.

[0246] Furthermore, the n-type region is made of a conductive material that readily bonds with oxygen, and is used as both the source electrode and the drain electrode. Using it makes it easier to form. Examples of the conductive materials mentioned above include Al and C. Examples include r, Cu, Ta, Ti, Mo, and W.

[0247] Furthermore, oxide semiconductor films are not necessarily composed of a single metal oxide film, but rather are stacked It may be composed of multiple metal oxide films. For example, the first to third metal oxide films may be arranged sequentially. In the case of semiconductor films stacked on a substrate, the first metal oxide film and the third metal oxide film are the second The metal oxide film contains at least one of the metal elements that make up the metal oxide film, and the conduction band The edge energy is 0.05 eV or more, 0.07 eV or more, and 0.07 eV or more than the second metal oxide film. 1 eV or more, or 0.15 eV or more, and 2 eV or less, 1 eV or less, 0.5 eV or less, The first oxide film is below 0.4 eV, close to the vacuum level. Furthermore, the second metal oxide film is small Even if indium is not present, it is preferable because it increases carrier mobility.

[0248] When a transistor has a semiconductor film with the above configuration, applying a voltage to the gate electrode allows the transistor to... When an electric field is applied to a semiconductor film, the second gold layer of the semiconductor film, which has low energy at the lower end of the conduction band, is formed. A channel region is formed in the metal oxide film. That is, between the second metal oxide film and the gate insulating film. A third metal oxide film is provided in between, which separates the gate insulating film from the third A channel region can be formed in the metal oxide film of type 2.

[0249] Furthermore, the third metal oxide film is composed of at least one of the metal elements that make up the second metal oxide film. Because it contains as a component, at the interface between the second metal oxide film and the third metal oxide film, Scattering is less likely to occur. Therefore, carrier movement is less likely to be hindered at the interface, The field-effect mobility of the transistor increases.

[0250] Furthermore, when an interface state is formed at the interface between the second metal oxide film and the first metal oxide film, the interface Because a channel region is formed in the neighboring region, the threshold voltage of the transistor fluctuates. However, the first metal oxide film has fewer metal elements in the second metal oxide film. Since both contain one of the components, at the interface between the second metal oxide film and the first metal oxide film Therefore, interface states are less likely to form. Thus, with the above configuration, the threshold voltage of the transistor, etc. Variations in electrical characteristics can be reduced.

[0251] Furthermore, the presence of impurities between the metal oxide films creates a carrier flow at the interface of each film. Multiple oxide semiconductor films are stacked to prevent the formation of interfering interface states. This is desirable. If impurities are present between the stacked metal oxide films, the metal oxide films will The energy continuity at the lower end of the conduction band is lost, and near the interface, carriers are traction This is because they are either removed or eliminated through recombination. By reducing this, multiple metal oxide films having at least one main metal component together are created. Rather than simply stacking layers, continuous bonding (in this case, especially the energy at the lower end of the conduction band between each film) is preferable. This makes it easier for a state with a continuously changing U-shaped well structure to form.

[0252] To form continuous bonds, a multi-chamber deposition apparatus equipped with a load-lock chamber is required. (Using a sputtering device) to continuously stack each film without exposing it to the atmosphere. This is necessary. Each chamber in the sputtering apparatus is impure for oxide semiconductors. To remove as much of the water and other materials as possible, an adsorption-type vacuum pump such as a cryopump is used. Using high vacuum evacuation (5×10 -7 Pa~1×10 -4 It is preferable to do so (up to approximately Pa). Alternatively, a turbomolecular pump and a cold trap can be combined to run from the exhaust system to the chamber. It is preferable to prevent gas from flowing back into the container.

[0253] To obtain high-purity, intrinsic oxide semiconductors, it is not enough to simply evacuate each chamber to a high vacuum. Furthermore, increasing the purity of the gas used in sputtering is also important. The oxygen gas used as the above gas The dew point of the argon gas is set to -40°C or lower, preferably -80°C or lower, more preferably - By keeping the temperature below 100°C and increasing the purity of the gas used, moisture and other substances are prevented from being absorbed into the oxide semiconductor film. This can prevent it from being incorporated as much as possible. Specifically, the second metal oxide film is In- In the case of M-Zn oxide (where M is Ga, Y, Zr, La, Ce, or Nd), the second metal In a target used to form an oxide film, the atomic ratio of metal elements is In:M: If Zn = x1:y1:z1, then 、 x1 / y1 is between 1 / 3 and 6, and also between 1 and 6. The following conditions apply, and it is preferable that z1 / y1 is between 1 / 3 and 6, and moreover, between 1 and 6. It seems so. Furthermore, by setting z1 / y1 to between 1 and 6, the second metal oxide film is CA AC-OS films are more easily formed. Typical examples of atomic ratios of target metal elements include , In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=3 There are options such as :1:2, etc.

[0254] Specifically, the first metal oxide film and the third metal oxide film are In-M-Zn oxide (where M is G In the case of a, Y, Zr, La, Ce, or Nd, the first metal oxide film, the third metal oxide In a target used for forming a metal film, the atomic ratio of metal elements is In:M:Zn Let =x2:y2:z2 、 x2 / y2 <x1 / y1であって、z2 / y2は、1 / 3 It is preferable that z2 / y2 be 6 or less, and more preferably 1 or more and 6 or less. By doing the following, the CAAC-OS film is formed as the first metal oxide film and the third metal oxide film. It becomes easier to form. A typical example of the atomic ratio of the target metal elements is In:M:Z n=1:3:2, In:M:Zn=1:3:4, In:M:Zn=1:3:6, In:M Examples include Zn=1:3:8.

[0255] The thickness of the first metal oxide film and the third metal oxide film is between 3 nm and 100 nm. Preferably, the thickness of the second metal oxide film is 3nm or more and 50nm or less. m or more and 200 nm or less, preferably 3 nm or more and 100 nm or less, and more preferably The range is between 3nm and 50nm.

[0256] In a three-layer semiconductor film, the first to third metal oxide films are amorphous. It can take both crystalline and non-crystalline forms. However, the second metal oxide in which the channel region is formed The crystalline nature of the film allows for stable electrical characteristics to be imparted to the transistor. Therefore, the second metal oxide film is preferably crystalline.

[0257] The channel formation region is the part of the transistor's semiconductor film that overlaps with the gate electrode. This refers to the region sandwiched between the source electrode and the drain electrode. The channel region is also defined as the channel region. This refers to the region within the Nell formation area where electric current primarily flows.

[0258] For example, the first metal oxide film and the third metal oxide film are shaped by the sputtering method. When using the resulting In-Ga-Zn oxide film, the first metal oxide film and the third metal acid For the deposition of oxide films, In-Ga-Zn oxides (In:Ga:Zn=1:3:2 [number of atoms]) are used. A target with a ratio of [ ] can be used. The film deposition conditions are, for example, using as the deposition gas. Using 30 sccm of argon gas and 15 sccm of oxygen gas, at a pressure of 0.4 Pa, the substrate temperature was... The temperature should be set to 200°C and the DC power to 0.5kW.

[0259] Furthermore, when the second metal oxide film is a CAAC-OS film, the deposition of the second metal oxide film is required. It is an In-Ga-Zn oxide (In:Ga:Zn = 1:1:1 [atomic ratio]), It is preferable to use a target containing a polycrystalline In-Ga-Zn oxide. Film deposition conditions For example, 30 sccm of argon gas and 15 sccm of oxygen gas are used as the film-forming gas. The pressure can be set to 0.4 Pa, the substrate temperature to 300°C, and the DC power to 0.5 kW. Cut.

[0260] Furthermore, the transistor may have a structure in which the edges of the semiconductor film are sloped, The body membrane may have a structure in which the ends are rounded.

[0261] Furthermore, when using a semiconductor film having multiple stacked metal oxide films in a transistor, Even if the source electrode and drain electrode are in contact with each other, the regions in contact with each other may be n-type. This improves the mobility and on-current of transistors, and enables the creation of semiconductor devices using transistors. This enables high-speed operation. Furthermore, a semiconductor having multiple stacked metal oxide films When a conductive film is used in a transistor, the region that becomes n-type is the second gold region which becomes the channel region. Reaching the oxide film increases the transistor's mobility and on-current, thus improving the semiconductor's performance. This is more preferable for achieving even faster operation of the device.

[0262] <Manufacturing Method> Next, using a liquid crystal display device as an example, a method for manufacturing a semiconductor display device according to one aspect of the present invention will be described. An example will be explained using Figures 11 to 14. Note that in Figures 11 to 14, The transistor 56 in the pixel 55 shown in 5, and the transistor in the drive circuit shown in Figure 2 A method for fabricating an element substrate having a zista 20 will be described.

[0263] As shown in Figure 11(A), after forming a conductive film on the substrate 31, the conductive film is etched. The conductive film 21 and conductive film 40 are formed by processing (patterning) the shape using the above methods. .

[0264] The substrate 31 is preferably a substrate with sufficient heat resistance to withstand subsequent manufacturing processes. For example, glass substrates, quartz substrates, ceramic substrates, sapphire substrates, etc., are used.

[0265] The conductive films 21 and 40 include aluminum, titanium, chromium, cobalt, and nickel. Ruthenium, copper, yttrium, zirconium, molybdenum, ruthenium, silver, tantalum, and tan It is possible to use a film made of a conductive material containing one or more types of gusten, with one or more layers laminated together. For example, the conductive film 21 and conductive film 40 are formed by laminating a copper film on a tungsten nitride film. A conductive film or a single-layer tungsten film can be used. In this embodiment, conductive film 21 Furthermore, the conductive film 40 shall be a tungsten film with a thickness of 200 nm.

[0266] Next, as shown in Figure 11(B), insulating film 2 covers conductive film 21 and conductive film 40. After forming 2, an oxide semiconductor film 23, an oxide semiconductor film 41, and an oxide film are placed on the insulating film 22. A semiconductor film 42a is formed. Note that the oxide semiconductor film 23 is formed in a position that overlaps with the conductive film 21. The oxide semiconductor film 41 is then formed in a position that overlaps with the conductive film 40.

[0267] The insulating film 22 can be aluminum oxide, magnesium oxide, silicon oxide, silicon oxide nitride, Silicon nitride, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, gallium oxide One or more of the following: lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. The insulating film can be used as a single layer or in a stacked configuration.

[0268] In this specification, oxidnitrides are defined as having a composition in which the oxygen content is greater than the nitrogen content. The term refers to materials with a high nitrogen content, and nitride oxides are materials whose composition contains more nitrogen than oxygen. To point.

[0269] For example, if the insulating film 22 has a two-layer structure, the first layer will be a silicon nitride film and the second layer will be silicon oxide A multilayer film can be formed as a thin film. The second layer, a silicon oxide film, can be a silicon oxide nitride film. Furthermore, the first silicon nitride film can be a silicon oxide nitride film. In this embodiment, A silicon nitride film with a thickness of 400 nm and a silicon oxidizide film with a thickness of 50 nm are sequentially stacked to create an insulating layer. It is used as the border film 22.

[0270] It is preferable to use a silicon oxide film with a low defect density. Specifically, electron speed The g value is 2.0 in electron spin resonance (ESR). The spin density of the spins originating from the O1 signal is 3 × 10 17 spins / cm 3 The following are preferred Or 5 x 10 16 spins / cm 3 The following silicon oxide film will be used. The silicon oxide film is, It is preferable to use a silicon oxide film containing an excess of oxygen. The silicon nitride film contains hydrogen and ammonia. A silicon nitride film with low emission levels is used. The amount of hydrogen and ammonia released is measured using TDS (Therm al Desorption Spectroscopy (temperature-controlled desorption gas spectroscopy) for analysis You can measure it that way.

[0271] Oxide semiconductor film 23, oxide semiconductor film 41, and oxide semiconductor film 42a are oxide semiconductor A conductive film can be used. Acid used as oxide semiconductor film 23 and oxide semiconductor film 41 When a large amount of hydrogen is present in an oxide semiconductor film, it combines with the oxide semiconductor, causing the hydrogen to... Some of them become donors, generating electrons, which are carriers. This causes transistor 2 The threshold voltage of transistor 0 and transistor 56 shifts to the negative direction. Therefore, oxidation After the formation of the material semiconductor film, a dehydration treatment (dehydrogenation treatment) is performed to remove the oxide semiconductor film. It is preferable to remove hydrogen or water to minimize the presence of impurities.

[0272] In this embodiment, the metal oxide has an atomic ratio of metal elements of In:Ga:Zn=3:1:2. A 35 nm thick In-Ga-Zn oxide semiconductor was formed using the constructed target. The conductive films are oxide semiconductor film 23, oxide semiconductor film 41, and oxide semiconductor film 42a. Use.

[0273] The thicknesses of oxide semiconductor film 23, oxide semiconductor film 41, and oxide semiconductor film 42a are 1 nm. More preferably 1 nm to 50 nm, and even more preferably 1 nm or less It is preferable that the wavelength be 30 nm or less, and more preferably between 3 nm and 20 nm.

[0274] Furthermore, the dehydration treatment (dehydrogenation treatment) of the oxide semiconductor film removes acid from the oxide semiconductor film. The amount of element may decrease. Therefore, dehydration treatment (dehydrogenation treatment) of oxide semiconductor films is necessary. To compensate for the increased oxygen deficiency caused by ), a process is performed to add oxygen to the oxide semiconductor film. This is preferable.

[0275] Thus, oxide semiconductor films undergo dehydration treatment (dehydrogenation treatment) to remove hydrogen or water. It is removed and the oxygen deficiency is compensated for by oxygenation treatment, resulting in type i (true) or It is possible to create an oxide semiconductor film that is very close to type i and is essentially type i (intrinsic).

[0276] Next, oxide semiconductor film 23, oxide semiconductor film 41, oxide semiconductor film 42a and insulation After forming a conductive film on film 22, the shape of the conductive film is processed by etching or the like. Furthermore, conductive films 24 and 25 that are in contact with the oxide semiconductor film 23, and oxide semiconductor film 41 A conductive film 43 and a conductive film 44 are formed in contact (see Figure 12(A)). Conductive film 24 and conductive The conductive film 25, conductive film 43, and conductive film 44 are made of the same conductive material as conductive film 21 and conductive film 40. You can use the fee.

[0277] In this embodiment, a tungsten film with a thickness of 50 nm and an aluminum film with a thickness of 400 nm are used. Then, a titanium film with a thickness of 200 nm is sequentially stacked to form conductive film 24 and conductive film 25, and conductive These are used as film 43 and conductive film 44.

[0278] Next, an oxide film or insulating film is formed to cover the substrate 31. In Figure 12(B), An example is given where insulating film 26 and insulating film 27 are formed by stacking them in order.

[0279] The insulating film 27 is preferably formed continuously after the insulating film 26 has been formed, without exposure to the atmosphere. It is not possible to open the insulating film 26 to the atmosphere, and the flow rate of the raw material gas, pressure, high-frequency power and By adjusting the substrate temperature to one degree or more, the insulating film 27 is continuously formed, thereby forming the insulating film 26 and Furthermore, the concentration of impurities at the interface in the insulating film 27 can be reduced, and the insulating film 27 can also be contained It is possible to transfer the oxygen contained in the oxide semiconductor film 23 and the oxide semiconductor film 41. This makes it possible to reduce the amount of oxygen vacancies in the oxide semiconductor film 23 and the oxide semiconductor film 41.

[0280] A substrate placed in the vacuum-evacuated processing chamber of a plasma CVD apparatus is subjected to temperatures of 180°C to 400°C. More preferably, the temperature is maintained between 200°C and 370°C, and the raw material gas is introduced into the processing chamber. The pressure inside the processing chamber is set to 30 Pa or more and 250 Pa or less, more preferably 40 Pa or more. The pressure is kept below 200 Pa, and high-frequency power is supplied to electrodes installed in the processing chamber. A silicon oxide film or a silicon oxide-nitride film is formed as the edge film 26.

[0281] As the raw material gas for the insulating film 26, a silicon-containing depositing gas and an oxidizing gas are used. This is preferable. Typical examples of silicon-containing depositing gases include silane, disilane, and trisilane. Examples include fluoride silanes. Oxidizing gases include oxygen, ozone, nitrous oxide, and carbon dioxide. It contains nitrogen, etc.

[0282] By using the above conditions, an oxide insulating film that permeates oxygen can be formed as the insulating film 26. This is possible. In addition, by providing the insulating film 26, the process of forming the insulating film 27 which is formed later can be improved. Damage to oxide semiconductor film 23, oxide semiconductor film 41, and oxide semiconductor film 42a It can be reduced.

[0283] Furthermore, by increasing the amount of oxidizing gas relative to the silicon-containing sedimentary gas to more than 100 times, It is possible to reduce the hydrogen content in the edge film 26, and also in the insulating film 26. The dangling bonds can be reduced. Oxygen moving from the insulating film 27 may be captured by the dangling bonds contained in the insulating film 26. Therefore, the oxygen contained in the insulating film 27 can be efficiently transferred to the oxide semiconductor film 23 and the oxide semiconductor film 41 to fill the oxygen deficiencies contained in the oxide semiconductor film 23 and the oxide semiconductor film 41. As a result, the amount of hydrogen mixed into the oxide semiconductor film 23 and the oxide semiconductor film 41 can be reduced, and at the same time, the oxygen deficiencies contained in the oxide semiconductor film 23 and the oxide semiconductor film 41 can be reduced. Therefore, the negative shift of the threshold voltages of the transistor 20 and the transistor 56 can be suppressed, and the off-currents of the transistor 20 and the transistor 56 can be reduced, and the electrical characteristics of the transistor can be improved. In the present embodiment, as the insulating film 26, silane with a flow rate of 20 sccm and dinitrogen monoxide with a flow rate of 3000 sccm are used as source gases, the pressure in the processing chamber is 200 Pa, the substrate temperature is 350 °C, and

[0284] 100 W of high-frequency power is supplied to the parallel plate electrodes using a high-frequency power source of 27.12 MHz to form a silicon oxynitride film with a thickness of 50 nm by plasma CVD. Note that the plasma CVD apparatus is a parallel plate type plasma CVD apparatus with an electrode area of 6000 cm . When the supplied power is converted to the power per unit area (power density), it is 1.6 × 10 W / 2 cm -2 . Under these conditions, a silicon oxynitride film that allows oxygen to permeate can be formed. W / cm 2 .

[0285] The insulating film 27 is formed by placing a substrate placed in the evacuated processing chamber of the plasma CVD apparatus at 180 Maintain the temperature between 260°C and 360°C, more preferably between 180°C and 230°C, and place the raw material in the processing chamber. By introducing a gas, the pressure inside the processing chamber is set to between 100 Pa and 250 Pa, and more preferably... The pressure should be between 100 Pa and 200 Pa, and 0.17 W / cm² should be applied to the electrode installed in the processing chamber. 2 More than 0.5W / cm 2 More preferably, 0.25 W / cm² 2 More than 0.35W / c m 2 Under the following conditions for supplying high-frequency power, a silicon oxide film or silicon oxide nitride film is formed. ru.

[0286] As a film deposition condition for the insulating film 27, high-frequency power of the above power density is applied in a reaction chamber at the above pressure. By supplying it, the decomposition efficiency of the raw material gas in the plasma increases, and oxygen radicals increase, As the oxidation of the gas progresses, the oxygen content in the insulating film 27 becomes higher than the stoichiometric composition. However, if the substrate temperature is as described above, the bonding force between silicon and oxygen is weak. Therefore, some of the oxygen is removed by heating. As a result, more oxygen than is needed to satisfy the stoichiometric composition remains. It is possible to form an oxide insulating film that contains a small amount of oxygen, and in which some of the oxygen is removed by heating. Furthermore, insulating on oxide semiconductor film 23, oxide semiconductor film 41, and oxide semiconductor film 42a Because the film 26 is provided, in the process of forming the insulating film 27, the insulating film 26 is an oxide semiconductor It has the function of protecting the body film 23, the oxide semiconductor film 41, and the oxide semiconductor film 42a. As a result, the oxide semiconductor film 23, oxide semiconductor film 41, and oxide semiconductor film 42a are damaged. The insulating film 27 is formed using high-frequency power with high power density while reducing image. can.

[0287] In this embodiment, as the insulating film 27, silane with a flow rate of 160 sccm is used as the source gas, and the reaction is carried out at a pressure of 200 Pa and a substrate temperature of 220 °C in a reaction chamber. A high-frequency power supply of 27.12 MHz is used to supply 1500 W of high-frequency power to the parallel plate electrodes, and a silicon oxynitride film with a thickness of 4 00 nm is formed by plasma CVD. The plasma CVD apparatus is a parallel plate type plasma CVD apparatus with an electrode area of 6000 cm 2 When the supplied power is converted to power per unit area (power density), it is 2.5×10 W / cm -1 2. 2 Next, after forming at least the insulating film 27, a heat treatment is performed to move the oxygen contained in the insulating film 26 or the insulating film

[0288] 27 to the oxide semiconductor film 23 and the oxide semiconductor film 41 to compensate for the oxygen deficiency in the oxide semiconductor film 23 and the oxide semiconductor film 41. The heat treatment may be performed as a heat treatment for dehydrogenation or dehydration of the oxide semiconductor film 23 and the oxide semiconductor film 41. Specifically, in this embodiment, in a nitrogen and oxygen atmosphere, a heat treatment is performed at 350 °C for 1 hour.

[0289]

[0290] Through the above series of steps, the transistor 20 and the transistor 56 are formed.

[0290] How Next, as shown in FIG. 13(A), the insulating film 26 and the insulating film 27 are partially etched to form the opening 58. In the opening 58, a part

[0291] or all of the oxide semiconductor film 42a is exposed. Next, a nitride insulating film 28 is formed on the insulating film 26 and the insulating film 27 so as to cover the opening 58.The insulating film 29 is formed by stacking them in order. The nitride insulating film 28 is formed at the opening 58. It is in contact with the oxide semiconductor film 42a.

[0292] As the nitride insulating film 28, for example, silicon nitride, nitrogen formed by the CVD method, etc. Silicon oxide, aluminum nitride, aluminum nitride oxide, etc. can be used. (See above) The nitride insulating film 28 using the above material is an oxide insulating film such as silicon oxide or aluminum oxide. In contrast, external impurities, such as water, alkali metals, and alkaline earth metals, oxidize. This prevents diffusion into the material semiconductor film 23 and the oxide semiconductor film 41. By forming a nitride insulating film 28 in contact with the oxide semiconductor film 42a at 58, The conductivity of the oxide semiconductor film 42a can be increased. Film 42a is shown as metal oxide film 42 in Figure 13(B).

[0293] In this embodiment, the nitride insulating film 28 is a silane at a flow rate of 50 sccm and a flow rate of 500 The raw material gases are nitrogen at 0 sccm and ammonia at a flow rate of 100 sccm, and the pressure in the processing chamber is With a pressure of 100 Pa and a substrate temperature of 350°C, a 27.12 MHz high-frequency power supply was used. 0W (Power density is 1.6 × 10⁻⁶) -1 W / cm 2 ) High-frequency power is supplied to parallel plate electrodes A silicon nitride film with a thickness of 100 nm is formed using the supplied plasma CVD method.

[0294] The insulating film 29 uses an insulating film with a lower relative permittivity and lower internal stress than the nitride insulating film 28. It is desirable to do so. Specifically, as the insulating film 29, for example, a silicon oxide film, a silicon oxide nitride film Aluminum oxide and the like can be used.

[0295] For example, as the insulating film 29, a silicon oxide film formed by a CVD method using organic silane gas. It can be used. As an organic silane gas, ethyl silicate (TEOS: chemical formula Si( OC2H5)4), tetramethylsilane (TMS: chemical formula Si(CH3)4), tetramethylsilane Tylcyclotetrasiloxane (TMCTS), Octamethylcyclotetrasiloxane (O MCTS), hexamethyldisilazane (HMDS), triethoxysilane (SiH(OC) Using 2H5)3), trisdimethylaminosilane (SiH(N(CH3)2)3), etc. It is possible.

[0296] In this embodiment, the insulating film 29 is a film thickness formed by a CVD method using ethyl silicate. A 200 nm silicon oxide film is used.

[0297] Next, as shown in Figure 14(A), the nitride insulating film 28 and insulating film 29 are partially etched. By doing so, an opening 62 is formed. At least Part of it is exposed.

[0298] Next, as shown in Figure 14(B), a transparent conductive film is formed on the insulating film 29, followed by etching, etc. The conductive film 30 and conductive film 45 are formed by processing the shape of the transparent conductive film. The conductive film 30 is provided in a position that overlaps with the conductive film 21, with the oxide semiconductor film 23 in between. Furthermore, the conductive film 45 is connected to the conductive film 44 at the opening 62.

[0299] Furthermore, the transparent conductive film used to form the conductive film 21 and the conductive film 45 is an oxide film. Indium oxide containing tungsten, indium zinc oxide containing tungsten oxide, acid Indium oxide containing titanium dioxide, indium tin oxide containing titanium dioxide, indium tin Oxides, indium zinc oxide, zinc oxide, zinc oxide with added gallium, silicon oxide A conductive film containing added indium tin oxide or the like can be used.

[0300] In this embodiment, the film thickness is 100 nm and includes silicon dioxide-doped indium tin oxide, etc. A conductive film is used to form conductive films 21 and 45.

[0301] After forming the conductive films 21 and 45, a heat treatment may be performed. The heat treatment may be, for example, This can be done under a nitrogen atmosphere at 250°C for 1 hour.

[0302] Next, an orientation film 52 is formed on the conductive film 45 as shown in Figure 5 to form the element substrate. It is possible.

[0303] The alignment film 52 is formed using an organic resin such as polyimide or polyvinyl alcohol. This creates an orientation treatment, such as rubbing, to align liquid crystal molecules in a specific direction on its surface. A special treatment has been applied. The rubbing is made by wrapping a cloth such as nylon so that it is in contact with the orientation film 52. This can be done by rotating the roller and rubbing the surface of the orientation film 52 in a certain direction. Furthermore, by using inorganic materials such as silicon dioxide and without applying orientation treatment, orientation characteristics can be obtained by vapor deposition. It is also possible to directly form an orientation film 52 having the following properties.

[0304] After forming the element substrate and the opposing substrate, a liquid crystal layer is placed between substrate 31 and substrate 46, as shown in Figure 5. By encapsulating 53, a panel for a liquid crystal display device can be formed. The liquid crystal injection performed for this purpose may be done using a dispenser (dropping) method, or a dip method. A pumping system may also be used.

[0305] <Top view and cross-sectional view of a semiconductor display device> Next, taking a liquid crystal display device as an example, the appearance of a semiconductor display device according to one aspect of the present invention... Next, we will explain using Figure 15. Figure 15 shows substrate 4001 and substrate 4006 sealed with encapsulating material 40 This is a top view of the liquid crystal display device bonded by 05. Also, Figure 16 is the dashed line C in Figure 15. This corresponds to the cross-sectional view in 1-C2.

[0306] The pixel section 4002 and the pair of drive circuits 4004 are surrounded on the substrate 4001. A sealing material 4005 is provided. Also, a base is provided on the pixel section 4002 and the drive circuit 4004. A plate 4006 is provided. Therefore, the pixel unit 4002 and the drive circuit 4004 are connected to the substrate. It is sealed by 4001, the sealing material 4005, and the substrate 4006.

[0307] Furthermore, in a region different from the region surrounded by the sealing material 4005 on the substrate 4001, The dynamic circuit 4003 is implemented.

[0308] Furthermore, the pixel section 4002 and the drive circuit 4004 provided on the substrate 4001 are transistors It has multiple such elements. Figure 16 illustrates the transistor 4010 included in the pixel section 4002. It is. On transistor 4010, there is an insulating film composed of various insulating films including a nitride insulating film. A border film 4020 is provided, and the transistor 4010 is provided on the insulating film 4020. At the opening, it is connected to the pixel electrode 4021 on the insulating film 4020.

[0309] Furthermore, a resin film 4059 is provided on the substrate 4006, and a common resin film 4059 is provided on the resin film 4059. An electrode 4060 is provided. And between substrate 4001 and substrate 4006, a pixel electrode A liquid crystal layer 4028 is provided so as to be sandwiched between electrode 4021 and common electrode 4060. The liquid crystal element 4023 has a pixel electrode 4021, a common electrode 4060, and a liquid crystal layer 4028. do.

[0310] In the liquid crystal element 4023, the value of the voltage applied between the pixel electrode 4021 and the common electrode 4060 Accordingly, the orientation of the liquid crystal molecules contained in the liquid crystal layer 4028 changes, and the transmittance changes. Then, the liquid crystal element 4023 is affected by the potential of the image signal applied to the pixel electrode 4021. By controlling the transmittance, it is possible to display gradations.

[0311] Furthermore, as shown in Figure 16, in one aspect of the present invention, the insulating film 4020 is located at the edge of the panel. And it is removed. And in the region where the insulating film 4020 has been removed, the conductive film 4 050 is formed. Conductive film 4050 and source or drain of transistor 4010 A conductive film that functions as an insulator can be formed by etching a conductive film. ru.

[0312] Furthermore, conductive particles 4061 having electrical conductivity are separated between substrate 4001 and substrate 4006. A scattered resin film 4062 is provided. The conductive film 4050 is connected to the common electrode 4060 and They are electrically connected via the electrically charged particle 4061. That is, the common electrode 4060 and the conductive The film 4050 is electrically connected at the edge of the panel via conductive particles 4061. This means that a thermosetting resin or an ultraviolet curing resin can be used for the resin film 4062. This can be done. In addition, the conductive particles 4061 can be made of, for example, spherical organic resins such as Au, Ni, and Co Particles coated with a thin film of metal, such as the above, can be used.

[0313] Although the alignment layer is not shown in Figure 16, the alignment layer is connected to the pixel electrode 4021 and the common electrode 4 When placed on 060, the common electrode 4060, conductive particles 4061, and conductive film 4050 To electrically connect them, a portion of the alignment film is removed in the area overlapping with the common electrode 4060. Therefore, the alignment film can be partially removed in the area where it overlaps with the conductive film 4050.

[0314] Furthermore, in a liquid crystal display device according to one aspect of the present invention, a color filter is used to produce color You can display an image, or you can sequentially light up multiple light sources that emit light of different hues. You may display color images.

[0315] Furthermore, the image signal from the drive circuit 4003 and various control signals and potentials from the FPC 4018 are also transmitted. The drive circuit 4004 or the pixel unit 400 is connected via the routing wires 4030 and 4031. It is given to 2.

[0316] <Examples of electronic device configurations using semiconductor devices> A semiconductor device according to one aspect of the present invention comprises a display device, a personal computer, and a recording medium. Image playback devices (typically DVDs: Digital Versatile Discs) To be used in a device that has a display capable of playing back recording media such as the above and displaying the images thereof. This is possible. In addition, electronic devices that can use a semiconductor device according to one aspect of the present invention And mobile phones, game consoles including portable devices, personal digital assistants, e-books, video cameras, digital cameras Cameras such as still cameras, goggle-type displays (head-mounted displays) ), navigation systems, sound playback devices (car audio, digital audio players) (e.g., photocopiers, fax machines, printers, multifunction printers, ATMs) Examples include ATMs and vending machines. Specific examples of these electronic devices are shown in Figure 18. vinegar.

[0317] Figure 18(A) shows a portable game console, comprising a casing 5001, casing 5002, display unit 5003, Display unit 5004, microphone 5005, speaker 5006, operation keys 5007, stand It has illustration 5008, etc. Display unit 5003 or display unit 5004, and other integrated circuits. A semiconductor device according to one aspect of the present invention can be used. The portable game console has two display units 5003 and 5004, but the portable The number of display units a game console has is not limited to this.

[0318] Figure 18(B) shows a portable information terminal, consisting of a first housing 5601, a second housing 5602, and a first display unit. It includes 5603, a second display unit 5604, a connection unit 5605, an operation key 5606, etc. Table 1 The display unit 5603 is provided in the first housing 5601, and the second display unit 5604 is provided in the second housing 56 It is located at 02. And the first housing 5601 and the second housing 5602 are connected at the connection part 56 The connection is made by 05, and the angle between the first housing 5601 and the second housing 5602 is the connection part It can be changed by 5605. The video in the first display unit 5603 is connected to the connection unit 5 The switching mechanism is determined according to the angle between the first housing 5601 and the second housing 5602 in 605. It may also be made into a first display unit 5603 or a second display unit 5604 or other integrated circuit. A semiconductor device according to one aspect of the present invention can be used.

[0319] Figure 18(C) shows a notebook personal computer, consisting of a casing 5401 and a display unit 5402. It has a keyboard 5403, a pointing device 5404, etc. Display unit 5402 and A semiconductor device according to one aspect of the present invention can be used in other integrated circuits.

[0320] Figure 18(D) shows a wristwatch, consisting of a casing 5201, a display unit 5202, operation buttons 5203, and It has a display unit 5202 and other integrated circuits, according to one aspect of the present invention. A semiconductor device can be used.

[0321] Figure 18(E) shows a video camera, consisting of a first housing 5801, a second housing 5802, and a display unit 58 03, it has an operation key 5804, a lens 5805, a connector 5806, etc. Operation key 580 4 and lens 5805 are provided in the first housing 5801, and the display unit 5803 is in the second housing It is located in 5802. And the first housing 5801 and the second housing 5802 are connected by a connection part. They are connected by 5806, and the angle between the first housing 5801 and the second housing 5802 is, The change can be made by the extension unit 5806. The video switching in the display unit 5803 This is done according to the angle between the first housing 5801 and the second housing 5802 at the connection part 5806. The configuration is also good. The display unit 5803 and other integrated circuits use semiconductors according to one aspect of the present invention. Body devices can be used.

[0322] Figure 18(F) shows a mobile phone, with a housing 5901 containing a display unit 5902, a microphone 5907, and a microphone. The speaker 5904, camera 5903, external connection unit 5906, and operation buttons 5905 are provided. It is installed. The display unit 5902 and other integrated circuits are equipped with a semiconductor device according to one aspect of the present invention. A flexible substrate can be used. Furthermore, a semiconductor device according to one aspect of the present invention can be provided on a flexible substrate. When formed in this manner, the semiconductor is mounted on the display section 5902 having a curved surface as shown in Figure 18(F). It is possible to apply the placement. [Examples]

[0323] In this example, a transistor was fabricated, and its Vg-Id characteristics and reliability were evaluated. I will now explain the results.

[0324] [Sample preparation] In this embodiment, samples 1 and 2, representing one aspect of the present invention, and a comparative sample 3 were prepared. More specifically, as Sample 1, which is one aspect of the present invention, a tra corresponding to the configuration shown in Figure 2 A generator was fabricated. Furthermore, as sample 2, which represents one aspect of the present invention, the configuration shown in Figure 19 corresponds to... A transistor was fabricated. For comparison, sample 3 was prepared using the configuration shown in Figure 2, specifically the conductive transistor. A transistor equivalent to one without the film 30 was fabricated.

[0325] [Sample 1] First, a glass substrate was used as the substrate, and a gate electrode was formed on the substrate.

[0326] As the gate electrode, a tungsten film with a thickness of 200 nm is formed by sputtering, A mask is formed on the tungsten film by a trisography process, and the mask is used to... It was formed by etching a portion of the ngsten film.

[0327] Next, a gate insulating film was formed on the gate electrode.

[0328] As gate insulating films, a silicon nitride film with a thickness of 400 nm and a silicon oxidizide film with a thickness of 50 nm are used. It was formed by layering.

[0329] Furthermore, the silicon nitride film consists of a first silicon nitride film, a second silicon nitride film, and a third silicon nitride film. It has a three-layer laminated structure.

[0330] The first silicon nitride film consists of silane at a flow rate of 200 sccm and nitrogen at a flow rate of 2000 sccm. and ammonia gas at a flow rate of 100 sccm is used as the raw material gas for processing in a plasma CVD apparatus. A 27.12 MHz high-frequency power supply is used to supply power to the chamber, control the pressure inside the processing chamber to 100 Pa, and supply power to the chamber. Then, 2000W of power was supplied and it was formed to a thickness of 50nm. Second silicon nitride The substrates are silane at a flow rate of 200 sccm, nitrogen at a flow rate of 2000 sccm, and 2 A 000 sccm ammonia gas is supplied as a raw material gas to the processing chamber of the plasma CVD apparatus. The pressure inside the processing chamber is controlled to 100 Pa, and a 27.12 MHz high-frequency power supply is used to generate 200 A 0W power supply was applied to form a third silicon nitride film with a thickness of 300 nm. For example, using silane at a flow rate of 200 sccm and nitrogen at a flow rate of 5000 sccm as raw material gases. It is supplied to the processing chamber of the plasma CVD apparatus, and the pressure inside the processing chamber is controlled to 100 Pa, 27.1 Using a 2MHz high-frequency power supply, 2000W of power is supplied to achieve a thickness of 50nm. It was formed as follows. Note that when the first silicon nitride film, the second silicon nitride film, and the third silicon nitride film were formed... The substrate temperature was set to 350°C.

[0331] For the silicon oxide nitride film, a flow rate of 20 sccm of silane and a flow rate of 3000 sccm of dioxide monoxide were used. Nitrogen is supplied as a raw material gas to the processing chamber of the plasma CVD apparatus, and the pressure inside the processing chamber is set to 40 Pa. It is controlled to supply 100W of power using a 27.12MHz high-frequency power supply, and oxidative nitridation is performed. A silicon film was formed. The substrate temperature during the formation of the silicon oxidnitride film was 350°C.

[0332] Next, an oxide semiconductor film was formed to overlap the gate electrode via a gate insulating film.

[0333] In this embodiment, a 35 nm thick oxide semiconductor film is formed on a gate insulating film by sputtering. I did it.

[0334] Oxide semiconductor films are sputtered using an In:Ga:Zn=1:1:1 (number of atoms) target. Using a ratio as the target, oxygen at a flow rate of 100 sccm is used as the sputtering gas. It is supplied to the processing chamber of the ring device, the pressure inside the processing chamber is controlled to 0.6 Pa, and 5 kW of DC power is used. The film was formed by applying force. The substrate temperature during the formation of the oxide semiconductor film was set to 170°C. .

[0335] Next, source electrodes and drain electrodes were formed to contact the oxide semiconductor film.

[0336] First, a conductive film was formed on the gate insulating film and the oxide semiconductor film. The conductive film had a thickness of A 400 nm thick aluminum film is formed on a 50 nm tungsten film, and the aluminum A 200 nm thick titanium film was formed on the film. Next, the film was processed using a photolithography process. A mask is formed on the conductive film, and a portion of the conductive film is etched using the mask, and the source electricity The electrode and drain electrode were formed.

[0337] Next, the substrate is moved to a depressurized processing chamber, heated to 350°C, and then placed on an upper part of the processing chamber. A high-frequency power of 150W is supplied to the electrode using a 27.12MHz high-frequency power supply, and a monochloride is produced. An oxide semiconductor film was exposed to an oxygen plasma generated in a nitrogen dioxide atmosphere.

[0338] Next, protective films were formed on the oxide semiconductor film, the source electrode, and the drain electrode. The protective film consists of three layers: a first oxide insulating film, a second oxide insulating film, and a nitride insulating film. This was the structure.

[0339] The first oxide insulating film is made of silane at a flow rate of 20 sccm and dioxide monoxide at a flow rate of 3000 sccm. Using nitrogen as the raw material gas, with a processing chamber pressure of 200 Pa and a substrate temperature of 350°C, a 100W power supply was used. It was formed by plasma CVD, a method in which high-frequency power was supplied to parallel plate electrodes.

[0340] The second oxide insulating film consists of silane at a flow rate of 160 sccm and oxide monoxide at a flow rate of 4000 sccm. Using dinitrogen as the raw material gas, with a processing chamber pressure of 200 Pa and a substrate temperature of 220°C, 1500 The material was formed by plasma CVD, in which high-frequency power W was supplied to parallel plate electrodes. Furthermore, it contains more oxygen than satisfactorily satisfying the oxygen composition, and some of the oxygen is removed by heating. It is possible to form a detachable silicon oxide nitride film.

[0341] Next, heat treatment is performed, and water, nitrogen, and water are added to the first oxide insulating film and the second oxide insulating film. While removing elements, some of the oxygen contained in the second oxide insulating film is transferred to the oxide semiconductor film. The material was supplied. In this example, heat treatment was performed at 350°C for 1 hour in a nitrogen and oxygen atmosphere. .

[0342] Next, a nitride insulating film with a thickness of 100 nm was formed on the second oxide insulating film. The membrane is subjected to silane at a flow rate of 50 sccm, nitrogen at a flow rate of 5000 sccm, and 100 sccc. Using ammonia gas at a concentration of m as the raw material gas, the pressure in the processing chamber was set to 100 Pa, and the substrate temperature was set to 350°C. The material was formed by a plasma CVD method in which 1000W of high-frequency power was supplied to parallel plate electrodes. .

[0343] Next, in the region where the oxide semiconductor film, source electrode, and drain electrode are not provided, An opening reaching the gate electrode was formed in a portion of the gate insulating film and protective film. A mask is formed on the protective film by a photolithography process, and the gate is sealed using the mask. It was formed by etching a portion of the edge film and protective film.

[0344] Next, a gate electrode was formed on the protective film. This gate electrode is formed on the gate insulating film and the protective film. Through an opening provided in part of the film, the gate electrode located in the lower layer of the oxide semiconductor film is electrically connected to the gate electrode. The configuration was designed to connect to the following. Hereafter, the gate electrode on the protective film will be referred to as the back gate electrode.

[0345] In this embodiment, a 100 nm thick oxide film was used as the back gate electrode by sputtering. A conductive film of silicon-containing indium oxide-tin oxide compound (ITO-SiO2) was formed. The composition of the target used in the conductive film is In2O3:SnO2:SiO2=85:1 The ratio was set to 0.5 [weight%]. After this, heat treatment was performed at 250°C for 1 hour in a nitrogen atmosphere. .

[0346] Sample 1 of this embodiment was obtained through the above steps.

[0347] [Sample 2] Sample 2 differs from Sample 1 in the structure of its protective film and back gate electrode. More specifically, In the channel width direction of the transistor, the first oxide insulating film and the second oxide insulating film The configuration was such that the back gate electrode covered the side of the device.

[0348] The preparation of sample 2 involves the first oxide insulating film and the second oxide in the preparation process of sample 1 described above. A material insulating film is formed, followed by heat treatment, and then a second oxidation is performed by a photolithography process. A mask was formed on the material insulating film. Subsequently, the first oxide insulating film and the second acid were used with the mask. A portion of the oxide insulating film was etched. The other steps were the same as those for sample 1 described above. Therefore, the description of Sample 1 can be used as a reference.

[0349] [Sample 3] Sample 3, used for comparison, differs from Sample 1 in that it lacks a back gate electrode. That's what I decided.

[0350] The preparation of sample 3 is carried out by omitting the back gate electrode formation step in the preparation process of sample 1 described above. It was prepared by abbreviating the process. The other steps are the same as those for sample 1 described above, therefore sample The description in 1 can be used as a reference.

[0351] Furthermore, the above-mentioned samples 1 to 3 have channel lengths (L) of 2 μm, 3 μm, or 6 μm. Each of the three types of transistors, each of which is m, was included. And, in Sample 1 to Sample 3 All transistors included had a channel width (W) of 50 μm.

[0352] [Vg-Id characteristics] Next, the Vg-Id characteristics were measured as initial characteristics of the transistors from sample 1 to sample 3. In this embodiment, the substrate temperature is set to 25°C, and the potential difference between the source and drain (hereinafter referred to as the drain potential) is set to 25°C. Let the voltage (also called Vd) be 1V and 10V, and the potential difference between the source and buck gate electrodes (hereinafter, Source-drain voltage (also called gate voltage Vg) when varied from -15V to 15V The characteristic change in the current flowing between the terminals (hereinafter also called drain current, Id), i.e., Vg-I The d-characteristics were measured.

[0353] In this case, in sample 1 and sample 2, the gate electrode and the back gate electrode are electrically short-circuited. A driving method was used in which the gate voltage was applied in that state. In Dual Gate driving, The gate voltages of the gate electrode and the buck gate electrode are always equal.

[0354] Figure 26 shows the Vg-Id characteristics of sample 3. Figures 26(A), (B), and (C) are, respectively, These are the results for transistors with channel lengths (L) of 2 μm, 3 μm, and 6 μm. Similarly, Figure 27 shows the Vg-Id characteristics of sample 1, and Figure 28 shows the Vg-Id characteristics of sample 2. These are shown respectively.

[0355] Furthermore, in Figures 26, 27, and 28, the horizontal axis represents the gate voltage Vg, and the first vertical axis represents the gate voltage Vg. The first vertical axis represents the drain current Id, and the second vertical axis represents the field effect mobility. Here, the electric field To show the effect mobility in the saturation region, the field effect mobility calculated with Vd = 10V is used. It is showing.

[0356] In the comparative sample 3 shown in Figure 26, the field effect mobility value is not affected by the channel length (L). It was found that it hardly changes. Also, the smaller the channel length (L), the drain The results showed that the threshold voltage shifts in the negative direction as the voltage Vd increases.

[0357] On the other hand, in sample 1 of one embodiment of the present invention shown in Figure 27, under all channel length (L) conditions... Furthermore, it was confirmed that the field-effect mobility was improved compared to sample 3 above. It was found that the smaller the length (L), the better the field effect mobility. Even under the condition of a small channel length (L=2μm), the ratio with respect to the drain voltage Vd The change in the 1-value voltage was found to be extremely small compared to sample 3.

[0358] In sample 2 of one embodiment of the present invention shown in Figure 28, under all channel length (L) conditions, Furthermore, it was confirmed that the field-effect mobility was improved compared to sample 3 above. It was found that the smaller the length (L), the better the field effect mobility. Even under the condition of a small channel length (L=2μm), the ratio with respect to the drain voltage Vd The change in the 1-value voltage was found to be extremely small compared to sample 3.

[0359] In samples 1 and 2, channel formation was achieved by dual gate drive compared to sample 3. This makes it possible to apply an electric field more effectively to oxide semiconductors, and as a result, channels Even when the drain length (L) is small, the change in threshold voltage with respect to the drain voltage Vd is kept small. It can be seen that this has been made possible. Also for the same reason, in sample 1 and sample 2, D The dual gate drive makes it less susceptible to the influence of the drain voltage Vd, and in the saturation region... It can also improve saturation.

[0360] From the above results, in a semiconductor device according to one aspect of the present invention, the channel length of the transistor (L The smaller the value, the better the field-effect mobility, and furthermore, in the case of a small channel length (L) Even in this case, it was confirmed that the threshold voltage could be set to a good value. By using transistors, it is possible to achieve narrow bezels for semiconductor display devices. . [Explanation of Symbols]

[0361] 10 sequential circuits 10_DUM sequential circuit 10_j Sequential circuit 10_j-1 Sequential circuit 10_y sequential circuit 10_1 Sequential circuit 10_8m sequential circuit 11 circuits 12 transistors 13 transistors 14 transistors 15 transistors 16 transistors 17 transistors 20 transistors 21 Conductive film 22 Insulating film 23 Oxide semiconductor film 23a Oxide semiconductor film 23b Oxide semiconductor film 23c oxide semiconductor film 24 Conductive film 25 Conductive film 26 Insulating film 27 Insulating film 28 Nitride insulating film 29 Insulating film 30 Conductive film 31 circuit boards 32 openings 32a opening 32b opening 34 Conductive film 40 Conductive film 41 Oxide semiconductor film 42 Metal oxide film 42a Oxide semiconductor film 43 Conductive film 44 Conductive film 45 Conductive film 46 circuit boards 47 Shielding membrane 48 Colored layer 50 Resin film 51 Orientation film 52 Orientation film 53 Liquid crystal layer 55 pixels 56 transistors 57 Capacitive elements 58 Opening 59 Conductive film 60 Click the LCD button 61 Conductive film 62 Opening 70 Semiconductor display devices 71 pixel section 72 Drive Circuit 73 Drive Circuit 80 transistors 81 Transistors 82 transistors 83 Transistors 84 transistors 85 transistors 86 transistors 90 buffers 91 Transistors 92 transistors 93 Transistors 95 transistors 96 transistors 97 Capacitive elements 98 light-emitting elements 4001 circuit board 4002 pixel section 4003 Drive Circuit 4004 Drive Circuit 4005 Sealing material 4006 circuit board 4010 Transistor 4018 FPC 4020 Insulating film 4021 Pixel Electrode 4023 Liquid crystal element 4028 Liquid Crystal Layer 4030 Wiring 4050 Conductive film 4059 Resin film 4060 Common electrode 4061 Conductive particles 4062 Resin film 5001 enclosure 5002 enclosure 5003 Display section 5004 Display section 5005 Microphone 5006 Speaker 5007 Operation Keys 5008 Stylus 5201 enclosure 5202 Display section 5203 Operation Buttons 5204 Band 5401 enclosure 5402 Display section 5403 Keyboard 5404 Pointing device 5601 enclosure 5602 enclosure 5603 Display section 5604 Display section 5605 Connection part 5606 Operation Keys 5801 enclosure 5802 enclosure 5803 Display section 5804 Operation Keys 5805 Lens 5806 Connection part 5901 enclosure 5902 Display section 5903 Camera 5904 Speaker 5905 button 5906 External connection section 5907 Mike

Claims

1. The pixel has a transistor, a capacitive element, and a display element. The source or drain of the transistor is electrically connected to the first electrode of the display element. The source or drain of the transistor is electrically connected to one electrode of the capacitive element, in a display device, A first conductive film having the function of a photoelectrode of the transistor, A first insulating film having a region positioned above the first conductive film and functioning as a gate insulating film of the transistor, An oxide semiconductor film having a region positioned above the first insulating film and having the channel region of the transistor, A metal oxide film having a region positioned above the first insulating film and functioning as the other electrode of the capacitive element, A third conductive film is electrically connected to the second conductive film having the function of the first electrode, and is also electrically connected to the oxide semiconductor film. A fourth conductive film having a region that is electrically connected to the oxide semiconductor film and functions as a first wiring that is electrically connected to the other of the source or drain of the transistor, and that extends in a first direction across the pixel and adjacent pixels, A fifth conductive film having a function as a second wiring electrically connected to the metal oxide film, and having a region extending in the first direction across the pixel and adjacent pixels, A second insulating film having a region positioned above the oxide semiconductor film and a region positioned above the metal oxide film, A third insulating film having a region positioned above the second insulating film and a region positioned above the metal oxide film, A sixth conductive film having a region positioned above the second conductive film and functioning as the second electrode of the display element, The second conductive film has a region located above the third insulating film, The metal oxide film has a region that does not overlap with the second insulating film, and a region in that region that is in contact with the third insulating film. Display device.

2. The pixel has a transistor, a capacitive element, and a display element. The source or drain of the transistor is electrically connected to the first electrode of the display element. The source or drain of the transistor is electrically connected to one electrode of the capacitive element, in a display device, A first conductive film having the function of a photoelectrode of the transistor, A first insulating film having a region positioned above the first conductive film and functioning as a gate insulating film of the transistor, An oxide semiconductor film having a region positioned above the first insulating film and having the channel region of the transistor, A metal oxide film having a region positioned above the first insulating film and functioning as the other electrode of the capacitive element, A third conductive film is electrically connected to the second conductive film having the function of the first electrode, and is also electrically connected to the oxide semiconductor film. A fourth conductive film having a region that is electrically connected to the oxide semiconductor film and functions as a first wiring that is electrically connected to the other of the source or drain of the transistor, and that extends in a first direction across the pixel and adjacent pixels, A fifth conductive film having a function as a second wiring electrically connected to the metal oxide film, and having a region extending in the first direction across the pixel and adjacent pixels, A second insulating film having a region positioned above the oxide semiconductor film and a region positioned above the metal oxide film, A third insulating film having a region positioned above the second insulating film and a region positioned above the metal oxide film, A sixth conductive film having a region positioned above the second conductive film and functioning as the second electrode of the display element, The second conductive film has a region located above the third insulating film, The metal oxide film has a region that does not overlap with the second insulating film, and a region in that region that is in contact with the third insulating film. The fifth conductive film does not overlap with the fourth conductive film. Display device.

3. The pixel has a transistor, a capacitive element, and a display element. The source or drain of the transistor is electrically connected to the first electrode of the display element. The source or drain of the transistor is electrically connected to one electrode of the capacitive element, in a display device, A first conductive film having the function of a photoelectrode of the transistor, A first insulating film having a region positioned above the first conductive film and functioning as a gate insulating film of the transistor, An oxide semiconductor film having a region positioned above the first insulating film and having the channel region of the transistor, A metal oxide film having a region positioned above the first insulating film and functioning as the other electrode of the capacitive element, A third conductive film is electrically connected to the second conductive film having the function of the first electrode, and is also electrically connected to the oxide semiconductor film. A fourth conductive film having a region that is electrically connected to the oxide semiconductor film and functions as a first wiring that is electrically connected to the other of the source or drain of the transistor, and that extends in a first direction across the pixel and adjacent pixels, A fifth conductive film having a function as a second wiring electrically connected to the metal oxide film, and having a region extending in the first direction across the pixel and adjacent pixels, A second insulating film having a region positioned above the oxide semiconductor film and a region positioned above the metal oxide film, A third insulating film having a region positioned above the second insulating film and a region positioned above the metal oxide film, A sixth conductive film having a region positioned above the second conductive film and functioning as the second electrode of the display element, The second conductive film has a region located above the third insulating film, The metal oxide film has a region that does not overlap with the second insulating film, and a region in that region that is in contact with the third insulating film. The metal oxide film does not overlap with the third conductive film. Display device.

4. The pixel has a transistor, a capacitive element, and a display element. The source or drain of the transistor is electrically connected to the first electrode of the display element. The source or drain of the transistor is electrically connected to one electrode of the capacitive element, in a display device, A first conductive film having the function of a photoelectrode of the transistor, A first insulating film having a region positioned above the first conductive film and functioning as a gate insulating film of the transistor, An oxide semiconductor film having a region positioned above the first insulating film and having the channel region of the transistor, A metal oxide film having a region positioned above the first insulating film and functioning as the other electrode of the capacitive element, A third conductive film is electrically connected to the second conductive film having the function of the first electrode, and is also electrically connected to the oxide semiconductor film. A fourth conductive film having a region that is electrically connected to the oxide semiconductor film and functions as a first wiring that is electrically connected to the other of the source or drain of the transistor, and that extends in a first direction across the pixel and adjacent pixels, A fifth conductive film having a function as a second wiring electrically connected to the metal oxide film, and having a region extending in the first direction across the pixel and adjacent pixels, A second insulating film having a region positioned above the oxide semiconductor film and a region positioned above the metal oxide film, A third insulating film having a region positioned above the second insulating film and a region positioned above the metal oxide film, A sixth conductive film having a region positioned above the second conductive film and functioning as the second electrode of the display element, The second conductive film has a region located above the third insulating film, The metal oxide film has a region that does not overlap with the second insulating film, and a region in that region that is in contact with the third insulating film. The metal oxide film does not overlap with the fourth conductive film. Display device.

5. In any one of claims 1 to 4, The oxide semiconductor film comprises In, Ga, and Zn. Display device.

6. In any one of claims 1 to 4, The oxide semiconductor contained in the aforementioned oxide semiconductor film is indium oxide. Display device.

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