Information processing device, information processing system, and information processing method

Abstract

This invention provides an information processing device, an information processing system, and an information processing method that reduce the number of instructions and shorten processing time associated with data movement between memory and register files. [Solution] The system comprises at least a memory that holds multiple source data, an arithmetic unit that performs calculations using one or more source data input from the memory, and an instruction code holding unit that holds multiple instruction codes including one or more source addresses in which one or more source data are stored in the memory, and an arithmetic unit operation signal that instructs the operation of the arithmetic unit. The instruction code holding unit transmits one or more source addresses included in the instruction code to the memory and transmits an arithmetic unit operation signal to the arithmetic unit. The memory outputs one or more source data stored at one or more source addresses, and the arithmetic unit performs calculations using one or more source data input from the memory in accordance with the operation instructed by the arithmetic unit operation signal.

Description

Technical Field

[0001] The present invention relates to an information processing apparatus, an information processing system, and an information processing method.

Background Art

[0002] In the control of industrial equipment such as industrial robots and power systems, it is necessary to achieve real-time control by means of inexpensive edge devices such as embedded systems. As a method for accelerating processing in edge devices, the use of a GPU (Graphics Processing Unit) can be considered, but in complex processing in the control field, the cost-effectiveness is poor, and acceleration based on a CPU (Central Processor Unit) is required.

[0003] As a technology related to accelerating processing using such a CPU, for example, there is Patent Document 1. This publication discloses "when an instruction decoded by a decode unit is an instruction that executes a plurality of times in parallel the arithmetic processing for a set of operands including a plurality of operands that are arithmetic processing targets, based on a predetermined address displacement for the plurality of operands included in each set of operands, an address generation unit that generates, for each arithmetic processing, a set of addresses corresponding to each set of operands, a plurality of instruction queues that respectively hold the sets of addresses corresponding to the generated sets of operands corresponding to each arithmetic unit, and a plurality of arithmetic units that perform in parallel the arithmetic processing for the sets of operands respectively obtained based on the sets of addresses output by the plurality of instruction queues."

Prior Art Documents

[0005] Figure 21 is a schematic diagram showing the configuration of an edge device equipped with a typical CPU. In Figure 21, only some of the configurations relevant to the following explanation are shown in a simplified manner. In Figure 21, the edge device 2000 controls a control target 2030 consisting of multiple industrial devices. The edge device 2000 includes a CPU 2010 and a communication buffer 2020 that temporarily stores data transmitted and received through communication with the control target 2030. The CPU 2010 includes a memory 2011, a register file 2012, and an arithmetic unit 2013. Data received from the control target 2030 is stored in the memory 2011 via the communication buffer 2020. Data necessary for calculations is transferred from the memory 2011 to the register file 2012 and temporarily stored, and various calculations are performed by the arithmetic unit 2013. The results of calculations by the arithmetic unit 2013 are written to the register file 2012 (temporarily stored), and then transferred from the register file 2012 to the memory 2011 and stored. The data stored in memory 2011 is read out as needed and sent to the controlled device 2030 via the communication buffer 2020.

[0006] In controlling industrial equipment as described above, for example, state information such as the motor angle and operating status of the controlled equipment, as well as surrounding information from cameras and sensors, are acquired. Command values ​​are calculated from this acquired information, and these command values ​​are converted into a drive format for the controlled equipment, such as pulses, for control. This information acquisition, command value calculation, and control according to the command values ​​are each performed by separate devices, and control of industrial equipment is realized by sending and receiving data between these devices. The number of information acquisition devices and controlled equipment is increasing, and with the improvement of the resolution of the acquired information and the increasing complexity of the control content, the amount of data sent and received between devices is also increasing, requiring the processing of large amounts of data. Furthermore, when deriving the optimal solution for the entire factory or facility equipped with multiple industrial devices, not just individual industrial devices, calculations using even larger amounts of data are required.

[0007] As described above, in the edge device 2000, this large amount of data is stored in memory 2011, transferred from memory 2011 to register file 2012, processed by the arithmetic unit 2013, and then stored again in memory 2011 via register file 2012. Because calculations for industrial equipment control require real-time processing, the arithmetic unit is being made faster. However, the movement of this large amount of data between memory and register file is becoming a problem as it increases the number of instructions and processing time in the CPU.

[0008] This invention has been made in view of these problems, and aims to provide an information processing device, an information processing system, and an information processing method that reduce the number of instructions and shorten processing time associated with data movement between memory and register files. [Means for solving the problem]

[0009] This invention includes several means to solve at least some of the above problems, one example of which is as follows. Specifically, the system comprises at least a memory for holding multiple source data, an arithmetic unit that performs calculations using one or more of the source data input from the memory and outputs one or more result data, and an instruction code holding unit that holds multiple instruction codes including one or more source addresses in the memory where the one or more of the source data are stored, one or more destination addresses in the memory where the one or more of the result data are stored, and an arithmetic unit operation signal that instructs the operation of the arithmetic unit. The instruction code holding unit selects one of the instruction codes, transmits the one or more of the source addresses and destination addresses included in the instruction code to the memory, transmits the arithmetic unit operation signal to the arithmetic unit, outputs the one or more of the source data stored at the one or more of the source addresses input from the instruction code holding unit, stores the one or more of the result data input from the arithmetic unit at each of the one or more destination addresses, and the arithmetic unit performs calculations using the one or more of the source data input from the memory in accordance with the operation instructed by the arithmetic unit operation signal input from the instruction code holding unit. [Effects of the Invention]

[0010] According to the present invention, by specifying the memory address in the instruction code, data can be moved directly between memory and the arithmetic unit without going through a register file. This makes it possible to provide an information processing device, an information processing system, and an information processing method that reduce the number of instructions and shorten processing time associated with data movement between memory and a register file.

[0011] Other issues, configurations, and effects not mentioned above will be clarified by the following description of the embodiments. [Brief explanation of the drawing]

[0012] [Figure 1] This is an example of a functional block diagram of the control device according to Example 1. [Figure 2] It is an example of a functional block diagram of an information processing apparatus according to Embodiment 1. [Figure 3] It is a diagram showing an example of the configuration of a memory according to Embodiment 1. [Figure 4] It is a diagram showing an example of the configuration of an instruction code holding unit according to Embodiment 1. [Figure 5] It is an example of a functional block diagram of an arithmetic unit according to Embodiment 1. [Figure 6] It is an example of a functional block diagram of an information processing apparatus according to Embodiment 2. [Figure 7] It is an example of a functional block diagram of an information processing apparatus according to Embodiment 3. [Figure 8] It is an example of a functional block diagram of an information processing apparatus according to Embodiment 4. [Figure 9] It is a diagram showing an example of the configuration of an instruction code holding unit according to Embodiment 4. [Figure 10] It is a diagram showing an example of the configuration of a connection signal generation unit according to Embodiment 4. <00所学内容, [Figure 11] It is a diagram showing an example of the configuration of a connection determination unit according to Embodiment 4. [Figure 12] It is an example of a functional block diagram of an information processing apparatus according to Embodiment 5. [Figure 13] It is a diagram showing an example of the configuration of an instruction code holding unit according to Embodiment 5. [Figure 14] It is a diagram showing an example of the configuration of a connection signal generation unit according to Embodiment 5. [Figure 15] [[ID=4所提供的内容, It is a diagram showing an example of the configuration of a connection determination unit according to Embodiment 5. [Figure 16] It is an example of a functional block diagram of an information processing apparatus according to Embodiment 6. [Figure 17] It is an example of a functional block diagram of an information processing apparatus according to Embodiment 7. [Figure 18] It is a diagram showing an example of the configuration of a register file according to Embodiment 7. [Figure 19] It is a diagram showing an example of the configuration of a connection signal generation unit according to Embodiment 7. [Figure 20]It is a diagram showing an example of the configuration of the connection determination unit according to Example 7. [Figure 21] It is a schematic diagram showing the configuration of an edge device equipped with a general CPU.

Embodiments for Carrying Out the Invention

[0013] Hereinafter, embodiments of the present invention will be described with reference to the drawings. The embodiments are examples for explaining the present invention, and for the sake of clarity of explanation, appropriate omissions and simplifications are made. The present invention can also be implemented in various other forms. Unless otherwise particularly limited, each component may be singular or plural.

[0014] In the drawings, the positions, sizes, shapes, ranges, etc. of the respective components shown may not represent the actual positions, sizes, shapes, ranges, etc. in order to facilitate understanding of the invention. Therefore, the present invention is not necessarily limited to the positions, sizes, shapes, ranges, etc. disclosed in the drawings. When there are a plurality of components having the same or similar functions, they may be described with the same reference numeral and different subscripts. Also, when it is not necessary to distinguish these plurality of components, the subscripts may be omitted in the description.

[0015] In the embodiments, the processes performed by executing a program may be described. Here, the computer executes the program by a processor (for example, CPU, GPU), and performs the processes defined in the program while using storage resources (for example, memory) and interface devices (for example, communication ports), etc. Therefore, the subject of the process performed by executing the program may be the processor. Similarly, the subject of the process performed by executing the program may be a controller, device, system, computer, or node having a processor.

[0016] The main component performing the processing when a program is executed can be an arithmetic unit, and may include dedicated circuits for specific processing. Here, dedicated circuits include, for example, FPGAs (Field Programmable Gate Arrays), ASICs (Application Specific Integrated Circuits), and CPLDs (Complex Programmable Logic Devices).

[0017] The program may be installed on the computer from the program source. The program source may be, for example, a program distribution server or a storage medium readable by the computer. If the program source is a program distribution server, the program distribution server includes a processor and storage resources to store the program to be distributed, and the processor of the program distribution server may distribute the program to other computers. In addition, in the embodiment, two or more programs may be implemented as one program, or one program may be implemented as two or more programs. [Examples]

[0018] Figure 1 shows an example of a functional block diagram of a control device according to Embodiment 1. In Figure 1, the control device 100 mainly consists of an information processing device 110 which is responsible for generating control command values ​​and analyzing information based on acquired data, and a communication device 120 which receives data and transmits control command values, and controls one or more control objects (hereinafter referred to as control objects 130-1 to 130-i (where i is an integer) or one or more control objects collectively referred to as control object 130), such as industrial equipment. The communication device 120 receives various data such as status information from control objects 130-1 to 130-i and also transmits control command values ​​to control objects 130-1 to 130-i. The communication device 120 can also send and receive various data with one or more peripheral devices 140, such as devices that collect peripheral information such as sensors and cameras, and devices that generate operation plans for control objects.

[0019] Figure 2 shows an example of a functional block diagram of an information processing device according to Embodiment 1. In Figure 2, the information processing device 110 includes an arithmetic unit 201 that performs calculations according to instructed operations based on input data, a memory 202 that stores data used for calculations (hereinafter referred to as source data) and calculation results, and an instruction code holding unit 203 that holds the address in the memory 202 where the source data is stored (hereinafter referred to as the source address), the address where the calculation results are stored (hereinafter referred to as the destination address), and an instruction code that specifies the operation of the arithmetic unit.

[0020] The instruction code holding unit 203 holds multiple instruction codes as a set of instruction codes, each containing one or more source addresses (in the example shown in Figure 2, source 1 address and source 2 address), one or more destination addresses where one or more calculation results are stored (in the example shown in Figure 2, destination addresses), and an arithmetic unit operation signal indicating the operation to be performed by the arithmetic unit 201 (type of calculation, etc.). The instruction code holding unit 203 selects instruction codes one by one in sequence, sends the source address and destination address of the instruction code to the memory 202, and sends the arithmetic unit operation signal to the arithmetic unit 201.

[0021] The arithmetic unit 201 is capable of performing multiple types of operations, including arithmetic operations such as addition, subtraction, multiplication, and division, logical operations such as AND and OR, and bit shifts. It outputs result data, which is the result of the operation indicated by the arithmetic unit operation signal input from the instruction code holding unit 203. The number of source data input to the arithmetic unit 201 during operation is one or more, and similarly, the number of result data output from the arithmetic unit 201 is also one or more. An example of result data being multiple is the quotient and remainder when the arithmetic unit 201 performs division.

[0022] The source data is held in memory 202, and the memory 202 outputs the source data stored at one or more source addresses received from the instruction code holding unit 203 (in the example shown in Figure 2, source 1 data and source 2 data stored at source 1 address and source 2 address, respectively) to the arithmetic unit 201. The memory 202 also stores one or more result data input from the arithmetic unit 201 (in the example shown in Figure 2, the result data) at one or more destination addresses input from the instruction code holding unit 203 (in the example shown in Figure 2, the destination addresses). In this way, input and output (data movement) of one or more data is performed between the memory 202 and the arithmetic unit 201 according to one or more addresses transmitted from the instruction code holding unit 203.

[0023] Figure 3 shows an example of the memory configuration according to Embodiment 1. In Figure 3, memory 202 holds multiple source data 1-1 to source data 1-j (where j is an integer). These source data are data received from the controlled objects 130-1 to 130-i shown in Figure 1, or data received from one or more peripheral devices 140. The length of each source data may be fixed to a specific length, or it may differ for each source data. For example, each source data may be data with a fixed length such as 32 bits or 64 bits, or source data of multiple lengths such as 64 bits, 32 bits, and 16 bits may be mixed. For example, if all source data is fixed to a length of 32 bits, the addresses M1, M2, M3...Mj shown in Figure 3 will be allocated at 32-bit intervals, i.e., 4-byte intervals. On the other hand, if source data of different lengths are mixed, addresses M1 to Mj will be allocated according to the length of the stored source data. For example, in Figure 3, if source data 1-1 is 32 bits long, source data 1-2 is 16 bits long, and source data 1-3 is 8 bits long, then the interval between addresses M1 and M2 is 4 bytes, the interval between M2 and M3 is 2 bytes, and the interval between M3 and M4 is 1 byte. Note that the length of the source data read from memory 202 may be determined by the address position or by the type of instruction.

[0024] Figure 4 is a diagram showing an example of the configuration of the instruction code holding unit according to Embodiment 1. As described in the explanation of Figure 2, the instruction code holding unit 203 holds multiple instruction codes, each set consisting of the source address of the memory 202 where one or more source data (source 1 data and source 2 data in the examples shown in Figures 2 and 4) is stored (source 1 address and source 2 address in the examples shown in Figures 2 and 4), the destination address of one or more result data (destination address in the examples shown in Figures 2 and 4), and an arithmetic unit operation signal indicating the operation to be executed by the arithmetic unit 201.

[0025] In Figure 4, each address "M1~M12" represents the address of the position (also called a memory address) indicated by each number from the beginning of memory 202 (for example, "M1" is the address of the first element (address 0) from the beginning of memory 202). Figure 4 also shows an example of representing addition, multiplication, etc., as arithmetic unit operation signals using 6 bits. Furthermore, in Figure 4, for ease of understanding, the arithmetic unit operation content indicated by the arithmetic unit operation signal is shown at the beginning of each instruction code as an example, but in the actual implementation, the arithmetic unit operation content is not necessary in the instruction code; the instruction code only needs to contain the arithmetic unit operation signal. Also, as mentioned above, Figure 4 shows an example where each instruction code has the same length (identical instruction code length) and includes two source addresses, one storage address, and an arithmetic unit operation signal.

[0026] As described above, Source 1 address represents the address of the first source data used in the calculation, and Source 2 address represents the address of the second source data used in the calculation. The data stored in the one or more source addresses specified by the instruction code, that is, the one or more source addresses transmitted from the instruction code holder 203 according to the instruction code selected in the instruction code holder 203, is output from memory 202 to the arithmetic unit 201. Note that in Figures 2 and 4, Source 1 address, Source 2 address, and storage address may each be specified as different addresses, or two or all of them may be specified as the same address.

[0027] In the examples shown in Figures 2 and 4, there are two source data points, and each instruction code contains two source addresses (source 1 address and source 2 address). However, it is not always necessary to specify both source addresses in an instruction code; only one may be used, and only the address of one source data point may be specified. For example, if only the address of one source data point is specified in source 1 address in Figure 4, the instruction code length does not change, and the portion allocated to source 2 address will not be used (the address will not be specified and will remain empty). For example, if the length of each address in the instruction code is 5 bits, the 5 bits allocated to source 2 address will not be used and will become empty bits. Therefore, instead of source 2 address, i.e., the empty bits may be used to specify an immediate value or specify detailed calculation content.

[0028] Furthermore, if the operation indicated by the arithmetic unit operation signal does not use data stored in memory 202, then, as in the case described above, the portions allocated to source 1 address and source 2 address will not be used, and the bits allocated to each address may be used for other purposes, such as specifying an immediate value or specifying the details of the operation.

[0029] As described above, each instruction code can contain one or more source addresses and one or more destination addresses, and the number of addresses is not limited to the example in Figure 4, i.e., two source addresses and one destination address. For example, it is possible to include multiple source addresses and destination addresses in an instruction code by increasing the instruction code length or by reducing the number of bits required for a single address specification. Also, in the example shown in Figure 4, the arithmetic unit operation signal is represented by 6 bits, but the number of bits used for the arithmetic unit operation signal may be changed as appropriate depending on the instruction code length, the specified operation content, and the number and length of each address.

[0030] Figure 5 shows an example of a functional block diagram of an arithmetic unit according to Embodiment 1. In Figure 5, the arithmetic unit 201 takes multiple source data as input, performs calculations, and outputs result data, which is the result of the calculation indicated by the arithmetic unit operation signal. The arithmetic unit 201 includes multiple arithmetic blocks such as an adder 501 that handles addition, a logical arithmetic unit 502 that handles operations such as AND and OR, a multiplier 503 that handles signed and unsigned multiplication, and a divider 504 that outputs quotients and remainders, as well as an arithmetic result selection unit 505 that selects result data to be output to memory 202 from the calculation results of each arithmetic block. The arithmetic unit 201 may also include arithmetic blocks other than those shown in Figure 5, such as shift operations and multiply-accumulate operations. Note that the adder 501 in Figure 5 can also be used as a subtractor by adding negative numbers.

[0031] Each arithmetic block 501 to 504 takes source 1 data and source 2 data as input, performs calculations, and outputs the calculation result to the calculation result selection unit 505. The calculation result selection unit 505 selects one of the input calculation results according to the arithmetic unit operation signal and outputs it to memory 202 as result data. In the example shown in Figure 5, similar to the examples shown in Figures 2 and 4, two source data sets, source 1 data and source 2 data, are input to the arithmetic unit 201. However, as described above, the source data is not limited to two; one or more source data sets can be input to the arithmetic unit 201, and each arithmetic block 501 to 504 can perform calculations using these source data sets. Also, although Figure 5 shows an example where only one calculation result is selected by the calculation result selection unit 505 and output by the arithmetic unit 201, the calculation result selection unit 505 may select multiple calculation results, such as the quotient and remainder output by the divider 504, and the arithmetic unit 201 may output them.

[0032] As explained above, in the information processing device of Example 1, by specifying the memory address (source address and storage address) in the instruction code, source data is directly input from memory to the arithmetic unit, and result data is directly input from the arithmetic unit to memory and stored. As a result, the information processing device can directly input and output source data (data movement) between memory and the arithmetic unit without using a register file. This eliminates the need for the information processing device to have a register file, to interpose a register file between memory and the arithmetic unit, and to move source data and result data between memory and the register file. This makes it possible to reduce the number of instructions and shorten processing time associated with such data movement. [Examples]

[0033] In Example 1, we described an example in which an information processing device has one memory and source data is input and output between the memory and the arithmetic unit. However, it is also possible to configure the information processing device to have multiple memories. Example 2 describes an example of an information processing device with such a configuration. In the following description, explanations that overlap with Example 1 will be omitted, and only the differences will be explained.

[0034] Figure 6 shows an example of a functional block diagram of the information processing device according to Embodiment 2, and the same reference numerals are used for components identical to those in the information processing device 110 shown in Figure 2. In Figure 6, the information processing device 210 has multiple memories (hereinafter referred to as memories 202-1 to 202-n (where n is an integer) or one or more memories collectively as memory 202) for one arithmetic unit 201. One or more source addresses (source 1 address, source 2 address in the example shown in Figure 6) and one or more destination addresses (destination addresses in the example shown in Figure 6) output from the instruction code holding unit 203 according to the instruction code selected in the instruction code holding unit 203 specify the addresses in each memory 202-1 to 202-n and are transmitted to each memory 202-1 to 202-n. For example, if the source 1 address is "M5", that is, the 5th address from the beginning, then according to the source 1 address transmitted from the instruction code holding unit 203, the source data stored in the 5th position of memory 202-1, the source data stored in the 5th position of memory 202-2, ... the source data stored in the 5th position of memory 202-n will be output from each memory 202-1 to 202-n to the arithmetic unit 201.

[0035] One or more destination addresses are similarly sent to each memory 202-1 to 202-n, and one or more result data output from the arithmetic unit 201 are stored at the location indicated by the one or more destination addresses in each memory 202-1 to 202-n.

[0036] The arithmetic unit 201 performs calculations using one arithmetic block based on multiple source data input from each memory 202-1 to 202-n, and outputs one or more result data. Alternatively, the arithmetic unit 201 may use multiple arithmetic blocks to perform a multiply-accumulate operation, for example, using the adder 501 and multiplier 503 shown in Figure 5, and output one or more result data.

[0037] Furthermore, in the information processing device 210, each memory 202-1 to 202-n can be provided corresponding to each control target 130-1 to 130-i shown in Figure 1. In this case, each memory 202-1 to 202-n stores data received from its corresponding control target 130-1 to 130-i (in this case, the number of memories and control targets will be the same). In this case, data received from one or more peripheral devices 140 may be stored in all memories 202-1 to 202-n in common, or in any specific memory. In addition, in this case, the arithmetic unit 201 may take one or more source data for each control target as input from each memory 202-1 to 202-n, perform calculations, and output one or more result data for each control target.

[0038] As explained above, the information processing device in Example 2 is equipped with multiple memories, and in one instruction code, the address of the source data and the destination address specified are sent to each memory, the data stored at the specified source data address is output from each memory, and the result data output from the arithmetic unit is stored at the location indicated by the destination address of each memory. In other words, the addresses (source addresses and destination addresses) of multiple memories are specified with one instruction code. By providing multiple memories, the memory capacity of the information processing device is effectively increased by the number of memories (n times), making it possible to hold n times the amount of data in the memory as a whole. With this configuration, in addition to the same effects as in Example 1, it becomes possible to specify n times the amount of data held in all multiple memories with a single instruction code of the same instruction code length as described in Example 1. This makes it possible to increase the amount of data that the information processing device can handle by n times. [Examples]

[0039] In Example 2, we described an example in which the information processing device has multiple memories. However, it is also possible to configure the information processing device to have multiple arithmetic units as well as multiple memories. Example 3 describes an example of an information processing device with such a configuration. In the following description, we will omit explanations that overlap with Examples 1 and 2 and explain the differences.

[0040] Figure 7 shows an example of a functional block diagram of the information processing device according to Embodiment 3, and components identical to those in the information processing devices 110 and 210 shown in Figures 2 and 6 are denoted by the same reference numerals. In Figure 7, the information processing device 310 has a plurality of arithmetic units (hereinafter, arithmetic units 201-1 to 201-n, or one or more arithmetic units collectively referred to as arithmetic unit 201) and a memory dedicated to each arithmetic unit (hereinafter, memories 202-1 to 202-n, or one or more memories collectively referred to as memory 202). For example, in Figure 7, memory 202-1 is a memory dedicated to arithmetic unit 201-1, similarly, memory 202-2 is a memory dedicated to arithmetic unit 201-2, and memory 202-n is a memory dedicated to arithmetic unit 201-n.

[0041] Similar to the information processing device 210 in Embodiment 2, the instruction code holding unit 203 transmits one or more source addresses (source 1 address, source 2 address in the example shown in Figure 7) and one or more destination addresses (storage address in the example shown in Figure 7) from the instruction code holding unit 203 to each memory based on the one or more instruction codes selected by the instruction code holding unit 203. Each memory 202-1 to 202-n outputs one or more source data to each arithmetic unit 201-1 to 201-n according to the one or more source addresses that were input, and stores the one or more result data output by each arithmetic unit 201-1 to 201-n at the location indicated by the one or more destination addresses that were input.

[0042] For example, if source 1 address is "M5", that is, the 5th address from the beginning, the source data stored in the 5th position of memory 202-1 is output to arithmetic unit 201-1, the source data stored in the 5th position of memory 202-2 is output to arithmetic unit 201-2, and similarly the source data stored in the 5th position of memory 202-n is output to arithmetic unit 201-n. Similarly, for the destination address, the result data output from arithmetic unit 201-1 is stored at the location indicated by the destination address of memory 202-1, the result data output from arithmetic unit 201-2 is stored at the location indicated by the destination address of memory 202-2, and similarly the result data output from arithmetic unit 201-n is stored at the location indicated by the destination address of memory 202-n.

[0043] The arithmetic unit 201-1 performs calculations using one or more arithmetic blocks based on one or more source data input from memory 202-1, the arithmetic unit 201-2 performs calculations based on one or more source data input from memory 202-2, and similarly, the arithmetic unit 201-n performs calculations using one or more arithmetic blocks based on one or more source data input from memory 202-n, similar to the arithmetic unit 201 in Example 2, and outputs one or more result data.

[0044] In addition, in the information processing device 310, each arithmetic unit 201-1 to 201-n and each memory 202-1 to 202-n can be provided corresponding to each control target 130-1 to 130-i shown in Figure 1. In this case, each memory 202-1 to 202-n stores the data received from its corresponding control target 130-1 to 130-i, and each arithmetic unit 201-1 to 201-n performs calculations related to its corresponding control target 130-1 to 130-i and outputs one or more result data (in this case, the number of memories, arithmetic units, and control targets will be the same). Furthermore, in this case, the data received from one or more peripheral devices 140 may be stored in common in each memory 202-1 to 202-n, or it may be stored in any specific memory.

[0045] As described above, the information processing device of Embodiment 3 is equipped with multiple arithmetic units and a memory dedicated to each arithmetic unit. A source address and storage address specified in a single instruction code are sent to the memory dedicated to each arithmetic unit. The source data stored at the specified source address in the memory dedicated to each arithmetic unit is input to each arithmetic unit. The arithmetic unit performs the calculation, and result data is output according to the arithmetic unit operation signal specified by the same instruction code. The result data is stored at the location indicated by the storage address in the memory dedicated to each arithmetic unit. With this configuration, in addition to the same effects as Embodiments 1 and 2, it becomes possible to perform parallel calculations using at least n or more source data with a single instruction code. [Examples]

[0046] In Example 2, we described an example in which the information processing device has multiple memories and the arithmetic unit performs calculations based on source data input from all memories. However, some arithmetic units may not have the capability to process a large amount of data input from multiple memories (or may not be able to accept a large amount of data input). In such cases, the arithmetic unit may not be able to operate properly with the configuration in Example 2. Therefore, it is also possible to configure the information processing device to have multiple memories, but connect the arithmetic unit to only one memory, and input source data from that memory and output result data to that memory. Example 4 describes an example of an information processing device with such a configuration. Note that in the following description, explanations that overlap with Examples 1 and 2 will be omitted, and only the differences will be explained.

[0047] Figure 8 shows an example of a functional block diagram of the information processing device according to Embodiment 4, and the same reference numerals are used for components identical to those in the information processing device 210 shown in Figure 6. In Figure 8, the information processing device 410, like the information processing device 210 according to Embodiment 2, includes an arithmetic unit 201, multiple memories (hereinafter referred to as memories 202-1 to 202-n or one or more memories collectively as memory 202), an instruction code holding unit 803, and further includes a connection signal generation unit 801 and a connection determination unit 802.

[0048] The instruction code holding unit 803, similar to the instruction code holding unit 203 in Embodiment 1, holds multiple instruction codes, with one or more source addresses (source 1 address and source 2 address in the example shown in Figure 8), one or more destination addresses (destination addresses in the example shown in Figure 8), arithmetic unit operation signals, and a memory number as one set of instruction codes. The instruction code holding unit 803 selects instruction codes in order and outputs the source address and destination address of the instruction code to each memory 202-1 to 202-n, the arithmetic unit operation signals to the arithmetic unit 201, and the memory number to the connection signal generation unit 801.

[0049] The connection signal generation unit 801 outputs a connection signal to the connection determination unit 802 that determines the connection relationship between the arithmetic unit 201 and each memory 202-1 to 202-n according to the memory number input from the instruction code holding unit 803. The connection determination unit 802 controls, according to the connection signal input from the connection signal generation unit 801, which of the multiple source data input from each memory 202-1 to 202-n will send one or more source data to the arithmetic unit 201, and which of the memory 202-1 to 202-n will send the result data input from the arithmetic unit 201 to.

[0050] Figure 9 shows an example of the configuration of the instruction code holding unit according to Embodiment 4. As described in the explanation of Figure 8, the instruction code holding unit 803 holds multiple instruction codes, each consisting of a set of memory numbers that indicate which of the memories 202-1 to 202-n to connect to the arithmetic unit, that is, which source data from any of the memories 202-1 to 202-n to input to the arithmetic unit, and which of the memories 202-1 to 202-n to store the result data from the arithmetic unit. By specifying a memory number for each instruction code, each instruction code indicates which source data from which memory to use for the calculation, based on the combination of the memory number and each address.

[0051] For example, as shown in the first instruction code in Figure 9, if the memory number is "1", the source 1 address is "M1", the source 2 address is "M5", and the destination address is "M10", this instruction code instructs the arithmetic unit 201 to input the source data stored in the 1st and 5th positions of memory 202-1, and to store the result data in the 10th position from the beginning of memory 202-1. The arithmetic unit operation signals, arithmetic unit operation details, and instruction code length are as described in the explanation of Figure 4.

[0052] Figure 10 shows an example of the configuration of the connection signal generation unit according to Embodiment 4. The connection signal generation unit 801 takes the memory number output by the instruction code holding unit 803 as input and generates a connection signal. The connection signal is a signal with the same number of bits as the number n of memories 202-1 to 202-n. In Figure 10, an example is shown where the connection signal is 5 bits and is a signal that controls the connection between the five memories 202-1 to 202-5 and the arithmetic unit 201. However, as described above, the number of bits in the connection signal changes depending on the number of memories 202-1 to 202-n.

[0053] Each bit of the connection signal controls whether the connection between each memory 202-1 to 202-n and the arithmetic unit 201 is enabled or disabled. The connection signal generation unit 801 generates the connection signal by, for example, setting the least significant bit to "1" if the memory number is "1", the second least significant bit to "1" if the memory number is "2", and similarly setting the most significant bit to "1" and all other bits to "0" if the memory number is "n". If the arithmetic unit 201 is not connected to any of the memories 202-1 to 202-n, the connection signal generation unit 801 sets all bits of the connection signal to 0. The connection signal generated in this way is then transmitted to the connection determination unit 802.

[0054] Furthermore, the connection signal generation unit 801 may generate a connection signal according to the input memory number as described above, or it may, for example, store each connection signal corresponding to each previously generated memory number and extract, identify, or read the connection signal corresponding to the input memory number from among them.

[0055] Figure 11 shows an example of the configuration of the connection determination unit according to Embodiment 4. The connection determination unit 802 has one or more multiplexers 1101 and one or more demultiplexers 1102. Each multiplexer 1101 and demultiplexer 1102 receives a connection signal from the connection signal generation unit 801. The number of multiplexers 1101 is the same as the number of source addresses included in the instruction code (i.e., the number of source data input to the arithmetic unit 201), and the number of demultiplexers 1102 is the same as the number of storage addresses included in the instruction code (i.e., the number of result data output from the arithmetic unit 201). For example, Figure 11 shows an example in which the connection determination unit 802 has two multiplexers 1101-1 and 1101-2 and one demultiplexer 1102, according to the instruction code shown in Figure 9.

[0056] Furthermore, each multiplexer 1101 is associated with each source data, and each demultiplexer 1102 is associated with each result data. Specifically, each multiplexer 1101 receives source data stored at one of the one or more source addresses in the instruction code from each memory 202-1 to 202-n, and outputs one of them according to the connection signal input from the connection signal generation unit 801. Also, each demultiplexer 1102 receives one of the one or more result data output from the arithmetic unit 201, and outputs the result data to one of the memories 202-1 to 202-n according to the connection signal input from the connection signal generation unit 801.

[0057] For example, in Figure 11, the multiplexer 1101-1 takes source 1 data transmitted from each memory 202-1 to 202-n as input and determines the source 1 data to be input to the arithmetic unit 201 according to the connection signal input from the connection signal generation unit 801, that is, it selects and outputs the source 1 data input from the memory with the memory number indicated by the connection signal. Similarly, the multiplexer 1101-2 takes source 2 data transmitted from each memory 202-1 to 202-n as input and determines (selects) and outputs the source 2 data to be input to the arithmetic unit 201 according to the connection signal. The demultiplexer 1102 takes the result data output from the arithmetic unit 201 as input and determines the memory to store the calculation result according to the connection signal input from the connection signal generation unit 801, that is, it selects the memory with the memory number indicated by the connection signal and transmits the calculation result to the determined (selected) memory.

[0058] In this configuration, the arithmetic unit 201 performs calculations based on one or more source data input from one of the memories 202-1 to 202-n specified by the instruction code, and one or more result data output from the arithmetic unit 201 according to the arithmetic unit operation signal are stored in the memory from which the source data was output.

[0059] As described above, the information processing device in Embodiment 4 includes multiple memories, a connection signal generation unit, and a connection determination unit. The connection signal generation unit and the connection determination unit control the connection between the arithmetic unit and the memory according to the memory number specified by the instruction code (the memory number output from the instruction code holding unit) (i.e., they output the source data to be input to the arithmetic unit and determine the memory to store the result data output by the arithmetic unit). This provides the same effects as in Embodiment 1, and even if the arithmetic unit does not have the function to process a large amount of source data output from multiple memories, as in Embodiment 2, it is possible to control the connection between the multiple memories and the arithmetic unit and operate the arithmetic unit properly. Furthermore, with this configuration, if the configuration of the arithmetic unit in the information processing device is changed to enable processing of multiple source data, it is possible to connect the arithmetic unit to multiple memories without changing other configurations. [Examples]

[0060] Example 4 described an example of an information processing device in which one memory number, i.e., one memory, is specified in the instruction code, one or more source data output from that specified memory is input to the arithmetic unit, and one or more result data output from the arithmetic unit is stored in that memory. However, it is also possible to configure the device so that multiple memory locations, which serve as the source and storage destinations, can be specified in the instruction code for each source data input to the arithmetic unit or for each result data output from the arithmetic unit. Example 5 describes an example of an information processing device with such a configuration. Note that in the following description, explanations that overlap with Example 4 will be omitted, and only the differences will be explained.

[0061] Figure 12 shows an example of a functional block diagram of the information processing device according to Embodiment 5, and components identical to those in the information processing device 410 shown in Figure 8 are denoted by the same reference numerals. The configuration of the information processing device 510 according to Embodiment 5 is approximately the same as that of the information processing device 410 shown in Figure 8, but the configurations of the connection signal generation unit 901, the connection determination unit 902, and the instruction code holding unit 903 differ from those shown in Figures 9 to 11. These configurations will be described in order below.

[0062] Figure 13 shows an example of the configuration of the instruction code holding unit according to Embodiment 5. The instruction code holding unit 903 holds multiple instruction codes, each set consisting of one or more source addresses (source 1 address, source 2 address in the example shown in Figure 13), one or more destination addresses for result data (destination addresses in the example shown in Figure 13), and arithmetic unit operation signals, as well as source memory numbers for one or more source data (source 1 memory number, source 2 memory number in the example shown in Figure 13) and destination memory numbers for one or more result data (destination memory numbers in the example shown in Figure 13). The instruction code holding unit 903 sequentially selects instruction codes and outputs the source addresses and destination addresses of the instruction codes to the respective memories 202-1 to 202-n, the arithmetic unit operation signals to the arithmetic unit 201, and each memory number to the connection signal generation unit 901 shown in Figure 14. The arithmetic unit operation signals, arithmetic unit operation details, and instruction code lengths are as described in the explanation of Figure 4.

[0063] As shown in Figure 13, the memory number is specified in the instruction code for each source data and result data. For example, as in the first instruction code in Figure 13, if the source 1 memory number is "1", the source 2 memory number is "2", the destination memory number is "3", the source 1 address is "M1", the source 2 address is "M5", and the destination address is "M10", then the instruction code will instruct the arithmetic unit 201 to input the data stored in the first position of memory 202-1 as source 1 data, the data stored in the fifth position of memory 202-2 as source 2 data, and to store the result data in the tenth position of memory 202-3.

[0064] Note that, as shown in the example above, each memory number in the instruction code may be different, or some or all of the same numbers may be specified, as in the second and third instruction codes in Figure 13. Also, as described above, in the instruction code, a source memory number and a storage memory number are specified for each source data and result data, and the number of these changes depending on the number of source data used in the calculation and the number of result data that are simultaneously generated and output as a result of the calculation. To change the number of memory numbers specified in the instruction code, for example, to specify more memory numbers, the instruction code length may be changed (increased), or the number of bits used by each element constituting the instruction code may be changed (decreased) to secure the bits necessary to specify additional memory numbers.

[0065] Figure 14 shows an example of the configuration of the connection signal generation unit according to Embodiment 5. Similar to the connection signal generation unit 801 shown in Figure 10, the connection signal generation unit 901 takes as input multiple memory numbers output by the instruction code holding unit 903 and generates multiple connection signals corresponding to each memory number. The connection signals are signals with the same number of bits as the number n of memories 202-1 to 202-n. Similar to the example shown in Figure 10, Figure 14 shows an example where the connection signal is 5 bits and is a signal that controls the connection between the five memories 202-1 to 202-5 and the arithmetic unit 201.

[0066] As shown in the example in Figure 13, when the memory numbers for source 1, source 2, and storage destination are specified in the instruction code and input from the instruction code holding unit 903, the connection signal generation unit 901 generates connection signals for source 1, source 2, and storage destination corresponding to each memory number. As described in the explanation of Figure 10, each connection signal is generated with the bit corresponding to the memory number set to 1 and the other bits set to 0. In the example shown in Figure 14, for example, if the source 2 memory number is "2", the second least significant bit corresponding to it is set to "1", and the source 2 connection signal becomes "00010".

[0067] If the arithmetic unit 201 is not connected to any of the memories 202-1 to 202-n, that is, if the values ​​for each memory number are not specified, the connection signal generation unit 901 sets all bits of each connection signal to 0. Similarly, if the values ​​for some memory numbers are not specified, for example, if the result data output from the arithmetic unit 201 is not stored in any of the memories 202-1 to 202-n, the connection signal generation unit 901 sets all bits of the destination connection signal to 0. Each connection signal generated in this way is transmitted from the connection signal generation unit 901 to the connection determination unit 902 shown in Figure 14.

[0068] The connection signal generation unit 901 may generate each connection signal according to each input memory number, as described above, similar to the connection signal generation unit 801 shown in Figure 10. Alternatively, it may store each connection signal corresponding to each memory number that has been generated in advance, and then extract, identify, or read the corresponding connection signal from them for each input memory number.

[0069] Figure 15 is a diagram showing an example of the configuration of the connection determination unit according to Embodiment 5, and the same reference numerals are used for components identical to those of the connection determination unit 802 shown in Figure 11. Similar to the connection determination unit 802 shown in Figure 11, the connection determination unit 902 has one or more multiplexers 1101 and one or more demultiplexers 1102. As described in the explanation of Figure 11, the number of multiplexers 1101 is the same as the number of source addresses included in the instruction code (i.e., the number of source data input to the arithmetic unit 201), and the number of demultiplexers 1102 is the same as the number of storage addresses included in the instruction code (i.e., the number of result data output from the arithmetic unit 201).

[0070] Furthermore, each multiplexer 1101 is associated with each source data, and each multiplexer 1101 receives a source connection signal from the connection signal generation unit 901 corresponding to the source memory number for each source data. Also, each demultiplexer 1102 is associated with each result data, and each demultiplexer 1102 receives a storage destination connection signal from the connection signal generation unit 901 corresponding to the storage destination memory number for each result data.

[0071] For example, Figure 15 shows an example in which the connection determination unit 902 comprises two multiplexers 1101-1 and 1101-2 and one demultiplexer 1102, according to the instruction code shown in Figure 13. Multiplexer 1101-1 is associated with source 1 data, and multiplexer 1101-1 receives source 1 data transmitted from each memory 202-1 to 202-n, as well as a source 1 connection signal corresponding to the source 1 memory number from the connection signal generation unit 901 (in the example of the first instruction code shown in Figures 13 and 14, multiplexer 1101-1 receives source 1 data stored in source 1 address "M1" of each memory 202-1 to 202-n, and also receives the source 1 connection signal "00001" corresponding to the source 1 memory number "1"). The multiplexer 1101-1 determines which source 1 data to input to the arithmetic unit 201 according to the source 1 connection signal, that is, it selects and outputs source 1 data from the memory with the memory number indicated by the source 1 connection signal (in the example above, memory 202-1 with memory number "1" indicated by the source 1 connection signal "00001").

[0072] Multiplexer 1101-2 is associated with source 2 data. Multiplexer 1101-2 receives source 2 data transmitted from each memory 202-1 to 202-n, as well as a source 2 connection signal corresponding to the source 2 memory number from the connection signal generation unit 901 (in the above example, multiplexer 1101-2 receives source 2 data stored in source 2 address "M5" of each memory 202-1 to 202-n, and also receives the source 2 connection signal "00010" corresponding to source 2 memory number "2"). Multiplexer 1101-2 determines which source 2 data to input to the arithmetic unit 201 according to the source 2 connection signal (in the above example, it selects the source 2 data input from memory 202-2 with memory number "2" indicated by the source 2 connection signal "00010") and outputs it.

[0073] The demultiplexer 1102 is associated with the result data output from the arithmetic unit 201. The demultiplexer 1102 receives the result data as input, along with a destination connection signal corresponding to the destination memory number from the connection signal generation unit 901 (in the above example, the demultiplexer 1102 receives the result data and the destination connection signal "00100" corresponding to the destination memory number "3"). The demultiplexer 1102 determines (selects) the memory to store the result data according to the destination connection signal (in the above example, memory 202-3, which corresponds to memory number "3" indicated by the destination connection signal "00100"), and transmits the result data.

[0074] In this configuration, the arithmetic unit 201 performs calculations based on one or more source data inputs from one or more memory locations specified by the instruction code, and the one or more result data output from the arithmetic unit 201 according to the arithmetic unit operation signal are stored in one or more memory locations specified by the instruction code.

[0075] As described above, the information processing device in Embodiment 5 includes multiple memories, a connection signal generation unit, and a connection determination unit. The connection signal generation unit and the connection determination unit control the connection between the arithmetic unit and each memory according to multiple memory numbers (multiple memory numbers output from the instruction code holding unit) specified by the instruction code for each source data and each result data. This configuration determines which memory outputs each source data to be input to the arithmetic unit, and which memory stores each result data output by the arithmetic unit. In addition to the same effects as Embodiments 1 and 4, this makes it possible to arbitrarily specify the source data to be input to the arithmetic unit from multiple memories, and to arbitrarily specify which memory stores the result data output from the arithmetic unit. This makes it possible to connect the arithmetic unit to multiple memories simultaneously and to operate the arithmetic unit properly, even if the arithmetic unit does not have the function to process a large amount of data output from multiple memories, as in Embodiment 2. [Examples]

[0076] In Example 4, an example was described in which the information processing device has one arithmetic unit. However, it is also possible to configure the information processing device to have multiple arithmetic units and multiple dedicated memories for each arithmetic unit. Example 6 describes an example of an information processing device with such a configuration. In the following description, explanations that overlap with Example 4 will be omitted, and only the differences will be explained.

[0077] Figure 16 shows an example of a functional block diagram of the information processing device according to Embodiment 6, and components identical to those in the information processing device 410 shown in Figure 8 are denoted by the same reference numerals. In Figure 16, the information processing device 610 includes an instruction code holding unit 803 and a connection signal generation unit 801, as well as a plurality of arithmetic units 201-1, 201-2, ..., a plurality of dedicated memories 202-1 to 202-n, 204-1 to 204-n, ... for each arithmetic unit, and also dedicated connection determination units 802-1, 802-2, ... for each arithmetic unit.

[0078] The instruction code holding unit 803 outputs one or more source addresses and storage addresses of the instruction code (in the example shown in Figure 16, source 1 address, source 2 address, and storage address) to each memory 202-1 to 202-n, 204-1 to 204-n, ... to the connection signal generation unit 801, and to each arithmetic unit 201-1, 201-2, ...

[0079] The connection signal generation unit 801 generates connection signals that determine the connection relationship between each arithmetic unit 201-1, 201-2, ... and the dedicated memories 202-1~202-n, 204-1~204-n, ... according to the memory number input from the instruction code holding unit 803, and outputs these signals to the respective connection determination units 802-1, 802-2, ...

[0080] The connection determination unit 802-1, in accordance with the connection signal input from the connection signal generation unit 801, determines which of the multiple source data (source 1 data and source 2 data in the example shown in Figure 16) input from each of the dedicated memories 202-1 to 202-n for the arithmetic unit 201-1 will send to the arithmetic unit 201-1, and also determines which of the dedicated memories 202-1 to 202-n for the arithmetic unit 201-1 will store the one or more result data input from the arithmetic unit 201-1. The connection determination unit 802-1 sends the one or more source data (source 1 data and source 2 data in the example shown in Figure 16) determined as described above to the arithmetic unit 201-1, and sends the result data output from the arithmetic unit 201-1 to the determined memory.

[0081] The connection determination unit 802-2 also performs the same processing (operation) as the connection determination unit 802-2 between the memory 204-1 to 204-n dedicated to the arithmetic unit 201-2 and the arithmetic unit 201-2. Although not shown in Figure 16, each of the other connection determination units also performs the same processing (operation) as the connection determination units 802-1 and 802-2 between the multiple memory assemblies dedicated to each of the other arithmetic units and each arithmetic unit.

[0082] As described above, the information processing device in Embodiment 6 is configured to include, in addition to the configuration of the information processing device in Embodiment 4, one or more arithmetic units, multiple memories dedicated to each arithmetic unit, and a connection determination unit. This provides the same effects as Embodiments 1 and 4, but also enables the execution of parallel operations using one or more source data with a single instruction code. [Examples]

[0083] Example 5 described an information processing device equipped with multiple memories, in which the instruction code specifies the memory numbers of the source and destination memories for each source data and result data, inputs one or more source data output from each specified memory to the arithmetic unit, and stores one or more result data output from the arithmetic unit in each specified memory. However, it is also possible to configure the device to have one or more register files in addition to multiple memories. Example 7 describes an example of an information processing device with such a configuration. Note that in the following description, explanations that overlap with Examples 4 and 5 will be omitted, and only the differences will be explained.

[0084] Figure 17 shows an example of a functional block diagram of the information processing device according to Embodiment 7, and the same components as those in the information processing device 510 shown in Figure 12 are denoted by the same reference numerals. In Figure 17, the information processing device 710 includes an arithmetic unit 201, multiple memories (hereinafter referred to as memories 202-1 to 202-n or one or more memories collectively as memory 202), an instruction code holding unit 1003, a connection signal generation unit 1001 and a connection determination unit 902, and one or more register files 1010, ..., similar to the information processing device 510 according to Embodiment 5. Note that Figure 16 shows a configuration with one register file 1010.

[0085] The configuration of the instruction code holding unit 1003 is roughly the same as that of the instruction code holding unit 903 shown in Figure 13. However, the instruction code holding unit 1003 outputs the source address and storage address of the instruction code to one or more register files 1010, ... in addition to each memory 202-1 to 202-n, and also outputs the arithmetic unit operation signals in addition to each memory number to the connection signal generation unit 1001.

[0086] Figure 18 shows an example of the configuration of a register file according to Embodiment 7. Figure 18 shows an example of the configuration of register file 1010 as representative of one or more register files, and other register files have a similar configuration. In Figure 18, register file 1010 is composed of multiple registers, and each register holds one source data R-1, R-2, R-3, ... As shown in Figure 18, each register is assigned a register number R1, R2, R3, ... The register numbers R1, R2, R3, ... indicate the storage location of the multiple source data R-1, R-2, R-3, ... held by register file 1010, and are equivalent to addresses in memory. Therefore, when the arithmetic unit 201 performs an operation using any of the source data R-1, R-2, R-3, ... held in the register file 1010, the instruction code specifies one or more register numbers as the source address and storage address, and outputs the instruction code from the instruction code holding unit 1003 to each memory 202-1 to 202-n and each register file 1010, ...

[0087] Furthermore, although not shown in Figures 17 and 18, each of the one or more register files 1010, ... provided by the information processing device 710 is assigned a register file number. The register file number specifies or identifies each register file and is equivalent to a memory number. Therefore, when an operation is performed in the arithmetic unit 201 using source data held in any of the register files, one or more register file numbers are specified as memory numbers in the instruction code and output from the instruction code holding unit 1003 to the connection signal generation unit 1001 along with the arithmetic unit operation signal.

[0088] In the example shown in Figure 18, the register numbers are represented as R1, R2, R3, ..., but register numbers can be represented in various other ways. Also, the number of register files provided by the information processing device 710 and the number of registers contained in each register file vary depending on the configuration of the information processing device 710 and the higher-level control device 100, as well as the implementation form of the register files.

[0089] Figure 19 shows an example of the configuration of the connection signal generation unit according to Embodiment 7. The connection signal generation unit 1001 takes the arithmetic unit operation signals output by the instruction code holding unit 1003 and multiple memory numbers as input and generates multiple connection signals corresponding to each memory number. In Figure 19, an example is shown in which the connection signal is 6 bits, with the upper 5 bits controlling the connection between five memories 202-1 to 202-5 and the arithmetic unit 201, and the lower 1 bit controlling the connection between the register file 1010 and the arithmetic unit 201. However, the number of bits in the connection signal will vary depending on the number of memories 202-1 to 202-n and the number of register files.

[0090] For example, if the arithmetic unit operation signal instructs an operation using source data from memory 202-1 to 202-n, each connection signal is generated with the bit corresponding to the memory number set to "1", as described in the explanation of Figure 14. In the example shown in Figure 19, for example, if the source 1 memory number is "1", the source 1 connection signal becomes "000010", with the corresponding least significant bit of the upper 5 bits set to "1".

[0091] On the other hand, if the arithmetic unit operation signal instructs an operation using the data in register file 1010, the connection signal is generated with the least significant bit corresponding to register file 1010 set to "1". For example, as in the fourth example in Figure 19, if the arithmetic unit operation signal instructs to add two data held in register file 1010 and store them in the register file, in the example shown in Figure 19, since there is only register file 1010, the memory numbers for source 1, source 2, and storage destination are left blank, indicating that register file 1010 will be used. The connection signal generation unit 1001 generates connection signals "000001" with the least significant bit set to "1" as the connection signals for source 1, source 2, and storage destination. However, leaving the memory number blank is just one example; the register file number of register file 1010 may be specified as the memory number, or, if the information processing device 710 has multiple register files, the register file number of each register file may be specified as the memory number, as described above.

[0092] Furthermore, when the arithmetic unit operation signals instruct data movement between memories 202-1 to 202-n and register file 1010, such as memory load or memory store, in the seventh memory load example in Figure 19, the memory from which the source data is output is specified by the source 1 memory number, and the register file 1010 is specified by the destination memory number, and the source 1 connection signal and destination connection signal are generated accordingly. Similarly, in the eighth memory store example in Figure 19, the register file 1010 is specified by the source 1 memory number, and the memory to which the data is stored is specified by the destination memory number, and the source 1 connection signal and destination connection signal are generated accordingly. In this way, in the case of data movement between memories 202-1 to 202-n and register file 1010, the source 1 connection signal and destination connection signal indicate the movement path of the source data.

[0093] In Figure 19, similar to the example shown in Figure 4, an example is shown in which arithmetic unit operation signals, such as addition and multiplication, and the use of a register file are represented by 6 bits. The upper 2 bits of the 6 bits indicate whether the register file and memory are being used simultaneously. For example, if the upper 2 bits are "00", only memory is used; if they are "10", only the register file is used; and if they are "11", both the register file and memory are being used. The connection signal generation unit 1001 identifies the above instructions based on these arithmetic unit operation signals and generates the respective connection signals.

[0094] Each connection signal generated in the manner described above is transmitted from the connection signal generation unit 1001 to the connection determination unit 902. The connection signal generation unit 1001 may generate each connection signal according to each input memory number as described above, similar to the connection signal generation unit 901 shown in Figure 14. Alternatively, it may, for example, store each connection signal corresponding to each memory number that has been generated in advance, and extract, identify, or read the corresponding connection signal from them for each input memory number.

[0095] Figure 20 shows an example of the configuration of the connection determination unit according to Embodiment 7. The connection determination unit 902 shown in Figure 20 is the same as the connection determination unit 902 shown in Figure 15, and all components are denoted by the same reference numerals. However, in the connection determination unit 902 shown in Figure 20, as shown in the figure, each multiplexer 1101 receives source data from each memory 202-1 to 202-n, as well as source data from the register file 1010. Each multiplexer 1101 determines (selects) the source data to be input to the arithmetic unit 201 according to each source connection signal input from the connection signal generation unit 1001 and outputs it. Each demultiplexer 1102 receives result data from the arithmetic unit 201, and each demultiplexer 1102 determines (selects) whether to store the result data in one of the memories 202-1 to 202-n or the register file 1010 according to the storage destination connection signal input from the connection signal generation unit 1001, and transmits the result data.

[0096] In Figure 20, as in Figure 15, an example is shown where the connection determination unit 902 has two multiplexers 1101-1 and 1101-2 and one demultiplexer 1102. However, as described in the explanation of Figure 15, the number of multiplexers 1101 is the same as the number of source addresses included in the instruction code (i.e., the number of source data input to the arithmetic unit 201), and the number of demultiplexers 1102 is the same as the number of storage addresses included in the instruction code (i.e., the number of result data output from the arithmetic unit 201). Also, in Figure 20, following the example shown in Figure 17, there is one source data from the register file input to each multiplexer 1101 (only source data from register file 1010), and there is also one register file to which the demultiplexer 1102 outputs (only register file 1010). However, if the information processing device 710 has multiple register files, there will be multiple for each.

[0097] In the above description of Embodiment 7, as shown in Figure 17, the information processing device 710 is equipped with one arithmetic unit 201 and one connection determination unit 902. However, as in Embodiments 3 and 6, it is also possible to configure it to be equipped with one or more arithmetic units, one or more memories dedicated to each arithmetic unit, one or more register files, and a connection determination unit.

[0098] As described above, the information processing device in Embodiment 7 includes one or more register files in addition to multiple memories. In the instruction code, each address specifies the address of each memory or the register number of each register file, and each memory number specifies each memory or each register file. In response to these memory numbers and arithmetic unit operation signals, the connection signal generation unit generates connection signals, including the specification of each register file, and the connection determination unit controls the connection between the arithmetic unit and each memory and each register file. This provides the same effects as Embodiments 1, 4, and 5, but also makes it possible to connect the arithmetic unit to multiple memories and register files as appropriate and perform calculations without significantly changing the configuration of the information processing device, even when the arithmetic unit configuration requires one or more register files.

[0099] Although embodiments of the present invention have been described in detail above, the present invention is not limited to the embodiments described above, and various design modifications can be made without departing from the spirit of the invention as described in the claims. For example, each of the embodiments described above is described in detail in order to explain the present invention in an easy-to-understand manner, and is not necessarily limited to having all of the described configurations. Furthermore, it is possible to replace a part of the configuration of one embodiment with the configuration of another embodiment, and it is also possible to add a configuration from another embodiment to the configuration of one embodiment. In addition, it is possible to add, delete, or replace a part of the configuration of each embodiment with other configurations. [Explanation of symbols]

[0100] 100...Control device 110, 210, 310, 410, 510, 610, 710… Information Processing Devices 120...Communication device 130, 2030…Controlled 140…Peripheral devices 201...Arithmetic unit 202, 204…memory 203, 803, 903, 1003... Instruction code holding unit 501... Adder 502...Logical Unit 503... Multiplier 504...Divider 505...Calculation result selection unit 801, 901, 1001... Connection signal generation unit 802, 902... Connection determination section 1010...Register file 1101... Multiplexer 1102... Demultiplexer 2000… Edge device 2010…CPU 2020...communication buffer

Claims

1. An information processing device, Memory that holds multiple source data, A calculation unit that performs calculations using one or more source data input from the memory and outputs one or more result data, An instruction code holding unit that holds a plurality of instruction codes including one or more source addresses in the memory where the one or more source data are stored, one or more destination addresses in the memory where the one or more result data are stored, and an arithmetic unit operation signal that instructs the operation of the arithmetic unit, It has at least the following features: The instruction code holding unit selects one instruction code, transmits the one or more source addresses and storage addresses included in the instruction code to the memory, and transmits the arithmetic unit operation signal to the arithmetic unit. The memory outputs the one or more source data stored at the one or more source addresses input from the instruction code holding unit, and stores the one or more result data input from the arithmetic unit at each of the one or more destination addresses. The arithmetic unit performs calculations using the one or more source data input from the memory, in accordance with the operation instructed by the arithmetic unit operation signal input from the instruction code holding unit. Information processing device.

2. An information processing apparatus according to claim 1, The memory comprises multiple such memories, The instruction code holding unit transmits the one or more source addresses and the storage destination addresses to the multiple memories. Each of the plurality of memories outputs the one or more source data stored at the one or more source addresses input from the instruction code holding unit. The arithmetic unit performs calculations using the multiple source data input from each of the multiple memories. Information processing device.

3. An information processing apparatus according to claim 1, The system comprises multiple arithmetic units and multiple memories, Each of the plurality of memories is a dedicated memory for each of the plurality of arithmetic units, The instruction code holding unit transmits the one or more source addresses and the storage destination addresses to the multiple memories. Each of the plurality of memories outputs the one or more source data stored at the one or more source addresses input from the instruction code holding unit. Each of the plurality of arithmetic units performs calculations using the one or more source data input from the dedicated memory. Information processing device.

4. An information processing apparatus according to claim 1, The system further comprises multiple memories, a connection signal generation unit, and a connection determination unit. The instruction code further includes a memory number, and the instruction code holding unit transmits the one or more source addresses and the storage destination addresses to the multiple memories, and transmits the memory number to the connection signal generation unit. Each of the plurality of memories outputs the one or more source data stored at the one or more source addresses input from the instruction code holding unit to the connection determination unit. The connection signal generation unit outputs a connection signal to the connection determination unit that determines the connection relationship between the arithmetic unit and each of the plurality of memories according to the memory number input from the instruction code holding unit. The connection determination unit outputs the one or more source data input from one of the multiple memories to the arithmetic unit in accordance with the connection signal input from the connection signal generation unit. The arithmetic unit performs calculations using the one or more source data input from the connection determination unit. Information processing device.

5. An information processing apparatus according to claim 1, The system further comprises multiple memories, a connection signal generation unit, and a connection determination unit. The instruction code further includes at least one or more source memory numbers, the instruction code holding unit transmits the one or more source addresses and the storage destination addresses to the multiple memories, and transmits the one or more source memory numbers to the connection signal generation unit. Each of the plurality of memories outputs the one or more source data stored at the one or more source addresses input from the instruction code holding unit to the connection determination unit. The connection signal generation unit outputs one or more connection signals to the connection determination unit that determine the connection relationship between the arithmetic unit and each of the multiple memories according to the one or more source memory numbers input from the instruction code holding unit. The connection determination unit determines, for each of the one or more connection signals input from the connection signal generation unit, one of the one or more source data input from one of the multiple memories and outputs it to the arithmetic unit. The arithmetic unit performs calculations using the one or more source data input from the connection determination unit. Information processing device.

6. An information processing apparatus according to claim 1, The system further comprises multiple memories, one or more register files, a connection signal generation unit, and a connection determination unit. The instruction code further includes at least one or more source memory numbers, the instruction code holding unit transmits the one or more source addresses and the storage address to the multiple memories and the one or more register files, and transmits the one or more source memory numbers and the arithmetic unit operation signals to the connection signal generation unit. Each of the plurality of memories outputs the one or more source data stored at the one or more source addresses input from the instruction code holding unit to the connection determination unit. If any or all of the source addresses in each of the one or more register files are register numbers, the one or more source data stored in each of the one or more register numbers is output to the connection determination unit. The connection signal generation unit outputs one or more connection signals to the connection determination unit that determine the connection relationship between the arithmetic unit and each of the multiple memories and the one or more register files, in accordance with the one or more source memory numbers and arithmetic unit operation signals input from the instruction code holding unit. The connection determination unit determines, for each of the one or more connection signals input from the connection signal generation unit, one of the one or more source data input from one of the multiple memories or one of the one or more register files, and outputs it to the arithmetic unit. The arithmetic unit performs calculations using the one or more source data input from the connection determination unit. Information processing device.

7. An information processing system, One or more controlled objects, A control device that controls each of the one or more of the control objects, It has at least the following features: The control device is The information processing apparatus according to claim 1, A communication device that communicates with each of the one or more of the aforementioned controlled objects, Equipped with, Information processing system.

8. An information processing method in an information processing device comprising a memory that holds multiple source data, and an arithmetic unit that performs calculations using one or more of the source data input from the memory according to an instruction code and outputs one or more result data, In the instruction code, one or more source addresses in the memory where the one or more source data are stored, one or more destination addresses in the memory where the one or more result data are stored, and an arithmetic unit operation signal that instructs the operation of the arithmetic unit are specified. The one or more source addresses and the destination address in the instruction code are input into the memory. The arithmetic unit operation signal in the instruction code is input to the arithmetic unit, The one or more source data stored at the one or more source addresses are input from the memory to the arithmetic unit. In the arithmetic unit, in accordance with the operation instructed by the arithmetic unit operation signal, calculations are performed using the one or more source data input from the memory. In the memory, the one or more result data output from the arithmetic unit are stored in each of the one or more storage destination addresses. Information processing methods.

9. The information processing method according to claim 8, The information processing device comprises a plurality of the memories, The one or more source addresses and the destination addresses in the instruction code are input into the multiple memories. The one or more source data stored at the one or more source addresses are input to the arithmetic unit from each of the multiple memories. In the aforementioned arithmetic unit, calculations are performed using the multiple source data input from each of the multiple memories. Information processing methods.

10. The information processing method according to claim 8, The information processing device comprises a plurality of arithmetic units and a dedicated memory for each of the plurality of arithmetic units. The one or more source addresses and the destination addresses in the instruction code are input into the multiple memories. Each of the plurality of arithmetic units receives input from the dedicated memory of the one or more source data stored at the one or more source addresses. Each of the plurality of arithmetic units performs an operation using the input one or more of the source data. Information processing methods.

11. The information processing method according to claim 8, The information processing device further comprises a plurality of memories, a connection signal generation unit, and a connection determination unit. In the aforementioned instruction code, a memory number is further specified, The one or more source addresses and the destination addresses in the instruction code are input into the multiple memories. The memory number in the instruction code is input to the connection signal generation unit. The one or more source data stored at the one or more source addresses are input to the connection determination unit from each of the multiple memories. A connection signal that determines the connection relationship between the arithmetic unit corresponding to the memory number and each of the plurality of memories is input from the connection signal generation unit to the connection determination unit. According to the connection signal, the connection determination unit inputs the one or more source data input from one of the multiple memories to the arithmetic unit, In the aforementioned arithmetic unit, calculations are performed using the one or more of the aforementioned source data. Information processing methods.

12. The information processing method according to claim 8, The information processing device further comprises a plurality of memories, a connection signal generation unit, and a connection determination unit. The instruction code further specifies at least one or more source memory numbers, The one or more source addresses and the destination addresses in the instruction code are input into the multiple memories. The one or more source memory numbers in the instruction code are input to the connection signal generation unit. The one or more source data stored at the one or more source addresses are input to the connection determination unit from each of the multiple memories. One or more connection signals are input from the connection signal generation unit to the connection determination unit to determine the connection relationship between the arithmetic unit corresponding to the one or more source memory numbers and each of the multiple memories. In the connection determination unit, for each of the one or more connection signals, one of the one or more source data input from one of the multiple memories is determined and input to the arithmetic unit. In the aforementioned arithmetic unit, calculations are performed using the one or more of the aforementioned source data. Information processing methods.

13. The information processing method according to claim 8, The information processing device further comprises a plurality of memories, one or more register files, a connection signal generation unit, and a connection determination unit. The instruction code may further specify one or more source memory numbers, The one or more source addresses and the destination addresses in the instruction code are input to the multiple memories and the one or more register files. The one or more source memory numbers and the arithmetic unit operation signals in the instruction code are input to the connection signal generation unit. The one or more source data stored at the one or more source addresses are input to the connection determination unit from each of the multiple memories. If any or all of the one or more source addresses are register numbers, the one or more source data stored in each of the one or more register numbers are input to the connection determination unit from each of the one or more register files. One or more connection signals are input from the connection signal generation unit to the connection determination unit, in accordance with the one or more source memory numbers and the arithmetic unit operation signals, to determine the connection relationship between the arithmetic unit and each of the multiple memories and the one or more register files. In the connection determination unit, for each of the one or more connection signals, one of the one or more source data input from one of the multiple memories or one of the register files is determined and input to the arithmetic unit. In the aforementioned arithmetic unit, calculations are performed using the one or more of the aforementioned source data. Information processing methods.

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