Battery management system and communication method for battery management

Abstract

The objective is to provide a battery management system and a battery management communication method that can reduce the number of external terminals and alleviate the load on the microcontroller. [Solution] Each address space of the memory 20 (000h~10Bh, 10Ch~217h, 218h~322h) is connected to the communication processing unit 22, and data is output to the MCU 18 via the communication processing unit 22. Each address space of the memory 20 (000h~10Bh, 10Ch~217h, 218h~322h) is connected to the OR circuit 24, and the packet storage flags are combined into a single line by the OR circuit 24 and output to an external terminal. In addition, an address change unit 26 is added to the communication processing unit 22, and the packet storage flags are input to the address change unit 26, and the address change unit 26 changes the data request address in response to a data request from the MCU based on the packet storage flags.

Description

Technical Field

[0001] The present disclosure relates to a battery management system and a communication method for battery management.

Background Art

[0002] Products equipped with batteries, such as electric vehicles, etc., are equipped with a battery management system (BMS: Battery Management System) for monitoring and controlling the state of the battery, and various technologies related to the BMS have been proposed.

[0003] For example, Patent Document 1 discloses a battery monitoring IC for a battery monitoring system that includes a first buffer amplifier and a second buffer amplifier that are driven by a power supply voltage or a boosted voltage, and an input terminal is connected to one end of any one of the battery cells of the battery pack. The control unit selects the battery cell connected to the input terminals of the first buffer amplifier and the second buffer amplifier, and when a higher-level battery cell is selected, switches the voltage for driving the first buffer amplifier and the second buffer amplifier to the boosted voltage, and when a battery cell other than the higher-level battery cell is selected, switches the voltage for driving the first buffer amplifier and the second buffer amplifier to the power supply voltage. Also, Patent Document 2 discloses that a first communication device and a second communication device each transmit different transmission request signals to a bus, and the bus is controlled to receive data from either communication device. The transmission request signals have different lengths, and communication is performed while monitoring the state of the bus to resolve communication conflicts.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

[0005] [Summary] Incidentally, in conventional battery management systems, voltage and current measurement data may be received from multiple paths, stored in multiple storage units, and transmitted in response to requests from the microcontroller. In this case, it is necessary to provide external terminals corresponding to each of the storage units to inform the microcontroller that data has been stored in the storage units.

[0006] Therefore, this disclosure has been made in consideration of the above facts, and aims to provide a battery management system and a battery management communication method that can reduce the number of external terminals and reduce the load on the microcontroller.

[0007] The battery management system according to this disclosure includes: a plurality of storage units with separate memory address spaces, each assigned to a plurality of communication paths, which store data received from the communication paths and output data storage information; an output unit that receives the data storage information from the plurality of storage units and outputs the data storage information; a modification unit that modifies the data request address in response to a data request from a microcontroller (MCU) that has received the data storage information from the output unit; and a communication processing unit that reads the data stored in the storage unit corresponding to the data request address modified by the modification unit and outputs it to the microcontroller. [Brief explanation of the drawing]

[0008] [Figure 1] Figure 1 is a block diagram showing the schematic configuration of the BMS according to this embodiment. [Figure 2] Figure 2 shows an example of the packet configuration used in the BMS according to this embodiment. [Figure 3] Figure 3 is a diagram illustrating the conventional method of inputting and outputting received data (when packet data is input). [Figure 4] Figure 4 is a diagram illustrating the conventional method of inputting and outputting received data (when a memory read request is made). [Figure 5]Figure 5 is a diagram illustrating the conventional method of inputting and outputting received data (when memory data is output). [Figure 6] Figure 6 is a block diagram showing the configuration of the communication IC of the BMS according to the first embodiment. [Figure 7] Figure 7 is a diagram illustrating the method for inputting and outputting received data (when packet data is input) of the communication IC of the BMS according to the first embodiment. [Figure 8] Figure 8 is a diagram illustrating the method for inputting and outputting received data (when a memory read request is made) of the communication IC of the BMS according to the first embodiment. [Figure 9] Figure 9 is a diagram illustrating the method for inputting and outputting received data (when outputting memory data) of the communication IC of the BMS according to the first embodiment. [Figure 10] Figure 10 is a block diagram showing the configuration of the communication IC of the BMS according to the second embodiment. [Figure 11] Figure 11 is a diagram illustrating the received data input / output method (when packet data is input) of the BMS communication IC according to the second embodiment. [Figure 12] Figure 12 is a diagram illustrating the method for inputting and outputting received data (when a memory read request is made) of the communication IC of the BMS according to the second embodiment. [Figure 13] Figure 13 illustrates the data input / output method (when memory data is output) of the communication IC of the BMS according to the second embodiment. [Detailed explanation]

[0009] Hereinafter, an example of an embodiment of the present disclosure will be described in detail with reference to the drawings. In this embodiment, a Battery Management System (BMS) applied to products including electric vehicles will be described as an example. Figure 1 is a block diagram showing the schematic configuration of the BMS according to this embodiment.

[0010] This embodiment describes an example of a BMS10 that includes a voltage monitoring IC (Integrated Circuit) 12, a current monitoring IC 14, a communication IC 16, and an MCU (microcontroller) 18.

[0011] The voltage monitoring IC 12 detects the voltage measurement of the battery and voltage abnormalities. The number of stages of the configuration changes depending on the number of cells of the battery. Insulation treatment is performed between each voltage monitoring IC 12, and they are connected in series via a communication line. Communication with the MCU 18 is enabled through each voltage monitoring IC 12 and the communication IC 16.

[0012] The current monitoring IC 14 detects the current measurement of the battery and current abnormalities. It is insulated and connected to the communication IC 16 via a communication line. Communication with the MCU 18 is enabled through the communication IC 16.

[0013] The communication IC 16 is a conversion IC that performs the conversion from SPI communication to insulated communication and from insulated communication to SPI communication. Also, the communication IC 16 has a memory so that measurement data etc. from each monitoring IC can be temporarily stored.

[0014] The MCU 18 is a control IC for each monitoring IC such as the voltage monitoring IC 12 and the current monitoring IC 14, and the communication IC 16.

[0015] Among these, since there are multiple communication paths (for example, communication paths 1, 2, and 3 in FIG. 1) for the register read / write command from the MCU 18, the communication IC 16 must send the command in the appropriate direction and temporarily store the received response data from the communication path.

[0016] Note that the description of each of the above ICs is an example of the configuration of the BMS, and not all BMSs have such functions and connections.

[0017] In the BMS 10 according to the present embodiment, communication between each IC is performed in a communication unit called a packet. FIG. 2 is a diagram showing a configuration example of the packet used in the BMS 10 according to the present embodiment.

[0018] As shown in FIG. 2, the packet has a first frame, a second frame, a CRC1 frame, a register frame, a data frame, and a CRC2 frame.

[0019] The first frame is used for storing the ID of each IC and for packet determination.

[0020] The second frame is used for packet determination and storing the number of data frames.

[0021] The CRC1 frame is the result of the CRC calculation generated for the first and second frames.

[0022] The register frame is used to store the register addresses to write, the register addresses to read, and the read register addresses.

[0023] A data frame consists of the values ​​of the registers being written to and the values ​​of the registers being read.

[0024] The CRC2 frame is the result of the CRC calculation generated for registers and data frames.

[0025] Packets are divided into command packets and response packets based on the first frame and second frame.

[0026] The instruction packet is a register read / write request from the MCU18, and is a read / write response to the instruction generated by the voltage monitoring IC12, current monitoring IC14, and communication IC16 in each communication path. It is temporarily stored in the memory of the communication IC16 after passing through each communication path. Subsequently, the response packet is transmitted to the MCU18 via a communication IC memory read request from the MCU18. At this time, the MCU18 does not need to indicate which communication path the data came from, as it determines which IC the information in the packet came from based on the ID.

[0027] Here, the conventional input / output methods for received data will be explained with reference to Figures 3 to 5. Figure 3 is a diagram illustrating the conventional input / output method for received data (when packet data is input). Figure 4 is a diagram illustrating the conventional input / output method for received data (when a memory read request is made). Figure 5 is a diagram illustrating the conventional input / output method for received data (when memory data is output). Figures 3 to 5 show the exchange between MCUs 18 when data arrives on communication path 2.

[0028] In conventional communication ICs 16, in order to handle simultaneous packet data input from two or more communication paths from each monitoring IC (voltage monitoring IC 12 and current monitoring IC 14), the memory 20 is divided into multiple address spaces, and data is stored in the address space of the memory 20 corresponding to each communication path.

[0029] (1) As shown in Figure 3, packet data from communication path 2 is received. The data from communication path 2 is stored in memory 20 at addresses 10Ch~217h. (2) As shown in Figure 4, memory 20 detects the accumulation of packets at addresses 10Ch to 217h and sets a flag on the external terminal (packet accumulation flag). (3) As shown in Figure 4, the MCU 18 detects the accumulation of data at addresses 10Ch to 217h in memory 20. (4) As shown in Figure 4, the MCU 18 issues a read request for addresses 10Ch to 217h of memory 20. (5) As shown in Figure 5, the communication processing unit 22 accesses addresses 10Ch to 217h of the memory 20 and outputs data to the MCU 18.

[0030] In conventional methods of inputting and outputting received data, the MCU18 has to detect the packet storage flag of each packet and select the corresponding address space in memory 20, which places a heavy load on the MCU18.

[0031] Furthermore, if the packet storage flag is output as an external terminal, a packet storage flag is required for each receiving path, which increases the number of external terminals.

[0032] Therefore, in the BMS10 according to this embodiment, the data output for each communication path is controlled within the communication IC16 to reduce the load on the MCU18 and the number of external terminals.

[0033] (First Embodiment) The configuration of the communication IC 16 of the BMS 10 according to the first embodiment will now be described. Figure 6 is a block diagram showing the configuration of the communication IC 16 of the BMS 10 according to this embodiment.

[0034] The communication IC 16 of the BMS 10 according to this embodiment, as in the conventional model, is equipped with an address space of the memory 20 (000h to 10Bh, 10Ch to 217h, 218h to 322h) as a storage unit for each communication path (communication paths 1, 2, and 3 in Figure 6). That is, the memory 20 has multiple addresses and outputs partial data depending on the requested address when reading.

[0035] Each address space of memory 20 (000h~10Bh, 10Ch~217h, 218h~322h) is connected to the communication processing unit 22, and data is output to the MCU 18 via the communication processing unit 22.

[0036] Furthermore, in this embodiment, each address space of the memory 20 (000h to 10Bh, 10Ch to 217h, 218h to 322h) is connected to an OR circuit 24, which is an example of an output unit, and the packet storage flags, which are an example of data storage flags, are combined into a single line by the OR circuit 24 and output to an external terminal.

[0037] Furthermore, an address change unit 26 is added to the communication processing unit 22 as an example of a change unit, and the packet storage flag is input to the address change unit 26. Based on the packet storage flag, the address change unit 26 changes the data request address in response to a data request from the MCU 18. This makes it possible to communicate without changing the data request from the MCU 18 for each communication path.

[0038] Next, the input / output methods for received data of the communication IC 16 of the BMS 10 according to this embodiment will be explained with reference to Figures 7 to 9. Figure 7 is a diagram illustrating the input / output method for received data of the communication IC 16 of the BMS 10 according to this embodiment (when packet data is input). Figure 8 is a diagram illustrating the input / output method for received data of the communication IC 16 of the BMS 10 according to this embodiment (when a memory read request is made). Figure 9 is a diagram illustrating the input / output method for received data of the communication IC 16 of the BMS 10 according to this embodiment (when memory data is output). Figures 7 to 9 show the exchange between the MCUs 18 when data arrives on the communication path 2.

[0039] (1) As shown in Figure 7, packet data from communication path 2 is received. The data from communication path 2 is stored in memory 20 at addresses 10Ch~217h. (2) As shown in Figure 8, the memory 20 detects the accumulation of packets at addresses 10Ch to 217h and outputs a packet accumulation flag to the external terminal connected via the OR circuit 24 and the address change unit 26. In this embodiment, as an example, when one packet is received, a data accumulation flag is output. (3) As shown in Figure 8, the MCU 18 detects memory storage at any of the addresses (000h to 10Bh, 10Ch to 217h, 218h to 322h) in memory 20. (4) As shown in Figure 8, the MCU 18 issues a read request for addresses 000h to 10Bh in memory 20. The MCU 18 does not know which memory 20 address has stored the packet. (5) As shown in Figure 8, the address change unit 26 changes the address value based on the packet storage flag. In the example in Figure 8, the address 000h~10Bh of the request from MCU18 is changed to address 10Ch~217h. (6) As shown in Figure 9, addresses 10Ch to 217h of memory 20 output data and output it to MCU 18 via the communication processing unit 22. Since each monitoring IC's ID is assigned to the data in the packet, it is not a problem even if MCU 18 does not know which communication path the packet data came from.

[0040] In this way, the address change unit 26 changes the address, eliminating the need for address selection from the MCU 18's perspective, while internally it can output the appropriate memory data containing the accumulated packets. This reduces the number of external terminals and lessens the load on the microcontroller.

[0041] In Figures 7-9, the case where data arrives via a single communication path (communication path 2) is explained. However, if data arrives via multiple communication paths, the address change unit 26 may preferentially change the address to the lowest address.

[0042] For example, when data arrives on communication paths 2 and 3, addresses 10Ch~217h and 218h~322h in memory 20 detect packet storage and output a packet storage flag to the OR circuit 24. The OR circuit 24 receives the packet storage flag from the addresses (10Ch~217h, 218h~322h) and outputs the packet storage flag to an external terminal. As a result, the MCU 18 detects memory storage in any of the address spaces of memory 20 and issues a read request for addresses 000h~10Bh (the MCU 18 does not know which memory 20 address has stored the packet). The address change unit 26 then changes the address value based on the packet storage flag, prioritizing the younger addresses. In this case, addresses 10Ch~217h in memory 20 are the younger addresses, so the address requested by the MCU 18 is changed to 10Ch~217h. As a result, addresses 10Ch to 217h in memory 20 will output data, and the data will be output to the MCU 18 via the communication processing unit 22. Note that if data arrives on communication path 1 and other communication paths, the address of the lower path is 000h to 10Bh, so no address change is necessary.

[0043] (Second Embodiment) Next, the configuration of the communication IC 16 of the BMS 10 according to the second embodiment will be described. Figure 10 is a block diagram showing the configuration of the communication IC 16 of the BMS 10 according to this embodiment.

[0044] In the first embodiment, the packet storage flag was output as an external terminal, but in this embodiment, the memory state is stored in a register or the like, and the MCU18 monitors the memory state by reading it using a polling method.

[0045] In other words, as shown in Figure 10, instead of the OR circuit 24, a status register 30 is provided in the memory area, and data storage information (packet storage flag or packet storage information) from each address of the memory 20 (000h to 10Bh, 10Ch to 217h, 218h to 322h) is stored in the status register 30.

[0046] Furthermore, similar to the first embodiment, packet storage flags or packet storage information from the addresses (000h to 10Bh, 10Ch to 217h, 218h to 322h) of the memory 20 are input to the address change unit 26.

[0047] Next, the input / output methods for received data of the communication IC 16 of the BMS 10 according to this embodiment will be explained with reference to Figures 11 to 13. Figure 11 is a diagram illustrating the input / output method for received data of the communication IC 16 of the BMS 10 according to this embodiment (when packet data is input). Figure 12 is a diagram illustrating the input / output method for received data of the communication IC 16 of the BMS 10 according to this embodiment (when a memory read request is made). Figure 13 is a diagram illustrating the input / output method for received data of the communication IC 16 of the BMS 10 according to this embodiment (when memory data is output). Figures 11 to 13 show the exchange between the MCUs 18 when data arrives on the communication path 2.

[0048] (1) As shown in Figure 11, packet data from communication path 2 is received. The data from communication path 2 is stored in memory addresses 10Ch~217h. (2) As shown in Figure 11, the MCU 18 periodically reads the status register (memory storage status) 30 of the communication IC 16 to check data storage. The memory 20 also detects the storage of addresses 10Ch to 217h and outputs the memory storage information to the status register 30 and the address change unit 26. (3) As shown in Figure 12, the MCU18 detects the memory storage information (memory storage status) in the status register and issues a read request for addresses 000h to 10Bh. (4) As shown in Figure 12, the address change unit 26 changes the address value from the MCU 18 based on the stored information in memory. In the example in Figure 12, addresses 000h to 10Bh are changed to 10Ch to 217h. If packet data is received at multiple memory addresses simultaneously, the memory address with the smaller value is given priority. (5) As shown in Figure 13, addresses 10Ch to 217h of memory 20 output data and output the data to MCU 18 via the communication processing unit 22. Thus, even if a status register 30 is provided instead of the OR circuit 24 and the MCU 18 polls the memory state, the number of external terminals can be reduced and the load on the microcontroller can be reduced, similar to the first embodiment.

[0049] In the embodiments described above, the memory 20 was configured to allow reading only a portion of the data within a packet by assigning addresses in units of 1 or 2 bytes, such as 000ch to 10Bh, to each address (000h to 10Bh, 10Ch to 217h, 218h to 322h). However, it is also possible to assign one address to each address (000h to 10Bh, 10Ch to 217h, 218h to 322h) of the memory 20, and to output a fixed amount of data (for example, one packet) from the memory when a memory read command is received.

[0050] Furthermore, in each of the embodiments described above, a packet storage flag was output in units of packets as an example of a predetermined communication unit, but a fixed amount of data storage flag may be output instead of packets.

[0051] Furthermore, the above embodiments are merely illustrative, and any modifications or improvements may be applied.

[0052] Furthermore, one or more elements included in one of the above multiple embodiments can be combined with one or more elements included in other embodiments of the above multiple embodiments.

[0053] The following additional information is disclosed regarding the embodiments described above.

[0054] (Note 1) Multiple storage units, each assigned to a separate communication path, store data received from the communication path, and have a divided memory address space. An output unit that outputs data storage information indicating that the plurality of storage units have stored the received data, A modification unit that modifies the data request address in response to a data request from a microcontroller that has received the data storage information from the output unit, A communication processing unit that reads the data stored in the storage unit corresponding to the data request address modified by the modification unit and outputs it to the microcontroller. A battery management system including [the following].

[0055] (Note 2) The battery management system described in Appendix 1, wherein the output unit outputs the data storage flags from each of the storage units as data storage information to an external terminal.

[0056] (Note 3) The output section is the battery management system described in Appendix 1, which includes registers readable from the microcontroller.

[0057] (Note 4) The battery management system described in any one of the appendices 1 to 3, wherein the plurality of storage units each have one address and output a predetermined amount of data upon reading.

[0058] (Note 5) The battery management system described in any one of the appendices 1 to 4, wherein the plurality of storage units have multiple addresses and output partial data according to the requested address at the time of reading.

[0059] (Note 6) The output unit is a battery management system according to any one of the appendices 1 to 5, which outputs the data storage information in a predetermined communication unit.

[0060] (Note 7) Multiple storage units, each assigned to a separate memory address space and responsible for storing data received from the communication path, output data storage information indicating that the data received has been stored. In response to a data request from the microcontroller that received the aforementioned data storage information, the data request address modification unit modifies the data request address. A communication method for a battery management system that reads data stored in the storage unit corresponding to the data request address modified by the modification unit and outputs it to the microcontroller. [Explanation of symbols]

[0061] 10. Battery Management System 16 Communication IC 20 memory 22 Communication Processing Unit 24 OR circuits 26 Address Change Section 30 Status Registers

Claims

1. Multiple storage units, each assigned to a separate communication path, store data received from the communication path, and have a divided memory address space. An output unit that outputs data storage information indicating that the plurality of storage units have stored the received data, A modification unit that modifies the data request address in response to a data request from a microcontroller that has received the data storage information from the output unit, A communication processing unit that reads the data stored in the storage unit corresponding to the data request address modified by the modification unit and outputs it to the microcontroller, A battery management system including [this].

2. The battery management system according to claim 1, wherein the output unit outputs data storage flags from each of the storage units as data storage information to an external terminal.

3. The battery management system according to claim 1, wherein the output unit includes a register readable from the microcontroller.

4. The battery management system according to claim 1, wherein the plurality of storage units each have one address and output a predetermined amount of data upon reading.

5. The battery management system according to claim 1, wherein the plurality of storage units have multiple addresses and output partial data according to the requested address at the time of reading.

6. The battery management system according to claim 1, wherein the output unit outputs the data storage information in a predetermined communication unit.

7. Multiple storage units, each assigned to a separate memory address space and responsible for storing data received from the communication path, output data storage information indicating that the data received has been stored. In response to a data request from the microcontroller that received the aforementioned data storage information, the data request address modification unit modifies the data request address. A communication method for a battery management system that reads data stored in the storage unit corresponding to the data request address modified by the modification unit and outputs it to the microcontroller.

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